[ALSA] hda-intel - Add barrier
[linux-2.6.git] / sound / pci / hda / hda_intel.c
1 /*
2  *
3  *  hda_intel.c - Implementation of primary alsa driver code base
4  *                for Intel HD Audio.
5  *
6  *  Copyright(c) 2004 Intel Corporation. All rights reserved.
7  *
8  *  Copyright (c) 2004 Takashi Iwai <tiwai@suse.de>
9  *                     PeiSen Hou <pshou@realtek.com.tw>
10  *
11  *  This program is free software; you can redistribute it and/or modify it
12  *  under the terms of the GNU General Public License as published by the Free
13  *  Software Foundation; either version 2 of the License, or (at your option)
14  *  any later version.
15  *
16  *  This program is distributed in the hope that it will be useful, but WITHOUT
17  *  ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
18  *  FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
19  *  more details.
20  *
21  *  You should have received a copy of the GNU General Public License along with
22  *  this program; if not, write to the Free Software Foundation, Inc., 59
23  *  Temple Place - Suite 330, Boston, MA  02111-1307, USA.
24  *
25  *  CONTACTS:
26  *
27  *  Matt Jared          matt.jared@intel.com
28  *  Andy Kopp           andy.kopp@intel.com
29  *  Dan Kogan           dan.d.kogan@intel.com
30  *
31  *  CHANGES:
32  *
33  *  2004.12.01  Major rewrite by tiwai, merged the work of pshou
34  * 
35  */
36
37 #include <asm/io.h>
38 #include <linux/delay.h>
39 #include <linux/interrupt.h>
40 #include <linux/kernel.h>
41 #include <linux/module.h>
42 #include <linux/dma-mapping.h>
43 #include <linux/moduleparam.h>
44 #include <linux/init.h>
45 #include <linux/slab.h>
46 #include <linux/pci.h>
47 #include <linux/mutex.h>
48 #include <sound/core.h>
49 #include <sound/initval.h>
50 #include "hda_codec.h"
51
52
53 static int index[SNDRV_CARDS] = SNDRV_DEFAULT_IDX;
54 static char *id[SNDRV_CARDS] = SNDRV_DEFAULT_STR;
55 static int enable[SNDRV_CARDS] = SNDRV_DEFAULT_ENABLE_PNP;
56 static char *model[SNDRV_CARDS];
57 static int position_fix[SNDRV_CARDS];
58 static int probe_mask[SNDRV_CARDS] = {[0 ... (SNDRV_CARDS-1)] = -1};
59 static int single_cmd;
60 static int enable_msi;
61
62 module_param_array(index, int, NULL, 0444);
63 MODULE_PARM_DESC(index, "Index value for Intel HD audio interface.");
64 module_param_array(id, charp, NULL, 0444);
65 MODULE_PARM_DESC(id, "ID string for Intel HD audio interface.");
66 module_param_array(enable, bool, NULL, 0444);
67 MODULE_PARM_DESC(enable, "Enable Intel HD audio interface.");
68 module_param_array(model, charp, NULL, 0444);
69 MODULE_PARM_DESC(model, "Use the given board model.");
70 module_param_array(position_fix, int, NULL, 0444);
71 MODULE_PARM_DESC(position_fix, "Fix DMA pointer "
72                  "(0 = auto, 1 = none, 2 = POSBUF, 3 = FIFO size).");
73 module_param_array(probe_mask, int, NULL, 0444);
74 MODULE_PARM_DESC(probe_mask, "Bitmask to probe codecs (default = -1).");
75 module_param(single_cmd, bool, 0444);
76 MODULE_PARM_DESC(single_cmd, "Use single command to communicate with codecs "
77                  "(for debugging only).");
78 module_param(enable_msi, int, 0444);
79 MODULE_PARM_DESC(enable_msi, "Enable Message Signaled Interrupt (MSI)");
80
81 #ifdef CONFIG_SND_HDA_POWER_SAVE
82 /* power_save option is defined in hda_codec.c */
83
84 /* reset the HD-audio controller in power save mode.
85  * this may give more power-saving, but will take longer time to
86  * wake up.
87  */
88 static int power_save_controller = 1;
89 module_param(power_save_controller, bool, 0644);
90 MODULE_PARM_DESC(power_save_controller, "Reset controller in power save mode.");
91 #endif
92
93 MODULE_LICENSE("GPL");
94 MODULE_SUPPORTED_DEVICE("{{Intel, ICH6},"
95                          "{Intel, ICH6M},"
96                          "{Intel, ICH7},"
97                          "{Intel, ESB2},"
98                          "{Intel, ICH8},"
99                          "{Intel, ICH9},"
100                          "{Intel, ICH10},"
101                          "{Intel, SCH},"
102                          "{ATI, SB450},"
103                          "{ATI, SB600},"
104                          "{ATI, RS600},"
105                          "{ATI, RS690},"
106                          "{ATI, RS780},"
107                          "{ATI, R600},"
108                          "{ATI, RV630},"
109                          "{ATI, RV610},"
110                          "{ATI, RV670},"
111                          "{ATI, RV635},"
112                          "{ATI, RV620},"
113                          "{ATI, RV770},"
114                          "{VIA, VT8251},"
115                          "{VIA, VT8237A},"
116                          "{SiS, SIS966},"
117                          "{ULI, M5461}}");
118 MODULE_DESCRIPTION("Intel HDA driver");
119
120 #define SFX     "hda-intel: "
121
122
123 /*
124  * registers
125  */
126 #define ICH6_REG_GCAP                   0x00
127 #define ICH6_REG_VMIN                   0x02
128 #define ICH6_REG_VMAJ                   0x03
129 #define ICH6_REG_OUTPAY                 0x04
130 #define ICH6_REG_INPAY                  0x06
131 #define ICH6_REG_GCTL                   0x08
132 #define ICH6_REG_WAKEEN                 0x0c
133 #define ICH6_REG_STATESTS               0x0e
134 #define ICH6_REG_GSTS                   0x10
135 #define ICH6_REG_INTCTL                 0x20
136 #define ICH6_REG_INTSTS                 0x24
137 #define ICH6_REG_WALCLK                 0x30
138 #define ICH6_REG_SYNC                   0x34    
139 #define ICH6_REG_CORBLBASE              0x40
140 #define ICH6_REG_CORBUBASE              0x44
141 #define ICH6_REG_CORBWP                 0x48
142 #define ICH6_REG_CORBRP                 0x4A
143 #define ICH6_REG_CORBCTL                0x4c
144 #define ICH6_REG_CORBSTS                0x4d
145 #define ICH6_REG_CORBSIZE               0x4e
146
147 #define ICH6_REG_RIRBLBASE              0x50
148 #define ICH6_REG_RIRBUBASE              0x54
149 #define ICH6_REG_RIRBWP                 0x58
150 #define ICH6_REG_RINTCNT                0x5a
151 #define ICH6_REG_RIRBCTL                0x5c
152 #define ICH6_REG_RIRBSTS                0x5d
153 #define ICH6_REG_RIRBSIZE               0x5e
154
155 #define ICH6_REG_IC                     0x60
156 #define ICH6_REG_IR                     0x64
157 #define ICH6_REG_IRS                    0x68
158 #define   ICH6_IRS_VALID        (1<<1)
159 #define   ICH6_IRS_BUSY         (1<<0)
160
161 #define ICH6_REG_DPLBASE                0x70
162 #define ICH6_REG_DPUBASE                0x74
163 #define   ICH6_DPLBASE_ENABLE   0x1     /* Enable position buffer */
164
165 /* SD offset: SDI0=0x80, SDI1=0xa0, ... SDO3=0x160 */
166 enum { SDI0, SDI1, SDI2, SDI3, SDO0, SDO1, SDO2, SDO3 };
167
168 /* stream register offsets from stream base */
169 #define ICH6_REG_SD_CTL                 0x00
170 #define ICH6_REG_SD_STS                 0x03
171 #define ICH6_REG_SD_LPIB                0x04
172 #define ICH6_REG_SD_CBL                 0x08
173 #define ICH6_REG_SD_LVI                 0x0c
174 #define ICH6_REG_SD_FIFOW               0x0e
175 #define ICH6_REG_SD_FIFOSIZE            0x10
176 #define ICH6_REG_SD_FORMAT              0x12
177 #define ICH6_REG_SD_BDLPL               0x18
178 #define ICH6_REG_SD_BDLPU               0x1c
179
180 /* PCI space */
181 #define ICH6_PCIREG_TCSEL       0x44
182
183 /*
184  * other constants
185  */
186
187 /* max number of SDs */
188 /* ICH, ATI and VIA have 4 playback and 4 capture */
189 #define ICH6_NUM_CAPTURE        4
190 #define ICH6_NUM_PLAYBACK       4
191
192 /* ULI has 6 playback and 5 capture */
193 #define ULI_NUM_CAPTURE         5
194 #define ULI_NUM_PLAYBACK        6
195
196 /* ATI HDMI has 1 playback and 0 capture */
197 #define ATIHDMI_NUM_CAPTURE     0
198 #define ATIHDMI_NUM_PLAYBACK    1
199
200 /* this number is statically defined for simplicity */
201 #define MAX_AZX_DEV             16
202
203 /* max number of fragments - we may use more if allocating more pages for BDL */
204 #define BDL_SIZE                4096
205 #define AZX_MAX_BDL_ENTRIES     (BDL_SIZE / 16)
206 #define AZX_MAX_FRAG            32
207 /* max buffer size - no h/w limit, you can increase as you like */
208 #define AZX_MAX_BUF_SIZE        (1024*1024*1024)
209 /* max number of PCM devics per card */
210 #define AZX_MAX_PCMS            8
211
212 /* RIRB int mask: overrun[2], response[0] */
213 #define RIRB_INT_RESPONSE       0x01
214 #define RIRB_INT_OVERRUN        0x04
215 #define RIRB_INT_MASK           0x05
216
217 /* STATESTS int mask: SD2,SD1,SD0 */
218 #define AZX_MAX_CODECS          3
219 #define STATESTS_INT_MASK       0x07
220
221 /* SD_CTL bits */
222 #define SD_CTL_STREAM_RESET     0x01    /* stream reset bit */
223 #define SD_CTL_DMA_START        0x02    /* stream DMA start bit */
224 #define SD_CTL_STREAM_TAG_MASK  (0xf << 20)
225 #define SD_CTL_STREAM_TAG_SHIFT 20
226
227 /* SD_CTL and SD_STS */
228 #define SD_INT_DESC_ERR         0x10    /* descriptor error interrupt */
229 #define SD_INT_FIFO_ERR         0x08    /* FIFO error interrupt */
230 #define SD_INT_COMPLETE         0x04    /* completion interrupt */
231 #define SD_INT_MASK             (SD_INT_DESC_ERR|SD_INT_FIFO_ERR|\
232                                  SD_INT_COMPLETE)
233
234 /* SD_STS */
235 #define SD_STS_FIFO_READY       0x20    /* FIFO ready */
236
237 /* INTCTL and INTSTS */
238 #define ICH6_INT_ALL_STREAM     0xff       /* all stream interrupts */
239 #define ICH6_INT_CTRL_EN        0x40000000 /* controller interrupt enable bit */
240 #define ICH6_INT_GLOBAL_EN      0x80000000 /* global interrupt enable bit */
241
242 /* GCTL unsolicited response enable bit */
243 #define ICH6_GCTL_UREN          (1<<8)
244
245 /* GCTL reset bit */
246 #define ICH6_GCTL_RESET         (1<<0)
247
248 /* CORB/RIRB control, read/write pointer */
249 #define ICH6_RBCTL_DMA_EN       0x02    /* enable DMA */
250 #define ICH6_RBCTL_IRQ_EN       0x01    /* enable IRQ */
251 #define ICH6_RBRWP_CLR          0x8000  /* read/write pointer clear */
252 /* below are so far hardcoded - should read registers in future */
253 #define ICH6_MAX_CORB_ENTRIES   256
254 #define ICH6_MAX_RIRB_ENTRIES   256
255
256 /* position fix mode */
257 enum {
258         POS_FIX_AUTO,
259         POS_FIX_NONE,
260         POS_FIX_POSBUF,
261         POS_FIX_FIFO,
262 };
263
264 /* Defines for ATI HD Audio support in SB450 south bridge */
265 #define ATI_SB450_HDAUDIO_MISC_CNTR2_ADDR   0x42
266 #define ATI_SB450_HDAUDIO_ENABLE_SNOOP      0x02
267
268 /* Defines for Nvidia HDA support */
269 #define NVIDIA_HDA_TRANSREG_ADDR      0x4e
270 #define NVIDIA_HDA_ENABLE_COHBITS     0x0f
271
272 /* Defines for Intel SCH HDA snoop control */
273 #define INTEL_SCH_HDA_DEVC      0x78
274 #define INTEL_SCH_HDA_DEVC_NOSNOOP       (0x1<<11)
275
276
277 /*
278  */
279
280 struct azx_dev {
281         struct snd_dma_buffer bdl; /* BDL buffer */
282         u32 *posbuf;            /* position buffer pointer */
283
284         unsigned int bufsize;   /* size of the play buffer in bytes */
285         unsigned int frags;     /* number for period in the play buffer */
286         unsigned int fifo_size; /* FIFO size */
287
288         void __iomem *sd_addr;  /* stream descriptor pointer */
289
290         u32 sd_int_sta_mask;    /* stream int status mask */
291
292         /* pcm support */
293         struct snd_pcm_substream *substream;    /* assigned substream,
294                                                  * set in PCM open
295                                                  */
296         unsigned int format_val;        /* format value to be set in the
297                                          * controller and the codec
298                                          */
299         unsigned char stream_tag;       /* assigned stream */
300         unsigned char index;            /* stream index */
301         /* for sanity check of position buffer */
302         unsigned int period_intr;
303
304         unsigned int opened :1;
305         unsigned int running :1;
306 };
307
308 /* CORB/RIRB */
309 struct azx_rb {
310         u32 *buf;               /* CORB/RIRB buffer
311                                  * Each CORB entry is 4byte, RIRB is 8byte
312                                  */
313         dma_addr_t addr;        /* physical address of CORB/RIRB buffer */
314         /* for RIRB */
315         unsigned short rp, wp;  /* read/write pointers */
316         int cmds;               /* number of pending requests */
317         u32 res;                /* last read value */
318 };
319
320 struct azx {
321         struct snd_card *card;
322         struct pci_dev *pci;
323
324         /* chip type specific */
325         int driver_type;
326         int playback_streams;
327         int playback_index_offset;
328         int capture_streams;
329         int capture_index_offset;
330         int num_streams;
331
332         /* pci resources */
333         unsigned long addr;
334         void __iomem *remap_addr;
335         int irq;
336
337         /* locks */
338         spinlock_t reg_lock;
339         struct mutex open_mutex;
340
341         /* streams (x num_streams) */
342         struct azx_dev *azx_dev;
343
344         /* PCM */
345         struct snd_pcm *pcm[AZX_MAX_PCMS];
346
347         /* HD codec */
348         unsigned short codec_mask;
349         struct hda_bus *bus;
350
351         /* CORB/RIRB */
352         struct azx_rb corb;
353         struct azx_rb rirb;
354
355         /* CORB/RIRB and position buffers */
356         struct snd_dma_buffer rb;
357         struct snd_dma_buffer posbuf;
358
359         /* flags */
360         int position_fix;
361         unsigned int running :1;
362         unsigned int initialized :1;
363         unsigned int single_cmd :1;
364         unsigned int polling_mode :1;
365         unsigned int msi :1;
366
367         /* for debugging */
368         unsigned int last_cmd;  /* last issued command (to sync) */
369 };
370
371 /* driver types */
372 enum {
373         AZX_DRIVER_ICH,
374         AZX_DRIVER_SCH,
375         AZX_DRIVER_ATI,
376         AZX_DRIVER_ATIHDMI,
377         AZX_DRIVER_VIA,
378         AZX_DRIVER_SIS,
379         AZX_DRIVER_ULI,
380         AZX_DRIVER_NVIDIA,
381 };
382
383 static char *driver_short_names[] __devinitdata = {
384         [AZX_DRIVER_ICH] = "HDA Intel",
385         [AZX_DRIVER_SCH] = "HDA Intel MID",
386         [AZX_DRIVER_ATI] = "HDA ATI SB",
387         [AZX_DRIVER_ATIHDMI] = "HDA ATI HDMI",
388         [AZX_DRIVER_VIA] = "HDA VIA VT82xx",
389         [AZX_DRIVER_SIS] = "HDA SIS966",
390         [AZX_DRIVER_ULI] = "HDA ULI M5461",
391         [AZX_DRIVER_NVIDIA] = "HDA NVidia",
392 };
393
394 /*
395  * macros for easy use
396  */
397 #define azx_writel(chip,reg,value) \
398         writel(value, (chip)->remap_addr + ICH6_REG_##reg)
399 #define azx_readl(chip,reg) \
400         readl((chip)->remap_addr + ICH6_REG_##reg)
401 #define azx_writew(chip,reg,value) \
402         writew(value, (chip)->remap_addr + ICH6_REG_##reg)
403 #define azx_readw(chip,reg) \
404         readw((chip)->remap_addr + ICH6_REG_##reg)
405 #define azx_writeb(chip,reg,value) \
406         writeb(value, (chip)->remap_addr + ICH6_REG_##reg)
407 #define azx_readb(chip,reg) \
408         readb((chip)->remap_addr + ICH6_REG_##reg)
409
410 #define azx_sd_writel(dev,reg,value) \
411         writel(value, (dev)->sd_addr + ICH6_REG_##reg)
412 #define azx_sd_readl(dev,reg) \
413         readl((dev)->sd_addr + ICH6_REG_##reg)
414 #define azx_sd_writew(dev,reg,value) \
415         writew(value, (dev)->sd_addr + ICH6_REG_##reg)
416 #define azx_sd_readw(dev,reg) \
417         readw((dev)->sd_addr + ICH6_REG_##reg)
418 #define azx_sd_writeb(dev,reg,value) \
419         writeb(value, (dev)->sd_addr + ICH6_REG_##reg)
420 #define azx_sd_readb(dev,reg) \
421         readb((dev)->sd_addr + ICH6_REG_##reg)
422
423 /* for pcm support */
424 #define get_azx_dev(substream) (substream->runtime->private_data)
425
426 /* Get the upper 32bit of the given dma_addr_t
427  * Compiler should optimize and eliminate the code if dma_addr_t is 32bit
428  */
429 #define upper_32bit(addr) (sizeof(addr) > 4 ? (u32)((addr) >> 32) : (u32)0)
430
431 static int azx_acquire_irq(struct azx *chip, int do_disconnect);
432
433 /*
434  * Interface for HD codec
435  */
436
437 /*
438  * CORB / RIRB interface
439  */
440 static int azx_alloc_cmd_io(struct azx *chip)
441 {
442         int err;
443
444         /* single page (at least 4096 bytes) must suffice for both ringbuffes */
445         err = snd_dma_alloc_pages(SNDRV_DMA_TYPE_DEV,
446                                   snd_dma_pci_data(chip->pci),
447                                   PAGE_SIZE, &chip->rb);
448         if (err < 0) {
449                 snd_printk(KERN_ERR SFX "cannot allocate CORB/RIRB\n");
450                 return err;
451         }
452         return 0;
453 }
454
455 static void azx_init_cmd_io(struct azx *chip)
456 {
457         /* CORB set up */
458         chip->corb.addr = chip->rb.addr;
459         chip->corb.buf = (u32 *)chip->rb.area;
460         azx_writel(chip, CORBLBASE, (u32)chip->corb.addr);
461         azx_writel(chip, CORBUBASE, upper_32bit(chip->corb.addr));
462
463         /* set the corb size to 256 entries (ULI requires explicitly) */
464         azx_writeb(chip, CORBSIZE, 0x02);
465         /* set the corb write pointer to 0 */
466         azx_writew(chip, CORBWP, 0);
467         /* reset the corb hw read pointer */
468         azx_writew(chip, CORBRP, ICH6_RBRWP_CLR);
469         /* enable corb dma */
470         azx_writeb(chip, CORBCTL, ICH6_RBCTL_DMA_EN);
471
472         /* RIRB set up */
473         chip->rirb.addr = chip->rb.addr + 2048;
474         chip->rirb.buf = (u32 *)(chip->rb.area + 2048);
475         azx_writel(chip, RIRBLBASE, (u32)chip->rirb.addr);
476         azx_writel(chip, RIRBUBASE, upper_32bit(chip->rirb.addr));
477
478         /* set the rirb size to 256 entries (ULI requires explicitly) */
479         azx_writeb(chip, RIRBSIZE, 0x02);
480         /* reset the rirb hw write pointer */
481         azx_writew(chip, RIRBWP, ICH6_RBRWP_CLR);
482         /* set N=1, get RIRB response interrupt for new entry */
483         azx_writew(chip, RINTCNT, 1);
484         /* enable rirb dma and response irq */
485         azx_writeb(chip, RIRBCTL, ICH6_RBCTL_DMA_EN | ICH6_RBCTL_IRQ_EN);
486         chip->rirb.rp = chip->rirb.cmds = 0;
487 }
488
489 static void azx_free_cmd_io(struct azx *chip)
490 {
491         /* disable ringbuffer DMAs */
492         azx_writeb(chip, RIRBCTL, 0);
493         azx_writeb(chip, CORBCTL, 0);
494 }
495
496 /* send a command */
497 static int azx_corb_send_cmd(struct hda_codec *codec, u32 val)
498 {
499         struct azx *chip = codec->bus->private_data;
500         unsigned int wp;
501
502         /* add command to corb */
503         wp = azx_readb(chip, CORBWP);
504         wp++;
505         wp %= ICH6_MAX_CORB_ENTRIES;
506
507         spin_lock_irq(&chip->reg_lock);
508         chip->rirb.cmds++;
509         chip->corb.buf[wp] = cpu_to_le32(val);
510         azx_writel(chip, CORBWP, wp);
511         spin_unlock_irq(&chip->reg_lock);
512
513         return 0;
514 }
515
516 #define ICH6_RIRB_EX_UNSOL_EV   (1<<4)
517
518 /* retrieve RIRB entry - called from interrupt handler */
519 static void azx_update_rirb(struct azx *chip)
520 {
521         unsigned int rp, wp;
522         u32 res, res_ex;
523
524         wp = azx_readb(chip, RIRBWP);
525         if (wp == chip->rirb.wp)
526                 return;
527         chip->rirb.wp = wp;
528                 
529         while (chip->rirb.rp != wp) {
530                 chip->rirb.rp++;
531                 chip->rirb.rp %= ICH6_MAX_RIRB_ENTRIES;
532
533                 rp = chip->rirb.rp << 1; /* an RIRB entry is 8-bytes */
534                 res_ex = le32_to_cpu(chip->rirb.buf[rp + 1]);
535                 res = le32_to_cpu(chip->rirb.buf[rp]);
536                 if (res_ex & ICH6_RIRB_EX_UNSOL_EV)
537                         snd_hda_queue_unsol_event(chip->bus, res, res_ex);
538                 else if (chip->rirb.cmds) {
539                         chip->rirb.res = res;
540                         smp_wmb();
541                         chip->rirb.cmds--;
542                 }
543         }
544 }
545
546 /* receive a response */
547 static unsigned int azx_rirb_get_response(struct hda_codec *codec)
548 {
549         struct azx *chip = codec->bus->private_data;
550         unsigned long timeout;
551
552  again:
553         timeout = jiffies + msecs_to_jiffies(1000);
554         for (;;) {
555                 if (chip->polling_mode) {
556                         spin_lock_irq(&chip->reg_lock);
557                         azx_update_rirb(chip);
558                         spin_unlock_irq(&chip->reg_lock);
559                 }
560                 if (!chip->rirb.cmds) {
561                         smp_rmb();
562                         return chip->rirb.res; /* the last value */
563                 }
564                 if (time_after(jiffies, timeout))
565                         break;
566                 if (codec->bus->needs_damn_long_delay)
567                         msleep(2); /* temporary workaround */
568                 else {
569                         udelay(10);
570                         cond_resched();
571                 }
572         }
573
574         if (chip->msi) {
575                 snd_printk(KERN_WARNING "hda_intel: No response from codec, "
576                            "disabling MSI: last cmd=0x%08x\n", chip->last_cmd);
577                 free_irq(chip->irq, chip);
578                 chip->irq = -1;
579                 pci_disable_msi(chip->pci);
580                 chip->msi = 0;
581                 if (azx_acquire_irq(chip, 1) < 0)
582                         return -1;
583                 goto again;
584         }
585
586         if (!chip->polling_mode) {
587                 snd_printk(KERN_WARNING "hda_intel: azx_get_response timeout, "
588                            "switching to polling mode: last cmd=0x%08x\n",
589                            chip->last_cmd);
590                 chip->polling_mode = 1;
591                 goto again;
592         }
593
594         snd_printk(KERN_ERR "hda_intel: azx_get_response timeout, "
595                    "switching to single_cmd mode: last cmd=0x%08x\n",
596                    chip->last_cmd);
597         chip->rirb.rp = azx_readb(chip, RIRBWP);
598         chip->rirb.cmds = 0;
599         /* switch to single_cmd mode */
600         chip->single_cmd = 1;
601         azx_free_cmd_io(chip);
602         return -1;
603 }
604
605 /*
606  * Use the single immediate command instead of CORB/RIRB for simplicity
607  *
608  * Note: according to Intel, this is not preferred use.  The command was
609  *       intended for the BIOS only, and may get confused with unsolicited
610  *       responses.  So, we shouldn't use it for normal operation from the
611  *       driver.
612  *       I left the codes, however, for debugging/testing purposes.
613  */
614
615 /* send a command */
616 static int azx_single_send_cmd(struct hda_codec *codec, u32 val)
617 {
618         struct azx *chip = codec->bus->private_data;
619         int timeout = 50;
620
621         while (timeout--) {
622                 /* check ICB busy bit */
623                 if (!((azx_readw(chip, IRS) & ICH6_IRS_BUSY))) {
624                         /* Clear IRV valid bit */
625                         azx_writew(chip, IRS, azx_readw(chip, IRS) |
626                                    ICH6_IRS_VALID);
627                         azx_writel(chip, IC, val);
628                         azx_writew(chip, IRS, azx_readw(chip, IRS) |
629                                    ICH6_IRS_BUSY);
630                         return 0;
631                 }
632                 udelay(1);
633         }
634         if (printk_ratelimit())
635                 snd_printd(SFX "send_cmd timeout: IRS=0x%x, val=0x%x\n",
636                            azx_readw(chip, IRS), val);
637         return -EIO;
638 }
639
640 /* receive a response */
641 static unsigned int azx_single_get_response(struct hda_codec *codec)
642 {
643         struct azx *chip = codec->bus->private_data;
644         int timeout = 50;
645
646         while (timeout--) {
647                 /* check IRV busy bit */
648                 if (azx_readw(chip, IRS) & ICH6_IRS_VALID)
649                         return azx_readl(chip, IR);
650                 udelay(1);
651         }
652         if (printk_ratelimit())
653                 snd_printd(SFX "get_response timeout: IRS=0x%x\n",
654                            azx_readw(chip, IRS));
655         return (unsigned int)-1;
656 }
657
658 /*
659  * The below are the main callbacks from hda_codec.
660  *
661  * They are just the skeleton to call sub-callbacks according to the
662  * current setting of chip->single_cmd.
663  */
664
665 /* send a command */
666 static int azx_send_cmd(struct hda_codec *codec, hda_nid_t nid,
667                         int direct, unsigned int verb,
668                         unsigned int para)
669 {
670         struct azx *chip = codec->bus->private_data;
671         u32 val;
672
673         val = (u32)(codec->addr & 0x0f) << 28;
674         val |= (u32)direct << 27;
675         val |= (u32)nid << 20;
676         val |= verb << 8;
677         val |= para;
678         chip->last_cmd = val;
679
680         if (chip->single_cmd)
681                 return azx_single_send_cmd(codec, val);
682         else
683                 return azx_corb_send_cmd(codec, val);
684 }
685
686 /* get a response */
687 static unsigned int azx_get_response(struct hda_codec *codec)
688 {
689         struct azx *chip = codec->bus->private_data;
690         if (chip->single_cmd)
691                 return azx_single_get_response(codec);
692         else
693                 return azx_rirb_get_response(codec);
694 }
695
696 #ifdef CONFIG_SND_HDA_POWER_SAVE
697 static void azx_power_notify(struct hda_codec *codec);
698 #endif
699
700 /* reset codec link */
701 static int azx_reset(struct azx *chip)
702 {
703         int count;
704
705         /* clear STATESTS */
706         azx_writeb(chip, STATESTS, STATESTS_INT_MASK);
707
708         /* reset controller */
709         azx_writel(chip, GCTL, azx_readl(chip, GCTL) & ~ICH6_GCTL_RESET);
710
711         count = 50;
712         while (azx_readb(chip, GCTL) && --count)
713                 msleep(1);
714
715         /* delay for >= 100us for codec PLL to settle per spec
716          * Rev 0.9 section 5.5.1
717          */
718         msleep(1);
719
720         /* Bring controller out of reset */
721         azx_writeb(chip, GCTL, azx_readb(chip, GCTL) | ICH6_GCTL_RESET);
722
723         count = 50;
724         while (!azx_readb(chip, GCTL) && --count)
725                 msleep(1);
726
727         /* Brent Chartrand said to wait >= 540us for codecs to initialize */
728         msleep(1);
729
730         /* check to see if controller is ready */
731         if (!azx_readb(chip, GCTL)) {
732                 snd_printd("azx_reset: controller not ready!\n");
733                 return -EBUSY;
734         }
735
736         /* Accept unsolicited responses */
737         azx_writel(chip, GCTL, azx_readl(chip, GCTL) | ICH6_GCTL_UREN);
738
739         /* detect codecs */
740         if (!chip->codec_mask) {
741                 chip->codec_mask = azx_readw(chip, STATESTS);
742                 snd_printdd("codec_mask = 0x%x\n", chip->codec_mask);
743         }
744
745         return 0;
746 }
747
748
749 /*
750  * Lowlevel interface
751  */  
752
753 /* enable interrupts */
754 static void azx_int_enable(struct azx *chip)
755 {
756         /* enable controller CIE and GIE */
757         azx_writel(chip, INTCTL, azx_readl(chip, INTCTL) |
758                    ICH6_INT_CTRL_EN | ICH6_INT_GLOBAL_EN);
759 }
760
761 /* disable interrupts */
762 static void azx_int_disable(struct azx *chip)
763 {
764         int i;
765
766         /* disable interrupts in stream descriptor */
767         for (i = 0; i < chip->num_streams; i++) {
768                 struct azx_dev *azx_dev = &chip->azx_dev[i];
769                 azx_sd_writeb(azx_dev, SD_CTL,
770                               azx_sd_readb(azx_dev, SD_CTL) & ~SD_INT_MASK);
771         }
772
773         /* disable SIE for all streams */
774         azx_writeb(chip, INTCTL, 0);
775
776         /* disable controller CIE and GIE */
777         azx_writel(chip, INTCTL, azx_readl(chip, INTCTL) &
778                    ~(ICH6_INT_CTRL_EN | ICH6_INT_GLOBAL_EN));
779 }
780
781 /* clear interrupts */
782 static void azx_int_clear(struct azx *chip)
783 {
784         int i;
785
786         /* clear stream status */
787         for (i = 0; i < chip->num_streams; i++) {
788                 struct azx_dev *azx_dev = &chip->azx_dev[i];
789                 azx_sd_writeb(azx_dev, SD_STS, SD_INT_MASK);
790         }
791
792         /* clear STATESTS */
793         azx_writeb(chip, STATESTS, STATESTS_INT_MASK);
794
795         /* clear rirb status */
796         azx_writeb(chip, RIRBSTS, RIRB_INT_MASK);
797
798         /* clear int status */
799         azx_writel(chip, INTSTS, ICH6_INT_CTRL_EN | ICH6_INT_ALL_STREAM);
800 }
801
802 /* start a stream */
803 static void azx_stream_start(struct azx *chip, struct azx_dev *azx_dev)
804 {
805         /* enable SIE */
806         azx_writeb(chip, INTCTL,
807                    azx_readb(chip, INTCTL) | (1 << azx_dev->index));
808         /* set DMA start and interrupt mask */
809         azx_sd_writeb(azx_dev, SD_CTL, azx_sd_readb(azx_dev, SD_CTL) |
810                       SD_CTL_DMA_START | SD_INT_MASK);
811 }
812
813 /* stop a stream */
814 static void azx_stream_stop(struct azx *chip, struct azx_dev *azx_dev)
815 {
816         /* stop DMA */
817         azx_sd_writeb(azx_dev, SD_CTL, azx_sd_readb(azx_dev, SD_CTL) &
818                       ~(SD_CTL_DMA_START | SD_INT_MASK));
819         azx_sd_writeb(azx_dev, SD_STS, SD_INT_MASK); /* to be sure */
820         /* disable SIE */
821         azx_writeb(chip, INTCTL,
822                    azx_readb(chip, INTCTL) & ~(1 << azx_dev->index));
823 }
824
825
826 /*
827  * reset and start the controller registers
828  */
829 static void azx_init_chip(struct azx *chip)
830 {
831         if (chip->initialized)
832                 return;
833
834         /* reset controller */
835         azx_reset(chip);
836
837         /* initialize interrupts */
838         azx_int_clear(chip);
839         azx_int_enable(chip);
840
841         /* initialize the codec command I/O */
842         if (!chip->single_cmd)
843                 azx_init_cmd_io(chip);
844
845         /* program the position buffer */
846         azx_writel(chip, DPLBASE, (u32)chip->posbuf.addr);
847         azx_writel(chip, DPUBASE, upper_32bit(chip->posbuf.addr));
848
849         chip->initialized = 1;
850 }
851
852 /*
853  * initialize the PCI registers
854  */
855 /* update bits in a PCI register byte */
856 static void update_pci_byte(struct pci_dev *pci, unsigned int reg,
857                             unsigned char mask, unsigned char val)
858 {
859         unsigned char data;
860
861         pci_read_config_byte(pci, reg, &data);
862         data &= ~mask;
863         data |= (val & mask);
864         pci_write_config_byte(pci, reg, data);
865 }
866
867 static void azx_init_pci(struct azx *chip)
868 {
869         unsigned short snoop;
870
871         /* Clear bits 0-2 of PCI register TCSEL (at offset 0x44)
872          * TCSEL == Traffic Class Select Register, which sets PCI express QOS
873          * Ensuring these bits are 0 clears playback static on some HD Audio
874          * codecs
875          */
876         update_pci_byte(chip->pci, ICH6_PCIREG_TCSEL, 0x07, 0);
877
878         switch (chip->driver_type) {
879         case AZX_DRIVER_ATI:
880                 /* For ATI SB450 azalia HD audio, we need to enable snoop */
881                 update_pci_byte(chip->pci,
882                                 ATI_SB450_HDAUDIO_MISC_CNTR2_ADDR, 
883                                 0x07, ATI_SB450_HDAUDIO_ENABLE_SNOOP);
884                 break;
885         case AZX_DRIVER_NVIDIA:
886                 /* For NVIDIA HDA, enable snoop */
887                 update_pci_byte(chip->pci,
888                                 NVIDIA_HDA_TRANSREG_ADDR,
889                                 0x0f, NVIDIA_HDA_ENABLE_COHBITS);
890                 break;
891         case AZX_DRIVER_SCH:
892                 pci_read_config_word(chip->pci, INTEL_SCH_HDA_DEVC, &snoop);
893                 if (snoop & INTEL_SCH_HDA_DEVC_NOSNOOP) {
894                         pci_write_config_word(chip->pci, INTEL_SCH_HDA_DEVC, \
895                                 snoop & (~INTEL_SCH_HDA_DEVC_NOSNOOP));
896                         pci_read_config_word(chip->pci,
897                                 INTEL_SCH_HDA_DEVC, &snoop);
898                         snd_printdd("HDA snoop disabled, enabling ... %s\n",\
899                                 (snoop & INTEL_SCH_HDA_DEVC_NOSNOOP) \
900                                 ? "Failed" : "OK");
901                 }
902                 break;
903
904         }
905 }
906
907
908 /*
909  * interrupt handler
910  */
911 static irqreturn_t azx_interrupt(int irq, void *dev_id)
912 {
913         struct azx *chip = dev_id;
914         struct azx_dev *azx_dev;
915         u32 status;
916         int i;
917
918         spin_lock(&chip->reg_lock);
919
920         status = azx_readl(chip, INTSTS);
921         if (status == 0) {
922                 spin_unlock(&chip->reg_lock);
923                 return IRQ_NONE;
924         }
925         
926         for (i = 0; i < chip->num_streams; i++) {
927                 azx_dev = &chip->azx_dev[i];
928                 if (status & azx_dev->sd_int_sta_mask) {
929                         azx_sd_writeb(azx_dev, SD_STS, SD_INT_MASK);
930                         if (azx_dev->substream && azx_dev->running) {
931                                 azx_dev->period_intr++;
932                                 spin_unlock(&chip->reg_lock);
933                                 snd_pcm_period_elapsed(azx_dev->substream);
934                                 spin_lock(&chip->reg_lock);
935                         }
936                 }
937         }
938
939         /* clear rirb int */
940         status = azx_readb(chip, RIRBSTS);
941         if (status & RIRB_INT_MASK) {
942                 if (!chip->single_cmd && (status & RIRB_INT_RESPONSE))
943                         azx_update_rirb(chip);
944                 azx_writeb(chip, RIRBSTS, RIRB_INT_MASK);
945         }
946
947 #if 0
948         /* clear state status int */
949         if (azx_readb(chip, STATESTS) & 0x04)
950                 azx_writeb(chip, STATESTS, 0x04);
951 #endif
952         spin_unlock(&chip->reg_lock);
953         
954         return IRQ_HANDLED;
955 }
956
957
958 /*
959  * set up BDL entries
960  */
961 static int azx_setup_periods(struct snd_pcm_substream *substream,
962                              struct azx_dev *azx_dev)
963 {
964         struct snd_sg_buf *sgbuf = snd_pcm_substream_sgbuf(substream);
965         u32 *bdl;
966         int i, ofs, periods, period_bytes;
967
968         /* reset BDL address */
969         azx_sd_writel(azx_dev, SD_BDLPL, 0);
970         azx_sd_writel(azx_dev, SD_BDLPU, 0);
971
972         period_bytes = snd_pcm_lib_period_bytes(substream);
973         periods = azx_dev->bufsize / period_bytes;
974
975         /* program the initial BDL entries */
976         bdl = (u32 *)azx_dev->bdl.area;
977         ofs = 0;
978         azx_dev->frags = 0;
979         for (i = 0; i < periods; i++) {
980                 int size, rest;
981                 if (i >= AZX_MAX_BDL_ENTRIES) {
982                         snd_printk(KERN_ERR "Too many BDL entries: "
983                                    "buffer=%d, period=%d\n",
984                                    azx_dev->bufsize, period_bytes);
985                         /* reset */
986                         azx_sd_writel(azx_dev, SD_BDLPL, 0);
987                         azx_sd_writel(azx_dev, SD_BDLPU, 0);
988                         return -EINVAL;
989                 }
990                 rest = period_bytes;
991                 do {
992                         dma_addr_t addr = snd_pcm_sgbuf_get_addr(sgbuf, ofs);
993                         /* program the address field of the BDL entry */
994                         bdl[0] = cpu_to_le32((u32)addr);
995                         bdl[1] = cpu_to_le32(upper_32bit(addr));
996                         /* program the size field of the BDL entry */
997                         size = PAGE_SIZE - (ofs % PAGE_SIZE);
998                         if (rest < size)
999                                 size = rest;
1000                         bdl[2] = cpu_to_le32(size);
1001                         /* program the IOC to enable interrupt
1002                          * only when the whole fragment is processed
1003                          */
1004                         rest -= size;
1005                         bdl[3] = rest ? 0 : cpu_to_le32(0x01);
1006                         bdl += 4;
1007                         azx_dev->frags++;
1008                         ofs += size;
1009                 } while (rest > 0);
1010         }
1011         return 0;
1012 }
1013
1014 /*
1015  * set up the SD for streaming
1016  */
1017 static int azx_setup_controller(struct azx *chip, struct azx_dev *azx_dev)
1018 {
1019         unsigned char val;
1020         int timeout;
1021
1022         /* make sure the run bit is zero for SD */
1023         azx_sd_writeb(azx_dev, SD_CTL, azx_sd_readb(azx_dev, SD_CTL) &
1024                       ~SD_CTL_DMA_START);
1025         /* reset stream */
1026         azx_sd_writeb(azx_dev, SD_CTL, azx_sd_readb(azx_dev, SD_CTL) |
1027                       SD_CTL_STREAM_RESET);
1028         udelay(3);
1029         timeout = 300;
1030         while (!((val = azx_sd_readb(azx_dev, SD_CTL)) & SD_CTL_STREAM_RESET) &&
1031                --timeout)
1032                 ;
1033         val &= ~SD_CTL_STREAM_RESET;
1034         azx_sd_writeb(azx_dev, SD_CTL, val);
1035         udelay(3);
1036
1037         timeout = 300;
1038         /* waiting for hardware to report that the stream is out of reset */
1039         while (((val = azx_sd_readb(azx_dev, SD_CTL)) & SD_CTL_STREAM_RESET) &&
1040                --timeout)
1041                 ;
1042
1043         /* program the stream_tag */
1044         azx_sd_writel(azx_dev, SD_CTL,
1045                       (azx_sd_readl(azx_dev, SD_CTL) & ~SD_CTL_STREAM_TAG_MASK)|
1046                       (azx_dev->stream_tag << SD_CTL_STREAM_TAG_SHIFT));
1047
1048         /* program the length of samples in cyclic buffer */
1049         azx_sd_writel(azx_dev, SD_CBL, azx_dev->bufsize);
1050
1051         /* program the stream format */
1052         /* this value needs to be the same as the one programmed */
1053         azx_sd_writew(azx_dev, SD_FORMAT, azx_dev->format_val);
1054
1055         /* program the stream LVI (last valid index) of the BDL */
1056         azx_sd_writew(azx_dev, SD_LVI, azx_dev->frags - 1);
1057
1058         /* program the BDL address */
1059         /* lower BDL address */
1060         azx_sd_writel(azx_dev, SD_BDLPL, (u32)azx_dev->bdl.addr);
1061         /* upper BDL address */
1062         azx_sd_writel(azx_dev, SD_BDLPU, upper_32bit(azx_dev->bdl.addr));
1063
1064         /* enable the position buffer */
1065         if (chip->position_fix == POS_FIX_POSBUF ||
1066             chip->position_fix == POS_FIX_AUTO) {
1067                 if (!(azx_readl(chip, DPLBASE) & ICH6_DPLBASE_ENABLE))
1068                         azx_writel(chip, DPLBASE,
1069                                 (u32)chip->posbuf.addr | ICH6_DPLBASE_ENABLE);
1070         }
1071
1072         /* set the interrupt enable bits in the descriptor control register */
1073         azx_sd_writel(azx_dev, SD_CTL,
1074                       azx_sd_readl(azx_dev, SD_CTL) | SD_INT_MASK);
1075
1076         return 0;
1077 }
1078
1079
1080 /*
1081  * Codec initialization
1082  */
1083
1084 static unsigned int azx_max_codecs[] __devinitdata = {
1085         [AZX_DRIVER_ICH] = 3,
1086         [AZX_DRIVER_SCH] = 3,
1087         [AZX_DRIVER_ATI] = 4,
1088         [AZX_DRIVER_ATIHDMI] = 4,
1089         [AZX_DRIVER_VIA] = 3,           /* FIXME: correct? */
1090         [AZX_DRIVER_SIS] = 3,           /* FIXME: correct? */
1091         [AZX_DRIVER_ULI] = 3,           /* FIXME: correct? */
1092         [AZX_DRIVER_NVIDIA] = 3,        /* FIXME: correct? */
1093 };
1094
1095 static int __devinit azx_codec_create(struct azx *chip, const char *model,
1096                                       unsigned int codec_probe_mask)
1097 {
1098         struct hda_bus_template bus_temp;
1099         int c, codecs, audio_codecs, err;
1100
1101         memset(&bus_temp, 0, sizeof(bus_temp));
1102         bus_temp.private_data = chip;
1103         bus_temp.modelname = model;
1104         bus_temp.pci = chip->pci;
1105         bus_temp.ops.command = azx_send_cmd;
1106         bus_temp.ops.get_response = azx_get_response;
1107 #ifdef CONFIG_SND_HDA_POWER_SAVE
1108         bus_temp.ops.pm_notify = azx_power_notify;
1109 #endif
1110
1111         err = snd_hda_bus_new(chip->card, &bus_temp, &chip->bus);
1112         if (err < 0)
1113                 return err;
1114
1115         codecs = audio_codecs = 0;
1116         for (c = 0; c < AZX_MAX_CODECS; c++) {
1117                 if ((chip->codec_mask & (1 << c)) & codec_probe_mask) {
1118                         struct hda_codec *codec;
1119                         err = snd_hda_codec_new(chip->bus, c, &codec);
1120                         if (err < 0)
1121                                 continue;
1122                         codecs++;
1123                         if (codec->afg)
1124                                 audio_codecs++;
1125                 }
1126         }
1127         if (!audio_codecs) {
1128                 /* probe additional slots if no codec is found */
1129                 for (; c < azx_max_codecs[chip->driver_type]; c++) {
1130                         if ((chip->codec_mask & (1 << c)) & codec_probe_mask) {
1131                                 err = snd_hda_codec_new(chip->bus, c, NULL);
1132                                 if (err < 0)
1133                                         continue;
1134                                 codecs++;
1135                         }
1136                 }
1137         }
1138         if (!codecs) {
1139                 snd_printk(KERN_ERR SFX "no codecs initialized\n");
1140                 return -ENXIO;
1141         }
1142
1143         return 0;
1144 }
1145
1146
1147 /*
1148  * PCM support
1149  */
1150
1151 /* assign a stream for the PCM */
1152 static inline struct azx_dev *azx_assign_device(struct azx *chip, int stream)
1153 {
1154         int dev, i, nums;
1155         if (stream == SNDRV_PCM_STREAM_PLAYBACK) {
1156                 dev = chip->playback_index_offset;
1157                 nums = chip->playback_streams;
1158         } else {
1159                 dev = chip->capture_index_offset;
1160                 nums = chip->capture_streams;
1161         }
1162         for (i = 0; i < nums; i++, dev++)
1163                 if (!chip->azx_dev[dev].opened) {
1164                         chip->azx_dev[dev].opened = 1;
1165                         return &chip->azx_dev[dev];
1166                 }
1167         return NULL;
1168 }
1169
1170 /* release the assigned stream */
1171 static inline void azx_release_device(struct azx_dev *azx_dev)
1172 {
1173         azx_dev->opened = 0;
1174 }
1175
1176 static struct snd_pcm_hardware azx_pcm_hw = {
1177         .info =                 (SNDRV_PCM_INFO_MMAP |
1178                                  SNDRV_PCM_INFO_INTERLEAVED |
1179                                  SNDRV_PCM_INFO_BLOCK_TRANSFER |
1180                                  SNDRV_PCM_INFO_MMAP_VALID |
1181                                  /* No full-resume yet implemented */
1182                                  /* SNDRV_PCM_INFO_RESUME |*/
1183                                  SNDRV_PCM_INFO_PAUSE),
1184         .formats =              SNDRV_PCM_FMTBIT_S16_LE,
1185         .rates =                SNDRV_PCM_RATE_48000,
1186         .rate_min =             48000,
1187         .rate_max =             48000,
1188         .channels_min =         2,
1189         .channels_max =         2,
1190         .buffer_bytes_max =     AZX_MAX_BUF_SIZE,
1191         .period_bytes_min =     128,
1192         .period_bytes_max =     AZX_MAX_BUF_SIZE / 2,
1193         .periods_min =          2,
1194         .periods_max =          AZX_MAX_FRAG,
1195         .fifo_size =            0,
1196 };
1197
1198 struct azx_pcm {
1199         struct azx *chip;
1200         struct hda_codec *codec;
1201         struct hda_pcm_stream *hinfo[2];
1202 };
1203
1204 static int azx_pcm_open(struct snd_pcm_substream *substream)
1205 {
1206         struct azx_pcm *apcm = snd_pcm_substream_chip(substream);
1207         struct hda_pcm_stream *hinfo = apcm->hinfo[substream->stream];
1208         struct azx *chip = apcm->chip;
1209         struct azx_dev *azx_dev;
1210         struct snd_pcm_runtime *runtime = substream->runtime;
1211         unsigned long flags;
1212         int err;
1213
1214         mutex_lock(&chip->open_mutex);
1215         azx_dev = azx_assign_device(chip, substream->stream);
1216         if (azx_dev == NULL) {
1217                 mutex_unlock(&chip->open_mutex);
1218                 return -EBUSY;
1219         }
1220         runtime->hw = azx_pcm_hw;
1221         runtime->hw.channels_min = hinfo->channels_min;
1222         runtime->hw.channels_max = hinfo->channels_max;
1223         runtime->hw.formats = hinfo->formats;
1224         runtime->hw.rates = hinfo->rates;
1225         snd_pcm_limit_hw_rates(runtime);
1226         snd_pcm_hw_constraint_integer(runtime, SNDRV_PCM_HW_PARAM_PERIODS);
1227         snd_pcm_hw_constraint_step(runtime, 0, SNDRV_PCM_HW_PARAM_BUFFER_BYTES,
1228                                    128);
1229         snd_pcm_hw_constraint_step(runtime, 0, SNDRV_PCM_HW_PARAM_PERIOD_BYTES,
1230                                    128);
1231         snd_hda_power_up(apcm->codec);
1232         err = hinfo->ops.open(hinfo, apcm->codec, substream);
1233         if (err < 0) {
1234                 azx_release_device(azx_dev);
1235                 snd_hda_power_down(apcm->codec);
1236                 mutex_unlock(&chip->open_mutex);
1237                 return err;
1238         }
1239         spin_lock_irqsave(&chip->reg_lock, flags);
1240         azx_dev->substream = substream;
1241         azx_dev->running = 0;
1242         spin_unlock_irqrestore(&chip->reg_lock, flags);
1243
1244         runtime->private_data = azx_dev;
1245         mutex_unlock(&chip->open_mutex);
1246         return 0;
1247 }
1248
1249 static int azx_pcm_close(struct snd_pcm_substream *substream)
1250 {
1251         struct azx_pcm *apcm = snd_pcm_substream_chip(substream);
1252         struct hda_pcm_stream *hinfo = apcm->hinfo[substream->stream];
1253         struct azx *chip = apcm->chip;
1254         struct azx_dev *azx_dev = get_azx_dev(substream);
1255         unsigned long flags;
1256
1257         mutex_lock(&chip->open_mutex);
1258         spin_lock_irqsave(&chip->reg_lock, flags);
1259         azx_dev->substream = NULL;
1260         azx_dev->running = 0;
1261         spin_unlock_irqrestore(&chip->reg_lock, flags);
1262         azx_release_device(azx_dev);
1263         hinfo->ops.close(hinfo, apcm->codec, substream);
1264         snd_hda_power_down(apcm->codec);
1265         mutex_unlock(&chip->open_mutex);
1266         return 0;
1267 }
1268
1269 static int azx_pcm_hw_params(struct snd_pcm_substream *substream,
1270                              struct snd_pcm_hw_params *hw_params)
1271 {
1272         return snd_pcm_lib_malloc_pages(substream,
1273                                         params_buffer_bytes(hw_params));
1274 }
1275
1276 static int azx_pcm_hw_free(struct snd_pcm_substream *substream)
1277 {
1278         struct azx_pcm *apcm = snd_pcm_substream_chip(substream);
1279         struct azx_dev *azx_dev = get_azx_dev(substream);
1280         struct hda_pcm_stream *hinfo = apcm->hinfo[substream->stream];
1281
1282         /* reset BDL address */
1283         azx_sd_writel(azx_dev, SD_BDLPL, 0);
1284         azx_sd_writel(azx_dev, SD_BDLPU, 0);
1285         azx_sd_writel(azx_dev, SD_CTL, 0);
1286
1287         hinfo->ops.cleanup(hinfo, apcm->codec, substream);
1288
1289         return snd_pcm_lib_free_pages(substream);
1290 }
1291
1292 static int azx_pcm_prepare(struct snd_pcm_substream *substream)
1293 {
1294         struct azx_pcm *apcm = snd_pcm_substream_chip(substream);
1295         struct azx *chip = apcm->chip;
1296         struct azx_dev *azx_dev = get_azx_dev(substream);
1297         struct hda_pcm_stream *hinfo = apcm->hinfo[substream->stream];
1298         struct snd_pcm_runtime *runtime = substream->runtime;
1299
1300         azx_dev->bufsize = snd_pcm_lib_buffer_bytes(substream);
1301         azx_dev->format_val = snd_hda_calc_stream_format(runtime->rate,
1302                                                          runtime->channels,
1303                                                          runtime->format,
1304                                                          hinfo->maxbps);
1305         if (!azx_dev->format_val) {
1306                 snd_printk(KERN_ERR SFX
1307                            "invalid format_val, rate=%d, ch=%d, format=%d\n",
1308                            runtime->rate, runtime->channels, runtime->format);
1309                 return -EINVAL;
1310         }
1311
1312         snd_printdd("azx_pcm_prepare: bufsize=0x%x, format=0x%x\n",
1313                     azx_dev->bufsize, azx_dev->format_val);
1314         if (azx_setup_periods(substream, azx_dev) < 0)
1315                 return -EINVAL;
1316         azx_setup_controller(chip, azx_dev);
1317         if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK)
1318                 azx_dev->fifo_size = azx_sd_readw(azx_dev, SD_FIFOSIZE) + 1;
1319         else
1320                 azx_dev->fifo_size = 0;
1321
1322         return hinfo->ops.prepare(hinfo, apcm->codec, azx_dev->stream_tag,
1323                                   azx_dev->format_val, substream);
1324 }
1325
1326 static int azx_pcm_trigger(struct snd_pcm_substream *substream, int cmd)
1327 {
1328         struct azx_pcm *apcm = snd_pcm_substream_chip(substream);
1329         struct azx_dev *azx_dev = get_azx_dev(substream);
1330         struct azx *chip = apcm->chip;
1331         int err = 0;
1332
1333         spin_lock(&chip->reg_lock);
1334         switch (cmd) {
1335         case SNDRV_PCM_TRIGGER_PAUSE_RELEASE:
1336         case SNDRV_PCM_TRIGGER_RESUME:
1337         case SNDRV_PCM_TRIGGER_START:
1338                 azx_stream_start(chip, azx_dev);
1339                 azx_dev->running = 1;
1340                 break;
1341         case SNDRV_PCM_TRIGGER_PAUSE_PUSH:
1342         case SNDRV_PCM_TRIGGER_SUSPEND:
1343         case SNDRV_PCM_TRIGGER_STOP:
1344                 azx_stream_stop(chip, azx_dev);
1345                 azx_dev->running = 0;
1346                 break;
1347         default:
1348                 err = -EINVAL;
1349         }
1350         spin_unlock(&chip->reg_lock);
1351         if (cmd == SNDRV_PCM_TRIGGER_PAUSE_PUSH ||
1352             cmd == SNDRV_PCM_TRIGGER_SUSPEND ||
1353             cmd == SNDRV_PCM_TRIGGER_STOP) {
1354                 int timeout = 5000;
1355                 while ((azx_sd_readb(azx_dev, SD_CTL) & SD_CTL_DMA_START) &&
1356                        --timeout)
1357                         ;
1358         }
1359         return err;
1360 }
1361
1362 static snd_pcm_uframes_t azx_pcm_pointer(struct snd_pcm_substream *substream)
1363 {
1364         struct azx_pcm *apcm = snd_pcm_substream_chip(substream);
1365         struct azx *chip = apcm->chip;
1366         struct azx_dev *azx_dev = get_azx_dev(substream);
1367         unsigned int pos;
1368
1369         if (chip->position_fix == POS_FIX_POSBUF ||
1370             chip->position_fix == POS_FIX_AUTO) {
1371                 /* use the position buffer */
1372                 pos = le32_to_cpu(*azx_dev->posbuf);
1373                 if (chip->position_fix == POS_FIX_AUTO &&
1374                     azx_dev->period_intr == 1 && !pos) {
1375                         printk(KERN_WARNING
1376                                "hda-intel: Invalid position buffer, "
1377                                "using LPIB read method instead.\n");
1378                         chip->position_fix = POS_FIX_NONE;
1379                         goto read_lpib;
1380                 }
1381         } else {
1382         read_lpib:
1383                 /* read LPIB */
1384                 pos = azx_sd_readl(azx_dev, SD_LPIB);
1385                 if (chip->position_fix == POS_FIX_FIFO)
1386                         pos += azx_dev->fifo_size;
1387         }
1388         if (pos >= azx_dev->bufsize)
1389                 pos = 0;
1390         return bytes_to_frames(substream->runtime, pos);
1391 }
1392
1393 static struct snd_pcm_ops azx_pcm_ops = {
1394         .open = azx_pcm_open,
1395         .close = azx_pcm_close,
1396         .ioctl = snd_pcm_lib_ioctl,
1397         .hw_params = azx_pcm_hw_params,
1398         .hw_free = azx_pcm_hw_free,
1399         .prepare = azx_pcm_prepare,
1400         .trigger = azx_pcm_trigger,
1401         .pointer = azx_pcm_pointer,
1402         .page = snd_pcm_sgbuf_ops_page,
1403 };
1404
1405 static void azx_pcm_free(struct snd_pcm *pcm)
1406 {
1407         kfree(pcm->private_data);
1408 }
1409
1410 static int __devinit create_codec_pcm(struct azx *chip, struct hda_codec *codec,
1411                                       struct hda_pcm *cpcm)
1412 {
1413         int err;
1414         struct snd_pcm *pcm;
1415         struct azx_pcm *apcm;
1416
1417         /* if no substreams are defined for both playback and capture,
1418          * it's just a placeholder.  ignore it.
1419          */
1420         if (!cpcm->stream[0].substreams && !cpcm->stream[1].substreams)
1421                 return 0;
1422
1423         snd_assert(cpcm->name, return -EINVAL);
1424
1425         err = snd_pcm_new(chip->card, cpcm->name, cpcm->device,
1426                           cpcm->stream[0].substreams,
1427                           cpcm->stream[1].substreams,
1428                           &pcm);
1429         if (err < 0)
1430                 return err;
1431         strcpy(pcm->name, cpcm->name);
1432         apcm = kmalloc(sizeof(*apcm), GFP_KERNEL);
1433         if (apcm == NULL)
1434                 return -ENOMEM;
1435         apcm->chip = chip;
1436         apcm->codec = codec;
1437         apcm->hinfo[0] = &cpcm->stream[0];
1438         apcm->hinfo[1] = &cpcm->stream[1];
1439         pcm->private_data = apcm;
1440         pcm->private_free = azx_pcm_free;
1441         if (cpcm->stream[0].substreams)
1442                 snd_pcm_set_ops(pcm, SNDRV_PCM_STREAM_PLAYBACK, &azx_pcm_ops);
1443         if (cpcm->stream[1].substreams)
1444                 snd_pcm_set_ops(pcm, SNDRV_PCM_STREAM_CAPTURE, &azx_pcm_ops);
1445         snd_pcm_lib_preallocate_pages_for_all(pcm, SNDRV_DMA_TYPE_DEV_SG,
1446                                               snd_dma_pci_data(chip->pci),
1447                                               1024 * 64, 1024 * 1024);
1448         chip->pcm[cpcm->device] = pcm;
1449         return 0;
1450 }
1451
1452 static int __devinit azx_pcm_create(struct azx *chip)
1453 {
1454         static const char *dev_name[HDA_PCM_NTYPES] = {
1455                 "Audio", "SPDIF", "HDMI", "Modem"
1456         };
1457         /* starting device index for each PCM type */
1458         static int dev_idx[HDA_PCM_NTYPES] = {
1459                 [HDA_PCM_TYPE_AUDIO] = 0,
1460                 [HDA_PCM_TYPE_SPDIF] = 1,
1461                 [HDA_PCM_TYPE_HDMI] = 3,
1462                 [HDA_PCM_TYPE_MODEM] = 6
1463         };
1464         /* normal audio device indices; not linear to keep compatibility */
1465         static int audio_idx[4] = { 0, 2, 4, 5 };
1466         struct hda_codec *codec;
1467         int c, err;
1468         int num_devs[HDA_PCM_NTYPES];
1469
1470         err = snd_hda_build_pcms(chip->bus);
1471         if (err < 0)
1472                 return err;
1473
1474         /* create audio PCMs */
1475         memset(num_devs, 0, sizeof(num_devs));
1476         list_for_each_entry(codec, &chip->bus->codec_list, list) {
1477                 for (c = 0; c < codec->num_pcms; c++) {
1478                         struct hda_pcm *cpcm = &codec->pcm_info[c];
1479                         int type = cpcm->pcm_type;
1480                         switch (type) {
1481                         case HDA_PCM_TYPE_AUDIO:
1482                                 if (num_devs[type] >= ARRAY_SIZE(audio_idx)) {
1483                                         snd_printk(KERN_WARNING
1484                                                    "Too many audio devices\n");
1485                                         continue;
1486                                 }
1487                                 cpcm->device = audio_idx[num_devs[type]];
1488                                 break;
1489                         case HDA_PCM_TYPE_SPDIF:
1490                         case HDA_PCM_TYPE_HDMI:
1491                         case HDA_PCM_TYPE_MODEM:
1492                                 if (num_devs[type]) {
1493                                         snd_printk(KERN_WARNING
1494                                                    "%s already defined\n",
1495                                                    dev_name[type]);
1496                                         continue;
1497                                 }
1498                                 cpcm->device = dev_idx[type];
1499                                 break;
1500                         default:
1501                                 snd_printk(KERN_WARNING
1502                                            "Invalid PCM type %d\n", type);
1503                                 continue;
1504                         }
1505                         num_devs[type]++;
1506                         err = create_codec_pcm(chip, codec, cpcm);
1507                         if (err < 0)
1508                                 return err;
1509                 }
1510         }
1511         return 0;
1512 }
1513
1514 /*
1515  * mixer creation - all stuff is implemented in hda module
1516  */
1517 static int __devinit azx_mixer_create(struct azx *chip)
1518 {
1519         return snd_hda_build_controls(chip->bus);
1520 }
1521
1522
1523 /*
1524  * initialize SD streams
1525  */
1526 static int __devinit azx_init_stream(struct azx *chip)
1527 {
1528         int i;
1529
1530         /* initialize each stream (aka device)
1531          * assign the starting bdl address to each stream (device)
1532          * and initialize
1533          */
1534         for (i = 0; i < chip->num_streams; i++) {
1535                 struct azx_dev *azx_dev = &chip->azx_dev[i];
1536                 azx_dev->posbuf = (u32 __iomem *)(chip->posbuf.area + i * 8);
1537                 /* offset: SDI0=0x80, SDI1=0xa0, ... SDO3=0x160 */
1538                 azx_dev->sd_addr = chip->remap_addr + (0x20 * i + 0x80);
1539                 /* int mask: SDI0=0x01, SDI1=0x02, ... SDO3=0x80 */
1540                 azx_dev->sd_int_sta_mask = 1 << i;
1541                 /* stream tag: must be non-zero and unique */
1542                 azx_dev->index = i;
1543                 azx_dev->stream_tag = i + 1;
1544         }
1545
1546         return 0;
1547 }
1548
1549 static int azx_acquire_irq(struct azx *chip, int do_disconnect)
1550 {
1551         if (request_irq(chip->pci->irq, azx_interrupt,
1552                         chip->msi ? 0 : IRQF_SHARED,
1553                         "HDA Intel", chip)) {
1554                 printk(KERN_ERR "hda-intel: unable to grab IRQ %d, "
1555                        "disabling device\n", chip->pci->irq);
1556                 if (do_disconnect)
1557                         snd_card_disconnect(chip->card);
1558                 return -1;
1559         }
1560         chip->irq = chip->pci->irq;
1561         pci_intx(chip->pci, !chip->msi);
1562         return 0;
1563 }
1564
1565
1566 static void azx_stop_chip(struct azx *chip)
1567 {
1568         if (!chip->initialized)
1569                 return;
1570
1571         /* disable interrupts */
1572         azx_int_disable(chip);
1573         azx_int_clear(chip);
1574
1575         /* disable CORB/RIRB */
1576         azx_free_cmd_io(chip);
1577
1578         /* disable position buffer */
1579         azx_writel(chip, DPLBASE, 0);
1580         azx_writel(chip, DPUBASE, 0);
1581
1582         chip->initialized = 0;
1583 }
1584
1585 #ifdef CONFIG_SND_HDA_POWER_SAVE
1586 /* power-up/down the controller */
1587 static void azx_power_notify(struct hda_codec *codec)
1588 {
1589         struct azx *chip = codec->bus->private_data;
1590         struct hda_codec *c;
1591         int power_on = 0;
1592
1593         list_for_each_entry(c, &codec->bus->codec_list, list) {
1594                 if (c->power_on) {
1595                         power_on = 1;
1596                         break;
1597                 }
1598         }
1599         if (power_on)
1600                 azx_init_chip(chip);
1601         else if (chip->running && power_save_controller)
1602                 azx_stop_chip(chip);
1603 }
1604 #endif /* CONFIG_SND_HDA_POWER_SAVE */
1605
1606 #ifdef CONFIG_PM
1607 /*
1608  * power management
1609  */
1610 static int azx_suspend(struct pci_dev *pci, pm_message_t state)
1611 {
1612         struct snd_card *card = pci_get_drvdata(pci);
1613         struct azx *chip = card->private_data;
1614         int i;
1615
1616         snd_power_change_state(card, SNDRV_CTL_POWER_D3hot);
1617         for (i = 0; i < AZX_MAX_PCMS; i++)
1618                 snd_pcm_suspend_all(chip->pcm[i]);
1619         if (chip->initialized)
1620                 snd_hda_suspend(chip->bus, state);
1621         azx_stop_chip(chip);
1622         if (chip->irq >= 0) {
1623                 synchronize_irq(chip->irq);
1624                 free_irq(chip->irq, chip);
1625                 chip->irq = -1;
1626         }
1627         if (chip->msi)
1628                 pci_disable_msi(chip->pci);
1629         pci_disable_device(pci);
1630         pci_save_state(pci);
1631         pci_set_power_state(pci, pci_choose_state(pci, state));
1632         return 0;
1633 }
1634
1635 static int azx_resume(struct pci_dev *pci)
1636 {
1637         struct snd_card *card = pci_get_drvdata(pci);
1638         struct azx *chip = card->private_data;
1639
1640         pci_set_power_state(pci, PCI_D0);
1641         pci_restore_state(pci);
1642         if (pci_enable_device(pci) < 0) {
1643                 printk(KERN_ERR "hda-intel: pci_enable_device failed, "
1644                        "disabling device\n");
1645                 snd_card_disconnect(card);
1646                 return -EIO;
1647         }
1648         pci_set_master(pci);
1649         if (chip->msi)
1650                 if (pci_enable_msi(pci) < 0)
1651                         chip->msi = 0;
1652         if (azx_acquire_irq(chip, 1) < 0)
1653                 return -EIO;
1654         azx_init_pci(chip);
1655
1656         if (snd_hda_codecs_inuse(chip->bus))
1657                 azx_init_chip(chip);
1658
1659         snd_hda_resume(chip->bus);
1660         snd_power_change_state(card, SNDRV_CTL_POWER_D0);
1661         return 0;
1662 }
1663 #endif /* CONFIG_PM */
1664
1665
1666 /*
1667  * destructor
1668  */
1669 static int azx_free(struct azx *chip)
1670 {
1671         int i;
1672
1673         if (chip->initialized) {
1674                 for (i = 0; i < chip->num_streams; i++)
1675                         azx_stream_stop(chip, &chip->azx_dev[i]);
1676                 azx_stop_chip(chip);
1677         }
1678
1679         if (chip->irq >= 0) {
1680                 synchronize_irq(chip->irq);
1681                 free_irq(chip->irq, (void*)chip);
1682         }
1683         if (chip->msi)
1684                 pci_disable_msi(chip->pci);
1685         if (chip->remap_addr)
1686                 iounmap(chip->remap_addr);
1687
1688         if (chip->azx_dev) {
1689                 for (i = 0; i < chip->num_streams; i++)
1690                         if (chip->azx_dev[i].bdl.area)
1691                                 snd_dma_free_pages(&chip->azx_dev[i].bdl);
1692         }
1693         if (chip->rb.area)
1694                 snd_dma_free_pages(&chip->rb);
1695         if (chip->posbuf.area)
1696                 snd_dma_free_pages(&chip->posbuf);
1697         pci_release_regions(chip->pci);
1698         pci_disable_device(chip->pci);
1699         kfree(chip->azx_dev);
1700         kfree(chip);
1701
1702         return 0;
1703 }
1704
1705 static int azx_dev_free(struct snd_device *device)
1706 {
1707         return azx_free(device->device_data);
1708 }
1709
1710 /*
1711  * white/black-listing for position_fix
1712  */
1713 static struct snd_pci_quirk position_fix_list[] __devinitdata = {
1714         SND_PCI_QUIRK(0x1028, 0x01cc, "Dell D820", POS_FIX_NONE),
1715         SND_PCI_QUIRK(0x1028, 0x01de, "Dell Precision 390", POS_FIX_NONE),
1716         SND_PCI_QUIRK(0x1043, 0x813d, "ASUS P5AD2", POS_FIX_NONE),
1717         {}
1718 };
1719
1720 static int __devinit check_position_fix(struct azx *chip, int fix)
1721 {
1722         const struct snd_pci_quirk *q;
1723
1724         if (fix == POS_FIX_AUTO) {
1725                 q = snd_pci_quirk_lookup(chip->pci, position_fix_list);
1726                 if (q) {
1727                         printk(KERN_INFO
1728                                     "hda_intel: position_fix set to %d "
1729                                     "for device %04x:%04x\n",
1730                                     q->value, q->subvendor, q->subdevice);
1731                         return q->value;
1732                 }
1733         }
1734         return fix;
1735 }
1736
1737 /*
1738  * black-lists for probe_mask
1739  */
1740 static struct snd_pci_quirk probe_mask_list[] __devinitdata = {
1741         /* Thinkpad often breaks the controller communication when accessing
1742          * to the non-working (or non-existing) modem codec slot.
1743          */
1744         SND_PCI_QUIRK(0x1014, 0x05b7, "Thinkpad Z60", 0x01),
1745         SND_PCI_QUIRK(0x17aa, 0x2010, "Thinkpad X/T/R60", 0x01),
1746         SND_PCI_QUIRK(0x17aa, 0x20ac, "Thinkpad X/T/R61", 0x01),
1747         {}
1748 };
1749
1750 static void __devinit check_probe_mask(struct azx *chip, int dev)
1751 {
1752         const struct snd_pci_quirk *q;
1753
1754         if (probe_mask[dev] == -1) {
1755                 q = snd_pci_quirk_lookup(chip->pci, probe_mask_list);
1756                 if (q) {
1757                         printk(KERN_INFO
1758                                "hda_intel: probe_mask set to 0x%x "
1759                                "for device %04x:%04x\n",
1760                                q->value, q->subvendor, q->subdevice);
1761                         probe_mask[dev] = q->value;
1762                 }
1763         }
1764 }
1765
1766
1767 /*
1768  * constructor
1769  */
1770 static int __devinit azx_create(struct snd_card *card, struct pci_dev *pci,
1771                                 int dev, int driver_type,
1772                                 struct azx **rchip)
1773 {
1774         struct azx *chip;
1775         int i, err;
1776         unsigned short gcap;
1777         static struct snd_device_ops ops = {
1778                 .dev_free = azx_dev_free,
1779         };
1780
1781         *rchip = NULL;
1782
1783         err = pci_enable_device(pci);
1784         if (err < 0)
1785                 return err;
1786
1787         chip = kzalloc(sizeof(*chip), GFP_KERNEL);
1788         if (!chip) {
1789                 snd_printk(KERN_ERR SFX "cannot allocate chip\n");
1790                 pci_disable_device(pci);
1791                 return -ENOMEM;
1792         }
1793
1794         spin_lock_init(&chip->reg_lock);
1795         mutex_init(&chip->open_mutex);
1796         chip->card = card;
1797         chip->pci = pci;
1798         chip->irq = -1;
1799         chip->driver_type = driver_type;
1800         chip->msi = enable_msi;
1801
1802         chip->position_fix = check_position_fix(chip, position_fix[dev]);
1803         check_probe_mask(chip, dev);
1804
1805         chip->single_cmd = single_cmd;
1806
1807 #if BITS_PER_LONG != 64
1808         /* Fix up base address on ULI M5461 */
1809         if (chip->driver_type == AZX_DRIVER_ULI) {
1810                 u16 tmp3;
1811                 pci_read_config_word(pci, 0x40, &tmp3);
1812                 pci_write_config_word(pci, 0x40, tmp3 | 0x10);
1813                 pci_write_config_dword(pci, PCI_BASE_ADDRESS_1, 0);
1814         }
1815 #endif
1816
1817         err = pci_request_regions(pci, "ICH HD audio");
1818         if (err < 0) {
1819                 kfree(chip);
1820                 pci_disable_device(pci);
1821                 return err;
1822         }
1823
1824         chip->addr = pci_resource_start(pci, 0);
1825         chip->remap_addr = ioremap_nocache(chip->addr, pci_resource_len(pci,0));
1826         if (chip->remap_addr == NULL) {
1827                 snd_printk(KERN_ERR SFX "ioremap error\n");
1828                 err = -ENXIO;
1829                 goto errout;
1830         }
1831
1832         if (chip->msi)
1833                 if (pci_enable_msi(pci) < 0)
1834                         chip->msi = 0;
1835
1836         if (azx_acquire_irq(chip, 0) < 0) {
1837                 err = -EBUSY;
1838                 goto errout;
1839         }
1840
1841         pci_set_master(pci);
1842         synchronize_irq(chip->irq);
1843
1844         gcap = azx_readw(chip, GCAP);
1845         snd_printdd("chipset global capabilities = 0x%x\n", gcap);
1846
1847         /* allow 64bit DMA address if supported by H/W */
1848         if ((gcap & 0x01) && !pci_set_dma_mask(pci, DMA_64BIT_MASK))
1849                 pci_set_consistent_dma_mask(pci, DMA_64BIT_MASK);
1850
1851         /* read number of streams from GCAP register instead of using
1852          * hardcoded value
1853          */
1854         chip->capture_streams = (gcap >> 8) & 0x0f;
1855         chip->playback_streams = (gcap >> 12) & 0x0f;
1856         if (!chip->playback_streams && !chip->capture_streams) {
1857                 /* gcap didn't give any info, switching to old method */
1858
1859                 switch (chip->driver_type) {
1860                 case AZX_DRIVER_ULI:
1861                         chip->playback_streams = ULI_NUM_PLAYBACK;
1862                         chip->capture_streams = ULI_NUM_CAPTURE;
1863                         break;
1864                 case AZX_DRIVER_ATIHDMI:
1865                         chip->playback_streams = ATIHDMI_NUM_PLAYBACK;
1866                         chip->capture_streams = ATIHDMI_NUM_CAPTURE;
1867                         break;
1868                 default:
1869                         chip->playback_streams = ICH6_NUM_PLAYBACK;
1870                         chip->capture_streams = ICH6_NUM_CAPTURE;
1871                         break;
1872                 }
1873         }
1874         chip->capture_index_offset = 0;
1875         chip->playback_index_offset = chip->capture_streams;
1876         chip->num_streams = chip->playback_streams + chip->capture_streams;
1877         chip->azx_dev = kcalloc(chip->num_streams, sizeof(*chip->azx_dev),
1878                                 GFP_KERNEL);
1879         if (!chip->azx_dev) {
1880                 snd_printk(KERN_ERR "cannot malloc azx_dev\n");
1881                 goto errout;
1882         }
1883
1884         for (i = 0; i < chip->num_streams; i++) {
1885                 /* allocate memory for the BDL for each stream */
1886                 err = snd_dma_alloc_pages(SNDRV_DMA_TYPE_DEV,
1887                                           snd_dma_pci_data(chip->pci),
1888                                           BDL_SIZE, &chip->azx_dev[i].bdl);
1889                 if (err < 0) {
1890                         snd_printk(KERN_ERR SFX "cannot allocate BDL\n");
1891                         goto errout;
1892                 }
1893         }
1894         /* allocate memory for the position buffer */
1895         err = snd_dma_alloc_pages(SNDRV_DMA_TYPE_DEV,
1896                                   snd_dma_pci_data(chip->pci),
1897                                   chip->num_streams * 8, &chip->posbuf);
1898         if (err < 0) {
1899                 snd_printk(KERN_ERR SFX "cannot allocate posbuf\n");
1900                 goto errout;
1901         }
1902         /* allocate CORB/RIRB */
1903         if (!chip->single_cmd) {
1904                 err = azx_alloc_cmd_io(chip);
1905                 if (err < 0)
1906                         goto errout;
1907         }
1908
1909         /* initialize streams */
1910         azx_init_stream(chip);
1911
1912         /* initialize chip */
1913         azx_init_pci(chip);
1914         azx_init_chip(chip);
1915
1916         /* codec detection */
1917         if (!chip->codec_mask) {
1918                 snd_printk(KERN_ERR SFX "no codecs found!\n");
1919                 err = -ENODEV;
1920                 goto errout;
1921         }
1922
1923         err = snd_device_new(card, SNDRV_DEV_LOWLEVEL, chip, &ops);
1924         if (err <0) {
1925                 snd_printk(KERN_ERR SFX "Error creating device [card]!\n");
1926                 goto errout;
1927         }
1928
1929         strcpy(card->driver, "HDA-Intel");
1930         strcpy(card->shortname, driver_short_names[chip->driver_type]);
1931         sprintf(card->longname, "%s at 0x%lx irq %i",
1932                 card->shortname, chip->addr, chip->irq);
1933
1934         *rchip = chip;
1935         return 0;
1936
1937  errout:
1938         azx_free(chip);
1939         return err;
1940 }
1941
1942 static void power_down_all_codecs(struct azx *chip)
1943 {
1944 #ifdef CONFIG_SND_HDA_POWER_SAVE
1945         /* The codecs were powered up in snd_hda_codec_new().
1946          * Now all initialization done, so turn them down if possible
1947          */
1948         struct hda_codec *codec;
1949         list_for_each_entry(codec, &chip->bus->codec_list, list) {
1950                 snd_hda_power_down(codec);
1951         }
1952 #endif
1953 }
1954
1955 static int __devinit azx_probe(struct pci_dev *pci,
1956                                const struct pci_device_id *pci_id)
1957 {
1958         static int dev;
1959         struct snd_card *card;
1960         struct azx *chip;
1961         int err;
1962
1963         if (dev >= SNDRV_CARDS)
1964                 return -ENODEV;
1965         if (!enable[dev]) {
1966                 dev++;
1967                 return -ENOENT;
1968         }
1969
1970         card = snd_card_new(index[dev], id[dev], THIS_MODULE, 0);
1971         if (!card) {
1972                 snd_printk(KERN_ERR SFX "Error creating card!\n");
1973                 return -ENOMEM;
1974         }
1975
1976         err = azx_create(card, pci, dev, pci_id->driver_data, &chip);
1977         if (err < 0) {
1978                 snd_card_free(card);
1979                 return err;
1980         }
1981         card->private_data = chip;
1982
1983         /* create codec instances */
1984         err = azx_codec_create(chip, model[dev], probe_mask[dev]);
1985         if (err < 0) {
1986                 snd_card_free(card);
1987                 return err;
1988         }
1989
1990         /* create PCM streams */
1991         err = azx_pcm_create(chip);
1992         if (err < 0) {
1993                 snd_card_free(card);
1994                 return err;
1995         }
1996
1997         /* create mixer controls */
1998         err = azx_mixer_create(chip);
1999         if (err < 0) {
2000                 snd_card_free(card);
2001                 return err;
2002         }
2003
2004         snd_card_set_dev(card, &pci->dev);
2005
2006         err = snd_card_register(card);
2007         if (err < 0) {
2008                 snd_card_free(card);
2009                 return err;
2010         }
2011
2012         pci_set_drvdata(pci, card);
2013         chip->running = 1;
2014         power_down_all_codecs(chip);
2015
2016         dev++;
2017         return err;
2018 }
2019
2020 static void __devexit azx_remove(struct pci_dev *pci)
2021 {
2022         snd_card_free(pci_get_drvdata(pci));
2023         pci_set_drvdata(pci, NULL);
2024 }
2025
2026 /* PCI IDs */
2027 static struct pci_device_id azx_ids[] = {
2028         /* ICH 6..10 */
2029         { PCI_DEVICE(0x8086, 0x2668), .driver_data = AZX_DRIVER_ICH },
2030         { PCI_DEVICE(0x8086, 0x27d8), .driver_data = AZX_DRIVER_ICH },
2031         { PCI_DEVICE(0x8086, 0x269a), .driver_data = AZX_DRIVER_ICH },
2032         { PCI_DEVICE(0x8086, 0x284b), .driver_data = AZX_DRIVER_ICH },
2033         { PCI_DEVICE(0x8086, 0x293e), .driver_data = AZX_DRIVER_ICH },
2034         { PCI_DEVICE(0x8086, 0x293f), .driver_data = AZX_DRIVER_ICH },
2035         { PCI_DEVICE(0x8086, 0x3a3e), .driver_data = AZX_DRIVER_ICH },
2036         { PCI_DEVICE(0x8086, 0x3a6e), .driver_data = AZX_DRIVER_ICH },
2037         /* SCH */
2038         { PCI_DEVICE(0x8086, 0x811b), .driver_data = AZX_DRIVER_SCH },
2039         /* ATI SB 450/600 */
2040         { PCI_DEVICE(0x1002, 0x437b), .driver_data = AZX_DRIVER_ATI },
2041         { PCI_DEVICE(0x1002, 0x4383), .driver_data = AZX_DRIVER_ATI },
2042         /* ATI HDMI */
2043         { PCI_DEVICE(0x1002, 0x793b), .driver_data = AZX_DRIVER_ATIHDMI },
2044         { PCI_DEVICE(0x1002, 0x7919), .driver_data = AZX_DRIVER_ATIHDMI },
2045         { PCI_DEVICE(0x1002, 0x960f), .driver_data = AZX_DRIVER_ATIHDMI },
2046         { PCI_DEVICE(0x1002, 0xaa00), .driver_data = AZX_DRIVER_ATIHDMI },
2047         { PCI_DEVICE(0x1002, 0xaa08), .driver_data = AZX_DRIVER_ATIHDMI },
2048         { PCI_DEVICE(0x1002, 0xaa10), .driver_data = AZX_DRIVER_ATIHDMI },
2049         { PCI_DEVICE(0x1002, 0xaa18), .driver_data = AZX_DRIVER_ATIHDMI },
2050         { PCI_DEVICE(0x1002, 0xaa20), .driver_data = AZX_DRIVER_ATIHDMI },
2051         { PCI_DEVICE(0x1002, 0xaa28), .driver_data = AZX_DRIVER_ATIHDMI },
2052         { PCI_DEVICE(0x1002, 0xaa30), .driver_data = AZX_DRIVER_ATIHDMI },
2053         { PCI_DEVICE(0x1002, 0xaa38), .driver_data = AZX_DRIVER_ATIHDMI },
2054         { PCI_DEVICE(0x1002, 0xaa40), .driver_data = AZX_DRIVER_ATIHDMI },
2055         { PCI_DEVICE(0x1002, 0xaa48), .driver_data = AZX_DRIVER_ATIHDMI },
2056         /* VIA VT8251/VT8237A */
2057         { PCI_DEVICE(0x1106, 0x3288), .driver_data = AZX_DRIVER_VIA },
2058         /* SIS966 */
2059         { PCI_DEVICE(0x1039, 0x7502), .driver_data = AZX_DRIVER_SIS },
2060         /* ULI M5461 */
2061         { PCI_DEVICE(0x10b9, 0x5461), .driver_data = AZX_DRIVER_ULI },
2062         /* NVIDIA MCP */
2063         { PCI_DEVICE(0x10de, 0x026c), .driver_data = AZX_DRIVER_NVIDIA },
2064         { PCI_DEVICE(0x10de, 0x0371), .driver_data = AZX_DRIVER_NVIDIA },
2065         { PCI_DEVICE(0x10de, 0x03e4), .driver_data = AZX_DRIVER_NVIDIA },
2066         { PCI_DEVICE(0x10de, 0x03f0), .driver_data = AZX_DRIVER_NVIDIA },
2067         { PCI_DEVICE(0x10de, 0x044a), .driver_data = AZX_DRIVER_NVIDIA },
2068         { PCI_DEVICE(0x10de, 0x044b), .driver_data = AZX_DRIVER_NVIDIA },
2069         { PCI_DEVICE(0x10de, 0x055c), .driver_data = AZX_DRIVER_NVIDIA },
2070         { PCI_DEVICE(0x10de, 0x055d), .driver_data = AZX_DRIVER_NVIDIA },
2071         { PCI_DEVICE(0x10de, 0x0774), .driver_data = AZX_DRIVER_NVIDIA },
2072         { PCI_DEVICE(0x10de, 0x0775), .driver_data = AZX_DRIVER_NVIDIA },
2073         { PCI_DEVICE(0x10de, 0x0776), .driver_data = AZX_DRIVER_NVIDIA },
2074         { PCI_DEVICE(0x10de, 0x0777), .driver_data = AZX_DRIVER_NVIDIA },
2075         { PCI_DEVICE(0x10de, 0x07fc), .driver_data = AZX_DRIVER_NVIDIA },
2076         { PCI_DEVICE(0x10de, 0x07fd), .driver_data = AZX_DRIVER_NVIDIA },
2077         { PCI_DEVICE(0x10de, 0x0ac0), .driver_data = AZX_DRIVER_NVIDIA },
2078         { PCI_DEVICE(0x10de, 0x0ac1), .driver_data = AZX_DRIVER_NVIDIA },
2079         { PCI_DEVICE(0x10de, 0x0ac2), .driver_data = AZX_DRIVER_NVIDIA },
2080         { PCI_DEVICE(0x10de, 0x0ac3), .driver_data = AZX_DRIVER_NVIDIA },
2081         { PCI_DEVICE(0x10de, 0x0bd4), .driver_data = AZX_DRIVER_NVIDIA },
2082         { PCI_DEVICE(0x10de, 0x0bd5), .driver_data = AZX_DRIVER_NVIDIA },
2083         { PCI_DEVICE(0x10de, 0x0bd6), .driver_data = AZX_DRIVER_NVIDIA },
2084         { PCI_DEVICE(0x10de, 0x0bd7), .driver_data = AZX_DRIVER_NVIDIA },
2085         { 0, }
2086 };
2087 MODULE_DEVICE_TABLE(pci, azx_ids);
2088
2089 /* pci_driver definition */
2090 static struct pci_driver driver = {
2091         .name = "HDA Intel",
2092         .id_table = azx_ids,
2093         .probe = azx_probe,
2094         .remove = __devexit_p(azx_remove),
2095 #ifdef CONFIG_PM
2096         .suspend = azx_suspend,
2097         .resume = azx_resume,
2098 #endif
2099 };
2100
2101 static int __init alsa_card_azx_init(void)
2102 {
2103         return pci_register_driver(&driver);
2104 }
2105
2106 static void __exit alsa_card_azx_exit(void)
2107 {
2108         pci_unregister_driver(&driver);
2109 }
2110
2111 module_init(alsa_card_azx_init)
2112 module_exit(alsa_card_azx_exit)