ALSA: HDA: Support for playback from VPR
[linux-2.6.git] / sound / pci / hda / hda_intel.c
1 /*
2  *
3  *  hda_intel.c - Implementation of primary alsa driver code base
4  *                for Intel HD Audio.
5  *
6  *  Copyright(c) 2004 Intel Corporation. All rights reserved.
7  *
8  *  Copyright (c) 2004 Takashi Iwai <tiwai@suse.de>
9  *                     PeiSen Hou <pshou@realtek.com.tw>
10  *
11  *  This program is free software; you can redistribute it and/or modify it
12  *  under the terms of the GNU General Public License as published by the Free
13  *  Software Foundation; either version 2 of the License, or (at your option)
14  *  any later version.
15  *
16  *  This program is distributed in the hope that it will be useful, but WITHOUT
17  *  ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
18  *  FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
19  *  more details.
20  *
21  *  You should have received a copy of the GNU General Public License along with
22  *  this program; if not, write to the Free Software Foundation, Inc., 59
23  *  Temple Place - Suite 330, Boston, MA  02111-1307, USA.
24  *
25  *  CONTACTS:
26  *
27  *  Matt Jared          matt.jared@intel.com
28  *  Andy Kopp           andy.kopp@intel.com
29  *  Dan Kogan           dan.d.kogan@intel.com
30  *
31  *  CHANGES:
32  *
33  *  2004.12.01  Major rewrite by tiwai, merged the work of pshou
34  *
35  */
36
37 #include <linux/delay.h>
38 #include <linux/interrupt.h>
39 #include <linux/kernel.h>
40 #include <linux/module.h>
41 #include <linux/dma-mapping.h>
42 #include <linux/moduleparam.h>
43 #include <linux/init.h>
44 #include <linux/slab.h>
45 #include <linux/pci.h>
46 #include <linux/mutex.h>
47 #include <linux/reboot.h>
48 #include <linux/io.h>
49 #include <linux/clk.h>
50 #ifdef CONFIG_X86
51 /* for snoop control */
52 #include <asm/pgtable.h>
53 #include <asm/cacheflush.h>
54 #endif
55 #include <sound/core.h>
56 #include <sound/initval.h>
57 #include "hda_codec.h"
58
59 #ifdef CONFIG_SND_HDA_VPR
60 #include <linux/nvmap.h>
61 #endif
62
63 static int index[SNDRV_CARDS] = SNDRV_DEFAULT_IDX;
64 static char *id[SNDRV_CARDS] = SNDRV_DEFAULT_STR;
65 static bool enable[SNDRV_CARDS] = SNDRV_DEFAULT_ENABLE_PNP;
66 static char *model[SNDRV_CARDS];
67 static int position_fix[SNDRV_CARDS];
68 static int bdl_pos_adj[SNDRV_CARDS] = {[0 ... (SNDRV_CARDS-1)] = -1};
69 static int probe_mask[SNDRV_CARDS] = {[0 ... (SNDRV_CARDS-1)] = -1};
70 static int probe_only[SNDRV_CARDS];
71 static bool single_cmd;
72 static int enable_msi = -1;
73 #ifdef CONFIG_SND_HDA_PATCH_LOADER
74 static char *patch[SNDRV_CARDS];
75 #endif
76 #ifdef CONFIG_SND_HDA_INPUT_BEEP
77 static int beep_mode[SNDRV_CARDS] = {[0 ... (SNDRV_CARDS-1)] =
78                                         CONFIG_SND_HDA_INPUT_BEEP_MODE};
79 #endif
80
81 module_param_array(index, int, NULL, 0444);
82 MODULE_PARM_DESC(index, "Index value for Intel HD audio interface.");
83 module_param_array(id, charp, NULL, 0444);
84 MODULE_PARM_DESC(id, "ID string for Intel HD audio interface.");
85 module_param_array(enable, bool, NULL, 0444);
86 MODULE_PARM_DESC(enable, "Enable Intel HD audio interface.");
87 module_param_array(model, charp, NULL, 0444);
88 MODULE_PARM_DESC(model, "Use the given board model.");
89 module_param_array(position_fix, int, NULL, 0444);
90 MODULE_PARM_DESC(position_fix, "DMA pointer read method."
91                  "(0 = auto, 1 = LPIB, 2 = POSBUF, 3 = VIACOMBO, 4 = COMBO).");
92 module_param_array(bdl_pos_adj, int, NULL, 0644);
93 MODULE_PARM_DESC(bdl_pos_adj, "BDL position adjustment offset.");
94 module_param_array(probe_mask, int, NULL, 0444);
95 MODULE_PARM_DESC(probe_mask, "Bitmask to probe codecs (default = -1).");
96 module_param_array(probe_only, int, NULL, 0444);
97 MODULE_PARM_DESC(probe_only, "Only probing and no codec initialization.");
98 module_param(single_cmd, bool, 0444);
99 MODULE_PARM_DESC(single_cmd, "Use single command to communicate with codecs "
100                  "(for debugging only).");
101 module_param(enable_msi, bint, 0444);
102 MODULE_PARM_DESC(enable_msi, "Enable Message Signaled Interrupt (MSI)");
103 #ifdef CONFIG_SND_HDA_PATCH_LOADER
104 module_param_array(patch, charp, NULL, 0444);
105 MODULE_PARM_DESC(patch, "Patch file for Intel HD audio interface.");
106 #endif
107 #ifdef CONFIG_SND_HDA_INPUT_BEEP
108 module_param_array(beep_mode, int, NULL, 0444);
109 MODULE_PARM_DESC(beep_mode, "Select HDA Beep registration mode "
110                             "(0=off, 1=on, 2=mute switch on/off) (default=1).");
111 #endif
112
113 #ifdef CONFIG_SND_HDA_POWER_SAVE
114 static int power_save = CONFIG_SND_HDA_POWER_SAVE_DEFAULT;
115 module_param(power_save, int, 0644);
116 MODULE_PARM_DESC(power_save, "Automatic power-saving timeout "
117                  "(in second, 0 = disable).");
118
119 /* reset the HD-audio controller in power save mode.
120  * this may give more power-saving, but will take longer time to
121  * wake up.
122  */
123 static bool power_save_controller = 1;
124 module_param(power_save_controller, bool, 0644);
125 MODULE_PARM_DESC(power_save_controller, "Reset controller in power save mode.");
126 #endif
127
128 static int align_buffer_size = -1;
129 module_param(align_buffer_size, bint, 0644);
130 MODULE_PARM_DESC(align_buffer_size,
131                 "Force buffer and period sizes to be multiple of 128 bytes.");
132
133 #ifdef CONFIG_X86
134 static bool hda_snoop = true;
135 module_param_named(snoop, hda_snoop, bool, 0444);
136 MODULE_PARM_DESC(snoop, "Enable/disable snooping");
137 #define azx_snoop(chip)         (chip)->snoop
138 #else
139 #define hda_snoop               true
140 #define azx_snoop(chip)         true
141 #endif
142
143
144 MODULE_LICENSE("GPL");
145 MODULE_SUPPORTED_DEVICE("{{Intel, ICH6},"
146                          "{Intel, ICH6M},"
147                          "{Intel, ICH7},"
148                          "{Intel, ESB2},"
149                          "{Intel, ICH8},"
150                          "{Intel, ICH9},"
151                          "{Intel, ICH10},"
152                          "{Intel, PCH},"
153                          "{Intel, CPT},"
154                          "{Intel, PPT},"
155                          "{Intel, LPT},"
156                          "{Intel, PBG},"
157                          "{Intel, SCH},"
158                          "{ATI, SB450},"
159                          "{ATI, SB600},"
160                          "{ATI, RS600},"
161                          "{ATI, RS690},"
162                          "{ATI, RS780},"
163                          "{ATI, R600},"
164                          "{ATI, RV630},"
165                          "{ATI, RV610},"
166                          "{ATI, RV670},"
167                          "{ATI, RV635},"
168                          "{ATI, RV620},"
169                          "{ATI, RV770},"
170                          "{VIA, VT8251},"
171                          "{VIA, VT8237A},"
172                          "{SiS, SIS966},"
173                          "{ULI, M5461}}");
174 MODULE_DESCRIPTION("Intel HDA driver");
175
176 #ifdef CONFIG_SND_VERBOSE_PRINTK
177 #define SFX     /* nop */
178 #else
179 #define SFX     "hda-intel: "
180 #endif
181
182 /*
183  * registers
184  */
185 #define ICH6_REG_GCAP                   0x00
186 #define   ICH6_GCAP_64OK        (1 << 0)   /* 64bit address support */
187 #define   ICH6_GCAP_NSDO        (3 << 1)   /* # of serial data out signals */
188 #define   ICH6_GCAP_BSS         (31 << 3)  /* # of bidirectional streams */
189 #define   ICH6_GCAP_ISS         (15 << 8)  /* # of input streams */
190 #define   ICH6_GCAP_OSS         (15 << 12) /* # of output streams */
191 #define ICH6_REG_VMIN                   0x02
192 #define ICH6_REG_VMAJ                   0x03
193 #define ICH6_REG_OUTPAY                 0x04
194 #define ICH6_REG_INPAY                  0x06
195 #define ICH6_REG_GCTL                   0x08
196 #define   ICH6_GCTL_RESET       (1 << 0)   /* controller reset */
197 #define   ICH6_GCTL_FCNTRL      (1 << 1)   /* flush control */
198 #define   ICH6_GCTL_UNSOL       (1 << 8)   /* accept unsol. response enable */
199 #define ICH6_REG_WAKEEN                 0x0c
200 #define ICH6_REG_STATESTS               0x0e
201 #define ICH6_REG_GSTS                   0x10
202 #define   ICH6_GSTS_FSTS        (1 << 1)   /* flush status */
203 #define ICH6_REG_INTCTL                 0x20
204 #define ICH6_REG_INTSTS                 0x24
205 #define ICH6_REG_WALLCLK                0x30    /* 24Mhz source */
206 #define ICH6_REG_OLD_SSYNC              0x34    /* SSYNC for old ICH */
207 #define ICH6_REG_SSYNC                  0x38
208 #define ICH6_REG_CORBLBASE              0x40
209 #define ICH6_REG_CORBUBASE              0x44
210 #define ICH6_REG_CORBWP                 0x48
211 #define ICH6_REG_CORBRP                 0x4a
212 #define   ICH6_CORBRP_RST       (1 << 15)  /* read pointer reset */
213 #define ICH6_REG_CORBCTL                0x4c
214 #define   ICH6_CORBCTL_RUN      (1 << 1)   /* enable DMA */
215 #define   ICH6_CORBCTL_CMEIE    (1 << 0)   /* enable memory error irq */
216 #define ICH6_REG_CORBSTS                0x4d
217 #define   ICH6_CORBSTS_CMEI     (1 << 0)   /* memory error indication */
218 #define ICH6_REG_CORBSIZE               0x4e
219
220 #define ICH6_REG_RIRBLBASE              0x50
221 #define ICH6_REG_RIRBUBASE              0x54
222 #define ICH6_REG_RIRBWP                 0x58
223 #define   ICH6_RIRBWP_RST       (1 << 15)  /* write pointer reset */
224 #define ICH6_REG_RINTCNT                0x5a
225 #define ICH6_REG_RIRBCTL                0x5c
226 #define   ICH6_RBCTL_IRQ_EN     (1 << 0)   /* enable IRQ */
227 #define   ICH6_RBCTL_DMA_EN     (1 << 1)   /* enable DMA */
228 #define   ICH6_RBCTL_OVERRUN_EN (1 << 2)   /* enable overrun irq */
229 #define ICH6_REG_RIRBSTS                0x5d
230 #define   ICH6_RBSTS_IRQ        (1 << 0)   /* response irq */
231 #define   ICH6_RBSTS_OVERRUN    (1 << 2)   /* overrun irq */
232 #define ICH6_REG_RIRBSIZE               0x5e
233
234 #define ICH6_REG_IC                     0x60
235 #define ICH6_REG_IR                     0x64
236 #define ICH6_REG_IRS                    0x68
237 #define   ICH6_IRS_VALID        (1<<1)
238 #define   ICH6_IRS_BUSY         (1<<0)
239
240 #define ICH6_REG_DPLBASE                0x70
241 #define ICH6_REG_DPUBASE                0x74
242 #define   ICH6_DPLBASE_ENABLE   0x1     /* Enable position buffer */
243
244 /* SD offset: SDI0=0x80, SDI1=0xa0, ... SDO3=0x160 */
245 enum { SDI0, SDI1, SDI2, SDI3, SDO0, SDO1, SDO2, SDO3 };
246
247 /* stream register offsets from stream base */
248 #define ICH6_REG_SD_CTL                 0x00
249 #define ICH6_REG_SD_STS                 0x03
250 #define ICH6_REG_SD_LPIB                0x04
251 #define ICH6_REG_SD_CBL                 0x08
252 #define ICH6_REG_SD_LVI                 0x0c
253 #define ICH6_REG_SD_FIFOW               0x0e
254 #define ICH6_REG_SD_FIFOSIZE            0x10
255 #define ICH6_REG_SD_FORMAT              0x12
256 #define ICH6_REG_SD_BDLPL               0x18
257 #define ICH6_REG_SD_BDLPU               0x1c
258
259 /* PCI space */
260 #define ICH6_PCIREG_TCSEL       0x44
261
262 /*
263  * other constants
264  */
265
266 /* max number of SDs */
267 /* ICH, ATI and VIA have 4 playback and 4 capture */
268 #define ICH6_NUM_CAPTURE        4
269 #define ICH6_NUM_PLAYBACK       4
270
271 /* ULI has 6 playback and 5 capture */
272 #define ULI_NUM_CAPTURE         5
273 #define ULI_NUM_PLAYBACK        6
274
275 /* ATI HDMI has 1 playback and 0 capture */
276 #define ATIHDMI_NUM_CAPTURE     0
277 #define ATIHDMI_NUM_PLAYBACK    1
278
279 /* TERA has 4 playback and 3 capture */
280 #define TERA_NUM_CAPTURE        3
281 #define TERA_NUM_PLAYBACK       4
282
283 /* this number is statically defined for simplicity */
284 #define MAX_AZX_DEV             16
285
286 /* max number of fragments - we may use more if allocating more pages for BDL */
287 #define BDL_SIZE                4096
288 #define AZX_MAX_BDL_ENTRIES     (BDL_SIZE / 16)
289 #define AZX_MAX_FRAG            32
290 /* max buffer size - no h/w limit, you can increase as you like */
291 #define AZX_MAX_BUF_SIZE        (1024*1024*1024)
292
293 /* RIRB int mask: overrun[2], response[0] */
294 #define RIRB_INT_RESPONSE       0x01
295 #define RIRB_INT_OVERRUN        0x04
296 #define RIRB_INT_MASK           0x05
297
298 /* STATESTS int mask: S3,SD2,SD1,SD0 */
299 #define AZX_MAX_CODECS          8
300 #define AZX_DEFAULT_CODECS      4
301 #define STATESTS_INT_MASK       ((1 << AZX_MAX_CODECS) - 1)
302
303 /* SD_CTL bits */
304 #define SD_CTL_STREAM_RESET     0x01    /* stream reset bit */
305 #define SD_CTL_DMA_START        0x02    /* stream DMA start bit */
306 #define SD_CTL_STRIPE           (3 << 16)       /* stripe control */
307 #define SD_CTL_TRAFFIC_PRIO     (1 << 18)       /* traffic priority */
308 #define SD_CTL_DIR              (1 << 19)       /* bi-directional stream */
309 #define SD_CTL_STREAM_TAG_MASK  (0xf << 20)
310 #define SD_CTL_STREAM_TAG_SHIFT 20
311
312 /* SD_CTL and SD_STS */
313 #define SD_INT_DESC_ERR         0x10    /* descriptor error interrupt */
314 #define SD_INT_FIFO_ERR         0x08    /* FIFO error interrupt */
315 #define SD_INT_COMPLETE         0x04    /* completion interrupt */
316 #define SD_INT_MASK             (SD_INT_DESC_ERR|SD_INT_FIFO_ERR|\
317                                  SD_INT_COMPLETE)
318
319 /* SD_STS */
320 #define SD_STS_FIFO_READY       0x20    /* FIFO ready */
321
322 /* INTCTL and INTSTS */
323 #define ICH6_INT_ALL_STREAM     0xff       /* all stream interrupts */
324 #define ICH6_INT_CTRL_EN        0x40000000 /* controller interrupt enable bit */
325 #define ICH6_INT_GLOBAL_EN      0x80000000 /* global interrupt enable bit */
326
327 /* below are so far hardcoded - should read registers in future */
328 #define ICH6_MAX_CORB_ENTRIES   256
329 #define ICH6_MAX_RIRB_ENTRIES   256
330
331 /* position fix mode */
332 enum {
333         POS_FIX_AUTO,
334         POS_FIX_LPIB,
335         POS_FIX_POSBUF,
336         POS_FIX_VIACOMBO,
337         POS_FIX_COMBO,
338 };
339
340 /* Defines for ATI HD Audio support in SB450 south bridge */
341 #define ATI_SB450_HDAUDIO_MISC_CNTR2_ADDR   0x42
342 #define ATI_SB450_HDAUDIO_ENABLE_SNOOP      0x02
343
344 /* Defines for Nvidia HDA support */
345 #define NVIDIA_HDA_TRANSREG_ADDR      0x4e
346 #define NVIDIA_HDA_ENABLE_COHBITS     0x0f
347 #define NVIDIA_HDA_ISTRM_COH          0x4d
348 #define NVIDIA_HDA_OSTRM_COH          0x4c
349 #define NVIDIA_HDA_ENABLE_COHBIT      0x01
350
351 #ifdef CONFIG_SND_HDA_PLATFORM_NVIDIA_TEGRA
352 /* Defines for Nvidia Tegra HDA support */
353 #define NVIDIA_TEGRA_HDA_BAR0_OFFSET           0x8000
354
355 #define NVIDIA_TEGRA_HDA_CFG_CMD_OFFSET        0x1004
356 #define NVIDIA_TEGRA_HDA_CFG_BAR0_OFFSET       0x1010
357
358 #define NVIDIA_TEGRA_HDA_ENABLE_IO_SPACE       (1 << 0)
359 #define NVIDIA_TEGRA_HDA_ENABLE_MEM_SPACE      (1 << 1)
360 #define NVIDIA_TEGRA_HDA_ENABLE_BUS_MASTER     (1 << 2)
361 #define NVIDIA_TEGRA_HDA_ENABLE_SERR           (1 << 8)
362 #define NVIDIA_TEGRA_HDA_DISABLE_INTR          (1 << 10)
363 #define NVIDIA_TEGRA_HDA_BAR0_INIT_PROGRAM     0xFFFFFFFF
364 #define NVIDIA_TEGRA_HDA_BAR0_FINAL_PROGRAM    (1 << 14)
365
366 /* IPFS */
367 #define NVIDIA_TEGRA_HDA_IPFS_CONFIG           0x180
368 #define NVIDIA_TEGRA_HDA_IPFS_EN_FPCI          0x1
369
370 #define NVIDIA_TEGRA_HDA_IPFS_FPCI_BAR0        0x80
371 #define NVIDIA_TEGRA_HDA_FPCI_BAR0_START       0x40
372
373 #define NVIDIA_TEGRA_HDA_IPFS_INTR_MASK        0x188
374 #define NVIDIA_TEGRA_HDA_IPFS_EN_INTR          (1 << 16)
375 #endif /* CONFIG_SND_HDA_PLATFORM_NVIDIA_TEGRA */
376
377 /* Defines for Intel SCH HDA snoop control */
378 #define INTEL_SCH_HDA_DEVC      0x78
379 #define INTEL_SCH_HDA_DEVC_NOSNOOP       (0x1<<11)
380
381 /* Define IN stream 0 FIFO size offset in VIA controller */
382 #define VIA_IN_STREAM0_FIFO_SIZE_OFFSET 0x90
383 /* Define VIA HD Audio Device ID*/
384 #define VIA_HDAC_DEVICE_ID              0x3288
385
386 /* HD Audio class code */
387 #define PCI_CLASS_MULTIMEDIA_HD_AUDIO   0x0403
388
389 /*
390  */
391
392 struct azx_dev {
393         struct snd_dma_buffer bdl; /* BDL buffer */
394         u32 *posbuf;            /* position buffer pointer */
395
396         unsigned int bufsize;   /* size of the play buffer in bytes */
397         unsigned int period_bytes; /* size of the period in bytes */
398         unsigned int frags;     /* number for period in the play buffer */
399         unsigned int fifo_size; /* FIFO size */
400         unsigned long start_wallclk;    /* start + minimum wallclk */
401         unsigned long period_wallclk;   /* wallclk for period */
402
403         void __iomem *sd_addr;  /* stream descriptor pointer */
404
405         u32 sd_int_sta_mask;    /* stream int status mask */
406
407         /* pcm support */
408         struct snd_pcm_substream *substream;    /* assigned substream,
409                                                  * set in PCM open
410                                                  */
411         unsigned int format_val;        /* format value to be set in the
412                                          * controller and the codec
413                                          */
414         unsigned char stream_tag;       /* assigned stream */
415         unsigned char index;            /* stream index */
416         int assigned_key;               /* last device# key assigned to */
417
418         unsigned int opened :1;
419         unsigned int running :1;
420         unsigned int irq_pending :1;
421         /*
422          * For VIA:
423          *  A flag to ensure DMA position is 0
424          *  when link position is not greater than FIFO size
425          */
426         unsigned int insufficient :1;
427         unsigned int wc_marked:1;
428 };
429
430 /* CORB/RIRB */
431 struct azx_rb {
432         u32 *buf;               /* CORB/RIRB buffer
433                                  * Each CORB entry is 4byte, RIRB is 8byte
434                                  */
435         dma_addr_t addr;        /* physical address of CORB/RIRB buffer */
436         /* for RIRB */
437         unsigned short rp, wp;  /* read/write pointers */
438         int cmds[AZX_MAX_CODECS];       /* number of pending requests */
439         u32 res[AZX_MAX_CODECS];        /* last read value */
440 };
441
442 struct azx_pcm {
443         struct azx *chip;
444         struct snd_pcm *pcm;
445         struct hda_codec *codec;
446         struct hda_pcm_stream *hinfo[2];
447         struct list_head list;
448 };
449
450 struct azx {
451         struct snd_card *card;
452         struct pci_dev *pci;
453         struct platform_device *pdev;
454         struct device *dev;
455         int irq_id;
456         int dev_index;
457
458         /* chip type specific */
459         int driver_type;
460         unsigned int driver_caps;
461         int playback_streams;
462         int playback_index_offset;
463         int capture_streams;
464         int capture_index_offset;
465         int num_streams;
466
467         /* pci resources */
468         unsigned long addr;
469         void __iomem *remap_addr;
470 #ifdef CONFIG_SND_HDA_PLATFORM_NVIDIA_TEGRA
471         void __iomem *remap_config_addr;
472 #endif
473         int irq;
474
475 #ifdef CONFIG_SND_HDA_PLATFORM_DRIVER
476         /* platform driver clocks */
477         struct clk **platform_clks;
478         int platform_clk_count;
479         int platform_clk_enable;
480 #endif
481
482 #ifdef CONFIG_SND_HDA_VPR
483         struct nvmap_client *hda_vpr;
484         struct nvmap_handle_ref *handle_ref;
485         unsigned char *vaddr;
486         phys_addr_t paddr;
487 #endif
488
489         /* locks */
490         spinlock_t reg_lock;
491         struct mutex open_mutex;
492
493         /* streams (x num_streams) */
494         struct azx_dev *azx_dev;
495
496         /* PCM */
497         struct list_head pcm_list; /* azx_pcm list */
498
499         /* HD codec */
500         unsigned short codec_mask;
501         int  codec_probe_mask; /* copied from probe_mask option */
502         struct hda_bus *bus;
503         unsigned int beep_mode;
504
505         /* CORB/RIRB */
506         struct azx_rb corb;
507         struct azx_rb rirb;
508
509         /* CORB/RIRB and position buffers */
510         struct snd_dma_buffer rb;
511         struct snd_dma_buffer posbuf;
512
513         /* flags */
514         int position_fix[2]; /* for both playback/capture streams */
515         int poll_count;
516         unsigned int running :1;
517         unsigned int initialized :1;
518         unsigned int single_cmd :1;
519         unsigned int polling_mode :1;
520         unsigned int msi :1;
521         unsigned int irq_pending_warned :1;
522         unsigned int probing :1; /* codec probing phase */
523         unsigned int snoop:1;
524         unsigned int align_buffer_size:1;
525
526         /* for debugging */
527         unsigned int last_cmd[AZX_MAX_CODECS];
528
529         /* for pending irqs */
530         struct work_struct irq_pending_work;
531
532         /* reboot notifier (for mysterious hangup problem at power-down) */
533         struct notifier_block reboot_notifier;
534 };
535
536 /* driver types */
537 enum {
538         AZX_DRIVER_ICH,
539         AZX_DRIVER_PCH,
540         AZX_DRIVER_SCH,
541         AZX_DRIVER_ATI,
542         AZX_DRIVER_ATIHDMI,
543         AZX_DRIVER_ATIHDMI_NS,
544         AZX_DRIVER_VIA,
545         AZX_DRIVER_SIS,
546         AZX_DRIVER_ULI,
547         AZX_DRIVER_NVIDIA,
548         AZX_DRIVER_NVIDIA_TEGRA,
549         AZX_DRIVER_TERA,
550         AZX_DRIVER_CTX,
551         AZX_DRIVER_GENERIC,
552         AZX_NUM_DRIVERS, /* keep this as last entry */
553 };
554
555 /* driver quirks (capabilities) */
556 /* bits 0-7 are used for indicating driver type */
557 #define AZX_DCAPS_NO_TCSEL      (1 << 8)        /* No Intel TCSEL bit */
558 #define AZX_DCAPS_NO_MSI        (1 << 9)        /* No MSI support */
559 #define AZX_DCAPS_ATI_SNOOP     (1 << 10)       /* ATI snoop enable */
560 #define AZX_DCAPS_NVIDIA_SNOOP  (1 << 11)       /* Nvidia snoop enable */
561 #define AZX_DCAPS_SCH_SNOOP     (1 << 12)       /* SCH/PCH snoop enable */
562 #define AZX_DCAPS_RIRB_DELAY    (1 << 13)       /* Long delay in read loop */
563 #define AZX_DCAPS_RIRB_PRE_DELAY (1 << 14)      /* Put a delay before read */
564 #define AZX_DCAPS_CTX_WORKAROUND (1 << 15)      /* X-Fi workaround */
565 #define AZX_DCAPS_POSFIX_LPIB   (1 << 16)       /* Use LPIB as default */
566 #define AZX_DCAPS_POSFIX_VIA    (1 << 17)       /* Use VIACOMBO as default */
567 #define AZX_DCAPS_NO_64BIT      (1 << 18)       /* No 64bit address */
568 #define AZX_DCAPS_SYNC_WRITE    (1 << 19)       /* sync each cmd write */
569 #define AZX_DCAPS_OLD_SSYNC     (1 << 20)       /* Old SSYNC reg for ICH */
570 #define AZX_DCAPS_BUFSIZE       (1 << 21)       /* no buffer size alignment */
571 #define AZX_DCAPS_ALIGN_BUFSIZE (1 << 22)       /* buffer size alignment */
572
573 /* quirks for ATI SB / AMD Hudson */
574 #define AZX_DCAPS_PRESET_ATI_SB \
575         (AZX_DCAPS_ATI_SNOOP | AZX_DCAPS_NO_TCSEL | \
576          AZX_DCAPS_SYNC_WRITE | AZX_DCAPS_POSFIX_LPIB)
577
578 /* quirks for ATI/AMD HDMI */
579 #define AZX_DCAPS_PRESET_ATI_HDMI \
580         (AZX_DCAPS_NO_TCSEL | AZX_DCAPS_SYNC_WRITE | AZX_DCAPS_POSFIX_LPIB)
581
582 /* quirks for Nvidia */
583 #define AZX_DCAPS_PRESET_NVIDIA \
584         (AZX_DCAPS_NVIDIA_SNOOP | AZX_DCAPS_RIRB_DELAY | AZX_DCAPS_NO_MSI |\
585          AZX_DCAPS_ALIGN_BUFSIZE)
586
587 static char *driver_short_names[] __devinitdata = {
588         [AZX_DRIVER_ICH] = "HDA Intel",
589         [AZX_DRIVER_PCH] = "HDA Intel PCH",
590         [AZX_DRIVER_SCH] = "HDA Intel MID",
591         [AZX_DRIVER_ATI] = "HDA ATI SB",
592         [AZX_DRIVER_ATIHDMI] = "HDA ATI HDMI",
593         [AZX_DRIVER_ATIHDMI_NS] = "HDA ATI HDMI",
594         [AZX_DRIVER_VIA] = "HDA VIA VT82xx",
595         [AZX_DRIVER_SIS] = "HDA SIS966",
596         [AZX_DRIVER_ULI] = "HDA ULI M5461",
597         [AZX_DRIVER_NVIDIA] = "HDA NVidia",
598         [AZX_DRIVER_NVIDIA_TEGRA] = "HDA NVIDIA Tegra",
599         [AZX_DRIVER_TERA] = "HDA Teradici",
600         [AZX_DRIVER_CTX] = "HDA Creative",
601         [AZX_DRIVER_GENERIC] = "HD-Audio Generic",
602 };
603
604 /*
605  * macros for easy use
606  */
607 #ifdef CONFIG_SND_HDA_PLATFORM_NVIDIA_TEGRA
608 #define MASK_LONG_ALIGN         0x3UL
609 #define SHIFT_BYTE              3
610 #define SHIFT_BITS(reg)         ((reg & MASK_LONG_ALIGN) << SHIFT_BYTE)
611 #define ADDR_ALIGN_L(base, reg) (base + (reg & ~MASK_LONG_ALIGN))
612 #define MASK(bits)              (BIT(bits) - 1)
613 #define MASK_REG(reg, bits)     (MASK(bits) << SHIFT_BITS(reg))
614
615 #define tegra_write(base, reg, val, bits) \
616         writel((readl(ADDR_ALIGN_L(base, reg)) & ~MASK_REG(reg, bits)) | \
617                ((val) << SHIFT_BITS(reg)), ADDR_ALIGN_L(base, reg))
618
619 #define tegra_read(base, reg, bits) \
620         ((readl(ADDR_ALIGN_L(base, reg)) >> SHIFT_BITS(reg)) & MASK(bits))
621
622 #define azx_writel(chip, reg, value) \
623         writel(value, (chip)->remap_addr + ICH6_REG_##reg)
624 #define azx_readl(chip, reg) \
625         readl((chip)->remap_addr + ICH6_REG_##reg)
626 #define azx_writew(chip, reg, value) \
627         tegra_write((chip)->remap_addr, ICH6_REG_##reg, value, 16)
628 #define azx_readw(chip, reg) \
629         tegra_read((chip)->remap_addr, ICH6_REG_##reg, 16)
630 #define azx_writeb(chip, reg, value) \
631         tegra_write((chip)->remap_addr, ICH6_REG_##reg, value, 8)
632 #define azx_readb(chip, reg) \
633         tegra_read((chip)->remap_addr, ICH6_REG_##reg, 8)
634
635 #define azx_sd_writel(dev, reg, value) \
636         writel(value, (dev)->sd_addr + ICH6_REG_##reg)
637 #define azx_sd_readl(dev, reg) \
638         readl((dev)->sd_addr + ICH6_REG_##reg)
639 #define azx_sd_writew(dev, reg, value) \
640         tegra_write((dev)->sd_addr, ICH6_REG_##reg, value, 16)
641 #define azx_sd_readw(dev, reg) \
642         tegra_read((dev)->sd_addr, ICH6_REG_##reg, 16)
643 #define azx_sd_writeb(dev, reg, value) \
644         tegra_write((dev)->sd_addr, ICH6_REG_##reg, value, 8)
645 #define azx_sd_readb(dev, reg) \
646         tegra_read((dev)->sd_addr, ICH6_REG_##reg, 8)
647
648 #else /* CONFIG_SND_HDA_PLATFORM_NVIDIA_TEGRA */
649 #define azx_writel(chip,reg,value) \
650         writel(value, (chip)->remap_addr + ICH6_REG_##reg)
651 #define azx_readl(chip,reg) \
652         readl((chip)->remap_addr + ICH6_REG_##reg)
653 #define azx_writew(chip,reg,value) \
654         writew(value, (chip)->remap_addr + ICH6_REG_##reg)
655 #define azx_readw(chip,reg) \
656         readw((chip)->remap_addr + ICH6_REG_##reg)
657 #define azx_writeb(chip,reg,value) \
658         writeb(value, (chip)->remap_addr + ICH6_REG_##reg)
659 #define azx_readb(chip,reg) \
660         readb((chip)->remap_addr + ICH6_REG_##reg)
661
662 #define azx_sd_writel(dev,reg,value) \
663         writel(value, (dev)->sd_addr + ICH6_REG_##reg)
664 #define azx_sd_readl(dev,reg) \
665         readl((dev)->sd_addr + ICH6_REG_##reg)
666 #define azx_sd_writew(dev,reg,value) \
667         writew(value, (dev)->sd_addr + ICH6_REG_##reg)
668 #define azx_sd_readw(dev,reg) \
669         readw((dev)->sd_addr + ICH6_REG_##reg)
670 #define azx_sd_writeb(dev,reg,value) \
671         writeb(value, (dev)->sd_addr + ICH6_REG_##reg)
672 #define azx_sd_readb(dev,reg) \
673         readb((dev)->sd_addr + ICH6_REG_##reg)
674
675 #endif /* CONFIG_SND_HDA_PLATFORM_NVIDIA_TEGRA */
676
677 /* for pcm support */
678 #define get_azx_dev(substream) (substream->runtime->private_data)
679
680 #ifdef CONFIG_X86
681 static void __mark_pages_wc(struct azx *chip, void *addr, size_t size, bool on)
682 {
683         if (azx_snoop(chip))
684                 return;
685         if (addr && size) {
686                 int pages = (size + PAGE_SIZE - 1) >> PAGE_SHIFT;
687                 if (on)
688                         set_memory_wc((unsigned long)addr, pages);
689                 else
690                         set_memory_wb((unsigned long)addr, pages);
691         }
692 }
693
694 static inline void mark_pages_wc(struct azx *chip, struct snd_dma_buffer *buf,
695                                  bool on)
696 {
697         __mark_pages_wc(chip, buf->area, buf->bytes, on);
698 }
699 static inline void mark_runtime_wc(struct azx *chip, struct azx_dev *azx_dev,
700                                    struct snd_pcm_runtime *runtime, bool on)
701 {
702         if (azx_dev->wc_marked != on) {
703                 __mark_pages_wc(chip, runtime->dma_area, runtime->dma_bytes, on);
704                 azx_dev->wc_marked = on;
705         }
706 }
707 #else
708 /* NOP for other archs */
709 static inline void mark_pages_wc(struct azx *chip, struct snd_dma_buffer *buf,
710                                  bool on)
711 {
712 }
713 static inline void mark_runtime_wc(struct azx *chip, struct azx_dev *azx_dev,
714                                    struct snd_pcm_runtime *runtime, bool on)
715 {
716 }
717 #endif
718
719 static int azx_acquire_irq(struct azx *chip, int do_disconnect);
720 static int azx_send_cmd(struct hda_bus *bus, unsigned int val);
721 /*
722  * Interface for HD codec
723  */
724
725 /*
726  * CORB / RIRB interface
727  */
728 static int azx_alloc_cmd_io(struct azx *chip)
729 {
730         int err;
731
732         /* single page (at least 4096 bytes) must suffice for both ringbuffes */
733         err = snd_dma_alloc_pages(SNDRV_DMA_TYPE_DEV,
734                                   chip->dev,
735                                   PAGE_SIZE, &chip->rb);
736         if (err < 0) {
737                 snd_printk(KERN_ERR SFX "cannot allocate CORB/RIRB\n");
738                 return err;
739         }
740         mark_pages_wc(chip, &chip->rb, true);
741         return 0;
742 }
743
744 static void azx_init_cmd_io(struct azx *chip)
745 {
746         spin_lock_irq(&chip->reg_lock);
747         /* CORB set up */
748         chip->corb.addr = chip->rb.addr;
749         chip->corb.buf = (u32 *)chip->rb.area;
750         azx_writel(chip, CORBLBASE, (u32)chip->corb.addr);
751         azx_writel(chip, CORBUBASE, upper_32_bits(chip->corb.addr));
752
753         /* set the corb size to 256 entries (ULI requires explicitly) */
754         azx_writeb(chip, CORBSIZE, 0x02);
755         /* set the corb write pointer to 0 */
756         azx_writew(chip, CORBWP, 0);
757         /* reset the corb hw read pointer */
758         azx_writew(chip, CORBRP, ICH6_CORBRP_RST);
759         /* enable corb dma */
760         azx_writeb(chip, CORBCTL, ICH6_CORBCTL_RUN);
761
762         /* RIRB set up */
763         chip->rirb.addr = chip->rb.addr + 2048;
764         chip->rirb.buf = (u32 *)(chip->rb.area + 2048);
765         chip->rirb.wp = chip->rirb.rp = 0;
766         memset(chip->rirb.cmds, 0, sizeof(chip->rirb.cmds));
767         azx_writel(chip, RIRBLBASE, (u32)chip->rirb.addr);
768         azx_writel(chip, RIRBUBASE, upper_32_bits(chip->rirb.addr));
769
770         /* set the rirb size to 256 entries (ULI requires explicitly) */
771         azx_writeb(chip, RIRBSIZE, 0x02);
772         /* reset the rirb hw write pointer */
773         azx_writew(chip, RIRBWP, ICH6_RIRBWP_RST);
774         /* set N=1, get RIRB response interrupt for new entry */
775         if (chip->driver_caps & AZX_DCAPS_CTX_WORKAROUND)
776                 azx_writew(chip, RINTCNT, 0xc0);
777         else
778                 azx_writew(chip, RINTCNT, 1);
779         /* enable rirb dma and response irq */
780         azx_writeb(chip, RIRBCTL, ICH6_RBCTL_DMA_EN | ICH6_RBCTL_IRQ_EN);
781         spin_unlock_irq(&chip->reg_lock);
782 }
783
784 static void azx_free_cmd_io(struct azx *chip)
785 {
786         spin_lock_irq(&chip->reg_lock);
787         /* disable ringbuffer DMAs */
788         azx_writeb(chip, RIRBCTL, 0);
789         azx_writeb(chip, CORBCTL, 0);
790         spin_unlock_irq(&chip->reg_lock);
791 }
792
793 static unsigned int azx_command_addr(u32 cmd)
794 {
795         unsigned int addr = cmd >> 28;
796
797         if (addr >= AZX_MAX_CODECS) {
798                 snd_BUG();
799                 addr = 0;
800         }
801
802         return addr;
803 }
804
805 static unsigned int azx_response_addr(u32 res)
806 {
807         unsigned int addr = res & 0xf;
808
809         if (addr >= AZX_MAX_CODECS) {
810                 snd_BUG();
811                 addr = 0;
812         }
813
814         return addr;
815 }
816
817 /* send a command */
818 static int azx_corb_send_cmd(struct hda_bus *bus, u32 val)
819 {
820         struct azx *chip = bus->private_data;
821         unsigned int addr = azx_command_addr(val);
822         unsigned int wp;
823
824         spin_lock_irq(&chip->reg_lock);
825
826         /* add command to corb */
827         wp = azx_readb(chip, CORBWP);
828         wp++;
829         wp %= ICH6_MAX_CORB_ENTRIES;
830
831         chip->rirb.cmds[addr]++;
832         chip->corb.buf[wp] = cpu_to_le32(val);
833         azx_writel(chip, CORBWP, wp);
834
835         spin_unlock_irq(&chip->reg_lock);
836
837         return 0;
838 }
839
840 #define ICH6_RIRB_EX_UNSOL_EV   (1<<4)
841
842 /* retrieve RIRB entry - called from interrupt handler */
843 static void azx_update_rirb(struct azx *chip)
844 {
845         unsigned int rp, wp;
846         unsigned int addr;
847         u32 res, res_ex;
848
849         wp = azx_readb(chip, RIRBWP);
850         if (wp == chip->rirb.wp)
851                 return;
852         chip->rirb.wp = wp;
853
854         while (chip->rirb.rp != wp) {
855                 chip->rirb.rp++;
856                 chip->rirb.rp %= ICH6_MAX_RIRB_ENTRIES;
857
858                 rp = chip->rirb.rp << 1; /* an RIRB entry is 8-bytes */
859                 res_ex = le32_to_cpu(chip->rirb.buf[rp + 1]);
860                 res = le32_to_cpu(chip->rirb.buf[rp]);
861                 addr = azx_response_addr(res_ex);
862                 if (res_ex & ICH6_RIRB_EX_UNSOL_EV)
863                         snd_hda_queue_unsol_event(chip->bus, res, res_ex);
864                 else if (chip->rirb.cmds[addr]) {
865                         chip->rirb.res[addr] = res;
866                         smp_wmb();
867                         chip->rirb.cmds[addr]--;
868                 } else
869                         snd_printk(KERN_ERR SFX "spurious response %#x:%#x, "
870                                    "last cmd=%#08x\n",
871                                    res, res_ex,
872                                    chip->last_cmd[addr]);
873         }
874 }
875
876 /* receive a response */
877 static unsigned int azx_rirb_get_response(struct hda_bus *bus,
878                                           unsigned int addr)
879 {
880         struct azx *chip = bus->private_data;
881         unsigned long timeout;
882         unsigned long loopcounter;
883         int do_poll = 0;
884
885  again:
886         timeout = jiffies + msecs_to_jiffies(1000);
887
888         for (loopcounter = 0;; loopcounter++) {
889                 if (chip->polling_mode || do_poll) {
890                         spin_lock_irq(&chip->reg_lock);
891                         azx_update_rirb(chip);
892                         spin_unlock_irq(&chip->reg_lock);
893                 }
894                 if (!chip->rirb.cmds[addr]) {
895                         smp_rmb();
896                         bus->rirb_error = 0;
897
898                         if (!do_poll)
899                                 chip->poll_count = 0;
900                         return chip->rirb.res[addr]; /* the last value */
901                 }
902                 if (time_after(jiffies, timeout))
903                         break;
904                 if (bus->needs_damn_long_delay || loopcounter > 3000)
905                         msleep(2); /* temporary workaround */
906                 else {
907                         udelay(10);
908                         cond_resched();
909                 }
910         }
911
912         if (!chip->polling_mode && chip->poll_count < 2) {
913                 snd_printdd(SFX "azx_get_response timeout, "
914                            "polling the codec once: last cmd=0x%08x\n",
915                            chip->last_cmd[addr]);
916                 do_poll = 1;
917                 chip->poll_count++;
918                 goto again;
919         }
920
921
922         if (!chip->polling_mode) {
923                 snd_printk(KERN_WARNING SFX "azx_get_response timeout, "
924                            "switching to polling mode: last cmd=0x%08x\n",
925                            chip->last_cmd[addr]);
926                 chip->polling_mode = 1;
927                 goto again;
928         }
929
930         if (chip->msi) {
931                 snd_printk(KERN_WARNING SFX "No response from codec, "
932                            "disabling MSI: last cmd=0x%08x\n",
933                            chip->last_cmd[addr]);
934                 free_irq(chip->irq, chip);
935                 chip->irq = -1;
936                 pci_disable_msi(chip->pci);
937                 chip->msi = 0;
938                 if (azx_acquire_irq(chip, 1) < 0) {
939                         bus->rirb_error = 1;
940                         return -1;
941                 }
942                 goto again;
943         }
944
945         if (chip->probing) {
946                 /* If this critical timeout happens during the codec probing
947                  * phase, this is likely an access to a non-existing codec
948                  * slot.  Better to return an error and reset the system.
949                  */
950                 return -1;
951         }
952
953         /* a fatal communication error; need either to reset or to fallback
954          * to the single_cmd mode
955          */
956         bus->rirb_error = 1;
957         if (bus->allow_bus_reset && !bus->response_reset && !bus->in_reset) {
958                 bus->response_reset = 1;
959                 return -1; /* give a chance to retry */
960         }
961
962         snd_printk(KERN_ERR "hda_intel: azx_get_response timeout, "
963                    "switching to single_cmd mode: last cmd=0x%08x\n",
964                    chip->last_cmd[addr]);
965         chip->single_cmd = 1;
966         bus->response_reset = 0;
967         /* release CORB/RIRB */
968         azx_free_cmd_io(chip);
969         /* disable unsolicited responses */
970         azx_writel(chip, GCTL, azx_readl(chip, GCTL) & ~ICH6_GCTL_UNSOL);
971         return -1;
972 }
973
974 /*
975  * Use the single immediate command instead of CORB/RIRB for simplicity
976  *
977  * Note: according to Intel, this is not preferred use.  The command was
978  *       intended for the BIOS only, and may get confused with unsolicited
979  *       responses.  So, we shouldn't use it for normal operation from the
980  *       driver.
981  *       I left the codes, however, for debugging/testing purposes.
982  */
983
984 /* receive a response */
985 static int azx_single_wait_for_response(struct azx *chip, unsigned int addr)
986 {
987         int timeout = 50;
988
989         while (timeout--) {
990                 /* check IRV busy bit */
991                 if (azx_readw(chip, IRS) & ICH6_IRS_VALID) {
992                         /* reuse rirb.res as the response return value */
993                         chip->rirb.res[addr] = azx_readl(chip, IR);
994                         return 0;
995                 }
996                 udelay(1);
997         }
998         if (printk_ratelimit())
999                 snd_printd(SFX "get_response timeout: IRS=0x%x\n",
1000                            azx_readw(chip, IRS));
1001         chip->rirb.res[addr] = -1;
1002         return -EIO;
1003 }
1004
1005 /* send a command */
1006 static int azx_single_send_cmd(struct hda_bus *bus, u32 val)
1007 {
1008         struct azx *chip = bus->private_data;
1009         unsigned int addr = azx_command_addr(val);
1010         int timeout = 50;
1011
1012         bus->rirb_error = 0;
1013         while (timeout--) {
1014                 /* check ICB busy bit */
1015                 if (!((azx_readw(chip, IRS) & ICH6_IRS_BUSY))) {
1016                         /* Clear IRV valid bit */
1017                         azx_writew(chip, IRS, azx_readw(chip, IRS) |
1018                                    ICH6_IRS_VALID);
1019                         azx_writel(chip, IC, val);
1020                         azx_writew(chip, IRS, azx_readw(chip, IRS) |
1021                                    ICH6_IRS_BUSY);
1022                         return azx_single_wait_for_response(chip, addr);
1023                 }
1024                 udelay(1);
1025         }
1026         if (printk_ratelimit())
1027                 snd_printd(SFX "send_cmd timeout: IRS=0x%x, val=0x%x\n",
1028                            azx_readw(chip, IRS), val);
1029         return -EIO;
1030 }
1031
1032 /* receive a response */
1033 static unsigned int azx_single_get_response(struct hda_bus *bus,
1034                                             unsigned int addr)
1035 {
1036         struct azx *chip = bus->private_data;
1037         return chip->rirb.res[addr];
1038 }
1039
1040 /*
1041  * The below are the main callbacks from hda_codec.
1042  *
1043  * They are just the skeleton to call sub-callbacks according to the
1044  * current setting of chip->single_cmd.
1045  */
1046
1047 /* send a command */
1048 static int azx_send_cmd(struct hda_bus *bus, unsigned int val)
1049 {
1050         struct azx *chip = bus->private_data;
1051
1052         chip->last_cmd[azx_command_addr(val)] = val;
1053         if (chip->single_cmd)
1054                 return azx_single_send_cmd(bus, val);
1055         else
1056                 return azx_corb_send_cmd(bus, val);
1057 }
1058
1059 /* get a response */
1060 static unsigned int azx_get_response(struct hda_bus *bus,
1061                                      unsigned int addr)
1062 {
1063         struct azx *chip = bus->private_data;
1064         if (chip->single_cmd)
1065                 return azx_single_get_response(bus, addr);
1066         else
1067                 return azx_rirb_get_response(bus, addr);
1068 }
1069
1070 #ifdef CONFIG_SND_HDA_POWER_SAVE
1071 static void azx_power_notify(struct hda_bus *bus);
1072 #endif
1073
1074 /* reset codec link */
1075 static int azx_reset(struct azx *chip, int full_reset)
1076 {
1077         int count;
1078
1079         if (!full_reset)
1080                 goto __skip;
1081
1082         /* clear STATESTS */
1083         azx_writeb(chip, STATESTS, STATESTS_INT_MASK);
1084
1085         /* reset controller */
1086         azx_writel(chip, GCTL, azx_readl(chip, GCTL) & ~ICH6_GCTL_RESET);
1087
1088         count = 50;
1089         while (azx_readb(chip, GCTL) && --count)
1090                 mdelay(1);
1091
1092         /* delay for >= 100us for codec PLL to settle per spec
1093          * Rev 0.9 section 5.5.1
1094          */
1095         mdelay(1);
1096
1097         /* Bring controller out of reset */
1098         azx_writeb(chip, GCTL, azx_readb(chip, GCTL) | ICH6_GCTL_RESET);
1099
1100         count = 50;
1101         while (!azx_readb(chip, GCTL) && --count)
1102                 mdelay(1);
1103
1104         /* Brent Chartrand said to wait >= 540us for codecs to initialize */
1105         mdelay(1);
1106
1107       __skip:
1108         /* check to see if controller is ready */
1109         if (!azx_readb(chip, GCTL)) {
1110                 snd_printd(SFX "azx_reset: controller not ready!\n");
1111                 return -EBUSY;
1112         }
1113
1114         /* Accept unsolicited responses */
1115         if (!chip->single_cmd)
1116                 azx_writel(chip, GCTL, azx_readl(chip, GCTL) |
1117                            ICH6_GCTL_UNSOL);
1118
1119         /* detect codecs */
1120         if (!chip->codec_mask) {
1121                 chip->codec_mask = azx_readw(chip, STATESTS);
1122                 snd_printdd(SFX "codec_mask = 0x%x\n", chip->codec_mask);
1123         }
1124
1125         return 0;
1126 }
1127
1128
1129 /*
1130  * Lowlevel interface
1131  */
1132
1133 /* enable interrupts */
1134 static void azx_int_enable(struct azx *chip)
1135 {
1136         /* enable controller CIE and GIE */
1137         azx_writel(chip, INTCTL, azx_readl(chip, INTCTL) |
1138                    ICH6_INT_CTRL_EN | ICH6_INT_GLOBAL_EN);
1139 }
1140
1141 /* disable interrupts */
1142 static void azx_int_disable(struct azx *chip)
1143 {
1144         int i;
1145
1146         /* disable interrupts in stream descriptor */
1147         for (i = 0; i < chip->num_streams; i++) {
1148                 struct azx_dev *azx_dev = &chip->azx_dev[i];
1149                 azx_sd_writeb(azx_dev, SD_CTL,
1150                               azx_sd_readb(azx_dev, SD_CTL) & ~SD_INT_MASK);
1151         }
1152
1153         /* disable SIE for all streams */
1154         azx_writeb(chip, INTCTL, 0);
1155
1156         /* disable controller CIE and GIE */
1157         azx_writel(chip, INTCTL, azx_readl(chip, INTCTL) &
1158                    ~(ICH6_INT_CTRL_EN | ICH6_INT_GLOBAL_EN));
1159 }
1160
1161 /* clear interrupts */
1162 static void azx_int_clear(struct azx *chip)
1163 {
1164         int i;
1165
1166         /* clear stream status */
1167         for (i = 0; i < chip->num_streams; i++) {
1168                 struct azx_dev *azx_dev = &chip->azx_dev[i];
1169                 azx_sd_writeb(azx_dev, SD_STS, SD_INT_MASK);
1170         }
1171
1172         /* clear STATESTS */
1173         azx_writeb(chip, STATESTS, STATESTS_INT_MASK);
1174
1175         /* clear rirb status */
1176         azx_writeb(chip, RIRBSTS, RIRB_INT_MASK);
1177
1178         /* clear int status */
1179         azx_writel(chip, INTSTS, ICH6_INT_CTRL_EN | ICH6_INT_ALL_STREAM);
1180 }
1181
1182 /* start a stream */
1183 static void azx_stream_start(struct azx *chip, struct azx_dev *azx_dev)
1184 {
1185         /*
1186          * Before stream start, initialize parameter
1187          */
1188         azx_dev->insufficient = 1;
1189
1190         /* enable SIE */
1191         azx_writel(chip, INTCTL,
1192                    azx_readl(chip, INTCTL) | (1 << azx_dev->index));
1193         /* set DMA start and interrupt mask */
1194         azx_sd_writeb(azx_dev, SD_CTL, azx_sd_readb(azx_dev, SD_CTL) |
1195                       SD_CTL_DMA_START | SD_INT_MASK);
1196 }
1197
1198 /* stop DMA */
1199 static void azx_stream_clear(struct azx *chip, struct azx_dev *azx_dev)
1200 {
1201         azx_sd_writeb(azx_dev, SD_CTL, azx_sd_readb(azx_dev, SD_CTL) &
1202                       ~(SD_CTL_DMA_START | SD_INT_MASK));
1203         azx_sd_writeb(azx_dev, SD_STS, SD_INT_MASK); /* to be sure */
1204 }
1205
1206 /* stop a stream */
1207 static void azx_stream_stop(struct azx *chip, struct azx_dev *azx_dev)
1208 {
1209         azx_stream_clear(chip, azx_dev);
1210         /* disable SIE */
1211         azx_writel(chip, INTCTL,
1212                    azx_readl(chip, INTCTL) & ~(1 << azx_dev->index));
1213 }
1214
1215
1216 /*
1217  * reset and start the controller registers
1218  */
1219 static void azx_init_chip(struct azx *chip, int full_reset)
1220 {
1221         if (chip->initialized)
1222                 return;
1223
1224         /* reset controller */
1225         azx_reset(chip, full_reset);
1226
1227         /* initialize interrupts */
1228         azx_int_clear(chip);
1229         azx_int_enable(chip);
1230
1231         /* initialize the codec command I/O */
1232         if (!chip->single_cmd)
1233                 azx_init_cmd_io(chip);
1234
1235         /* program the position buffer */
1236         azx_writel(chip, DPLBASE, (u32)chip->posbuf.addr);
1237         azx_writel(chip, DPUBASE, upper_32_bits(chip->posbuf.addr));
1238
1239         chip->initialized = 1;
1240 }
1241
1242 /*
1243  * initialize the PCI registers
1244  */
1245 /* update bits in a PCI register byte */
1246 static void update_pci_byte(struct pci_dev *pci, unsigned int reg,
1247                             unsigned char mask, unsigned char val)
1248 {
1249         unsigned char data;
1250
1251         pci_read_config_byte(pci, reg, &data);
1252         data &= ~mask;
1253         data |= (val & mask);
1254         pci_write_config_byte(pci, reg, data);
1255 }
1256
1257 static void azx_init_pci(struct azx *chip)
1258 {
1259         /* Clear bits 0-2 of PCI register TCSEL (at offset 0x44)
1260          * TCSEL == Traffic Class Select Register, which sets PCI express QOS
1261          * Ensuring these bits are 0 clears playback static on some HD Audio
1262          * codecs.
1263          * The PCI register TCSEL is defined in the Intel manuals.
1264          */
1265         if (!(chip->driver_caps & AZX_DCAPS_NO_TCSEL)) {
1266                 snd_printdd(SFX "Clearing TCSEL\n");
1267                 update_pci_byte(chip->pci, ICH6_PCIREG_TCSEL, 0x07, 0);
1268         }
1269
1270         /* For ATI SB450/600/700/800/900 and AMD Hudson azalia HD audio,
1271          * we need to enable snoop.
1272          */
1273         if (chip->driver_caps & AZX_DCAPS_ATI_SNOOP) {
1274                 snd_printdd(SFX "Setting ATI snoop: %d\n", azx_snoop(chip));
1275                 update_pci_byte(chip->pci,
1276                                 ATI_SB450_HDAUDIO_MISC_CNTR2_ADDR, 0x07,
1277                                 azx_snoop(chip) ? ATI_SB450_HDAUDIO_ENABLE_SNOOP : 0);
1278         }
1279
1280         /* For NVIDIA HDA, enable snoop */
1281         if (chip->driver_caps & AZX_DCAPS_NVIDIA_SNOOP) {
1282                 snd_printdd(SFX "Setting Nvidia snoop: %d\n", azx_snoop(chip));
1283                 update_pci_byte(chip->pci,
1284                                 NVIDIA_HDA_TRANSREG_ADDR,
1285                                 0x0f, NVIDIA_HDA_ENABLE_COHBITS);
1286                 update_pci_byte(chip->pci,
1287                                 NVIDIA_HDA_ISTRM_COH,
1288                                 0x01, NVIDIA_HDA_ENABLE_COHBIT);
1289                 update_pci_byte(chip->pci,
1290                                 NVIDIA_HDA_OSTRM_COH,
1291                                 0x01, NVIDIA_HDA_ENABLE_COHBIT);
1292         }
1293
1294         /* Enable SCH/PCH snoop if needed */
1295         if (chip->driver_caps & AZX_DCAPS_SCH_SNOOP) {
1296                 unsigned short snoop;
1297                 pci_read_config_word(chip->pci, INTEL_SCH_HDA_DEVC, &snoop);
1298                 if ((!azx_snoop(chip) && !(snoop & INTEL_SCH_HDA_DEVC_NOSNOOP)) ||
1299                     (azx_snoop(chip) && (snoop & INTEL_SCH_HDA_DEVC_NOSNOOP))) {
1300                         snoop &= ~INTEL_SCH_HDA_DEVC_NOSNOOP;
1301                         if (!azx_snoop(chip))
1302                                 snoop |= INTEL_SCH_HDA_DEVC_NOSNOOP;
1303                         pci_write_config_word(chip->pci, INTEL_SCH_HDA_DEVC, snoop);
1304                         pci_read_config_word(chip->pci,
1305                                 INTEL_SCH_HDA_DEVC, &snoop);
1306                 }
1307                 snd_printdd(SFX "SCH snoop: %s\n",
1308                                 (snoop & INTEL_SCH_HDA_DEVC_NOSNOOP)
1309                                 ? "Disabled" : "Enabled");
1310         }
1311 }
1312
1313 #ifdef CONFIG_SND_HDA_PLATFORM_DRIVER
1314 /*
1315  * initialize the platform specific registers
1316  */
1317 static void reg_update_bits(void __iomem *base, unsigned int reg,
1318                             unsigned int mask, unsigned int val)
1319 {
1320         unsigned int data;
1321
1322         data = readl(base + reg);
1323         data &= ~mask;
1324         data |= (val & mask);
1325         writel(data, base + reg);
1326 }
1327
1328 static void azx_init_platform(struct azx *chip)
1329 {
1330         switch (chip->driver_type) {
1331 #ifdef CONFIG_SND_HDA_PLATFORM_NVIDIA_TEGRA
1332         case AZX_DRIVER_NVIDIA_TEGRA:
1333                 /*Enable the PCI access */
1334                 reg_update_bits(chip->remap_config_addr,
1335                                 NVIDIA_TEGRA_HDA_IPFS_CONFIG,
1336                                 NVIDIA_TEGRA_HDA_IPFS_EN_FPCI,
1337                                 NVIDIA_TEGRA_HDA_IPFS_EN_FPCI);
1338                 /* Enable MEM/IO space and bus master */
1339                 reg_update_bits(chip->remap_config_addr,
1340                                 NVIDIA_TEGRA_HDA_CFG_CMD_OFFSET, 0x507,
1341                                 NVIDIA_TEGRA_HDA_ENABLE_MEM_SPACE |
1342                                 NVIDIA_TEGRA_HDA_ENABLE_IO_SPACE |
1343                                 NVIDIA_TEGRA_HDA_ENABLE_BUS_MASTER |
1344                                 NVIDIA_TEGRA_HDA_ENABLE_SERR);
1345                 reg_update_bits(chip->remap_config_addr,
1346                                 NVIDIA_TEGRA_HDA_CFG_BAR0_OFFSET, 0xFFFFFFFF,
1347                                 NVIDIA_TEGRA_HDA_BAR0_INIT_PROGRAM);
1348                 reg_update_bits(chip->remap_config_addr,
1349                                 NVIDIA_TEGRA_HDA_CFG_BAR0_OFFSET, 0xFFFFFFFF,
1350                                 NVIDIA_TEGRA_HDA_BAR0_FINAL_PROGRAM);
1351                 reg_update_bits(chip->remap_config_addr,
1352                                 NVIDIA_TEGRA_HDA_IPFS_FPCI_BAR0, 0xFFFFFFFF,
1353                                 NVIDIA_TEGRA_HDA_FPCI_BAR0_START);
1354                 reg_update_bits(chip->remap_config_addr,
1355                                 NVIDIA_TEGRA_HDA_IPFS_INTR_MASK,
1356                                 NVIDIA_TEGRA_HDA_IPFS_EN_INTR,
1357                                 NVIDIA_TEGRA_HDA_IPFS_EN_INTR);
1358                 break;
1359 #endif
1360         default:
1361                 break;
1362         }
1363
1364         return;
1365 }
1366
1367 static void azx_platform_enable_clocks(struct azx *chip)
1368 {
1369         int i;
1370
1371         for (i = 0; i < chip->platform_clk_count; i++)
1372                 clk_enable(chip->platform_clks[i]);
1373
1374         chip->platform_clk_enable++;
1375 }
1376
1377 static void azx_platform_disable_clocks(struct azx *chip)
1378 {
1379         int i;
1380
1381         if (!chip->platform_clk_enable)
1382                 return;
1383
1384         for (i = 0; i < chip->platform_clk_count; i++)
1385                 clk_disable(chip->platform_clks[i]);
1386
1387         chip->platform_clk_enable--;
1388 }
1389 #endif /* CONFIG_SND_HDA_PLATFORM_DRIVER */
1390
1391 static int azx_position_ok(struct azx *chip, struct azx_dev *azx_dev);
1392
1393 /*
1394  * interrupt handler
1395  */
1396 static irqreturn_t azx_interrupt(int irq, void *dev_id)
1397 {
1398         struct azx *chip = dev_id;
1399         struct azx_dev *azx_dev;
1400         u32 status;
1401         u8 sd_status;
1402         int i, ok;
1403
1404         spin_lock(&chip->reg_lock);
1405
1406         status = azx_readl(chip, INTSTS);
1407         if (status == 0) {
1408                 spin_unlock(&chip->reg_lock);
1409                 return IRQ_NONE;
1410         }
1411
1412         for (i = 0; i < chip->num_streams; i++) {
1413                 azx_dev = &chip->azx_dev[i];
1414                 if (status & azx_dev->sd_int_sta_mask) {
1415                         sd_status = azx_sd_readb(azx_dev, SD_STS);
1416                         azx_sd_writeb(azx_dev, SD_STS, SD_INT_MASK);
1417                         if (!azx_dev->substream || !azx_dev->running ||
1418                             !(sd_status & SD_INT_COMPLETE))
1419                                 continue;
1420                         /* check whether this IRQ is really acceptable */
1421                         ok = azx_position_ok(chip, azx_dev);
1422                         if (ok == 1) {
1423                                 azx_dev->irq_pending = 0;
1424                                 spin_unlock(&chip->reg_lock);
1425                                 snd_pcm_period_elapsed(azx_dev->substream);
1426                                 spin_lock(&chip->reg_lock);
1427                         } else if (ok == 0 && chip->bus && chip->bus->workq) {
1428                                 /* bogus IRQ, process it later */
1429                                 azx_dev->irq_pending = 1;
1430                                 queue_work(chip->bus->workq,
1431                                            &chip->irq_pending_work);
1432                         }
1433                 }
1434         }
1435
1436         /* clear rirb int */
1437         status = azx_readb(chip, RIRBSTS);
1438         if (status & RIRB_INT_MASK) {
1439                 if (status & RIRB_INT_RESPONSE) {
1440                         if (chip->driver_caps & AZX_DCAPS_RIRB_PRE_DELAY)
1441                                 udelay(80);
1442                         azx_update_rirb(chip);
1443                 }
1444                 azx_writeb(chip, RIRBSTS, RIRB_INT_MASK);
1445         }
1446
1447 #if 0
1448         /* clear state status int */
1449         if (azx_readb(chip, STATESTS) & 0x04)
1450                 azx_writeb(chip, STATESTS, 0x04);
1451 #endif
1452         spin_unlock(&chip->reg_lock);
1453
1454         return IRQ_HANDLED;
1455 }
1456
1457
1458 /*
1459  * set up a BDL entry
1460  */
1461 static int setup_bdle(struct snd_pcm_substream *substream,
1462                       struct azx_dev *azx_dev, u32 **bdlp,
1463                       int ofs, int size, int with_ioc)
1464 {
1465         u32 *bdl = *bdlp;
1466
1467         while (size > 0) {
1468                 dma_addr_t addr;
1469                 int chunk;
1470
1471                 if (azx_dev->frags >= AZX_MAX_BDL_ENTRIES)
1472                         return -EINVAL;
1473
1474                 addr = snd_pcm_sgbuf_get_addr(substream, ofs);
1475                 /* program the address field of the BDL entry */
1476                 bdl[0] = cpu_to_le32((u32)addr);
1477                 bdl[1] = cpu_to_le32(upper_32_bits(addr));
1478                 /* program the size field of the BDL entry */
1479                 chunk = snd_pcm_sgbuf_get_chunk_size(substream, ofs, size);
1480                 bdl[2] = cpu_to_le32(chunk);
1481                 /* program the IOC to enable interrupt
1482                  * only when the whole fragment is processed
1483                  */
1484                 size -= chunk;
1485                 bdl[3] = (size || !with_ioc) ? 0 : cpu_to_le32(0x01);
1486                 bdl += 4;
1487                 azx_dev->frags++;
1488                 ofs += chunk;
1489         }
1490         *bdlp = bdl;
1491         return ofs;
1492 }
1493
1494 /*
1495  * set up BDL entries
1496  */
1497 static int azx_setup_periods(struct azx *chip,
1498                              struct snd_pcm_substream *substream,
1499                              struct azx_dev *azx_dev)
1500 {
1501         u32 *bdl;
1502         int i, ofs, periods, period_bytes;
1503         int pos_adj;
1504
1505         /* reset BDL address */
1506         azx_sd_writel(azx_dev, SD_BDLPL, 0);
1507         azx_sd_writel(azx_dev, SD_BDLPU, 0);
1508
1509         period_bytes = azx_dev->period_bytes;
1510         periods = azx_dev->bufsize / period_bytes;
1511
1512         /* program the initial BDL entries */
1513         bdl = (u32 *)azx_dev->bdl.area;
1514         ofs = 0;
1515         azx_dev->frags = 0;
1516         pos_adj = bdl_pos_adj[chip->dev_index];
1517         if (pos_adj > 0) {
1518                 struct snd_pcm_runtime *runtime = substream->runtime;
1519                 int pos_align = pos_adj;
1520                 pos_adj = (pos_adj * runtime->rate + 47999) / 48000;
1521                 if (!pos_adj)
1522                         pos_adj = pos_align;
1523                 else
1524                         pos_adj = ((pos_adj + pos_align - 1) / pos_align) *
1525                                 pos_align;
1526                 pos_adj = frames_to_bytes(runtime, pos_adj);
1527                 if (pos_adj >= period_bytes) {
1528                         snd_printk(KERN_WARNING SFX "Too big adjustment %d\n",
1529                                    bdl_pos_adj[chip->dev_index]);
1530                         pos_adj = 0;
1531                 } else {
1532                         ofs = setup_bdle(substream, azx_dev,
1533                                          &bdl, ofs, pos_adj,
1534                                          !substream->runtime->no_period_wakeup);
1535                         if (ofs < 0)
1536                                 goto error;
1537                 }
1538         } else
1539                 pos_adj = 0;
1540         for (i = 0; i < periods; i++) {
1541                 if (i == periods - 1 && pos_adj)
1542                         ofs = setup_bdle(substream, azx_dev, &bdl, ofs,
1543                                          period_bytes - pos_adj, 0);
1544                 else
1545                         ofs = setup_bdle(substream, azx_dev, &bdl, ofs,
1546                                          period_bytes,
1547                                          !substream->runtime->no_period_wakeup);
1548                 if (ofs < 0)
1549                         goto error;
1550         }
1551         return 0;
1552
1553  error:
1554         snd_printk(KERN_ERR SFX "Too many BDL entries: buffer=%d, period=%d\n",
1555                    azx_dev->bufsize, period_bytes);
1556         return -EINVAL;
1557 }
1558
1559 /* reset stream */
1560 static void azx_stream_reset(struct azx *chip, struct azx_dev *azx_dev)
1561 {
1562         unsigned char val;
1563         int timeout;
1564
1565         azx_stream_clear(chip, azx_dev);
1566
1567         azx_sd_writeb(azx_dev, SD_CTL, azx_sd_readb(azx_dev, SD_CTL) |
1568                       SD_CTL_STREAM_RESET);
1569         udelay(3);
1570         timeout = 300;
1571         while (!((val = azx_sd_readb(azx_dev, SD_CTL)) & SD_CTL_STREAM_RESET) &&
1572                --timeout)
1573                 ;
1574         val &= ~SD_CTL_STREAM_RESET;
1575         azx_sd_writeb(azx_dev, SD_CTL, val);
1576         udelay(3);
1577
1578         timeout = 300;
1579         /* waiting for hardware to report that the stream is out of reset */
1580         while (((val = azx_sd_readb(azx_dev, SD_CTL)) & SD_CTL_STREAM_RESET) &&
1581                --timeout)
1582                 ;
1583
1584         /* reset first position - may not be synced with hw at this time */
1585         *azx_dev->posbuf = 0;
1586 }
1587
1588 /*
1589  * set up the SD for streaming
1590  */
1591 static int azx_setup_controller(struct azx *chip, struct azx_dev *azx_dev)
1592 {
1593         unsigned int val;
1594         /* make sure the run bit is zero for SD */
1595         azx_stream_clear(chip, azx_dev);
1596         /* program the stream_tag */
1597         val = azx_sd_readl(azx_dev, SD_CTL);
1598         val = (val & ~SD_CTL_STREAM_TAG_MASK) |
1599                 (azx_dev->stream_tag << SD_CTL_STREAM_TAG_SHIFT);
1600         if (!azx_snoop(chip))
1601                 val |= SD_CTL_TRAFFIC_PRIO;
1602         azx_sd_writel(azx_dev, SD_CTL, val);
1603
1604         /* program the length of samples in cyclic buffer */
1605         azx_sd_writel(azx_dev, SD_CBL, azx_dev->bufsize);
1606
1607         /* program the stream format */
1608         /* this value needs to be the same as the one programmed */
1609         azx_sd_writew(azx_dev, SD_FORMAT, azx_dev->format_val);
1610
1611         /* program the stream LVI (last valid index) of the BDL */
1612         azx_sd_writew(azx_dev, SD_LVI, azx_dev->frags - 1);
1613
1614         /* program the BDL address */
1615         /* lower BDL address */
1616         azx_sd_writel(azx_dev, SD_BDLPL, (u32)azx_dev->bdl.addr);
1617         /* upper BDL address */
1618         azx_sd_writel(azx_dev, SD_BDLPU, upper_32_bits(azx_dev->bdl.addr));
1619
1620         /* enable the position buffer */
1621         if (chip->position_fix[0] != POS_FIX_LPIB ||
1622             chip->position_fix[1] != POS_FIX_LPIB) {
1623                 if (!(azx_readl(chip, DPLBASE) & ICH6_DPLBASE_ENABLE))
1624                         azx_writel(chip, DPLBASE,
1625                                 (u32)chip->posbuf.addr | ICH6_DPLBASE_ENABLE);
1626         }
1627
1628         /* set the interrupt enable bits in the descriptor control register */
1629         azx_sd_writel(azx_dev, SD_CTL,
1630                       azx_sd_readl(azx_dev, SD_CTL) | SD_INT_MASK);
1631
1632         return 0;
1633 }
1634
1635 /*
1636  * Probe the given codec address
1637  */
1638 static int probe_codec(struct azx *chip, int addr)
1639 {
1640         unsigned int cmd = (addr << 28) | (AC_NODE_ROOT << 20) |
1641                 (AC_VERB_PARAMETERS << 8) | AC_PAR_VENDOR_ID;
1642         unsigned int res;
1643
1644         mutex_lock(&chip->bus->cmd_mutex);
1645         chip->probing = 1;
1646         azx_send_cmd(chip->bus, cmd);
1647         res = azx_get_response(chip->bus, addr);
1648         chip->probing = 0;
1649         mutex_unlock(&chip->bus->cmd_mutex);
1650         if (res == -1)
1651                 return -EIO;
1652         snd_printdd(SFX "codec #%d probed OK\n", addr);
1653         return 0;
1654 }
1655
1656 static int azx_attach_pcm_stream(struct hda_bus *bus, struct hda_codec *codec,
1657                                  struct hda_pcm *cpcm);
1658 static void azx_stop_chip(struct azx *chip);
1659
1660 static void azx_bus_reset(struct hda_bus *bus)
1661 {
1662         struct azx *chip = bus->private_data;
1663
1664         bus->in_reset = 1;
1665         azx_stop_chip(chip);
1666         azx_init_chip(chip, 1);
1667 #ifdef CONFIG_PM
1668         if (chip->initialized) {
1669                 struct azx_pcm *p;
1670                 list_for_each_entry(p, &chip->pcm_list, list)
1671                         snd_pcm_suspend_all(p->pcm);
1672                 snd_hda_suspend(chip->bus);
1673                 snd_hda_resume(chip->bus);
1674         }
1675 #endif
1676         bus->in_reset = 0;
1677 }
1678
1679 /*
1680  * Codec initialization
1681  */
1682
1683 /* number of codec slots for each chipset: 0 = default slots (i.e. 4) */
1684 static unsigned int azx_max_codecs[AZX_NUM_DRIVERS] __devinitdata = {
1685         [AZX_DRIVER_NVIDIA] = 8,
1686         [AZX_DRIVER_TERA] = 1,
1687 };
1688
1689 static int __devinit azx_codec_create(struct azx *chip, const char *model)
1690 {
1691         struct hda_bus_template bus_temp;
1692         int c, codecs, err;
1693         int max_slots;
1694
1695         memset(&bus_temp, 0, sizeof(bus_temp));
1696         bus_temp.private_data = chip;
1697         bus_temp.modelname = model;
1698         bus_temp.pci = chip->pci;
1699         bus_temp.pdev = chip->pdev;
1700         bus_temp.ops.command = azx_send_cmd;
1701         bus_temp.ops.get_response = azx_get_response;
1702         bus_temp.ops.attach_pcm = azx_attach_pcm_stream;
1703         bus_temp.ops.bus_reset = azx_bus_reset;
1704 #ifdef CONFIG_SND_HDA_POWER_SAVE
1705         bus_temp.power_save = &power_save;
1706         bus_temp.ops.pm_notify = azx_power_notify;
1707 #endif
1708
1709         err = snd_hda_bus_new(chip->card, &bus_temp, &chip->bus);
1710         if (err < 0)
1711                 return err;
1712
1713         if (chip->driver_caps & AZX_DCAPS_RIRB_DELAY) {
1714                 snd_printd(SFX "Enable delay in RIRB handling\n");
1715                 chip->bus->needs_damn_long_delay = 1;
1716         }
1717
1718         codecs = 0;
1719         max_slots = azx_max_codecs[chip->driver_type];
1720         if (!max_slots)
1721                 max_slots = AZX_DEFAULT_CODECS;
1722
1723         /* First try to probe all given codec slots */
1724         for (c = 0; c < max_slots; c++) {
1725                 if ((chip->codec_mask & (1 << c)) & chip->codec_probe_mask) {
1726                         if (probe_codec(chip, c) < 0) {
1727                                 /* Some BIOSen give you wrong codec addresses
1728                                  * that don't exist
1729                                  */
1730                                 snd_printk(KERN_WARNING SFX
1731                                            "Codec #%d probe error; "
1732                                            "disabling it...\n", c);
1733                                 chip->codec_mask &= ~(1 << c);
1734                                 /* More badly, accessing to a non-existing
1735                                  * codec often screws up the controller chip,
1736                                  * and disturbs the further communications.
1737                                  * Thus if an error occurs during probing,
1738                                  * better to reset the controller chip to
1739                                  * get back to the sanity state.
1740                                  */
1741                                 azx_stop_chip(chip);
1742                                 azx_init_chip(chip, 1);
1743                         }
1744                 }
1745         }
1746
1747         /* AMD chipsets often cause the communication stalls upon certain
1748          * sequence like the pin-detection.  It seems that forcing the synced
1749          * access works around the stall.  Grrr...
1750          */
1751         if (chip->driver_caps & AZX_DCAPS_SYNC_WRITE) {
1752                 snd_printd(SFX "Enable sync_write for stable communication\n");
1753                 chip->bus->sync_write = 1;
1754                 chip->bus->allow_bus_reset = 1;
1755         }
1756
1757         /* Then create codec instances */
1758         for (c = 0; c < max_slots; c++) {
1759                 if ((chip->codec_mask & (1 << c)) & chip->codec_probe_mask) {
1760                         struct hda_codec *codec;
1761                         err = snd_hda_codec_new(chip->bus, c, &codec);
1762                         if (err < 0)
1763                                 continue;
1764                         codec->beep_mode = chip->beep_mode;
1765                         codecs++;
1766                 }
1767         }
1768         if (!codecs) {
1769                 snd_printk(KERN_ERR SFX "no codecs initialized\n");
1770                 return -ENXIO;
1771         }
1772         return 0;
1773 }
1774
1775 /* configure each codec instance */
1776 static int __devinit azx_codec_configure(struct azx *chip)
1777 {
1778         struct hda_codec *codec;
1779         list_for_each_entry(codec, &chip->bus->codec_list, list) {
1780                 snd_hda_codec_configure(codec);
1781         }
1782         return 0;
1783 }
1784
1785
1786 /*
1787  * PCM support
1788  */
1789
1790 /* assign a stream for the PCM */
1791 static inline struct azx_dev *
1792 azx_assign_device(struct azx *chip, struct snd_pcm_substream *substream)
1793 {
1794         int dev, i, nums;
1795         struct azx_dev *res = NULL;
1796         /* make a non-zero unique key for the substream */
1797         int key = (substream->pcm->device << 16) | (substream->number << 2) |
1798                 (substream->stream + 1);
1799
1800         if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) {
1801                 dev = chip->playback_index_offset;
1802                 nums = chip->playback_streams;
1803         } else {
1804                 dev = chip->capture_index_offset;
1805                 nums = chip->capture_streams;
1806         }
1807         for (i = 0; i < nums; i++, dev++)
1808                 if (!chip->azx_dev[dev].opened) {
1809                         res = &chip->azx_dev[dev];
1810                         if (res->assigned_key == key)
1811                                 break;
1812                 }
1813         if (res) {
1814                 res->opened = 1;
1815                 res->assigned_key = key;
1816         }
1817         return res;
1818 }
1819
1820 /* release the assigned stream */
1821 static inline void azx_release_device(struct azx_dev *azx_dev)
1822 {
1823         azx_dev->opened = 0;
1824 }
1825
1826 static struct snd_pcm_hardware azx_pcm_hw = {
1827         .info =                 (SNDRV_PCM_INFO_MMAP |
1828                                  SNDRV_PCM_INFO_INTERLEAVED |
1829                                  SNDRV_PCM_INFO_BLOCK_TRANSFER |
1830                                  SNDRV_PCM_INFO_MMAP_VALID |
1831                                  /* No full-resume yet implemented */
1832                                  /* SNDRV_PCM_INFO_RESUME |*/
1833                                  SNDRV_PCM_INFO_PAUSE |
1834                                  SNDRV_PCM_INFO_SYNC_START |
1835                                  SNDRV_PCM_INFO_NO_PERIOD_WAKEUP),
1836         .formats =              SNDRV_PCM_FMTBIT_S16_LE,
1837         .rates =                SNDRV_PCM_RATE_48000,
1838         .rate_min =             48000,
1839         .rate_max =             48000,
1840         .channels_min =         2,
1841         .channels_max =         2,
1842         .buffer_bytes_max =     AZX_MAX_BUF_SIZE,
1843         .period_bytes_min =     128,
1844         .period_bytes_max =     AZX_MAX_BUF_SIZE / 2,
1845         .periods_min =          2,
1846         .periods_max =          AZX_MAX_FRAG,
1847         .fifo_size =            0,
1848 };
1849
1850 static int azx_pcm_open(struct snd_pcm_substream *substream)
1851 {
1852         struct azx_pcm *apcm = snd_pcm_substream_chip(substream);
1853         struct hda_pcm_stream *hinfo = apcm->hinfo[substream->stream];
1854         struct azx *chip = apcm->chip;
1855         struct azx_dev *azx_dev;
1856         struct snd_pcm_runtime *runtime = substream->runtime;
1857         unsigned long flags;
1858         int err;
1859         int buff_step;
1860
1861         mutex_lock(&chip->open_mutex);
1862         azx_dev = azx_assign_device(chip, substream);
1863         if (azx_dev == NULL) {
1864                 mutex_unlock(&chip->open_mutex);
1865                 return -EBUSY;
1866         }
1867         runtime->hw = azx_pcm_hw;
1868         runtime->hw.channels_min = hinfo->channels_min;
1869         runtime->hw.channels_max = hinfo->channels_max;
1870         runtime->hw.formats = hinfo->formats;
1871         runtime->hw.rates = hinfo->rates;
1872         snd_pcm_limit_hw_rates(runtime);
1873         snd_pcm_hw_constraint_integer(runtime, SNDRV_PCM_HW_PARAM_PERIODS);
1874         if (chip->align_buffer_size)
1875                 /* constrain buffer sizes to be multiple of 128
1876                    bytes. This is more efficient in terms of memory
1877                    access but isn't required by the HDA spec and
1878                    prevents users from specifying exact period/buffer
1879                    sizes. For example for 44.1kHz, a period size set
1880                    to 20ms will be rounded to 19.59ms. */
1881                 buff_step = 128;
1882         else
1883                 /* Don't enforce steps on buffer sizes, still need to
1884                    be multiple of 4 bytes (HDA spec). Tested on Intel
1885                    HDA controllers, may not work on all devices where
1886                    option needs to be disabled */
1887                 buff_step = 4;
1888
1889         snd_pcm_hw_constraint_step(runtime, 0, SNDRV_PCM_HW_PARAM_BUFFER_BYTES,
1890                                    buff_step);
1891         snd_pcm_hw_constraint_step(runtime, 0, SNDRV_PCM_HW_PARAM_PERIOD_BYTES,
1892                                    buff_step);
1893         snd_hda_power_up(apcm->codec);
1894         err = hinfo->ops.open(hinfo, apcm->codec, substream);
1895         if (err < 0) {
1896                 azx_release_device(azx_dev);
1897                 snd_hda_power_down(apcm->codec);
1898                 mutex_unlock(&chip->open_mutex);
1899                 return err;
1900         }
1901         snd_pcm_limit_hw_rates(runtime);
1902         /* sanity check */
1903         if (snd_BUG_ON(!runtime->hw.channels_min) ||
1904             snd_BUG_ON(!runtime->hw.channels_max) ||
1905             snd_BUG_ON(!runtime->hw.formats) ||
1906             snd_BUG_ON(!runtime->hw.rates)) {
1907                 azx_release_device(azx_dev);
1908                 hinfo->ops.close(hinfo, apcm->codec, substream);
1909                 snd_hda_power_down(apcm->codec);
1910                 mutex_unlock(&chip->open_mutex);
1911                 return -EINVAL;
1912         }
1913         spin_lock_irqsave(&chip->reg_lock, flags);
1914         azx_dev->substream = substream;
1915         azx_dev->running = 0;
1916         spin_unlock_irqrestore(&chip->reg_lock, flags);
1917
1918         runtime->private_data = azx_dev;
1919         snd_pcm_set_sync(substream);
1920         mutex_unlock(&chip->open_mutex);
1921         return 0;
1922 }
1923
1924 static int azx_pcm_close(struct snd_pcm_substream *substream)
1925 {
1926         struct azx_pcm *apcm = snd_pcm_substream_chip(substream);
1927         struct hda_pcm_stream *hinfo = apcm->hinfo[substream->stream];
1928         struct azx *chip = apcm->chip;
1929         struct azx_dev *azx_dev = get_azx_dev(substream);
1930         unsigned long flags;
1931
1932         mutex_lock(&chip->open_mutex);
1933         spin_lock_irqsave(&chip->reg_lock, flags);
1934         azx_dev->substream = NULL;
1935         azx_dev->running = 0;
1936         spin_unlock_irqrestore(&chip->reg_lock, flags);
1937         azx_release_device(azx_dev);
1938         hinfo->ops.close(hinfo, apcm->codec, substream);
1939         snd_hda_power_down(apcm->codec);
1940         mutex_unlock(&chip->open_mutex);
1941         return 0;
1942 }
1943
1944 static int azx_pcm_hw_params(struct snd_pcm_substream *substream,
1945                              struct snd_pcm_hw_params *hw_params)
1946 {
1947         struct azx_pcm *apcm = snd_pcm_substream_chip(substream);
1948         struct azx *chip = apcm->chip;
1949         struct snd_pcm_runtime *runtime = substream->runtime;
1950         struct azx_dev *azx_dev = get_azx_dev(substream);
1951         int ret;
1952
1953         mark_runtime_wc(chip, azx_dev, runtime, false);
1954         azx_dev->bufsize = 0;
1955         azx_dev->period_bytes = 0;
1956         azx_dev->format_val = 0;
1957         ret = snd_pcm_lib_malloc_pages(substream,
1958                                         params_buffer_bytes(hw_params));
1959         if (ret < 0)
1960                 return ret;
1961         mark_runtime_wc(chip, azx_dev, runtime, true);
1962         return ret;
1963 }
1964
1965 static int azx_pcm_hw_free(struct snd_pcm_substream *substream)
1966 {
1967         struct azx_pcm *apcm = snd_pcm_substream_chip(substream);
1968         struct azx_dev *azx_dev = get_azx_dev(substream);
1969         struct azx *chip = apcm->chip;
1970         struct snd_pcm_runtime *runtime = substream->runtime;
1971         struct hda_pcm_stream *hinfo = apcm->hinfo[substream->stream];
1972
1973         /* reset BDL address */
1974         azx_sd_writel(azx_dev, SD_BDLPL, 0);
1975         azx_sd_writel(azx_dev, SD_BDLPU, 0);
1976         azx_sd_writel(azx_dev, SD_CTL, 0);
1977         azx_dev->bufsize = 0;
1978         azx_dev->period_bytes = 0;
1979         azx_dev->format_val = 0;
1980
1981         snd_hda_codec_cleanup(apcm->codec, hinfo, substream);
1982
1983         mark_runtime_wc(chip, azx_dev, runtime, false);
1984         return snd_pcm_lib_free_pages(substream);
1985 }
1986
1987 static int azx_pcm_prepare(struct snd_pcm_substream *substream)
1988 {
1989         struct azx_pcm *apcm = snd_pcm_substream_chip(substream);
1990         struct azx *chip = apcm->chip;
1991         struct azx_dev *azx_dev = get_azx_dev(substream);
1992         struct hda_pcm_stream *hinfo = apcm->hinfo[substream->stream];
1993         struct snd_pcm_runtime *runtime = substream->runtime;
1994         unsigned int bufsize, period_bytes, format_val, stream_tag;
1995         int err;
1996         struct hda_spdif_out *spdif =
1997                 snd_hda_spdif_out_of_nid(apcm->codec, hinfo->nid);
1998         unsigned short ctls = spdif ? spdif->ctls : 0;
1999
2000         azx_stream_reset(chip, azx_dev);
2001         format_val = snd_hda_calc_stream_format(runtime->rate,
2002                                                 runtime->channels,
2003                                                 runtime->format,
2004                                                 hinfo->maxbps,
2005                                                 ctls);
2006         if (!format_val) {
2007                 snd_printk(KERN_ERR SFX
2008                            "invalid format_val, rate=%d, ch=%d, format=%d\n",
2009                            runtime->rate, runtime->channels, runtime->format);
2010                 return -EINVAL;
2011         }
2012
2013         bufsize = snd_pcm_lib_buffer_bytes(substream);
2014         period_bytes = snd_pcm_lib_period_bytes(substream);
2015
2016         snd_printdd(SFX "azx_pcm_prepare: bufsize=0x%x, format=0x%x\n",
2017                     bufsize, format_val);
2018
2019         if (bufsize != azx_dev->bufsize ||
2020             period_bytes != azx_dev->period_bytes ||
2021             format_val != azx_dev->format_val) {
2022                 azx_dev->bufsize = bufsize;
2023                 azx_dev->period_bytes = period_bytes;
2024                 azx_dev->format_val = format_val;
2025                 err = azx_setup_periods(chip, substream, azx_dev);
2026                 if (err < 0)
2027                         return err;
2028         }
2029
2030         /* wallclk has 24Mhz clock source */
2031         azx_dev->period_wallclk = (((runtime->period_size * 24000) /
2032                                                 runtime->rate) * 1000);
2033         azx_setup_controller(chip, azx_dev);
2034         if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK)
2035                 azx_dev->fifo_size = azx_sd_readw(azx_dev, SD_FIFOSIZE) + 1;
2036         else
2037                 azx_dev->fifo_size = 0;
2038
2039         stream_tag = azx_dev->stream_tag;
2040         /* CA-IBG chips need the playback stream starting from 1 */
2041         if ((chip->driver_caps & AZX_DCAPS_CTX_WORKAROUND) &&
2042             stream_tag > chip->capture_streams)
2043                 stream_tag -= chip->capture_streams;
2044         return snd_hda_codec_prepare(apcm->codec, hinfo, stream_tag,
2045                                      azx_dev->format_val, substream);
2046 }
2047
2048 static int azx_pcm_trigger(struct snd_pcm_substream *substream, int cmd)
2049 {
2050         struct azx_pcm *apcm = snd_pcm_substream_chip(substream);
2051         struct azx *chip = apcm->chip;
2052         struct azx_dev *azx_dev;
2053         struct snd_pcm_substream *s;
2054         int rstart = 0, start, nsync = 0, sbits = 0;
2055         int nwait, timeout;
2056
2057         switch (cmd) {
2058         case SNDRV_PCM_TRIGGER_START:
2059                 rstart = 1;
2060         case SNDRV_PCM_TRIGGER_PAUSE_RELEASE:
2061         case SNDRV_PCM_TRIGGER_RESUME:
2062                 start = 1;
2063                 break;
2064         case SNDRV_PCM_TRIGGER_PAUSE_PUSH:
2065         case SNDRV_PCM_TRIGGER_SUSPEND:
2066         case SNDRV_PCM_TRIGGER_STOP:
2067                 start = 0;
2068                 break;
2069         default:
2070                 return -EINVAL;
2071         }
2072
2073         snd_pcm_group_for_each_entry(s, substream) {
2074                 if (s->pcm->card != substream->pcm->card)
2075                         continue;
2076                 azx_dev = get_azx_dev(s);
2077                 sbits |= 1 << azx_dev->index;
2078                 nsync++;
2079                 snd_pcm_trigger_done(s, substream);
2080         }
2081
2082         spin_lock(&chip->reg_lock);
2083         if (nsync > 1) {
2084                 /* first, set SYNC bits of corresponding streams */
2085                 if (chip->driver_caps & AZX_DCAPS_OLD_SSYNC)
2086                         azx_writel(chip, OLD_SSYNC,
2087                                    azx_readl(chip, OLD_SSYNC) | sbits);
2088                 else
2089                         azx_writel(chip, SSYNC, azx_readl(chip, SSYNC) | sbits);
2090         }
2091         snd_pcm_group_for_each_entry(s, substream) {
2092                 if (s->pcm->card != substream->pcm->card)
2093                         continue;
2094                 azx_dev = get_azx_dev(s);
2095                 if (start) {
2096                         azx_dev->start_wallclk = azx_readl(chip, WALLCLK);
2097                         if (!rstart)
2098                                 azx_dev->start_wallclk -=
2099                                                 azx_dev->period_wallclk;
2100                         azx_stream_start(chip, azx_dev);
2101                 } else {
2102                         azx_stream_stop(chip, azx_dev);
2103                 }
2104                 azx_dev->running = start;
2105         }
2106         spin_unlock(&chip->reg_lock);
2107         if (start) {
2108                 if (nsync == 1)
2109                         return 0;
2110                 /* wait until all FIFOs get ready */
2111                 for (timeout = 5000; timeout; timeout--) {
2112                         nwait = 0;
2113                         snd_pcm_group_for_each_entry(s, substream) {
2114                                 if (s->pcm->card != substream->pcm->card)
2115                                         continue;
2116                                 azx_dev = get_azx_dev(s);
2117                                 if (!(azx_sd_readb(azx_dev, SD_STS) &
2118                                       SD_STS_FIFO_READY))
2119                                         nwait++;
2120                         }
2121                         if (!nwait)
2122                                 break;
2123                         cpu_relax();
2124                 }
2125         } else {
2126                 /* wait until all RUN bits are cleared */
2127                 for (timeout = 5000; timeout; timeout--) {
2128                         nwait = 0;
2129                         snd_pcm_group_for_each_entry(s, substream) {
2130                                 if (s->pcm->card != substream->pcm->card)
2131                                         continue;
2132                                 azx_dev = get_azx_dev(s);
2133                                 if (azx_sd_readb(azx_dev, SD_CTL) &
2134                                     SD_CTL_DMA_START)
2135                                         nwait++;
2136                         }
2137                         if (!nwait)
2138                                 break;
2139                         cpu_relax();
2140                 }
2141         }
2142         if (nsync > 1) {
2143                 spin_lock(&chip->reg_lock);
2144                 /* reset SYNC bits */
2145                 if (chip->driver_caps & AZX_DCAPS_OLD_SSYNC)
2146                         azx_writel(chip, OLD_SSYNC,
2147                                    azx_readl(chip, OLD_SSYNC) & ~sbits);
2148                 else
2149                         azx_writel(chip, SSYNC, azx_readl(chip, SSYNC) & ~sbits);
2150                 spin_unlock(&chip->reg_lock);
2151         }
2152         return 0;
2153 }
2154
2155 /* get the current DMA position with correction on VIA chips */
2156 static unsigned int azx_via_get_position(struct azx *chip,
2157                                          struct azx_dev *azx_dev)
2158 {
2159         unsigned int link_pos, mini_pos, bound_pos;
2160         unsigned int mod_link_pos, mod_dma_pos, mod_mini_pos;
2161         unsigned int fifo_size;
2162
2163         link_pos = azx_sd_readl(azx_dev, SD_LPIB);
2164         if (azx_dev->substream->stream == SNDRV_PCM_STREAM_PLAYBACK) {
2165                 /* Playback, no problem using link position */
2166                 return link_pos;
2167         }
2168
2169         /* Capture */
2170         /* For new chipset,
2171          * use mod to get the DMA position just like old chipset
2172          */
2173         mod_dma_pos = le32_to_cpu(*azx_dev->posbuf);
2174         mod_dma_pos %= azx_dev->period_bytes;
2175
2176         /* azx_dev->fifo_size can't get FIFO size of in stream.
2177          * Get from base address + offset.
2178          */
2179         fifo_size = readw(chip->remap_addr + VIA_IN_STREAM0_FIFO_SIZE_OFFSET);
2180
2181         if (azx_dev->insufficient) {
2182                 /* Link position never gather than FIFO size */
2183                 if (link_pos <= fifo_size)
2184                         return 0;
2185
2186                 azx_dev->insufficient = 0;
2187         }
2188
2189         if (link_pos <= fifo_size)
2190                 mini_pos = azx_dev->bufsize + link_pos - fifo_size;
2191         else
2192                 mini_pos = link_pos - fifo_size;
2193
2194         /* Find nearest previous boudary */
2195         mod_mini_pos = mini_pos % azx_dev->period_bytes;
2196         mod_link_pos = link_pos % azx_dev->period_bytes;
2197         if (mod_link_pos >= fifo_size)
2198                 bound_pos = link_pos - mod_link_pos;
2199         else if (mod_dma_pos >= mod_mini_pos)
2200                 bound_pos = mini_pos - mod_mini_pos;
2201         else {
2202                 bound_pos = mini_pos - mod_mini_pos + azx_dev->period_bytes;
2203                 if (bound_pos >= azx_dev->bufsize)
2204                         bound_pos = 0;
2205         }
2206
2207         /* Calculate real DMA position we want */
2208         return bound_pos + mod_dma_pos;
2209 }
2210
2211 static unsigned int azx_get_position(struct azx *chip,
2212                                      struct azx_dev *azx_dev,
2213                                      bool with_check)
2214 {
2215         unsigned int pos;
2216         int stream = azx_dev->substream->stream;
2217
2218         switch (chip->position_fix[stream]) {
2219         case POS_FIX_LPIB:
2220                 /* read LPIB */
2221                 pos = azx_sd_readl(azx_dev, SD_LPIB);
2222                 break;
2223         case POS_FIX_VIACOMBO:
2224                 pos = azx_via_get_position(chip, azx_dev);
2225                 break;
2226         default:
2227                 /* use the position buffer */
2228                 pos = le32_to_cpu(*azx_dev->posbuf);
2229                 if (with_check && chip->position_fix[stream] == POS_FIX_AUTO) {
2230                         if (!pos || pos == (u32)-1) {
2231                                 printk(KERN_WARNING
2232                                        "hda-intel: Invalid position buffer, "
2233                                        "using LPIB read method instead.\n");
2234                                 chip->position_fix[stream] = POS_FIX_LPIB;
2235                                 pos = azx_sd_readl(azx_dev, SD_LPIB);
2236                         } else
2237                                 chip->position_fix[stream] = POS_FIX_POSBUF;
2238                 }
2239                 break;
2240         }
2241
2242         if (pos >= azx_dev->bufsize)
2243                 pos = 0;
2244         return pos;
2245 }
2246
2247 static snd_pcm_uframes_t azx_pcm_pointer(struct snd_pcm_substream *substream)
2248 {
2249         struct azx_pcm *apcm = snd_pcm_substream_chip(substream);
2250         struct azx *chip = apcm->chip;
2251         struct azx_dev *azx_dev = get_azx_dev(substream);
2252         return bytes_to_frames(substream->runtime,
2253                                azx_get_position(chip, azx_dev, false));
2254 }
2255
2256 /*
2257  * Check whether the current DMA position is acceptable for updating
2258  * periods.  Returns non-zero if it's OK.
2259  *
2260  * Many HD-audio controllers appear pretty inaccurate about
2261  * the update-IRQ timing.  The IRQ is issued before actually the
2262  * data is processed.  So, we need to process it afterwords in a
2263  * workqueue.
2264  */
2265 static int azx_position_ok(struct azx *chip, struct azx_dev *azx_dev)
2266 {
2267         u32 wallclk;
2268         unsigned int pos;
2269         int stream;
2270
2271         wallclk = azx_readl(chip, WALLCLK) - azx_dev->start_wallclk;
2272         if (wallclk < (azx_dev->period_wallclk * 2) / 3)
2273                 return -1;      /* bogus (too early) interrupt */
2274
2275         stream = azx_dev->substream->stream;
2276         pos = azx_get_position(chip, azx_dev, true);
2277
2278         if (WARN_ONCE(!azx_dev->period_bytes,
2279                       "hda-intel: zero azx_dev->period_bytes"))
2280                 return -1; /* this shouldn't happen! */
2281         if (wallclk < (azx_dev->period_wallclk * 5) / 4 &&
2282             pos % azx_dev->period_bytes > azx_dev->period_bytes / 2)
2283                 /* NG - it's below the first next period boundary */
2284                 return bdl_pos_adj[chip->dev_index] ? 0 : -1;
2285         azx_dev->start_wallclk += wallclk;
2286         return 1; /* OK, it's fine */
2287 }
2288
2289 /*
2290  * The work for pending PCM period updates.
2291  */
2292 static void azx_irq_pending_work(struct work_struct *work)
2293 {
2294         struct azx *chip = container_of(work, struct azx, irq_pending_work);
2295         int i, pending, ok;
2296
2297         if (!chip->irq_pending_warned) {
2298                 printk(KERN_WARNING
2299                        "hda-intel: IRQ timing workaround is activated "
2300                        "for card #%d. Suggest a bigger bdl_pos_adj.\n",
2301                        chip->card->number);
2302                 chip->irq_pending_warned = 1;
2303         }
2304
2305         for (;;) {
2306                 pending = 0;
2307                 spin_lock_irq(&chip->reg_lock);
2308                 for (i = 0; i < chip->num_streams; i++) {
2309                         struct azx_dev *azx_dev = &chip->azx_dev[i];
2310                         if (!azx_dev->irq_pending ||
2311                             !azx_dev->substream ||
2312                             !azx_dev->running)
2313                                 continue;
2314                         ok = azx_position_ok(chip, azx_dev);
2315                         if (ok > 0) {
2316                                 azx_dev->irq_pending = 0;
2317                                 spin_unlock(&chip->reg_lock);
2318                                 snd_pcm_period_elapsed(azx_dev->substream);
2319                                 spin_lock(&chip->reg_lock);
2320                         } else if (ok < 0) {
2321                                 pending = 0;    /* too early */
2322                         } else
2323                                 pending++;
2324                 }
2325                 spin_unlock_irq(&chip->reg_lock);
2326                 if (!pending)
2327                         return;
2328                 msleep(1);
2329         }
2330 }
2331
2332 /* clear irq_pending flags and assure no on-going workq */
2333 static void azx_clear_irq_pending(struct azx *chip)
2334 {
2335         int i;
2336
2337         spin_lock_irq(&chip->reg_lock);
2338         for (i = 0; i < chip->num_streams; i++)
2339                 chip->azx_dev[i].irq_pending = 0;
2340         spin_unlock_irq(&chip->reg_lock);
2341 }
2342
2343 #ifdef CONFIG_X86
2344 static int azx_pcm_mmap(struct snd_pcm_substream *substream,
2345                         struct vm_area_struct *area)
2346 {
2347         struct azx_pcm *apcm = snd_pcm_substream_chip(substream);
2348         struct azx *chip = apcm->chip;
2349         if (!azx_snoop(chip))
2350                 area->vm_page_prot = pgprot_writecombine(area->vm_page_prot);
2351         return snd_pcm_lib_default_mmap(substream, area);
2352 }
2353 #else
2354 #define azx_pcm_mmap    NULL
2355 #endif
2356
2357 static struct snd_pcm_ops azx_pcm_ops = {
2358         .open = azx_pcm_open,
2359         .close = azx_pcm_close,
2360         .ioctl = snd_pcm_lib_ioctl,
2361         .hw_params = azx_pcm_hw_params,
2362         .hw_free = azx_pcm_hw_free,
2363         .prepare = azx_pcm_prepare,
2364         .trigger = azx_pcm_trigger,
2365         .pointer = azx_pcm_pointer,
2366         .mmap = azx_pcm_mmap,
2367         .page = snd_pcm_sgbuf_ops_page,
2368 };
2369
2370 static void azx_pcm_free(struct snd_pcm *pcm)
2371 {
2372         struct azx_pcm *apcm = pcm->private_data;
2373         if (apcm) {
2374                 list_del(&apcm->list);
2375                 kfree(apcm);
2376         }
2377 }
2378
2379 #define MAX_PREALLOC_SIZE       (32 * 1024 * 1024)
2380
2381 static int
2382 azx_attach_pcm_stream(struct hda_bus *bus, struct hda_codec *codec,
2383                       struct hda_pcm *cpcm)
2384 {
2385         struct azx *chip = bus->private_data;
2386         struct snd_pcm *pcm;
2387         struct azx_pcm *apcm;
2388         int pcm_dev = cpcm->device;
2389         unsigned int size;
2390         int s, err;
2391
2392         list_for_each_entry(apcm, &chip->pcm_list, list) {
2393                 if (apcm->pcm->device == pcm_dev) {
2394                         snd_printk(KERN_ERR SFX "PCM %d already exists\n", pcm_dev);
2395                         return -EBUSY;
2396                 }
2397         }
2398         err = snd_pcm_new(chip->card, cpcm->name, pcm_dev,
2399                           cpcm->stream[SNDRV_PCM_STREAM_PLAYBACK].substreams,
2400                           cpcm->stream[SNDRV_PCM_STREAM_CAPTURE].substreams,
2401                           &pcm);
2402         if (err < 0)
2403                 return err;
2404         strlcpy(pcm->name, cpcm->name, sizeof(pcm->name));
2405         apcm = kzalloc(sizeof(*apcm), GFP_KERNEL);
2406         if (apcm == NULL)
2407                 return -ENOMEM;
2408         apcm->chip = chip;
2409         apcm->pcm = pcm;
2410         apcm->codec = codec;
2411         pcm->private_data = apcm;
2412         pcm->private_free = azx_pcm_free;
2413         if (cpcm->pcm_type == HDA_PCM_TYPE_MODEM)
2414                 pcm->dev_class = SNDRV_PCM_CLASS_MODEM;
2415         list_add_tail(&apcm->list, &chip->pcm_list);
2416         cpcm->pcm = pcm;
2417         for (s = 0; s < 2; s++) {
2418                 apcm->hinfo[s] = &cpcm->stream[s];
2419                 if (cpcm->stream[s].substreams)
2420                         snd_pcm_set_ops(pcm, s, &azx_pcm_ops);
2421         }
2422         /* buffer pre-allocation */
2423         size = CONFIG_SND_HDA_PREALLOC_SIZE * 1024;
2424         if (size > MAX_PREALLOC_SIZE)
2425                 size = MAX_PREALLOC_SIZE;
2426 #ifdef CONFIG_SND_HDA_VPR
2427         chip->hda_vpr = nvmap_create_client(nvmap_dev, "hda_vpr");
2428         for (s = 0; s < 2; s++) {
2429                 struct snd_pcm_substream *substream;
2430                 for (substream = pcm->streams[s].substream;
2431                   substream; substream = substream->next) {
2432                         chip->handle_ref = nvmap_alloc(chip->hda_vpr, size, 32,
2433                           NVMAP_HANDLE_WRITE_COMBINE, NVMAP_HEAP_CARVEOUT_VPR);
2434                         chip->vaddr =
2435                           (unsigned char *) nvmap_mmap(chip->handle_ref);
2436                         chip->paddr =
2437                           nvmap_pin(chip->hda_vpr, chip->handle_ref);
2438                         snd_printk(KERN_DEBUG SFX
2439                           "paddr=%08x vaddr=%08x\n", chip->paddr, chip->vaddr);
2440                         substream->dma_buffer.area = chip->vaddr;
2441                         substream->dma_buffer.addr = chip->paddr;
2442                         substream->dma_buffer.bytes = size;
2443                         substream->dma_buffer.dev.dev = chip->dev;
2444                         if (substream->dma_buffer.bytes > 0)
2445                                 substream->buffer_bytes_max =
2446                                    substream->dma_buffer.bytes;
2447                         substream->dma_max = MAX_PREALLOC_SIZE;
2448                 }
2449         }
2450 #else
2451         snd_pcm_lib_preallocate_pages_for_all(pcm, SNDRV_DMA_TYPE_DEV_SG,
2452                                               chip->dev,
2453                                               size, MAX_PREALLOC_SIZE);
2454 #endif
2455         return 0;
2456 }
2457
2458 /*
2459  * mixer creation - all stuff is implemented in hda module
2460  */
2461 static int __devinit azx_mixer_create(struct azx *chip)
2462 {
2463         return snd_hda_build_controls(chip->bus);
2464 }
2465
2466
2467 /*
2468  * initialize SD streams
2469  */
2470 static int __devinit azx_init_stream(struct azx *chip)
2471 {
2472         int i;
2473
2474         /* initialize each stream (aka device)
2475          * assign the starting bdl address to each stream (device)
2476          * and initialize
2477          */
2478         for (i = 0; i < chip->num_streams; i++) {
2479                 struct azx_dev *azx_dev = &chip->azx_dev[i];
2480                 azx_dev->posbuf = (u32 __iomem *)(chip->posbuf.area + i * 8);
2481                 /* offset: SDI0=0x80, SDI1=0xa0, ... SDO3=0x160 */
2482                 azx_dev->sd_addr = chip->remap_addr + (0x20 * i + 0x80);
2483                 /* int mask: SDI0=0x01, SDI1=0x02, ... SDO3=0x80 */
2484                 azx_dev->sd_int_sta_mask = 1 << i;
2485                 /* stream tag: must be non-zero and unique */
2486                 azx_dev->index = i;
2487                 azx_dev->stream_tag = i + 1;
2488         }
2489
2490         return 0;
2491 }
2492
2493 static int azx_acquire_irq(struct azx *chip, int do_disconnect)
2494 {
2495         if (request_irq(chip->irq_id, azx_interrupt,
2496                         chip->msi ? 0 : IRQF_SHARED,
2497                         KBUILD_MODNAME, chip)) {
2498                 printk(KERN_ERR "hda-intel: unable to grab IRQ %d, "
2499                        "disabling device\n", chip->irq_id);
2500                 if (do_disconnect)
2501                         snd_card_disconnect(chip->card);
2502                 return -1;
2503         }
2504         chip->irq = chip->irq_id;
2505         if (chip->pci)
2506                 pci_intx(chip->pci, !chip->msi);
2507
2508         return 0;
2509 }
2510
2511
2512 static void azx_stop_chip(struct azx *chip)
2513 {
2514         if (!chip->initialized)
2515                 return;
2516
2517         /* disable interrupts */
2518         azx_int_disable(chip);
2519         azx_int_clear(chip);
2520
2521         /* disable CORB/RIRB */
2522         azx_free_cmd_io(chip);
2523
2524         /* disable position buffer */
2525         azx_writel(chip, DPLBASE, 0);
2526         azx_writel(chip, DPUBASE, 0);
2527
2528         chip->initialized = 0;
2529 }
2530
2531 #ifdef CONFIG_SND_HDA_POWER_SAVE
2532 /* power-up/down the controller */
2533 static void azx_power_notify(struct hda_bus *bus)
2534 {
2535         struct azx *chip = bus->private_data;
2536         struct hda_codec *c;
2537         int power_on = 0;
2538
2539         list_for_each_entry(c, &bus->codec_list, list) {
2540                 if (c->power_on) {
2541                         power_on = 1;
2542                         break;
2543                 }
2544         }
2545         if (power_on) {
2546 #ifdef CONFIG_SND_HDA_PLATFORM_DRIVER
2547                 azx_platform_enable_clocks(chip);
2548 #endif
2549                 azx_init_chip(chip, 1);
2550         }
2551         else if (chip->running && power_save_controller &&
2552                  !bus->power_keep_link_on) {
2553                 azx_stop_chip(chip);
2554 #ifdef CONFIG_SND_HDA_PLATFORM_DRIVER
2555                 azx_platform_disable_clocks(chip);
2556 #endif
2557         }
2558 }
2559 #endif /* CONFIG_SND_HDA_POWER_SAVE */
2560
2561 #ifdef CONFIG_PM
2562 /*
2563  * power management
2564  */
2565
2566 static int snd_hda_codecs_inuse(struct hda_bus *bus)
2567 {
2568         struct hda_codec *codec;
2569
2570         list_for_each_entry(codec, &bus->codec_list, list) {
2571                 if (snd_hda_codec_needs_resume(codec))
2572                         return 1;
2573         }
2574         return 0;
2575 }
2576
2577 static int azx_suspend(struct azx *chip, pm_message_t state)
2578 {
2579         struct snd_card *card = chip->card;
2580         struct azx_pcm *p;
2581
2582 #if defined(CONFIG_SND_HDA_PLATFORM_DRIVER) && \
2583         defined(CONFIG_SND_HDA_POWER_SAVE)
2584         if (chip->pdev)
2585                 azx_platform_enable_clocks(chip);
2586 #endif
2587
2588         snd_power_change_state(card, SNDRV_CTL_POWER_D3hot);
2589         azx_clear_irq_pending(chip);
2590         list_for_each_entry(p, &chip->pcm_list, list)
2591                 snd_pcm_suspend_all(p->pcm);
2592         if (chip->initialized)
2593                 snd_hda_suspend(chip->bus);
2594         azx_stop_chip(chip);
2595         if (chip->irq >= 0) {
2596                 free_irq(chip->irq, chip);
2597                 chip->irq = -1;
2598         }
2599
2600         if (chip->pci) {
2601                 if (chip->msi)
2602                         pci_disable_msi(chip->pci);
2603                 pci_disable_device(chip->pci);
2604                 pci_save_state(chip->pci);
2605                 pci_set_power_state(chip->pci,
2606                                     pci_choose_state(chip->pci, state));
2607         }
2608
2609 #ifdef CONFIG_SND_HDA_PLATFORM_DRIVER
2610         if (chip->pdev) {
2611                 /* Disable all clk references */
2612                 while (chip->platform_clk_enable)
2613                         azx_platform_disable_clocks(chip);
2614         }
2615 #endif
2616
2617         return 0;
2618 }
2619
2620 static int azx_resume(struct azx *chip)
2621 {
2622         struct snd_card *card = chip->card;
2623
2624 #ifdef CONFIG_SND_HDA_PLATFORM_DRIVER
2625         if (chip->pdev)
2626                 azx_platform_enable_clocks(chip);
2627 #endif
2628
2629         if (chip->pci) {
2630                 pci_set_power_state(chip->pci, PCI_D0);
2631                 pci_restore_state(chip->pci);
2632                 if (pci_enable_device(chip->pci) < 0) {
2633                         printk(KERN_ERR "hda-intel: pci_enable_device failed, "
2634                                "disabling device\n");
2635                         snd_card_disconnect(card);
2636                         return -EIO;
2637                 }
2638                 pci_set_master(chip->pci);
2639                 if (chip->msi)
2640                         if (pci_enable_msi(chip->pci) < 0)
2641                                 chip->msi = 0;
2642         }
2643
2644         if (azx_acquire_irq(chip, 1) < 0)
2645                 return -EIO;
2646
2647         if (chip->pci)
2648                 azx_init_pci(chip);
2649
2650 #ifdef CONFIG_SND_HDA_PLATFORM_DRIVER
2651         if (chip->pdev)
2652                 azx_init_platform(chip);
2653 #endif
2654
2655         if (snd_hda_codecs_inuse(chip->bus))
2656                 azx_init_chip(chip, 1);
2657
2658         snd_hda_resume(chip->bus);
2659         snd_power_change_state(card, SNDRV_CTL_POWER_D0);
2660
2661 #if defined(CONFIG_SND_HDA_PLATFORM_DRIVER) && \
2662         defined(CONFIG_SND_HDA_POWER_SAVE)
2663         if (chip->pdev)
2664                 azx_platform_disable_clocks(chip);
2665 #endif
2666
2667         return 0;
2668 }
2669
2670 static int azx_suspend_pci(struct pci_dev *pci, pm_message_t state)
2671 {
2672         struct snd_card *card = pci_get_drvdata(pci);
2673         struct azx *chip = card->private_data;
2674
2675         return azx_suspend(chip, state);
2676 }
2677
2678 static int azx_resume_pci(struct pci_dev *pci)
2679 {
2680         struct snd_card *card = pci_get_drvdata(pci);
2681         struct azx *chip = card->private_data;
2682
2683         return azx_resume(chip);
2684 }
2685
2686 #ifdef CONFIG_SND_HDA_PLATFORM_DRIVER
2687 static int azx_suspend_platform(struct platform_device *pdev,
2688                                 pm_message_t state)
2689 {
2690         struct snd_card *card = dev_get_drvdata(&pdev->dev);
2691         struct azx *chip = card->private_data;
2692
2693         return azx_suspend(chip, state);
2694 }
2695
2696 static int azx_resume_platform(struct platform_device *pdev)
2697 {
2698         struct snd_card *card = dev_get_drvdata(&pdev->dev);
2699         struct azx *chip = card->private_data;
2700
2701         return azx_resume(chip);
2702 }
2703 #endif /* CONFIG_SND_HDA_PLATFORM_DRIVER */
2704 #endif /* CONFIG_PM */
2705
2706
2707 /*
2708  * reboot notifier for hang-up problem at power-down
2709  */
2710 static int azx_halt(struct notifier_block *nb, unsigned long event, void *buf)
2711 {
2712         struct azx *chip = container_of(nb, struct azx, reboot_notifier);
2713
2714 #if defined(CONFIG_SND_HDA_PLATFORM_DRIVER) && \
2715         defined(CONFIG_SND_HDA_POWER_SAVE)
2716         if (chip->pdev)
2717                 azx_platform_enable_clocks(chip);
2718 #endif
2719
2720         snd_hda_bus_reboot_notify(chip->bus);
2721         azx_stop_chip(chip);
2722
2723 #if defined(CONFIG_SND_HDA_PLATFORM_DRIVER) && \
2724         defined(CONFIG_SND_HDA_POWER_SAVE)
2725         if (chip->pdev)
2726                 azx_platform_disable_clocks(chip);
2727 #endif
2728
2729         return NOTIFY_OK;
2730 }
2731
2732 static void azx_notifier_register(struct azx *chip)
2733 {
2734         chip->reboot_notifier.notifier_call = azx_halt;
2735         register_reboot_notifier(&chip->reboot_notifier);
2736 }
2737
2738 static void azx_notifier_unregister(struct azx *chip)
2739 {
2740         if (chip->reboot_notifier.notifier_call)
2741                 unregister_reboot_notifier(&chip->reboot_notifier);
2742 }
2743
2744 /*
2745  * destructor
2746  */
2747 static int azx_free(struct azx *chip)
2748 {
2749         int i;
2750
2751         azx_notifier_unregister(chip);
2752
2753         if (chip->initialized) {
2754                 azx_clear_irq_pending(chip);
2755                 for (i = 0; i < chip->num_streams; i++)
2756                         azx_stream_stop(chip, &chip->azx_dev[i]);
2757                 azx_stop_chip(chip);
2758         }
2759
2760 #ifdef CONFIG_SND_HDA_PLATFORM_DRIVER
2761         azx_platform_disable_clocks(chip);
2762         for (i = 0; i < chip->platform_clk_count; i++)
2763                 clk_put(chip->platform_clks[i]);
2764 #endif
2765
2766         if (chip->irq >= 0)
2767                 free_irq(chip->irq, (void*)chip);
2768         if (chip->pci && chip->msi)
2769                 pci_disable_msi(chip->pci);
2770         if (chip->remap_addr)
2771                 iounmap(chip->remap_addr);
2772
2773         if (chip->azx_dev) {
2774                 for (i = 0; i < chip->num_streams; i++)
2775                         if (chip->azx_dev[i].bdl.area) {
2776                                 mark_pages_wc(chip, &chip->azx_dev[i].bdl, false);
2777                                 snd_dma_free_pages(&chip->azx_dev[i].bdl);
2778                         }
2779         }
2780         if (chip->rb.area) {
2781                 mark_pages_wc(chip, &chip->rb, false);
2782                 snd_dma_free_pages(&chip->rb);
2783         }
2784         if (chip->posbuf.area) {
2785                 mark_pages_wc(chip, &chip->posbuf, false);
2786                 snd_dma_free_pages(&chip->posbuf);
2787         }
2788         if (chip->pci) {
2789                 pci_release_regions(chip->pci);
2790                 pci_disable_device(chip->pci);
2791         }
2792         kfree(chip->azx_dev);
2793         kfree(chip);
2794 #ifdef CONFIG_SND_HDA_VPR
2795         if(chip->handle_ref) {
2796                 nvmap_unpin(chip->hda_vpr, chip->handle_ref);
2797                 nvmap_munmap(chip->handle_ref, chip->vaddr);
2798                 nvmap_free(chip->hda_vpr, chip->handle_ref);
2799         }
2800 #endif
2801
2802         return 0;
2803 }
2804
2805 static int azx_dev_free(struct snd_device *device)
2806 {
2807         return azx_free(device->device_data);
2808 }
2809
2810 /*
2811  * white/black-listing for position_fix
2812  */
2813 static struct snd_pci_quirk position_fix_list[] __devinitdata = {
2814         SND_PCI_QUIRK(0x1028, 0x01cc, "Dell D820", POS_FIX_LPIB),
2815         SND_PCI_QUIRK(0x1028, 0x01de, "Dell Precision 390", POS_FIX_LPIB),
2816         SND_PCI_QUIRK(0x103c, 0x306d, "HP dv3", POS_FIX_LPIB),
2817         SND_PCI_QUIRK(0x1043, 0x813d, "ASUS P5AD2", POS_FIX_LPIB),
2818         SND_PCI_QUIRK(0x1043, 0x81b3, "ASUS", POS_FIX_LPIB),
2819         SND_PCI_QUIRK(0x1043, 0x81e7, "ASUS M2V", POS_FIX_LPIB),
2820         SND_PCI_QUIRK(0x104d, 0x9069, "Sony VPCS11V9E", POS_FIX_LPIB),
2821         SND_PCI_QUIRK(0x10de, 0xcb89, "Macbook Pro 7,1", POS_FIX_LPIB),
2822         SND_PCI_QUIRK(0x1297, 0x3166, "Shuttle", POS_FIX_LPIB),
2823         SND_PCI_QUIRK(0x1458, 0xa022, "ga-ma770-ud3", POS_FIX_LPIB),
2824         SND_PCI_QUIRK(0x1462, 0x1002, "MSI Wind U115", POS_FIX_LPIB),
2825         SND_PCI_QUIRK(0x1565, 0x8218, "Biostar Microtech", POS_FIX_LPIB),
2826         SND_PCI_QUIRK(0x1849, 0x0888, "775Dual-VSTA", POS_FIX_LPIB),
2827         SND_PCI_QUIRK(0x8086, 0x2503, "DG965OT AAD63733-203", POS_FIX_LPIB),
2828         {}
2829 };
2830
2831 static int __devinit check_position_fix(struct azx *chip, int fix)
2832 {
2833         const struct snd_pci_quirk *q;
2834
2835         switch (fix) {
2836         case POS_FIX_LPIB:
2837         case POS_FIX_POSBUF:
2838         case POS_FIX_VIACOMBO:
2839         case POS_FIX_COMBO:
2840                 return fix;
2841         }
2842
2843         if (chip->pci) {
2844                 q = snd_pci_quirk_lookup(chip->pci, position_fix_list);
2845                 if (q) {
2846                         printk(KERN_INFO
2847                                "hda_intel: position_fix set to %d "
2848                                "for device %04x:%04x\n",
2849                                q->value, q->subvendor, q->subdevice);
2850                         return q->value;
2851                 }
2852         }
2853
2854         /* Check VIA/ATI HD Audio Controller exist */
2855         if (chip->driver_caps & AZX_DCAPS_POSFIX_VIA) {
2856                 snd_printd(SFX "Using VIACOMBO position fix\n");
2857                 return POS_FIX_VIACOMBO;
2858         }
2859         if (chip->driver_caps & AZX_DCAPS_POSFIX_LPIB) {
2860                 snd_printd(SFX "Using LPIB position fix\n");
2861                 return POS_FIX_LPIB;
2862         }
2863         return POS_FIX_AUTO;
2864 }
2865
2866 /*
2867  * black-lists for probe_mask
2868  */
2869 static struct snd_pci_quirk probe_mask_list[] __devinitdata = {
2870         /* Thinkpad often breaks the controller communication when accessing
2871          * to the non-working (or non-existing) modem codec slot.
2872          */
2873         SND_PCI_QUIRK(0x1014, 0x05b7, "Thinkpad Z60", 0x01),
2874         SND_PCI_QUIRK(0x17aa, 0x2010, "Thinkpad X/T/R60", 0x01),
2875         SND_PCI_QUIRK(0x17aa, 0x20ac, "Thinkpad X/T/R61", 0x01),
2876         /* broken BIOS */
2877         SND_PCI_QUIRK(0x1028, 0x20ac, "Dell Studio Desktop", 0x01),
2878         /* including bogus ALC268 in slot#2 that conflicts with ALC888 */
2879         SND_PCI_QUIRK(0x17c0, 0x4085, "Medion MD96630", 0x01),
2880         /* forced codec slots */
2881         SND_PCI_QUIRK(0x1043, 0x1262, "ASUS W5Fm", 0x103),
2882         SND_PCI_QUIRK(0x1046, 0x1262, "ASUS W5F", 0x103),
2883         {}
2884 };
2885
2886 #define AZX_FORCE_CODEC_MASK    0x100
2887
2888 static void __devinit check_probe_mask(struct azx *chip, int dev)
2889 {
2890         const struct snd_pci_quirk *q;
2891
2892         chip->codec_probe_mask = probe_mask[dev];
2893         if (chip->pci && (chip->codec_probe_mask == -1)) {
2894                 q = snd_pci_quirk_lookup(chip->pci, probe_mask_list);
2895                 if (q) {
2896                         printk(KERN_INFO
2897                                "hda_intel: probe_mask set to 0x%x "
2898                                "for device %04x:%04x\n",
2899                                q->value, q->subvendor, q->subdevice);
2900                         chip->codec_probe_mask = q->value;
2901                 }
2902         }
2903
2904         /* check forced option */
2905         if (chip->codec_probe_mask != -1 &&
2906             (chip->codec_probe_mask & AZX_FORCE_CODEC_MASK)) {
2907                 chip->codec_mask = chip->codec_probe_mask & 0xff;
2908                 printk(KERN_INFO "hda_intel: codec_mask forced to 0x%x\n",
2909                        chip->codec_mask);
2910         }
2911 }
2912
2913 /*
2914  * white/black-list for enable_msi
2915  */
2916 static struct snd_pci_quirk msi_black_list[] __devinitdata = {
2917         SND_PCI_QUIRK(0x1043, 0x81f2, "ASUS", 0), /* Athlon64 X2 + nvidia */
2918         SND_PCI_QUIRK(0x1043, 0x81f6, "ASUS", 0), /* nvidia */
2919         SND_PCI_QUIRK(0x1043, 0x822d, "ASUS", 0), /* Athlon64 X2 + nvidia MCP55 */
2920         SND_PCI_QUIRK(0x1849, 0x0888, "ASRock", 0), /* Athlon64 X2 + nvidia */
2921         SND_PCI_QUIRK(0xa0a0, 0x0575, "Aopen MZ915-M", 0), /* ICH6 */
2922         {}
2923 };
2924
2925 static void __devinit check_msi(struct azx *chip)
2926 {
2927         const struct snd_pci_quirk *q;
2928
2929         /* Disable MSI if chip is not a pci device */
2930         if (!chip->pci) {
2931                 chip->msi = 0;
2932                 return;
2933         }
2934
2935         if (enable_msi >= 0) {
2936                 chip->msi = !!enable_msi;
2937                 return;
2938         }
2939         chip->msi = 1;  /* enable MSI as default */
2940         q = snd_pci_quirk_lookup(chip->pci, msi_black_list);
2941         if (q) {
2942                 printk(KERN_INFO
2943                        "hda_intel: msi for device %04x:%04x set to %d\n",
2944                        q->subvendor, q->subdevice, q->value);
2945                 chip->msi = q->value;
2946                 return;
2947         }
2948
2949         /* NVidia chipsets seem to cause troubles with MSI */
2950         if (chip->driver_caps & AZX_DCAPS_NO_MSI) {
2951                 printk(KERN_INFO "hda_intel: Disabling MSI\n");
2952                 chip->msi = 0;
2953         }
2954 }
2955
2956 /* check the snoop mode availability */
2957 static void __devinit azx_check_snoop_available(struct azx *chip)
2958 {
2959         bool snoop = chip->snoop;
2960
2961         switch (chip->driver_type) {
2962         case AZX_DRIVER_VIA:
2963                 /* force to non-snoop mode for a new VIA controller
2964                  * when BIOS is set
2965                  */
2966                 if (snoop) {
2967                         u8 val;
2968                         pci_read_config_byte(chip->pci, 0x42, &val);
2969                         if (!(val & 0x80) && chip->pci->revision == 0x30)
2970                                 snoop = false;
2971                 }
2972                 break;
2973         case AZX_DRIVER_ATIHDMI_NS:
2974                 /* new ATI HDMI requires non-snoop */
2975                 snoop = false;
2976                 break;
2977         }
2978
2979         if (snoop != chip->snoop) {
2980                 snd_printk(KERN_INFO SFX "Force to %s mode\n",
2981                            snoop ? "snoop" : "non-snoop");
2982                 chip->snoop = snoop;
2983         }
2984 }
2985
2986 #ifdef CONFIG_SND_HDA_PLATFORM_NVIDIA_TEGRA
2987 static const char *tegra_clk_names[] __devinitdata = {
2988         "hda",
2989         "hda2codec",
2990         "hda2hdmi",
2991 };
2992 static struct clk *tegra_clks[ARRAY_SIZE(tegra_clk_names)];
2993 #endif
2994
2995 /*
2996  * constructor
2997  */
2998 static int __devinit azx_create(struct snd_card *card, struct pci_dev *pci,
2999                                 struct platform_device *pdev,
3000                                 int dev, unsigned int driver_caps,
3001                                 struct azx **rchip)
3002 {
3003         struct azx *chip;
3004         int i, err = 0;
3005         unsigned short gcap;
3006         static struct snd_device_ops ops = {
3007                 .dev_free = azx_dev_free,
3008         };
3009
3010         *rchip = NULL;
3011
3012         if (pci) {
3013                 err = pci_enable_device(pci);
3014                 if (err < 0)
3015                         return err;
3016         }
3017
3018         chip = kzalloc(sizeof(*chip), GFP_KERNEL);
3019         if (!chip) {
3020                 snd_printk(KERN_ERR SFX "cannot allocate chip\n");
3021                 if (pci)
3022                         pci_disable_device(pci);
3023                 return -ENOMEM;
3024         }
3025
3026         spin_lock_init(&chip->reg_lock);
3027         mutex_init(&chip->open_mutex);
3028         chip->card = card;
3029         chip->pci = pci;
3030         chip->pdev = pdev;
3031         chip->dev = pci ? snd_dma_pci_data(pci) : &pdev->dev;
3032         chip->irq_id = pci ? pci->irq : platform_get_irq(pdev, 0);
3033         chip->irq = -1;
3034         chip->driver_caps = driver_caps;
3035         chip->driver_type = driver_caps & 0xff;
3036         check_msi(chip);
3037         chip->dev_index = dev;
3038         INIT_WORK(&chip->irq_pending_work, azx_irq_pending_work);
3039         INIT_LIST_HEAD(&chip->pcm_list);
3040
3041         chip->position_fix[0] = chip->position_fix[1] =
3042                 check_position_fix(chip, position_fix[dev]);
3043         /* combo mode uses LPIB for playback */
3044         if (chip->position_fix[0] == POS_FIX_COMBO) {
3045                 chip->position_fix[0] = POS_FIX_LPIB;
3046                 chip->position_fix[1] = POS_FIX_AUTO;
3047         }
3048
3049         check_probe_mask(chip, dev);
3050
3051         chip->single_cmd = single_cmd;
3052         chip->snoop = hda_snoop;
3053         azx_check_snoop_available(chip);
3054
3055         if (bdl_pos_adj[dev] < 0) {
3056                 switch (chip->driver_type) {
3057                 case AZX_DRIVER_ICH:
3058                 case AZX_DRIVER_PCH:
3059                         bdl_pos_adj[dev] = 1;
3060                         break;
3061                 default:
3062                         bdl_pos_adj[dev] = 32;
3063                         break;
3064                 }
3065         }
3066
3067 #if BITS_PER_LONG != 64
3068         /* Fix up base address on ULI M5461 */
3069         if (chip->driver_type == AZX_DRIVER_ULI) {
3070                 u16 tmp3;
3071                 pci_read_config_word(pci, 0x40, &tmp3);
3072                 pci_write_config_word(pci, 0x40, tmp3 | 0x10);
3073                 pci_write_config_dword(pci, PCI_BASE_ADDRESS_1, 0);
3074         }
3075 #endif
3076
3077         if (chip->pci) {
3078                 err = pci_request_regions(pci, "ICH HD audio");
3079                 if (err < 0) {
3080                         kfree(chip);
3081                         pci_disable_device(pci);
3082                         return err;
3083                 }
3084
3085                 chip->addr = pci_resource_start(pci, 0);
3086                 chip->remap_addr = pci_ioremap_bar(pci, 0);
3087                 if (chip->remap_addr == NULL) {
3088                         snd_printk(KERN_ERR SFX "ioremap error\n");
3089                         err = -ENXIO;
3090                         goto errout;
3091                 }
3092
3093                 if (chip->msi)
3094                         if (pci_enable_msi(pci) < 0)
3095                                 chip->msi = 0;
3096         }
3097
3098 #ifdef CONFIG_SND_HDA_PLATFORM_DRIVER
3099         if (chip->pdev) {
3100                 struct resource *res, *region;
3101
3102                 /* Do platform specific initialization */
3103                 switch (chip->driver_type) {
3104 #ifdef CONFIG_SND_HDA_PLATFORM_NVIDIA_TEGRA
3105                 case AZX_DRIVER_NVIDIA_TEGRA:
3106                         chip->platform_clk_count = ARRAY_SIZE(tegra_clk_names);
3107                         for (i = 0; i < chip->platform_clk_count; i++) {
3108                                 tegra_clks[i] = clk_get(&pdev->dev,
3109                                                         tegra_clk_names[i]);
3110                                 if (IS_ERR_OR_NULL(tegra_clks[i])) {
3111                                         err = PTR_ERR(tegra_clks[i]);
3112                                         goto errout;
3113                                 }
3114                         }
3115                         chip->platform_clks = tegra_clks;
3116                         break;
3117 #endif
3118                 default:
3119                         break;
3120                 }
3121
3122                 azx_platform_enable_clocks(chip);
3123
3124                 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
3125                 if (res == NULL) {
3126                         err = EINVAL;
3127                         goto errout;
3128                 }
3129
3130                 region = devm_request_mem_region(chip->dev, res->start,
3131                                                  resource_size(res),
3132                                                  pdev->name);
3133                 if (!region) {
3134                         snd_printk(KERN_ERR SFX "Mem region already claimed\n");
3135                         err = -EINVAL;
3136                         goto errout;
3137                 }
3138
3139                 chip->addr = res->start;
3140                 chip->remap_addr = devm_ioremap(chip->dev,
3141                                                 res->start,
3142                                                 resource_size(res));
3143                 if (chip->remap_addr == NULL) {
3144                         snd_printk(KERN_ERR SFX "ioremap error\n");
3145                         err = -ENXIO;
3146                         goto errout;
3147                 }
3148
3149 #ifdef CONFIG_SND_HDA_PLATFORM_NVIDIA_TEGRA
3150                 if (chip->driver_type == AZX_DRIVER_NVIDIA_TEGRA) {
3151                         chip->remap_config_addr = chip->remap_addr;
3152                         chip->remap_addr += NVIDIA_TEGRA_HDA_BAR0_OFFSET;
3153                         chip->addr += NVIDIA_TEGRA_HDA_BAR0_OFFSET;
3154                 }
3155 #endif
3156
3157                 azx_init_platform(chip);
3158         }
3159 #endif /* CONFIG_SND_HDA_PLATFORM_DRIVER */
3160
3161         if (azx_acquire_irq(chip, 0) < 0) {
3162                 err = -EBUSY;
3163                 goto errout;
3164         }
3165
3166         if (chip->pci)
3167                 pci_set_master(pci);
3168
3169         synchronize_irq(chip->irq);
3170
3171         gcap = azx_readw(chip, GCAP);
3172         snd_printdd(SFX "chipset global capabilities = 0x%x\n", gcap);
3173
3174         /* disable SB600 64bit support for safety */
3175         if (chip->pci && chip->pci->vendor == PCI_VENDOR_ID_ATI) {
3176                 struct pci_dev *p_smbus;
3177                 p_smbus = pci_get_device(PCI_VENDOR_ID_ATI,
3178                                          PCI_DEVICE_ID_ATI_SBX00_SMBUS,
3179                                          NULL);
3180                 if (p_smbus) {
3181                         if (p_smbus->revision < 0x30)
3182                                 gcap &= ~ICH6_GCAP_64OK;
3183                         pci_dev_put(p_smbus);
3184                 }
3185         }
3186
3187         /* disable 64bit DMA address on some devices */
3188         if (chip->driver_caps & AZX_DCAPS_NO_64BIT) {
3189                 snd_printd(SFX "Disabling 64bit DMA\n");
3190                 gcap &= ~ICH6_GCAP_64OK;
3191         }
3192
3193         /* disable buffer size rounding to 128-byte multiples if supported */
3194         if (align_buffer_size >= 0)
3195                 chip->align_buffer_size = !!align_buffer_size;
3196         else {
3197                 if (chip->driver_caps & AZX_DCAPS_BUFSIZE)
3198                         chip->align_buffer_size = 0;
3199                 else if (chip->driver_caps & AZX_DCAPS_ALIGN_BUFSIZE)
3200                         chip->align_buffer_size = 1;
3201                 else
3202                         chip->align_buffer_size = 1;
3203         }
3204
3205         if (chip->pci) {
3206                 /* allow 64bit DMA address if supported by H/W */
3207                 if ((gcap & ICH6_GCAP_64OK) &&
3208                     !pci_set_dma_mask(pci, DMA_BIT_MASK(64)))
3209                         pci_set_consistent_dma_mask(pci, DMA_BIT_MASK(64));
3210                 else {
3211                         pci_set_dma_mask(pci, DMA_BIT_MASK(32));
3212                         pci_set_consistent_dma_mask(pci, DMA_BIT_MASK(32));
3213                 }
3214         }
3215
3216         /* read number of streams from GCAP register instead of using
3217          * hardcoded value
3218          */
3219         chip->capture_streams = (gcap >> 8) & 0x0f;
3220         chip->playback_streams = (gcap >> 12) & 0x0f;
3221         if (!chip->playback_streams && !chip->capture_streams) {
3222                 /* gcap didn't give any info, switching to old method */
3223
3224                 switch (chip->driver_type) {
3225                 case AZX_DRIVER_ULI:
3226                         chip->playback_streams = ULI_NUM_PLAYBACK;
3227                         chip->capture_streams = ULI_NUM_CAPTURE;
3228                         break;
3229                 case AZX_DRIVER_ATIHDMI:
3230                 case AZX_DRIVER_ATIHDMI_NS:
3231                         chip->playback_streams = ATIHDMI_NUM_PLAYBACK;
3232                         chip->capture_streams = ATIHDMI_NUM_CAPTURE;
3233                         break;
3234                 case AZX_DRIVER_GENERIC:
3235                 default:
3236                         chip->playback_streams = ICH6_NUM_PLAYBACK;
3237                         chip->capture_streams = ICH6_NUM_CAPTURE;
3238                         break;
3239                 }
3240         }
3241         chip->capture_index_offset = 0;
3242         chip->playback_index_offset = chip->capture_streams;
3243         chip->num_streams = chip->playback_streams + chip->capture_streams;
3244         chip->azx_dev = kcalloc(chip->num_streams, sizeof(*chip->azx_dev),
3245                                 GFP_KERNEL);
3246         if (!chip->azx_dev) {
3247                 snd_printk(KERN_ERR SFX "cannot malloc azx_dev\n");
3248                 goto errout;
3249         }
3250
3251         for (i = 0; i < chip->num_streams; i++) {
3252                 /* allocate memory for the BDL for each stream */
3253                 err = snd_dma_alloc_pages(SNDRV_DMA_TYPE_DEV,
3254                                           chip->dev,
3255                                           BDL_SIZE, &chip->azx_dev[i].bdl);
3256                 if (err < 0) {
3257                         snd_printk(KERN_ERR SFX "cannot allocate BDL\n");
3258                         goto errout;
3259                 }
3260                 mark_pages_wc(chip, &chip->azx_dev[i].bdl, true);
3261         }
3262         /* allocate memory for the position buffer */
3263         err = snd_dma_alloc_pages(SNDRV_DMA_TYPE_DEV,
3264                                   chip->dev,
3265                                   chip->num_streams * 8, &chip->posbuf);
3266         if (err < 0) {
3267                 snd_printk(KERN_ERR SFX "cannot allocate posbuf\n");
3268                 goto errout;
3269         }
3270         mark_pages_wc(chip, &chip->posbuf, true);
3271         /* allocate CORB/RIRB */
3272         err = azx_alloc_cmd_io(chip);
3273         if (err < 0)
3274                 goto errout;
3275
3276         /* initialize streams */
3277         azx_init_stream(chip);
3278
3279         /* initialize chip */
3280         if (chip->pci)
3281                 azx_init_pci(chip);
3282         azx_init_chip(chip, (probe_only[dev] & 2) == 0);
3283
3284         /* codec detection */
3285         if (!chip->codec_mask) {
3286                 snd_printk(KERN_ERR SFX "no codecs found!\n");
3287                 err = -ENODEV;
3288                 goto errout;
3289         }
3290
3291         err = snd_device_new(card, SNDRV_DEV_LOWLEVEL, chip, &ops);
3292         if (err <0) {
3293                 snd_printk(KERN_ERR SFX "Error creating device [card]!\n");
3294                 goto errout;
3295         }
3296
3297         strcpy(card->driver, "HDA-Intel");
3298         strlcpy(card->shortname, driver_short_names[chip->driver_type],
3299                 sizeof(card->shortname));
3300         snprintf(card->longname, sizeof(card->longname),
3301                  "%s at 0x%lx irq %i",
3302                  card->shortname, chip->addr, chip->irq);
3303
3304         *rchip = chip;
3305         return 0;
3306
3307  errout:
3308         azx_free(chip);
3309         return err;
3310 }
3311
3312 static void power_down_all_codecs(struct azx *chip)
3313 {
3314 #ifdef CONFIG_SND_HDA_POWER_SAVE
3315         /* The codecs were powered up in snd_hda_codec_new().
3316          * Now all initialization done, so turn them down if possible
3317          */
3318         struct hda_codec *codec;
3319         list_for_each_entry(codec, &chip->bus->codec_list, list) {
3320                 snd_hda_power_down(codec);
3321         }
3322 #endif
3323 }
3324
3325 static int __devinit azx_probe(struct pci_dev *pci,
3326                                struct platform_device *pdev,
3327                                int driver_data)
3328 {
3329         static int dev;
3330         struct snd_card *card;
3331         struct azx *chip;
3332         struct device *azx_dev = pci ? &pci->dev : &pdev->dev;
3333         int err;
3334
3335         if (dev >= SNDRV_CARDS)
3336                 return -ENODEV;
3337         if (!enable[dev]) {
3338                 dev++;
3339                 return -ENOENT;
3340         }
3341
3342         err = snd_card_create(index[dev], id[dev], THIS_MODULE, 0, &card);
3343         if (err < 0) {
3344                 snd_printk(KERN_ERR SFX "Error creating card!\n");
3345                 return err;
3346         }
3347
3348         /* set this here since it's referred in snd_hda_load_patch() */
3349         snd_card_set_dev(card, azx_dev);
3350
3351         err = azx_create(card, pci, pdev, dev, driver_data, &chip);
3352         if (err < 0)
3353                 goto out_free;
3354         card->private_data = chip;
3355
3356 #ifdef CONFIG_SND_HDA_INPUT_BEEP
3357         chip->beep_mode = beep_mode[dev];
3358 #endif
3359
3360         /* create codec instances */
3361         err = azx_codec_create(chip, model[dev]);
3362         if (err < 0)
3363                 goto out_free;
3364 #ifdef CONFIG_SND_HDA_PATCH_LOADER
3365         if (patch[dev] && *patch[dev]) {
3366                 snd_printk(KERN_ERR SFX "Applying patch firmware '%s'\n",
3367                            patch[dev]);
3368                 err = snd_hda_load_patch(chip->bus, patch[dev]);
3369                 if (err < 0)
3370                         goto out_free;
3371         }
3372 #endif
3373         if ((probe_only[dev] & 1) == 0) {
3374                 err = azx_codec_configure(chip);
3375                 if (err < 0)
3376                         goto out_free;
3377         }
3378
3379         /* create PCM streams */
3380         err = snd_hda_build_pcms(chip->bus);
3381         if (err < 0)
3382                 goto out_free;
3383
3384         /* create mixer controls */
3385         err = azx_mixer_create(chip);
3386         if (err < 0)
3387                 goto out_free;
3388
3389         err = snd_card_register(card);
3390         if (err < 0)
3391                 goto out_free;
3392
3393         if (pci)
3394                 pci_set_drvdata(pci, card);
3395         else
3396                 dev_set_drvdata(&pdev->dev, card);
3397
3398         chip->running = 1;
3399         power_down_all_codecs(chip);
3400         azx_notifier_register(chip);
3401
3402         dev++;
3403         return err;
3404 out_free:
3405         snd_card_free(card);
3406         return err;
3407 }
3408
3409 static int __devinit azx_probe_pci(struct pci_dev *pci,
3410                                    const struct pci_device_id *pci_id)
3411 {
3412         return azx_probe(pci, NULL, pci_id->driver_data);
3413 }
3414
3415 static void __devexit azx_remove_pci(struct pci_dev *pci)
3416 {
3417         snd_card_free(pci_get_drvdata(pci));
3418         pci_set_drvdata(pci, NULL);
3419 }
3420
3421 /* PCI IDs */
3422 static DEFINE_PCI_DEVICE_TABLE(azx_pci_ids) = {
3423         /* CPT */
3424         { PCI_DEVICE(0x8086, 0x1c20),
3425           .driver_data = AZX_DRIVER_PCH | AZX_DCAPS_SCH_SNOOP |
3426           AZX_DCAPS_BUFSIZE },
3427         /* PBG */
3428         { PCI_DEVICE(0x8086, 0x1d20),
3429           .driver_data = AZX_DRIVER_PCH | AZX_DCAPS_SCH_SNOOP |
3430           AZX_DCAPS_BUFSIZE},
3431         /* Panther Point */
3432         { PCI_DEVICE(0x8086, 0x1e20),
3433           .driver_data = AZX_DRIVER_PCH | AZX_DCAPS_SCH_SNOOP |
3434           AZX_DCAPS_BUFSIZE},
3435         /* Lynx Point */
3436         { PCI_DEVICE(0x8086, 0x8c20),
3437           .driver_data = AZX_DRIVER_PCH | AZX_DCAPS_SCH_SNOOP |
3438           AZX_DCAPS_BUFSIZE},
3439         /* SCH */
3440         { PCI_DEVICE(0x8086, 0x811b),
3441           .driver_data = AZX_DRIVER_SCH | AZX_DCAPS_SCH_SNOOP |
3442           AZX_DCAPS_BUFSIZE | AZX_DCAPS_POSFIX_LPIB }, /* Poulsbo */
3443         { PCI_DEVICE(0x8086, 0x080a),
3444           .driver_data = AZX_DRIVER_SCH | AZX_DCAPS_SCH_SNOOP |
3445           AZX_DCAPS_BUFSIZE | AZX_DCAPS_POSFIX_LPIB }, /* Oaktrail */
3446         /* ICH */
3447         { PCI_DEVICE(0x8086, 0x2668),
3448           .driver_data = AZX_DRIVER_ICH | AZX_DCAPS_OLD_SSYNC |
3449           AZX_DCAPS_BUFSIZE },  /* ICH6 */
3450         { PCI_DEVICE(0x8086, 0x27d8),
3451           .driver_data = AZX_DRIVER_ICH | AZX_DCAPS_OLD_SSYNC |
3452           AZX_DCAPS_BUFSIZE },  /* ICH7 */
3453         { PCI_DEVICE(0x8086, 0x269a),
3454           .driver_data = AZX_DRIVER_ICH | AZX_DCAPS_OLD_SSYNC |
3455           AZX_DCAPS_BUFSIZE },  /* ESB2 */
3456         { PCI_DEVICE(0x8086, 0x284b),
3457           .driver_data = AZX_DRIVER_ICH | AZX_DCAPS_OLD_SSYNC |
3458           AZX_DCAPS_BUFSIZE },  /* ICH8 */
3459         { PCI_DEVICE(0x8086, 0x293e),
3460           .driver_data = AZX_DRIVER_ICH | AZX_DCAPS_OLD_SSYNC |
3461           AZX_DCAPS_BUFSIZE },  /* ICH9 */
3462         { PCI_DEVICE(0x8086, 0x293f),
3463           .driver_data = AZX_DRIVER_ICH | AZX_DCAPS_OLD_SSYNC |
3464           AZX_DCAPS_BUFSIZE },  /* ICH9 */
3465         { PCI_DEVICE(0x8086, 0x3a3e),
3466           .driver_data = AZX_DRIVER_ICH | AZX_DCAPS_OLD_SSYNC |
3467           AZX_DCAPS_BUFSIZE },  /* ICH10 */
3468         { PCI_DEVICE(0x8086, 0x3a6e),
3469           .driver_data = AZX_DRIVER_ICH | AZX_DCAPS_OLD_SSYNC |
3470           AZX_DCAPS_BUFSIZE },  /* ICH10 */
3471         /* Generic Intel */
3472         { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_ANY_ID),
3473           .class = PCI_CLASS_MULTIMEDIA_HD_AUDIO << 8,
3474           .class_mask = 0xffffff,
3475           .driver_data = AZX_DRIVER_ICH | AZX_DCAPS_BUFSIZE },
3476         /* ATI SB 450/600/700/800/900 */
3477         { PCI_DEVICE(0x1002, 0x437b),
3478           .driver_data = AZX_DRIVER_ATI | AZX_DCAPS_PRESET_ATI_SB },
3479         { PCI_DEVICE(0x1002, 0x4383),
3480           .driver_data = AZX_DRIVER_ATI | AZX_DCAPS_PRESET_ATI_SB },
3481         /* AMD Hudson */
3482         { PCI_DEVICE(0x1022, 0x780d),
3483           .driver_data = AZX_DRIVER_GENERIC | AZX_DCAPS_PRESET_ATI_SB },
3484         /* ATI HDMI */
3485         { PCI_DEVICE(0x1002, 0x793b),
3486           .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
3487         { PCI_DEVICE(0x1002, 0x7919),
3488           .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
3489         { PCI_DEVICE(0x1002, 0x960f),
3490           .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
3491         { PCI_DEVICE(0x1002, 0x970f),
3492           .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
3493         { PCI_DEVICE(0x1002, 0xaa00),
3494           .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
3495         { PCI_DEVICE(0x1002, 0xaa08),
3496           .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
3497         { PCI_DEVICE(0x1002, 0xaa10),
3498           .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
3499         { PCI_DEVICE(0x1002, 0xaa18),
3500           .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
3501         { PCI_DEVICE(0x1002, 0xaa20),
3502           .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
3503         { PCI_DEVICE(0x1002, 0xaa28),
3504           .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
3505         { PCI_DEVICE(0x1002, 0xaa30),
3506           .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
3507         { PCI_DEVICE(0x1002, 0xaa38),
3508           .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
3509         { PCI_DEVICE(0x1002, 0xaa40),
3510           .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
3511         { PCI_DEVICE(0x1002, 0xaa48),
3512           .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
3513         { PCI_DEVICE(0x1002, 0x9902),
3514           .driver_data = AZX_DRIVER_ATIHDMI_NS | AZX_DCAPS_PRESET_ATI_HDMI },
3515         { PCI_DEVICE(0x1002, 0xaaa0),
3516           .driver_data = AZX_DRIVER_ATIHDMI_NS | AZX_DCAPS_PRESET_ATI_HDMI },
3517         { PCI_DEVICE(0x1002, 0xaaa8),
3518           .driver_data = AZX_DRIVER_ATIHDMI_NS | AZX_DCAPS_PRESET_ATI_HDMI },
3519         { PCI_DEVICE(0x1002, 0xaab0),
3520           .driver_data = AZX_DRIVER_ATIHDMI_NS | AZX_DCAPS_PRESET_ATI_HDMI },
3521         /* VIA VT8251/VT8237A */
3522         { PCI_DEVICE(0x1106, 0x3288),
3523           .driver_data = AZX_DRIVER_VIA | AZX_DCAPS_POSFIX_VIA },
3524         /* SIS966 */
3525         { PCI_DEVICE(0x1039, 0x7502), .driver_data = AZX_DRIVER_SIS },
3526         /* ULI M5461 */
3527         { PCI_DEVICE(0x10b9, 0x5461), .driver_data = AZX_DRIVER_ULI },
3528         /* NVIDIA MCP */
3529         { PCI_DEVICE(PCI_VENDOR_ID_NVIDIA, PCI_ANY_ID),
3530           .class = PCI_CLASS_MULTIMEDIA_HD_AUDIO << 8,
3531           .class_mask = 0xffffff,
3532           .driver_data = AZX_DRIVER_NVIDIA | AZX_DCAPS_PRESET_NVIDIA },
3533         /* Teradici */
3534         { PCI_DEVICE(0x6549, 0x1200),
3535           .driver_data = AZX_DRIVER_TERA | AZX_DCAPS_NO_64BIT },
3536         /* Creative X-Fi (CA0110-IBG) */
3537 #if !defined(CONFIG_SND_CTXFI) && !defined(CONFIG_SND_CTXFI_MODULE)
3538         /* the following entry conflicts with snd-ctxfi driver,
3539          * as ctxfi driver mutates from HD-audio to native mode with
3540          * a special command sequence.
3541          */
3542         { PCI_DEVICE(PCI_VENDOR_ID_CREATIVE, PCI_ANY_ID),
3543           .class = PCI_CLASS_MULTIMEDIA_HD_AUDIO << 8,
3544           .class_mask = 0xffffff,
3545           .driver_data = AZX_DRIVER_CTX | AZX_DCAPS_CTX_WORKAROUND |
3546           AZX_DCAPS_RIRB_PRE_DELAY | AZX_DCAPS_POSFIX_LPIB },
3547 #else
3548         /* this entry seems still valid -- i.e. without emu20kx chip */
3549         { PCI_DEVICE(0x1102, 0x0009),
3550           .driver_data = AZX_DRIVER_CTX | AZX_DCAPS_CTX_WORKAROUND |
3551           AZX_DCAPS_RIRB_PRE_DELAY | AZX_DCAPS_POSFIX_LPIB },
3552 #endif
3553         /* Vortex86MX */
3554         { PCI_DEVICE(0x17f3, 0x3010), .driver_data = AZX_DRIVER_GENERIC },
3555         /* VMware HDAudio */
3556         { PCI_DEVICE(0x15ad, 0x1977), .driver_data = AZX_DRIVER_GENERIC },
3557         /* AMD/ATI Generic, PCI class code and Vendor ID for HD Audio */
3558         { PCI_DEVICE(PCI_VENDOR_ID_ATI, PCI_ANY_ID),
3559           .class = PCI_CLASS_MULTIMEDIA_HD_AUDIO << 8,
3560           .class_mask = 0xffffff,
3561           .driver_data = AZX_DRIVER_GENERIC | AZX_DCAPS_PRESET_ATI_HDMI },
3562         { PCI_DEVICE(PCI_VENDOR_ID_AMD, PCI_ANY_ID),
3563           .class = PCI_CLASS_MULTIMEDIA_HD_AUDIO << 8,
3564           .class_mask = 0xffffff,
3565           .driver_data = AZX_DRIVER_GENERIC | AZX_DCAPS_PRESET_ATI_HDMI },
3566         { 0, }
3567 };
3568 MODULE_DEVICE_TABLE(pci, azx_pci_ids);
3569
3570 /* pci_driver definition */
3571 static struct pci_driver driver = {
3572         .name = KBUILD_MODNAME,
3573         .id_table = azx_pci_ids,
3574         .probe = azx_probe_pci,
3575         .remove = __devexit_p(azx_remove_pci),
3576 #ifdef CONFIG_PM
3577         .suspend = azx_suspend_pci,
3578         .resume = azx_resume_pci,
3579 #endif
3580 };
3581
3582 #ifdef CONFIG_SND_HDA_PLATFORM_DRIVER
3583 static int __devinit azx_probe_platform(struct platform_device *pdev)
3584 {
3585         const struct platform_device_id *pdev_id = platform_get_device_id(pdev);
3586
3587         return azx_probe(NULL, pdev, pdev_id->driver_data);
3588 }
3589
3590 static int __devexit azx_remove_platform(struct platform_device *pdev)
3591 {
3592         return snd_card_free(dev_get_drvdata(&pdev->dev));
3593 }
3594
3595 static const struct platform_device_id azx_platform_ids[] = {
3596 #ifdef CONFIG_SND_HDA_PLATFORM_NVIDIA_TEGRA
3597         { "tegra30-hda",
3598           .driver_data = AZX_DRIVER_NVIDIA_TEGRA | AZX_DCAPS_RIRB_DELAY },
3599 #endif
3600         { },
3601 };
3602 MODULE_DEVICE_TABLE(platform, azx_platform_ids);
3603
3604 /* platform_driver definition */
3605 static struct platform_driver hda_platform_driver = {
3606         .driver = {
3607                 .name = "hda-platform"
3608         },
3609         .probe = azx_probe_platform,
3610         .remove = __devexit_p(azx_remove_platform),
3611         .id_table = azx_platform_ids,
3612 #ifdef CONFIG_PM
3613         .suspend = azx_suspend_platform,
3614         .resume = azx_resume_platform,
3615 #endif
3616 };
3617 #endif /* CONFIG_SND_HDA_PLATFORM_DRIVER */
3618
3619 static int __init alsa_card_azx_init(void)
3620 {
3621         int err = 0;
3622
3623         err = pci_register_driver(&driver);
3624         if (err < 0) {
3625                 snd_printk(KERN_ERR SFX "Failed to register pci driver\n");
3626                 return err;
3627         }
3628
3629 #ifdef CONFIG_SND_HDA_PLATFORM_DRIVER
3630         err = platform_driver_register(&hda_platform_driver);
3631         if (err < 0) {
3632                 snd_printk(KERN_ERR SFX "Failed to register platform driver\n");
3633                 pci_unregister_driver(&driver);
3634                 return err;
3635         }
3636 #endif
3637
3638         return 0;
3639 }
3640
3641 static void __exit alsa_card_azx_exit(void)
3642 {
3643 #ifdef CONFIG_SND_HDA_PLATFORM_DRIVER
3644         platform_driver_unregister(&hda_platform_driver);
3645 #endif
3646
3647         pci_unregister_driver(&driver);
3648 }
3649
3650 module_init(alsa_card_azx_init)
3651 module_exit(alsa_card_azx_exit)