Merge git://git.kernel.org/pub/scm/linux/kernel/git/davem/sparc-2.6
[linux-2.6.git] / sound / pci / ens1370.c
1 /*
2  *  Driver for Ensoniq ES1370/ES1371 AudioPCI soundcard
3  *  Copyright (c) by Jaroslav Kysela <perex@perex.cz>,
4  *                   Thomas Sailer <sailer@ife.ee.ethz.ch>
5  *
6  *   This program is free software; you can redistribute it and/or modify
7  *   it under the terms of the GNU General Public License as published by
8  *   the Free Software Foundation; either version 2 of the License, or
9  *   (at your option) any later version.
10  *
11  *   This program is distributed in the hope that it will be useful,
12  *   but WITHOUT ANY WARRANTY; without even the implied warranty of
13  *   MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
14  *   GNU General Public License for more details.
15  *
16  *   You should have received a copy of the GNU General Public License
17  *   along with this program; if not, write to the Free Software
18  *   Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307 USA
19  *
20  */
21
22 /* Power-Management-Code ( CONFIG_PM )
23  * for ens1371 only ( FIXME )
24  * derived from cs4281.c, atiixp.c and via82xx.c
25  * using http://www.alsa-project.org/~iwai/writing-an-alsa-driver/c1540.htm
26  * by Kurt J. Bosch
27  */
28
29 #include <asm/io.h>
30 #include <linux/delay.h>
31 #include <linux/interrupt.h>
32 #include <linux/init.h>
33 #include <linux/pci.h>
34 #include <linux/slab.h>
35 #include <linux/gameport.h>
36 #include <linux/moduleparam.h>
37 #include <linux/mutex.h>
38
39 #include <sound/core.h>
40 #include <sound/control.h>
41 #include <sound/pcm.h>
42 #include <sound/rawmidi.h>
43 #ifdef CHIP1371
44 #include <sound/ac97_codec.h>
45 #else
46 #include <sound/ak4531_codec.h>
47 #endif
48 #include <sound/initval.h>
49 #include <sound/asoundef.h>
50
51 #ifndef CHIP1371
52 #undef CHIP1370
53 #define CHIP1370
54 #endif
55
56 #ifdef CHIP1370
57 #define DRIVER_NAME "ENS1370"
58 #else
59 #define DRIVER_NAME "ENS1371"
60 #endif
61
62
63 MODULE_AUTHOR("Jaroslav Kysela <perex@perex.cz>, Thomas Sailer <sailer@ife.ee.ethz.ch>");
64 MODULE_LICENSE("GPL");
65 #ifdef CHIP1370
66 MODULE_DESCRIPTION("Ensoniq AudioPCI ES1370");
67 MODULE_SUPPORTED_DEVICE("{{Ensoniq,AudioPCI-97 ES1370},"
68                 "{Creative Labs,SB PCI64/128 (ES1370)}}");
69 #endif
70 #ifdef CHIP1371
71 MODULE_DESCRIPTION("Ensoniq/Creative AudioPCI ES1371+");
72 MODULE_SUPPORTED_DEVICE("{{Ensoniq,AudioPCI ES1371/73},"
73                 "{Ensoniq,AudioPCI ES1373},"
74                 "{Creative Labs,Ectiva EV1938},"
75                 "{Creative Labs,SB PCI64/128 (ES1371/73)},"
76                 "{Creative Labs,Vibra PCI128},"
77                 "{Ectiva,EV1938}}");
78 #endif
79
80 #if defined(CONFIG_GAMEPORT) || (defined(MODULE) && defined(CONFIG_GAMEPORT_MODULE))
81 #define SUPPORT_JOYSTICK
82 #endif
83
84 static int index[SNDRV_CARDS] = SNDRV_DEFAULT_IDX;      /* Index 0-MAX */
85 static char *id[SNDRV_CARDS] = SNDRV_DEFAULT_STR;       /* ID for this card */
86 static int enable[SNDRV_CARDS] = SNDRV_DEFAULT_ENABLE_PNP;      /* Enable switches */
87 #ifdef SUPPORT_JOYSTICK
88 #ifdef CHIP1371
89 static int joystick_port[SNDRV_CARDS];
90 #else
91 static int joystick[SNDRV_CARDS];
92 #endif
93 #endif
94 #ifdef CHIP1371
95 static int spdif[SNDRV_CARDS];
96 static int lineio[SNDRV_CARDS];
97 #endif
98
99 module_param_array(index, int, NULL, 0444);
100 MODULE_PARM_DESC(index, "Index value for Ensoniq AudioPCI soundcard.");
101 module_param_array(id, charp, NULL, 0444);
102 MODULE_PARM_DESC(id, "ID string for Ensoniq AudioPCI soundcard.");
103 module_param_array(enable, bool, NULL, 0444);
104 MODULE_PARM_DESC(enable, "Enable Ensoniq AudioPCI soundcard.");
105 #ifdef SUPPORT_JOYSTICK
106 #ifdef CHIP1371
107 module_param_array(joystick_port, int, NULL, 0444);
108 MODULE_PARM_DESC(joystick_port, "Joystick port address.");
109 #else
110 module_param_array(joystick, bool, NULL, 0444);
111 MODULE_PARM_DESC(joystick, "Enable joystick.");
112 #endif
113 #endif /* SUPPORT_JOYSTICK */
114 #ifdef CHIP1371
115 module_param_array(spdif, int, NULL, 0444);
116 MODULE_PARM_DESC(spdif, "S/PDIF output (-1 = none, 0 = auto, 1 = force).");
117 module_param_array(lineio, int, NULL, 0444);
118 MODULE_PARM_DESC(lineio, "Line In to Rear Out (0 = auto, 1 = force).");
119 #endif
120
121 /* ES1371 chip ID */
122 /* This is a little confusing because all ES1371 compatible chips have the
123    same DEVICE_ID, the only thing differentiating them is the REV_ID field.
124    This is only significant if you want to enable features on the later parts.
125    Yes, I know it's stupid and why didn't we use the sub IDs?
126 */
127 #define ES1371REV_ES1373_A  0x04
128 #define ES1371REV_ES1373_B  0x06
129 #define ES1371REV_CT5880_A  0x07
130 #define CT5880REV_CT5880_C  0x02
131 #define CT5880REV_CT5880_D  0x03        /* ??? -jk */
132 #define CT5880REV_CT5880_E  0x04        /* mw */
133 #define ES1371REV_ES1371_B  0x09
134 #define EV1938REV_EV1938_A  0x00
135 #define ES1371REV_ES1373_8  0x08
136
137 /*
138  * Direct registers
139  */
140
141 #define ES_REG(ensoniq, x) ((ensoniq)->port + ES_REG_##x)
142
143 #define ES_REG_CONTROL  0x00    /* R/W: Interrupt/Chip select control register */
144 #define   ES_1370_ADC_STOP      (1<<31)         /* disable capture buffer transfers */
145 #define   ES_1370_XCTL1         (1<<30)         /* general purpose output bit */
146 #define   ES_1373_BYPASS_P1     (1<<31)         /* bypass SRC for PB1 */
147 #define   ES_1373_BYPASS_P2     (1<<30)         /* bypass SRC for PB2 */
148 #define   ES_1373_BYPASS_R      (1<<29)         /* bypass SRC for REC */
149 #define   ES_1373_TEST_BIT      (1<<28)         /* should be set to 0 for normal operation */
150 #define   ES_1373_RECEN_B       (1<<27)         /* mix record with playback for I2S/SPDIF out */
151 #define   ES_1373_SPDIF_THRU    (1<<26)         /* 0 = SPDIF thru mode, 1 = SPDIF == dig out */
152 #define   ES_1371_JOY_ASEL(o)   (((o)&0x03)<<24)/* joystick port mapping */
153 #define   ES_1371_JOY_ASELM     (0x03<<24)      /* mask for above */
154 #define   ES_1371_JOY_ASELI(i)  (((i)>>24)&0x03)
155 #define   ES_1371_GPIO_IN(i)    (((i)>>20)&0x0f)/* GPIO in [3:0] pins - R/O */
156 #define   ES_1370_PCLKDIVO(o)   (((o)&0x1fff)<<16)/* clock divide ratio for DAC2 */
157 #define   ES_1370_PCLKDIVM      ((0x1fff)<<16)  /* mask for above */
158 #define   ES_1370_PCLKDIVI(i)   (((i)>>16)&0x1fff)/* clock divide ratio for DAC2 */
159 #define   ES_1371_GPIO_OUT(o)   (((o)&0x0f)<<16)/* GPIO out [3:0] pins - W/R */
160 #define   ES_1371_GPIO_OUTM     (0x0f<<16)      /* mask for above */
161 #define   ES_MSFMTSEL           (1<<15)         /* MPEG serial data format; 0 = SONY, 1 = I2S */
162 #define   ES_1370_M_SBB         (1<<14)         /* clock source for DAC - 0 = clock generator; 1 = MPEG clocks */
163 #define   ES_1371_SYNC_RES      (1<<14)         /* Warm AC97 reset */
164 #define   ES_1370_WTSRSEL(o)    (((o)&0x03)<<12)/* fixed frequency clock for DAC1 */
165 #define   ES_1370_WTSRSELM      (0x03<<12)      /* mask for above */
166 #define   ES_1371_ADC_STOP      (1<<13)         /* disable CCB transfer capture information */
167 #define   ES_1371_PWR_INTRM     (1<<12)         /* power level change interrupts enable */
168 #define   ES_1370_DAC_SYNC      (1<<11)         /* DAC's are synchronous */
169 #define   ES_1371_M_CB          (1<<11)         /* capture clock source; 0 = AC'97 ADC; 1 = I2S */
170 #define   ES_CCB_INTRM          (1<<10)         /* CCB voice interrupts enable */
171 #define   ES_1370_M_CB          (1<<9)          /* capture clock source; 0 = ADC; 1 = MPEG */
172 #define   ES_1370_XCTL0         (1<<8)          /* generap purpose output bit */
173 #define   ES_1371_PDLEV(o)      (((o)&0x03)<<8) /* current power down level */
174 #define   ES_1371_PDLEVM        (0x03<<8)       /* mask for above */
175 #define   ES_BREQ               (1<<7)          /* memory bus request enable */
176 #define   ES_DAC1_EN            (1<<6)          /* DAC1 playback channel enable */
177 #define   ES_DAC2_EN            (1<<5)          /* DAC2 playback channel enable */
178 #define   ES_ADC_EN             (1<<4)          /* ADC capture channel enable */
179 #define   ES_UART_EN            (1<<3)          /* UART enable */
180 #define   ES_JYSTK_EN           (1<<2)          /* Joystick module enable */
181 #define   ES_1370_CDC_EN        (1<<1)          /* Codec interface enable */
182 #define   ES_1371_XTALCKDIS     (1<<1)          /* Xtal clock disable */
183 #define   ES_1370_SERR_DISABLE  (1<<0)          /* PCI serr signal disable */
184 #define   ES_1371_PCICLKDIS     (1<<0)          /* PCI clock disable */
185 #define ES_REG_STATUS   0x04    /* R/O: Interrupt/Chip select status register */
186 #define   ES_INTR               (1<<31)         /* Interrupt is pending */
187 #define   ES_1371_ST_AC97_RST   (1<<29)         /* CT5880 AC'97 Reset bit */
188 #define   ES_1373_REAR_BIT27    (1<<27)         /* rear bits: 000 - front, 010 - mirror, 101 - separate */
189 #define   ES_1373_REAR_BIT26    (1<<26)
190 #define   ES_1373_REAR_BIT24    (1<<24)
191 #define   ES_1373_GPIO_INT_EN(o)(((o)&0x0f)<<20)/* GPIO [3:0] pins - interrupt enable */
192 #define   ES_1373_SPDIF_EN      (1<<18)         /* SPDIF enable */
193 #define   ES_1373_SPDIF_TEST    (1<<17)         /* SPDIF test */
194 #define   ES_1371_TEST          (1<<16)         /* test ASIC */
195 #define   ES_1373_GPIO_INT(i)   (((i)&0x0f)>>12)/* GPIO [3:0] pins - interrupt pending */
196 #define   ES_1370_CSTAT         (1<<10)         /* CODEC is busy or register write in progress */
197 #define   ES_1370_CBUSY         (1<<9)          /* CODEC is busy */
198 #define   ES_1370_CWRIP         (1<<8)          /* CODEC register write in progress */
199 #define   ES_1371_SYNC_ERR      (1<<8)          /* CODEC synchronization error occurred */
200 #define   ES_1371_VC(i)         (((i)>>6)&0x03) /* voice code from CCB module */
201 #define   ES_1370_VC(i)         (((i)>>5)&0x03) /* voice code from CCB module */
202 #define   ES_1371_MPWR          (1<<5)          /* power level interrupt pending */
203 #define   ES_MCCB               (1<<4)          /* CCB interrupt pending */
204 #define   ES_UART               (1<<3)          /* UART interrupt pending */
205 #define   ES_DAC1               (1<<2)          /* DAC1 channel interrupt pending */
206 #define   ES_DAC2               (1<<1)          /* DAC2 channel interrupt pending */
207 #define   ES_ADC                (1<<0)          /* ADC channel interrupt pending */
208 #define ES_REG_UART_DATA 0x08   /* R/W: UART data register */
209 #define ES_REG_UART_STATUS 0x09 /* R/O: UART status register */
210 #define   ES_RXINT              (1<<7)          /* RX interrupt occurred */
211 #define   ES_TXINT              (1<<2)          /* TX interrupt occurred */
212 #define   ES_TXRDY              (1<<1)          /* transmitter ready */
213 #define   ES_RXRDY              (1<<0)          /* receiver ready */
214 #define ES_REG_UART_CONTROL 0x09        /* W/O: UART control register */
215 #define   ES_RXINTEN            (1<<7)          /* RX interrupt enable */
216 #define   ES_TXINTENO(o)        (((o)&0x03)<<5) /* TX interrupt enable */
217 #define   ES_TXINTENM           (0x03<<5)       /* mask for above */
218 #define   ES_TXINTENI(i)        (((i)>>5)&0x03)
219 #define   ES_CNTRL(o)           (((o)&0x03)<<0) /* control */
220 #define   ES_CNTRLM             (0x03<<0)       /* mask for above */
221 #define ES_REG_UART_RES 0x0a    /* R/W: UART reserver register */
222 #define   ES_TEST_MODE          (1<<0)          /* test mode enabled */
223 #define ES_REG_MEM_PAGE 0x0c    /* R/W: Memory page register */
224 #define   ES_MEM_PAGEO(o)       (((o)&0x0f)<<0) /* memory page select - out */
225 #define   ES_MEM_PAGEM          (0x0f<<0)       /* mask for above */
226 #define   ES_MEM_PAGEI(i)       (((i)>>0)&0x0f) /* memory page select - in */
227 #define ES_REG_1370_CODEC 0x10  /* W/O: Codec write register address */
228 #define   ES_1370_CODEC_WRITE(a,d) ((((a)&0xff)<<8)|(((d)&0xff)<<0))
229 #define ES_REG_1371_CODEC 0x14  /* W/R: Codec Read/Write register address */
230 #define   ES_1371_CODEC_RDY        (1<<31)      /* codec ready */
231 #define   ES_1371_CODEC_WIP        (1<<30)      /* codec register access in progress */
232 #define   ES_1371_CODEC_PIRD       (1<<23)      /* codec read/write select register */
233 #define   ES_1371_CODEC_WRITE(a,d) ((((a)&0x7f)<<16)|(((d)&0xffff)<<0))
234 #define   ES_1371_CODEC_READS(a)   ((((a)&0x7f)<<16)|ES_1371_CODEC_PIRD)
235 #define   ES_1371_CODEC_READ(i)    (((i)>>0)&0xffff)
236
237 #define ES_REG_1371_SMPRATE 0x10        /* W/R: Codec rate converter interface register */
238 #define   ES_1371_SRC_RAM_ADDRO(o) (((o)&0x7f)<<25)/* address of the sample rate converter */
239 #define   ES_1371_SRC_RAM_ADDRM    (0x7f<<25)   /* mask for above */
240 #define   ES_1371_SRC_RAM_ADDRI(i) (((i)>>25)&0x7f)/* address of the sample rate converter */
241 #define   ES_1371_SRC_RAM_WE       (1<<24)      /* R/W: read/write control for sample rate converter */
242 #define   ES_1371_SRC_RAM_BUSY     (1<<23)      /* R/O: sample rate memory is busy */
243 #define   ES_1371_SRC_DISABLE      (1<<22)      /* sample rate converter disable */
244 #define   ES_1371_DIS_P1           (1<<21)      /* playback channel 1 accumulator update disable */
245 #define   ES_1371_DIS_P2           (1<<20)      /* playback channel 1 accumulator update disable */
246 #define   ES_1371_DIS_R1           (1<<19)      /* capture channel accumulator update disable */
247 #define   ES_1371_SRC_RAM_DATAO(o) (((o)&0xffff)<<0)/* current value of the sample rate converter */
248 #define   ES_1371_SRC_RAM_DATAM    (0xffff<<0)  /* mask for above */
249 #define   ES_1371_SRC_RAM_DATAI(i) (((i)>>0)&0xffff)/* current value of the sample rate converter */
250
251 #define ES_REG_1371_LEGACY 0x18 /* W/R: Legacy control/status register */
252 #define   ES_1371_JFAST         (1<<31)         /* fast joystick timing */
253 #define   ES_1371_HIB           (1<<30)         /* host interrupt blocking enable */
254 #define   ES_1371_VSB           (1<<29)         /* SB; 0 = addr 0x220xH, 1 = 0x22FxH */
255 #define   ES_1371_VMPUO(o)      (((o)&0x03)<<27)/* base register address; 0 = 0x320xH; 1 = 0x330xH; 2 = 0x340xH; 3 = 0x350xH */
256 #define   ES_1371_VMPUM         (0x03<<27)      /* mask for above */
257 #define   ES_1371_VMPUI(i)      (((i)>>27)&0x03)/* base register address */
258 #define   ES_1371_VCDCO(o)      (((o)&0x03)<<25)/* CODEC; 0 = 0x530xH; 1 = undefined; 2 = 0xe80xH; 3 = 0xF40xH */
259 #define   ES_1371_VCDCM         (0x03<<25)      /* mask for above */
260 #define   ES_1371_VCDCI(i)      (((i)>>25)&0x03)/* CODEC address */
261 #define   ES_1371_FIRQ          (1<<24)         /* force an interrupt */
262 #define   ES_1371_SDMACAP       (1<<23)         /* enable event capture for slave DMA controller */
263 #define   ES_1371_SPICAP        (1<<22)         /* enable event capture for slave IRQ controller */
264 #define   ES_1371_MDMACAP       (1<<21)         /* enable event capture for master DMA controller */
265 #define   ES_1371_MPICAP        (1<<20)         /* enable event capture for master IRQ controller */
266 #define   ES_1371_ADCAP         (1<<19)         /* enable event capture for ADLIB register; 0x388xH */
267 #define   ES_1371_SVCAP         (1<<18)         /* enable event capture for SB registers */
268 #define   ES_1371_CDCCAP        (1<<17)         /* enable event capture for CODEC registers */
269 #define   ES_1371_BACAP         (1<<16)         /* enable event capture for SoundScape base address */
270 #define   ES_1371_EXI(i)        (((i)>>8)&0x07) /* event number */
271 #define   ES_1371_AI(i)         (((i)>>3)&0x1f) /* event significant I/O address */
272 #define   ES_1371_WR            (1<<2)  /* event capture; 0 = read; 1 = write */
273 #define   ES_1371_LEGINT        (1<<0)  /* interrupt for legacy events; 0 = interrupt did occur */
274
275 #define ES_REG_CHANNEL_STATUS 0x1c /* R/W: first 32-bits from S/PDIF channel status block, es1373 */
276
277 #define ES_REG_SERIAL   0x20    /* R/W: Serial interface control register */
278 #define   ES_1371_DAC_TEST      (1<<22)         /* DAC test mode enable */
279 #define   ES_P2_END_INCO(o)     (((o)&0x07)<<19)/* binary offset value to increment / loop end */
280 #define   ES_P2_END_INCM        (0x07<<19)      /* mask for above */
281 #define   ES_P2_END_INCI(i)     (((i)>>16)&0x07)/* binary offset value to increment / loop end */
282 #define   ES_P2_ST_INCO(o)      (((o)&0x07)<<16)/* binary offset value to increment / start */
283 #define   ES_P2_ST_INCM         (0x07<<16)      /* mask for above */
284 #define   ES_P2_ST_INCI(i)      (((i)<<16)&0x07)/* binary offset value to increment / start */
285 #define   ES_R1_LOOP_SEL        (1<<15)         /* ADC; 0 - loop mode; 1 = stop mode */
286 #define   ES_P2_LOOP_SEL        (1<<14)         /* DAC2; 0 - loop mode; 1 = stop mode */
287 #define   ES_P1_LOOP_SEL        (1<<13)         /* DAC1; 0 - loop mode; 1 = stop mode */
288 #define   ES_P2_PAUSE           (1<<12)         /* DAC2; 0 - play mode; 1 = pause mode */
289 #define   ES_P1_PAUSE           (1<<11)         /* DAC1; 0 - play mode; 1 = pause mode */
290 #define   ES_R1_INT_EN          (1<<10)         /* ADC interrupt enable */
291 #define   ES_P2_INT_EN          (1<<9)          /* DAC2 interrupt enable */
292 #define   ES_P1_INT_EN          (1<<8)          /* DAC1 interrupt enable */
293 #define   ES_P1_SCT_RLD         (1<<7)          /* force sample counter reload for DAC1 */
294 #define   ES_P2_DAC_SEN         (1<<6)          /* when stop mode: 0 - DAC2 play back zeros; 1 = DAC2 play back last sample */
295 #define   ES_R1_MODEO(o)        (((o)&0x03)<<4) /* ADC mode; 0 = 8-bit mono; 1 = 8-bit stereo; 2 = 16-bit mono; 3 = 16-bit stereo */
296 #define   ES_R1_MODEM           (0x03<<4)       /* mask for above */
297 #define   ES_R1_MODEI(i)        (((i)>>4)&0x03)
298 #define   ES_P2_MODEO(o)        (((o)&0x03)<<2) /* DAC2 mode; -- '' -- */
299 #define   ES_P2_MODEM           (0x03<<2)       /* mask for above */
300 #define   ES_P2_MODEI(i)        (((i)>>2)&0x03)
301 #define   ES_P1_MODEO(o)        (((o)&0x03)<<0) /* DAC1 mode; -- '' -- */
302 #define   ES_P1_MODEM           (0x03<<0)       /* mask for above */
303 #define   ES_P1_MODEI(i)        (((i)>>0)&0x03)
304
305 #define ES_REG_DAC1_COUNT 0x24  /* R/W: DAC1 sample count register */
306 #define ES_REG_DAC2_COUNT 0x28  /* R/W: DAC2 sample count register */
307 #define ES_REG_ADC_COUNT  0x2c  /* R/W: ADC sample count register */
308 #define   ES_REG_CURR_COUNT(i)  (((i)>>16)&0xffff)
309 #define   ES_REG_COUNTO(o)      (((o)&0xffff)<<0)
310 #define   ES_REG_COUNTM         (0xffff<<0)
311 #define   ES_REG_COUNTI(i)      (((i)>>0)&0xffff)
312
313 #define ES_REG_DAC1_FRAME 0x30  /* R/W: PAGE 0x0c; DAC1 frame address */
314 #define ES_REG_DAC1_SIZE  0x34  /* R/W: PAGE 0x0c; DAC1 frame size */
315 #define ES_REG_DAC2_FRAME 0x38  /* R/W: PAGE 0x0c; DAC2 frame address */
316 #define ES_REG_DAC2_SIZE  0x3c  /* R/W: PAGE 0x0c; DAC2 frame size */
317 #define ES_REG_ADC_FRAME  0x30  /* R/W: PAGE 0x0d; ADC frame address */
318 #define ES_REG_ADC_SIZE   0x34  /* R/W: PAGE 0x0d; ADC frame size */
319 #define   ES_REG_FCURR_COUNTO(o) (((o)&0xffff)<<16)
320 #define   ES_REG_FCURR_COUNTM    (0xffff<<16)
321 #define   ES_REG_FCURR_COUNTI(i) (((i)>>14)&0x3fffc)
322 #define   ES_REG_FSIZEO(o)       (((o)&0xffff)<<0)
323 #define   ES_REG_FSIZEM          (0xffff<<0)
324 #define   ES_REG_FSIZEI(i)       (((i)>>0)&0xffff)
325 #define ES_REG_PHANTOM_FRAME 0x38 /* R/W: PAGE 0x0d: phantom frame address */
326 #define ES_REG_PHANTOM_COUNT 0x3c /* R/W: PAGE 0x0d: phantom frame count */
327
328 #define ES_REG_UART_FIFO  0x30  /* R/W: PAGE 0x0e; UART FIFO register */
329 #define   ES_REG_UF_VALID        (1<<8)
330 #define   ES_REG_UF_BYTEO(o)     (((o)&0xff)<<0)
331 #define   ES_REG_UF_BYTEM        (0xff<<0)
332 #define   ES_REG_UF_BYTEI(i)     (((i)>>0)&0xff)
333
334
335 /*
336  *  Pages
337  */
338
339 #define ES_PAGE_DAC     0x0c
340 #define ES_PAGE_ADC     0x0d
341 #define ES_PAGE_UART    0x0e
342 #define ES_PAGE_UART1   0x0f
343
344 /*
345  *  Sample rate converter addresses
346  */
347
348 #define ES_SMPREG_DAC1          0x70
349 #define ES_SMPREG_DAC2          0x74
350 #define ES_SMPREG_ADC           0x78
351 #define ES_SMPREG_VOL_ADC       0x6c
352 #define ES_SMPREG_VOL_DAC1      0x7c
353 #define ES_SMPREG_VOL_DAC2      0x7e
354 #define ES_SMPREG_TRUNC_N       0x00
355 #define ES_SMPREG_INT_REGS      0x01
356 #define ES_SMPREG_ACCUM_FRAC    0x02
357 #define ES_SMPREG_VFREQ_FRAC    0x03
358
359 /*
360  *  Some contants
361  */
362
363 #define ES_1370_SRCLOCK    1411200
364 #define ES_1370_SRTODIV(x) (ES_1370_SRCLOCK/(x)-2)
365
366 /*
367  *  Open modes
368  */
369
370 #define ES_MODE_PLAY1   0x0001
371 #define ES_MODE_PLAY2   0x0002
372 #define ES_MODE_CAPTURE 0x0004
373
374 #define ES_MODE_OUTPUT  0x0001  /* for MIDI */
375 #define ES_MODE_INPUT   0x0002  /* for MIDI */
376
377 /*
378
379  */
380
381 struct ensoniq {
382         spinlock_t reg_lock;
383         struct mutex src_mutex;
384
385         int irq;
386
387         unsigned long playback1size;
388         unsigned long playback2size;
389         unsigned long capture3size;
390
391         unsigned long port;
392         unsigned int mode;
393         unsigned int uartm;     /* UART mode */
394
395         unsigned int ctrl;      /* control register */
396         unsigned int sctrl;     /* serial control register */
397         unsigned int cssr;      /* control status register */
398         unsigned int uartc;     /* uart control register */
399         unsigned int rev;       /* chip revision */
400
401         union {
402 #ifdef CHIP1371
403                 struct {
404                         struct snd_ac97 *ac97;
405                 } es1371;
406 #else
407                 struct {
408                         int pclkdiv_lock;
409                         struct snd_ak4531 *ak4531;
410                 } es1370;
411 #endif
412         } u;
413
414         struct pci_dev *pci;
415         struct snd_card *card;
416         struct snd_pcm *pcm1;   /* DAC1/ADC PCM */
417         struct snd_pcm *pcm2;   /* DAC2 PCM */
418         struct snd_pcm_substream *playback1_substream;
419         struct snd_pcm_substream *playback2_substream;
420         struct snd_pcm_substream *capture_substream;
421         unsigned int p1_dma_size;
422         unsigned int p2_dma_size;
423         unsigned int c_dma_size;
424         unsigned int p1_period_size;
425         unsigned int p2_period_size;
426         unsigned int c_period_size;
427         struct snd_rawmidi *rmidi;
428         struct snd_rawmidi_substream *midi_input;
429         struct snd_rawmidi_substream *midi_output;
430
431         unsigned int spdif;
432         unsigned int spdif_default;
433         unsigned int spdif_stream;
434
435 #ifdef CHIP1370
436         struct snd_dma_buffer dma_bug;
437 #endif
438
439 #ifdef SUPPORT_JOYSTICK
440         struct gameport *gameport;
441 #endif
442 };
443
444 static irqreturn_t snd_audiopci_interrupt(int irq, void *dev_id);
445
446 static DEFINE_PCI_DEVICE_TABLE(snd_audiopci_ids) = {
447 #ifdef CHIP1370
448         { PCI_VDEVICE(ENSONIQ, 0x5000), 0, },   /* ES1370 */
449 #endif
450 #ifdef CHIP1371
451         { PCI_VDEVICE(ENSONIQ, 0x1371), 0, },   /* ES1371 */
452         { PCI_VDEVICE(ENSONIQ, 0x5880), 0, },   /* ES1373 - CT5880 */
453         { PCI_VDEVICE(ECTIVA, 0x8938), 0, },    /* Ectiva EV1938 */
454 #endif
455         { 0, }
456 };
457
458 MODULE_DEVICE_TABLE(pci, snd_audiopci_ids);
459
460 /*
461  *  constants
462  */
463
464 #define POLL_COUNT      0xa000
465
466 #ifdef CHIP1370
467 static unsigned int snd_es1370_fixed_rates[] =
468         {5512, 11025, 22050, 44100};
469 static struct snd_pcm_hw_constraint_list snd_es1370_hw_constraints_rates = {
470         .count = 4, 
471         .list = snd_es1370_fixed_rates,
472         .mask = 0,
473 };
474 static struct snd_ratnum es1370_clock = {
475         .num = ES_1370_SRCLOCK,
476         .den_min = 29, 
477         .den_max = 353,
478         .den_step = 1,
479 };
480 static struct snd_pcm_hw_constraint_ratnums snd_es1370_hw_constraints_clock = {
481         .nrats = 1,
482         .rats = &es1370_clock,
483 };
484 #else
485 static struct snd_ratden es1371_dac_clock = {
486         .num_min = 3000 * (1 << 15),
487         .num_max = 48000 * (1 << 15),
488         .num_step = 3000,
489         .den = 1 << 15,
490 };
491 static struct snd_pcm_hw_constraint_ratdens snd_es1371_hw_constraints_dac_clock = {
492         .nrats = 1,
493         .rats = &es1371_dac_clock,
494 };
495 static struct snd_ratnum es1371_adc_clock = {
496         .num = 48000 << 15,
497         .den_min = 32768, 
498         .den_max = 393216,
499         .den_step = 1,
500 };
501 static struct snd_pcm_hw_constraint_ratnums snd_es1371_hw_constraints_adc_clock = {
502         .nrats = 1,
503         .rats = &es1371_adc_clock,
504 };
505 #endif
506 static const unsigned int snd_ensoniq_sample_shift[] =
507         {0, 1, 1, 2};
508
509 /*
510  *  common I/O routines
511  */
512
513 #ifdef CHIP1371
514
515 static unsigned int snd_es1371_wait_src_ready(struct ensoniq * ensoniq)
516 {
517         unsigned int t, r = 0;
518
519         for (t = 0; t < POLL_COUNT; t++) {
520                 r = inl(ES_REG(ensoniq, 1371_SMPRATE));
521                 if ((r & ES_1371_SRC_RAM_BUSY) == 0)
522                         return r;
523                 cond_resched();
524         }
525         snd_printk(KERN_ERR "wait src ready timeout 0x%lx [0x%x]\n",
526                    ES_REG(ensoniq, 1371_SMPRATE), r);
527         return 0;
528 }
529
530 static unsigned int snd_es1371_src_read(struct ensoniq * ensoniq, unsigned short reg)
531 {
532         unsigned int temp, i, orig, r;
533
534         /* wait for ready */
535         temp = orig = snd_es1371_wait_src_ready(ensoniq);
536
537         /* expose the SRC state bits */
538         r = temp & (ES_1371_SRC_DISABLE | ES_1371_DIS_P1 |
539                     ES_1371_DIS_P2 | ES_1371_DIS_R1);
540         r |= ES_1371_SRC_RAM_ADDRO(reg) | 0x10000;
541         outl(r, ES_REG(ensoniq, 1371_SMPRATE));
542
543         /* now, wait for busy and the correct time to read */
544         temp = snd_es1371_wait_src_ready(ensoniq);
545         
546         if ((temp & 0x00870000) != 0x00010000) {
547                 /* wait for the right state */
548                 for (i = 0; i < POLL_COUNT; i++) {
549                         temp = inl(ES_REG(ensoniq, 1371_SMPRATE));
550                         if ((temp & 0x00870000) == 0x00010000)
551                                 break;
552                 }
553         }
554
555         /* hide the state bits */       
556         r = orig & (ES_1371_SRC_DISABLE | ES_1371_DIS_P1 |
557                    ES_1371_DIS_P2 | ES_1371_DIS_R1);
558         r |= ES_1371_SRC_RAM_ADDRO(reg);
559         outl(r, ES_REG(ensoniq, 1371_SMPRATE));
560         
561         return temp;
562 }
563
564 static void snd_es1371_src_write(struct ensoniq * ensoniq,
565                                  unsigned short reg, unsigned short data)
566 {
567         unsigned int r;
568
569         r = snd_es1371_wait_src_ready(ensoniq) &
570             (ES_1371_SRC_DISABLE | ES_1371_DIS_P1 |
571              ES_1371_DIS_P2 | ES_1371_DIS_R1);
572         r |= ES_1371_SRC_RAM_ADDRO(reg) | ES_1371_SRC_RAM_DATAO(data);
573         outl(r | ES_1371_SRC_RAM_WE, ES_REG(ensoniq, 1371_SMPRATE));
574 }
575
576 #endif /* CHIP1371 */
577
578 #ifdef CHIP1370
579
580 static void snd_es1370_codec_write(struct snd_ak4531 *ak4531,
581                                    unsigned short reg, unsigned short val)
582 {
583         struct ensoniq *ensoniq = ak4531->private_data;
584         unsigned long end_time = jiffies + HZ / 10;
585
586 #if 0
587         printk(KERN_DEBUG
588                "CODEC WRITE: reg = 0x%x, val = 0x%x (0x%x), creg = 0x%x\n",
589                reg, val, ES_1370_CODEC_WRITE(reg, val), ES_REG(ensoniq, 1370_CODEC));
590 #endif
591         do {
592                 if (!(inl(ES_REG(ensoniq, STATUS)) & ES_1370_CSTAT)) {
593                         outw(ES_1370_CODEC_WRITE(reg, val), ES_REG(ensoniq, 1370_CODEC));
594                         return;
595                 }
596                 schedule_timeout_uninterruptible(1);
597         } while (time_after(end_time, jiffies));
598         snd_printk(KERN_ERR "codec write timeout, status = 0x%x\n",
599                    inl(ES_REG(ensoniq, STATUS)));
600 }
601
602 #endif /* CHIP1370 */
603
604 #ifdef CHIP1371
605
606 static void snd_es1371_codec_write(struct snd_ac97 *ac97,
607                                    unsigned short reg, unsigned short val)
608 {
609         struct ensoniq *ensoniq = ac97->private_data;
610         unsigned int t, x;
611
612         mutex_lock(&ensoniq->src_mutex);
613         for (t = 0; t < POLL_COUNT; t++) {
614                 if (!(inl(ES_REG(ensoniq, 1371_CODEC)) & ES_1371_CODEC_WIP)) {
615                         /* save the current state for latter */
616                         x = snd_es1371_wait_src_ready(ensoniq);
617                         outl((x & (ES_1371_SRC_DISABLE | ES_1371_DIS_P1 |
618                                    ES_1371_DIS_P2 | ES_1371_DIS_R1)) | 0x00010000,
619                              ES_REG(ensoniq, 1371_SMPRATE));
620                         /* wait for not busy (state 0) first to avoid
621                            transition states */
622                         for (t = 0; t < POLL_COUNT; t++) {
623                                 if ((inl(ES_REG(ensoniq, 1371_SMPRATE)) & 0x00870000) ==
624                                     0x00000000)
625                                         break;
626                         }
627                         /* wait for a SAFE time to write addr/data and then do it, dammit */
628                         for (t = 0; t < POLL_COUNT; t++) {
629                                 if ((inl(ES_REG(ensoniq, 1371_SMPRATE)) & 0x00870000) ==
630                                     0x00010000)
631                                         break;
632                         }
633                         outl(ES_1371_CODEC_WRITE(reg, val), ES_REG(ensoniq, 1371_CODEC));
634                         /* restore SRC reg */
635                         snd_es1371_wait_src_ready(ensoniq);
636                         outl(x, ES_REG(ensoniq, 1371_SMPRATE));
637                         mutex_unlock(&ensoniq->src_mutex);
638                         return;
639                 }
640         }
641         mutex_unlock(&ensoniq->src_mutex);
642         snd_printk(KERN_ERR "codec write timeout at 0x%lx [0x%x]\n",
643                    ES_REG(ensoniq, 1371_CODEC), inl(ES_REG(ensoniq, 1371_CODEC)));
644 }
645
646 static unsigned short snd_es1371_codec_read(struct snd_ac97 *ac97,
647                                             unsigned short reg)
648 {
649         struct ensoniq *ensoniq = ac97->private_data;
650         unsigned int t, x, fail = 0;
651
652       __again:
653         mutex_lock(&ensoniq->src_mutex);
654         for (t = 0; t < POLL_COUNT; t++) {
655                 if (!(inl(ES_REG(ensoniq, 1371_CODEC)) & ES_1371_CODEC_WIP)) {
656                         /* save the current state for latter */
657                         x = snd_es1371_wait_src_ready(ensoniq);
658                         outl((x & (ES_1371_SRC_DISABLE | ES_1371_DIS_P1 |
659                                    ES_1371_DIS_P2 | ES_1371_DIS_R1)) | 0x00010000,
660                              ES_REG(ensoniq, 1371_SMPRATE));
661                         /* wait for not busy (state 0) first to avoid
662                            transition states */
663                         for (t = 0; t < POLL_COUNT; t++) {
664                                 if ((inl(ES_REG(ensoniq, 1371_SMPRATE)) & 0x00870000) ==
665                                     0x00000000)
666                                         break;
667                         }
668                         /* wait for a SAFE time to write addr/data and then do it, dammit */
669                         for (t = 0; t < POLL_COUNT; t++) {
670                                 if ((inl(ES_REG(ensoniq, 1371_SMPRATE)) & 0x00870000) ==
671                                     0x00010000)
672                                         break;
673                         }
674                         outl(ES_1371_CODEC_READS(reg), ES_REG(ensoniq, 1371_CODEC));
675                         /* restore SRC reg */
676                         snd_es1371_wait_src_ready(ensoniq);
677                         outl(x, ES_REG(ensoniq, 1371_SMPRATE));
678                         /* wait for WIP again */
679                         for (t = 0; t < POLL_COUNT; t++) {
680                                 if (!(inl(ES_REG(ensoniq, 1371_CODEC)) & ES_1371_CODEC_WIP))
681                                         break;          
682                         }
683                         /* now wait for the stinkin' data (RDY) */
684                         for (t = 0; t < POLL_COUNT; t++) {
685                                 if ((x = inl(ES_REG(ensoniq, 1371_CODEC))) & ES_1371_CODEC_RDY) {
686                                         mutex_unlock(&ensoniq->src_mutex);
687                                         return ES_1371_CODEC_READ(x);
688                                 }
689                         }
690                         mutex_unlock(&ensoniq->src_mutex);
691                         if (++fail > 10) {
692                                 snd_printk(KERN_ERR "codec read timeout (final) "
693                                            "at 0x%lx, reg = 0x%x [0x%x]\n",
694                                            ES_REG(ensoniq, 1371_CODEC), reg,
695                                            inl(ES_REG(ensoniq, 1371_CODEC)));
696                                 return 0;
697                         }
698                         goto __again;
699                 }
700         }
701         mutex_unlock(&ensoniq->src_mutex);
702         snd_printk(KERN_ERR "es1371: codec read timeout at 0x%lx [0x%x]\n",
703                    ES_REG(ensoniq, 1371_CODEC), inl(ES_REG(ensoniq, 1371_CODEC)));
704         return 0;
705 }
706
707 static void snd_es1371_codec_wait(struct snd_ac97 *ac97)
708 {
709         msleep(750);
710         snd_es1371_codec_read(ac97, AC97_RESET);
711         snd_es1371_codec_read(ac97, AC97_VENDOR_ID1);
712         snd_es1371_codec_read(ac97, AC97_VENDOR_ID2);
713         msleep(50);
714 }
715
716 static void snd_es1371_adc_rate(struct ensoniq * ensoniq, unsigned int rate)
717 {
718         unsigned int n, truncm, freq, result;
719
720         mutex_lock(&ensoniq->src_mutex);
721         n = rate / 3000;
722         if ((1 << n) & ((1 << 15) | (1 << 13) | (1 << 11) | (1 << 9)))
723                 n--;
724         truncm = (21 * n - 1) | 1;
725         freq = ((48000UL << 15) / rate) * n;
726         result = (48000UL << 15) / (freq / n);
727         if (rate >= 24000) {
728                 if (truncm > 239)
729                         truncm = 239;
730                 snd_es1371_src_write(ensoniq, ES_SMPREG_ADC + ES_SMPREG_TRUNC_N,
731                                 (((239 - truncm) >> 1) << 9) | (n << 4));
732         } else {
733                 if (truncm > 119)
734                         truncm = 119;
735                 snd_es1371_src_write(ensoniq, ES_SMPREG_ADC + ES_SMPREG_TRUNC_N,
736                                 0x8000 | (((119 - truncm) >> 1) << 9) | (n << 4));
737         }
738         snd_es1371_src_write(ensoniq, ES_SMPREG_ADC + ES_SMPREG_INT_REGS,
739                              (snd_es1371_src_read(ensoniq, ES_SMPREG_ADC +
740                                                   ES_SMPREG_INT_REGS) & 0x00ff) |
741                              ((freq >> 5) & 0xfc00));
742         snd_es1371_src_write(ensoniq, ES_SMPREG_ADC + ES_SMPREG_VFREQ_FRAC, freq & 0x7fff);
743         snd_es1371_src_write(ensoniq, ES_SMPREG_VOL_ADC, n << 8);
744         snd_es1371_src_write(ensoniq, ES_SMPREG_VOL_ADC + 1, n << 8);
745         mutex_unlock(&ensoniq->src_mutex);
746 }
747
748 static void snd_es1371_dac1_rate(struct ensoniq * ensoniq, unsigned int rate)
749 {
750         unsigned int freq, r;
751
752         mutex_lock(&ensoniq->src_mutex);
753         freq = ((rate << 15) + 1500) / 3000;
754         r = (snd_es1371_wait_src_ready(ensoniq) & (ES_1371_SRC_DISABLE |
755                                                    ES_1371_DIS_P2 | ES_1371_DIS_R1)) |
756                 ES_1371_DIS_P1;
757         outl(r, ES_REG(ensoniq, 1371_SMPRATE));
758         snd_es1371_src_write(ensoniq, ES_SMPREG_DAC1 + ES_SMPREG_INT_REGS,
759                              (snd_es1371_src_read(ensoniq, ES_SMPREG_DAC1 +
760                                                   ES_SMPREG_INT_REGS) & 0x00ff) |
761                              ((freq >> 5) & 0xfc00));
762         snd_es1371_src_write(ensoniq, ES_SMPREG_DAC1 + ES_SMPREG_VFREQ_FRAC, freq & 0x7fff);
763         r = (snd_es1371_wait_src_ready(ensoniq) & (ES_1371_SRC_DISABLE |
764                                                    ES_1371_DIS_P2 | ES_1371_DIS_R1));
765         outl(r, ES_REG(ensoniq, 1371_SMPRATE));
766         mutex_unlock(&ensoniq->src_mutex);
767 }
768
769 static void snd_es1371_dac2_rate(struct ensoniq * ensoniq, unsigned int rate)
770 {
771         unsigned int freq, r;
772
773         mutex_lock(&ensoniq->src_mutex);
774         freq = ((rate << 15) + 1500) / 3000;
775         r = (snd_es1371_wait_src_ready(ensoniq) & (ES_1371_SRC_DISABLE |
776                                                    ES_1371_DIS_P1 | ES_1371_DIS_R1)) |
777                 ES_1371_DIS_P2;
778         outl(r, ES_REG(ensoniq, 1371_SMPRATE));
779         snd_es1371_src_write(ensoniq, ES_SMPREG_DAC2 + ES_SMPREG_INT_REGS,
780                              (snd_es1371_src_read(ensoniq, ES_SMPREG_DAC2 +
781                                                   ES_SMPREG_INT_REGS) & 0x00ff) |
782                              ((freq >> 5) & 0xfc00));
783         snd_es1371_src_write(ensoniq, ES_SMPREG_DAC2 + ES_SMPREG_VFREQ_FRAC,
784                              freq & 0x7fff);
785         r = (snd_es1371_wait_src_ready(ensoniq) & (ES_1371_SRC_DISABLE |
786                                                    ES_1371_DIS_P1 | ES_1371_DIS_R1));
787         outl(r, ES_REG(ensoniq, 1371_SMPRATE));
788         mutex_unlock(&ensoniq->src_mutex);
789 }
790
791 #endif /* CHIP1371 */
792
793 static int snd_ensoniq_trigger(struct snd_pcm_substream *substream, int cmd)
794 {
795         struct ensoniq *ensoniq = snd_pcm_substream_chip(substream);
796         switch (cmd) {
797         case SNDRV_PCM_TRIGGER_PAUSE_PUSH:
798         case SNDRV_PCM_TRIGGER_PAUSE_RELEASE:
799         {
800                 unsigned int what = 0;
801                 struct snd_pcm_substream *s;
802                 snd_pcm_group_for_each_entry(s, substream) {
803                         if (s == ensoniq->playback1_substream) {
804                                 what |= ES_P1_PAUSE;
805                                 snd_pcm_trigger_done(s, substream);
806                         } else if (s == ensoniq->playback2_substream) {
807                                 what |= ES_P2_PAUSE;
808                                 snd_pcm_trigger_done(s, substream);
809                         } else if (s == ensoniq->capture_substream)
810                                 return -EINVAL;
811                 }
812                 spin_lock(&ensoniq->reg_lock);
813                 if (cmd == SNDRV_PCM_TRIGGER_PAUSE_PUSH)
814                         ensoniq->sctrl |= what;
815                 else
816                         ensoniq->sctrl &= ~what;
817                 outl(ensoniq->sctrl, ES_REG(ensoniq, SERIAL));
818                 spin_unlock(&ensoniq->reg_lock);
819                 break;
820         }
821         case SNDRV_PCM_TRIGGER_START:
822         case SNDRV_PCM_TRIGGER_STOP:
823         {
824                 unsigned int what = 0;
825                 struct snd_pcm_substream *s;
826                 snd_pcm_group_for_each_entry(s, substream) {
827                         if (s == ensoniq->playback1_substream) {
828                                 what |= ES_DAC1_EN;
829                                 snd_pcm_trigger_done(s, substream);
830                         } else if (s == ensoniq->playback2_substream) {
831                                 what |= ES_DAC2_EN;
832                                 snd_pcm_trigger_done(s, substream);
833                         } else if (s == ensoniq->capture_substream) {
834                                 what |= ES_ADC_EN;
835                                 snd_pcm_trigger_done(s, substream);
836                         }
837                 }
838                 spin_lock(&ensoniq->reg_lock);
839                 if (cmd == SNDRV_PCM_TRIGGER_START)
840                         ensoniq->ctrl |= what;
841                 else
842                         ensoniq->ctrl &= ~what;
843                 outl(ensoniq->ctrl, ES_REG(ensoniq, CONTROL));
844                 spin_unlock(&ensoniq->reg_lock);
845                 break;
846         }
847         default:
848                 return -EINVAL;
849         }
850         return 0;
851 }
852
853 /*
854  *  PCM part
855  */
856
857 static int snd_ensoniq_hw_params(struct snd_pcm_substream *substream,
858                                  struct snd_pcm_hw_params *hw_params)
859 {
860         return snd_pcm_lib_malloc_pages(substream, params_buffer_bytes(hw_params));
861 }
862
863 static int snd_ensoniq_hw_free(struct snd_pcm_substream *substream)
864 {
865         return snd_pcm_lib_free_pages(substream);
866 }
867
868 static int snd_ensoniq_playback1_prepare(struct snd_pcm_substream *substream)
869 {
870         struct ensoniq *ensoniq = snd_pcm_substream_chip(substream);
871         struct snd_pcm_runtime *runtime = substream->runtime;
872         unsigned int mode = 0;
873
874         ensoniq->p1_dma_size = snd_pcm_lib_buffer_bytes(substream);
875         ensoniq->p1_period_size = snd_pcm_lib_period_bytes(substream);
876         if (snd_pcm_format_width(runtime->format) == 16)
877                 mode |= 0x02;
878         if (runtime->channels > 1)
879                 mode |= 0x01;
880         spin_lock_irq(&ensoniq->reg_lock);
881         ensoniq->ctrl &= ~ES_DAC1_EN;
882 #ifdef CHIP1371
883         /* 48k doesn't need SRC (it breaks AC3-passthru) */
884         if (runtime->rate == 48000)
885                 ensoniq->ctrl |= ES_1373_BYPASS_P1;
886         else
887                 ensoniq->ctrl &= ~ES_1373_BYPASS_P1;
888 #endif
889         outl(ensoniq->ctrl, ES_REG(ensoniq, CONTROL));
890         outl(ES_MEM_PAGEO(ES_PAGE_DAC), ES_REG(ensoniq, MEM_PAGE));
891         outl(runtime->dma_addr, ES_REG(ensoniq, DAC1_FRAME));
892         outl((ensoniq->p1_dma_size >> 2) - 1, ES_REG(ensoniq, DAC1_SIZE));
893         ensoniq->sctrl &= ~(ES_P1_LOOP_SEL | ES_P1_PAUSE | ES_P1_SCT_RLD | ES_P1_MODEM);
894         ensoniq->sctrl |= ES_P1_INT_EN | ES_P1_MODEO(mode);
895         outl(ensoniq->sctrl, ES_REG(ensoniq, SERIAL));
896         outl((ensoniq->p1_period_size >> snd_ensoniq_sample_shift[mode]) - 1,
897              ES_REG(ensoniq, DAC1_COUNT));
898 #ifdef CHIP1370
899         ensoniq->ctrl &= ~ES_1370_WTSRSELM;
900         switch (runtime->rate) {
901         case 5512: ensoniq->ctrl |= ES_1370_WTSRSEL(0); break;
902         case 11025: ensoniq->ctrl |= ES_1370_WTSRSEL(1); break;
903         case 22050: ensoniq->ctrl |= ES_1370_WTSRSEL(2); break;
904         case 44100: ensoniq->ctrl |= ES_1370_WTSRSEL(3); break;
905         default: snd_BUG();
906         }
907 #endif
908         outl(ensoniq->ctrl, ES_REG(ensoniq, CONTROL));
909         spin_unlock_irq(&ensoniq->reg_lock);
910 #ifndef CHIP1370
911         snd_es1371_dac1_rate(ensoniq, runtime->rate);
912 #endif
913         return 0;
914 }
915
916 static int snd_ensoniq_playback2_prepare(struct snd_pcm_substream *substream)
917 {
918         struct ensoniq *ensoniq = snd_pcm_substream_chip(substream);
919         struct snd_pcm_runtime *runtime = substream->runtime;
920         unsigned int mode = 0;
921
922         ensoniq->p2_dma_size = snd_pcm_lib_buffer_bytes(substream);
923         ensoniq->p2_period_size = snd_pcm_lib_period_bytes(substream);
924         if (snd_pcm_format_width(runtime->format) == 16)
925                 mode |= 0x02;
926         if (runtime->channels > 1)
927                 mode |= 0x01;
928         spin_lock_irq(&ensoniq->reg_lock);
929         ensoniq->ctrl &= ~ES_DAC2_EN;
930         outl(ensoniq->ctrl, ES_REG(ensoniq, CONTROL));
931         outl(ES_MEM_PAGEO(ES_PAGE_DAC), ES_REG(ensoniq, MEM_PAGE));
932         outl(runtime->dma_addr, ES_REG(ensoniq, DAC2_FRAME));
933         outl((ensoniq->p2_dma_size >> 2) - 1, ES_REG(ensoniq, DAC2_SIZE));
934         ensoniq->sctrl &= ~(ES_P2_LOOP_SEL | ES_P2_PAUSE | ES_P2_DAC_SEN |
935                             ES_P2_END_INCM | ES_P2_ST_INCM | ES_P2_MODEM);
936         ensoniq->sctrl |= ES_P2_INT_EN | ES_P2_MODEO(mode) |
937                           ES_P2_END_INCO(mode & 2 ? 2 : 1) | ES_P2_ST_INCO(0);
938         outl(ensoniq->sctrl, ES_REG(ensoniq, SERIAL));
939         outl((ensoniq->p2_period_size >> snd_ensoniq_sample_shift[mode]) - 1,
940              ES_REG(ensoniq, DAC2_COUNT));
941 #ifdef CHIP1370
942         if (!(ensoniq->u.es1370.pclkdiv_lock & ES_MODE_CAPTURE)) {
943                 ensoniq->ctrl &= ~ES_1370_PCLKDIVM;
944                 ensoniq->ctrl |= ES_1370_PCLKDIVO(ES_1370_SRTODIV(runtime->rate));
945                 ensoniq->u.es1370.pclkdiv_lock |= ES_MODE_PLAY2;
946         }
947 #endif
948         outl(ensoniq->ctrl, ES_REG(ensoniq, CONTROL));
949         spin_unlock_irq(&ensoniq->reg_lock);
950 #ifndef CHIP1370
951         snd_es1371_dac2_rate(ensoniq, runtime->rate);
952 #endif
953         return 0;
954 }
955
956 static int snd_ensoniq_capture_prepare(struct snd_pcm_substream *substream)
957 {
958         struct ensoniq *ensoniq = snd_pcm_substream_chip(substream);
959         struct snd_pcm_runtime *runtime = substream->runtime;
960         unsigned int mode = 0;
961
962         ensoniq->c_dma_size = snd_pcm_lib_buffer_bytes(substream);
963         ensoniq->c_period_size = snd_pcm_lib_period_bytes(substream);
964         if (snd_pcm_format_width(runtime->format) == 16)
965                 mode |= 0x02;
966         if (runtime->channels > 1)
967                 mode |= 0x01;
968         spin_lock_irq(&ensoniq->reg_lock);
969         ensoniq->ctrl &= ~ES_ADC_EN;
970         outl(ensoniq->ctrl, ES_REG(ensoniq, CONTROL));
971         outl(ES_MEM_PAGEO(ES_PAGE_ADC), ES_REG(ensoniq, MEM_PAGE));
972         outl(runtime->dma_addr, ES_REG(ensoniq, ADC_FRAME));
973         outl((ensoniq->c_dma_size >> 2) - 1, ES_REG(ensoniq, ADC_SIZE));
974         ensoniq->sctrl &= ~(ES_R1_LOOP_SEL | ES_R1_MODEM);
975         ensoniq->sctrl |= ES_R1_INT_EN | ES_R1_MODEO(mode);
976         outl(ensoniq->sctrl, ES_REG(ensoniq, SERIAL));
977         outl((ensoniq->c_period_size >> snd_ensoniq_sample_shift[mode]) - 1,
978              ES_REG(ensoniq, ADC_COUNT));
979 #ifdef CHIP1370
980         if (!(ensoniq->u.es1370.pclkdiv_lock & ES_MODE_PLAY2)) {
981                 ensoniq->ctrl &= ~ES_1370_PCLKDIVM;
982                 ensoniq->ctrl |= ES_1370_PCLKDIVO(ES_1370_SRTODIV(runtime->rate));
983                 ensoniq->u.es1370.pclkdiv_lock |= ES_MODE_CAPTURE;
984         }
985 #endif
986         outl(ensoniq->ctrl, ES_REG(ensoniq, CONTROL));
987         spin_unlock_irq(&ensoniq->reg_lock);
988 #ifndef CHIP1370
989         snd_es1371_adc_rate(ensoniq, runtime->rate);
990 #endif
991         return 0;
992 }
993
994 static snd_pcm_uframes_t snd_ensoniq_playback1_pointer(struct snd_pcm_substream *substream)
995 {
996         struct ensoniq *ensoniq = snd_pcm_substream_chip(substream);
997         size_t ptr;
998
999         spin_lock(&ensoniq->reg_lock);
1000         if (inl(ES_REG(ensoniq, CONTROL)) & ES_DAC1_EN) {
1001                 outl(ES_MEM_PAGEO(ES_PAGE_DAC), ES_REG(ensoniq, MEM_PAGE));
1002                 ptr = ES_REG_FCURR_COUNTI(inl(ES_REG(ensoniq, DAC1_SIZE)));
1003                 ptr = bytes_to_frames(substream->runtime, ptr);
1004         } else {
1005                 ptr = 0;
1006         }
1007         spin_unlock(&ensoniq->reg_lock);
1008         return ptr;
1009 }
1010
1011 static snd_pcm_uframes_t snd_ensoniq_playback2_pointer(struct snd_pcm_substream *substream)
1012 {
1013         struct ensoniq *ensoniq = snd_pcm_substream_chip(substream);
1014         size_t ptr;
1015
1016         spin_lock(&ensoniq->reg_lock);
1017         if (inl(ES_REG(ensoniq, CONTROL)) & ES_DAC2_EN) {
1018                 outl(ES_MEM_PAGEO(ES_PAGE_DAC), ES_REG(ensoniq, MEM_PAGE));
1019                 ptr = ES_REG_FCURR_COUNTI(inl(ES_REG(ensoniq, DAC2_SIZE)));
1020                 ptr = bytes_to_frames(substream->runtime, ptr);
1021         } else {
1022                 ptr = 0;
1023         }
1024         spin_unlock(&ensoniq->reg_lock);
1025         return ptr;
1026 }
1027
1028 static snd_pcm_uframes_t snd_ensoniq_capture_pointer(struct snd_pcm_substream *substream)
1029 {
1030         struct ensoniq *ensoniq = snd_pcm_substream_chip(substream);
1031         size_t ptr;
1032
1033         spin_lock(&ensoniq->reg_lock);
1034         if (inl(ES_REG(ensoniq, CONTROL)) & ES_ADC_EN) {
1035                 outl(ES_MEM_PAGEO(ES_PAGE_ADC), ES_REG(ensoniq, MEM_PAGE));
1036                 ptr = ES_REG_FCURR_COUNTI(inl(ES_REG(ensoniq, ADC_SIZE)));
1037                 ptr = bytes_to_frames(substream->runtime, ptr);
1038         } else {
1039                 ptr = 0;
1040         }
1041         spin_unlock(&ensoniq->reg_lock);
1042         return ptr;
1043 }
1044
1045 static struct snd_pcm_hardware snd_ensoniq_playback1 =
1046 {
1047         .info =                 (SNDRV_PCM_INFO_MMAP | SNDRV_PCM_INFO_INTERLEAVED |
1048                                  SNDRV_PCM_INFO_BLOCK_TRANSFER |
1049                                  SNDRV_PCM_INFO_MMAP_VALID |
1050                                  SNDRV_PCM_INFO_PAUSE | SNDRV_PCM_INFO_SYNC_START),
1051         .formats =              SNDRV_PCM_FMTBIT_U8 | SNDRV_PCM_FMTBIT_S16_LE,
1052         .rates =
1053 #ifndef CHIP1370
1054                                 SNDRV_PCM_RATE_CONTINUOUS | SNDRV_PCM_RATE_8000_48000,
1055 #else
1056                                 (SNDRV_PCM_RATE_KNOT |  /* 5512Hz rate */
1057                                  SNDRV_PCM_RATE_11025 | SNDRV_PCM_RATE_22050 | 
1058                                  SNDRV_PCM_RATE_44100),
1059 #endif
1060         .rate_min =             4000,
1061         .rate_max =             48000,
1062         .channels_min =         1,
1063         .channels_max =         2,
1064         .buffer_bytes_max =     (128*1024),
1065         .period_bytes_min =     64,
1066         .period_bytes_max =     (128*1024),
1067         .periods_min =          1,
1068         .periods_max =          1024,
1069         .fifo_size =            0,
1070 };
1071
1072 static struct snd_pcm_hardware snd_ensoniq_playback2 =
1073 {
1074         .info =                 (SNDRV_PCM_INFO_MMAP | SNDRV_PCM_INFO_INTERLEAVED |
1075                                  SNDRV_PCM_INFO_BLOCK_TRANSFER |
1076                                  SNDRV_PCM_INFO_MMAP_VALID | SNDRV_PCM_INFO_PAUSE | 
1077                                  SNDRV_PCM_INFO_SYNC_START),
1078         .formats =              SNDRV_PCM_FMTBIT_U8 | SNDRV_PCM_FMTBIT_S16_LE,
1079         .rates =                SNDRV_PCM_RATE_CONTINUOUS | SNDRV_PCM_RATE_8000_48000,
1080         .rate_min =             4000,
1081         .rate_max =             48000,
1082         .channels_min =         1,
1083         .channels_max =         2,
1084         .buffer_bytes_max =     (128*1024),
1085         .period_bytes_min =     64,
1086         .period_bytes_max =     (128*1024),
1087         .periods_min =          1,
1088         .periods_max =          1024,
1089         .fifo_size =            0,
1090 };
1091
1092 static struct snd_pcm_hardware snd_ensoniq_capture =
1093 {
1094         .info =                 (SNDRV_PCM_INFO_MMAP | SNDRV_PCM_INFO_INTERLEAVED |
1095                                  SNDRV_PCM_INFO_BLOCK_TRANSFER |
1096                                  SNDRV_PCM_INFO_MMAP_VALID | SNDRV_PCM_INFO_SYNC_START),
1097         .formats =              SNDRV_PCM_FMTBIT_U8 | SNDRV_PCM_FMTBIT_S16_LE,
1098         .rates =                SNDRV_PCM_RATE_CONTINUOUS | SNDRV_PCM_RATE_8000_48000,
1099         .rate_min =             4000,
1100         .rate_max =             48000,
1101         .channels_min =         1,
1102         .channels_max =         2,
1103         .buffer_bytes_max =     (128*1024),
1104         .period_bytes_min =     64,
1105         .period_bytes_max =     (128*1024),
1106         .periods_min =          1,
1107         .periods_max =          1024,
1108         .fifo_size =            0,
1109 };
1110
1111 static int snd_ensoniq_playback1_open(struct snd_pcm_substream *substream)
1112 {
1113         struct ensoniq *ensoniq = snd_pcm_substream_chip(substream);
1114         struct snd_pcm_runtime *runtime = substream->runtime;
1115
1116         ensoniq->mode |= ES_MODE_PLAY1;
1117         ensoniq->playback1_substream = substream;
1118         runtime->hw = snd_ensoniq_playback1;
1119         snd_pcm_set_sync(substream);
1120         spin_lock_irq(&ensoniq->reg_lock);
1121         if (ensoniq->spdif && ensoniq->playback2_substream == NULL)
1122                 ensoniq->spdif_stream = ensoniq->spdif_default;
1123         spin_unlock_irq(&ensoniq->reg_lock);
1124 #ifdef CHIP1370
1125         snd_pcm_hw_constraint_list(runtime, 0, SNDRV_PCM_HW_PARAM_RATE,
1126                                    &snd_es1370_hw_constraints_rates);
1127 #else
1128         snd_pcm_hw_constraint_ratdens(runtime, 0, SNDRV_PCM_HW_PARAM_RATE,
1129                                       &snd_es1371_hw_constraints_dac_clock);
1130 #endif
1131         return 0;
1132 }
1133
1134 static int snd_ensoniq_playback2_open(struct snd_pcm_substream *substream)
1135 {
1136         struct ensoniq *ensoniq = snd_pcm_substream_chip(substream);
1137         struct snd_pcm_runtime *runtime = substream->runtime;
1138
1139         ensoniq->mode |= ES_MODE_PLAY2;
1140         ensoniq->playback2_substream = substream;
1141         runtime->hw = snd_ensoniq_playback2;
1142         snd_pcm_set_sync(substream);
1143         spin_lock_irq(&ensoniq->reg_lock);
1144         if (ensoniq->spdif && ensoniq->playback1_substream == NULL)
1145                 ensoniq->spdif_stream = ensoniq->spdif_default;
1146         spin_unlock_irq(&ensoniq->reg_lock);
1147 #ifdef CHIP1370
1148         snd_pcm_hw_constraint_ratnums(runtime, 0, SNDRV_PCM_HW_PARAM_RATE,
1149                                       &snd_es1370_hw_constraints_clock);
1150 #else
1151         snd_pcm_hw_constraint_ratdens(runtime, 0, SNDRV_PCM_HW_PARAM_RATE,
1152                                       &snd_es1371_hw_constraints_dac_clock);
1153 #endif
1154         return 0;
1155 }
1156
1157 static int snd_ensoniq_capture_open(struct snd_pcm_substream *substream)
1158 {
1159         struct ensoniq *ensoniq = snd_pcm_substream_chip(substream);
1160         struct snd_pcm_runtime *runtime = substream->runtime;
1161
1162         ensoniq->mode |= ES_MODE_CAPTURE;
1163         ensoniq->capture_substream = substream;
1164         runtime->hw = snd_ensoniq_capture;
1165         snd_pcm_set_sync(substream);
1166 #ifdef CHIP1370
1167         snd_pcm_hw_constraint_ratnums(runtime, 0, SNDRV_PCM_HW_PARAM_RATE,
1168                                       &snd_es1370_hw_constraints_clock);
1169 #else
1170         snd_pcm_hw_constraint_ratnums(runtime, 0, SNDRV_PCM_HW_PARAM_RATE,
1171                                       &snd_es1371_hw_constraints_adc_clock);
1172 #endif
1173         return 0;
1174 }
1175
1176 static int snd_ensoniq_playback1_close(struct snd_pcm_substream *substream)
1177 {
1178         struct ensoniq *ensoniq = snd_pcm_substream_chip(substream);
1179
1180         ensoniq->playback1_substream = NULL;
1181         ensoniq->mode &= ~ES_MODE_PLAY1;
1182         return 0;
1183 }
1184
1185 static int snd_ensoniq_playback2_close(struct snd_pcm_substream *substream)
1186 {
1187         struct ensoniq *ensoniq = snd_pcm_substream_chip(substream);
1188
1189         ensoniq->playback2_substream = NULL;
1190         spin_lock_irq(&ensoniq->reg_lock);
1191 #ifdef CHIP1370
1192         ensoniq->u.es1370.pclkdiv_lock &= ~ES_MODE_PLAY2;
1193 #endif
1194         ensoniq->mode &= ~ES_MODE_PLAY2;
1195         spin_unlock_irq(&ensoniq->reg_lock);
1196         return 0;
1197 }
1198
1199 static int snd_ensoniq_capture_close(struct snd_pcm_substream *substream)
1200 {
1201         struct ensoniq *ensoniq = snd_pcm_substream_chip(substream);
1202
1203         ensoniq->capture_substream = NULL;
1204         spin_lock_irq(&ensoniq->reg_lock);
1205 #ifdef CHIP1370
1206         ensoniq->u.es1370.pclkdiv_lock &= ~ES_MODE_CAPTURE;
1207 #endif
1208         ensoniq->mode &= ~ES_MODE_CAPTURE;
1209         spin_unlock_irq(&ensoniq->reg_lock);
1210         return 0;
1211 }
1212
1213 static struct snd_pcm_ops snd_ensoniq_playback1_ops = {
1214         .open =         snd_ensoniq_playback1_open,
1215         .close =        snd_ensoniq_playback1_close,
1216         .ioctl =        snd_pcm_lib_ioctl,
1217         .hw_params =    snd_ensoniq_hw_params,
1218         .hw_free =      snd_ensoniq_hw_free,
1219         .prepare =      snd_ensoniq_playback1_prepare,
1220         .trigger =      snd_ensoniq_trigger,
1221         .pointer =      snd_ensoniq_playback1_pointer,
1222 };
1223
1224 static struct snd_pcm_ops snd_ensoniq_playback2_ops = {
1225         .open =         snd_ensoniq_playback2_open,
1226         .close =        snd_ensoniq_playback2_close,
1227         .ioctl =        snd_pcm_lib_ioctl,
1228         .hw_params =    snd_ensoniq_hw_params,
1229         .hw_free =      snd_ensoniq_hw_free,
1230         .prepare =      snd_ensoniq_playback2_prepare,
1231         .trigger =      snd_ensoniq_trigger,
1232         .pointer =      snd_ensoniq_playback2_pointer,
1233 };
1234
1235 static struct snd_pcm_ops snd_ensoniq_capture_ops = {
1236         .open =         snd_ensoniq_capture_open,
1237         .close =        snd_ensoniq_capture_close,
1238         .ioctl =        snd_pcm_lib_ioctl,
1239         .hw_params =    snd_ensoniq_hw_params,
1240         .hw_free =      snd_ensoniq_hw_free,
1241         .prepare =      snd_ensoniq_capture_prepare,
1242         .trigger =      snd_ensoniq_trigger,
1243         .pointer =      snd_ensoniq_capture_pointer,
1244 };
1245
1246 static int __devinit snd_ensoniq_pcm(struct ensoniq * ensoniq, int device,
1247                                      struct snd_pcm ** rpcm)
1248 {
1249         struct snd_pcm *pcm;
1250         int err;
1251
1252         if (rpcm)
1253                 *rpcm = NULL;
1254 #ifdef CHIP1370
1255         err = snd_pcm_new(ensoniq->card, "ES1370/1", device, 1, 1, &pcm);
1256 #else
1257         err = snd_pcm_new(ensoniq->card, "ES1371/1", device, 1, 1, &pcm);
1258 #endif
1259         if (err < 0)
1260                 return err;
1261
1262 #ifdef CHIP1370
1263         snd_pcm_set_ops(pcm, SNDRV_PCM_STREAM_PLAYBACK, &snd_ensoniq_playback2_ops);
1264 #else
1265         snd_pcm_set_ops(pcm, SNDRV_PCM_STREAM_PLAYBACK, &snd_ensoniq_playback1_ops);
1266 #endif
1267         snd_pcm_set_ops(pcm, SNDRV_PCM_STREAM_CAPTURE, &snd_ensoniq_capture_ops);
1268
1269         pcm->private_data = ensoniq;
1270         pcm->info_flags = 0;
1271 #ifdef CHIP1370
1272         strcpy(pcm->name, "ES1370 DAC2/ADC");
1273 #else
1274         strcpy(pcm->name, "ES1371 DAC2/ADC");
1275 #endif
1276         ensoniq->pcm1 = pcm;
1277
1278         snd_pcm_lib_preallocate_pages_for_all(pcm, SNDRV_DMA_TYPE_DEV,
1279                                               snd_dma_pci_data(ensoniq->pci), 64*1024, 128*1024);
1280
1281         if (rpcm)
1282                 *rpcm = pcm;
1283         return 0;
1284 }
1285
1286 static int __devinit snd_ensoniq_pcm2(struct ensoniq * ensoniq, int device,
1287                                       struct snd_pcm ** rpcm)
1288 {
1289         struct snd_pcm *pcm;
1290         int err;
1291
1292         if (rpcm)
1293                 *rpcm = NULL;
1294 #ifdef CHIP1370
1295         err = snd_pcm_new(ensoniq->card, "ES1370/2", device, 1, 0, &pcm);
1296 #else
1297         err = snd_pcm_new(ensoniq->card, "ES1371/2", device, 1, 0, &pcm);
1298 #endif
1299         if (err < 0)
1300                 return err;
1301
1302 #ifdef CHIP1370
1303         snd_pcm_set_ops(pcm, SNDRV_PCM_STREAM_PLAYBACK, &snd_ensoniq_playback1_ops);
1304 #else
1305         snd_pcm_set_ops(pcm, SNDRV_PCM_STREAM_PLAYBACK, &snd_ensoniq_playback2_ops);
1306 #endif
1307         pcm->private_data = ensoniq;
1308         pcm->info_flags = 0;
1309 #ifdef CHIP1370
1310         strcpy(pcm->name, "ES1370 DAC1");
1311 #else
1312         strcpy(pcm->name, "ES1371 DAC1");
1313 #endif
1314         ensoniq->pcm2 = pcm;
1315
1316         snd_pcm_lib_preallocate_pages_for_all(pcm, SNDRV_DMA_TYPE_DEV,
1317                                               snd_dma_pci_data(ensoniq->pci), 64*1024, 128*1024);
1318
1319         if (rpcm)
1320                 *rpcm = pcm;
1321         return 0;
1322 }
1323
1324 /*
1325  *  Mixer section
1326  */
1327
1328 /*
1329  * ENS1371 mixer (including SPDIF interface)
1330  */
1331 #ifdef CHIP1371
1332 static int snd_ens1373_spdif_info(struct snd_kcontrol *kcontrol,
1333                                   struct snd_ctl_elem_info *uinfo)
1334 {
1335         uinfo->type = SNDRV_CTL_ELEM_TYPE_IEC958;
1336         uinfo->count = 1;
1337         return 0;
1338 }
1339
1340 static int snd_ens1373_spdif_default_get(struct snd_kcontrol *kcontrol,
1341                                          struct snd_ctl_elem_value *ucontrol)
1342 {
1343         struct ensoniq *ensoniq = snd_kcontrol_chip(kcontrol);
1344         spin_lock_irq(&ensoniq->reg_lock);
1345         ucontrol->value.iec958.status[0] = (ensoniq->spdif_default >> 0) & 0xff;
1346         ucontrol->value.iec958.status[1] = (ensoniq->spdif_default >> 8) & 0xff;
1347         ucontrol->value.iec958.status[2] = (ensoniq->spdif_default >> 16) & 0xff;
1348         ucontrol->value.iec958.status[3] = (ensoniq->spdif_default >> 24) & 0xff;
1349         spin_unlock_irq(&ensoniq->reg_lock);
1350         return 0;
1351 }
1352
1353 static int snd_ens1373_spdif_default_put(struct snd_kcontrol *kcontrol,
1354                                          struct snd_ctl_elem_value *ucontrol)
1355 {
1356         struct ensoniq *ensoniq = snd_kcontrol_chip(kcontrol);
1357         unsigned int val;
1358         int change;
1359
1360         val = ((u32)ucontrol->value.iec958.status[0] << 0) |
1361               ((u32)ucontrol->value.iec958.status[1] << 8) |
1362               ((u32)ucontrol->value.iec958.status[2] << 16) |
1363               ((u32)ucontrol->value.iec958.status[3] << 24);
1364         spin_lock_irq(&ensoniq->reg_lock);
1365         change = ensoniq->spdif_default != val;
1366         ensoniq->spdif_default = val;
1367         if (change && ensoniq->playback1_substream == NULL &&
1368             ensoniq->playback2_substream == NULL)
1369                 outl(val, ES_REG(ensoniq, CHANNEL_STATUS));
1370         spin_unlock_irq(&ensoniq->reg_lock);
1371         return change;
1372 }
1373
1374 static int snd_ens1373_spdif_mask_get(struct snd_kcontrol *kcontrol,
1375                                       struct snd_ctl_elem_value *ucontrol)
1376 {
1377         ucontrol->value.iec958.status[0] = 0xff;
1378         ucontrol->value.iec958.status[1] = 0xff;
1379         ucontrol->value.iec958.status[2] = 0xff;
1380         ucontrol->value.iec958.status[3] = 0xff;
1381         return 0;
1382 }
1383
1384 static int snd_ens1373_spdif_stream_get(struct snd_kcontrol *kcontrol,
1385                                         struct snd_ctl_elem_value *ucontrol)
1386 {
1387         struct ensoniq *ensoniq = snd_kcontrol_chip(kcontrol);
1388         spin_lock_irq(&ensoniq->reg_lock);
1389         ucontrol->value.iec958.status[0] = (ensoniq->spdif_stream >> 0) & 0xff;
1390         ucontrol->value.iec958.status[1] = (ensoniq->spdif_stream >> 8) & 0xff;
1391         ucontrol->value.iec958.status[2] = (ensoniq->spdif_stream >> 16) & 0xff;
1392         ucontrol->value.iec958.status[3] = (ensoniq->spdif_stream >> 24) & 0xff;
1393         spin_unlock_irq(&ensoniq->reg_lock);
1394         return 0;
1395 }
1396
1397 static int snd_ens1373_spdif_stream_put(struct snd_kcontrol *kcontrol,
1398                                         struct snd_ctl_elem_value *ucontrol)
1399 {
1400         struct ensoniq *ensoniq = snd_kcontrol_chip(kcontrol);
1401         unsigned int val;
1402         int change;
1403
1404         val = ((u32)ucontrol->value.iec958.status[0] << 0) |
1405               ((u32)ucontrol->value.iec958.status[1] << 8) |
1406               ((u32)ucontrol->value.iec958.status[2] << 16) |
1407               ((u32)ucontrol->value.iec958.status[3] << 24);
1408         spin_lock_irq(&ensoniq->reg_lock);
1409         change = ensoniq->spdif_stream != val;
1410         ensoniq->spdif_stream = val;
1411         if (change && (ensoniq->playback1_substream != NULL ||
1412                        ensoniq->playback2_substream != NULL))
1413                 outl(val, ES_REG(ensoniq, CHANNEL_STATUS));
1414         spin_unlock_irq(&ensoniq->reg_lock);
1415         return change;
1416 }
1417
1418 #define ES1371_SPDIF(xname) \
1419 { .iface = SNDRV_CTL_ELEM_IFACE_MIXER, .name = xname, .info = snd_es1371_spdif_info, \
1420   .get = snd_es1371_spdif_get, .put = snd_es1371_spdif_put }
1421
1422 #define snd_es1371_spdif_info           snd_ctl_boolean_mono_info
1423
1424 static int snd_es1371_spdif_get(struct snd_kcontrol *kcontrol,
1425                                 struct snd_ctl_elem_value *ucontrol)
1426 {
1427         struct ensoniq *ensoniq = snd_kcontrol_chip(kcontrol);
1428         
1429         spin_lock_irq(&ensoniq->reg_lock);
1430         ucontrol->value.integer.value[0] = ensoniq->ctrl & ES_1373_SPDIF_THRU ? 1 : 0;
1431         spin_unlock_irq(&ensoniq->reg_lock);
1432         return 0;
1433 }
1434
1435 static int snd_es1371_spdif_put(struct snd_kcontrol *kcontrol,
1436                                 struct snd_ctl_elem_value *ucontrol)
1437 {
1438         struct ensoniq *ensoniq = snd_kcontrol_chip(kcontrol);
1439         unsigned int nval1, nval2;
1440         int change;
1441         
1442         nval1 = ucontrol->value.integer.value[0] ? ES_1373_SPDIF_THRU : 0;
1443         nval2 = ucontrol->value.integer.value[0] ? ES_1373_SPDIF_EN : 0;
1444         spin_lock_irq(&ensoniq->reg_lock);
1445         change = (ensoniq->ctrl & ES_1373_SPDIF_THRU) != nval1;
1446         ensoniq->ctrl &= ~ES_1373_SPDIF_THRU;
1447         ensoniq->ctrl |= nval1;
1448         ensoniq->cssr &= ~ES_1373_SPDIF_EN;
1449         ensoniq->cssr |= nval2;
1450         outl(ensoniq->ctrl, ES_REG(ensoniq, CONTROL));
1451         outl(ensoniq->cssr, ES_REG(ensoniq, STATUS));
1452         spin_unlock_irq(&ensoniq->reg_lock);
1453         return change;
1454 }
1455
1456
1457 /* spdif controls */
1458 static struct snd_kcontrol_new snd_es1371_mixer_spdif[] __devinitdata = {
1459         ES1371_SPDIF(SNDRV_CTL_NAME_IEC958("",PLAYBACK,SWITCH)),
1460         {
1461                 .iface =        SNDRV_CTL_ELEM_IFACE_PCM,
1462                 .name =         SNDRV_CTL_NAME_IEC958("",PLAYBACK,DEFAULT),
1463                 .info =         snd_ens1373_spdif_info,
1464                 .get =          snd_ens1373_spdif_default_get,
1465                 .put =          snd_ens1373_spdif_default_put,
1466         },
1467         {
1468                 .access =       SNDRV_CTL_ELEM_ACCESS_READ,
1469                 .iface =        SNDRV_CTL_ELEM_IFACE_PCM,
1470                 .name =         SNDRV_CTL_NAME_IEC958("",PLAYBACK,MASK),
1471                 .info =         snd_ens1373_spdif_info,
1472                 .get =          snd_ens1373_spdif_mask_get
1473         },
1474         {
1475                 .iface =        SNDRV_CTL_ELEM_IFACE_PCM,
1476                 .name =         SNDRV_CTL_NAME_IEC958("",PLAYBACK,PCM_STREAM),
1477                 .info =         snd_ens1373_spdif_info,
1478                 .get =          snd_ens1373_spdif_stream_get,
1479                 .put =          snd_ens1373_spdif_stream_put
1480         },
1481 };
1482
1483
1484 #define snd_es1373_rear_info            snd_ctl_boolean_mono_info
1485
1486 static int snd_es1373_rear_get(struct snd_kcontrol *kcontrol,
1487                                struct snd_ctl_elem_value *ucontrol)
1488 {
1489         struct ensoniq *ensoniq = snd_kcontrol_chip(kcontrol);
1490         int val = 0;
1491         
1492         spin_lock_irq(&ensoniq->reg_lock);
1493         if ((ensoniq->cssr & (ES_1373_REAR_BIT27|ES_1373_REAR_BIT26|
1494                               ES_1373_REAR_BIT24)) == ES_1373_REAR_BIT26)
1495                 val = 1;
1496         ucontrol->value.integer.value[0] = val;
1497         spin_unlock_irq(&ensoniq->reg_lock);
1498         return 0;
1499 }
1500
1501 static int snd_es1373_rear_put(struct snd_kcontrol *kcontrol,
1502                                struct snd_ctl_elem_value *ucontrol)
1503 {
1504         struct ensoniq *ensoniq = snd_kcontrol_chip(kcontrol);
1505         unsigned int nval1;
1506         int change;
1507         
1508         nval1 = ucontrol->value.integer.value[0] ?
1509                 ES_1373_REAR_BIT26 : (ES_1373_REAR_BIT27|ES_1373_REAR_BIT24);
1510         spin_lock_irq(&ensoniq->reg_lock);
1511         change = (ensoniq->cssr & (ES_1373_REAR_BIT27|
1512                                    ES_1373_REAR_BIT26|ES_1373_REAR_BIT24)) != nval1;
1513         ensoniq->cssr &= ~(ES_1373_REAR_BIT27|ES_1373_REAR_BIT26|ES_1373_REAR_BIT24);
1514         ensoniq->cssr |= nval1;
1515         outl(ensoniq->cssr, ES_REG(ensoniq, STATUS));
1516         spin_unlock_irq(&ensoniq->reg_lock);
1517         return change;
1518 }
1519
1520 static struct snd_kcontrol_new snd_ens1373_rear __devinitdata =
1521 {
1522         .iface =        SNDRV_CTL_ELEM_IFACE_MIXER,
1523         .name =         "AC97 2ch->4ch Copy Switch",
1524         .info =         snd_es1373_rear_info,
1525         .get =          snd_es1373_rear_get,
1526         .put =          snd_es1373_rear_put,
1527 };
1528
1529 #define snd_es1373_line_info            snd_ctl_boolean_mono_info
1530
1531 static int snd_es1373_line_get(struct snd_kcontrol *kcontrol,
1532                                struct snd_ctl_elem_value *ucontrol)
1533 {
1534         struct ensoniq *ensoniq = snd_kcontrol_chip(kcontrol);
1535         int val = 0;
1536         
1537         spin_lock_irq(&ensoniq->reg_lock);
1538         if ((ensoniq->ctrl & ES_1371_GPIO_OUTM) >= 4)
1539                 val = 1;
1540         ucontrol->value.integer.value[0] = val;
1541         spin_unlock_irq(&ensoniq->reg_lock);
1542         return 0;
1543 }
1544
1545 static int snd_es1373_line_put(struct snd_kcontrol *kcontrol,
1546                                struct snd_ctl_elem_value *ucontrol)
1547 {
1548         struct ensoniq *ensoniq = snd_kcontrol_chip(kcontrol);
1549         int changed;
1550         unsigned int ctrl;
1551         
1552         spin_lock_irq(&ensoniq->reg_lock);
1553         ctrl = ensoniq->ctrl;
1554         if (ucontrol->value.integer.value[0])
1555                 ensoniq->ctrl |= ES_1371_GPIO_OUT(4);   /* switch line-in -> rear out */
1556         else
1557                 ensoniq->ctrl &= ~ES_1371_GPIO_OUT(4);
1558         changed = (ctrl != ensoniq->ctrl);
1559         if (changed)
1560                 outl(ensoniq->ctrl, ES_REG(ensoniq, CONTROL));
1561         spin_unlock_irq(&ensoniq->reg_lock);
1562         return changed;
1563 }
1564
1565 static struct snd_kcontrol_new snd_ens1373_line __devinitdata =
1566 {
1567         .iface =        SNDRV_CTL_ELEM_IFACE_MIXER,
1568         .name =         "Line In->Rear Out Switch",
1569         .info =         snd_es1373_line_info,
1570         .get =          snd_es1373_line_get,
1571         .put =          snd_es1373_line_put,
1572 };
1573
1574 static void snd_ensoniq_mixer_free_ac97(struct snd_ac97 *ac97)
1575 {
1576         struct ensoniq *ensoniq = ac97->private_data;
1577         ensoniq->u.es1371.ac97 = NULL;
1578 }
1579
1580 struct es1371_quirk {
1581         unsigned short vid;             /* vendor ID */
1582         unsigned short did;             /* device ID */
1583         unsigned char rev;              /* revision */
1584 };
1585
1586 static int es1371_quirk_lookup(struct ensoniq *ensoniq,
1587                                 struct es1371_quirk *list)
1588 {
1589         while (list->vid != (unsigned short)PCI_ANY_ID) {
1590                 if (ensoniq->pci->vendor == list->vid &&
1591                     ensoniq->pci->device == list->did &&
1592                     ensoniq->rev == list->rev)
1593                         return 1;
1594                 list++;
1595         }
1596         return 0;
1597 }
1598
1599 static struct es1371_quirk es1371_spdif_present[] __devinitdata = {
1600         { .vid = PCI_VENDOR_ID_ENSONIQ, .did = PCI_DEVICE_ID_ENSONIQ_CT5880, .rev = CT5880REV_CT5880_C },
1601         { .vid = PCI_VENDOR_ID_ENSONIQ, .did = PCI_DEVICE_ID_ENSONIQ_CT5880, .rev = CT5880REV_CT5880_D },
1602         { .vid = PCI_VENDOR_ID_ENSONIQ, .did = PCI_DEVICE_ID_ENSONIQ_CT5880, .rev = CT5880REV_CT5880_E },
1603         { .vid = PCI_VENDOR_ID_ENSONIQ, .did = PCI_DEVICE_ID_ENSONIQ_ES1371, .rev = ES1371REV_CT5880_A },
1604         { .vid = PCI_VENDOR_ID_ENSONIQ, .did = PCI_DEVICE_ID_ENSONIQ_ES1371, .rev = ES1371REV_ES1373_8 },
1605         { .vid = PCI_ANY_ID, .did = PCI_ANY_ID }
1606 };
1607
1608 static struct snd_pci_quirk ens1373_line_quirk[] __devinitdata = {
1609         SND_PCI_QUIRK_ID(0x1274, 0x2000), /* GA-7DXR */
1610         SND_PCI_QUIRK_ID(0x1458, 0xa000), /* GA-8IEXP */
1611         { } /* end */
1612 };
1613
1614 static int __devinit snd_ensoniq_1371_mixer(struct ensoniq *ensoniq,
1615                                             int has_spdif, int has_line)
1616 {
1617         struct snd_card *card = ensoniq->card;
1618         struct snd_ac97_bus *pbus;
1619         struct snd_ac97_template ac97;
1620         int err;
1621         static struct snd_ac97_bus_ops ops = {
1622                 .write = snd_es1371_codec_write,
1623                 .read = snd_es1371_codec_read,
1624                 .wait = snd_es1371_codec_wait,
1625         };
1626
1627         if ((err = snd_ac97_bus(card, 0, &ops, NULL, &pbus)) < 0)
1628                 return err;
1629
1630         memset(&ac97, 0, sizeof(ac97));
1631         ac97.private_data = ensoniq;
1632         ac97.private_free = snd_ensoniq_mixer_free_ac97;
1633         ac97.pci = ensoniq->pci;
1634         ac97.scaps = AC97_SCAP_AUDIO;
1635         if ((err = snd_ac97_mixer(pbus, &ac97, &ensoniq->u.es1371.ac97)) < 0)
1636                 return err;
1637         if (has_spdif > 0 ||
1638             (!has_spdif && es1371_quirk_lookup(ensoniq, es1371_spdif_present))) {
1639                 struct snd_kcontrol *kctl;
1640                 int i, is_spdif = 0;
1641
1642                 ensoniq->spdif_default = ensoniq->spdif_stream =
1643                         SNDRV_PCM_DEFAULT_CON_SPDIF;
1644                 outl(ensoniq->spdif_default, ES_REG(ensoniq, CHANNEL_STATUS));
1645
1646                 if (ensoniq->u.es1371.ac97->ext_id & AC97_EI_SPDIF)
1647                         is_spdif++;
1648
1649                 for (i = 0; i < ARRAY_SIZE(snd_es1371_mixer_spdif); i++) {
1650                         kctl = snd_ctl_new1(&snd_es1371_mixer_spdif[i], ensoniq);
1651                         if (!kctl)
1652                                 return -ENOMEM;
1653                         kctl->id.index = is_spdif;
1654                         err = snd_ctl_add(card, kctl);
1655                         if (err < 0)
1656                                 return err;
1657                 }
1658         }
1659         if (ensoniq->u.es1371.ac97->ext_id & AC97_EI_SDAC) {
1660                 /* mirror rear to front speakers */
1661                 ensoniq->cssr &= ~(ES_1373_REAR_BIT27|ES_1373_REAR_BIT24);
1662                 ensoniq->cssr |= ES_1373_REAR_BIT26;
1663                 err = snd_ctl_add(card, snd_ctl_new1(&snd_ens1373_rear, ensoniq));
1664                 if (err < 0)
1665                         return err;
1666         }
1667         if (has_line > 0 ||
1668             snd_pci_quirk_lookup(ensoniq->pci, ens1373_line_quirk)) {
1669                  err = snd_ctl_add(card, snd_ctl_new1(&snd_ens1373_line,
1670                                                       ensoniq));
1671                  if (err < 0)
1672                          return err;
1673         }
1674
1675         return 0;
1676 }
1677
1678 #endif /* CHIP1371 */
1679
1680 /* generic control callbacks for ens1370 */
1681 #ifdef CHIP1370
1682 #define ENSONIQ_CONTROL(xname, mask) \
1683 { .iface = SNDRV_CTL_ELEM_IFACE_CARD, .name = xname, .info = snd_ensoniq_control_info, \
1684   .get = snd_ensoniq_control_get, .put = snd_ensoniq_control_put, \
1685   .private_value = mask }
1686
1687 #define snd_ensoniq_control_info        snd_ctl_boolean_mono_info
1688
1689 static int snd_ensoniq_control_get(struct snd_kcontrol *kcontrol,
1690                                    struct snd_ctl_elem_value *ucontrol)
1691 {
1692         struct ensoniq *ensoniq = snd_kcontrol_chip(kcontrol);
1693         int mask = kcontrol->private_value;
1694         
1695         spin_lock_irq(&ensoniq->reg_lock);
1696         ucontrol->value.integer.value[0] = ensoniq->ctrl & mask ? 1 : 0;
1697         spin_unlock_irq(&ensoniq->reg_lock);
1698         return 0;
1699 }
1700
1701 static int snd_ensoniq_control_put(struct snd_kcontrol *kcontrol,
1702                                    struct snd_ctl_elem_value *ucontrol)
1703 {
1704         struct ensoniq *ensoniq = snd_kcontrol_chip(kcontrol);
1705         int mask = kcontrol->private_value;
1706         unsigned int nval;
1707         int change;
1708         
1709         nval = ucontrol->value.integer.value[0] ? mask : 0;
1710         spin_lock_irq(&ensoniq->reg_lock);
1711         change = (ensoniq->ctrl & mask) != nval;
1712         ensoniq->ctrl &= ~mask;
1713         ensoniq->ctrl |= nval;
1714         outl(ensoniq->ctrl, ES_REG(ensoniq, CONTROL));
1715         spin_unlock_irq(&ensoniq->reg_lock);
1716         return change;
1717 }
1718
1719 /*
1720  * ENS1370 mixer
1721  */
1722
1723 static struct snd_kcontrol_new snd_es1370_controls[2] __devinitdata = {
1724 ENSONIQ_CONTROL("PCM 0 Output also on Line-In Jack", ES_1370_XCTL0),
1725 ENSONIQ_CONTROL("Mic +5V bias", ES_1370_XCTL1)
1726 };
1727
1728 #define ES1370_CONTROLS ARRAY_SIZE(snd_es1370_controls)
1729
1730 static void snd_ensoniq_mixer_free_ak4531(struct snd_ak4531 *ak4531)
1731 {
1732         struct ensoniq *ensoniq = ak4531->private_data;
1733         ensoniq->u.es1370.ak4531 = NULL;
1734 }
1735
1736 static int __devinit snd_ensoniq_1370_mixer(struct ensoniq * ensoniq)
1737 {
1738         struct snd_card *card = ensoniq->card;
1739         struct snd_ak4531 ak4531;
1740         unsigned int idx;
1741         int err;
1742
1743         /* try reset AK4531 */
1744         outw(ES_1370_CODEC_WRITE(AK4531_RESET, 0x02), ES_REG(ensoniq, 1370_CODEC));
1745         inw(ES_REG(ensoniq, 1370_CODEC));
1746         udelay(100);
1747         outw(ES_1370_CODEC_WRITE(AK4531_RESET, 0x03), ES_REG(ensoniq, 1370_CODEC));
1748         inw(ES_REG(ensoniq, 1370_CODEC));
1749         udelay(100);
1750
1751         memset(&ak4531, 0, sizeof(ak4531));
1752         ak4531.write = snd_es1370_codec_write;
1753         ak4531.private_data = ensoniq;
1754         ak4531.private_free = snd_ensoniq_mixer_free_ak4531;
1755         if ((err = snd_ak4531_mixer(card, &ak4531, &ensoniq->u.es1370.ak4531)) < 0)
1756                 return err;
1757         for (idx = 0; idx < ES1370_CONTROLS; idx++) {
1758                 err = snd_ctl_add(card, snd_ctl_new1(&snd_es1370_controls[idx], ensoniq));
1759                 if (err < 0)
1760                         return err;
1761         }
1762         return 0;
1763 }
1764
1765 #endif /* CHIP1370 */
1766
1767 #ifdef SUPPORT_JOYSTICK
1768
1769 #ifdef CHIP1371
1770 static int __devinit snd_ensoniq_get_joystick_port(int dev)
1771 {
1772         switch (joystick_port[dev]) {
1773         case 0: /* disabled */
1774         case 1: /* auto-detect */
1775         case 0x200:
1776         case 0x208:
1777         case 0x210:
1778         case 0x218:
1779                 return joystick_port[dev];
1780
1781         default:
1782                 printk(KERN_ERR "ens1371: invalid joystick port %#x", joystick_port[dev]);
1783                 return 0;
1784         }
1785 }
1786 #else
1787 static inline int snd_ensoniq_get_joystick_port(int dev)
1788 {
1789         return joystick[dev] ? 0x200 : 0;
1790 }
1791 #endif
1792
1793 static int __devinit snd_ensoniq_create_gameport(struct ensoniq *ensoniq, int dev)
1794 {
1795         struct gameport *gp;
1796         int io_port;
1797
1798         io_port = snd_ensoniq_get_joystick_port(dev);
1799
1800         switch (io_port) {
1801         case 0:
1802                 return -ENOSYS;
1803
1804         case 1: /* auto_detect */
1805                 for (io_port = 0x200; io_port <= 0x218; io_port += 8)
1806                         if (request_region(io_port, 8, "ens137x: gameport"))
1807                                 break;
1808                 if (io_port > 0x218) {
1809                         printk(KERN_WARNING "ens137x: no gameport ports available\n");
1810                         return -EBUSY;
1811                 }
1812                 break;
1813
1814         default:
1815                 if (!request_region(io_port, 8, "ens137x: gameport")) {
1816                         printk(KERN_WARNING "ens137x: gameport io port 0x%#x in use\n",
1817                                io_port);
1818                         return -EBUSY;
1819                 }
1820                 break;
1821         }
1822
1823         ensoniq->gameport = gp = gameport_allocate_port();
1824         if (!gp) {
1825                 printk(KERN_ERR "ens137x: cannot allocate memory for gameport\n");
1826                 release_region(io_port, 8);
1827                 return -ENOMEM;
1828         }
1829
1830         gameport_set_name(gp, "ES137x");
1831         gameport_set_phys(gp, "pci%s/gameport0", pci_name(ensoniq->pci));
1832         gameport_set_dev_parent(gp, &ensoniq->pci->dev);
1833         gp->io = io_port;
1834
1835         ensoniq->ctrl |= ES_JYSTK_EN;
1836 #ifdef CHIP1371
1837         ensoniq->ctrl &= ~ES_1371_JOY_ASELM;
1838         ensoniq->ctrl |= ES_1371_JOY_ASEL((io_port - 0x200) / 8);
1839 #endif
1840         outl(ensoniq->ctrl, ES_REG(ensoniq, CONTROL));
1841
1842         gameport_register_port(ensoniq->gameport);
1843
1844         return 0;
1845 }
1846
1847 static void snd_ensoniq_free_gameport(struct ensoniq *ensoniq)
1848 {
1849         if (ensoniq->gameport) {
1850                 int port = ensoniq->gameport->io;
1851
1852                 gameport_unregister_port(ensoniq->gameport);
1853                 ensoniq->gameport = NULL;
1854                 ensoniq->ctrl &= ~ES_JYSTK_EN;
1855                 outl(ensoniq->ctrl, ES_REG(ensoniq, CONTROL));
1856                 release_region(port, 8);
1857         }
1858 }
1859 #else
1860 static inline int snd_ensoniq_create_gameport(struct ensoniq *ensoniq, long port) { return -ENOSYS; }
1861 static inline void snd_ensoniq_free_gameport(struct ensoniq *ensoniq) { }
1862 #endif /* SUPPORT_JOYSTICK */
1863
1864 /*
1865
1866  */
1867
1868 static void snd_ensoniq_proc_read(struct snd_info_entry *entry, 
1869                                   struct snd_info_buffer *buffer)
1870 {
1871         struct ensoniq *ensoniq = entry->private_data;
1872
1873 #ifdef CHIP1370
1874         snd_iprintf(buffer, "Ensoniq AudioPCI ES1370\n\n");
1875 #else
1876         snd_iprintf(buffer, "Ensoniq AudioPCI ES1371\n\n");
1877 #endif
1878         snd_iprintf(buffer, "Joystick enable  : %s\n",
1879                     ensoniq->ctrl & ES_JYSTK_EN ? "on" : "off");
1880 #ifdef CHIP1370
1881         snd_iprintf(buffer, "MIC +5V bias     : %s\n",
1882                     ensoniq->ctrl & ES_1370_XCTL1 ? "on" : "off");
1883         snd_iprintf(buffer, "Line In to AOUT  : %s\n",
1884                     ensoniq->ctrl & ES_1370_XCTL0 ? "on" : "off");
1885 #else
1886         snd_iprintf(buffer, "Joystick port    : 0x%x\n",
1887                     (ES_1371_JOY_ASELI(ensoniq->ctrl) * 8) + 0x200);
1888 #endif
1889 }
1890
1891 static void __devinit snd_ensoniq_proc_init(struct ensoniq * ensoniq)
1892 {
1893         struct snd_info_entry *entry;
1894
1895         if (! snd_card_proc_new(ensoniq->card, "audiopci", &entry))
1896                 snd_info_set_text_ops(entry, ensoniq, snd_ensoniq_proc_read);
1897 }
1898
1899 /*
1900
1901  */
1902
1903 static int snd_ensoniq_free(struct ensoniq *ensoniq)
1904 {
1905         snd_ensoniq_free_gameport(ensoniq);
1906         if (ensoniq->irq < 0)
1907                 goto __hw_end;
1908 #ifdef CHIP1370
1909         outl(ES_1370_SERR_DISABLE, ES_REG(ensoniq, CONTROL));   /* switch everything off */
1910         outl(0, ES_REG(ensoniq, SERIAL));       /* clear serial interface */
1911 #else
1912         outl(0, ES_REG(ensoniq, CONTROL));      /* switch everything off */
1913         outl(0, ES_REG(ensoniq, SERIAL));       /* clear serial interface */
1914 #endif
1915         if (ensoniq->irq >= 0)
1916                 synchronize_irq(ensoniq->irq);
1917         pci_set_power_state(ensoniq->pci, 3);
1918       __hw_end:
1919 #ifdef CHIP1370
1920         if (ensoniq->dma_bug.area)
1921                 snd_dma_free_pages(&ensoniq->dma_bug);
1922 #endif
1923         if (ensoniq->irq >= 0)
1924                 free_irq(ensoniq->irq, ensoniq);
1925         pci_release_regions(ensoniq->pci);
1926         pci_disable_device(ensoniq->pci);
1927         kfree(ensoniq);
1928         return 0;
1929 }
1930
1931 static int snd_ensoniq_dev_free(struct snd_device *device)
1932 {
1933         struct ensoniq *ensoniq = device->device_data;
1934         return snd_ensoniq_free(ensoniq);
1935 }
1936
1937 #ifdef CHIP1371
1938 static struct snd_pci_quirk es1371_amplifier_hack[] __devinitdata = {
1939         SND_PCI_QUIRK_ID(0x107b, 0x2150),       /* Gateway Solo 2150 */
1940         SND_PCI_QUIRK_ID(0x13bd, 0x100c),       /* EV1938 on Mebius PC-MJ100V */
1941         SND_PCI_QUIRK_ID(0x1102, 0x5938),       /* Targa Xtender300 */
1942         SND_PCI_QUIRK_ID(0x1102, 0x8938),       /* IPC Topnote G notebook */
1943         { } /* end */
1944 };
1945
1946 static struct es1371_quirk es1371_ac97_reset_hack[] = {
1947         { .vid = PCI_VENDOR_ID_ENSONIQ, .did = PCI_DEVICE_ID_ENSONIQ_CT5880, .rev = CT5880REV_CT5880_C },
1948         { .vid = PCI_VENDOR_ID_ENSONIQ, .did = PCI_DEVICE_ID_ENSONIQ_CT5880, .rev = CT5880REV_CT5880_D },
1949         { .vid = PCI_VENDOR_ID_ENSONIQ, .did = PCI_DEVICE_ID_ENSONIQ_CT5880, .rev = CT5880REV_CT5880_E },
1950         { .vid = PCI_VENDOR_ID_ENSONIQ, .did = PCI_DEVICE_ID_ENSONIQ_ES1371, .rev = ES1371REV_CT5880_A },
1951         { .vid = PCI_VENDOR_ID_ENSONIQ, .did = PCI_DEVICE_ID_ENSONIQ_ES1371, .rev = ES1371REV_ES1373_8 },
1952         { .vid = PCI_ANY_ID, .did = PCI_ANY_ID }
1953 };
1954 #endif
1955
1956 static void snd_ensoniq_chip_init(struct ensoniq *ensoniq)
1957 {
1958 #ifdef CHIP1371
1959         int idx;
1960 #endif
1961         /* this code was part of snd_ensoniq_create before intruduction
1962           * of suspend/resume
1963           */
1964 #ifdef CHIP1370
1965         outl(ensoniq->ctrl, ES_REG(ensoniq, CONTROL));
1966         outl(ensoniq->sctrl, ES_REG(ensoniq, SERIAL));
1967         outl(ES_MEM_PAGEO(ES_PAGE_ADC), ES_REG(ensoniq, MEM_PAGE));
1968         outl(ensoniq->dma_bug.addr, ES_REG(ensoniq, PHANTOM_FRAME));
1969         outl(0, ES_REG(ensoniq, PHANTOM_COUNT));
1970 #else
1971         outl(ensoniq->ctrl, ES_REG(ensoniq, CONTROL));
1972         outl(ensoniq->sctrl, ES_REG(ensoniq, SERIAL));
1973         outl(0, ES_REG(ensoniq, 1371_LEGACY));
1974         if (es1371_quirk_lookup(ensoniq, es1371_ac97_reset_hack)) {
1975             outl(ensoniq->cssr, ES_REG(ensoniq, STATUS));
1976             /* need to delay around 20ms(bleech) to give
1977                some CODECs enough time to wakeup */
1978             msleep(20);
1979         }
1980         /* AC'97 warm reset to start the bitclk */
1981         outl(ensoniq->ctrl | ES_1371_SYNC_RES, ES_REG(ensoniq, CONTROL));
1982         inl(ES_REG(ensoniq, CONTROL));
1983         udelay(20);
1984         outl(ensoniq->ctrl, ES_REG(ensoniq, CONTROL));
1985         /* Init the sample rate converter */
1986         snd_es1371_wait_src_ready(ensoniq);     
1987         outl(ES_1371_SRC_DISABLE, ES_REG(ensoniq, 1371_SMPRATE));
1988         for (idx = 0; idx < 0x80; idx++)
1989                 snd_es1371_src_write(ensoniq, idx, 0);
1990         snd_es1371_src_write(ensoniq, ES_SMPREG_DAC1 + ES_SMPREG_TRUNC_N, 16 << 4);
1991         snd_es1371_src_write(ensoniq, ES_SMPREG_DAC1 + ES_SMPREG_INT_REGS, 16 << 10);
1992         snd_es1371_src_write(ensoniq, ES_SMPREG_DAC2 + ES_SMPREG_TRUNC_N, 16 << 4);
1993         snd_es1371_src_write(ensoniq, ES_SMPREG_DAC2 + ES_SMPREG_INT_REGS, 16 << 10);
1994         snd_es1371_src_write(ensoniq, ES_SMPREG_VOL_ADC, 1 << 12);
1995         snd_es1371_src_write(ensoniq, ES_SMPREG_VOL_ADC + 1, 1 << 12);
1996         snd_es1371_src_write(ensoniq, ES_SMPREG_VOL_DAC1, 1 << 12);
1997         snd_es1371_src_write(ensoniq, ES_SMPREG_VOL_DAC1 + 1, 1 << 12);
1998         snd_es1371_src_write(ensoniq, ES_SMPREG_VOL_DAC2, 1 << 12);
1999         snd_es1371_src_write(ensoniq, ES_SMPREG_VOL_DAC2 + 1, 1 << 12);
2000         snd_es1371_adc_rate(ensoniq, 22050);
2001         snd_es1371_dac1_rate(ensoniq, 22050);
2002         snd_es1371_dac2_rate(ensoniq, 22050);
2003         /* WARNING:
2004          * enabling the sample rate converter without properly programming
2005          * its parameters causes the chip to lock up (the SRC busy bit will
2006          * be stuck high, and I've found no way to rectify this other than
2007          * power cycle) - Thomas Sailer
2008          */
2009         snd_es1371_wait_src_ready(ensoniq);
2010         outl(0, ES_REG(ensoniq, 1371_SMPRATE));
2011         /* try reset codec directly */
2012         outl(ES_1371_CODEC_WRITE(0, 0), ES_REG(ensoniq, 1371_CODEC));
2013 #endif
2014         outb(ensoniq->uartc = 0x00, ES_REG(ensoniq, UART_CONTROL));
2015         outb(0x00, ES_REG(ensoniq, UART_RES));
2016         outl(ensoniq->cssr, ES_REG(ensoniq, STATUS));
2017         synchronize_irq(ensoniq->irq);
2018 }
2019
2020 #ifdef CONFIG_PM
2021 static int snd_ensoniq_suspend(struct pci_dev *pci, pm_message_t state)
2022 {
2023         struct snd_card *card = pci_get_drvdata(pci);
2024         struct ensoniq *ensoniq = card->private_data;
2025         
2026         snd_power_change_state(card, SNDRV_CTL_POWER_D3hot);
2027
2028         snd_pcm_suspend_all(ensoniq->pcm1);
2029         snd_pcm_suspend_all(ensoniq->pcm2);
2030         
2031 #ifdef CHIP1371 
2032         snd_ac97_suspend(ensoniq->u.es1371.ac97);
2033 #else
2034         /* try to reset AK4531 */
2035         outw(ES_1370_CODEC_WRITE(AK4531_RESET, 0x02), ES_REG(ensoniq, 1370_CODEC));
2036         inw(ES_REG(ensoniq, 1370_CODEC));
2037         udelay(100);
2038         outw(ES_1370_CODEC_WRITE(AK4531_RESET, 0x03), ES_REG(ensoniq, 1370_CODEC));
2039         inw(ES_REG(ensoniq, 1370_CODEC));
2040         udelay(100);
2041         snd_ak4531_suspend(ensoniq->u.es1370.ak4531);
2042 #endif  
2043
2044         pci_disable_device(pci);
2045         pci_save_state(pci);
2046         pci_set_power_state(pci, pci_choose_state(pci, state));
2047         return 0;
2048 }
2049
2050 static int snd_ensoniq_resume(struct pci_dev *pci)
2051 {
2052         struct snd_card *card = pci_get_drvdata(pci);
2053         struct ensoniq *ensoniq = card->private_data;
2054
2055         pci_set_power_state(pci, PCI_D0);
2056         pci_restore_state(pci);
2057         if (pci_enable_device(pci) < 0) {
2058                 printk(KERN_ERR DRIVER_NAME ": pci_enable_device failed, "
2059                        "disabling device\n");
2060                 snd_card_disconnect(card);
2061                 return -EIO;
2062         }
2063         pci_set_master(pci);
2064
2065         snd_ensoniq_chip_init(ensoniq);
2066
2067 #ifdef CHIP1371 
2068         snd_ac97_resume(ensoniq->u.es1371.ac97);
2069 #else
2070         snd_ak4531_resume(ensoniq->u.es1370.ak4531);
2071 #endif  
2072         snd_power_change_state(card, SNDRV_CTL_POWER_D0);
2073         return 0;
2074 }
2075 #endif /* CONFIG_PM */
2076
2077
2078 static int __devinit snd_ensoniq_create(struct snd_card *card,
2079                                      struct pci_dev *pci,
2080                                      struct ensoniq ** rensoniq)
2081 {
2082         struct ensoniq *ensoniq;
2083         int err;
2084         static struct snd_device_ops ops = {
2085                 .dev_free =     snd_ensoniq_dev_free,
2086         };
2087
2088         *rensoniq = NULL;
2089         if ((err = pci_enable_device(pci)) < 0)
2090                 return err;
2091         ensoniq = kzalloc(sizeof(*ensoniq), GFP_KERNEL);
2092         if (ensoniq == NULL) {
2093                 pci_disable_device(pci);
2094                 return -ENOMEM;
2095         }
2096         spin_lock_init(&ensoniq->reg_lock);
2097         mutex_init(&ensoniq->src_mutex);
2098         ensoniq->card = card;
2099         ensoniq->pci = pci;
2100         ensoniq->irq = -1;
2101         if ((err = pci_request_regions(pci, "Ensoniq AudioPCI")) < 0) {
2102                 kfree(ensoniq);
2103                 pci_disable_device(pci);
2104                 return err;
2105         }
2106         ensoniq->port = pci_resource_start(pci, 0);
2107         if (request_irq(pci->irq, snd_audiopci_interrupt, IRQF_SHARED,
2108                         "Ensoniq AudioPCI", ensoniq)) {
2109                 snd_printk(KERN_ERR "unable to grab IRQ %d\n", pci->irq);
2110                 snd_ensoniq_free(ensoniq);
2111                 return -EBUSY;
2112         }
2113         ensoniq->irq = pci->irq;
2114 #ifdef CHIP1370
2115         if (snd_dma_alloc_pages(SNDRV_DMA_TYPE_DEV, snd_dma_pci_data(pci),
2116                                 16, &ensoniq->dma_bug) < 0) {
2117                 snd_printk(KERN_ERR "unable to allocate space for phantom area - dma_bug\n");
2118                 snd_ensoniq_free(ensoniq);
2119                 return -EBUSY;
2120         }
2121 #endif
2122         pci_set_master(pci);
2123         ensoniq->rev = pci->revision;
2124 #ifdef CHIP1370
2125 #if 0
2126         ensoniq->ctrl = ES_1370_CDC_EN | ES_1370_SERR_DISABLE |
2127                 ES_1370_PCLKDIVO(ES_1370_SRTODIV(8000));
2128 #else   /* get microphone working */
2129         ensoniq->ctrl = ES_1370_CDC_EN | ES_1370_PCLKDIVO(ES_1370_SRTODIV(8000));
2130 #endif
2131         ensoniq->sctrl = 0;
2132 #else
2133         ensoniq->ctrl = 0;
2134         ensoniq->sctrl = 0;
2135         ensoniq->cssr = 0;
2136         if (snd_pci_quirk_lookup(pci, es1371_amplifier_hack))
2137                 ensoniq->ctrl |= ES_1371_GPIO_OUT(1);   /* turn amplifier on */
2138
2139         if (es1371_quirk_lookup(ensoniq, es1371_ac97_reset_hack))
2140                 ensoniq->cssr |= ES_1371_ST_AC97_RST;
2141 #endif
2142
2143         snd_ensoniq_chip_init(ensoniq);
2144
2145         if ((err = snd_device_new(card, SNDRV_DEV_LOWLEVEL, ensoniq, &ops)) < 0) {
2146                 snd_ensoniq_free(ensoniq);
2147                 return err;
2148         }
2149
2150         snd_ensoniq_proc_init(ensoniq);
2151
2152         snd_card_set_dev(card, &pci->dev);
2153
2154         *rensoniq = ensoniq;
2155         return 0;
2156 }
2157
2158 /*
2159  *  MIDI section
2160  */
2161
2162 static void snd_ensoniq_midi_interrupt(struct ensoniq * ensoniq)
2163 {
2164         struct snd_rawmidi *rmidi = ensoniq->rmidi;
2165         unsigned char status, mask, byte;
2166
2167         if (rmidi == NULL)
2168                 return;
2169         /* do Rx at first */
2170         spin_lock(&ensoniq->reg_lock);
2171         mask = ensoniq->uartm & ES_MODE_INPUT ? ES_RXRDY : 0;
2172         while (mask) {
2173                 status = inb(ES_REG(ensoniq, UART_STATUS));
2174                 if ((status & mask) == 0)
2175                         break;
2176                 byte = inb(ES_REG(ensoniq, UART_DATA));
2177                 snd_rawmidi_receive(ensoniq->midi_input, &byte, 1);
2178         }
2179         spin_unlock(&ensoniq->reg_lock);
2180
2181         /* do Tx at second */
2182         spin_lock(&ensoniq->reg_lock);
2183         mask = ensoniq->uartm & ES_MODE_OUTPUT ? ES_TXRDY : 0;
2184         while (mask) {
2185                 status = inb(ES_REG(ensoniq, UART_STATUS));
2186                 if ((status & mask) == 0)
2187                         break;
2188                 if (snd_rawmidi_transmit(ensoniq->midi_output, &byte, 1) != 1) {
2189                         ensoniq->uartc &= ~ES_TXINTENM;
2190                         outb(ensoniq->uartc, ES_REG(ensoniq, UART_CONTROL));
2191                         mask &= ~ES_TXRDY;
2192                 } else {
2193                         outb(byte, ES_REG(ensoniq, UART_DATA));
2194                 }
2195         }
2196         spin_unlock(&ensoniq->reg_lock);
2197 }
2198
2199 static int snd_ensoniq_midi_input_open(struct snd_rawmidi_substream *substream)
2200 {
2201         struct ensoniq *ensoniq = substream->rmidi->private_data;
2202
2203         spin_lock_irq(&ensoniq->reg_lock);
2204         ensoniq->uartm |= ES_MODE_INPUT;
2205         ensoniq->midi_input = substream;
2206         if (!(ensoniq->uartm & ES_MODE_OUTPUT)) {
2207                 outb(ES_CNTRL(3), ES_REG(ensoniq, UART_CONTROL));
2208                 outb(ensoniq->uartc = 0, ES_REG(ensoniq, UART_CONTROL));
2209                 outl(ensoniq->ctrl |= ES_UART_EN, ES_REG(ensoniq, CONTROL));
2210         }
2211         spin_unlock_irq(&ensoniq->reg_lock);
2212         return 0;
2213 }
2214
2215 static int snd_ensoniq_midi_input_close(struct snd_rawmidi_substream *substream)
2216 {
2217         struct ensoniq *ensoniq = substream->rmidi->private_data;
2218
2219         spin_lock_irq(&ensoniq->reg_lock);
2220         if (!(ensoniq->uartm & ES_MODE_OUTPUT)) {
2221                 outb(ensoniq->uartc = 0, ES_REG(ensoniq, UART_CONTROL));
2222                 outl(ensoniq->ctrl &= ~ES_UART_EN, ES_REG(ensoniq, CONTROL));
2223         } else {
2224                 outb(ensoniq->uartc &= ~ES_RXINTEN, ES_REG(ensoniq, UART_CONTROL));
2225         }
2226         ensoniq->midi_input = NULL;
2227         ensoniq->uartm &= ~ES_MODE_INPUT;
2228         spin_unlock_irq(&ensoniq->reg_lock);
2229         return 0;
2230 }
2231
2232 static int snd_ensoniq_midi_output_open(struct snd_rawmidi_substream *substream)
2233 {
2234         struct ensoniq *ensoniq = substream->rmidi->private_data;
2235
2236         spin_lock_irq(&ensoniq->reg_lock);
2237         ensoniq->uartm |= ES_MODE_OUTPUT;
2238         ensoniq->midi_output = substream;
2239         if (!(ensoniq->uartm & ES_MODE_INPUT)) {
2240                 outb(ES_CNTRL(3), ES_REG(ensoniq, UART_CONTROL));
2241                 outb(ensoniq->uartc = 0, ES_REG(ensoniq, UART_CONTROL));
2242                 outl(ensoniq->ctrl |= ES_UART_EN, ES_REG(ensoniq, CONTROL));
2243         }
2244         spin_unlock_irq(&ensoniq->reg_lock);
2245         return 0;
2246 }
2247
2248 static int snd_ensoniq_midi_output_close(struct snd_rawmidi_substream *substream)
2249 {
2250         struct ensoniq *ensoniq = substream->rmidi->private_data;
2251
2252         spin_lock_irq(&ensoniq->reg_lock);
2253         if (!(ensoniq->uartm & ES_MODE_INPUT)) {
2254                 outb(ensoniq->uartc = 0, ES_REG(ensoniq, UART_CONTROL));
2255                 outl(ensoniq->ctrl &= ~ES_UART_EN, ES_REG(ensoniq, CONTROL));
2256         } else {
2257                 outb(ensoniq->uartc &= ~ES_TXINTENM, ES_REG(ensoniq, UART_CONTROL));
2258         }
2259         ensoniq->midi_output = NULL;
2260         ensoniq->uartm &= ~ES_MODE_OUTPUT;
2261         spin_unlock_irq(&ensoniq->reg_lock);
2262         return 0;
2263 }
2264
2265 static void snd_ensoniq_midi_input_trigger(struct snd_rawmidi_substream *substream, int up)
2266 {
2267         unsigned long flags;
2268         struct ensoniq *ensoniq = substream->rmidi->private_data;
2269         int idx;
2270
2271         spin_lock_irqsave(&ensoniq->reg_lock, flags);
2272         if (up) {
2273                 if ((ensoniq->uartc & ES_RXINTEN) == 0) {
2274                         /* empty input FIFO */
2275                         for (idx = 0; idx < 32; idx++)
2276                                 inb(ES_REG(ensoniq, UART_DATA));
2277                         ensoniq->uartc |= ES_RXINTEN;
2278                         outb(ensoniq->uartc, ES_REG(ensoniq, UART_CONTROL));
2279                 }
2280         } else {
2281                 if (ensoniq->uartc & ES_RXINTEN) {
2282                         ensoniq->uartc &= ~ES_RXINTEN;
2283                         outb(ensoniq->uartc, ES_REG(ensoniq, UART_CONTROL));
2284                 }
2285         }
2286         spin_unlock_irqrestore(&ensoniq->reg_lock, flags);
2287 }
2288
2289 static void snd_ensoniq_midi_output_trigger(struct snd_rawmidi_substream *substream, int up)
2290 {
2291         unsigned long flags;
2292         struct ensoniq *ensoniq = substream->rmidi->private_data;
2293         unsigned char byte;
2294
2295         spin_lock_irqsave(&ensoniq->reg_lock, flags);
2296         if (up) {
2297                 if (ES_TXINTENI(ensoniq->uartc) == 0) {
2298                         ensoniq->uartc |= ES_TXINTENO(1);
2299                         /* fill UART FIFO buffer at first, and turn Tx interrupts only if necessary */
2300                         while (ES_TXINTENI(ensoniq->uartc) == 1 &&
2301                                (inb(ES_REG(ensoniq, UART_STATUS)) & ES_TXRDY)) {
2302                                 if (snd_rawmidi_transmit(substream, &byte, 1) != 1) {
2303                                         ensoniq->uartc &= ~ES_TXINTENM;
2304                                 } else {
2305                                         outb(byte, ES_REG(ensoniq, UART_DATA));
2306                                 }
2307                         }
2308                         outb(ensoniq->uartc, ES_REG(ensoniq, UART_CONTROL));
2309                 }
2310         } else {
2311                 if (ES_TXINTENI(ensoniq->uartc) == 1) {
2312                         ensoniq->uartc &= ~ES_TXINTENM;
2313                         outb(ensoniq->uartc, ES_REG(ensoniq, UART_CONTROL));
2314                 }
2315         }
2316         spin_unlock_irqrestore(&ensoniq->reg_lock, flags);
2317 }
2318
2319 static struct snd_rawmidi_ops snd_ensoniq_midi_output =
2320 {
2321         .open =         snd_ensoniq_midi_output_open,
2322         .close =        snd_ensoniq_midi_output_close,
2323         .trigger =      snd_ensoniq_midi_output_trigger,
2324 };
2325
2326 static struct snd_rawmidi_ops snd_ensoniq_midi_input =
2327 {
2328         .open =         snd_ensoniq_midi_input_open,
2329         .close =        snd_ensoniq_midi_input_close,
2330         .trigger =      snd_ensoniq_midi_input_trigger,
2331 };
2332
2333 static int __devinit snd_ensoniq_midi(struct ensoniq * ensoniq, int device,
2334                                       struct snd_rawmidi **rrawmidi)
2335 {
2336         struct snd_rawmidi *rmidi;
2337         int err;
2338
2339         if (rrawmidi)
2340                 *rrawmidi = NULL;
2341         if ((err = snd_rawmidi_new(ensoniq->card, "ES1370/1", device, 1, 1, &rmidi)) < 0)
2342                 return err;
2343 #ifdef CHIP1370
2344         strcpy(rmidi->name, "ES1370");
2345 #else
2346         strcpy(rmidi->name, "ES1371");
2347 #endif
2348         snd_rawmidi_set_ops(rmidi, SNDRV_RAWMIDI_STREAM_OUTPUT, &snd_ensoniq_midi_output);
2349         snd_rawmidi_set_ops(rmidi, SNDRV_RAWMIDI_STREAM_INPUT, &snd_ensoniq_midi_input);
2350         rmidi->info_flags |= SNDRV_RAWMIDI_INFO_OUTPUT | SNDRV_RAWMIDI_INFO_INPUT |
2351                 SNDRV_RAWMIDI_INFO_DUPLEX;
2352         rmidi->private_data = ensoniq;
2353         ensoniq->rmidi = rmidi;
2354         if (rrawmidi)
2355                 *rrawmidi = rmidi;
2356         return 0;
2357 }
2358
2359 /*
2360  *  Interrupt handler
2361  */
2362
2363 static irqreturn_t snd_audiopci_interrupt(int irq, void *dev_id)
2364 {
2365         struct ensoniq *ensoniq = dev_id;
2366         unsigned int status, sctrl;
2367
2368         if (ensoniq == NULL)
2369                 return IRQ_NONE;
2370
2371         status = inl(ES_REG(ensoniq, STATUS));
2372         if (!(status & ES_INTR))
2373                 return IRQ_NONE;
2374
2375         spin_lock(&ensoniq->reg_lock);
2376         sctrl = ensoniq->sctrl;
2377         if (status & ES_DAC1)
2378                 sctrl &= ~ES_P1_INT_EN;
2379         if (status & ES_DAC2)
2380                 sctrl &= ~ES_P2_INT_EN;
2381         if (status & ES_ADC)
2382                 sctrl &= ~ES_R1_INT_EN;
2383         outl(sctrl, ES_REG(ensoniq, SERIAL));
2384         outl(ensoniq->sctrl, ES_REG(ensoniq, SERIAL));
2385         spin_unlock(&ensoniq->reg_lock);
2386
2387         if (status & ES_UART)
2388                 snd_ensoniq_midi_interrupt(ensoniq);
2389         if ((status & ES_DAC2) && ensoniq->playback2_substream)
2390                 snd_pcm_period_elapsed(ensoniq->playback2_substream);
2391         if ((status & ES_ADC) && ensoniq->capture_substream)
2392                 snd_pcm_period_elapsed(ensoniq->capture_substream);
2393         if ((status & ES_DAC1) && ensoniq->playback1_substream)
2394                 snd_pcm_period_elapsed(ensoniq->playback1_substream);
2395         return IRQ_HANDLED;
2396 }
2397
2398 static int __devinit snd_audiopci_probe(struct pci_dev *pci,
2399                                         const struct pci_device_id *pci_id)
2400 {
2401         static int dev;
2402         struct snd_card *card;
2403         struct ensoniq *ensoniq;
2404         int err, pcm_devs[2];
2405
2406         if (dev >= SNDRV_CARDS)
2407                 return -ENODEV;
2408         if (!enable[dev]) {
2409                 dev++;
2410                 return -ENOENT;
2411         }
2412
2413         err = snd_card_create(index[dev], id[dev], THIS_MODULE, 0, &card);
2414         if (err < 0)
2415                 return err;
2416
2417         if ((err = snd_ensoniq_create(card, pci, &ensoniq)) < 0) {
2418                 snd_card_free(card);
2419                 return err;
2420         }
2421         card->private_data = ensoniq;
2422
2423         pcm_devs[0] = 0; pcm_devs[1] = 1;
2424 #ifdef CHIP1370
2425         if ((err = snd_ensoniq_1370_mixer(ensoniq)) < 0) {
2426                 snd_card_free(card);
2427                 return err;
2428         }
2429 #endif
2430 #ifdef CHIP1371
2431         if ((err = snd_ensoniq_1371_mixer(ensoniq, spdif[dev], lineio[dev])) < 0) {
2432                 snd_card_free(card);
2433                 return err;
2434         }
2435 #endif
2436         if ((err = snd_ensoniq_pcm(ensoniq, 0, NULL)) < 0) {
2437                 snd_card_free(card);
2438                 return err;
2439         }
2440         if ((err = snd_ensoniq_pcm2(ensoniq, 1, NULL)) < 0) {
2441                 snd_card_free(card);
2442                 return err;
2443         }
2444         if ((err = snd_ensoniq_midi(ensoniq, 0, NULL)) < 0) {
2445                 snd_card_free(card);
2446                 return err;
2447         }
2448
2449         snd_ensoniq_create_gameport(ensoniq, dev);
2450
2451         strcpy(card->driver, DRIVER_NAME);
2452
2453         strcpy(card->shortname, "Ensoniq AudioPCI");
2454         sprintf(card->longname, "%s %s at 0x%lx, irq %i",
2455                 card->shortname,
2456                 card->driver,
2457                 ensoniq->port,
2458                 ensoniq->irq);
2459
2460         if ((err = snd_card_register(card)) < 0) {
2461                 snd_card_free(card);
2462                 return err;
2463         }
2464
2465         pci_set_drvdata(pci, card);
2466         dev++;
2467         return 0;
2468 }
2469
2470 static void __devexit snd_audiopci_remove(struct pci_dev *pci)
2471 {
2472         snd_card_free(pci_get_drvdata(pci));
2473         pci_set_drvdata(pci, NULL);
2474 }
2475
2476 static struct pci_driver driver = {
2477         .name = DRIVER_NAME,
2478         .id_table = snd_audiopci_ids,
2479         .probe = snd_audiopci_probe,
2480         .remove = __devexit_p(snd_audiopci_remove),
2481 #ifdef CONFIG_PM
2482         .suspend = snd_ensoniq_suspend,
2483         .resume = snd_ensoniq_resume,
2484 #endif
2485 };
2486         
2487 static int __init alsa_card_ens137x_init(void)
2488 {
2489         return pci_register_driver(&driver);
2490 }
2491
2492 static void __exit alsa_card_ens137x_exit(void)
2493 {
2494         pci_unregister_driver(&driver);
2495 }
2496
2497 module_init(alsa_card_ens137x_init)
2498 module_exit(alsa_card_ens137x_exit)