[ALSA] Remove superfluous pcm_free callbacks
[linux-2.6.git] / sound / pci / cs4281.c
1 /*
2  *  Driver for Cirrus Logic CS4281 based PCI soundcard
3  *  Copyright (c) by Jaroslav Kysela <perex@suse.cz>,
4  *
5  *
6  *   This program is free software; you can redistribute it and/or modify
7  *   it under the terms of the GNU General Public License as published by
8  *   the Free Software Foundation; either version 2 of the License, or
9  *   (at your option) any later version.
10  *
11  *   This program is distributed in the hope that it will be useful,
12  *   but WITHOUT ANY WARRANTY; without even the implied warranty of
13  *   MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
14  *   GNU General Public License for more details.
15  *
16  *   You should have received a copy of the GNU General Public License
17  *   along with this program; if not, write to the Free Software
18  *   Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307 USA
19  *
20  */
21
22 #include <sound/driver.h>
23 #include <asm/io.h>
24 #include <linux/delay.h>
25 #include <linux/interrupt.h>
26 #include <linux/init.h>
27 #include <linux/pci.h>
28 #include <linux/slab.h>
29 #include <linux/gameport.h>
30 #include <linux/moduleparam.h>
31 #include <sound/core.h>
32 #include <sound/control.h>
33 #include <sound/pcm.h>
34 #include <sound/rawmidi.h>
35 #include <sound/ac97_codec.h>
36 #include <sound/opl3.h>
37 #include <sound/initval.h>
38
39
40 MODULE_AUTHOR("Jaroslav Kysela <perex@suse.cz>");
41 MODULE_DESCRIPTION("Cirrus Logic CS4281");
42 MODULE_LICENSE("GPL");
43 MODULE_SUPPORTED_DEVICE("{{Cirrus Logic,CS4281}}");
44
45 static int index[SNDRV_CARDS] = SNDRV_DEFAULT_IDX;      /* Index 0-MAX */
46 static char *id[SNDRV_CARDS] = SNDRV_DEFAULT_STR;       /* ID for this card */
47 static int enable[SNDRV_CARDS] = SNDRV_DEFAULT_ENABLE_PNP;      /* Enable switches */
48 static int dual_codec[SNDRV_CARDS];     /* dual codec */
49
50 module_param_array(index, int, NULL, 0444);
51 MODULE_PARM_DESC(index, "Index value for CS4281 soundcard.");
52 module_param_array(id, charp, NULL, 0444);
53 MODULE_PARM_DESC(id, "ID string for CS4281 soundcard.");
54 module_param_array(enable, bool, NULL, 0444);
55 MODULE_PARM_DESC(enable, "Enable CS4281 soundcard.");
56 module_param_array(dual_codec, bool, NULL, 0444);
57 MODULE_PARM_DESC(dual_codec, "Secondary Codec ID (0 = disabled).");
58
59 /*
60  *  Direct registers
61  */
62
63 #define CS4281_BA0_SIZE         0x1000
64 #define CS4281_BA1_SIZE         0x10000
65
66 /*
67  *  BA0 registers
68  */
69 #define BA0_HISR                0x0000  /* Host Interrupt Status Register */
70 #define BA0_HISR_INTENA         (1<<31) /* Internal Interrupt Enable Bit */
71 #define BA0_HISR_MIDI           (1<<22) /* MIDI port interrupt */
72 #define BA0_HISR_FIFOI          (1<<20) /* FIFO polled interrupt */
73 #define BA0_HISR_DMAI           (1<<18) /* DMA interrupt (half or end) */
74 #define BA0_HISR_FIFO(c)        (1<<(12+(c))) /* FIFO channel interrupt */
75 #define BA0_HISR_DMA(c)         (1<<(8+(c)))  /* DMA channel interrupt */
76 #define BA0_HISR_GPPI           (1<<5)  /* General Purpose Input (Primary chip) */
77 #define BA0_HISR_GPSI           (1<<4)  /* General Purpose Input (Secondary chip) */
78 #define BA0_HISR_GP3I           (1<<3)  /* GPIO3 pin Interrupt */
79 #define BA0_HISR_GP1I           (1<<2)  /* GPIO1 pin Interrupt */
80 #define BA0_HISR_VUPI           (1<<1)  /* VOLUP pin Interrupt */
81 #define BA0_HISR_VDNI           (1<<0)  /* VOLDN pin Interrupt */
82
83 #define BA0_HICR                0x0008  /* Host Interrupt Control Register */
84 #define BA0_HICR_CHGM           (1<<1)  /* INTENA Change Mask */
85 #define BA0_HICR_IEV            (1<<0)  /* INTENA Value */
86 #define BA0_HICR_EOI            (3<<0)  /* End of Interrupt command */
87
88 #define BA0_HIMR                0x000c  /* Host Interrupt Mask Register */
89                                         /* Use same contants as for BA0_HISR */
90
91 #define BA0_IIER                0x0010  /* ISA Interrupt Enable Register */
92
93 #define BA0_HDSR0               0x00f0  /* Host DMA Engine 0 Status Register */
94 #define BA0_HDSR1               0x00f4  /* Host DMA Engine 1 Status Register */
95 #define BA0_HDSR2               0x00f8  /* Host DMA Engine 2 Status Register */
96 #define BA0_HDSR3               0x00fc  /* Host DMA Engine 3 Status Register */
97
98 #define BA0_HDSR_CH1P           (1<<25) /* Channel 1 Pending */
99 #define BA0_HDSR_CH2P           (1<<24) /* Channel 2 Pending */
100 #define BA0_HDSR_DHTC           (1<<17) /* DMA Half Terminal Count */
101 #define BA0_HDSR_DTC            (1<<16) /* DMA Terminal Count */
102 #define BA0_HDSR_DRUN           (1<<15) /* DMA Running */
103 #define BA0_HDSR_RQ             (1<<7)  /* Pending Request */
104
105 #define BA0_DCA0                0x0110  /* Host DMA Engine 0 Current Address */
106 #define BA0_DCC0                0x0114  /* Host DMA Engine 0 Current Count */
107 #define BA0_DBA0                0x0118  /* Host DMA Engine 0 Base Address */
108 #define BA0_DBC0                0x011c  /* Host DMA Engine 0 Base Count */
109 #define BA0_DCA1                0x0120  /* Host DMA Engine 1 Current Address */
110 #define BA0_DCC1                0x0124  /* Host DMA Engine 1 Current Count */
111 #define BA0_DBA1                0x0128  /* Host DMA Engine 1 Base Address */
112 #define BA0_DBC1                0x012c  /* Host DMA Engine 1 Base Count */
113 #define BA0_DCA2                0x0130  /* Host DMA Engine 2 Current Address */
114 #define BA0_DCC2                0x0134  /* Host DMA Engine 2 Current Count */
115 #define BA0_DBA2                0x0138  /* Host DMA Engine 2 Base Address */
116 #define BA0_DBC2                0x013c  /* Host DMA Engine 2 Base Count */
117 #define BA0_DCA3                0x0140  /* Host DMA Engine 3 Current Address */
118 #define BA0_DCC3                0x0144  /* Host DMA Engine 3 Current Count */
119 #define BA0_DBA3                0x0148  /* Host DMA Engine 3 Base Address */
120 #define BA0_DBC3                0x014c  /* Host DMA Engine 3 Base Count */
121 #define BA0_DMR0                0x0150  /* Host DMA Engine 0 Mode */
122 #define BA0_DCR0                0x0154  /* Host DMA Engine 0 Command */
123 #define BA0_DMR1                0x0158  /* Host DMA Engine 1 Mode */
124 #define BA0_DCR1                0x015c  /* Host DMA Engine 1 Command */
125 #define BA0_DMR2                0x0160  /* Host DMA Engine 2 Mode */
126 #define BA0_DCR2                0x0164  /* Host DMA Engine 2 Command */
127 #define BA0_DMR3                0x0168  /* Host DMA Engine 3 Mode */
128 #define BA0_DCR3                0x016c  /* Host DMA Engine 3 Command */
129
130 #define BA0_DMR_DMA             (1<<29) /* Enable DMA mode */
131 #define BA0_DMR_POLL            (1<<28) /* Enable poll mode */
132 #define BA0_DMR_TBC             (1<<25) /* Transfer By Channel */
133 #define BA0_DMR_CBC             (1<<24) /* Count By Channel (0 = frame resolution) */
134 #define BA0_DMR_SWAPC           (1<<22) /* Swap Left/Right Channels */
135 #define BA0_DMR_SIZE20          (1<<20) /* Sample is 20-bit */
136 #define BA0_DMR_USIGN           (1<<19) /* Unsigned */
137 #define BA0_DMR_BEND            (1<<18) /* Big Endian */
138 #define BA0_DMR_MONO            (1<<17) /* Mono */
139 #define BA0_DMR_SIZE8           (1<<16) /* Sample is 8-bit */
140 #define BA0_DMR_TYPE_DEMAND     (0<<6)
141 #define BA0_DMR_TYPE_SINGLE     (1<<6)
142 #define BA0_DMR_TYPE_BLOCK      (2<<6)
143 #define BA0_DMR_TYPE_CASCADE    (3<<6)  /* Not supported */
144 #define BA0_DMR_DEC             (1<<5)  /* Access Increment (0) or Decrement (1) */
145 #define BA0_DMR_AUTO            (1<<4)  /* Auto-Initialize */
146 #define BA0_DMR_TR_VERIFY       (0<<2)  /* Verify Transfer */
147 #define BA0_DMR_TR_WRITE        (1<<2)  /* Write Transfer */
148 #define BA0_DMR_TR_READ         (2<<2)  /* Read Transfer */
149
150 #define BA0_DCR_HTCIE           (1<<17) /* Half Terminal Count Interrupt */
151 #define BA0_DCR_TCIE            (1<<16) /* Terminal Count Interrupt */
152 #define BA0_DCR_MSK             (1<<0)  /* DMA Mask bit */
153
154 #define BA0_FCR0                0x0180  /* FIFO Control 0 */
155 #define BA0_FCR1                0x0184  /* FIFO Control 1 */
156 #define BA0_FCR2                0x0188  /* FIFO Control 2 */
157 #define BA0_FCR3                0x018c  /* FIFO Control 3 */
158
159 #define BA0_FCR_FEN             (1<<31) /* FIFO Enable bit */
160 #define BA0_FCR_DACZ            (1<<30) /* DAC Zero */
161 #define BA0_FCR_PSH             (1<<29) /* Previous Sample Hold */
162 #define BA0_FCR_RS(x)           (((x)&0x1f)<<24) /* Right Slot Mapping */
163 #define BA0_FCR_LS(x)           (((x)&0x1f)<<16) /* Left Slot Mapping */
164 #define BA0_FCR_SZ(x)           (((x)&0x7f)<<8) /* FIFO buffer size (in samples) */
165 #define BA0_FCR_OF(x)           (((x)&0x7f)<<0) /* FIFO starting offset (in samples) */
166
167 #define BA0_FPDR0               0x0190  /* FIFO Polled Data 0 */
168 #define BA0_FPDR1               0x0194  /* FIFO Polled Data 1 */
169 #define BA0_FPDR2               0x0198  /* FIFO Polled Data 2 */
170 #define BA0_FPDR3               0x019c  /* FIFO Polled Data 3 */
171
172 #define BA0_FCHS                0x020c  /* FIFO Channel Status */
173 #define BA0_FCHS_RCO(x)         (1<<(7+(((x)&3)<<3))) /* Right Channel Out */
174 #define BA0_FCHS_LCO(x)         (1<<(6+(((x)&3)<<3))) /* Left Channel Out */
175 #define BA0_FCHS_MRP(x)         (1<<(5+(((x)&3)<<3))) /* Move Read Pointer */
176 #define BA0_FCHS_FE(x)          (1<<(4+(((x)&3)<<3))) /* FIFO Empty */
177 #define BA0_FCHS_FF(x)          (1<<(3+(((x)&3)<<3))) /* FIFO Full */
178 #define BA0_FCHS_IOR(x)         (1<<(2+(((x)&3)<<3))) /* Internal Overrun Flag */
179 #define BA0_FCHS_RCI(x)         (1<<(1+(((x)&3)<<3))) /* Right Channel In */
180 #define BA0_FCHS_LCI(x)         (1<<(0+(((x)&3)<<3))) /* Left Channel In */
181
182 #define BA0_FSIC0               0x0210  /* FIFO Status and Interrupt Control 0 */
183 #define BA0_FSIC1               0x0214  /* FIFO Status and Interrupt Control 1 */
184 #define BA0_FSIC2               0x0218  /* FIFO Status and Interrupt Control 2 */
185 #define BA0_FSIC3               0x021c  /* FIFO Status and Interrupt Control 3 */
186
187 #define BA0_FSIC_FIC(x)         (((x)&0x7f)<<24) /* FIFO Interrupt Count */
188 #define BA0_FSIC_FORIE          (1<<23) /* FIFO OverRun Interrupt Enable */
189 #define BA0_FSIC_FURIE          (1<<22) /* FIFO UnderRun Interrupt Enable */
190 #define BA0_FSIC_FSCIE          (1<<16) /* FIFO Sample Count Interrupt Enable */
191 #define BA0_FSIC_FSC(x)         (((x)&0x7f)<<8) /* FIFO Sample Count */
192 #define BA0_FSIC_FOR            (1<<7)  /* FIFO OverRun */
193 #define BA0_FSIC_FUR            (1<<6)  /* FIFO UnderRun */
194 #define BA0_FSIC_FSCR           (1<<0)  /* FIFO Sample Count Reached */
195
196 #define BA0_PMCS                0x0344  /* Power Management Control/Status */
197 #define BA0_CWPR                0x03e0  /* Configuration Write Protect */
198
199 #define BA0_EPPMC               0x03e4  /* Extended PCI Power Management Control */
200 #define BA0_EPPMC_FPDN          (1<<14) /* Full Power DowN */
201
202 #define BA0_GPIOR               0x03e8  /* GPIO Pin Interface Register */
203
204 #define BA0_SPMC                0x03ec  /* Serial Port Power Management Control (& ASDIN2 enable) */
205 #define BA0_SPMC_GIPPEN         (1<<15) /* GP INT Primary PME# Enable */
206 #define BA0_SPMC_GISPEN         (1<<14) /* GP INT Secondary PME# Enable */
207 #define BA0_SPMC_EESPD          (1<<9)  /* EEPROM Serial Port Disable */
208 #define BA0_SPMC_ASDI2E         (1<<8)  /* ASDIN2 Enable */
209 #define BA0_SPMC_ASDO           (1<<7)  /* Asynchronous ASDOUT Assertion */
210 #define BA0_SPMC_WUP2           (1<<3)  /* Wakeup for Secondary Input */
211 #define BA0_SPMC_WUP1           (1<<2)  /* Wakeup for Primary Input */
212 #define BA0_SPMC_ASYNC          (1<<1)  /* Asynchronous ASYNC Assertion */
213 #define BA0_SPMC_RSTN           (1<<0)  /* Reset Not! */
214
215 #define BA0_CFLR                0x03f0  /* Configuration Load Register (EEPROM or BIOS) */
216 #define BA0_CFLR_DEFAULT        0x00000001 /* CFLR must be in AC97 link mode */
217 #define BA0_IISR                0x03f4  /* ISA Interrupt Select */
218 #define BA0_TMS                 0x03f8  /* Test Register */
219 #define BA0_SSVID               0x03fc  /* Subsystem ID register */
220
221 #define BA0_CLKCR1              0x0400  /* Clock Control Register 1 */
222 #define BA0_CLKCR1_CLKON        (1<<25) /* Read Only */
223 #define BA0_CLKCR1_DLLRDY       (1<<24) /* DLL Ready */
224 #define BA0_CLKCR1_DLLOS        (1<<6)  /* DLL Output Select */
225 #define BA0_CLKCR1_SWCE         (1<<5)  /* Clock Enable */
226 #define BA0_CLKCR1_DLLP         (1<<4)  /* DLL PowerUp */
227 #define BA0_CLKCR1_DLLSS        (((x)&3)<<3) /* DLL Source Select */
228
229 #define BA0_FRR                 0x0410  /* Feature Reporting Register */
230 #define BA0_SLT12O              0x041c  /* Slot 12 GPIO Output Register for AC-Link */
231
232 #define BA0_SERMC               0x0420  /* Serial Port Master Control */
233 #define BA0_SERMC_FCRN          (1<<27) /* Force Codec Ready Not */
234 #define BA0_SERMC_ODSEN2        (1<<25) /* On-Demand Support Enable ASDIN2 */
235 #define BA0_SERMC_ODSEN1        (1<<24) /* On-Demand Support Enable ASDIN1 */
236 #define BA0_SERMC_SXLB          (1<<21) /* ASDIN2 to ASDOUT Loopback */
237 #define BA0_SERMC_SLB           (1<<20) /* ASDOUT to ASDIN2 Loopback */
238 #define BA0_SERMC_LOVF          (1<<19) /* Loopback Output Valid Frame bit */
239 #define BA0_SERMC_TCID(x)       (((x)&3)<<16) /* Target Secondary Codec ID */
240 #define BA0_SERMC_PXLB          (5<<1)  /* Primary Port External Loopback */
241 #define BA0_SERMC_PLB           (4<<1)  /* Primary Port Internal Loopback */
242 #define BA0_SERMC_PTC           (7<<1)  /* Port Timing Configuration */
243 #define BA0_SERMC_PTC_AC97      (1<<1)  /* AC97 mode */
244 #define BA0_SERMC_MSPE          (1<<0)  /* Master Serial Port Enable */
245
246 #define BA0_SERC1               0x0428  /* Serial Port Configuration 1 */
247 #define BA0_SERC1_SO1F(x)       (((x)&7)>>1) /* Primary Output Port Format */
248 #define BA0_SERC1_AC97          (1<<1)
249 #define BA0_SERC1_SO1EN         (1<<0)  /* Primary Output Port Enable */
250
251 #define BA0_SERC2               0x042c  /* Serial Port Configuration 2 */
252 #define BA0_SERC2_SI1F(x)       (((x)&7)>>1) /* Primary Input Port Format */
253 #define BA0_SERC2_AC97          (1<<1)
254 #define BA0_SERC2_SI1EN         (1<<0)  /* Primary Input Port Enable */
255
256 #define BA0_SLT12M              0x045c  /* Slot 12 Monitor Register for Primary AC-Link */
257
258 #define BA0_ACCTL               0x0460  /* AC'97 Control */
259 #define BA0_ACCTL_TC            (1<<6)  /* Target Codec */
260 #define BA0_ACCTL_CRW           (1<<4)  /* 0=Write, 1=Read Command */
261 #define BA0_ACCTL_DCV           (1<<3)  /* Dynamic Command Valid */
262 #define BA0_ACCTL_VFRM          (1<<2)  /* Valid Frame */
263 #define BA0_ACCTL_ESYN          (1<<1)  /* Enable Sync */
264
265 #define BA0_ACSTS               0x0464  /* AC'97 Status */
266 #define BA0_ACSTS_VSTS          (1<<1)  /* Valid Status */
267 #define BA0_ACSTS_CRDY          (1<<0)  /* Codec Ready */
268
269 #define BA0_ACOSV               0x0468  /* AC'97 Output Slot Valid */
270 #define BA0_ACOSV_SLV(x)        (1<<((x)-3))
271
272 #define BA0_ACCAD               0x046c  /* AC'97 Command Address */
273 #define BA0_ACCDA               0x0470  /* AC'97 Command Data */
274
275 #define BA0_ACISV               0x0474  /* AC'97 Input Slot Valid */
276 #define BA0_ACISV_SLV(x)        (1<<((x)-3))
277
278 #define BA0_ACSAD               0x0478  /* AC'97 Status Address */
279 #define BA0_ACSDA               0x047c  /* AC'97 Status Data */
280 #define BA0_JSPT                0x0480  /* Joystick poll/trigger */
281 #define BA0_JSCTL               0x0484  /* Joystick control */
282 #define BA0_JSC1                0x0488  /* Joystick control */
283 #define BA0_JSC2                0x048c  /* Joystick control */
284 #define BA0_JSIO                0x04a0
285
286 #define BA0_MIDCR               0x0490  /* MIDI Control */
287 #define BA0_MIDCR_MRST          (1<<5)  /* Reset MIDI Interface */
288 #define BA0_MIDCR_MLB           (1<<4)  /* MIDI Loop Back Enable */
289 #define BA0_MIDCR_TIE           (1<<3)  /* MIDI Transmuit Interrupt Enable */
290 #define BA0_MIDCR_RIE           (1<<2)  /* MIDI Receive Interrupt Enable */
291 #define BA0_MIDCR_RXE           (1<<1)  /* MIDI Receive Enable */
292 #define BA0_MIDCR_TXE           (1<<0)  /* MIDI Transmit Enable */
293
294 #define BA0_MIDCMD              0x0494  /* MIDI Command (wo) */
295
296 #define BA0_MIDSR               0x0494  /* MIDI Status (ro) */
297 #define BA0_MIDSR_RDA           (1<<15) /* Sticky bit (RBE 1->0) */
298 #define BA0_MIDSR_TBE           (1<<14) /* Sticky bit (TBF 0->1) */
299 #define BA0_MIDSR_RBE           (1<<7)  /* Receive Buffer Empty */
300 #define BA0_MIDSR_TBF           (1<<6)  /* Transmit Buffer Full */
301
302 #define BA0_MIDWP               0x0498  /* MIDI Write */
303 #define BA0_MIDRP               0x049c  /* MIDI Read (ro) */
304
305 #define BA0_AODSD1              0x04a8  /* AC'97 On-Demand Slot Disable for primary link (ro) */
306 #define BA0_AODSD1_NDS(x)       (1<<((x)-3))
307
308 #define BA0_AODSD2              0x04ac  /* AC'97 On-Demand Slot Disable for secondary link (ro) */
309 #define BA0_AODSD2_NDS(x)       (1<<((x)-3))
310
311 #define BA0_CFGI                0x04b0  /* Configure Interface (EEPROM interface) */
312 #define BA0_SLT12M2             0x04dc  /* Slot 12 Monitor Register 2 for secondary AC-link */
313 #define BA0_ACSTS2              0x04e4  /* AC'97 Status Register 2 */
314 #define BA0_ACISV2              0x04f4  /* AC'97 Input Slot Valid Register 2 */
315 #define BA0_ACSAD2              0x04f8  /* AC'97 Status Address Register 2 */
316 #define BA0_ACSDA2              0x04fc  /* AC'97 Status Data Register 2 */
317 #define BA0_FMSR                0x0730  /* FM Synthesis Status (ro) */
318 #define BA0_B0AP                0x0730  /* FM Bank 0 Address Port (wo) */
319 #define BA0_FMDP                0x0734  /* FM Data Port */
320 #define BA0_B1AP                0x0738  /* FM Bank 1 Address Port */
321 #define BA0_B1DP                0x073c  /* FM Bank 1 Data Port */
322
323 #define BA0_SSPM                0x0740  /* Sound System Power Management */
324 #define BA0_SSPM_MIXEN          (1<<6)  /* Playback SRC + FM/Wavetable MIX */
325 #define BA0_SSPM_CSRCEN         (1<<5)  /* Capture Sample Rate Converter Enable */
326 #define BA0_SSPM_PSRCEN         (1<<4)  /* Playback Sample Rate Converter Enable */
327 #define BA0_SSPM_JSEN           (1<<3)  /* Joystick Enable */
328 #define BA0_SSPM_ACLEN          (1<<2)  /* Serial Port Engine and AC-Link Enable */
329 #define BA0_SSPM_FMEN           (1<<1)  /* FM Synthesis Block Enable */
330
331 #define BA0_DACSR               0x0744  /* DAC Sample Rate - Playback SRC */
332 #define BA0_ADCSR               0x0748  /* ADC Sample Rate - Capture SRC */
333
334 #define BA0_SSCR                0x074c  /* Sound System Control Register */
335 #define BA0_SSCR_HVS1           (1<<23) /* Hardwave Volume Step (0=1,1=2) */
336 #define BA0_SSCR_MVCS           (1<<19) /* Master Volume Codec Select */
337 #define BA0_SSCR_MVLD           (1<<18) /* Master Volume Line Out Disable */
338 #define BA0_SSCR_MVAD           (1<<17) /* Master Volume Alternate Out Disable */
339 #define BA0_SSCR_MVMD           (1<<16) /* Master Volume Mono Out Disable */
340 #define BA0_SSCR_XLPSRC         (1<<8)  /* External SRC Loopback Mode */
341 #define BA0_SSCR_LPSRC          (1<<7)  /* SRC Loopback Mode */
342 #define BA0_SSCR_CDTX           (1<<5)  /* CD Transfer Data */
343 #define BA0_SSCR_HVC            (1<<3)  /* Harware Volume Control Enable */
344
345 #define BA0_FMLVC               0x0754  /* FM Synthesis Left Volume Control */
346 #define BA0_FMRVC               0x0758  /* FM Synthesis Right Volume Control */
347 #define BA0_SRCSA               0x075c  /* SRC Slot Assignments */
348 #define BA0_PPLVC               0x0760  /* PCM Playback Left Volume Control */
349 #define BA0_PPRVC               0x0764  /* PCM Playback Right Volume Control */
350 #define BA0_PASR                0x0768  /* playback sample rate */
351 #define BA0_CASR                0x076C  /* capture sample rate */
352
353 /* Source Slot Numbers - Playback */
354 #define SRCSLOT_LEFT_PCM_PLAYBACK               0
355 #define SRCSLOT_RIGHT_PCM_PLAYBACK              1
356 #define SRCSLOT_PHONE_LINE_1_DAC                2
357 #define SRCSLOT_CENTER_PCM_PLAYBACK             3
358 #define SRCSLOT_LEFT_SURROUND_PCM_PLAYBACK      4
359 #define SRCSLOT_RIGHT_SURROUND_PCM_PLAYBACK     5
360 #define SRCSLOT_LFE_PCM_PLAYBACK                6
361 #define SRCSLOT_PHONE_LINE_2_DAC                7
362 #define SRCSLOT_HEADSET_DAC                     8
363 #define SRCSLOT_LEFT_WT                         29  /* invalid for BA0_SRCSA */
364 #define SRCSLOT_RIGHT_WT                        30  /* invalid for BA0_SRCSA */
365
366 /* Source Slot Numbers - Capture */
367 #define SRCSLOT_LEFT_PCM_RECORD                 10
368 #define SRCSLOT_RIGHT_PCM_RECORD                11
369 #define SRCSLOT_PHONE_LINE_1_ADC                12
370 #define SRCSLOT_MIC_ADC                         13
371 #define SRCSLOT_PHONE_LINE_2_ADC                17
372 #define SRCSLOT_HEADSET_ADC                     18
373 #define SRCSLOT_SECONDARY_LEFT_PCM_RECORD       20
374 #define SRCSLOT_SECONDARY_RIGHT_PCM_RECORD      21
375 #define SRCSLOT_SECONDARY_PHONE_LINE_1_ADC      22
376 #define SRCSLOT_SECONDARY_MIC_ADC               23
377 #define SRCSLOT_SECONDARY_PHONE_LINE_2_ADC      27
378 #define SRCSLOT_SECONDARY_HEADSET_ADC           28
379
380 /* Source Slot Numbers - Others */
381 #define SRCSLOT_POWER_DOWN                      31
382
383 /* MIDI modes */
384 #define CS4281_MODE_OUTPUT              (1<<0)
385 #define CS4281_MODE_INPUT               (1<<1)
386
387 /* joystick bits */
388 /* Bits for JSPT */
389 #define JSPT_CAX                                0x00000001
390 #define JSPT_CAY                                0x00000002
391 #define JSPT_CBX                                0x00000004
392 #define JSPT_CBY                                0x00000008
393 #define JSPT_BA1                                0x00000010
394 #define JSPT_BA2                                0x00000020
395 #define JSPT_BB1                                0x00000040
396 #define JSPT_BB2                                0x00000080
397
398 /* Bits for JSCTL */
399 #define JSCTL_SP_MASK                           0x00000003
400 #define JSCTL_SP_SLOW                           0x00000000
401 #define JSCTL_SP_MEDIUM_SLOW                    0x00000001
402 #define JSCTL_SP_MEDIUM_FAST                    0x00000002
403 #define JSCTL_SP_FAST                           0x00000003
404 #define JSCTL_ARE                               0x00000004
405
406 /* Data register pairs masks */
407 #define JSC1_Y1V_MASK                           0x0000FFFF
408 #define JSC1_X1V_MASK                           0xFFFF0000
409 #define JSC1_Y1V_SHIFT                          0
410 #define JSC1_X1V_SHIFT                          16
411 #define JSC2_Y2V_MASK                           0x0000FFFF
412 #define JSC2_X2V_MASK                           0xFFFF0000
413 #define JSC2_Y2V_SHIFT                          0
414 #define JSC2_X2V_SHIFT                          16
415
416 /* JS GPIO */
417 #define JSIO_DAX                                0x00000001
418 #define JSIO_DAY                                0x00000002
419 #define JSIO_DBX                                0x00000004
420 #define JSIO_DBY                                0x00000008
421 #define JSIO_AXOE                               0x00000010
422 #define JSIO_AYOE                               0x00000020
423 #define JSIO_BXOE                               0x00000040
424 #define JSIO_BYOE                               0x00000080
425
426 /*
427  *
428  */
429
430 typedef struct snd_cs4281 cs4281_t;
431 typedef struct snd_cs4281_dma cs4281_dma_t;
432
433 struct snd_cs4281_dma {
434         snd_pcm_substream_t *substream;
435         unsigned int regDBA;            /* offset to DBA register */
436         unsigned int regDCA;            /* offset to DCA register */
437         unsigned int regDBC;            /* offset to DBC register */
438         unsigned int regDCC;            /* offset to DCC register */
439         unsigned int regDMR;            /* offset to DMR register */
440         unsigned int regDCR;            /* offset to DCR register */
441         unsigned int regHDSR;           /* offset to HDSR register */
442         unsigned int regFCR;            /* offset to FCR register */
443         unsigned int regFSIC;           /* offset to FSIC register */
444         unsigned int valDMR;            /* DMA mode */
445         unsigned int valDCR;            /* DMA command */
446         unsigned int valFCR;            /* FIFO control */
447         unsigned int fifo_offset;       /* FIFO offset within BA1 */
448         unsigned char left_slot;        /* FIFO left slot */
449         unsigned char right_slot;       /* FIFO right slot */
450         int frag;                       /* period number */
451 };
452
453 #define SUSPEND_REGISTERS       20
454
455 struct snd_cs4281 {
456         int irq;
457
458         void __iomem *ba0;              /* virtual (accessible) address */
459         void __iomem *ba1;              /* virtual (accessible) address */
460         unsigned long ba0_addr;
461         unsigned long ba1_addr;
462
463         int dual_codec;
464
465         ac97_bus_t *ac97_bus;
466         ac97_t *ac97;
467         ac97_t *ac97_secondary;
468
469         struct pci_dev *pci;
470         snd_card_t *card;
471         snd_pcm_t *pcm;
472         snd_rawmidi_t *rmidi;
473         snd_rawmidi_substream_t *midi_input;
474         snd_rawmidi_substream_t *midi_output;
475
476         cs4281_dma_t dma[4];
477
478         unsigned char src_left_play_slot;
479         unsigned char src_right_play_slot;
480         unsigned char src_left_rec_slot;
481         unsigned char src_right_rec_slot;
482
483         unsigned int spurious_dhtc_irq;
484         unsigned int spurious_dtc_irq;
485
486         spinlock_t reg_lock;
487         unsigned int midcr;
488         unsigned int uartm;
489
490         struct gameport *gameport;
491
492 #ifdef CONFIG_PM
493         u32 suspend_regs[SUSPEND_REGISTERS];
494 #endif
495
496 };
497
498 static irqreturn_t snd_cs4281_interrupt(int irq, void *dev_id, struct pt_regs *regs);
499
500 static struct pci_device_id snd_cs4281_ids[] = {
501         { 0x1013, 0x6005, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0, },   /* CS4281 */
502         { 0, }
503 };
504
505 MODULE_DEVICE_TABLE(pci, snd_cs4281_ids);
506
507 /*
508  *  constants
509  */
510
511 #define CS4281_FIFO_SIZE        32
512
513 /*
514  *  common I/O routines
515  */
516
517 static void snd_cs4281_delay(unsigned int delay)
518 {
519         if (delay > 999) {
520                 unsigned long end_time;
521                 delay = (delay * HZ) / 1000000;
522                 if (delay < 1)
523                         delay = 1;
524                 end_time = jiffies + delay;
525                 do {
526                         schedule_timeout_uninterruptible(1);
527                 } while (time_after_eq(end_time, jiffies));
528         } else {
529                 udelay(delay);
530         }
531 }
532
533 static inline void snd_cs4281_delay_long(void)
534 {
535         schedule_timeout_uninterruptible(1);
536 }
537
538 static inline void snd_cs4281_pokeBA0(cs4281_t *chip, unsigned long offset, unsigned int val)
539 {
540         writel(val, chip->ba0 + offset);
541 }
542
543 static inline unsigned int snd_cs4281_peekBA0(cs4281_t *chip, unsigned long offset)
544 {
545         return readl(chip->ba0 + offset);
546 }
547
548 static void snd_cs4281_ac97_write(ac97_t *ac97,
549                                   unsigned short reg, unsigned short val)
550 {
551         /*
552          *  1. Write ACCAD = Command Address Register = 46Ch for AC97 register address
553          *  2. Write ACCDA = Command Data Register = 470h    for data to write to AC97
554          *  3. Write ACCTL = Control Register = 460h for initiating the write
555          *  4. Read ACCTL = 460h, DCV should be reset by now and 460h = 07h
556          *  5. if DCV not cleared, break and return error
557          */
558         cs4281_t *chip = ac97->private_data;
559         int count;
560
561         /*
562          *  Setup the AC97 control registers on the CS461x to send the
563          *  appropriate command to the AC97 to perform the read.
564          *  ACCAD = Command Address Register = 46Ch
565          *  ACCDA = Command Data Register = 470h
566          *  ACCTL = Control Register = 460h
567          *  set DCV - will clear when process completed
568          *  reset CRW - Write command
569          *  set VFRM - valid frame enabled
570          *  set ESYN - ASYNC generation enabled
571          *  set RSTN - ARST# inactive, AC97 codec not reset
572          */
573         snd_cs4281_pokeBA0(chip, BA0_ACCAD, reg);
574         snd_cs4281_pokeBA0(chip, BA0_ACCDA, val);
575         snd_cs4281_pokeBA0(chip, BA0_ACCTL, BA0_ACCTL_DCV | BA0_ACCTL_VFRM |
576                                             BA0_ACCTL_ESYN | (ac97->num ? BA0_ACCTL_TC : 0));
577         for (count = 0; count < 2000; count++) {
578                 /*
579                  *  First, we want to wait for a short time.
580                  */
581                 udelay(10);
582                 /*
583                  *  Now, check to see if the write has completed.
584                  *  ACCTL = 460h, DCV should be reset by now and 460h = 07h
585                  */
586                 if (!(snd_cs4281_peekBA0(chip, BA0_ACCTL) & BA0_ACCTL_DCV)) {
587                         return;
588                 }
589         }
590         snd_printk(KERN_ERR "AC'97 write problem, reg = 0x%x, val = 0x%x\n", reg, val);
591 }
592
593 static unsigned short snd_cs4281_ac97_read(ac97_t *ac97,
594                                            unsigned short reg)
595 {
596         cs4281_t *chip = ac97->private_data;
597         int count;
598         unsigned short result;
599         // FIXME: volatile is necessary in the following due to a bug of
600         // some gcc versions
601         volatile int ac97_num = ((volatile ac97_t *)ac97)->num;
602
603         /*
604          *  1. Write ACCAD = Command Address Register = 46Ch for AC97 register address
605          *  2. Write ACCDA = Command Data Register = 470h    for data to write to AC97 
606          *  3. Write ACCTL = Control Register = 460h for initiating the write
607          *  4. Read ACCTL = 460h, DCV should be reset by now and 460h = 17h
608          *  5. if DCV not cleared, break and return error
609          *  6. Read ACSTS = Status Register = 464h, check VSTS bit
610          */
611
612         snd_cs4281_peekBA0(chip, ac97_num ? BA0_ACSDA2 : BA0_ACSDA);
613
614         /*
615          *  Setup the AC97 control registers on the CS461x to send the
616          *  appropriate command to the AC97 to perform the read.
617          *  ACCAD = Command Address Register = 46Ch
618          *  ACCDA = Command Data Register = 470h
619          *  ACCTL = Control Register = 460h
620          *  set DCV - will clear when process completed
621          *  set CRW - Read command
622          *  set VFRM - valid frame enabled
623          *  set ESYN - ASYNC generation enabled
624          *  set RSTN - ARST# inactive, AC97 codec not reset
625          */
626
627         snd_cs4281_pokeBA0(chip, BA0_ACCAD, reg);
628         snd_cs4281_pokeBA0(chip, BA0_ACCDA, 0);
629         snd_cs4281_pokeBA0(chip, BA0_ACCTL, BA0_ACCTL_DCV | BA0_ACCTL_CRW |
630                                             BA0_ACCTL_VFRM | BA0_ACCTL_ESYN |
631                            (ac97_num ? BA0_ACCTL_TC : 0));
632
633
634         /*
635          *  Wait for the read to occur.
636          */
637         for (count = 0; count < 500; count++) {
638                 /*
639                  *  First, we want to wait for a short time.
640                  */
641                 udelay(10);
642                 /*
643                  *  Now, check to see if the read has completed.
644                  *  ACCTL = 460h, DCV should be reset by now and 460h = 17h
645                  */
646                 if (!(snd_cs4281_peekBA0(chip, BA0_ACCTL) & BA0_ACCTL_DCV))
647                         goto __ok1;
648         }
649
650         snd_printk(KERN_ERR "AC'97 read problem (ACCTL_DCV), reg = 0x%x\n", reg);
651         result = 0xffff;
652         goto __end;
653         
654       __ok1:
655         /*
656          *  Wait for the valid status bit to go active.
657          */
658         for (count = 0; count < 100; count++) {
659                 /*
660                  *  Read the AC97 status register.
661                  *  ACSTS = Status Register = 464h
662                  *  VSTS - Valid Status
663                  */
664                 if (snd_cs4281_peekBA0(chip, ac97_num ? BA0_ACSTS2 : BA0_ACSTS) & BA0_ACSTS_VSTS)
665                         goto __ok2;
666                 udelay(10);
667         }
668         
669         snd_printk(KERN_ERR "AC'97 read problem (ACSTS_VSTS), reg = 0x%x\n", reg);
670         result = 0xffff;
671         goto __end;
672
673       __ok2:
674         /*
675          *  Read the data returned from the AC97 register.
676          *  ACSDA = Status Data Register = 474h
677          */
678         result = snd_cs4281_peekBA0(chip, ac97_num ? BA0_ACSDA2 : BA0_ACSDA);
679
680       __end:
681         return result;
682 }
683
684 /*
685  *  PCM part
686  */
687
688 static int snd_cs4281_trigger(snd_pcm_substream_t *substream, int cmd)
689 {
690         cs4281_dma_t *dma = (cs4281_dma_t *)substream->runtime->private_data;
691         cs4281_t *chip = snd_pcm_substream_chip(substream);
692
693         spin_lock(&chip->reg_lock);
694         switch (cmd) {
695         case SNDRV_PCM_TRIGGER_PAUSE_PUSH:
696                 dma->valDCR |= BA0_DCR_MSK;
697                 dma->valFCR |= BA0_FCR_FEN;
698                 break;
699         case SNDRV_PCM_TRIGGER_PAUSE_RELEASE:
700                 dma->valDCR &= ~BA0_DCR_MSK;
701                 dma->valFCR &= ~BA0_FCR_FEN;
702                 break;
703         case SNDRV_PCM_TRIGGER_START:
704         case SNDRV_PCM_TRIGGER_RESUME:
705                 snd_cs4281_pokeBA0(chip, dma->regDMR, dma->valDMR & ~BA0_DMR_DMA);
706                 dma->valDMR |= BA0_DMR_DMA;
707                 dma->valDCR &= ~BA0_DCR_MSK;
708                 dma->valFCR |= BA0_FCR_FEN;
709                 break;
710         case SNDRV_PCM_TRIGGER_STOP:
711         case SNDRV_PCM_TRIGGER_SUSPEND:
712                 dma->valDMR &= ~(BA0_DMR_DMA|BA0_DMR_POLL);
713                 dma->valDCR |= BA0_DCR_MSK;
714                 dma->valFCR &= ~BA0_FCR_FEN;
715                 /* Leave wave playback FIFO enabled for FM */
716                 if (dma->regFCR != BA0_FCR0)
717                         dma->valFCR &= ~BA0_FCR_FEN;
718                 break;
719         default:
720                 spin_unlock(&chip->reg_lock);
721                 return -EINVAL;
722         }
723         snd_cs4281_pokeBA0(chip, dma->regDMR, dma->valDMR);
724         snd_cs4281_pokeBA0(chip, dma->regFCR, dma->valFCR);
725         snd_cs4281_pokeBA0(chip, dma->regDCR, dma->valDCR);
726         spin_unlock(&chip->reg_lock);
727         return 0;
728 }
729
730 static unsigned int snd_cs4281_rate(unsigned int rate, unsigned int *real_rate)
731 {
732         unsigned int val = ~0;
733         
734         if (real_rate)
735                 *real_rate = rate;
736         /* special "hardcoded" rates */
737         switch (rate) {
738         case 8000:      return 5;
739         case 11025:     return 4;
740         case 16000:     return 3;
741         case 22050:     return 2;
742         case 44100:     return 1;
743         case 48000:     return 0;
744         default:
745                 goto __variable;
746         }
747       __variable:
748         val = 1536000 / rate;
749         if (real_rate)
750                 *real_rate = 1536000 / val;
751         return val;
752 }
753
754 static void snd_cs4281_mode(cs4281_t *chip, cs4281_dma_t *dma, snd_pcm_runtime_t *runtime, int capture, int src)
755 {
756         int rec_mono;
757
758         dma->valDMR = BA0_DMR_TYPE_SINGLE | BA0_DMR_AUTO |
759                       (capture ? BA0_DMR_TR_WRITE : BA0_DMR_TR_READ);
760         if (runtime->channels == 1)
761                 dma->valDMR |= BA0_DMR_MONO;
762         if (snd_pcm_format_unsigned(runtime->format) > 0)
763                 dma->valDMR |= BA0_DMR_USIGN;
764         if (snd_pcm_format_big_endian(runtime->format) > 0)
765                 dma->valDMR |= BA0_DMR_BEND;
766         switch (snd_pcm_format_width(runtime->format)) {
767         case 8: dma->valDMR |= BA0_DMR_SIZE8;
768                 if (runtime->channels == 1)
769                         dma->valDMR |= BA0_DMR_SWAPC;
770                 break;
771         case 32: dma->valDMR |= BA0_DMR_SIZE20; break;
772         }
773         dma->frag = 0;  /* for workaround */
774         dma->valDCR = BA0_DCR_TCIE | BA0_DCR_MSK;
775         if (runtime->buffer_size != runtime->period_size)
776                 dma->valDCR |= BA0_DCR_HTCIE;
777         /* Initialize DMA */
778         snd_cs4281_pokeBA0(chip, dma->regDBA, runtime->dma_addr);
779         snd_cs4281_pokeBA0(chip, dma->regDBC, runtime->buffer_size - 1);
780         rec_mono = (chip->dma[1].valDMR & BA0_DMR_MONO) == BA0_DMR_MONO;
781         snd_cs4281_pokeBA0(chip, BA0_SRCSA, (chip->src_left_play_slot << 0) |
782                                             (chip->src_right_play_slot << 8) |
783                                             (chip->src_left_rec_slot << 16) |
784                                             ((rec_mono ? 31 : chip->src_right_rec_slot) << 24));
785         if (!src)
786                 goto __skip_src;
787         if (!capture) {
788                 if (dma->left_slot == chip->src_left_play_slot) {
789                         unsigned int val = snd_cs4281_rate(runtime->rate, NULL);
790                         snd_assert(dma->right_slot == chip->src_right_play_slot, );
791                         snd_cs4281_pokeBA0(chip, BA0_DACSR, val);
792                 }
793         } else {
794                 if (dma->left_slot == chip->src_left_rec_slot) {
795                         unsigned int val = snd_cs4281_rate(runtime->rate, NULL);
796                         snd_assert(dma->right_slot == chip->src_right_rec_slot, );
797                         snd_cs4281_pokeBA0(chip, BA0_ADCSR, val);
798                 }
799         }
800       __skip_src:
801         /* Deactivate wave playback FIFO before changing slot assignments */
802         if (dma->regFCR == BA0_FCR0)
803                 snd_cs4281_pokeBA0(chip, dma->regFCR, snd_cs4281_peekBA0(chip, dma->regFCR) & ~BA0_FCR_FEN);
804         /* Initialize FIFO */
805         dma->valFCR = BA0_FCR_LS(dma->left_slot) |
806                       BA0_FCR_RS(capture && (dma->valDMR & BA0_DMR_MONO) ? 31 : dma->right_slot) |
807                       BA0_FCR_SZ(CS4281_FIFO_SIZE) |
808                       BA0_FCR_OF(dma->fifo_offset);
809         snd_cs4281_pokeBA0(chip, dma->regFCR, dma->valFCR | (capture ? BA0_FCR_PSH : 0));
810         /* Activate FIFO again for FM playback */
811         if (dma->regFCR == BA0_FCR0)
812                 snd_cs4281_pokeBA0(chip, dma->regFCR, dma->valFCR | BA0_FCR_FEN);
813         /* Clear FIFO Status and Interrupt Control Register */
814         snd_cs4281_pokeBA0(chip, dma->regFSIC, 0);
815 }
816
817 static int snd_cs4281_hw_params(snd_pcm_substream_t * substream,
818                                 snd_pcm_hw_params_t * hw_params)
819 {
820         return snd_pcm_lib_malloc_pages(substream, params_buffer_bytes(hw_params));
821 }
822
823 static int snd_cs4281_hw_free(snd_pcm_substream_t * substream)
824 {
825         return snd_pcm_lib_free_pages(substream);
826 }
827
828 static int snd_cs4281_playback_prepare(snd_pcm_substream_t * substream)
829 {
830         snd_pcm_runtime_t *runtime = substream->runtime;
831         cs4281_dma_t *dma = (cs4281_dma_t *)runtime->private_data;
832         cs4281_t *chip = snd_pcm_substream_chip(substream);
833
834         spin_lock_irq(&chip->reg_lock);
835         snd_cs4281_mode(chip, dma, runtime, 0, 1);
836         spin_unlock_irq(&chip->reg_lock);
837         return 0;
838 }
839
840 static int snd_cs4281_capture_prepare(snd_pcm_substream_t * substream)
841 {
842         snd_pcm_runtime_t *runtime = substream->runtime;
843         cs4281_dma_t *dma = (cs4281_dma_t *)runtime->private_data;
844         cs4281_t *chip = snd_pcm_substream_chip(substream);
845
846         spin_lock_irq(&chip->reg_lock);
847         snd_cs4281_mode(chip, dma, runtime, 1, 1);
848         spin_unlock_irq(&chip->reg_lock);
849         return 0;
850 }
851
852 static snd_pcm_uframes_t snd_cs4281_pointer(snd_pcm_substream_t * substream)
853 {
854         snd_pcm_runtime_t *runtime = substream->runtime;
855         cs4281_dma_t *dma = (cs4281_dma_t *)runtime->private_data;
856         cs4281_t *chip = snd_pcm_substream_chip(substream);
857
858         // printk("DCC = 0x%x, buffer_size = 0x%x, jiffies = %li\n", snd_cs4281_peekBA0(chip, dma->regDCC), runtime->buffer_size, jiffies);
859         return runtime->buffer_size -
860                snd_cs4281_peekBA0(chip, dma->regDCC) - 1;
861 }
862
863 static snd_pcm_hardware_t snd_cs4281_playback =
864 {
865         .info =                 (SNDRV_PCM_INFO_MMAP |
866                                  SNDRV_PCM_INFO_INTERLEAVED |
867                                  SNDRV_PCM_INFO_MMAP_VALID |
868                                  SNDRV_PCM_INFO_PAUSE |
869                                  SNDRV_PCM_INFO_RESUME |
870                                  SNDRV_PCM_INFO_SYNC_START),
871         .formats =              SNDRV_PCM_FMTBIT_U8 | SNDRV_PCM_FMTBIT_S8 |
872                                 SNDRV_PCM_FMTBIT_U16_LE | SNDRV_PCM_FMTBIT_S16_LE |
873                                 SNDRV_PCM_FMTBIT_U16_BE | SNDRV_PCM_FMTBIT_S16_BE |
874                                 SNDRV_PCM_FMTBIT_U32_LE | SNDRV_PCM_FMTBIT_S32_LE |
875                                 SNDRV_PCM_FMTBIT_U32_BE | SNDRV_PCM_FMTBIT_S32_BE,
876         .rates =                SNDRV_PCM_RATE_CONTINUOUS | SNDRV_PCM_RATE_8000_48000,
877         .rate_min =             4000,
878         .rate_max =             48000,
879         .channels_min =         1,
880         .channels_max =         2,
881         .buffer_bytes_max =     (512*1024),
882         .period_bytes_min =     64,
883         .period_bytes_max =     (512*1024),
884         .periods_min =          1,
885         .periods_max =          2,
886         .fifo_size =            CS4281_FIFO_SIZE,
887 };
888
889 static snd_pcm_hardware_t snd_cs4281_capture =
890 {
891         .info =                 (SNDRV_PCM_INFO_MMAP |
892                                  SNDRV_PCM_INFO_INTERLEAVED |
893                                  SNDRV_PCM_INFO_MMAP_VALID |
894                                  SNDRV_PCM_INFO_PAUSE |
895                                  SNDRV_PCM_INFO_RESUME |
896                                  SNDRV_PCM_INFO_SYNC_START),
897         .formats =              SNDRV_PCM_FMTBIT_U8 | SNDRV_PCM_FMTBIT_S8 |
898                                 SNDRV_PCM_FMTBIT_U16_LE | SNDRV_PCM_FMTBIT_S16_LE |
899                                 SNDRV_PCM_FMTBIT_U16_BE | SNDRV_PCM_FMTBIT_S16_BE |
900                                 SNDRV_PCM_FMTBIT_U32_LE | SNDRV_PCM_FMTBIT_S32_LE |
901                                 SNDRV_PCM_FMTBIT_U32_BE | SNDRV_PCM_FMTBIT_S32_BE,
902         .rates =                SNDRV_PCM_RATE_CONTINUOUS | SNDRV_PCM_RATE_8000_48000,
903         .rate_min =             4000,
904         .rate_max =             48000,
905         .channels_min =         1,
906         .channels_max =         2,
907         .buffer_bytes_max =     (512*1024),
908         .period_bytes_min =     64,
909         .period_bytes_max =     (512*1024),
910         .periods_min =          1,
911         .periods_max =          2,
912         .fifo_size =            CS4281_FIFO_SIZE,
913 };
914
915 static int snd_cs4281_playback_open(snd_pcm_substream_t * substream)
916 {
917         cs4281_t *chip = snd_pcm_substream_chip(substream);
918         snd_pcm_runtime_t *runtime = substream->runtime;
919         cs4281_dma_t *dma;
920
921         dma = &chip->dma[0];
922         dma->substream = substream;
923         dma->left_slot = 0;
924         dma->right_slot = 1;
925         runtime->private_data = dma;
926         runtime->hw = snd_cs4281_playback;
927         snd_pcm_set_sync(substream);
928         /* should be detected from the AC'97 layer, but it seems
929            that although CS4297A rev B reports 18-bit ADC resolution,
930            samples are 20-bit */
931         snd_pcm_hw_constraint_msbits(runtime, 0, 32, 20);
932         return 0;
933 }
934
935 static int snd_cs4281_capture_open(snd_pcm_substream_t * substream)
936 {
937         cs4281_t *chip = snd_pcm_substream_chip(substream);
938         snd_pcm_runtime_t *runtime = substream->runtime;
939         cs4281_dma_t *dma;
940
941         dma = &chip->dma[1];
942         dma->substream = substream;
943         dma->left_slot = 10;
944         dma->right_slot = 11;
945         runtime->private_data = dma;
946         runtime->hw = snd_cs4281_capture;
947         snd_pcm_set_sync(substream);
948         /* should be detected from the AC'97 layer, but it seems
949            that although CS4297A rev B reports 18-bit ADC resolution,
950            samples are 20-bit */
951         snd_pcm_hw_constraint_msbits(runtime, 0, 32, 20);
952         return 0;
953 }
954
955 static int snd_cs4281_playback_close(snd_pcm_substream_t * substream)
956 {
957         cs4281_dma_t *dma = (cs4281_dma_t *)substream->runtime->private_data;
958
959         dma->substream = NULL;
960         return 0;
961 }
962
963 static int snd_cs4281_capture_close(snd_pcm_substream_t * substream)
964 {
965         cs4281_dma_t *dma = (cs4281_dma_t *)substream->runtime->private_data;
966
967         dma->substream = NULL;
968         return 0;
969 }
970
971 static snd_pcm_ops_t snd_cs4281_playback_ops = {
972         .open =         snd_cs4281_playback_open,
973         .close =        snd_cs4281_playback_close,
974         .ioctl =        snd_pcm_lib_ioctl,
975         .hw_params =    snd_cs4281_hw_params,
976         .hw_free =      snd_cs4281_hw_free,
977         .prepare =      snd_cs4281_playback_prepare,
978         .trigger =      snd_cs4281_trigger,
979         .pointer =      snd_cs4281_pointer,
980 };
981
982 static snd_pcm_ops_t snd_cs4281_capture_ops = {
983         .open =         snd_cs4281_capture_open,
984         .close =        snd_cs4281_capture_close,
985         .ioctl =        snd_pcm_lib_ioctl,
986         .hw_params =    snd_cs4281_hw_params,
987         .hw_free =      snd_cs4281_hw_free,
988         .prepare =      snd_cs4281_capture_prepare,
989         .trigger =      snd_cs4281_trigger,
990         .pointer =      snd_cs4281_pointer,
991 };
992
993 static int __devinit snd_cs4281_pcm(cs4281_t * chip, int device, snd_pcm_t ** rpcm)
994 {
995         snd_pcm_t *pcm;
996         int err;
997
998         if (rpcm)
999                 *rpcm = NULL;
1000         err = snd_pcm_new(chip->card, "CS4281", device, 1, 1, &pcm);
1001         if (err < 0)
1002                 return err;
1003
1004         snd_pcm_set_ops(pcm, SNDRV_PCM_STREAM_PLAYBACK, &snd_cs4281_playback_ops);
1005         snd_pcm_set_ops(pcm, SNDRV_PCM_STREAM_CAPTURE, &snd_cs4281_capture_ops);
1006
1007         pcm->private_data = chip;
1008         pcm->info_flags = 0;
1009         strcpy(pcm->name, "CS4281");
1010         chip->pcm = pcm;
1011
1012         snd_pcm_lib_preallocate_pages_for_all(pcm, SNDRV_DMA_TYPE_DEV,
1013                                               snd_dma_pci_data(chip->pci), 64*1024, 512*1024);
1014
1015         if (rpcm)
1016                 *rpcm = pcm;
1017         return 0;
1018 }
1019
1020 /*
1021  *  Mixer section
1022  */
1023
1024 #define CS_VOL_MASK     0x1f
1025
1026 static int snd_cs4281_info_volume(snd_kcontrol_t * kcontrol, snd_ctl_elem_info_t * uinfo)
1027 {
1028         uinfo->type              = SNDRV_CTL_ELEM_TYPE_INTEGER;
1029         uinfo->count             = 2;
1030         uinfo->value.integer.min = 0;
1031         uinfo->value.integer.max = CS_VOL_MASK;
1032         return 0;
1033 }
1034  
1035 static int snd_cs4281_get_volume(snd_kcontrol_t * kcontrol, snd_ctl_elem_value_t * ucontrol)
1036 {
1037         cs4281_t *chip = snd_kcontrol_chip(kcontrol);
1038         int regL = (kcontrol->private_value >> 16) & 0xffff;
1039         int regR = kcontrol->private_value & 0xffff;
1040         int volL, volR;
1041
1042         volL = CS_VOL_MASK - (snd_cs4281_peekBA0(chip, regL) & CS_VOL_MASK);
1043         volR = CS_VOL_MASK - (snd_cs4281_peekBA0(chip, regR) & CS_VOL_MASK);
1044
1045         ucontrol->value.integer.value[0] = volL;
1046         ucontrol->value.integer.value[1] = volR;
1047         return 0;
1048 }
1049
1050 static int snd_cs4281_put_volume(snd_kcontrol_t * kcontrol, snd_ctl_elem_value_t * ucontrol)
1051 {
1052         cs4281_t *chip = snd_kcontrol_chip(kcontrol);
1053         int change = 0;
1054         int regL = (kcontrol->private_value >> 16) & 0xffff;
1055         int regR = kcontrol->private_value & 0xffff;
1056         int volL, volR;
1057
1058         volL = CS_VOL_MASK - (snd_cs4281_peekBA0(chip, regL) & CS_VOL_MASK);
1059         volR = CS_VOL_MASK - (snd_cs4281_peekBA0(chip, regR) & CS_VOL_MASK);
1060
1061         if (ucontrol->value.integer.value[0] != volL) {
1062                 volL = CS_VOL_MASK - (ucontrol->value.integer.value[0] & CS_VOL_MASK);
1063                 snd_cs4281_pokeBA0(chip, regL, volL);
1064                 change = 1;
1065         }
1066         if (ucontrol->value.integer.value[0] != volL) {
1067                 volR = CS_VOL_MASK - (ucontrol->value.integer.value[1] & CS_VOL_MASK);
1068                 snd_cs4281_pokeBA0(chip, regR, volR);
1069                 change = 1;
1070         }
1071         return change;
1072 }
1073
1074 static snd_kcontrol_new_t snd_cs4281_fm_vol = 
1075 {
1076         .iface = SNDRV_CTL_ELEM_IFACE_MIXER,
1077         .name = "Synth Playback Volume",
1078         .info = snd_cs4281_info_volume, 
1079         .get = snd_cs4281_get_volume,
1080         .put = snd_cs4281_put_volume, 
1081         .private_value = ((BA0_FMLVC << 16) | BA0_FMRVC),
1082 };
1083
1084 static snd_kcontrol_new_t snd_cs4281_pcm_vol = 
1085 {
1086         .iface = SNDRV_CTL_ELEM_IFACE_MIXER,
1087         .name = "PCM Stream Playback Volume",
1088         .info = snd_cs4281_info_volume, 
1089         .get = snd_cs4281_get_volume,
1090         .put = snd_cs4281_put_volume, 
1091         .private_value = ((BA0_PPLVC << 16) | BA0_PPRVC),
1092 };
1093
1094 static void snd_cs4281_mixer_free_ac97_bus(ac97_bus_t *bus)
1095 {
1096         cs4281_t *chip = bus->private_data;
1097         chip->ac97_bus = NULL;
1098 }
1099
1100 static void snd_cs4281_mixer_free_ac97(ac97_t *ac97)
1101 {
1102         cs4281_t *chip = ac97->private_data;
1103         if (ac97->num)
1104                 chip->ac97_secondary = NULL;
1105         else
1106                 chip->ac97 = NULL;
1107 }
1108
1109 static int __devinit snd_cs4281_mixer(cs4281_t * chip)
1110 {
1111         snd_card_t *card = chip->card;
1112         ac97_template_t ac97;
1113         int err;
1114         static ac97_bus_ops_t ops = {
1115                 .write = snd_cs4281_ac97_write,
1116                 .read = snd_cs4281_ac97_read,
1117         };
1118
1119         if ((err = snd_ac97_bus(card, 0, &ops, chip, &chip->ac97_bus)) < 0)
1120                 return err;
1121         chip->ac97_bus->private_free = snd_cs4281_mixer_free_ac97_bus;
1122
1123         memset(&ac97, 0, sizeof(ac97));
1124         ac97.private_data = chip;
1125         ac97.private_free = snd_cs4281_mixer_free_ac97;
1126         if ((err = snd_ac97_mixer(chip->ac97_bus, &ac97, &chip->ac97)) < 0)
1127                 return err;
1128         if (chip->dual_codec) {
1129                 ac97.num = 1;
1130                 if ((err = snd_ac97_mixer(chip->ac97_bus, &ac97, &chip->ac97_secondary)) < 0)
1131                         return err;
1132         }
1133         if ((err = snd_ctl_add(card, snd_ctl_new1(&snd_cs4281_fm_vol, chip))) < 0)
1134                 return err;
1135         if ((err = snd_ctl_add(card, snd_ctl_new1(&snd_cs4281_pcm_vol, chip))) < 0)
1136                 return err;
1137         return 0;
1138 }
1139
1140
1141 /*
1142  * proc interface
1143  */
1144
1145 static void snd_cs4281_proc_read(snd_info_entry_t *entry, 
1146                                   snd_info_buffer_t * buffer)
1147 {
1148         cs4281_t *chip = entry->private_data;
1149
1150         snd_iprintf(buffer, "Cirrus Logic CS4281\n\n");
1151         snd_iprintf(buffer, "Spurious half IRQs   : %u\n", chip->spurious_dhtc_irq);
1152         snd_iprintf(buffer, "Spurious end IRQs    : %u\n", chip->spurious_dtc_irq);
1153 }
1154
1155 static long snd_cs4281_BA0_read(snd_info_entry_t *entry, void *file_private_data,
1156                                 struct file *file, char __user *buf,
1157                                 unsigned long count, unsigned long pos)
1158 {
1159         long size;
1160         cs4281_t *chip = entry->private_data;
1161         
1162         size = count;
1163         if (pos + size > CS4281_BA0_SIZE)
1164                 size = (long)CS4281_BA0_SIZE - pos;
1165         if (size > 0) {
1166                 if (copy_to_user_fromio(buf, chip->ba0 + pos, size))
1167                         return -EFAULT;
1168         }
1169         return size;
1170 }
1171
1172 static long snd_cs4281_BA1_read(snd_info_entry_t *entry, void *file_private_data,
1173                                 struct file *file, char __user *buf,
1174                                 unsigned long count, unsigned long pos)
1175 {
1176         long size;
1177         cs4281_t *chip = entry->private_data;
1178         
1179         size = count;
1180         if (pos + size > CS4281_BA1_SIZE)
1181                 size = (long)CS4281_BA1_SIZE - pos;
1182         if (size > 0) {
1183                 if (copy_to_user_fromio(buf, chip->ba1 + pos, size))
1184                         return -EFAULT;
1185         }
1186         return size;
1187 }
1188
1189 static struct snd_info_entry_ops snd_cs4281_proc_ops_BA0 = {
1190         .read = snd_cs4281_BA0_read,
1191 };
1192
1193 static struct snd_info_entry_ops snd_cs4281_proc_ops_BA1 = {
1194         .read = snd_cs4281_BA1_read,
1195 };
1196
1197 static void __devinit snd_cs4281_proc_init(cs4281_t * chip)
1198 {
1199         snd_info_entry_t *entry;
1200
1201         if (! snd_card_proc_new(chip->card, "cs4281", &entry))
1202                 snd_info_set_text_ops(entry, chip, 1024, snd_cs4281_proc_read);
1203         if (! snd_card_proc_new(chip->card, "cs4281_BA0", &entry)) {
1204                 entry->content = SNDRV_INFO_CONTENT_DATA;
1205                 entry->private_data = chip;
1206                 entry->c.ops = &snd_cs4281_proc_ops_BA0;
1207                 entry->size = CS4281_BA0_SIZE;
1208         }
1209         if (! snd_card_proc_new(chip->card, "cs4281_BA1", &entry)) {
1210                 entry->content = SNDRV_INFO_CONTENT_DATA;
1211                 entry->private_data = chip;
1212                 entry->c.ops = &snd_cs4281_proc_ops_BA1;
1213                 entry->size = CS4281_BA1_SIZE;
1214         }
1215 }
1216
1217 /*
1218  * joystick support
1219  */
1220
1221 #if defined(CONFIG_GAMEPORT) || (defined(MODULE) && defined(CONFIG_GAMEPORT_MODULE))
1222
1223 static void snd_cs4281_gameport_trigger(struct gameport *gameport)
1224 {
1225         cs4281_t *chip = gameport_get_port_data(gameport);
1226
1227         snd_assert(chip, return);
1228         snd_cs4281_pokeBA0(chip, BA0_JSPT, 0xff);
1229 }
1230
1231 static unsigned char snd_cs4281_gameport_read(struct gameport *gameport)
1232 {
1233         cs4281_t *chip = gameport_get_port_data(gameport);
1234
1235         snd_assert(chip, return 0);
1236         return snd_cs4281_peekBA0(chip, BA0_JSPT);
1237 }
1238
1239 #ifdef COOKED_MODE
1240 static int snd_cs4281_gameport_cooked_read(struct gameport *gameport, int *axes, int *buttons)
1241 {
1242         cs4281_t *chip = gameport_get_port_data(gameport);
1243         unsigned js1, js2, jst;
1244         
1245         snd_assert(chip, return 0);
1246
1247         js1 = snd_cs4281_peekBA0(chip, BA0_JSC1);
1248         js2 = snd_cs4281_peekBA0(chip, BA0_JSC2);
1249         jst = snd_cs4281_peekBA0(chip, BA0_JSPT);
1250         
1251         *buttons = (~jst >> 4) & 0x0F; 
1252         
1253         axes[0] = ((js1 & JSC1_Y1V_MASK) >> JSC1_Y1V_SHIFT) & 0xFFFF;
1254         axes[1] = ((js1 & JSC1_X1V_MASK) >> JSC1_X1V_SHIFT) & 0xFFFF;
1255         axes[2] = ((js2 & JSC2_Y2V_MASK) >> JSC2_Y2V_SHIFT) & 0xFFFF;
1256         axes[3] = ((js2 & JSC2_X2V_MASK) >> JSC2_X2V_SHIFT) & 0xFFFF;
1257
1258         for (jst = 0; jst < 4; ++jst)
1259                 if (axes[jst] == 0xFFFF) axes[jst] = -1;
1260         return 0;
1261 }
1262 #else
1263 #define snd_cs4281_gameport_cooked_read NULL
1264 #endif
1265
1266 static int snd_cs4281_gameport_open(struct gameport *gameport, int mode)
1267 {
1268         switch (mode) {
1269 #ifdef COOKED_MODE
1270         case GAMEPORT_MODE_COOKED:
1271                 return 0;
1272 #endif
1273         case GAMEPORT_MODE_RAW:
1274                 return 0;
1275         default:
1276                 return -1;
1277         }
1278         return 0;
1279 }
1280
1281 static int __devinit snd_cs4281_create_gameport(cs4281_t *chip)
1282 {
1283         struct gameport *gp;
1284
1285         chip->gameport = gp = gameport_allocate_port();
1286         if (!gp) {
1287                 printk(KERN_ERR "cs4281: cannot allocate memory for gameport\n");
1288                 return -ENOMEM;
1289         }
1290
1291         gameport_set_name(gp, "CS4281 Gameport");
1292         gameport_set_phys(gp, "pci%s/gameport0", pci_name(chip->pci));
1293         gameport_set_dev_parent(gp, &chip->pci->dev);
1294         gp->open = snd_cs4281_gameport_open;
1295         gp->read = snd_cs4281_gameport_read;
1296         gp->trigger = snd_cs4281_gameport_trigger;
1297         gp->cooked_read = snd_cs4281_gameport_cooked_read;
1298         gameport_set_port_data(gp, chip);
1299
1300         snd_cs4281_pokeBA0(chip, BA0_JSIO, 0xFF); // ?
1301         snd_cs4281_pokeBA0(chip, BA0_JSCTL, JSCTL_SP_MEDIUM_SLOW);
1302
1303         gameport_register_port(gp);
1304
1305         return 0;
1306 }
1307
1308 static void snd_cs4281_free_gameport(cs4281_t *chip)
1309 {
1310         if (chip->gameport) {
1311                 gameport_unregister_port(chip->gameport);
1312                 chip->gameport = NULL;
1313         }
1314 }
1315 #else
1316 static inline int snd_cs4281_create_gameport(cs4281_t *chip) { return -ENOSYS; }
1317 static inline void snd_cs4281_free_gameport(cs4281_t *chip) { }
1318 #endif /* CONFIG_GAMEPORT || (MODULE && CONFIG_GAMEPORT_MODULE) */
1319
1320 static int snd_cs4281_free(cs4281_t *chip)
1321 {
1322         snd_cs4281_free_gameport(chip);
1323
1324         if (chip->irq >= 0)
1325                 synchronize_irq(chip->irq);
1326
1327         /* Mask interrupts */
1328         snd_cs4281_pokeBA0(chip, BA0_HIMR, 0x7fffffff);
1329         /* Stop the DLL Clock logic. */
1330         snd_cs4281_pokeBA0(chip, BA0_CLKCR1, 0);
1331         /* Sound System Power Management - Turn Everything OFF */
1332         snd_cs4281_pokeBA0(chip, BA0_SSPM, 0);
1333         /* PCI interface - D3 state */
1334         pci_set_power_state(chip->pci, 3);
1335
1336         if (chip->irq >= 0)
1337                 free_irq(chip->irq, (void *)chip);
1338         if (chip->ba0)
1339                 iounmap(chip->ba0);
1340         if (chip->ba1)
1341                 iounmap(chip->ba1);
1342         pci_release_regions(chip->pci);
1343         pci_disable_device(chip->pci);
1344
1345         kfree(chip);
1346         return 0;
1347 }
1348
1349 static int snd_cs4281_dev_free(snd_device_t *device)
1350 {
1351         cs4281_t *chip = device->device_data;
1352         return snd_cs4281_free(chip);
1353 }
1354
1355 static int snd_cs4281_chip_init(cs4281_t *chip); /* defined below */
1356 #ifdef CONFIG_PM
1357 static int cs4281_suspend(snd_card_t *card, pm_message_t state);
1358 static int cs4281_resume(snd_card_t *card);
1359 #endif
1360
1361 static int __devinit snd_cs4281_create(snd_card_t * card,
1362                                        struct pci_dev *pci,
1363                                        cs4281_t ** rchip,
1364                                        int dual_codec)
1365 {
1366         cs4281_t *chip;
1367         unsigned int tmp;
1368         int err;
1369         static snd_device_ops_t ops = {
1370                 .dev_free =     snd_cs4281_dev_free,
1371         };
1372
1373         *rchip = NULL;
1374         if ((err = pci_enable_device(pci)) < 0)
1375                 return err;
1376         chip = kzalloc(sizeof(*chip), GFP_KERNEL);
1377         if (chip == NULL) {
1378                 pci_disable_device(pci);
1379                 return -ENOMEM;
1380         }
1381         spin_lock_init(&chip->reg_lock);
1382         chip->card = card;
1383         chip->pci = pci;
1384         chip->irq = -1;
1385         pci_set_master(pci);
1386         if (dual_codec < 0 || dual_codec > 3) {
1387                 snd_printk(KERN_ERR "invalid dual_codec option %d\n", dual_codec);
1388                 dual_codec = 0;
1389         }
1390         chip->dual_codec = dual_codec;
1391
1392         if ((err = pci_request_regions(pci, "CS4281")) < 0) {
1393                 kfree(chip);
1394                 pci_disable_device(pci);
1395                 return err;
1396         }
1397         chip->ba0_addr = pci_resource_start(pci, 0);
1398         chip->ba1_addr = pci_resource_start(pci, 1);
1399
1400         if (request_irq(pci->irq, snd_cs4281_interrupt, SA_INTERRUPT|SA_SHIRQ, "CS4281", (void *)chip)) {
1401                 snd_printk(KERN_ERR "unable to grab IRQ %d\n", pci->irq);
1402                 snd_cs4281_free(chip);
1403                 return -ENOMEM;
1404         }
1405         chip->irq = pci->irq;
1406
1407         chip->ba0 = ioremap_nocache(chip->ba0_addr, pci_resource_len(pci, 0));
1408         chip->ba1 = ioremap_nocache(chip->ba1_addr, pci_resource_len(pci, 1));
1409         if (!chip->ba0 || !chip->ba1) {
1410                 snd_cs4281_free(chip);
1411                 return -ENOMEM;
1412         }
1413         
1414         tmp = snd_cs4281_chip_init(chip);
1415         if (tmp) {
1416                 snd_cs4281_free(chip);
1417                 return tmp;
1418         }
1419
1420         if ((err = snd_device_new(card, SNDRV_DEV_LOWLEVEL, chip, &ops)) < 0) {
1421                 snd_cs4281_free(chip);
1422                 return err;
1423         }
1424
1425         snd_cs4281_proc_init(chip);
1426
1427         snd_card_set_pm_callback(card, cs4281_suspend, cs4281_resume, chip);
1428
1429         snd_card_set_dev(card, &pci->dev);
1430
1431         *rchip = chip;
1432         return 0;
1433 }
1434
1435 static int snd_cs4281_chip_init(cs4281_t *chip)
1436 {
1437         unsigned int tmp;
1438         int timeout;
1439         int retry_count = 2;
1440
1441         /* Having EPPMC.FPDN=1 prevent proper chip initialisation */
1442         tmp = snd_cs4281_peekBA0(chip, BA0_EPPMC);
1443         if (tmp & BA0_EPPMC_FPDN)
1444                 snd_cs4281_pokeBA0(chip, BA0_EPPMC, tmp & ~BA0_EPPMC_FPDN);
1445
1446       __retry:
1447         tmp = snd_cs4281_peekBA0(chip, BA0_CFLR);
1448         if (tmp != BA0_CFLR_DEFAULT) {
1449                 snd_cs4281_pokeBA0(chip, BA0_CFLR, BA0_CFLR_DEFAULT);
1450                 tmp = snd_cs4281_peekBA0(chip, BA0_CFLR);
1451                 if (tmp != BA0_CFLR_DEFAULT) {
1452                         snd_printk(KERN_ERR "CFLR setup failed (0x%x)\n", tmp);
1453                         return -EIO;
1454                 }
1455         }
1456
1457         /* Set the 'Configuration Write Protect' register
1458          * to 4281h.  Allows vendor-defined configuration
1459          * space between 0e4h and 0ffh to be written. */        
1460         snd_cs4281_pokeBA0(chip, BA0_CWPR, 0x4281);
1461         
1462         if ((tmp = snd_cs4281_peekBA0(chip, BA0_SERC1)) != (BA0_SERC1_SO1EN | BA0_SERC1_AC97)) {
1463                 snd_printk(KERN_ERR "SERC1 AC'97 check failed (0x%x)\n", tmp);
1464                 return -EIO;
1465         }
1466         if ((tmp = snd_cs4281_peekBA0(chip, BA0_SERC2)) != (BA0_SERC2_SI1EN | BA0_SERC2_AC97)) {
1467                 snd_printk(KERN_ERR "SERC2 AC'97 check failed (0x%x)\n", tmp);
1468                 return -EIO;
1469         }
1470
1471         /* Sound System Power Management */
1472         snd_cs4281_pokeBA0(chip, BA0_SSPM, BA0_SSPM_MIXEN | BA0_SSPM_CSRCEN |
1473                                            BA0_SSPM_PSRCEN | BA0_SSPM_JSEN |
1474                                            BA0_SSPM_ACLEN | BA0_SSPM_FMEN);
1475
1476         /* Serial Port Power Management */
1477         /* Blast the clock control register to zero so that the
1478          * PLL starts out in a known state, and blast the master serial
1479          * port control register to zero so that the serial ports also
1480          * start out in a known state. */
1481         snd_cs4281_pokeBA0(chip, BA0_CLKCR1, 0);
1482         snd_cs4281_pokeBA0(chip, BA0_SERMC, 0);
1483
1484         /* Make ESYN go to zero to turn off
1485          * the Sync pulse on the AC97 link. */
1486         snd_cs4281_pokeBA0(chip, BA0_ACCTL, 0);
1487         udelay(50);
1488                 
1489         /*  Drive the ARST# pin low for a minimum of 1uS (as defined in the AC97
1490          *  spec) and then drive it high.  This is done for non AC97 modes since
1491          *  there might be logic external to the CS4281 that uses the ARST# line
1492          *  for a reset. */
1493         snd_cs4281_pokeBA0(chip, BA0_SPMC, 0);
1494         udelay(50);
1495         snd_cs4281_pokeBA0(chip, BA0_SPMC, BA0_SPMC_RSTN);
1496         snd_cs4281_delay(50000);
1497
1498         if (chip->dual_codec)
1499                 snd_cs4281_pokeBA0(chip, BA0_SPMC, BA0_SPMC_RSTN | BA0_SPMC_ASDI2E);
1500
1501         /*
1502          *  Set the serial port timing configuration.
1503          */
1504         snd_cs4281_pokeBA0(chip, BA0_SERMC,
1505                            (chip->dual_codec ? BA0_SERMC_TCID(chip->dual_codec) : BA0_SERMC_TCID(1)) |
1506                            BA0_SERMC_PTC_AC97 | BA0_SERMC_MSPE);
1507
1508         /*
1509          *  Start the DLL Clock logic.
1510          */
1511         snd_cs4281_pokeBA0(chip, BA0_CLKCR1, BA0_CLKCR1_DLLP);
1512         snd_cs4281_delay(50000);
1513         snd_cs4281_pokeBA0(chip, BA0_CLKCR1, BA0_CLKCR1_SWCE | BA0_CLKCR1_DLLP);
1514
1515         /*
1516          * Wait for the DLL ready signal from the clock logic.
1517          */
1518         timeout = HZ;
1519         do {
1520                 /*
1521                  *  Read the AC97 status register to see if we've seen a CODEC
1522                  *  signal from the AC97 codec.
1523                  */
1524                 if (snd_cs4281_peekBA0(chip, BA0_CLKCR1) & BA0_CLKCR1_DLLRDY)
1525                         goto __ok0;
1526                 snd_cs4281_delay_long();
1527         } while (timeout-- > 0);
1528
1529         snd_printk(KERN_ERR "DLLRDY not seen\n");
1530         return -EIO;
1531
1532       __ok0:
1533
1534         /*
1535          *  The first thing we do here is to enable sync generation.  As soon
1536          *  as we start receiving bit clock, we'll start producing the SYNC
1537          *  signal.
1538          */
1539         snd_cs4281_pokeBA0(chip, BA0_ACCTL, BA0_ACCTL_ESYN);
1540
1541         /*
1542          * Wait for the codec ready signal from the AC97 codec.
1543          */
1544         timeout = HZ;
1545         do {
1546                 /*
1547                  *  Read the AC97 status register to see if we've seen a CODEC
1548                  *  signal from the AC97 codec.
1549                  */
1550                 if (snd_cs4281_peekBA0(chip, BA0_ACSTS) & BA0_ACSTS_CRDY)
1551                         goto __ok1;
1552                 snd_cs4281_delay_long();
1553         } while (timeout-- > 0);
1554
1555         snd_printk(KERN_ERR "never read codec ready from AC'97 (0x%x)\n", snd_cs4281_peekBA0(chip, BA0_ACSTS));
1556         return -EIO;
1557
1558       __ok1:
1559         if (chip->dual_codec) {
1560                 timeout = HZ;
1561                 do {
1562                         if (snd_cs4281_peekBA0(chip, BA0_ACSTS2) & BA0_ACSTS_CRDY)
1563                                 goto __codec2_ok;
1564                         snd_cs4281_delay_long();
1565                 } while (timeout-- > 0);
1566                 snd_printk(KERN_INFO "secondary codec doesn't respond. disable it...\n");
1567                 chip->dual_codec = 0;
1568         __codec2_ok: ;
1569         }
1570
1571         /*
1572          *  Assert the valid frame signal so that we can start sending commands
1573          *  to the AC97 codec.
1574          */
1575
1576         snd_cs4281_pokeBA0(chip, BA0_ACCTL, BA0_ACCTL_VFRM | BA0_ACCTL_ESYN);
1577
1578         /*
1579          *  Wait until we've sampled input slots 3 and 4 as valid, meaning that
1580          *  the codec is pumping ADC data across the AC-link.
1581          */
1582
1583         timeout = HZ;
1584         do {
1585                 /*
1586                  *  Read the input slot valid register and see if input slots 3
1587                  *  4 are valid yet.
1588                  */
1589                 if ((snd_cs4281_peekBA0(chip, BA0_ACISV) & (BA0_ACISV_SLV(3) | BA0_ACISV_SLV(4))) == (BA0_ACISV_SLV(3) | BA0_ACISV_SLV(4)))
1590                         goto __ok2;
1591                 snd_cs4281_delay_long();
1592         } while (timeout-- > 0);
1593
1594         if (--retry_count > 0)
1595                 goto __retry;
1596         snd_printk(KERN_ERR "never read ISV3 and ISV4 from AC'97\n");
1597         return -EIO;
1598
1599       __ok2:
1600
1601         /*
1602          *  Now, assert valid frame and the slot 3 and 4 valid bits.  This will
1603          *  commense the transfer of digital audio data to the AC97 codec.
1604          */
1605         snd_cs4281_pokeBA0(chip, BA0_ACOSV, BA0_ACOSV_SLV(3) | BA0_ACOSV_SLV(4));
1606
1607         /*
1608          *  Initialize DMA structures
1609          */
1610         for (tmp = 0; tmp < 4; tmp++) {
1611                 cs4281_dma_t *dma = &chip->dma[tmp];
1612                 dma->regDBA = BA0_DBA0 + (tmp * 0x10);
1613                 dma->regDCA = BA0_DCA0 + (tmp * 0x10);
1614                 dma->regDBC = BA0_DBC0 + (tmp * 0x10);
1615                 dma->regDCC = BA0_DCC0 + (tmp * 0x10);
1616                 dma->regDMR = BA0_DMR0 + (tmp * 8);
1617                 dma->regDCR = BA0_DCR0 + (tmp * 8);
1618                 dma->regHDSR = BA0_HDSR0 + (tmp * 4);
1619                 dma->regFCR = BA0_FCR0 + (tmp * 4);
1620                 dma->regFSIC = BA0_FSIC0 + (tmp * 4);
1621                 dma->fifo_offset = tmp * CS4281_FIFO_SIZE;
1622                 snd_cs4281_pokeBA0(chip, dma->regFCR,
1623                                    BA0_FCR_LS(31) |
1624                                    BA0_FCR_RS(31) |
1625                                    BA0_FCR_SZ(CS4281_FIFO_SIZE) |
1626                                    BA0_FCR_OF(dma->fifo_offset));
1627         }
1628
1629         chip->src_left_play_slot = 0;   /* AC'97 left PCM playback (3) */
1630         chip->src_right_play_slot = 1;  /* AC'97 right PCM playback (4) */
1631         chip->src_left_rec_slot = 10;   /* AC'97 left PCM record (3) */
1632         chip->src_right_rec_slot = 11;  /* AC'97 right PCM record (4) */
1633
1634         /* Activate wave playback FIFO for FM playback */
1635         chip->dma[0].valFCR = BA0_FCR_FEN | BA0_FCR_LS(0) |
1636                               BA0_FCR_RS(1) |
1637                               BA0_FCR_SZ(CS4281_FIFO_SIZE) |
1638                               BA0_FCR_OF(chip->dma[0].fifo_offset);
1639         snd_cs4281_pokeBA0(chip, chip->dma[0].regFCR, chip->dma[0].valFCR);
1640         snd_cs4281_pokeBA0(chip, BA0_SRCSA, (chip->src_left_play_slot << 0) |
1641                                             (chip->src_right_play_slot << 8) |
1642                                             (chip->src_left_rec_slot << 16) |
1643                                             (chip->src_right_rec_slot << 24));
1644
1645         /* Initialize digital volume */
1646         snd_cs4281_pokeBA0(chip, BA0_PPLVC, 0);
1647         snd_cs4281_pokeBA0(chip, BA0_PPRVC, 0);
1648
1649         /* Enable IRQs */
1650         snd_cs4281_pokeBA0(chip, BA0_HICR, BA0_HICR_EOI);
1651         /* Unmask interrupts */
1652         snd_cs4281_pokeBA0(chip, BA0_HIMR, 0x7fffffff & ~(
1653                                         BA0_HISR_MIDI |
1654                                         BA0_HISR_DMAI |
1655                                         BA0_HISR_DMA(0) |
1656                                         BA0_HISR_DMA(1) |
1657                                         BA0_HISR_DMA(2) |
1658                                         BA0_HISR_DMA(3)));
1659         synchronize_irq(chip->irq);
1660
1661         return 0;
1662 }
1663
1664 /*
1665  *  MIDI section
1666  */
1667
1668 static void snd_cs4281_midi_reset(cs4281_t *chip)
1669 {
1670         snd_cs4281_pokeBA0(chip, BA0_MIDCR, chip->midcr | BA0_MIDCR_MRST);
1671         udelay(100);
1672         snd_cs4281_pokeBA0(chip, BA0_MIDCR, chip->midcr);
1673 }
1674
1675 static int snd_cs4281_midi_input_open(snd_rawmidi_substream_t * substream)
1676 {
1677         cs4281_t *chip = substream->rmidi->private_data;
1678
1679         spin_lock_irq(&chip->reg_lock);
1680         chip->midcr |= BA0_MIDCR_RXE;
1681         chip->midi_input = substream;
1682         if (!(chip->uartm & CS4281_MODE_OUTPUT)) {
1683                 snd_cs4281_midi_reset(chip);
1684         } else {
1685                 snd_cs4281_pokeBA0(chip, BA0_MIDCR, chip->midcr);
1686         }
1687         spin_unlock_irq(&chip->reg_lock);
1688         return 0;
1689 }
1690
1691 static int snd_cs4281_midi_input_close(snd_rawmidi_substream_t * substream)
1692 {
1693         cs4281_t *chip = substream->rmidi->private_data;
1694
1695         spin_lock_irq(&chip->reg_lock);
1696         chip->midcr &= ~(BA0_MIDCR_RXE | BA0_MIDCR_RIE);
1697         chip->midi_input = NULL;
1698         if (!(chip->uartm & CS4281_MODE_OUTPUT)) {
1699                 snd_cs4281_midi_reset(chip);
1700         } else {
1701                 snd_cs4281_pokeBA0(chip, BA0_MIDCR, chip->midcr);
1702         }
1703         chip->uartm &= ~CS4281_MODE_INPUT;
1704         spin_unlock_irq(&chip->reg_lock);
1705         return 0;
1706 }
1707
1708 static int snd_cs4281_midi_output_open(snd_rawmidi_substream_t * substream)
1709 {
1710         cs4281_t *chip = substream->rmidi->private_data;
1711
1712         spin_lock_irq(&chip->reg_lock);
1713         chip->uartm |= CS4281_MODE_OUTPUT;
1714         chip->midcr |= BA0_MIDCR_TXE;
1715         chip->midi_output = substream;
1716         if (!(chip->uartm & CS4281_MODE_INPUT)) {
1717                 snd_cs4281_midi_reset(chip);
1718         } else {
1719                 snd_cs4281_pokeBA0(chip, BA0_MIDCR, chip->midcr);
1720         }
1721         spin_unlock_irq(&chip->reg_lock);
1722         return 0;
1723 }
1724
1725 static int snd_cs4281_midi_output_close(snd_rawmidi_substream_t * substream)
1726 {
1727         cs4281_t *chip = substream->rmidi->private_data;
1728
1729         spin_lock_irq(&chip->reg_lock);
1730         chip->midcr &= ~(BA0_MIDCR_TXE | BA0_MIDCR_TIE);
1731         chip->midi_output = NULL;
1732         if (!(chip->uartm & CS4281_MODE_INPUT)) {
1733                 snd_cs4281_midi_reset(chip);
1734         } else {
1735                 snd_cs4281_pokeBA0(chip, BA0_MIDCR, chip->midcr);
1736         }
1737         chip->uartm &= ~CS4281_MODE_OUTPUT;
1738         spin_unlock_irq(&chip->reg_lock);
1739         return 0;
1740 }
1741
1742 static void snd_cs4281_midi_input_trigger(snd_rawmidi_substream_t * substream, int up)
1743 {
1744         unsigned long flags;
1745         cs4281_t *chip = substream->rmidi->private_data;
1746
1747         spin_lock_irqsave(&chip->reg_lock, flags);
1748         if (up) {
1749                 if ((chip->midcr & BA0_MIDCR_RIE) == 0) {
1750                         chip->midcr |= BA0_MIDCR_RIE;
1751                         snd_cs4281_pokeBA0(chip, BA0_MIDCR, chip->midcr);
1752                 }
1753         } else {
1754                 if (chip->midcr & BA0_MIDCR_RIE) {
1755                         chip->midcr &= ~BA0_MIDCR_RIE;
1756                         snd_cs4281_pokeBA0(chip, BA0_MIDCR, chip->midcr);
1757                 }
1758         }
1759         spin_unlock_irqrestore(&chip->reg_lock, flags);
1760 }
1761
1762 static void snd_cs4281_midi_output_trigger(snd_rawmidi_substream_t * substream, int up)
1763 {
1764         unsigned long flags;
1765         cs4281_t *chip = substream->rmidi->private_data;
1766         unsigned char byte;
1767
1768         spin_lock_irqsave(&chip->reg_lock, flags);
1769         if (up) {
1770                 if ((chip->midcr & BA0_MIDCR_TIE) == 0) {
1771                         chip->midcr |= BA0_MIDCR_TIE;
1772                         /* fill UART FIFO buffer at first, and turn Tx interrupts only if necessary */
1773                         while ((chip->midcr & BA0_MIDCR_TIE) &&
1774                                (snd_cs4281_peekBA0(chip, BA0_MIDSR) & BA0_MIDSR_TBF) == 0) {
1775                                 if (snd_rawmidi_transmit(substream, &byte, 1) != 1) {
1776                                         chip->midcr &= ~BA0_MIDCR_TIE;
1777                                 } else {
1778                                         snd_cs4281_pokeBA0(chip, BA0_MIDWP, byte);
1779                                 }
1780                         }
1781                         snd_cs4281_pokeBA0(chip, BA0_MIDCR, chip->midcr);
1782                 }
1783         } else {
1784                 if (chip->midcr & BA0_MIDCR_TIE) {
1785                         chip->midcr &= ~BA0_MIDCR_TIE;
1786                         snd_cs4281_pokeBA0(chip, BA0_MIDCR, chip->midcr);
1787                 }
1788         }
1789         spin_unlock_irqrestore(&chip->reg_lock, flags);
1790 }
1791
1792 static snd_rawmidi_ops_t snd_cs4281_midi_output =
1793 {
1794         .open =         snd_cs4281_midi_output_open,
1795         .close =        snd_cs4281_midi_output_close,
1796         .trigger =      snd_cs4281_midi_output_trigger,
1797 };
1798
1799 static snd_rawmidi_ops_t snd_cs4281_midi_input =
1800 {
1801         .open =         snd_cs4281_midi_input_open,
1802         .close =        snd_cs4281_midi_input_close,
1803         .trigger =      snd_cs4281_midi_input_trigger,
1804 };
1805
1806 static int __devinit snd_cs4281_midi(cs4281_t * chip, int device, snd_rawmidi_t **rrawmidi)
1807 {
1808         snd_rawmidi_t *rmidi;
1809         int err;
1810
1811         if (rrawmidi)
1812                 *rrawmidi = NULL;
1813         if ((err = snd_rawmidi_new(chip->card, "CS4281", device, 1, 1, &rmidi)) < 0)
1814                 return err;
1815         strcpy(rmidi->name, "CS4281");
1816         snd_rawmidi_set_ops(rmidi, SNDRV_RAWMIDI_STREAM_OUTPUT, &snd_cs4281_midi_output);
1817         snd_rawmidi_set_ops(rmidi, SNDRV_RAWMIDI_STREAM_INPUT, &snd_cs4281_midi_input);
1818         rmidi->info_flags |= SNDRV_RAWMIDI_INFO_OUTPUT | SNDRV_RAWMIDI_INFO_INPUT | SNDRV_RAWMIDI_INFO_DUPLEX;
1819         rmidi->private_data = chip;
1820         chip->rmidi = rmidi;
1821         if (rrawmidi)
1822                 *rrawmidi = rmidi;
1823         return 0;
1824 }
1825
1826 /*
1827  *  Interrupt handler
1828  */
1829
1830 static irqreturn_t snd_cs4281_interrupt(int irq, void *dev_id, struct pt_regs *regs)
1831 {
1832         cs4281_t *chip = dev_id;
1833         unsigned int status, dma, val;
1834         cs4281_dma_t *cdma;
1835
1836         if (chip == NULL)
1837                 return IRQ_NONE;
1838         status = snd_cs4281_peekBA0(chip, BA0_HISR);
1839         if ((status & 0x7fffffff) == 0) {
1840                 snd_cs4281_pokeBA0(chip, BA0_HICR, BA0_HICR_EOI);
1841                 return IRQ_NONE;
1842         }
1843
1844         if (status & (BA0_HISR_DMA(0)|BA0_HISR_DMA(1)|BA0_HISR_DMA(2)|BA0_HISR_DMA(3))) {
1845                 for (dma = 0; dma < 4; dma++)
1846                         if (status & BA0_HISR_DMA(dma)) {
1847                                 cdma = &chip->dma[dma];
1848                                 spin_lock(&chip->reg_lock);
1849                                 /* ack DMA IRQ */
1850                                 val = snd_cs4281_peekBA0(chip, cdma->regHDSR);
1851                                 /* workaround, sometimes CS4281 acknowledges */
1852                                 /* end or middle transfer position twice */
1853                                 cdma->frag++;
1854                                 if ((val & BA0_HDSR_DHTC) && !(cdma->frag & 1)) {
1855                                         cdma->frag--;
1856                                         chip->spurious_dhtc_irq++;
1857                                         spin_unlock(&chip->reg_lock);
1858                                         continue;
1859                                 }
1860                                 if ((val & BA0_HDSR_DTC) && (cdma->frag & 1)) {
1861                                         cdma->frag--;
1862                                         chip->spurious_dtc_irq++;
1863                                         spin_unlock(&chip->reg_lock);
1864                                         continue;
1865                                 }
1866                                 spin_unlock(&chip->reg_lock);
1867                                 snd_pcm_period_elapsed(cdma->substream);
1868                         }
1869         }
1870
1871         if ((status & BA0_HISR_MIDI) && chip->rmidi) {
1872                 unsigned char c;
1873                 
1874                 spin_lock(&chip->reg_lock);
1875                 while ((snd_cs4281_peekBA0(chip, BA0_MIDSR) & BA0_MIDSR_RBE) == 0) {
1876                         c = snd_cs4281_peekBA0(chip, BA0_MIDRP);
1877                         if ((chip->midcr & BA0_MIDCR_RIE) == 0)
1878                                 continue;
1879                         snd_rawmidi_receive(chip->midi_input, &c, 1);
1880                 }
1881                 while ((snd_cs4281_peekBA0(chip, BA0_MIDSR) & BA0_MIDSR_TBF) == 0) {
1882                         if ((chip->midcr & BA0_MIDCR_TIE) == 0)
1883                                 break;
1884                         if (snd_rawmidi_transmit(chip->midi_output, &c, 1) != 1) {
1885                                 chip->midcr &= ~BA0_MIDCR_TIE;
1886                                 snd_cs4281_pokeBA0(chip, BA0_MIDCR, chip->midcr);
1887                                 break;
1888                         }
1889                         snd_cs4281_pokeBA0(chip, BA0_MIDWP, c);
1890                 }
1891                 spin_unlock(&chip->reg_lock);
1892         }
1893
1894         /* EOI to the PCI part... reenables interrupts */
1895         snd_cs4281_pokeBA0(chip, BA0_HICR, BA0_HICR_EOI);
1896
1897         return IRQ_HANDLED;
1898 }
1899
1900
1901 /*
1902  * OPL3 command
1903  */
1904 static void snd_cs4281_opl3_command(opl3_t * opl3, unsigned short cmd, unsigned char val)
1905 {
1906         unsigned long flags;
1907         cs4281_t *chip = opl3->private_data;
1908         void __iomem *port;
1909
1910         if (cmd & OPL3_RIGHT)
1911                 port = chip->ba0 + BA0_B1AP; /* right port */
1912         else
1913                 port = chip->ba0 + BA0_B0AP; /* left port */
1914
1915         spin_lock_irqsave(&opl3->reg_lock, flags);
1916
1917         writel((unsigned int)cmd, port);
1918         udelay(10);
1919
1920         writel((unsigned int)val, port + 4);
1921         udelay(30);
1922
1923         spin_unlock_irqrestore(&opl3->reg_lock, flags);
1924 }
1925
1926 static int __devinit snd_cs4281_probe(struct pci_dev *pci,
1927                                       const struct pci_device_id *pci_id)
1928 {
1929         static int dev;
1930         snd_card_t *card;
1931         cs4281_t *chip;
1932         opl3_t *opl3;
1933         int err;
1934
1935         if (dev >= SNDRV_CARDS)
1936                 return -ENODEV;
1937         if (!enable[dev]) {
1938                 dev++;
1939                 return -ENOENT;
1940         }
1941
1942         card = snd_card_new(index[dev], id[dev], THIS_MODULE, 0);
1943         if (card == NULL)
1944                 return -ENOMEM;
1945
1946         if ((err = snd_cs4281_create(card, pci, &chip, dual_codec[dev])) < 0) {
1947                 snd_card_free(card);
1948                 return err;
1949         }
1950
1951         if ((err = snd_cs4281_mixer(chip)) < 0) {
1952                 snd_card_free(card);
1953                 return err;
1954         }
1955         if ((err = snd_cs4281_pcm(chip, 0, NULL)) < 0) {
1956                 snd_card_free(card);
1957                 return err;
1958         }
1959         if ((err = snd_cs4281_midi(chip, 0, NULL)) < 0) {
1960                 snd_card_free(card);
1961                 return err;
1962         }
1963         if ((err = snd_opl3_new(card, OPL3_HW_OPL3_CS4281, &opl3)) < 0) {
1964                 snd_card_free(card);
1965                 return err;
1966         }
1967         opl3->private_data = chip;
1968         opl3->command = snd_cs4281_opl3_command;
1969         snd_opl3_init(opl3);
1970         if ((err = snd_opl3_hwdep_new(opl3, 0, 1, NULL)) < 0) {
1971                 snd_card_free(card);
1972                 return err;
1973         }
1974         snd_cs4281_create_gameport(chip);
1975         strcpy(card->driver, "CS4281");
1976         strcpy(card->shortname, "Cirrus Logic CS4281");
1977         sprintf(card->longname, "%s at 0x%lx, irq %d",
1978                 card->shortname,
1979                 chip->ba0_addr,
1980                 chip->irq);
1981
1982         if ((err = snd_card_register(card)) < 0) {
1983                 snd_card_free(card);
1984                 return err;
1985         }
1986
1987         pci_set_drvdata(pci, card);
1988         dev++;
1989         return 0;
1990 }
1991
1992 static void __devexit snd_cs4281_remove(struct pci_dev *pci)
1993 {
1994         snd_card_free(pci_get_drvdata(pci));
1995         pci_set_drvdata(pci, NULL);
1996 }
1997
1998 /*
1999  * Power Management
2000  */
2001 #ifdef CONFIG_PM
2002
2003 static int saved_regs[SUSPEND_REGISTERS] = {
2004         BA0_JSCTL,
2005         BA0_GPIOR,
2006         BA0_SSCR,
2007         BA0_MIDCR,
2008         BA0_SRCSA,
2009         BA0_PASR,
2010         BA0_CASR,
2011         BA0_DACSR,
2012         BA0_ADCSR,
2013         BA0_FMLVC,
2014         BA0_FMRVC,
2015         BA0_PPLVC,
2016         BA0_PPRVC,
2017 };
2018
2019 #define CLKCR1_CKRA                             0x00010000L
2020
2021 static int cs4281_suspend(snd_card_t *card, pm_message_t state)
2022 {
2023         cs4281_t *chip = card->pm_private_data;
2024         u32 ulCLK;
2025         unsigned int i;
2026
2027         snd_pcm_suspend_all(chip->pcm);
2028
2029         if (chip->ac97)
2030                 snd_ac97_suspend(chip->ac97);
2031         if (chip->ac97_secondary)
2032                 snd_ac97_suspend(chip->ac97_secondary);
2033
2034         ulCLK = snd_cs4281_peekBA0(chip, BA0_CLKCR1);
2035         ulCLK |= CLKCR1_CKRA;
2036         snd_cs4281_pokeBA0(chip, BA0_CLKCR1, ulCLK);
2037
2038         /* Disable interrupts. */
2039         snd_cs4281_pokeBA0(chip, BA0_HICR, BA0_HICR_CHGM);
2040
2041         /* remember the status registers */
2042         for (i = 0; i < ARRAY_SIZE(saved_regs); i++)
2043                 if (saved_regs[i])
2044                         chip->suspend_regs[i] = snd_cs4281_peekBA0(chip, saved_regs[i]);
2045
2046         /* Turn off the serial ports. */
2047         snd_cs4281_pokeBA0(chip, BA0_SERMC, 0);
2048
2049         /* Power off FM, Joystick, AC link, */
2050         snd_cs4281_pokeBA0(chip, BA0_SSPM, 0);
2051
2052         /* DLL off. */
2053         snd_cs4281_pokeBA0(chip, BA0_CLKCR1, 0);
2054
2055         /* AC link off. */
2056         snd_cs4281_pokeBA0(chip, BA0_SPMC, 0);
2057
2058         ulCLK = snd_cs4281_peekBA0(chip, BA0_CLKCR1);
2059         ulCLK &= ~CLKCR1_CKRA;
2060         snd_cs4281_pokeBA0(chip, BA0_CLKCR1, ulCLK);
2061
2062         pci_disable_device(chip->pci);
2063         return 0;
2064 }
2065
2066 static int cs4281_resume(snd_card_t *card)
2067 {
2068         cs4281_t *chip = card->pm_private_data;
2069         unsigned int i;
2070         u32 ulCLK;
2071
2072         pci_enable_device(chip->pci);
2073         pci_set_master(chip->pci);
2074
2075         ulCLK = snd_cs4281_peekBA0(chip, BA0_CLKCR1);
2076         ulCLK |= CLKCR1_CKRA;
2077         snd_cs4281_pokeBA0(chip, BA0_CLKCR1, ulCLK);
2078
2079         snd_cs4281_chip_init(chip);
2080
2081         /* restore the status registers */
2082         for (i = 0; i < ARRAY_SIZE(saved_regs); i++)
2083                 if (saved_regs[i])
2084                         snd_cs4281_pokeBA0(chip, saved_regs[i], chip->suspend_regs[i]);
2085
2086         if (chip->ac97)
2087                 snd_ac97_resume(chip->ac97);
2088         if (chip->ac97_secondary)
2089                 snd_ac97_resume(chip->ac97_secondary);
2090
2091         ulCLK = snd_cs4281_peekBA0(chip, BA0_CLKCR1);
2092         ulCLK &= ~CLKCR1_CKRA;
2093         snd_cs4281_pokeBA0(chip, BA0_CLKCR1, ulCLK);
2094
2095         return 0;
2096 }
2097 #endif /* CONFIG_PM */
2098
2099 static struct pci_driver driver = {
2100         .name = "CS4281",
2101         .id_table = snd_cs4281_ids,
2102         .probe = snd_cs4281_probe,
2103         .remove = __devexit_p(snd_cs4281_remove),
2104         SND_PCI_PM_CALLBACKS
2105 };
2106         
2107 static int __init alsa_card_cs4281_init(void)
2108 {
2109         return pci_register_driver(&driver);
2110 }
2111
2112 static void __exit alsa_card_cs4281_exit(void)
2113 {
2114         pci_unregister_driver(&driver);
2115 }
2116
2117 module_init(alsa_card_cs4281_init)
2118 module_exit(alsa_card_cs4281_exit)