[ALSA] cmipci: show actual chip name in card longname
[linux-2.6.git] / sound / pci / cmipci.c
1 /*
2  * Driver for C-Media CMI8338 and 8738 PCI soundcards.
3  * Copyright (c) 2000 by Takashi Iwai <tiwai@suse.de>
4  *
5  *   This program is free software; you can redistribute it and/or modify
6  *   it under the terms of the GNU General Public License as published by
7  *   the Free Software Foundation; either version 2 of the License, or
8  *   (at your option) any later version.
9  *
10  *   This program is distributed in the hope that it will be useful,
11  *   but WITHOUT ANY WARRANTY; without even the implied warranty of
12  *   MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
13  *   GNU General Public License for more details.
14  *
15  *   You should have received a copy of the GNU General Public License
16  *   along with this program; if not, write to the Free Software
17  *   Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307 USA
18  */
19  
20 /* Does not work. Warning may block system in capture mode */
21 /* #define USE_VAR48KRATE */
22
23 #include <sound/driver.h>
24 #include <asm/io.h>
25 #include <linux/delay.h>
26 #include <linux/interrupt.h>
27 #include <linux/init.h>
28 #include <linux/pci.h>
29 #include <linux/slab.h>
30 #include <linux/gameport.h>
31 #include <linux/moduleparam.h>
32 #include <linux/mutex.h>
33 #include <sound/core.h>
34 #include <sound/info.h>
35 #include <sound/control.h>
36 #include <sound/pcm.h>
37 #include <sound/rawmidi.h>
38 #include <sound/mpu401.h>
39 #include <sound/opl3.h>
40 #include <sound/sb.h>
41 #include <sound/asoundef.h>
42 #include <sound/initval.h>
43
44 MODULE_AUTHOR("Takashi Iwai <tiwai@suse.de>");
45 MODULE_DESCRIPTION("C-Media CMI8x38 PCI");
46 MODULE_LICENSE("GPL");
47 MODULE_SUPPORTED_DEVICE("{{C-Media,CMI8738},"
48                 "{C-Media,CMI8738B},"
49                 "{C-Media,CMI8338A},"
50                 "{C-Media,CMI8338B}}");
51
52 #if defined(CONFIG_GAMEPORT) || (defined(MODULE) && defined(CONFIG_GAMEPORT_MODULE))
53 #define SUPPORT_JOYSTICK 1
54 #endif
55
56 static int index[SNDRV_CARDS] = SNDRV_DEFAULT_IDX;      /* Index 0-MAX */
57 static char *id[SNDRV_CARDS] = SNDRV_DEFAULT_STR;       /* ID for this card */
58 static int enable[SNDRV_CARDS] = SNDRV_DEFAULT_ENABLE_PNP;      /* Enable switches */
59 static long mpu_port[SNDRV_CARDS];
60 static long fm_port[SNDRV_CARDS] = {[0 ... (SNDRV_CARDS-1)]=1};
61 static int soft_ac3[SNDRV_CARDS] = {[0 ... (SNDRV_CARDS-1)]=1};
62 #ifdef SUPPORT_JOYSTICK
63 static int joystick_port[SNDRV_CARDS];
64 #endif
65
66 module_param_array(index, int, NULL, 0444);
67 MODULE_PARM_DESC(index, "Index value for C-Media PCI soundcard.");
68 module_param_array(id, charp, NULL, 0444);
69 MODULE_PARM_DESC(id, "ID string for C-Media PCI soundcard.");
70 module_param_array(enable, bool, NULL, 0444);
71 MODULE_PARM_DESC(enable, "Enable C-Media PCI soundcard.");
72 module_param_array(mpu_port, long, NULL, 0444);
73 MODULE_PARM_DESC(mpu_port, "MPU-401 port.");
74 module_param_array(fm_port, long, NULL, 0444);
75 MODULE_PARM_DESC(fm_port, "FM port.");
76 module_param_array(soft_ac3, bool, NULL, 0444);
77 MODULE_PARM_DESC(soft_ac3, "Sofware-conversion of raw SPDIF packets (model 033 only).");
78 #ifdef SUPPORT_JOYSTICK
79 module_param_array(joystick_port, int, NULL, 0444);
80 MODULE_PARM_DESC(joystick_port, "Joystick port address.");
81 #endif
82
83 /*
84  * CM8x38 registers definition
85  */
86
87 #define CM_REG_FUNCTRL0         0x00
88 #define CM_RST_CH1              0x00080000
89 #define CM_RST_CH0              0x00040000
90 #define CM_CHEN1                0x00020000      /* ch1: enable */
91 #define CM_CHEN0                0x00010000      /* ch0: enable */
92 #define CM_PAUSE1               0x00000008      /* ch1: pause */
93 #define CM_PAUSE0               0x00000004      /* ch0: pause */
94 #define CM_CHADC1               0x00000002      /* ch1, 0:playback, 1:record */
95 #define CM_CHADC0               0x00000001      /* ch0, 0:playback, 1:record */
96
97 #define CM_REG_FUNCTRL1         0x04
98 #define CM_ASFC_MASK            0x0000E000      /* ADC sampling frequency */
99 #define CM_ASFC_SHIFT           13
100 #define CM_DSFC_MASK            0x00001C00      /* DAC sampling frequency */
101 #define CM_DSFC_SHIFT           10
102 #define CM_SPDF_1               0x00000200      /* SPDIF IN/OUT at channel B */
103 #define CM_SPDF_0               0x00000100      /* SPDIF OUT only channel A */
104 #define CM_SPDFLOOP             0x00000080      /* ext. SPDIIF/OUT -> IN loopback */
105 #define CM_SPDO2DAC             0x00000040      /* SPDIF/OUT can be heard from internal DAC */
106 #define CM_INTRM                0x00000020      /* master control block (MCB) interrupt enabled */
107 #define CM_BREQ                 0x00000010      /* bus master enabled */
108 #define CM_VOICE_EN             0x00000008      /* legacy voice (SB16,FM) */
109 #define CM_UART_EN              0x00000004      /* UART */
110 #define CM_JYSTK_EN             0x00000002      /* joy stick */
111
112 #define CM_REG_CHFORMAT         0x08
113
114 #define CM_CHB3D5C              0x80000000      /* 5,6 channels */
115 #define CM_CHB3D                0x20000000      /* 4 channels */
116
117 #define CM_CHIP_MASK1           0x1f000000
118 #define CM_CHIP_037             0x01000000
119
120 #define CM_SPDIF_SELECT1        0x00080000      /* for model <= 037 ? */
121 #define CM_AC3EN1               0x00100000      /* enable AC3: model 037 */
122 #define CM_SPD24SEL             0x00020000      /* 24bit spdif: model 037 */
123 /* #define CM_SPDIF_INVERSE     0x00010000 */ /* ??? */
124
125 #define CM_ADCBITLEN_MASK       0x0000C000      
126 #define CM_ADCBITLEN_16         0x00000000
127 #define CM_ADCBITLEN_15         0x00004000
128 #define CM_ADCBITLEN_14         0x00008000
129 #define CM_ADCBITLEN_13         0x0000C000
130
131 #define CM_ADCDACLEN_MASK       0x00003000
132 #define CM_ADCDACLEN_060        0x00000000
133 #define CM_ADCDACLEN_066        0x00001000
134 #define CM_ADCDACLEN_130        0x00002000
135 #define CM_ADCDACLEN_280        0x00003000
136
137 #define CM_CH1_SRATE_176K       0x00000800
138 #define CM_CH1_SRATE_88K        0x00000400
139 #define CM_CH0_SRATE_176K       0x00000200
140 #define CM_CH0_SRATE_88K        0x00000100
141
142 #define CM_SPDIF_INVERSE2       0x00000080      /* model 055? */
143
144 #define CM_CH1FMT_MASK          0x0000000C
145 #define CM_CH1FMT_SHIFT         2
146 #define CM_CH0FMT_MASK          0x00000003
147 #define CM_CH0FMT_SHIFT         0
148
149 #define CM_REG_INT_HLDCLR       0x0C
150 #define CM_CHIP_MASK2           0xff000000
151 #define CM_CHIP_039             0x04000000
152 #define CM_CHIP_039_6CH         0x01000000
153 #define CM_CHIP_055             0x08000000
154 #define CM_CHIP_8768            0x20000000
155 #define CM_TDMA_INT_EN          0x00040000
156 #define CM_CH1_INT_EN           0x00020000
157 #define CM_CH0_INT_EN           0x00010000
158 #define CM_INT_HOLD             0x00000002
159 #define CM_INT_CLEAR            0x00000001
160
161 #define CM_REG_INT_STATUS       0x10
162 #define CM_INTR                 0x80000000
163 #define CM_VCO                  0x08000000      /* Voice Control? CMI8738 */
164 #define CM_MCBINT               0x04000000      /* Master Control Block abort cond.? */
165 #define CM_UARTINT              0x00010000
166 #define CM_LTDMAINT             0x00008000
167 #define CM_HTDMAINT             0x00004000
168 #define CM_XDO46                0x00000080      /* Modell 033? Direct programming EEPROM (read data register) */
169 #define CM_LHBTOG               0x00000040      /* High/Low status from DMA ctrl register */
170 #define CM_LEG_HDMA             0x00000020      /* Legacy is in High DMA channel */
171 #define CM_LEG_STEREO           0x00000010      /* Legacy is in Stereo mode */
172 #define CM_CH1BUSY              0x00000008
173 #define CM_CH0BUSY              0x00000004
174 #define CM_CHINT1               0x00000002
175 #define CM_CHINT0               0x00000001
176
177 #define CM_REG_LEGACY_CTRL      0x14
178 #define CM_NXCHG                0x80000000      /* h/w multi channels? */
179 #define CM_VMPU_MASK            0x60000000      /* MPU401 i/o port address */
180 #define CM_VMPU_330             0x00000000
181 #define CM_VMPU_320             0x20000000
182 #define CM_VMPU_310             0x40000000
183 #define CM_VMPU_300             0x60000000
184 #define CM_VSBSEL_MASK          0x0C000000      /* SB16 base address */
185 #define CM_VSBSEL_220           0x00000000
186 #define CM_VSBSEL_240           0x04000000
187 #define CM_VSBSEL_260           0x08000000
188 #define CM_VSBSEL_280           0x0C000000
189 #define CM_FMSEL_MASK           0x03000000      /* FM OPL3 base address */
190 #define CM_FMSEL_388            0x00000000
191 #define CM_FMSEL_3C8            0x01000000
192 #define CM_FMSEL_3E0            0x02000000
193 #define CM_FMSEL_3E8            0x03000000
194 #define CM_ENSPDOUT             0x00800000      /* enable XPDIF/OUT to I/O interface */
195 #define CM_SPDCOPYRHT           0x00400000      /* set copyright spdif in/out */
196 #define CM_DAC2SPDO             0x00200000      /* enable wave+fm_midi -> SPDIF/OUT */
197 #define CM_SETRETRY             0x00010000      /* 0: legacy i/o wait (default), 1: legacy i/o bus retry */
198 #define CM_CHB3D6C              0x00008000      /* 5.1 channels support */
199 #define CM_LINE_AS_BASS         0x00006000      /* use line-in as bass */
200
201 #define CM_REG_MISC_CTRL        0x18
202 #define CM_PWD                  0x80000000
203 #define CM_RESET                0x40000000
204 #define CM_SFIL_MASK            0x30000000
205 #define CM_TXVX                 0x08000000
206 #define CM_N4SPK3D              0x04000000      /* 4ch output */
207 #define CM_SPDO5V               0x02000000      /* 5V spdif output (1 = 0.5v (coax)) */
208 #define CM_SPDIF48K             0x01000000      /* write */
209 #define CM_SPATUS48K            0x01000000      /* read */
210 #define CM_ENDBDAC              0x00800000      /* enable dual dac */
211 #define CM_XCHGDAC              0x00400000      /* 0: front=ch0, 1: front=ch1 */
212 #define CM_SPD32SEL             0x00200000      /* 0: 16bit SPDIF, 1: 32bit */
213 #define CM_SPDFLOOPI            0x00100000      /* int. SPDIF-IN -> int. OUT */
214 #define CM_FM_EN                0x00080000      /* enalbe FM */
215 #define CM_AC3EN2               0x00040000      /* enable AC3: model 039 */
216 #define CM_VIDWPDSB             0x00010000 
217 #define CM_SPDF_AC97            0x00008000      /* 0: SPDIF/OUT 44.1K, 1: 48K */
218 #define CM_MASK_EN              0x00004000
219 #define CM_VIDWPPRT             0x00002000
220 #define CM_SFILENB              0x00001000
221 #define CM_MMODE_MASK           0x00000E00
222 #define CM_SPDIF_SELECT2        0x00000100      /* for model > 039 ? */
223 #define CM_ENCENTER             0x00000080
224 #define CM_FLINKON              0x00000040
225 #define CM_FLINKOFF             0x00000020
226 #define CM_MIDSMP               0x00000010
227 #define CM_UPDDMA_MASK          0x0000000C
228 #define CM_TWAIT_MASK           0x00000003
229
230         /* byte */
231 #define CM_REG_MIXER0           0x20
232
233 #define CM_REG_SB16_DATA        0x22
234 #define CM_REG_SB16_ADDR        0x23
235
236 #define CM_REFFREQ_XIN          (315*1000*1000)/22      /* 14.31818 Mhz reference clock frequency pin XIN */
237 #define CM_ADCMULT_XIN          512                     /* Guessed (487 best for 44.1kHz, not for 88/176kHz) */
238 #define CM_TOLERANCE_RATE       0.001                   /* Tolerance sample rate pitch (1000ppm) */
239 #define CM_MAXIMUM_RATE         80000000                /* Note more than 80MHz */
240
241 #define CM_REG_MIXER1           0x24
242 #define CM_FMMUTE               0x80    /* mute FM */
243 #define CM_FMMUTE_SHIFT         7
244 #define CM_WSMUTE               0x40    /* mute PCM */
245 #define CM_WSMUTE_SHIFT         6
246 #define CM_SPK4                 0x20    /* lin-in -> rear line out */
247 #define CM_SPK4_SHIFT           5
248 #define CM_REAR2FRONT           0x10    /* exchange rear/front */
249 #define CM_REAR2FRONT_SHIFT     4
250 #define CM_WAVEINL              0x08    /* digital wave rec. left chan */
251 #define CM_WAVEINL_SHIFT        3
252 #define CM_WAVEINR              0x04    /* digical wave rec. right */
253 #define CM_WAVEINR_SHIFT        2
254 #define CM_X3DEN                0x02    /* 3D surround enable */
255 #define CM_X3DEN_SHIFT          1
256 #define CM_CDPLAY               0x01    /* enable SPDIF/IN PCM -> DAC */
257 #define CM_CDPLAY_SHIFT         0
258
259 #define CM_REG_MIXER2           0x25
260 #define CM_RAUXREN              0x80    /* AUX right capture */
261 #define CM_RAUXREN_SHIFT        7
262 #define CM_RAUXLEN              0x40    /* AUX left capture */
263 #define CM_RAUXLEN_SHIFT        6
264 #define CM_VAUXRM               0x20    /* AUX right mute */
265 #define CM_VAUXRM_SHIFT         5
266 #define CM_VAUXLM               0x10    /* AUX left mute */
267 #define CM_VAUXLM_SHIFT         4
268 #define CM_VADMIC_MASK          0x0e    /* mic gain level (0-3) << 1 */
269 #define CM_VADMIC_SHIFT         1
270 #define CM_MICGAINZ             0x01    /* mic boost */
271 #define CM_MICGAINZ_SHIFT       0
272
273 #define CM_REG_MIXER3           0x24
274 #define CM_REG_AUX_VOL          0x26
275 #define CM_VAUXL_MASK           0xf0
276 #define CM_VAUXR_MASK           0x0f
277
278 #define CM_REG_MISC             0x27
279 #define CM_XGPO1                0x20
280 // #define CM_XGPBIO            0x04
281 #define CM_MIC_CENTER_LFE       0x04    /* mic as center/lfe out? (model 039 or later?) */
282 #define CM_SPDIF_INVERSE        0x04    /* spdif input phase inverse (model 037) */
283 #define CM_SPDVALID             0x02    /* spdif input valid check */
284 #define CM_DMAUTO               0x01
285
286 #define CM_REG_AC97             0x28    /* hmmm.. do we have ac97 link? */
287 /*
288  * For CMI-8338 (0x28 - 0x2b) .. is this valid for CMI-8738
289  * or identical with AC97 codec?
290  */
291 #define CM_REG_EXTERN_CODEC     CM_REG_AC97
292
293 /*
294  * MPU401 pci port index address 0x40 - 0x4f (CMI-8738 spec ver. 0.6)
295  */
296 #define CM_REG_MPU_PCI          0x40
297
298 /*
299  * FM pci port index address 0x50 - 0x5f (CMI-8738 spec ver. 0.6)
300  */
301 #define CM_REG_FM_PCI           0x50
302
303 /*
304  * access from SB-mixer port
305  */
306 #define CM_REG_EXTENT_IND       0xf0
307 #define CM_VPHONE_MASK          0xe0    /* Phone volume control (0-3) << 5 */
308 #define CM_VPHONE_SHIFT         5
309 #define CM_VPHOM                0x10    /* Phone mute control */
310 #define CM_VSPKM                0x08    /* Speaker mute control, default high */
311 #define CM_RLOOPREN             0x04    /* Rec. R-channel enable */
312 #define CM_RLOOPLEN             0x02    /* Rec. L-channel enable */
313 #define CM_VADMIC3              0x01    /* Mic record boost */
314
315 /*
316  * CMI-8338 spec ver 0.5 (this is not valid for CMI-8738):
317  * the 8 registers 0xf8 - 0xff are used for programming m/n counter by the PLL
318  * unit (readonly?).
319  */
320 #define CM_REG_PLL              0xf8
321
322 /*
323  * extended registers
324  */
325 #define CM_REG_CH0_FRAME1       0x80    /* base address */
326 #define CM_REG_CH0_FRAME2       0x84
327 #define CM_REG_CH1_FRAME1       0x88    /* 0-15: count of samples at bus master; buffer size */
328 #define CM_REG_CH1_FRAME2       0x8C    /* 16-31: count of samples at codec; fragment size */
329 #define CM_REG_EXT_MISC         0x90
330 #define CM_REG_MISC_CTRL_8768   0x92    /* reg. name the same as 0x18 */
331 #define CM_CHB3D8C              0x20    /* 7.1 channels support */
332 #define CM_SPD32FMT             0x10    /* SPDIF/IN 32k */
333 #define CM_ADC2SPDIF            0x08    /* ADC output to SPDIF/OUT */
334 #define CM_SHAREADC             0x04    /* DAC in ADC as Center/LFE */
335 #define CM_REALTCMP             0x02    /* monitor the CMPL/CMPR of ADC */
336 #define CM_INVLRCK              0x01    /* invert ZVPORT's LRCK */
337
338 /*
339  * size of i/o region
340  */
341 #define CM_EXTENT_CODEC   0x100
342 #define CM_EXTENT_MIDI    0x2
343 #define CM_EXTENT_SYNTH   0x4
344
345
346 /*
347  * channels for playback / capture
348  */
349 #define CM_CH_PLAY      0
350 #define CM_CH_CAPT      1
351
352 /*
353  * flags to check device open/close
354  */
355 #define CM_OPEN_NONE    0
356 #define CM_OPEN_CH_MASK 0x01
357 #define CM_OPEN_DAC     0x10
358 #define CM_OPEN_ADC     0x20
359 #define CM_OPEN_SPDIF   0x40
360 #define CM_OPEN_MCHAN   0x80
361 #define CM_OPEN_PLAYBACK        (CM_CH_PLAY | CM_OPEN_DAC)
362 #define CM_OPEN_PLAYBACK2       (CM_CH_CAPT | CM_OPEN_DAC)
363 #define CM_OPEN_PLAYBACK_MULTI  (CM_CH_PLAY | CM_OPEN_DAC | CM_OPEN_MCHAN)
364 #define CM_OPEN_CAPTURE         (CM_CH_CAPT | CM_OPEN_ADC)
365 #define CM_OPEN_SPDIF_PLAYBACK  (CM_CH_PLAY | CM_OPEN_DAC | CM_OPEN_SPDIF)
366 #define CM_OPEN_SPDIF_CAPTURE   (CM_CH_CAPT | CM_OPEN_ADC | CM_OPEN_SPDIF)
367
368
369 #if CM_CH_PLAY == 1
370 #define CM_PLAYBACK_SRATE_176K  CM_CH1_SRATE_176K
371 #define CM_PLAYBACK_SPDF        CM_SPDF_1
372 #define CM_CAPTURE_SPDF         CM_SPDF_0
373 #else
374 #define CM_PLAYBACK_SRATE_176K CM_CH0_SRATE_176K
375 #define CM_PLAYBACK_SPDF        CM_SPDF_0
376 #define CM_CAPTURE_SPDF         CM_SPDF_1
377 #endif
378
379
380 /*
381  * driver data
382  */
383
384 struct cmipci_pcm {
385         struct snd_pcm_substream *substream;
386         int running;            /* dac/adc running? */
387         unsigned int dma_size;  /* in frames */
388         unsigned int period_size;       /* in frames */
389         unsigned int offset;    /* physical address of the buffer */
390         unsigned int fmt;       /* format bits */
391         int ch;                 /* channel (0/1) */
392         unsigned int is_dac;            /* is dac? */
393         int bytes_per_frame;
394         int shift;
395 };
396
397 /* mixer elements toggled/resumed during ac3 playback */
398 struct cmipci_mixer_auto_switches {
399         const char *name;       /* switch to toggle */
400         int toggle_on;          /* value to change when ac3 mode */
401 };
402 static const struct cmipci_mixer_auto_switches cm_saved_mixer[] = {
403         {"PCM Playback Switch", 0},
404         {"IEC958 Output Switch", 1},
405         {"IEC958 Mix Analog", 0},
406         // {"IEC958 Out To DAC", 1}, // no longer used
407         {"IEC958 Loop", 0},
408 };
409 #define CM_SAVED_MIXERS         ARRAY_SIZE(cm_saved_mixer)
410
411 struct cmipci {
412         struct snd_card *card;
413
414         struct pci_dev *pci;
415         unsigned int device;    /* device ID */
416         int irq;
417
418         unsigned long iobase;
419         unsigned int ctrl;      /* FUNCTRL0 current value */
420
421         struct snd_pcm *pcm;            /* DAC/ADC PCM */
422         struct snd_pcm *pcm2;   /* 2nd DAC */
423         struct snd_pcm *pcm_spdif;      /* SPDIF */
424
425         int chip_version;
426         int max_channels;
427         unsigned int can_ac3_sw: 1;
428         unsigned int can_ac3_hw: 1;
429         unsigned int can_multi_ch: 1;
430         unsigned int do_soft_ac3: 1;
431
432         unsigned int spdif_playback_avail: 1;   /* spdif ready? */
433         unsigned int spdif_playback_enabled: 1; /* spdif switch enabled? */
434         int spdif_counter;      /* for software AC3 */
435
436         unsigned int dig_status;
437         unsigned int dig_pcm_status;
438
439         struct snd_pcm_hardware *hw_info[3]; /* for playbacks */
440
441         int opened[2];  /* open mode */
442         struct mutex open_mutex;
443
444         unsigned int mixer_insensitive: 1;
445         struct snd_kcontrol *mixer_res_ctl[CM_SAVED_MIXERS];
446         int mixer_res_status[CM_SAVED_MIXERS];
447
448         struct cmipci_pcm channel[2];   /* ch0 - DAC, ch1 - ADC or 2nd DAC */
449
450         /* external MIDI */
451         struct snd_rawmidi *rmidi;
452
453 #ifdef SUPPORT_JOYSTICK
454         struct gameport *gameport;
455 #endif
456
457         spinlock_t reg_lock;
458
459 #ifdef CONFIG_PM
460         unsigned int saved_regs[0x20];
461         unsigned char saved_mixers[0x20];
462 #endif
463 };
464
465
466 /* read/write operations for dword register */
467 static inline void snd_cmipci_write(struct cmipci *cm, unsigned int cmd, unsigned int data)
468 {
469         outl(data, cm->iobase + cmd);
470 }
471
472 static inline unsigned int snd_cmipci_read(struct cmipci *cm, unsigned int cmd)
473 {
474         return inl(cm->iobase + cmd);
475 }
476
477 /* read/write operations for word register */
478 static inline void snd_cmipci_write_w(struct cmipci *cm, unsigned int cmd, unsigned short data)
479 {
480         outw(data, cm->iobase + cmd);
481 }
482
483 static inline unsigned short snd_cmipci_read_w(struct cmipci *cm, unsigned int cmd)
484 {
485         return inw(cm->iobase + cmd);
486 }
487
488 /* read/write operations for byte register */
489 static inline void snd_cmipci_write_b(struct cmipci *cm, unsigned int cmd, unsigned char data)
490 {
491         outb(data, cm->iobase + cmd);
492 }
493
494 static inline unsigned char snd_cmipci_read_b(struct cmipci *cm, unsigned int cmd)
495 {
496         return inb(cm->iobase + cmd);
497 }
498
499 /* bit operations for dword register */
500 static int snd_cmipci_set_bit(struct cmipci *cm, unsigned int cmd, unsigned int flag)
501 {
502         unsigned int val, oval;
503         val = oval = inl(cm->iobase + cmd);
504         val |= flag;
505         if (val == oval)
506                 return 0;
507         outl(val, cm->iobase + cmd);
508         return 1;
509 }
510
511 static int snd_cmipci_clear_bit(struct cmipci *cm, unsigned int cmd, unsigned int flag)
512 {
513         unsigned int val, oval;
514         val = oval = inl(cm->iobase + cmd);
515         val &= ~flag;
516         if (val == oval)
517                 return 0;
518         outl(val, cm->iobase + cmd);
519         return 1;
520 }
521
522 /* bit operations for byte register */
523 static int snd_cmipci_set_bit_b(struct cmipci *cm, unsigned int cmd, unsigned char flag)
524 {
525         unsigned char val, oval;
526         val = oval = inb(cm->iobase + cmd);
527         val |= flag;
528         if (val == oval)
529                 return 0;
530         outb(val, cm->iobase + cmd);
531         return 1;
532 }
533
534 static int snd_cmipci_clear_bit_b(struct cmipci *cm, unsigned int cmd, unsigned char flag)
535 {
536         unsigned char val, oval;
537         val = oval = inb(cm->iobase + cmd);
538         val &= ~flag;
539         if (val == oval)
540                 return 0;
541         outb(val, cm->iobase + cmd);
542         return 1;
543 }
544
545
546 /*
547  * PCM interface
548  */
549
550 /*
551  * calculate frequency
552  */
553
554 static unsigned int rates[] = { 5512, 11025, 22050, 44100, 8000, 16000, 32000, 48000 };
555
556 static unsigned int snd_cmipci_rate_freq(unsigned int rate)
557 {
558         unsigned int i;
559         for (i = 0; i < ARRAY_SIZE(rates); i++) {
560                 if (rates[i] == rate)
561                         return i;
562         }
563         snd_BUG();
564         return 0;
565 }
566
567 #ifdef USE_VAR48KRATE
568 /*
569  * Determine PLL values for frequency setup, maybe the CMI8338 (CMI8738???)
570  * does it this way .. maybe not.  Never get any information from C-Media about
571  * that <werner@suse.de>.
572  */
573 static int snd_cmipci_pll_rmn(unsigned int rate, unsigned int adcmult, int *r, int *m, int *n)
574 {
575         unsigned int delta, tolerance;
576         int xm, xn, xr;
577
578         for (*r = 0; rate < CM_MAXIMUM_RATE/adcmult; *r += (1<<5))
579                 rate <<= 1;
580         *n = -1;
581         if (*r > 0xff)
582                 goto out;
583         tolerance = rate*CM_TOLERANCE_RATE;
584
585         for (xn = (1+2); xn < (0x1f+2); xn++) {
586                 for (xm = (1+2); xm < (0xff+2); xm++) {
587                         xr = ((CM_REFFREQ_XIN/adcmult) * xm) / xn;
588
589                         if (xr < rate)
590                                 delta = rate - xr;
591                         else
592                                 delta = xr - rate;
593
594                         /*
595                          * If we found one, remember this,
596                          * and try to find a closer one
597                          */
598                         if (delta < tolerance) {
599                                 tolerance = delta;
600                                 *m = xm - 2;
601                                 *n = xn - 2;
602                         }
603                 }
604         }
605 out:
606         return (*n > -1);
607 }
608
609 /*
610  * Program pll register bits, I assume that the 8 registers 0xf8 upto 0xff
611  * are mapped onto the 8 ADC/DAC sampling frequency which can be choosen
612  * at the register CM_REG_FUNCTRL1 (0x04).
613  * Problem: other ways are also possible (any information about that?)
614  */
615 static void snd_cmipci_set_pll(struct cmipci *cm, unsigned int rate, unsigned int slot)
616 {
617         unsigned int reg = CM_REG_PLL + slot;
618         /*
619          * Guess that this programs at reg. 0x04 the pos 15:13/12:10
620          * for DSFC/ASFC (000 upto 111).
621          */
622
623         /* FIXME: Init (Do we've to set an other register first before programming?) */
624
625         /* FIXME: Is this correct? Or shouldn't the m/n/r values be used for that? */
626         snd_cmipci_write_b(cm, reg, rate>>8);
627         snd_cmipci_write_b(cm, reg, rate&0xff);
628
629         /* FIXME: Setup (Do we've to set an other register first to enable this?) */
630 }
631 #endif /* USE_VAR48KRATE */
632
633 static int snd_cmipci_hw_params(struct snd_pcm_substream *substream,
634                                 struct snd_pcm_hw_params *hw_params)
635 {
636         return snd_pcm_lib_malloc_pages(substream, params_buffer_bytes(hw_params));
637 }
638
639 static int snd_cmipci_playback2_hw_params(struct snd_pcm_substream *substream,
640                                           struct snd_pcm_hw_params *hw_params)
641 {
642         struct cmipci *cm = snd_pcm_substream_chip(substream);
643         if (params_channels(hw_params) > 2) {
644                 mutex_lock(&cm->open_mutex);
645                 if (cm->opened[CM_CH_PLAY]) {
646                         mutex_unlock(&cm->open_mutex);
647                         return -EBUSY;
648                 }
649                 /* reserve the channel A */
650                 cm->opened[CM_CH_PLAY] = CM_OPEN_PLAYBACK_MULTI;
651                 mutex_unlock(&cm->open_mutex);
652         }
653         return snd_pcm_lib_malloc_pages(substream, params_buffer_bytes(hw_params));
654 }
655
656 static void snd_cmipci_ch_reset(struct cmipci *cm, int ch)
657 {
658         int reset = CM_RST_CH0 << (cm->channel[ch].ch);
659         snd_cmipci_write(cm, CM_REG_FUNCTRL0, cm->ctrl | reset);
660         snd_cmipci_write(cm, CM_REG_FUNCTRL0, cm->ctrl & ~reset);
661         udelay(10);
662 }
663
664 static int snd_cmipci_hw_free(struct snd_pcm_substream *substream)
665 {
666         return snd_pcm_lib_free_pages(substream);
667 }
668
669
670 /*
671  */
672
673 static unsigned int hw_channels[] = {1, 2, 4, 5, 6, 8};
674 static struct snd_pcm_hw_constraint_list hw_constraints_channels_4 = {
675         .count = 3,
676         .list = hw_channels,
677         .mask = 0,
678 };
679 static struct snd_pcm_hw_constraint_list hw_constraints_channels_6 = {
680         .count = 5,
681         .list = hw_channels,
682         .mask = 0,
683 };
684 static struct snd_pcm_hw_constraint_list hw_constraints_channels_8 = {
685         .count = 6,
686         .list = hw_channels,
687         .mask = 0,
688 };
689
690 static int set_dac_channels(struct cmipci *cm, struct cmipci_pcm *rec, int channels)
691 {
692         if (channels > 2) {
693                 if (! cm->can_multi_ch)
694                         return -EINVAL;
695                 if (rec->fmt != 0x03) /* stereo 16bit only */
696                         return -EINVAL;
697
698                 spin_lock_irq(&cm->reg_lock);
699                 snd_cmipci_set_bit(cm, CM_REG_LEGACY_CTRL, CM_NXCHG);
700                 snd_cmipci_set_bit(cm, CM_REG_MISC_CTRL, CM_XCHGDAC);
701                 if (channels > 4) {
702                         snd_cmipci_clear_bit(cm, CM_REG_CHFORMAT, CM_CHB3D);
703                         snd_cmipci_set_bit(cm, CM_REG_CHFORMAT, CM_CHB3D5C);
704                 } else {
705                         snd_cmipci_clear_bit(cm, CM_REG_CHFORMAT, CM_CHB3D5C);
706                         snd_cmipci_set_bit(cm, CM_REG_CHFORMAT, CM_CHB3D);
707                 }
708                 if (channels >= 6) {
709                         snd_cmipci_set_bit(cm, CM_REG_LEGACY_CTRL, CM_CHB3D6C);
710                         snd_cmipci_set_bit(cm, CM_REG_MISC_CTRL, CM_ENCENTER);
711                 } else {
712                         snd_cmipci_clear_bit(cm, CM_REG_LEGACY_CTRL, CM_CHB3D6C);
713                         snd_cmipci_clear_bit(cm, CM_REG_MISC_CTRL, CM_ENCENTER);
714                 }
715                 if (cm->chip_version == 68) {
716                         if (channels == 8) {
717                                 snd_cmipci_set_bit(cm, CM_REG_MISC_CTRL_8768, CM_CHB3D8C);
718                         } else {
719                                 snd_cmipci_clear_bit(cm, CM_REG_MISC_CTRL_8768, CM_CHB3D8C);
720                         }
721                 }
722                 spin_unlock_irq(&cm->reg_lock);
723
724         } else {
725                 if (cm->can_multi_ch) {
726                         spin_lock_irq(&cm->reg_lock);
727                         snd_cmipci_clear_bit(cm, CM_REG_LEGACY_CTRL, CM_NXCHG);
728                         snd_cmipci_clear_bit(cm, CM_REG_CHFORMAT, CM_CHB3D);
729                         snd_cmipci_clear_bit(cm, CM_REG_CHFORMAT, CM_CHB3D5C);
730                         snd_cmipci_clear_bit(cm, CM_REG_LEGACY_CTRL, CM_CHB3D6C);
731                         snd_cmipci_clear_bit(cm, CM_REG_MISC_CTRL, CM_ENCENTER);
732                         snd_cmipci_clear_bit(cm, CM_REG_MISC_CTRL, CM_XCHGDAC);
733                         spin_unlock_irq(&cm->reg_lock);
734                 }
735         }
736         return 0;
737 }
738
739
740 /*
741  * prepare playback/capture channel
742  * channel to be used must have been set in rec->ch.
743  */
744 static int snd_cmipci_pcm_prepare(struct cmipci *cm, struct cmipci_pcm *rec,
745                                  struct snd_pcm_substream *substream)
746 {
747         unsigned int reg, freq, val;
748         struct snd_pcm_runtime *runtime = substream->runtime;
749
750         rec->fmt = 0;
751         rec->shift = 0;
752         if (snd_pcm_format_width(runtime->format) >= 16) {
753                 rec->fmt |= 0x02;
754                 if (snd_pcm_format_width(runtime->format) > 16)
755                         rec->shift++; /* 24/32bit */
756         }
757         if (runtime->channels > 1)
758                 rec->fmt |= 0x01;
759         if (rec->is_dac && set_dac_channels(cm, rec, runtime->channels) < 0) {
760                 snd_printd("cannot set dac channels\n");
761                 return -EINVAL;
762         }
763
764         rec->offset = runtime->dma_addr;
765         /* buffer and period sizes in frame */
766         rec->dma_size = runtime->buffer_size << rec->shift;
767         rec->period_size = runtime->period_size << rec->shift;
768         if (runtime->channels > 2) {
769                 /* multi-channels */
770                 rec->dma_size = (rec->dma_size * runtime->channels) / 2;
771                 rec->period_size = (rec->period_size * runtime->channels) / 2;
772         }
773
774         spin_lock_irq(&cm->reg_lock);
775
776         /* set buffer address */
777         reg = rec->ch ? CM_REG_CH1_FRAME1 : CM_REG_CH0_FRAME1;
778         snd_cmipci_write(cm, reg, rec->offset);
779         /* program sample counts */
780         reg = rec->ch ? CM_REG_CH1_FRAME2 : CM_REG_CH0_FRAME2;
781         snd_cmipci_write_w(cm, reg, rec->dma_size - 1);
782         snd_cmipci_write_w(cm, reg + 2, rec->period_size - 1);
783
784         /* set adc/dac flag */
785         val = rec->ch ? CM_CHADC1 : CM_CHADC0;
786         if (rec->is_dac)
787                 cm->ctrl &= ~val;
788         else
789                 cm->ctrl |= val;
790         snd_cmipci_write(cm, CM_REG_FUNCTRL0, cm->ctrl);
791         //snd_printd("cmipci: functrl0 = %08x\n", cm->ctrl);
792
793         /* set sample rate */
794         freq = snd_cmipci_rate_freq(runtime->rate);
795         val = snd_cmipci_read(cm, CM_REG_FUNCTRL1);
796         if (rec->ch) {
797                 val &= ~CM_ASFC_MASK;
798                 val |= (freq << CM_ASFC_SHIFT) & CM_ASFC_MASK;
799         } else {
800                 val &= ~CM_DSFC_MASK;
801                 val |= (freq << CM_DSFC_SHIFT) & CM_DSFC_MASK;
802         }
803         snd_cmipci_write(cm, CM_REG_FUNCTRL1, val);
804         //snd_printd("cmipci: functrl1 = %08x\n", val);
805
806         /* set format */
807         val = snd_cmipci_read(cm, CM_REG_CHFORMAT);
808         if (rec->ch) {
809                 val &= ~CM_CH1FMT_MASK;
810                 val |= rec->fmt << CM_CH1FMT_SHIFT;
811         } else {
812                 val &= ~CM_CH0FMT_MASK;
813                 val |= rec->fmt << CM_CH0FMT_SHIFT;
814         }
815         snd_cmipci_write(cm, CM_REG_CHFORMAT, val);
816         //snd_printd("cmipci: chformat = %08x\n", val);
817
818         rec->running = 0;
819         spin_unlock_irq(&cm->reg_lock);
820
821         return 0;
822 }
823
824 /*
825  * PCM trigger/stop
826  */
827 static int snd_cmipci_pcm_trigger(struct cmipci *cm, struct cmipci_pcm *rec,
828                                   struct snd_pcm_substream *substream, int cmd)
829 {
830         unsigned int inthld, chen, reset, pause;
831         int result = 0;
832
833         inthld = CM_CH0_INT_EN << rec->ch;
834         chen = CM_CHEN0 << rec->ch;
835         reset = CM_RST_CH0 << rec->ch;
836         pause = CM_PAUSE0 << rec->ch;
837
838         spin_lock(&cm->reg_lock);
839         switch (cmd) {
840         case SNDRV_PCM_TRIGGER_START:
841                 rec->running = 1;
842                 /* set interrupt */
843                 snd_cmipci_set_bit(cm, CM_REG_INT_HLDCLR, inthld);
844                 cm->ctrl |= chen;
845                 /* enable channel */
846                 snd_cmipci_write(cm, CM_REG_FUNCTRL0, cm->ctrl);
847                 //snd_printd("cmipci: functrl0 = %08x\n", cm->ctrl);
848                 break;
849         case SNDRV_PCM_TRIGGER_STOP:
850                 rec->running = 0;
851                 /* disable interrupt */
852                 snd_cmipci_clear_bit(cm, CM_REG_INT_HLDCLR, inthld);
853                 /* reset */
854                 cm->ctrl &= ~chen;
855                 snd_cmipci_write(cm, CM_REG_FUNCTRL0, cm->ctrl | reset);
856                 snd_cmipci_write(cm, CM_REG_FUNCTRL0, cm->ctrl & ~reset);
857                 break;
858         case SNDRV_PCM_TRIGGER_PAUSE_PUSH:
859         case SNDRV_PCM_TRIGGER_SUSPEND:
860                 cm->ctrl |= pause;
861                 snd_cmipci_write(cm, CM_REG_FUNCTRL0, cm->ctrl);
862                 break;
863         case SNDRV_PCM_TRIGGER_PAUSE_RELEASE:
864         case SNDRV_PCM_TRIGGER_RESUME:
865                 cm->ctrl &= ~pause;
866                 snd_cmipci_write(cm, CM_REG_FUNCTRL0, cm->ctrl);
867                 break;
868         default:
869                 result = -EINVAL;
870                 break;
871         }
872         spin_unlock(&cm->reg_lock);
873         return result;
874 }
875
876 /*
877  * return the current pointer
878  */
879 static snd_pcm_uframes_t snd_cmipci_pcm_pointer(struct cmipci *cm, struct cmipci_pcm *rec,
880                                                 struct snd_pcm_substream *substream)
881 {
882         size_t ptr;
883         unsigned int reg;
884         if (!rec->running)
885                 return 0;
886 #if 1 // this seems better..
887         reg = rec->ch ? CM_REG_CH1_FRAME2 : CM_REG_CH0_FRAME2;
888         ptr = rec->dma_size - (snd_cmipci_read_w(cm, reg) + 1);
889         ptr >>= rec->shift;
890 #else
891         reg = rec->ch ? CM_REG_CH1_FRAME1 : CM_REG_CH0_FRAME1;
892         ptr = snd_cmipci_read(cm, reg) - rec->offset;
893         ptr = bytes_to_frames(substream->runtime, ptr);
894 #endif
895         if (substream->runtime->channels > 2)
896                 ptr = (ptr * 2) / substream->runtime->channels;
897         return ptr;
898 }
899
900 /*
901  * playback
902  */
903
904 static int snd_cmipci_playback_trigger(struct snd_pcm_substream *substream,
905                                        int cmd)
906 {
907         struct cmipci *cm = snd_pcm_substream_chip(substream);
908         return snd_cmipci_pcm_trigger(cm, &cm->channel[CM_CH_PLAY], substream, cmd);
909 }
910
911 static snd_pcm_uframes_t snd_cmipci_playback_pointer(struct snd_pcm_substream *substream)
912 {
913         struct cmipci *cm = snd_pcm_substream_chip(substream);
914         return snd_cmipci_pcm_pointer(cm, &cm->channel[CM_CH_PLAY], substream);
915 }
916
917
918
919 /*
920  * capture
921  */
922
923 static int snd_cmipci_capture_trigger(struct snd_pcm_substream *substream,
924                                      int cmd)
925 {
926         struct cmipci *cm = snd_pcm_substream_chip(substream);
927         return snd_cmipci_pcm_trigger(cm, &cm->channel[CM_CH_CAPT], substream, cmd);
928 }
929
930 static snd_pcm_uframes_t snd_cmipci_capture_pointer(struct snd_pcm_substream *substream)
931 {
932         struct cmipci *cm = snd_pcm_substream_chip(substream);
933         return snd_cmipci_pcm_pointer(cm, &cm->channel[CM_CH_CAPT], substream);
934 }
935
936
937 /*
938  * hw preparation for spdif
939  */
940
941 static int snd_cmipci_spdif_default_info(struct snd_kcontrol *kcontrol,
942                                          struct snd_ctl_elem_info *uinfo)
943 {
944         uinfo->type = SNDRV_CTL_ELEM_TYPE_IEC958;
945         uinfo->count = 1;
946         return 0;
947 }
948
949 static int snd_cmipci_spdif_default_get(struct snd_kcontrol *kcontrol,
950                                         struct snd_ctl_elem_value *ucontrol)
951 {
952         struct cmipci *chip = snd_kcontrol_chip(kcontrol);
953         int i;
954
955         spin_lock_irq(&chip->reg_lock);
956         for (i = 0; i < 4; i++)
957                 ucontrol->value.iec958.status[i] = (chip->dig_status >> (i * 8)) & 0xff;
958         spin_unlock_irq(&chip->reg_lock);
959         return 0;
960 }
961
962 static int snd_cmipci_spdif_default_put(struct snd_kcontrol *kcontrol,
963                                          struct snd_ctl_elem_value *ucontrol)
964 {
965         struct cmipci *chip = snd_kcontrol_chip(kcontrol);
966         int i, change;
967         unsigned int val;
968
969         val = 0;
970         spin_lock_irq(&chip->reg_lock);
971         for (i = 0; i < 4; i++)
972                 val |= (unsigned int)ucontrol->value.iec958.status[i] << (i * 8);
973         change = val != chip->dig_status;
974         chip->dig_status = val;
975         spin_unlock_irq(&chip->reg_lock);
976         return change;
977 }
978
979 static struct snd_kcontrol_new snd_cmipci_spdif_default __devinitdata =
980 {
981         .iface =        SNDRV_CTL_ELEM_IFACE_PCM,
982         .name =         SNDRV_CTL_NAME_IEC958("",PLAYBACK,DEFAULT),
983         .info =         snd_cmipci_spdif_default_info,
984         .get =          snd_cmipci_spdif_default_get,
985         .put =          snd_cmipci_spdif_default_put
986 };
987
988 static int snd_cmipci_spdif_mask_info(struct snd_kcontrol *kcontrol,
989                                       struct snd_ctl_elem_info *uinfo)
990 {
991         uinfo->type = SNDRV_CTL_ELEM_TYPE_IEC958;
992         uinfo->count = 1;
993         return 0;
994 }
995
996 static int snd_cmipci_spdif_mask_get(struct snd_kcontrol *kcontrol,
997                                      struct snd_ctl_elem_value *ucontrol)
998 {
999         ucontrol->value.iec958.status[0] = 0xff;
1000         ucontrol->value.iec958.status[1] = 0xff;
1001         ucontrol->value.iec958.status[2] = 0xff;
1002         ucontrol->value.iec958.status[3] = 0xff;
1003         return 0;
1004 }
1005
1006 static struct snd_kcontrol_new snd_cmipci_spdif_mask __devinitdata =
1007 {
1008         .access =       SNDRV_CTL_ELEM_ACCESS_READ,
1009         .iface =        SNDRV_CTL_ELEM_IFACE_PCM,
1010         .name =         SNDRV_CTL_NAME_IEC958("",PLAYBACK,CON_MASK),
1011         .info =         snd_cmipci_spdif_mask_info,
1012         .get =          snd_cmipci_spdif_mask_get,
1013 };
1014
1015 static int snd_cmipci_spdif_stream_info(struct snd_kcontrol *kcontrol,
1016                                         struct snd_ctl_elem_info *uinfo)
1017 {
1018         uinfo->type = SNDRV_CTL_ELEM_TYPE_IEC958;
1019         uinfo->count = 1;
1020         return 0;
1021 }
1022
1023 static int snd_cmipci_spdif_stream_get(struct snd_kcontrol *kcontrol,
1024                                        struct snd_ctl_elem_value *ucontrol)
1025 {
1026         struct cmipci *chip = snd_kcontrol_chip(kcontrol);
1027         int i;
1028
1029         spin_lock_irq(&chip->reg_lock);
1030         for (i = 0; i < 4; i++)
1031                 ucontrol->value.iec958.status[i] = (chip->dig_pcm_status >> (i * 8)) & 0xff;
1032         spin_unlock_irq(&chip->reg_lock);
1033         return 0;
1034 }
1035
1036 static int snd_cmipci_spdif_stream_put(struct snd_kcontrol *kcontrol,
1037                                        struct snd_ctl_elem_value *ucontrol)
1038 {
1039         struct cmipci *chip = snd_kcontrol_chip(kcontrol);
1040         int i, change;
1041         unsigned int val;
1042
1043         val = 0;
1044         spin_lock_irq(&chip->reg_lock);
1045         for (i = 0; i < 4; i++)
1046                 val |= (unsigned int)ucontrol->value.iec958.status[i] << (i * 8);
1047         change = val != chip->dig_pcm_status;
1048         chip->dig_pcm_status = val;
1049         spin_unlock_irq(&chip->reg_lock);
1050         return change;
1051 }
1052
1053 static struct snd_kcontrol_new snd_cmipci_spdif_stream __devinitdata =
1054 {
1055         .access =       SNDRV_CTL_ELEM_ACCESS_READWRITE | SNDRV_CTL_ELEM_ACCESS_INACTIVE,
1056         .iface =        SNDRV_CTL_ELEM_IFACE_PCM,
1057         .name =         SNDRV_CTL_NAME_IEC958("",PLAYBACK,PCM_STREAM),
1058         .info =         snd_cmipci_spdif_stream_info,
1059         .get =          snd_cmipci_spdif_stream_get,
1060         .put =          snd_cmipci_spdif_stream_put
1061 };
1062
1063 /*
1064  */
1065
1066 /* save mixer setting and mute for AC3 playback */
1067 static int save_mixer_state(struct cmipci *cm)
1068 {
1069         if (! cm->mixer_insensitive) {
1070                 struct snd_ctl_elem_value *val;
1071                 unsigned int i;
1072
1073                 val = kmalloc(sizeof(*val), GFP_ATOMIC);
1074                 if (!val)
1075                         return -ENOMEM;
1076                 for (i = 0; i < CM_SAVED_MIXERS; i++) {
1077                         struct snd_kcontrol *ctl = cm->mixer_res_ctl[i];
1078                         if (ctl) {
1079                                 int event;
1080                                 memset(val, 0, sizeof(*val));
1081                                 ctl->get(ctl, val);
1082                                 cm->mixer_res_status[i] = val->value.integer.value[0];
1083                                 val->value.integer.value[0] = cm_saved_mixer[i].toggle_on;
1084                                 event = SNDRV_CTL_EVENT_MASK_INFO;
1085                                 if (cm->mixer_res_status[i] != val->value.integer.value[0]) {
1086                                         ctl->put(ctl, val); /* toggle */
1087                                         event |= SNDRV_CTL_EVENT_MASK_VALUE;
1088                                 }
1089                                 ctl->vd[0].access |= SNDRV_CTL_ELEM_ACCESS_INACTIVE;
1090                                 snd_ctl_notify(cm->card, event, &ctl->id);
1091                         }
1092                 }
1093                 kfree(val);
1094                 cm->mixer_insensitive = 1;
1095         }
1096         return 0;
1097 }
1098
1099
1100 /* restore the previously saved mixer status */
1101 static void restore_mixer_state(struct cmipci *cm)
1102 {
1103         if (cm->mixer_insensitive) {
1104                 struct snd_ctl_elem_value *val;
1105                 unsigned int i;
1106
1107                 val = kmalloc(sizeof(*val), GFP_KERNEL);
1108                 if (!val)
1109                         return;
1110                 cm->mixer_insensitive = 0; /* at first clear this;
1111                                               otherwise the changes will be ignored */
1112                 for (i = 0; i < CM_SAVED_MIXERS; i++) {
1113                         struct snd_kcontrol *ctl = cm->mixer_res_ctl[i];
1114                         if (ctl) {
1115                                 int event;
1116
1117                                 memset(val, 0, sizeof(*val));
1118                                 ctl->vd[0].access &= ~SNDRV_CTL_ELEM_ACCESS_INACTIVE;
1119                                 ctl->get(ctl, val);
1120                                 event = SNDRV_CTL_EVENT_MASK_INFO;
1121                                 if (val->value.integer.value[0] != cm->mixer_res_status[i]) {
1122                                         val->value.integer.value[0] = cm->mixer_res_status[i];
1123                                         ctl->put(ctl, val);
1124                                         event |= SNDRV_CTL_EVENT_MASK_VALUE;
1125                                 }
1126                                 snd_ctl_notify(cm->card, event, &ctl->id);
1127                         }
1128                 }
1129                 kfree(val);
1130         }
1131 }
1132
1133 /* spinlock held! */
1134 static void setup_ac3(struct cmipci *cm, struct snd_pcm_substream *subs, int do_ac3, int rate)
1135 {
1136         if (do_ac3) {
1137                 /* AC3EN for 037 */
1138                 snd_cmipci_set_bit(cm, CM_REG_CHFORMAT, CM_AC3EN1);
1139                 /* AC3EN for 039 */
1140                 snd_cmipci_set_bit(cm, CM_REG_MISC_CTRL, CM_AC3EN2);
1141         
1142                 if (cm->can_ac3_hw) {
1143                         /* SPD24SEL for 037, 0x02 */
1144                         /* SPD24SEL for 039, 0x20, but cannot be set */
1145                         snd_cmipci_set_bit(cm, CM_REG_CHFORMAT, CM_SPD24SEL);
1146                         snd_cmipci_clear_bit(cm, CM_REG_MISC_CTRL, CM_SPD32SEL);
1147                 } else { /* can_ac3_sw */
1148                         /* SPD32SEL for 037 & 039, 0x20 */
1149                         snd_cmipci_set_bit(cm, CM_REG_MISC_CTRL, CM_SPD32SEL);
1150                         /* set 176K sample rate to fix 033 HW bug */
1151                         if (cm->chip_version == 33) {
1152                                 if (rate >= 48000) {
1153                                         snd_cmipci_set_bit(cm, CM_REG_CHFORMAT, CM_PLAYBACK_SRATE_176K);
1154                                 } else {
1155                                         snd_cmipci_clear_bit(cm, CM_REG_CHFORMAT, CM_PLAYBACK_SRATE_176K);
1156                                 }
1157                         }
1158                 }
1159
1160         } else {
1161                 snd_cmipci_clear_bit(cm, CM_REG_CHFORMAT, CM_AC3EN1);
1162                 snd_cmipci_clear_bit(cm, CM_REG_MISC_CTRL, CM_AC3EN2);
1163
1164                 if (cm->can_ac3_hw) {
1165                         /* chip model >= 37 */
1166                         if (snd_pcm_format_width(subs->runtime->format) > 16) {
1167                                 snd_cmipci_set_bit(cm, CM_REG_MISC_CTRL, CM_SPD32SEL);
1168                                 snd_cmipci_set_bit(cm, CM_REG_CHFORMAT, CM_SPD24SEL);
1169                         } else {
1170                                 snd_cmipci_clear_bit(cm, CM_REG_MISC_CTRL, CM_SPD32SEL);
1171                                 snd_cmipci_clear_bit(cm, CM_REG_CHFORMAT, CM_SPD24SEL);
1172                         }
1173                 } else {
1174                         snd_cmipci_clear_bit(cm, CM_REG_MISC_CTRL, CM_SPD32SEL);
1175                         snd_cmipci_clear_bit(cm, CM_REG_CHFORMAT, CM_SPD24SEL);
1176                         snd_cmipci_clear_bit(cm, CM_REG_CHFORMAT, CM_PLAYBACK_SRATE_176K);
1177                 }
1178         }
1179 }
1180
1181 static int setup_spdif_playback(struct cmipci *cm, struct snd_pcm_substream *subs, int up, int do_ac3)
1182 {
1183         int rate, err;
1184
1185         rate = subs->runtime->rate;
1186
1187         if (up && do_ac3)
1188                 if ((err = save_mixer_state(cm)) < 0)
1189                         return err;
1190
1191         spin_lock_irq(&cm->reg_lock);
1192         cm->spdif_playback_avail = up;
1193         if (up) {
1194                 /* they are controlled via "IEC958 Output Switch" */
1195                 /* snd_cmipci_set_bit(cm, CM_REG_LEGACY_CTRL, CM_ENSPDOUT); */
1196                 /* snd_cmipci_set_bit(cm, CM_REG_FUNCTRL1, CM_SPDO2DAC); */
1197                 if (cm->spdif_playback_enabled)
1198                         snd_cmipci_set_bit(cm, CM_REG_FUNCTRL1, CM_PLAYBACK_SPDF);
1199                 setup_ac3(cm, subs, do_ac3, rate);
1200
1201                 if (rate == 48000)
1202                         snd_cmipci_set_bit(cm, CM_REG_MISC_CTRL, CM_SPDIF48K | CM_SPDF_AC97);
1203                 else
1204                         snd_cmipci_clear_bit(cm, CM_REG_MISC_CTRL, CM_SPDIF48K | CM_SPDF_AC97);
1205
1206         } else {
1207                 /* they are controlled via "IEC958 Output Switch" */
1208                 /* snd_cmipci_clear_bit(cm, CM_REG_LEGACY_CTRL, CM_ENSPDOUT); */
1209                 /* snd_cmipci_clear_bit(cm, CM_REG_FUNCTRL1, CM_SPDO2DAC); */
1210                 snd_cmipci_clear_bit(cm, CM_REG_FUNCTRL1, CM_PLAYBACK_SPDF);
1211                 setup_ac3(cm, subs, 0, 0);
1212         }
1213         spin_unlock_irq(&cm->reg_lock);
1214         return 0;
1215 }
1216
1217
1218 /*
1219  * preparation
1220  */
1221
1222 /* playback - enable spdif only on the certain condition */
1223 static int snd_cmipci_playback_prepare(struct snd_pcm_substream *substream)
1224 {
1225         struct cmipci *cm = snd_pcm_substream_chip(substream);
1226         int rate = substream->runtime->rate;
1227         int err, do_spdif, do_ac3 = 0;
1228
1229         do_spdif = ((rate == 44100 || rate == 48000) &&
1230                     substream->runtime->format == SNDRV_PCM_FORMAT_S16_LE &&
1231                     substream->runtime->channels == 2);
1232         if (do_spdif && cm->can_ac3_hw) 
1233                 do_ac3 = cm->dig_pcm_status & IEC958_AES0_NONAUDIO;
1234         if ((err = setup_spdif_playback(cm, substream, do_spdif, do_ac3)) < 0)
1235                 return err;
1236         return snd_cmipci_pcm_prepare(cm, &cm->channel[CM_CH_PLAY], substream);
1237 }
1238
1239 /* playback  (via device #2) - enable spdif always */
1240 static int snd_cmipci_playback_spdif_prepare(struct snd_pcm_substream *substream)
1241 {
1242         struct cmipci *cm = snd_pcm_substream_chip(substream);
1243         int err, do_ac3;
1244
1245         if (cm->can_ac3_hw) 
1246                 do_ac3 = cm->dig_pcm_status & IEC958_AES0_NONAUDIO;
1247         else
1248                 do_ac3 = 1; /* doesn't matter */
1249         if ((err = setup_spdif_playback(cm, substream, 1, do_ac3)) < 0)
1250                 return err;
1251         return snd_cmipci_pcm_prepare(cm, &cm->channel[CM_CH_PLAY], substream);
1252 }
1253
1254 static int snd_cmipci_playback_hw_free(struct snd_pcm_substream *substream)
1255 {
1256         struct cmipci *cm = snd_pcm_substream_chip(substream);
1257         setup_spdif_playback(cm, substream, 0, 0);
1258         restore_mixer_state(cm);
1259         return snd_cmipci_hw_free(substream);
1260 }
1261
1262 /* capture */
1263 static int snd_cmipci_capture_prepare(struct snd_pcm_substream *substream)
1264 {
1265         struct cmipci *cm = snd_pcm_substream_chip(substream);
1266         return snd_cmipci_pcm_prepare(cm, &cm->channel[CM_CH_CAPT], substream);
1267 }
1268
1269 /* capture with spdif (via device #2) */
1270 static int snd_cmipci_capture_spdif_prepare(struct snd_pcm_substream *substream)
1271 {
1272         struct cmipci *cm = snd_pcm_substream_chip(substream);
1273
1274         spin_lock_irq(&cm->reg_lock);
1275         snd_cmipci_set_bit(cm, CM_REG_FUNCTRL1, CM_CAPTURE_SPDF);
1276         spin_unlock_irq(&cm->reg_lock);
1277
1278         return snd_cmipci_pcm_prepare(cm, &cm->channel[CM_CH_CAPT], substream);
1279 }
1280
1281 static int snd_cmipci_capture_spdif_hw_free(struct snd_pcm_substream *subs)
1282 {
1283         struct cmipci *cm = snd_pcm_substream_chip(subs);
1284
1285         spin_lock_irq(&cm->reg_lock);
1286         snd_cmipci_clear_bit(cm, CM_REG_FUNCTRL1, CM_CAPTURE_SPDF);
1287         spin_unlock_irq(&cm->reg_lock);
1288
1289         return snd_cmipci_hw_free(subs);
1290 }
1291
1292
1293 /*
1294  * interrupt handler
1295  */
1296 static irqreturn_t snd_cmipci_interrupt(int irq, void *dev_id)
1297 {
1298         struct cmipci *cm = dev_id;
1299         unsigned int status, mask = 0;
1300         
1301         /* fastpath out, to ease interrupt sharing */
1302         status = snd_cmipci_read(cm, CM_REG_INT_STATUS);
1303         if (!(status & CM_INTR))
1304                 return IRQ_NONE;
1305
1306         /* acknowledge interrupt */
1307         spin_lock(&cm->reg_lock);
1308         if (status & CM_CHINT0)
1309                 mask |= CM_CH0_INT_EN;
1310         if (status & CM_CHINT1)
1311                 mask |= CM_CH1_INT_EN;
1312         snd_cmipci_clear_bit(cm, CM_REG_INT_HLDCLR, mask);
1313         snd_cmipci_set_bit(cm, CM_REG_INT_HLDCLR, mask);
1314         spin_unlock(&cm->reg_lock);
1315
1316         if (cm->rmidi && (status & CM_UARTINT))
1317                 snd_mpu401_uart_interrupt(irq, cm->rmidi->private_data);
1318
1319         if (cm->pcm) {
1320                 if ((status & CM_CHINT0) && cm->channel[0].running)
1321                         snd_pcm_period_elapsed(cm->channel[0].substream);
1322                 if ((status & CM_CHINT1) && cm->channel[1].running)
1323                         snd_pcm_period_elapsed(cm->channel[1].substream);
1324         }
1325         return IRQ_HANDLED;
1326 }
1327
1328 /*
1329  * h/w infos
1330  */
1331
1332 /* playback on channel A */
1333 static struct snd_pcm_hardware snd_cmipci_playback =
1334 {
1335         .info =                 (SNDRV_PCM_INFO_MMAP | SNDRV_PCM_INFO_INTERLEAVED |
1336                                  SNDRV_PCM_INFO_BLOCK_TRANSFER | SNDRV_PCM_INFO_PAUSE |
1337                                  SNDRV_PCM_INFO_RESUME | SNDRV_PCM_INFO_MMAP_VALID),
1338         .formats =              SNDRV_PCM_FMTBIT_U8 | SNDRV_PCM_FMTBIT_S16_LE,
1339         .rates =                SNDRV_PCM_RATE_5512 | SNDRV_PCM_RATE_8000_48000,
1340         .rate_min =             5512,
1341         .rate_max =             48000,
1342         .channels_min =         1,
1343         .channels_max =         2,
1344         .buffer_bytes_max =     (128*1024),
1345         .period_bytes_min =     64,
1346         .period_bytes_max =     (128*1024),
1347         .periods_min =          2,
1348         .periods_max =          1024,
1349         .fifo_size =            0,
1350 };
1351
1352 /* capture on channel B */
1353 static struct snd_pcm_hardware snd_cmipci_capture =
1354 {
1355         .info =                 (SNDRV_PCM_INFO_MMAP | SNDRV_PCM_INFO_INTERLEAVED |
1356                                  SNDRV_PCM_INFO_BLOCK_TRANSFER | SNDRV_PCM_INFO_PAUSE |
1357                                  SNDRV_PCM_INFO_RESUME | SNDRV_PCM_INFO_MMAP_VALID),
1358         .formats =              SNDRV_PCM_FMTBIT_U8 | SNDRV_PCM_FMTBIT_S16_LE,
1359         .rates =                SNDRV_PCM_RATE_5512 | SNDRV_PCM_RATE_8000_48000,
1360         .rate_min =             5512,
1361         .rate_max =             48000,
1362         .channels_min =         1,
1363         .channels_max =         2,
1364         .buffer_bytes_max =     (128*1024),
1365         .period_bytes_min =     64,
1366         .period_bytes_max =     (128*1024),
1367         .periods_min =          2,
1368         .periods_max =          1024,
1369         .fifo_size =            0,
1370 };
1371
1372 /* playback on channel B - stereo 16bit only? */
1373 static struct snd_pcm_hardware snd_cmipci_playback2 =
1374 {
1375         .info =                 (SNDRV_PCM_INFO_MMAP | SNDRV_PCM_INFO_INTERLEAVED |
1376                                  SNDRV_PCM_INFO_BLOCK_TRANSFER | SNDRV_PCM_INFO_PAUSE |
1377                                  SNDRV_PCM_INFO_RESUME | SNDRV_PCM_INFO_MMAP_VALID),
1378         .formats =              SNDRV_PCM_FMTBIT_S16_LE,
1379         .rates =                SNDRV_PCM_RATE_5512 | SNDRV_PCM_RATE_8000_48000,
1380         .rate_min =             5512,
1381         .rate_max =             48000,
1382         .channels_min =         2,
1383         .channels_max =         2,
1384         .buffer_bytes_max =     (128*1024),
1385         .period_bytes_min =     64,
1386         .period_bytes_max =     (128*1024),
1387         .periods_min =          2,
1388         .periods_max =          1024,
1389         .fifo_size =            0,
1390 };
1391
1392 /* spdif playback on channel A */
1393 static struct snd_pcm_hardware snd_cmipci_playback_spdif =
1394 {
1395         .info =                 (SNDRV_PCM_INFO_MMAP | SNDRV_PCM_INFO_INTERLEAVED |
1396                                  SNDRV_PCM_INFO_BLOCK_TRANSFER | SNDRV_PCM_INFO_PAUSE |
1397                                  SNDRV_PCM_INFO_RESUME | SNDRV_PCM_INFO_MMAP_VALID),
1398         .formats =              SNDRV_PCM_FMTBIT_S16_LE,
1399         .rates =                SNDRV_PCM_RATE_44100 | SNDRV_PCM_RATE_48000,
1400         .rate_min =             44100,
1401         .rate_max =             48000,
1402         .channels_min =         2,
1403         .channels_max =         2,
1404         .buffer_bytes_max =     (128*1024),
1405         .period_bytes_min =     64,
1406         .period_bytes_max =     (128*1024),
1407         .periods_min =          2,
1408         .periods_max =          1024,
1409         .fifo_size =            0,
1410 };
1411
1412 /* spdif playback on channel A (32bit, IEC958 subframes) */
1413 static struct snd_pcm_hardware snd_cmipci_playback_iec958_subframe =
1414 {
1415         .info =                 (SNDRV_PCM_INFO_MMAP | SNDRV_PCM_INFO_INTERLEAVED |
1416                                  SNDRV_PCM_INFO_BLOCK_TRANSFER | SNDRV_PCM_INFO_PAUSE |
1417                                  SNDRV_PCM_INFO_RESUME | SNDRV_PCM_INFO_MMAP_VALID),
1418         .formats =              SNDRV_PCM_FMTBIT_IEC958_SUBFRAME_LE,
1419         .rates =                SNDRV_PCM_RATE_44100 | SNDRV_PCM_RATE_48000,
1420         .rate_min =             44100,
1421         .rate_max =             48000,
1422         .channels_min =         2,
1423         .channels_max =         2,
1424         .buffer_bytes_max =     (128*1024),
1425         .period_bytes_min =     64,
1426         .period_bytes_max =     (128*1024),
1427         .periods_min =          2,
1428         .periods_max =          1024,
1429         .fifo_size =            0,
1430 };
1431
1432 /* spdif capture on channel B */
1433 static struct snd_pcm_hardware snd_cmipci_capture_spdif =
1434 {
1435         .info =                 (SNDRV_PCM_INFO_MMAP | SNDRV_PCM_INFO_INTERLEAVED |
1436                                  SNDRV_PCM_INFO_BLOCK_TRANSFER | SNDRV_PCM_INFO_PAUSE |
1437                                  SNDRV_PCM_INFO_RESUME | SNDRV_PCM_INFO_MMAP_VALID),
1438         .formats =              SNDRV_PCM_FMTBIT_S16_LE,
1439         .rates =                SNDRV_PCM_RATE_44100 | SNDRV_PCM_RATE_48000,
1440         .rate_min =             44100,
1441         .rate_max =             48000,
1442         .channels_min =         2,
1443         .channels_max =         2,
1444         .buffer_bytes_max =     (128*1024),
1445         .period_bytes_min =     64,
1446         .period_bytes_max =     (128*1024),
1447         .periods_min =          2,
1448         .periods_max =          1024,
1449         .fifo_size =            0,
1450 };
1451
1452 /*
1453  * check device open/close
1454  */
1455 static int open_device_check(struct cmipci *cm, int mode, struct snd_pcm_substream *subs)
1456 {
1457         int ch = mode & CM_OPEN_CH_MASK;
1458
1459         /* FIXME: a file should wait until the device becomes free
1460          * when it's opened on blocking mode.  however, since the current
1461          * pcm framework doesn't pass file pointer before actually opened,
1462          * we can't know whether blocking mode or not in open callback..
1463          */
1464         mutex_lock(&cm->open_mutex);
1465         if (cm->opened[ch]) {
1466                 mutex_unlock(&cm->open_mutex);
1467                 return -EBUSY;
1468         }
1469         cm->opened[ch] = mode;
1470         cm->channel[ch].substream = subs;
1471         if (! (mode & CM_OPEN_DAC)) {
1472                 /* disable dual DAC mode */
1473                 cm->channel[ch].is_dac = 0;
1474                 spin_lock_irq(&cm->reg_lock);
1475                 snd_cmipci_clear_bit(cm, CM_REG_MISC_CTRL, CM_ENDBDAC);
1476                 spin_unlock_irq(&cm->reg_lock);
1477         }
1478         mutex_unlock(&cm->open_mutex);
1479         return 0;
1480 }
1481
1482 static void close_device_check(struct cmipci *cm, int mode)
1483 {
1484         int ch = mode & CM_OPEN_CH_MASK;
1485
1486         mutex_lock(&cm->open_mutex);
1487         if (cm->opened[ch] == mode) {
1488                 if (cm->channel[ch].substream) {
1489                         snd_cmipci_ch_reset(cm, ch);
1490                         cm->channel[ch].running = 0;
1491                         cm->channel[ch].substream = NULL;
1492                 }
1493                 cm->opened[ch] = 0;
1494                 if (! cm->channel[ch].is_dac) {
1495                         /* enable dual DAC mode again */
1496                         cm->channel[ch].is_dac = 1;
1497                         spin_lock_irq(&cm->reg_lock);
1498                         snd_cmipci_set_bit(cm, CM_REG_MISC_CTRL, CM_ENDBDAC);
1499                         spin_unlock_irq(&cm->reg_lock);
1500                 }
1501         }
1502         mutex_unlock(&cm->open_mutex);
1503 }
1504
1505 /*
1506  */
1507
1508 static int snd_cmipci_playback_open(struct snd_pcm_substream *substream)
1509 {
1510         struct cmipci *cm = snd_pcm_substream_chip(substream);
1511         struct snd_pcm_runtime *runtime = substream->runtime;
1512         int err;
1513
1514         if ((err = open_device_check(cm, CM_OPEN_PLAYBACK, substream)) < 0)
1515                 return err;
1516         runtime->hw = snd_cmipci_playback;
1517         runtime->hw.channels_max = cm->max_channels;
1518         snd_pcm_hw_constraint_minmax(runtime, SNDRV_PCM_HW_PARAM_BUFFER_SIZE, 0, 0x10000);
1519         cm->dig_pcm_status = cm->dig_status;
1520         return 0;
1521 }
1522
1523 static int snd_cmipci_capture_open(struct snd_pcm_substream *substream)
1524 {
1525         struct cmipci *cm = snd_pcm_substream_chip(substream);
1526         struct snd_pcm_runtime *runtime = substream->runtime;
1527         int err;
1528
1529         if ((err = open_device_check(cm, CM_OPEN_CAPTURE, substream)) < 0)
1530                 return err;
1531         runtime->hw = snd_cmipci_capture;
1532         if (cm->chip_version == 68) {   // 8768 only supports 44k/48k recording
1533                 runtime->hw.rate_min = 41000;
1534                 runtime->hw.rates = SNDRV_PCM_RATE_44100 | SNDRV_PCM_RATE_48000;
1535         }
1536         snd_pcm_hw_constraint_minmax(runtime, SNDRV_PCM_HW_PARAM_BUFFER_SIZE, 0, 0x10000);
1537         return 0;
1538 }
1539
1540 static int snd_cmipci_playback2_open(struct snd_pcm_substream *substream)
1541 {
1542         struct cmipci *cm = snd_pcm_substream_chip(substream);
1543         struct snd_pcm_runtime *runtime = substream->runtime;
1544         int err;
1545
1546         if ((err = open_device_check(cm, CM_OPEN_PLAYBACK2, substream)) < 0) /* use channel B */
1547                 return err;
1548         runtime->hw = snd_cmipci_playback2;
1549         mutex_lock(&cm->open_mutex);
1550         if (! cm->opened[CM_CH_PLAY]) {
1551                 if (cm->can_multi_ch) {
1552                         runtime->hw.channels_max = cm->max_channels;
1553                         if (cm->max_channels == 4)
1554                                 snd_pcm_hw_constraint_list(runtime, 0, SNDRV_PCM_HW_PARAM_CHANNELS, &hw_constraints_channels_4);
1555                         else if (cm->max_channels == 6)
1556                                 snd_pcm_hw_constraint_list(runtime, 0, SNDRV_PCM_HW_PARAM_CHANNELS, &hw_constraints_channels_6);
1557                         else if (cm->max_channels == 8)
1558                                 snd_pcm_hw_constraint_list(runtime, 0, SNDRV_PCM_HW_PARAM_CHANNELS, &hw_constraints_channels_8);
1559                 }
1560                 snd_pcm_hw_constraint_minmax(runtime, SNDRV_PCM_HW_PARAM_BUFFER_SIZE, 0, 0x10000);
1561         }
1562         mutex_unlock(&cm->open_mutex);
1563         return 0;
1564 }
1565
1566 static int snd_cmipci_playback_spdif_open(struct snd_pcm_substream *substream)
1567 {
1568         struct cmipci *cm = snd_pcm_substream_chip(substream);
1569         struct snd_pcm_runtime *runtime = substream->runtime;
1570         int err;
1571
1572         if ((err = open_device_check(cm, CM_OPEN_SPDIF_PLAYBACK, substream)) < 0) /* use channel A */
1573                 return err;
1574         if (cm->can_ac3_hw) {
1575                 runtime->hw = snd_cmipci_playback_spdif;
1576                 if (cm->chip_version >= 37)
1577                         runtime->hw.formats |= SNDRV_PCM_FMTBIT_S32_LE;
1578         } else {
1579                 runtime->hw = snd_cmipci_playback_iec958_subframe;
1580         }
1581         snd_pcm_hw_constraint_minmax(runtime, SNDRV_PCM_HW_PARAM_BUFFER_SIZE, 0, 0x40000);
1582         cm->dig_pcm_status = cm->dig_status;
1583         return 0;
1584 }
1585
1586 static int snd_cmipci_capture_spdif_open(struct snd_pcm_substream *substream)
1587 {
1588         struct cmipci *cm = snd_pcm_substream_chip(substream);
1589         struct snd_pcm_runtime *runtime = substream->runtime;
1590         int err;
1591
1592         if ((err = open_device_check(cm, CM_OPEN_SPDIF_CAPTURE, substream)) < 0) /* use channel B */
1593                 return err;
1594         runtime->hw = snd_cmipci_capture_spdif;
1595         snd_pcm_hw_constraint_minmax(runtime, SNDRV_PCM_HW_PARAM_BUFFER_SIZE, 0, 0x40000);
1596         return 0;
1597 }
1598
1599
1600 /*
1601  */
1602
1603 static int snd_cmipci_playback_close(struct snd_pcm_substream *substream)
1604 {
1605         struct cmipci *cm = snd_pcm_substream_chip(substream);
1606         close_device_check(cm, CM_OPEN_PLAYBACK);
1607         return 0;
1608 }
1609
1610 static int snd_cmipci_capture_close(struct snd_pcm_substream *substream)
1611 {
1612         struct cmipci *cm = snd_pcm_substream_chip(substream);
1613         close_device_check(cm, CM_OPEN_CAPTURE);
1614         return 0;
1615 }
1616
1617 static int snd_cmipci_playback2_close(struct snd_pcm_substream *substream)
1618 {
1619         struct cmipci *cm = snd_pcm_substream_chip(substream);
1620         close_device_check(cm, CM_OPEN_PLAYBACK2);
1621         close_device_check(cm, CM_OPEN_PLAYBACK_MULTI);
1622         return 0;
1623 }
1624
1625 static int snd_cmipci_playback_spdif_close(struct snd_pcm_substream *substream)
1626 {
1627         struct cmipci *cm = snd_pcm_substream_chip(substream);
1628         close_device_check(cm, CM_OPEN_SPDIF_PLAYBACK);
1629         return 0;
1630 }
1631
1632 static int snd_cmipci_capture_spdif_close(struct snd_pcm_substream *substream)
1633 {
1634         struct cmipci *cm = snd_pcm_substream_chip(substream);
1635         close_device_check(cm, CM_OPEN_SPDIF_CAPTURE);
1636         return 0;
1637 }
1638
1639
1640 /*
1641  */
1642
1643 static struct snd_pcm_ops snd_cmipci_playback_ops = {
1644         .open =         snd_cmipci_playback_open,
1645         .close =        snd_cmipci_playback_close,
1646         .ioctl =        snd_pcm_lib_ioctl,
1647         .hw_params =    snd_cmipci_hw_params,
1648         .hw_free =      snd_cmipci_playback_hw_free,
1649         .prepare =      snd_cmipci_playback_prepare,
1650         .trigger =      snd_cmipci_playback_trigger,
1651         .pointer =      snd_cmipci_playback_pointer,
1652 };
1653
1654 static struct snd_pcm_ops snd_cmipci_capture_ops = {
1655         .open =         snd_cmipci_capture_open,
1656         .close =        snd_cmipci_capture_close,
1657         .ioctl =        snd_pcm_lib_ioctl,
1658         .hw_params =    snd_cmipci_hw_params,
1659         .hw_free =      snd_cmipci_hw_free,
1660         .prepare =      snd_cmipci_capture_prepare,
1661         .trigger =      snd_cmipci_capture_trigger,
1662         .pointer =      snd_cmipci_capture_pointer,
1663 };
1664
1665 static struct snd_pcm_ops snd_cmipci_playback2_ops = {
1666         .open =         snd_cmipci_playback2_open,
1667         .close =        snd_cmipci_playback2_close,
1668         .ioctl =        snd_pcm_lib_ioctl,
1669         .hw_params =    snd_cmipci_playback2_hw_params,
1670         .hw_free =      snd_cmipci_hw_free,
1671         .prepare =      snd_cmipci_capture_prepare,     /* channel B */
1672         .trigger =      snd_cmipci_capture_trigger,     /* channel B */
1673         .pointer =      snd_cmipci_capture_pointer,     /* channel B */
1674 };
1675
1676 static struct snd_pcm_ops snd_cmipci_playback_spdif_ops = {
1677         .open =         snd_cmipci_playback_spdif_open,
1678         .close =        snd_cmipci_playback_spdif_close,
1679         .ioctl =        snd_pcm_lib_ioctl,
1680         .hw_params =    snd_cmipci_hw_params,
1681         .hw_free =      snd_cmipci_playback_hw_free,
1682         .prepare =      snd_cmipci_playback_spdif_prepare,      /* set up rate */
1683         .trigger =      snd_cmipci_playback_trigger,
1684         .pointer =      snd_cmipci_playback_pointer,
1685 };
1686
1687 static struct snd_pcm_ops snd_cmipci_capture_spdif_ops = {
1688         .open =         snd_cmipci_capture_spdif_open,
1689         .close =        snd_cmipci_capture_spdif_close,
1690         .ioctl =        snd_pcm_lib_ioctl,
1691         .hw_params =    snd_cmipci_hw_params,
1692         .hw_free =      snd_cmipci_capture_spdif_hw_free,
1693         .prepare =      snd_cmipci_capture_spdif_prepare,
1694         .trigger =      snd_cmipci_capture_trigger,
1695         .pointer =      snd_cmipci_capture_pointer,
1696 };
1697
1698
1699 /*
1700  */
1701
1702 static int __devinit snd_cmipci_pcm_new(struct cmipci *cm, int device)
1703 {
1704         struct snd_pcm *pcm;
1705         int err;
1706
1707         err = snd_pcm_new(cm->card, cm->card->driver, device, 1, 1, &pcm);
1708         if (err < 0)
1709                 return err;
1710
1711         snd_pcm_set_ops(pcm, SNDRV_PCM_STREAM_PLAYBACK, &snd_cmipci_playback_ops);
1712         snd_pcm_set_ops(pcm, SNDRV_PCM_STREAM_CAPTURE, &snd_cmipci_capture_ops);
1713
1714         pcm->private_data = cm;
1715         pcm->info_flags = 0;
1716         strcpy(pcm->name, "C-Media PCI DAC/ADC");
1717         cm->pcm = pcm;
1718
1719         snd_pcm_lib_preallocate_pages_for_all(pcm, SNDRV_DMA_TYPE_DEV,
1720                                               snd_dma_pci_data(cm->pci), 64*1024, 128*1024);
1721
1722         return 0;
1723 }
1724
1725 static int __devinit snd_cmipci_pcm2_new(struct cmipci *cm, int device)
1726 {
1727         struct snd_pcm *pcm;
1728         int err;
1729
1730         err = snd_pcm_new(cm->card, cm->card->driver, device, 1, 0, &pcm);
1731         if (err < 0)
1732                 return err;
1733
1734         snd_pcm_set_ops(pcm, SNDRV_PCM_STREAM_PLAYBACK, &snd_cmipci_playback2_ops);
1735
1736         pcm->private_data = cm;
1737         pcm->info_flags = 0;
1738         strcpy(pcm->name, "C-Media PCI 2nd DAC");
1739         cm->pcm2 = pcm;
1740
1741         snd_pcm_lib_preallocate_pages_for_all(pcm, SNDRV_DMA_TYPE_DEV,
1742                                               snd_dma_pci_data(cm->pci), 64*1024, 128*1024);
1743
1744         return 0;
1745 }
1746
1747 static int __devinit snd_cmipci_pcm_spdif_new(struct cmipci *cm, int device)
1748 {
1749         struct snd_pcm *pcm;
1750         int err;
1751
1752         err = snd_pcm_new(cm->card, cm->card->driver, device, 1, 1, &pcm);
1753         if (err < 0)
1754                 return err;
1755
1756         snd_pcm_set_ops(pcm, SNDRV_PCM_STREAM_PLAYBACK, &snd_cmipci_playback_spdif_ops);
1757         snd_pcm_set_ops(pcm, SNDRV_PCM_STREAM_CAPTURE, &snd_cmipci_capture_spdif_ops);
1758
1759         pcm->private_data = cm;
1760         pcm->info_flags = 0;
1761         strcpy(pcm->name, "C-Media PCI IEC958");
1762         cm->pcm_spdif = pcm;
1763
1764         snd_pcm_lib_preallocate_pages_for_all(pcm, SNDRV_DMA_TYPE_DEV,
1765                                               snd_dma_pci_data(cm->pci), 64*1024, 128*1024);
1766
1767         return 0;
1768 }
1769
1770 /*
1771  * mixer interface:
1772  * - CM8338/8738 has a compatible mixer interface with SB16, but
1773  *   lack of some elements like tone control, i/o gain and AGC.
1774  * - Access to native registers:
1775  *   - A 3D switch
1776  *   - Output mute switches
1777  */
1778
1779 static void snd_cmipci_mixer_write(struct cmipci *s, unsigned char idx, unsigned char data)
1780 {
1781         outb(idx, s->iobase + CM_REG_SB16_ADDR);
1782         outb(data, s->iobase + CM_REG_SB16_DATA);
1783 }
1784
1785 static unsigned char snd_cmipci_mixer_read(struct cmipci *s, unsigned char idx)
1786 {
1787         unsigned char v;
1788
1789         outb(idx, s->iobase + CM_REG_SB16_ADDR);
1790         v = inb(s->iobase + CM_REG_SB16_DATA);
1791         return v;
1792 }
1793
1794 /*
1795  * general mixer element
1796  */
1797 struct cmipci_sb_reg {
1798         unsigned int left_reg, right_reg;
1799         unsigned int left_shift, right_shift;
1800         unsigned int mask;
1801         unsigned int invert: 1;
1802         unsigned int stereo: 1;
1803 };
1804
1805 #define COMPOSE_SB_REG(lreg,rreg,lshift,rshift,mask,invert,stereo) \
1806  ((lreg) | ((rreg) << 8) | (lshift << 16) | (rshift << 19) | (mask << 24) | (invert << 22) | (stereo << 23))
1807
1808 #define CMIPCI_DOUBLE(xname, left_reg, right_reg, left_shift, right_shift, mask, invert, stereo) \
1809 { .iface = SNDRV_CTL_ELEM_IFACE_MIXER, .name = xname, \
1810   .info = snd_cmipci_info_volume, \
1811   .get = snd_cmipci_get_volume, .put = snd_cmipci_put_volume, \
1812   .private_value = COMPOSE_SB_REG(left_reg, right_reg, left_shift, right_shift, mask, invert, stereo), \
1813 }
1814
1815 #define CMIPCI_SB_VOL_STEREO(xname,reg,shift,mask) CMIPCI_DOUBLE(xname, reg, reg+1, shift, shift, mask, 0, 1)
1816 #define CMIPCI_SB_VOL_MONO(xname,reg,shift,mask) CMIPCI_DOUBLE(xname, reg, reg, shift, shift, mask, 0, 0)
1817 #define CMIPCI_SB_SW_STEREO(xname,lshift,rshift) CMIPCI_DOUBLE(xname, SB_DSP4_OUTPUT_SW, SB_DSP4_OUTPUT_SW, lshift, rshift, 1, 0, 1)
1818 #define CMIPCI_SB_SW_MONO(xname,shift) CMIPCI_DOUBLE(xname, SB_DSP4_OUTPUT_SW, SB_DSP4_OUTPUT_SW, shift, shift, 1, 0, 0)
1819
1820 static void cmipci_sb_reg_decode(struct cmipci_sb_reg *r, unsigned long val)
1821 {
1822         r->left_reg = val & 0xff;
1823         r->right_reg = (val >> 8) & 0xff;
1824         r->left_shift = (val >> 16) & 0x07;
1825         r->right_shift = (val >> 19) & 0x07;
1826         r->invert = (val >> 22) & 1;
1827         r->stereo = (val >> 23) & 1;
1828         r->mask = (val >> 24) & 0xff;
1829 }
1830
1831 static int snd_cmipci_info_volume(struct snd_kcontrol *kcontrol,
1832                                   struct snd_ctl_elem_info *uinfo)
1833 {
1834         struct cmipci_sb_reg reg;
1835
1836         cmipci_sb_reg_decode(&reg, kcontrol->private_value);
1837         uinfo->type = reg.mask == 1 ? SNDRV_CTL_ELEM_TYPE_BOOLEAN : SNDRV_CTL_ELEM_TYPE_INTEGER;
1838         uinfo->count = reg.stereo + 1;
1839         uinfo->value.integer.min = 0;
1840         uinfo->value.integer.max = reg.mask;
1841         return 0;
1842 }
1843  
1844 static int snd_cmipci_get_volume(struct snd_kcontrol *kcontrol,
1845                                  struct snd_ctl_elem_value *ucontrol)
1846 {
1847         struct cmipci *cm = snd_kcontrol_chip(kcontrol);
1848         struct cmipci_sb_reg reg;
1849         int val;
1850
1851         cmipci_sb_reg_decode(&reg, kcontrol->private_value);
1852         spin_lock_irq(&cm->reg_lock);
1853         val = (snd_cmipci_mixer_read(cm, reg.left_reg) >> reg.left_shift) & reg.mask;
1854         if (reg.invert)
1855                 val = reg.mask - val;
1856         ucontrol->value.integer.value[0] = val;
1857         if (reg.stereo) {
1858                 val = (snd_cmipci_mixer_read(cm, reg.right_reg) >> reg.right_shift) & reg.mask;
1859                 if (reg.invert)
1860                         val = reg.mask - val;
1861                  ucontrol->value.integer.value[1] = val;
1862         }
1863         spin_unlock_irq(&cm->reg_lock);
1864         return 0;
1865 }
1866
1867 static int snd_cmipci_put_volume(struct snd_kcontrol *kcontrol,
1868                                  struct snd_ctl_elem_value *ucontrol)
1869 {
1870         struct cmipci *cm = snd_kcontrol_chip(kcontrol);
1871         struct cmipci_sb_reg reg;
1872         int change;
1873         int left, right, oleft, oright;
1874
1875         cmipci_sb_reg_decode(&reg, kcontrol->private_value);
1876         left = ucontrol->value.integer.value[0] & reg.mask;
1877         if (reg.invert)
1878                 left = reg.mask - left;
1879         left <<= reg.left_shift;
1880         if (reg.stereo) {
1881                 right = ucontrol->value.integer.value[1] & reg.mask;
1882                 if (reg.invert)
1883                         right = reg.mask - right;
1884                 right <<= reg.right_shift;
1885         } else
1886                 right = 0;
1887         spin_lock_irq(&cm->reg_lock);
1888         oleft = snd_cmipci_mixer_read(cm, reg.left_reg);
1889         left |= oleft & ~(reg.mask << reg.left_shift);
1890         change = left != oleft;
1891         if (reg.stereo) {
1892                 if (reg.left_reg != reg.right_reg) {
1893                         snd_cmipci_mixer_write(cm, reg.left_reg, left);
1894                         oright = snd_cmipci_mixer_read(cm, reg.right_reg);
1895                 } else
1896                         oright = left;
1897                 right |= oright & ~(reg.mask << reg.right_shift);
1898                 change |= right != oright;
1899                 snd_cmipci_mixer_write(cm, reg.right_reg, right);
1900         } else
1901                 snd_cmipci_mixer_write(cm, reg.left_reg, left);
1902         spin_unlock_irq(&cm->reg_lock);
1903         return change;
1904 }
1905
1906 /*
1907  * input route (left,right) -> (left,right)
1908  */
1909 #define CMIPCI_SB_INPUT_SW(xname, left_shift, right_shift) \
1910 { .iface = SNDRV_CTL_ELEM_IFACE_MIXER, .name = xname, \
1911   .info = snd_cmipci_info_input_sw, \
1912   .get = snd_cmipci_get_input_sw, .put = snd_cmipci_put_input_sw, \
1913   .private_value = COMPOSE_SB_REG(SB_DSP4_INPUT_LEFT, SB_DSP4_INPUT_RIGHT, left_shift, right_shift, 1, 0, 1), \
1914 }
1915
1916 static int snd_cmipci_info_input_sw(struct snd_kcontrol *kcontrol,
1917                                     struct snd_ctl_elem_info *uinfo)
1918 {
1919         uinfo->type = SNDRV_CTL_ELEM_TYPE_BOOLEAN;
1920         uinfo->count = 4;
1921         uinfo->value.integer.min = 0;
1922         uinfo->value.integer.max = 1;
1923         return 0;
1924 }
1925  
1926 static int snd_cmipci_get_input_sw(struct snd_kcontrol *kcontrol,
1927                                    struct snd_ctl_elem_value *ucontrol)
1928 {
1929         struct cmipci *cm = snd_kcontrol_chip(kcontrol);
1930         struct cmipci_sb_reg reg;
1931         int val1, val2;
1932
1933         cmipci_sb_reg_decode(&reg, kcontrol->private_value);
1934         spin_lock_irq(&cm->reg_lock);
1935         val1 = snd_cmipci_mixer_read(cm, reg.left_reg);
1936         val2 = snd_cmipci_mixer_read(cm, reg.right_reg);
1937         spin_unlock_irq(&cm->reg_lock);
1938         ucontrol->value.integer.value[0] = (val1 >> reg.left_shift) & 1;
1939         ucontrol->value.integer.value[1] = (val2 >> reg.left_shift) & 1;
1940         ucontrol->value.integer.value[2] = (val1 >> reg.right_shift) & 1;
1941         ucontrol->value.integer.value[3] = (val2 >> reg.right_shift) & 1;
1942         return 0;
1943 }
1944
1945 static int snd_cmipci_put_input_sw(struct snd_kcontrol *kcontrol,
1946                                    struct snd_ctl_elem_value *ucontrol)
1947 {
1948         struct cmipci *cm = snd_kcontrol_chip(kcontrol);
1949         struct cmipci_sb_reg reg;
1950         int change;
1951         int val1, val2, oval1, oval2;
1952
1953         cmipci_sb_reg_decode(&reg, kcontrol->private_value);
1954         spin_lock_irq(&cm->reg_lock);
1955         oval1 = snd_cmipci_mixer_read(cm, reg.left_reg);
1956         oval2 = snd_cmipci_mixer_read(cm, reg.right_reg);
1957         val1 = oval1 & ~((1 << reg.left_shift) | (1 << reg.right_shift));
1958         val2 = oval2 & ~((1 << reg.left_shift) | (1 << reg.right_shift));
1959         val1 |= (ucontrol->value.integer.value[0] & 1) << reg.left_shift;
1960         val2 |= (ucontrol->value.integer.value[1] & 1) << reg.left_shift;
1961         val1 |= (ucontrol->value.integer.value[2] & 1) << reg.right_shift;
1962         val2 |= (ucontrol->value.integer.value[3] & 1) << reg.right_shift;
1963         change = val1 != oval1 || val2 != oval2;
1964         snd_cmipci_mixer_write(cm, reg.left_reg, val1);
1965         snd_cmipci_mixer_write(cm, reg.right_reg, val2);
1966         spin_unlock_irq(&cm->reg_lock);
1967         return change;
1968 }
1969
1970 /*
1971  * native mixer switches/volumes
1972  */
1973
1974 #define CMIPCI_MIXER_SW_STEREO(xname, reg, lshift, rshift, invert) \
1975 { .iface = SNDRV_CTL_ELEM_IFACE_MIXER, .name = xname, \
1976   .info = snd_cmipci_info_native_mixer, \
1977   .get = snd_cmipci_get_native_mixer, .put = snd_cmipci_put_native_mixer, \
1978   .private_value = COMPOSE_SB_REG(reg, reg, lshift, rshift, 1, invert, 1), \
1979 }
1980
1981 #define CMIPCI_MIXER_SW_MONO(xname, reg, shift, invert) \
1982 { .iface = SNDRV_CTL_ELEM_IFACE_MIXER, .name = xname, \
1983   .info = snd_cmipci_info_native_mixer, \
1984   .get = snd_cmipci_get_native_mixer, .put = snd_cmipci_put_native_mixer, \
1985   .private_value = COMPOSE_SB_REG(reg, reg, shift, shift, 1, invert, 0), \
1986 }
1987
1988 #define CMIPCI_MIXER_VOL_STEREO(xname, reg, lshift, rshift, mask) \
1989 { .iface = SNDRV_CTL_ELEM_IFACE_MIXER, .name = xname, \
1990   .info = snd_cmipci_info_native_mixer, \
1991   .get = snd_cmipci_get_native_mixer, .put = snd_cmipci_put_native_mixer, \
1992   .private_value = COMPOSE_SB_REG(reg, reg, lshift, rshift, mask, 0, 1), \
1993 }
1994
1995 #define CMIPCI_MIXER_VOL_MONO(xname, reg, shift, mask) \
1996 { .iface = SNDRV_CTL_ELEM_IFACE_MIXER, .name = xname, \
1997   .info = snd_cmipci_info_native_mixer, \
1998   .get = snd_cmipci_get_native_mixer, .put = snd_cmipci_put_native_mixer, \
1999   .private_value = COMPOSE_SB_REG(reg, reg, shift, shift, mask, 0, 0), \
2000 }
2001
2002 static int snd_cmipci_info_native_mixer(struct snd_kcontrol *kcontrol,
2003                                         struct snd_ctl_elem_info *uinfo)
2004 {
2005         struct cmipci_sb_reg reg;
2006
2007         cmipci_sb_reg_decode(&reg, kcontrol->private_value);
2008         uinfo->type = reg.mask == 1 ? SNDRV_CTL_ELEM_TYPE_BOOLEAN : SNDRV_CTL_ELEM_TYPE_INTEGER;
2009         uinfo->count = reg.stereo + 1;
2010         uinfo->value.integer.min = 0;
2011         uinfo->value.integer.max = reg.mask;
2012         return 0;
2013
2014 }
2015
2016 static int snd_cmipci_get_native_mixer(struct snd_kcontrol *kcontrol,
2017                                        struct snd_ctl_elem_value *ucontrol)
2018 {
2019         struct cmipci *cm = snd_kcontrol_chip(kcontrol);
2020         struct cmipci_sb_reg reg;
2021         unsigned char oreg, val;
2022
2023         cmipci_sb_reg_decode(&reg, kcontrol->private_value);
2024         spin_lock_irq(&cm->reg_lock);
2025         oreg = inb(cm->iobase + reg.left_reg);
2026         val = (oreg >> reg.left_shift) & reg.mask;
2027         if (reg.invert)
2028                 val = reg.mask - val;
2029         ucontrol->value.integer.value[0] = val;
2030         if (reg.stereo) {
2031                 val = (oreg >> reg.right_shift) & reg.mask;
2032                 if (reg.invert)
2033                         val = reg.mask - val;
2034                 ucontrol->value.integer.value[1] = val;
2035         }
2036         spin_unlock_irq(&cm->reg_lock);
2037         return 0;
2038 }
2039
2040 static int snd_cmipci_put_native_mixer(struct snd_kcontrol *kcontrol,
2041                                        struct snd_ctl_elem_value *ucontrol)
2042 {
2043         struct cmipci *cm = snd_kcontrol_chip(kcontrol);
2044         struct cmipci_sb_reg reg;
2045         unsigned char oreg, nreg, val;
2046
2047         cmipci_sb_reg_decode(&reg, kcontrol->private_value);
2048         spin_lock_irq(&cm->reg_lock);
2049         oreg = inb(cm->iobase + reg.left_reg);
2050         val = ucontrol->value.integer.value[0] & reg.mask;
2051         if (reg.invert)
2052                 val = reg.mask - val;
2053         nreg = oreg & ~(reg.mask << reg.left_shift);
2054         nreg |= (val << reg.left_shift);
2055         if (reg.stereo) {
2056                 val = ucontrol->value.integer.value[1] & reg.mask;
2057                 if (reg.invert)
2058                         val = reg.mask - val;
2059                 nreg &= ~(reg.mask << reg.right_shift);
2060                 nreg |= (val << reg.right_shift);
2061         }
2062         outb(nreg, cm->iobase + reg.left_reg);
2063         spin_unlock_irq(&cm->reg_lock);
2064         return (nreg != oreg);
2065 }
2066
2067 /*
2068  * special case - check mixer sensitivity
2069  */
2070 static int snd_cmipci_get_native_mixer_sensitive(struct snd_kcontrol *kcontrol,
2071                                                  struct snd_ctl_elem_value *ucontrol)
2072 {
2073         //struct cmipci *cm = snd_kcontrol_chip(kcontrol);
2074         return snd_cmipci_get_native_mixer(kcontrol, ucontrol);
2075 }
2076
2077 static int snd_cmipci_put_native_mixer_sensitive(struct snd_kcontrol *kcontrol,
2078                                                  struct snd_ctl_elem_value *ucontrol)
2079 {
2080         struct cmipci *cm = snd_kcontrol_chip(kcontrol);
2081         if (cm->mixer_insensitive) {
2082                 /* ignored */
2083                 return 0;
2084         }
2085         return snd_cmipci_put_native_mixer(kcontrol, ucontrol);
2086 }
2087
2088
2089 static struct snd_kcontrol_new snd_cmipci_mixers[] __devinitdata = {
2090         CMIPCI_SB_VOL_STEREO("Master Playback Volume", SB_DSP4_MASTER_DEV, 3, 31),
2091         CMIPCI_MIXER_SW_MONO("3D Control - Switch", CM_REG_MIXER1, CM_X3DEN_SHIFT, 0),
2092         CMIPCI_SB_VOL_STEREO("PCM Playback Volume", SB_DSP4_PCM_DEV, 3, 31),
2093         //CMIPCI_MIXER_SW_MONO("PCM Playback Switch", CM_REG_MIXER1, CM_WSMUTE_SHIFT, 1),
2094         { /* switch with sensitivity */
2095                 .iface = SNDRV_CTL_ELEM_IFACE_MIXER,
2096                 .name = "PCM Playback Switch",
2097                 .info = snd_cmipci_info_native_mixer,
2098                 .get = snd_cmipci_get_native_mixer_sensitive,
2099                 .put = snd_cmipci_put_native_mixer_sensitive,
2100                 .private_value = COMPOSE_SB_REG(CM_REG_MIXER1, CM_REG_MIXER1, CM_WSMUTE_SHIFT, CM_WSMUTE_SHIFT, 1, 1, 0),
2101         },
2102         CMIPCI_MIXER_SW_STEREO("PCM Capture Switch", CM_REG_MIXER1, CM_WAVEINL_SHIFT, CM_WAVEINR_SHIFT, 0),
2103         CMIPCI_SB_VOL_STEREO("Synth Playback Volume", SB_DSP4_SYNTH_DEV, 3, 31),
2104         CMIPCI_MIXER_SW_MONO("Synth Playback Switch", CM_REG_MIXER1, CM_FMMUTE_SHIFT, 1),
2105         CMIPCI_SB_INPUT_SW("Synth Capture Route", 6, 5),
2106         CMIPCI_SB_VOL_STEREO("CD Playback Volume", SB_DSP4_CD_DEV, 3, 31),
2107         CMIPCI_SB_SW_STEREO("CD Playback Switch", 2, 1),
2108         CMIPCI_SB_INPUT_SW("CD Capture Route", 2, 1),
2109         CMIPCI_SB_VOL_STEREO("Line Playback Volume", SB_DSP4_LINE_DEV, 3, 31),
2110         CMIPCI_SB_SW_STEREO("Line Playback Switch", 4, 3),
2111         CMIPCI_SB_INPUT_SW("Line Capture Route", 4, 3),
2112         CMIPCI_SB_VOL_MONO("Mic Playback Volume", SB_DSP4_MIC_DEV, 3, 31),
2113         CMIPCI_SB_SW_MONO("Mic Playback Switch", 0),
2114         CMIPCI_DOUBLE("Mic Capture Switch", SB_DSP4_INPUT_LEFT, SB_DSP4_INPUT_RIGHT, 0, 0, 1, 0, 0),
2115         CMIPCI_SB_VOL_MONO("PC Speaker Playback Volume", SB_DSP4_SPEAKER_DEV, 6, 3),
2116         CMIPCI_MIXER_VOL_STEREO("Aux Playback Volume", CM_REG_AUX_VOL, 4, 0, 15),
2117         CMIPCI_MIXER_SW_STEREO("Aux Playback Switch", CM_REG_MIXER2, CM_VAUXLM_SHIFT, CM_VAUXRM_SHIFT, 0),
2118         CMIPCI_MIXER_SW_STEREO("Aux Capture Switch", CM_REG_MIXER2, CM_RAUXLEN_SHIFT, CM_RAUXREN_SHIFT, 0),
2119         CMIPCI_MIXER_SW_MONO("Mic Boost Playback Switch", CM_REG_MIXER2, CM_MICGAINZ_SHIFT, 1),
2120         CMIPCI_MIXER_VOL_MONO("Mic Capture Volume", CM_REG_MIXER2, CM_VADMIC_SHIFT, 7),
2121         CMIPCI_SB_VOL_MONO("Phone Playback Volume", CM_REG_EXTENT_IND, 5, 7),
2122         CMIPCI_DOUBLE("Phone Playback Switch", CM_REG_EXTENT_IND, CM_REG_EXTENT_IND, 4, 4, 1, 0, 0),
2123         CMIPCI_DOUBLE("PC Speaker Playback Switch", CM_REG_EXTENT_IND, CM_REG_EXTENT_IND, 3, 3, 1, 0, 0),
2124         CMIPCI_DOUBLE("Mic Boost Capture Switch", CM_REG_EXTENT_IND, CM_REG_EXTENT_IND, 0, 0, 1, 0, 0),
2125 };
2126
2127 /*
2128  * other switches
2129  */
2130
2131 struct cmipci_switch_args {
2132         int reg;                /* register index */
2133         unsigned int mask;      /* mask bits */
2134         unsigned int mask_on;   /* mask bits to turn on */
2135         unsigned int is_byte: 1;                /* byte access? */
2136         unsigned int ac3_sensitive: 1;  /* access forbidden during
2137                                          * non-audio operation?
2138                                          */
2139 };
2140
2141 #define snd_cmipci_uswitch_info         snd_ctl_boolean_mono_info
2142
2143 static int _snd_cmipci_uswitch_get(struct snd_kcontrol *kcontrol,
2144                                    struct snd_ctl_elem_value *ucontrol,
2145                                    struct cmipci_switch_args *args)
2146 {
2147         unsigned int val;
2148         struct cmipci *cm = snd_kcontrol_chip(kcontrol);
2149
2150         spin_lock_irq(&cm->reg_lock);
2151         if (args->ac3_sensitive && cm->mixer_insensitive) {
2152                 ucontrol->value.integer.value[0] = 0;
2153                 spin_unlock_irq(&cm->reg_lock);
2154                 return 0;
2155         }
2156         if (args->is_byte)
2157                 val = inb(cm->iobase + args->reg);
2158         else
2159                 val = snd_cmipci_read(cm, args->reg);
2160         ucontrol->value.integer.value[0] = ((val & args->mask) == args->mask_on) ? 1 : 0;
2161         spin_unlock_irq(&cm->reg_lock);
2162         return 0;
2163 }
2164
2165 static int snd_cmipci_uswitch_get(struct snd_kcontrol *kcontrol,
2166                                   struct snd_ctl_elem_value *ucontrol)
2167 {
2168         struct cmipci_switch_args *args;
2169         args = (struct cmipci_switch_args *)kcontrol->private_value;
2170         snd_assert(args != NULL, return -EINVAL);
2171         return _snd_cmipci_uswitch_get(kcontrol, ucontrol, args);
2172 }
2173
2174 static int _snd_cmipci_uswitch_put(struct snd_kcontrol *kcontrol,
2175                                    struct snd_ctl_elem_value *ucontrol,
2176                                    struct cmipci_switch_args *args)
2177 {
2178         unsigned int val;
2179         int change;
2180         struct cmipci *cm = snd_kcontrol_chip(kcontrol);
2181
2182         spin_lock_irq(&cm->reg_lock);
2183         if (args->ac3_sensitive && cm->mixer_insensitive) {
2184                 /* ignored */
2185                 spin_unlock_irq(&cm->reg_lock);
2186                 return 0;
2187         }
2188         if (args->is_byte)
2189                 val = inb(cm->iobase + args->reg);
2190         else
2191                 val = snd_cmipci_read(cm, args->reg);
2192         change = (val & args->mask) != (ucontrol->value.integer.value[0] ? 
2193                         args->mask_on : (args->mask & ~args->mask_on));
2194         if (change) {
2195                 val &= ~args->mask;
2196                 if (ucontrol->value.integer.value[0])
2197                         val |= args->mask_on;
2198                 else
2199                         val |= (args->mask & ~args->mask_on);
2200                 if (args->is_byte)
2201                         outb((unsigned char)val, cm->iobase + args->reg);
2202                 else
2203                         snd_cmipci_write(cm, args->reg, val);
2204         }
2205         spin_unlock_irq(&cm->reg_lock);
2206         return change;
2207 }
2208
2209 static int snd_cmipci_uswitch_put(struct snd_kcontrol *kcontrol,
2210                                   struct snd_ctl_elem_value *ucontrol)
2211 {
2212         struct cmipci_switch_args *args;
2213         args = (struct cmipci_switch_args *)kcontrol->private_value;
2214         snd_assert(args != NULL, return -EINVAL);
2215         return _snd_cmipci_uswitch_put(kcontrol, ucontrol, args);
2216 }
2217
2218 #define DEFINE_SWITCH_ARG(sname, xreg, xmask, xmask_on, xis_byte, xac3) \
2219 static struct cmipci_switch_args cmipci_switch_arg_##sname = { \
2220   .reg = xreg, \
2221   .mask = xmask, \
2222   .mask_on = xmask_on, \
2223   .is_byte = xis_byte, \
2224   .ac3_sensitive = xac3, \
2225 }
2226         
2227 #define DEFINE_BIT_SWITCH_ARG(sname, xreg, xmask, xis_byte, xac3) \
2228         DEFINE_SWITCH_ARG(sname, xreg, xmask, xmask, xis_byte, xac3)
2229
2230 #if 0 /* these will be controlled in pcm device */
2231 DEFINE_BIT_SWITCH_ARG(spdif_in, CM_REG_FUNCTRL1, CM_SPDF_1, 0, 0);
2232 DEFINE_BIT_SWITCH_ARG(spdif_out, CM_REG_FUNCTRL1, CM_SPDF_0, 0, 0);
2233 #endif
2234 DEFINE_BIT_SWITCH_ARG(spdif_in_sel1, CM_REG_CHFORMAT, CM_SPDIF_SELECT1, 0, 0);
2235 DEFINE_BIT_SWITCH_ARG(spdif_in_sel2, CM_REG_MISC_CTRL, CM_SPDIF_SELECT2, 0, 0);
2236 DEFINE_BIT_SWITCH_ARG(spdif_enable, CM_REG_LEGACY_CTRL, CM_ENSPDOUT, 0, 0);
2237 DEFINE_BIT_SWITCH_ARG(spdo2dac, CM_REG_FUNCTRL1, CM_SPDO2DAC, 0, 1);
2238 DEFINE_BIT_SWITCH_ARG(spdi_valid, CM_REG_MISC, CM_SPDVALID, 1, 0);
2239 DEFINE_BIT_SWITCH_ARG(spdif_copyright, CM_REG_LEGACY_CTRL, CM_SPDCOPYRHT, 0, 0);
2240 DEFINE_BIT_SWITCH_ARG(spdif_dac_out, CM_REG_LEGACY_CTRL, CM_DAC2SPDO, 0, 1);
2241 DEFINE_SWITCH_ARG(spdo_5v, CM_REG_MISC_CTRL, CM_SPDO5V, 0, 0, 0); /* inverse: 0 = 5V */
2242 // DEFINE_BIT_SWITCH_ARG(spdo_48k, CM_REG_MISC_CTRL, CM_SPDF_AC97|CM_SPDIF48K, 0, 1);
2243 DEFINE_BIT_SWITCH_ARG(spdif_loop, CM_REG_FUNCTRL1, CM_SPDFLOOP, 0, 1);
2244 DEFINE_BIT_SWITCH_ARG(spdi_monitor, CM_REG_MIXER1, CM_CDPLAY, 1, 0);
2245 /* DEFINE_BIT_SWITCH_ARG(spdi_phase, CM_REG_CHFORMAT, CM_SPDIF_INVERSE, 0, 0); */
2246 DEFINE_BIT_SWITCH_ARG(spdi_phase, CM_REG_MISC, CM_SPDIF_INVERSE, 1, 0);
2247 DEFINE_BIT_SWITCH_ARG(spdi_phase2, CM_REG_CHFORMAT, CM_SPDIF_INVERSE2, 0, 0);
2248 #if CM_CH_PLAY == 1
2249 DEFINE_SWITCH_ARG(exchange_dac, CM_REG_MISC_CTRL, CM_XCHGDAC, 0, 0, 0); /* reversed */
2250 #else
2251 DEFINE_SWITCH_ARG(exchange_dac, CM_REG_MISC_CTRL, CM_XCHGDAC, CM_XCHGDAC, 0, 0);
2252 #endif
2253 DEFINE_BIT_SWITCH_ARG(fourch, CM_REG_MISC_CTRL, CM_N4SPK3D, 0, 0);
2254 // DEFINE_BIT_SWITCH_ARG(line_rear, CM_REG_MIXER1, CM_SPK4, 1, 0);
2255 // DEFINE_BIT_SWITCH_ARG(line_bass, CM_REG_LEGACY_CTRL, CM_LINE_AS_BASS, 0, 0);
2256 // DEFINE_BIT_SWITCH_ARG(joystick, CM_REG_FUNCTRL1, CM_JYSTK_EN, 0, 0); /* now module option */
2257 DEFINE_SWITCH_ARG(modem, CM_REG_MISC_CTRL, CM_FLINKON|CM_FLINKOFF, CM_FLINKON, 0, 0);
2258
2259 #define DEFINE_SWITCH(sname, stype, sarg) \
2260 { .name = sname, \
2261   .iface = stype, \
2262   .info = snd_cmipci_uswitch_info, \
2263   .get = snd_cmipci_uswitch_get, \
2264   .put = snd_cmipci_uswitch_put, \
2265   .private_value = (unsigned long)&cmipci_switch_arg_##sarg,\
2266 }
2267
2268 #define DEFINE_CARD_SWITCH(sname, sarg) DEFINE_SWITCH(sname, SNDRV_CTL_ELEM_IFACE_CARD, sarg)
2269 #define DEFINE_MIXER_SWITCH(sname, sarg) DEFINE_SWITCH(sname, SNDRV_CTL_ELEM_IFACE_MIXER, sarg)
2270
2271
2272 /*
2273  * callbacks for spdif output switch
2274  * needs toggle two registers..
2275  */
2276 static int snd_cmipci_spdout_enable_get(struct snd_kcontrol *kcontrol,
2277                                         struct snd_ctl_elem_value *ucontrol)
2278 {
2279         int changed;
2280         changed = _snd_cmipci_uswitch_get(kcontrol, ucontrol, &cmipci_switch_arg_spdif_enable);
2281         changed |= _snd_cmipci_uswitch_get(kcontrol, ucontrol, &cmipci_switch_arg_spdo2dac);
2282         return changed;
2283 }
2284
2285 static int snd_cmipci_spdout_enable_put(struct snd_kcontrol *kcontrol,
2286                                         struct snd_ctl_elem_value *ucontrol)
2287 {
2288         struct cmipci *chip = snd_kcontrol_chip(kcontrol);
2289         int changed;
2290         changed = _snd_cmipci_uswitch_put(kcontrol, ucontrol, &cmipci_switch_arg_spdif_enable);
2291         changed |= _snd_cmipci_uswitch_put(kcontrol, ucontrol, &cmipci_switch_arg_spdo2dac);
2292         if (changed) {
2293                 if (ucontrol->value.integer.value[0]) {
2294                         if (chip->spdif_playback_avail)
2295                                 snd_cmipci_set_bit(chip, CM_REG_FUNCTRL1, CM_PLAYBACK_SPDF);
2296                 } else {
2297                         if (chip->spdif_playback_avail)
2298                                 snd_cmipci_clear_bit(chip, CM_REG_FUNCTRL1, CM_PLAYBACK_SPDF);
2299                 }
2300         }
2301         chip->spdif_playback_enabled = ucontrol->value.integer.value[0];
2302         return changed;
2303 }
2304
2305
2306 static int snd_cmipci_line_in_mode_info(struct snd_kcontrol *kcontrol,
2307                                         struct snd_ctl_elem_info *uinfo)
2308 {
2309         struct cmipci *cm = snd_kcontrol_chip(kcontrol);
2310         static char *texts[3] = { "Line-In", "Rear Output", "Bass Output" };
2311         uinfo->type = SNDRV_CTL_ELEM_TYPE_ENUMERATED;
2312         uinfo->count = 1;
2313         uinfo->value.enumerated.items = cm->chip_version >= 39 ? 3 : 2;
2314         if (uinfo->value.enumerated.item >= uinfo->value.enumerated.items)
2315                 uinfo->value.enumerated.item = uinfo->value.enumerated.items - 1;
2316         strcpy(uinfo->value.enumerated.name, texts[uinfo->value.enumerated.item]);
2317         return 0;
2318 }
2319
2320 static inline unsigned int get_line_in_mode(struct cmipci *cm)
2321 {
2322         unsigned int val;
2323         if (cm->chip_version >= 39) {
2324                 val = snd_cmipci_read(cm, CM_REG_LEGACY_CTRL);
2325                 if (val & CM_LINE_AS_BASS)
2326                         return 2;
2327         }
2328         val = snd_cmipci_read_b(cm, CM_REG_MIXER1);
2329         if (val & CM_SPK4)
2330                 return 1;
2331         return 0;
2332 }
2333
2334 static int snd_cmipci_line_in_mode_get(struct snd_kcontrol *kcontrol,
2335                                        struct snd_ctl_elem_value *ucontrol)
2336 {
2337         struct cmipci *cm = snd_kcontrol_chip(kcontrol);
2338
2339         spin_lock_irq(&cm->reg_lock);
2340         ucontrol->value.enumerated.item[0] = get_line_in_mode(cm);
2341         spin_unlock_irq(&cm->reg_lock);
2342         return 0;
2343 }
2344
2345 static int snd_cmipci_line_in_mode_put(struct snd_kcontrol *kcontrol,
2346                                        struct snd_ctl_elem_value *ucontrol)
2347 {
2348         struct cmipci *cm = snd_kcontrol_chip(kcontrol);
2349         int change;
2350
2351         spin_lock_irq(&cm->reg_lock);
2352         if (ucontrol->value.enumerated.item[0] == 2)
2353                 change = snd_cmipci_set_bit(cm, CM_REG_LEGACY_CTRL, CM_LINE_AS_BASS);
2354         else
2355                 change = snd_cmipci_clear_bit(cm, CM_REG_LEGACY_CTRL, CM_LINE_AS_BASS);
2356         if (ucontrol->value.enumerated.item[0] == 1)
2357                 change |= snd_cmipci_set_bit_b(cm, CM_REG_MIXER1, CM_SPK4);
2358         else
2359                 change |= snd_cmipci_clear_bit_b(cm, CM_REG_MIXER1, CM_SPK4);
2360         spin_unlock_irq(&cm->reg_lock);
2361         return change;
2362 }
2363
2364 static int snd_cmipci_mic_in_mode_info(struct snd_kcontrol *kcontrol,
2365                                        struct snd_ctl_elem_info *uinfo)
2366 {
2367         static char *texts[2] = { "Mic-In", "Center/LFE Output" };
2368         uinfo->type = SNDRV_CTL_ELEM_TYPE_ENUMERATED;
2369         uinfo->count = 1;
2370         uinfo->value.enumerated.items = 2;
2371         if (uinfo->value.enumerated.item >= uinfo->value.enumerated.items)
2372                 uinfo->value.enumerated.item = uinfo->value.enumerated.items - 1;
2373         strcpy(uinfo->value.enumerated.name, texts[uinfo->value.enumerated.item]);
2374         return 0;
2375 }
2376
2377 static int snd_cmipci_mic_in_mode_get(struct snd_kcontrol *kcontrol,
2378                                       struct snd_ctl_elem_value *ucontrol)
2379 {
2380         struct cmipci *cm = snd_kcontrol_chip(kcontrol);
2381         /* same bit as spdi_phase */
2382         spin_lock_irq(&cm->reg_lock);
2383         ucontrol->value.enumerated.item[0] = 
2384                 (snd_cmipci_read_b(cm, CM_REG_MISC) & CM_SPDIF_INVERSE) ? 1 : 0;
2385         spin_unlock_irq(&cm->reg_lock);
2386         return 0;
2387 }
2388
2389 static int snd_cmipci_mic_in_mode_put(struct snd_kcontrol *kcontrol,
2390                                       struct snd_ctl_elem_value *ucontrol)
2391 {
2392         struct cmipci *cm = snd_kcontrol_chip(kcontrol);
2393         int change;
2394
2395         spin_lock_irq(&cm->reg_lock);
2396         if (ucontrol->value.enumerated.item[0])
2397                 change = snd_cmipci_set_bit_b(cm, CM_REG_MISC, CM_SPDIF_INVERSE);
2398         else
2399                 change = snd_cmipci_clear_bit_b(cm, CM_REG_MISC, CM_SPDIF_INVERSE);
2400         spin_unlock_irq(&cm->reg_lock);
2401         return change;
2402 }
2403
2404 /* both for CM8338/8738 */
2405 static struct snd_kcontrol_new snd_cmipci_mixer_switches[] __devinitdata = {
2406         DEFINE_MIXER_SWITCH("Four Channel Mode", fourch),
2407         {
2408                 .name = "Line-In Mode",
2409                 .iface = SNDRV_CTL_ELEM_IFACE_MIXER,
2410                 .info = snd_cmipci_line_in_mode_info,
2411                 .get = snd_cmipci_line_in_mode_get,
2412                 .put = snd_cmipci_line_in_mode_put,
2413         },
2414 };
2415
2416 /* for non-multichannel chips */
2417 static struct snd_kcontrol_new snd_cmipci_nomulti_switch __devinitdata =
2418 DEFINE_MIXER_SWITCH("Exchange DAC", exchange_dac);
2419
2420 /* only for CM8738 */
2421 static struct snd_kcontrol_new snd_cmipci_8738_mixer_switches[] __devinitdata = {
2422 #if 0 /* controlled in pcm device */
2423         DEFINE_MIXER_SWITCH("IEC958 In Record", spdif_in),
2424         DEFINE_MIXER_SWITCH("IEC958 Out", spdif_out),
2425         DEFINE_MIXER_SWITCH("IEC958 Out To DAC", spdo2dac),
2426 #endif
2427         // DEFINE_MIXER_SWITCH("IEC958 Output Switch", spdif_enable),
2428         { .name = "IEC958 Output Switch",
2429           .iface = SNDRV_CTL_ELEM_IFACE_MIXER,
2430           .info = snd_cmipci_uswitch_info,
2431           .get = snd_cmipci_spdout_enable_get,
2432           .put = snd_cmipci_spdout_enable_put,
2433         },
2434         DEFINE_MIXER_SWITCH("IEC958 In Valid", spdi_valid),
2435         DEFINE_MIXER_SWITCH("IEC958 Copyright", spdif_copyright),
2436         DEFINE_MIXER_SWITCH("IEC958 5V", spdo_5v),
2437 //      DEFINE_MIXER_SWITCH("IEC958 In/Out 48KHz", spdo_48k),
2438         DEFINE_MIXER_SWITCH("IEC958 Loop", spdif_loop),
2439         DEFINE_MIXER_SWITCH("IEC958 In Monitor", spdi_monitor),
2440 };
2441
2442 /* only for model 033/037 */
2443 static struct snd_kcontrol_new snd_cmipci_old_mixer_switches[] __devinitdata = {
2444         DEFINE_MIXER_SWITCH("IEC958 Mix Analog", spdif_dac_out),
2445         DEFINE_MIXER_SWITCH("IEC958 In Phase Inverse", spdi_phase),
2446         DEFINE_MIXER_SWITCH("IEC958 In Select", spdif_in_sel1),
2447 };
2448
2449 /* only for model 039 or later */
2450 static struct snd_kcontrol_new snd_cmipci_extra_mixer_switches[] __devinitdata = {
2451         DEFINE_MIXER_SWITCH("IEC958 In Select", spdif_in_sel2),
2452         DEFINE_MIXER_SWITCH("IEC958 In Phase Inverse", spdi_phase2),
2453         {
2454                 .name = "Mic-In Mode",
2455                 .iface = SNDRV_CTL_ELEM_IFACE_MIXER,
2456                 .info = snd_cmipci_mic_in_mode_info,
2457                 .get = snd_cmipci_mic_in_mode_get,
2458                 .put = snd_cmipci_mic_in_mode_put,
2459         }
2460 };
2461
2462 /* card control switches */
2463 static struct snd_kcontrol_new snd_cmipci_control_switches[] __devinitdata = {
2464         // DEFINE_CARD_SWITCH("Joystick", joystick), /* now module option */
2465         DEFINE_CARD_SWITCH("Modem", modem),
2466 };
2467
2468
2469 static int __devinit snd_cmipci_mixer_new(struct cmipci *cm, int pcm_spdif_device)
2470 {
2471         struct snd_card *card;
2472         struct snd_kcontrol_new *sw;
2473         struct snd_kcontrol *kctl;
2474         unsigned int idx;
2475         int err;
2476
2477         snd_assert(cm != NULL && cm->card != NULL, return -EINVAL);
2478
2479         card = cm->card;
2480
2481         strcpy(card->mixername, "CMedia PCI");
2482
2483         spin_lock_irq(&cm->reg_lock);
2484         snd_cmipci_mixer_write(cm, 0x00, 0x00);         /* mixer reset */
2485         spin_unlock_irq(&cm->reg_lock);
2486
2487         for (idx = 0; idx < ARRAY_SIZE(snd_cmipci_mixers); idx++) {
2488                 if (cm->chip_version == 68) {   // 8768 has no PCM volume
2489                         if (!strcmp(snd_cmipci_mixers[idx].name,
2490                                 "PCM Playback Volume"))
2491                                 continue;
2492                 }
2493                 if ((err = snd_ctl_add(card, snd_ctl_new1(&snd_cmipci_mixers[idx], cm))) < 0)
2494                         return err;
2495         }
2496
2497         /* mixer switches */
2498         sw = snd_cmipci_mixer_switches;
2499         for (idx = 0; idx < ARRAY_SIZE(snd_cmipci_mixer_switches); idx++, sw++) {
2500                 err = snd_ctl_add(cm->card, snd_ctl_new1(sw, cm));
2501                 if (err < 0)
2502                         return err;
2503         }
2504         if (! cm->can_multi_ch) {
2505                 err = snd_ctl_add(cm->card, snd_ctl_new1(&snd_cmipci_nomulti_switch, cm));
2506                 if (err < 0)
2507                         return err;
2508         }
2509         if (cm->device == PCI_DEVICE_ID_CMEDIA_CM8738 ||
2510             cm->device == PCI_DEVICE_ID_CMEDIA_CM8738B) {
2511                 sw = snd_cmipci_8738_mixer_switches;
2512                 for (idx = 0; idx < ARRAY_SIZE(snd_cmipci_8738_mixer_switches); idx++, sw++) {
2513                         err = snd_ctl_add(cm->card, snd_ctl_new1(sw, cm));
2514                         if (err < 0)
2515                                 return err;
2516                 }
2517                 if (cm->can_ac3_hw) {
2518                         if ((err = snd_ctl_add(card, kctl = snd_ctl_new1(&snd_cmipci_spdif_default, cm))) < 0)
2519                                 return err;
2520                         kctl->id.device = pcm_spdif_device;
2521                         if ((err = snd_ctl_add(card, kctl = snd_ctl_new1(&snd_cmipci_spdif_mask, cm))) < 0)
2522                                 return err;
2523                         kctl->id.device = pcm_spdif_device;
2524                         if ((err = snd_ctl_add(card, kctl = snd_ctl_new1(&snd_cmipci_spdif_stream, cm))) < 0)
2525                                 return err;
2526                         kctl->id.device = pcm_spdif_device;
2527                 }
2528                 if (cm->chip_version <= 37) {
2529                         sw = snd_cmipci_old_mixer_switches;
2530                         for (idx = 0; idx < ARRAY_SIZE(snd_cmipci_old_mixer_switches); idx++, sw++) {
2531                                 err = snd_ctl_add(cm->card, snd_ctl_new1(sw, cm));
2532                                 if (err < 0)
2533                                         return err;
2534                         }
2535                 }
2536         }
2537         if (cm->chip_version >= 39) {
2538                 sw = snd_cmipci_extra_mixer_switches;
2539                 for (idx = 0; idx < ARRAY_SIZE(snd_cmipci_extra_mixer_switches); idx++, sw++) {
2540                         err = snd_ctl_add(cm->card, snd_ctl_new1(sw, cm));
2541                         if (err < 0)
2542                                 return err;
2543                 }
2544         }
2545
2546         /* card switches */
2547         sw = snd_cmipci_control_switches;
2548         for (idx = 0; idx < ARRAY_SIZE(snd_cmipci_control_switches); idx++, sw++) {
2549                 err = snd_ctl_add(cm->card, snd_ctl_new1(sw, cm));
2550                 if (err < 0)
2551                         return err;
2552         }
2553
2554         for (idx = 0; idx < CM_SAVED_MIXERS; idx++) {
2555                 struct snd_ctl_elem_id id;
2556                 struct snd_kcontrol *ctl;
2557                 memset(&id, 0, sizeof(id));
2558                 id.iface = SNDRV_CTL_ELEM_IFACE_MIXER;
2559                 strcpy(id.name, cm_saved_mixer[idx].name);
2560                 if ((ctl = snd_ctl_find_id(cm->card, &id)) != NULL)
2561                         cm->mixer_res_ctl[idx] = ctl;
2562         }
2563
2564         return 0;
2565 }
2566
2567
2568 /*
2569  * proc interface
2570  */
2571
2572 #ifdef CONFIG_PROC_FS
2573 static void snd_cmipci_proc_read(struct snd_info_entry *entry, 
2574                                  struct snd_info_buffer *buffer)
2575 {
2576         struct cmipci *cm = entry->private_data;
2577         int i;
2578         
2579         snd_iprintf(buffer, "%s\n\n", cm->card->longname);
2580         for (i = 0; i < 0x40; i++) {
2581                 int v = inb(cm->iobase + i);
2582                 if (i % 4 == 0)
2583                         snd_iprintf(buffer, "%02x: ", i);
2584                 snd_iprintf(buffer, "%02x", v);
2585                 if (i % 4 == 3)
2586                         snd_iprintf(buffer, "\n");
2587                 else
2588                         snd_iprintf(buffer, " ");
2589         }
2590 }
2591
2592 static void __devinit snd_cmipci_proc_init(struct cmipci *cm)
2593 {
2594         struct snd_info_entry *entry;
2595
2596         if (! snd_card_proc_new(cm->card, "cmipci", &entry))
2597                 snd_info_set_text_ops(entry, cm, snd_cmipci_proc_read);
2598 }
2599 #else /* !CONFIG_PROC_FS */
2600 static inline void snd_cmipci_proc_init(struct cmipci *cm) {}
2601 #endif
2602
2603
2604 static struct pci_device_id snd_cmipci_ids[] = {
2605         {PCI_VENDOR_ID_CMEDIA, PCI_DEVICE_ID_CMEDIA_CM8338A, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
2606         {PCI_VENDOR_ID_CMEDIA, PCI_DEVICE_ID_CMEDIA_CM8338B, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
2607         {PCI_VENDOR_ID_CMEDIA, PCI_DEVICE_ID_CMEDIA_CM8738, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
2608         {PCI_VENDOR_ID_CMEDIA, PCI_DEVICE_ID_CMEDIA_CM8738B, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
2609         {PCI_VENDOR_ID_AL, PCI_DEVICE_ID_CMEDIA_CM8738, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
2610         {0,},
2611 };
2612
2613
2614 /*
2615  * check chip version and capabilities
2616  * driver name is modified according to the chip model
2617  */
2618 static void __devinit query_chip(struct cmipci *cm)
2619 {
2620         unsigned int detect;
2621
2622         /* check reg 0Ch, bit 24-31 */
2623         detect = snd_cmipci_read(cm, CM_REG_INT_HLDCLR) & CM_CHIP_MASK2;
2624         if (! detect) {
2625                 /* check reg 08h, bit 24-28 */
2626                 detect = snd_cmipci_read(cm, CM_REG_CHFORMAT) & CM_CHIP_MASK1;
2627                 switch (detect) {
2628                 case 0:
2629                         cm->chip_version = 33;
2630                         if (cm->do_soft_ac3)
2631                                 cm->can_ac3_sw = 1;
2632                         else
2633                                 cm->can_ac3_hw = 1;
2634                         break;
2635                 case 1:
2636                         cm->chip_version = 37;
2637                         cm->can_ac3_hw = 1;
2638                         break;
2639                 default:
2640                         cm->chip_version = 39;
2641                         cm->can_ac3_hw = 1;
2642                         break;
2643                 }
2644                 cm->max_channels = 2;
2645         } else {
2646                 if (detect & CM_CHIP_039) {
2647                         cm->chip_version = 39;
2648                         if (detect & CM_CHIP_039_6CH) /* 4 or 6 channels */
2649                                 cm->max_channels = 6;
2650                         else
2651                                 cm->max_channels = 4;
2652                 } else if (detect & CM_CHIP_8768) {
2653                         cm->chip_version = 68;
2654                         cm->max_channels = 8;
2655                 } else {
2656                         cm->chip_version = 55;
2657                         cm->max_channels = 6;
2658                 }
2659                 cm->can_ac3_hw = 1;
2660                 cm->can_multi_ch = 1;
2661         }
2662 }
2663
2664 #ifdef SUPPORT_JOYSTICK
2665 static int __devinit snd_cmipci_create_gameport(struct cmipci *cm, int dev)
2666 {
2667         static int ports[] = { 0x201, 0x200, 0 }; /* FIXME: majority is 0x201? */
2668         struct gameport *gp;
2669         struct resource *r = NULL;
2670         int i, io_port = 0;
2671
2672         if (joystick_port[dev] == 0)
2673                 return -ENODEV;
2674
2675         if (joystick_port[dev] == 1) { /* auto-detect */
2676                 for (i = 0; ports[i]; i++) {
2677                         io_port = ports[i];
2678                         r = request_region(io_port, 1, "CMIPCI gameport");
2679                         if (r)
2680                                 break;
2681                 }
2682         } else {
2683                 io_port = joystick_port[dev];
2684                 r = request_region(io_port, 1, "CMIPCI gameport");
2685         }
2686
2687         if (!r) {
2688                 printk(KERN_WARNING "cmipci: cannot reserve joystick ports\n");
2689                 return -EBUSY;
2690         }
2691
2692         cm->gameport = gp = gameport_allocate_port();
2693         if (!gp) {
2694                 printk(KERN_ERR "cmipci: cannot allocate memory for gameport\n");
2695                 release_and_free_resource(r);
2696                 return -ENOMEM;
2697         }
2698         gameport_set_name(gp, "C-Media Gameport");
2699         gameport_set_phys(gp, "pci%s/gameport0", pci_name(cm->pci));
2700         gameport_set_dev_parent(gp, &cm->pci->dev);
2701         gp->io = io_port;
2702         gameport_set_port_data(gp, r);
2703
2704         snd_cmipci_set_bit(cm, CM_REG_FUNCTRL1, CM_JYSTK_EN);
2705
2706         gameport_register_port(cm->gameport);
2707
2708         return 0;
2709 }
2710
2711 static void snd_cmipci_free_gameport(struct cmipci *cm)
2712 {
2713         if (cm->gameport) {
2714                 struct resource *r = gameport_get_port_data(cm->gameport);
2715
2716                 gameport_unregister_port(cm->gameport);
2717                 cm->gameport = NULL;
2718
2719                 snd_cmipci_clear_bit(cm, CM_REG_FUNCTRL1, CM_JYSTK_EN);
2720                 release_and_free_resource(r);
2721         }
2722 }
2723 #else
2724 static inline int snd_cmipci_create_gameport(struct cmipci *cm, int dev) { return -ENOSYS; }
2725 static inline void snd_cmipci_free_gameport(struct cmipci *cm) { }
2726 #endif
2727
2728 static int snd_cmipci_free(struct cmipci *cm)
2729 {
2730         if (cm->irq >= 0) {
2731                 snd_cmipci_clear_bit(cm, CM_REG_MISC_CTRL, CM_FM_EN);
2732                 snd_cmipci_clear_bit(cm, CM_REG_LEGACY_CTRL, CM_ENSPDOUT);
2733                 snd_cmipci_write(cm, CM_REG_INT_HLDCLR, 0);  /* disable ints */
2734                 snd_cmipci_ch_reset(cm, CM_CH_PLAY);
2735                 snd_cmipci_ch_reset(cm, CM_CH_CAPT);
2736                 snd_cmipci_write(cm, CM_REG_FUNCTRL0, 0); /* disable channels */
2737                 snd_cmipci_write(cm, CM_REG_FUNCTRL1, 0);
2738
2739                 /* reset mixer */
2740                 snd_cmipci_mixer_write(cm, 0, 0);
2741
2742                 synchronize_irq(cm->irq);
2743
2744                 free_irq(cm->irq, cm);
2745         }
2746
2747         snd_cmipci_free_gameport(cm);
2748         pci_release_regions(cm->pci);
2749         pci_disable_device(cm->pci);
2750         kfree(cm);
2751         return 0;
2752 }
2753
2754 static int snd_cmipci_dev_free(struct snd_device *device)
2755 {
2756         struct cmipci *cm = device->device_data;
2757         return snd_cmipci_free(cm);
2758 }
2759
2760 static int __devinit snd_cmipci_create_fm(struct cmipci *cm, long fm_port)
2761 {
2762         long iosynth;
2763         unsigned int val;
2764         struct snd_opl3 *opl3;
2765         int err;
2766
2767         if (!fm_port)
2768                 goto disable_fm;
2769
2770         if (cm->chip_version > 33) {
2771                 /* first try FM regs in PCI port range */
2772                 iosynth = cm->iobase + CM_REG_FM_PCI;
2773                 err = snd_opl3_create(cm->card, iosynth, iosynth + 2,
2774                                       OPL3_HW_OPL3, 1, &opl3);
2775         } else {
2776                 err = -EIO;
2777         }
2778         if (err < 0) {
2779                 /* then try legacy ports */
2780                 val = snd_cmipci_read(cm, CM_REG_LEGACY_CTRL) & ~CM_FMSEL_MASK;
2781                 iosynth = fm_port;
2782                 switch (iosynth) {
2783                 case 0x3E8: val |= CM_FMSEL_3E8; break;
2784                 case 0x3E0: val |= CM_FMSEL_3E0; break;
2785                 case 0x3C8: val |= CM_FMSEL_3C8; break;
2786                 case 0x388: val |= CM_FMSEL_388; break;
2787                 default:
2788                         goto disable_fm;
2789                 }
2790                 snd_cmipci_write(cm, CM_REG_LEGACY_CTRL, val);
2791                 /* enable FM */
2792                 snd_cmipci_set_bit(cm, CM_REG_MISC_CTRL, CM_FM_EN);
2793
2794                 if (snd_opl3_create(cm->card, iosynth, iosynth + 2,
2795                                     OPL3_HW_OPL3, 0, &opl3) < 0) {
2796                         printk(KERN_ERR "cmipci: no OPL device at %#lx, "
2797                                "skipping...\n", iosynth);
2798                         goto disable_fm;
2799                 }
2800         }
2801         if ((err = snd_opl3_hwdep_new(opl3, 0, 1, NULL)) < 0) {
2802                 printk(KERN_ERR "cmipci: cannot create OPL3 hwdep\n");
2803                 return err;
2804         }
2805         return 0;
2806
2807  disable_fm:
2808         snd_cmipci_clear_bit(cm, CM_REG_LEGACY_CTRL, CM_FMSEL_MASK);
2809         snd_cmipci_clear_bit(cm, CM_REG_MISC_CTRL, CM_FM_EN);
2810         return 0;
2811 }
2812
2813 static int __devinit snd_cmipci_create(struct snd_card *card, struct pci_dev *pci,
2814                                        int dev, struct cmipci **rcmipci)
2815 {
2816         struct cmipci *cm;
2817         int err;
2818         static struct snd_device_ops ops = {
2819                 .dev_free =     snd_cmipci_dev_free,
2820         };
2821         unsigned int val;
2822         long iomidi;
2823         int integrated_midi = 0;
2824         int pcm_index, pcm_spdif_index;
2825         static struct pci_device_id intel_82437vx[] = {
2826                 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82437VX) },
2827                 { },
2828         };
2829
2830         *rcmipci = NULL;
2831
2832         if ((err = pci_enable_device(pci)) < 0)
2833                 return err;
2834
2835         cm = kzalloc(sizeof(*cm), GFP_KERNEL);
2836         if (cm == NULL) {
2837                 pci_disable_device(pci);
2838                 return -ENOMEM;
2839         }
2840
2841         spin_lock_init(&cm->reg_lock);
2842         mutex_init(&cm->open_mutex);
2843         cm->device = pci->device;
2844         cm->card = card;
2845         cm->pci = pci;
2846         cm->irq = -1;
2847         cm->channel[0].ch = 0;
2848         cm->channel[1].ch = 1;
2849         cm->channel[0].is_dac = cm->channel[1].is_dac = 1; /* dual DAC mode */
2850
2851         if ((err = pci_request_regions(pci, card->driver)) < 0) {
2852                 kfree(cm);
2853                 pci_disable_device(pci);
2854                 return err;
2855         }
2856         cm->iobase = pci_resource_start(pci, 0);
2857
2858         if (request_irq(pci->irq, snd_cmipci_interrupt,
2859                         IRQF_SHARED, card->driver, cm)) {
2860                 snd_printk(KERN_ERR "unable to grab IRQ %d\n", pci->irq);
2861                 snd_cmipci_free(cm);
2862                 return -EBUSY;
2863         }
2864         cm->irq = pci->irq;
2865
2866         pci_set_master(cm->pci);
2867
2868         /*
2869          * check chip version, max channels and capabilities
2870          */
2871
2872         cm->chip_version = 0;
2873         cm->max_channels = 2;
2874         cm->do_soft_ac3 = soft_ac3[dev];
2875
2876         if (pci->device != PCI_DEVICE_ID_CMEDIA_CM8338A &&
2877             pci->device != PCI_DEVICE_ID_CMEDIA_CM8338B)
2878                 query_chip(cm);
2879         /* added -MCx suffix for chip supporting multi-channels */
2880         if (cm->can_multi_ch)
2881                 sprintf(cm->card->driver + strlen(cm->card->driver),
2882                         "-MC%d", cm->max_channels);
2883         else if (cm->can_ac3_sw)
2884                 strcpy(cm->card->driver + strlen(cm->card->driver), "-SWIEC");
2885
2886         cm->dig_status = SNDRV_PCM_DEFAULT_CON_SPDIF;
2887         cm->dig_pcm_status = SNDRV_PCM_DEFAULT_CON_SPDIF;
2888
2889 #if CM_CH_PLAY == 1
2890         cm->ctrl = CM_CHADC0;   /* default FUNCNTRL0 */
2891 #else
2892         cm->ctrl = CM_CHADC1;   /* default FUNCNTRL0 */
2893 #endif
2894
2895         /* initialize codec registers */
2896         snd_cmipci_write(cm, CM_REG_INT_HLDCLR, 0);     /* disable ints */
2897         snd_cmipci_ch_reset(cm, CM_CH_PLAY);
2898         snd_cmipci_ch_reset(cm, CM_CH_CAPT);
2899         snd_cmipci_write(cm, CM_REG_FUNCTRL0, 0);       /* disable channels */
2900         snd_cmipci_write(cm, CM_REG_FUNCTRL1, 0);
2901
2902         snd_cmipci_write(cm, CM_REG_CHFORMAT, 0);
2903         snd_cmipci_set_bit(cm, CM_REG_MISC_CTRL, CM_ENDBDAC|CM_N4SPK3D);
2904 #if CM_CH_PLAY == 1
2905         snd_cmipci_set_bit(cm, CM_REG_MISC_CTRL, CM_XCHGDAC);
2906 #else
2907         snd_cmipci_clear_bit(cm, CM_REG_MISC_CTRL, CM_XCHGDAC);
2908 #endif
2909         /* Set Bus Master Request */
2910         snd_cmipci_set_bit(cm, CM_REG_FUNCTRL1, CM_BREQ);
2911
2912         /* Assume TX and compatible chip set (Autodetection required for VX chip sets) */
2913         switch (pci->device) {
2914         case PCI_DEVICE_ID_CMEDIA_CM8738:
2915         case PCI_DEVICE_ID_CMEDIA_CM8738B:
2916                 if (!pci_dev_present(intel_82437vx)) 
2917                         snd_cmipci_set_bit(cm, CM_REG_MISC_CTRL, CM_TXVX);
2918                 break;
2919         default:
2920                 break;
2921         }
2922
2923         sprintf(card->shortname, "C-Media %s", card->driver);
2924         if (cm->chip_version < 68) {
2925                 val = pci->device < 0x110 ? 8338 : 8738;
2926                 sprintf(card->longname,
2927                         "C-Media CMI%d (model %d) at 0x%lx, irq %i",
2928                         val, cm->chip_version, cm->iobase, cm->irq);
2929         } else {
2930                 switch (snd_cmipci_read_b(cm, CM_REG_INT_HLDCLR + 3) & 0x03) {
2931                 case 0:
2932                         val = 8769;
2933                         break;
2934                 case 2:
2935                         val = 8762;
2936                         break;
2937                 default:
2938                         switch ((pci->subsystem_vendor << 16) |
2939                                 pci->subsystem_device) {
2940                         case 0x13f69761:
2941                         case 0x584d3741:
2942                         case 0x584d3751:
2943                         case 0x584d3761:
2944                         case 0x584d3771:
2945                         case 0x72848384:
2946                                 val = 8770;
2947                                 break;
2948                         default:
2949                                 val = 8768;
2950                                 break;
2951                         }
2952                 }
2953                 sprintf(card->longname, "C-Media CMI%d at 0x%lx, irq %i",
2954                         val, cm->iobase, cm->irq);
2955         }
2956
2957         if ((err = snd_device_new(card, SNDRV_DEV_LOWLEVEL, cm, &ops)) < 0) {
2958                 snd_cmipci_free(cm);
2959                 return err;
2960         }
2961
2962         val = 0;
2963         if (cm->chip_version > 33 && mpu_port[dev] == 1) {
2964                 val = snd_cmipci_read_b(cm, CM_REG_MPU_PCI + 1);
2965                 if (val != 0x00 && val != 0xff) {
2966                         iomidi = cm->iobase + CM_REG_MPU_PCI;
2967                         integrated_midi = 1;
2968                 }
2969         }
2970         if (!integrated_midi) {
2971                 iomidi = mpu_port[dev];
2972                 switch (iomidi) {
2973                 case 0x320: val = CM_VMPU_320; break;
2974                 case 0x310: val = CM_VMPU_310; break;
2975                 case 0x300: val = CM_VMPU_300; break;
2976                 case 0x330: val = CM_VMPU_330; break;
2977                 default:
2978                             iomidi = 0; break;
2979                 }
2980                 if (iomidi > 0) {
2981                         snd_cmipci_write(cm, CM_REG_LEGACY_CTRL, val);
2982                         /* enable UART */
2983                         snd_cmipci_set_bit(cm, CM_REG_FUNCTRL1, CM_UART_EN);
2984                 }
2985         }
2986
2987         if (cm->chip_version < 68) {
2988                 err = snd_cmipci_create_fm(cm, fm_port[dev]);
2989                 if (err < 0)
2990                         return err;
2991         }
2992
2993         /* reset mixer */
2994         snd_cmipci_mixer_write(cm, 0, 0);
2995
2996         snd_cmipci_proc_init(cm);
2997
2998         /* create pcm devices */
2999         pcm_index = pcm_spdif_index = 0;
3000         if ((err = snd_cmipci_pcm_new(cm, pcm_index)) < 0)
3001                 return err;
3002         pcm_index++;
3003         if ((err = snd_cmipci_pcm2_new(cm, pcm_index)) < 0)
3004                 return err;
3005         pcm_index++;
3006         if (cm->can_ac3_hw || cm->can_ac3_sw) {
3007                 pcm_spdif_index = pcm_index;
3008                 if ((err = snd_cmipci_pcm_spdif_new(cm, pcm_index)) < 0)
3009                         return err;
3010         }
3011
3012         /* create mixer interface & switches */
3013         if ((err = snd_cmipci_mixer_new(cm, pcm_spdif_index)) < 0)
3014                 return err;
3015
3016         if (iomidi > 0) {
3017                 if ((err = snd_mpu401_uart_new(card, 0, MPU401_HW_CMIPCI,
3018                                                iomidi,
3019                                                (integrated_midi ?
3020                                                 MPU401_INFO_INTEGRATED : 0),
3021                                                cm->irq, 0, &cm->rmidi)) < 0) {
3022                         printk(KERN_ERR "cmipci: no UART401 device at 0x%lx\n", iomidi);
3023                 }
3024         }
3025
3026 #ifdef USE_VAR48KRATE
3027         for (val = 0; val < ARRAY_SIZE(rates); val++)
3028                 snd_cmipci_set_pll(cm, rates[val], val);
3029
3030         /*
3031          * (Re-)Enable external switch spdo_48k
3032          */
3033         snd_cmipci_set_bit(cm, CM_REG_MISC_CTRL, CM_SPDIF48K|CM_SPDF_AC97);
3034 #endif /* USE_VAR48KRATE */
3035
3036         if (snd_cmipci_create_gameport(cm, dev) < 0)
3037                 snd_cmipci_clear_bit(cm, CM_REG_FUNCTRL1, CM_JYSTK_EN);
3038
3039         snd_card_set_dev(card, &pci->dev);
3040
3041         *rcmipci = cm;
3042         return 0;
3043 }
3044
3045 /*
3046  */
3047
3048 MODULE_DEVICE_TABLE(pci, snd_cmipci_ids);
3049
3050 static int __devinit snd_cmipci_probe(struct pci_dev *pci,
3051                                       const struct pci_device_id *pci_id)
3052 {
3053         static int dev;
3054         struct snd_card *card;
3055         struct cmipci *cm;
3056         int err;
3057
3058         if (dev >= SNDRV_CARDS)
3059                 return -ENODEV;
3060         if (! enable[dev]) {
3061                 dev++;
3062                 return -ENOENT;
3063         }
3064
3065         card = snd_card_new(index[dev], id[dev], THIS_MODULE, 0);
3066         if (card == NULL)
3067                 return -ENOMEM;
3068         
3069         switch (pci->device) {
3070         case PCI_DEVICE_ID_CMEDIA_CM8738:
3071         case PCI_DEVICE_ID_CMEDIA_CM8738B:
3072                 strcpy(card->driver, "CMI8738");
3073                 break;
3074         case PCI_DEVICE_ID_CMEDIA_CM8338A:
3075         case PCI_DEVICE_ID_CMEDIA_CM8338B:
3076                 strcpy(card->driver, "CMI8338");
3077                 break;
3078         default:
3079                 strcpy(card->driver, "CMIPCI");
3080                 break;
3081         }
3082
3083         if ((err = snd_cmipci_create(card, pci, dev, &cm)) < 0) {
3084                 snd_card_free(card);
3085                 return err;
3086         }
3087         card->private_data = cm;
3088
3089         if ((err = snd_card_register(card)) < 0) {
3090                 snd_card_free(card);
3091                 return err;
3092         }
3093         pci_set_drvdata(pci, card);
3094         dev++;
3095         return 0;
3096
3097 }
3098
3099 static void __devexit snd_cmipci_remove(struct pci_dev *pci)
3100 {
3101         snd_card_free(pci_get_drvdata(pci));
3102         pci_set_drvdata(pci, NULL);
3103 }
3104
3105
3106 #ifdef CONFIG_PM
3107 /*
3108  * power management
3109  */
3110 static unsigned char saved_regs[] = {
3111         CM_REG_FUNCTRL1, CM_REG_CHFORMAT, CM_REG_LEGACY_CTRL, CM_REG_MISC_CTRL,
3112         CM_REG_MIXER0, CM_REG_MIXER1, CM_REG_MIXER2, CM_REG_MIXER3, CM_REG_PLL,
3113         CM_REG_CH0_FRAME1, CM_REG_CH0_FRAME2,
3114         CM_REG_CH1_FRAME1, CM_REG_CH1_FRAME2, CM_REG_EXT_MISC,
3115         CM_REG_INT_STATUS, CM_REG_INT_HLDCLR, CM_REG_FUNCTRL0,
3116 };
3117
3118 static unsigned char saved_mixers[] = {
3119         SB_DSP4_MASTER_DEV, SB_DSP4_MASTER_DEV + 1,
3120         SB_DSP4_PCM_DEV, SB_DSP4_PCM_DEV + 1,
3121         SB_DSP4_SYNTH_DEV, SB_DSP4_SYNTH_DEV + 1,
3122         SB_DSP4_CD_DEV, SB_DSP4_CD_DEV + 1,
3123         SB_DSP4_LINE_DEV, SB_DSP4_LINE_DEV + 1,
3124         SB_DSP4_MIC_DEV, SB_DSP4_SPEAKER_DEV,
3125         CM_REG_EXTENT_IND, SB_DSP4_OUTPUT_SW,
3126         SB_DSP4_INPUT_LEFT, SB_DSP4_INPUT_RIGHT,
3127 };
3128
3129 static int snd_cmipci_suspend(struct pci_dev *pci, pm_message_t state)
3130 {
3131         struct snd_card *card = pci_get_drvdata(pci);
3132         struct cmipci *cm = card->private_data;
3133         int i;
3134
3135         snd_power_change_state(card, SNDRV_CTL_POWER_D3hot);
3136         
3137         snd_pcm_suspend_all(cm->pcm);
3138         snd_pcm_suspend_all(cm->pcm2);
3139         snd_pcm_suspend_all(cm->pcm_spdif);
3140
3141         /* save registers */
3142         for (i = 0; i < ARRAY_SIZE(saved_regs); i++)
3143                 cm->saved_regs[i] = snd_cmipci_read(cm, saved_regs[i]);
3144         for (i = 0; i < ARRAY_SIZE(saved_mixers); i++)
3145                 cm->saved_mixers[i] = snd_cmipci_mixer_read(cm, saved_mixers[i]);
3146
3147         /* disable ints */
3148         snd_cmipci_write(cm, CM_REG_INT_HLDCLR, 0);
3149
3150         pci_disable_device(pci);
3151         pci_save_state(pci);
3152         pci_set_power_state(pci, pci_choose_state(pci, state));
3153         return 0;
3154 }
3155
3156 static int snd_cmipci_resume(struct pci_dev *pci)
3157 {
3158         struct snd_card *card = pci_get_drvdata(pci);
3159         struct cmipci *cm = card->private_data;
3160         int i;
3161
3162         pci_set_power_state(pci, PCI_D0);
3163         pci_restore_state(pci);
3164         if (pci_enable_device(pci) < 0) {
3165                 printk(KERN_ERR "cmipci: pci_enable_device failed, "
3166                        "disabling device\n");
3167                 snd_card_disconnect(card);
3168                 return -EIO;
3169         }
3170         pci_set_master(pci);
3171
3172         /* reset / initialize to a sane state */
3173         snd_cmipci_write(cm, CM_REG_INT_HLDCLR, 0);
3174         snd_cmipci_ch_reset(cm, CM_CH_PLAY);
3175         snd_cmipci_ch_reset(cm, CM_CH_CAPT);
3176         snd_cmipci_mixer_write(cm, 0, 0);
3177
3178         /* restore registers */
3179         for (i = 0; i < ARRAY_SIZE(saved_regs); i++)
3180                 snd_cmipci_write(cm, saved_regs[i], cm->saved_regs[i]);
3181         for (i = 0; i < ARRAY_SIZE(saved_mixers); i++)
3182                 snd_cmipci_mixer_write(cm, saved_mixers[i], cm->saved_mixers[i]);
3183
3184         snd_power_change_state(card, SNDRV_CTL_POWER_D0);
3185         return 0;
3186 }
3187 #endif /* CONFIG_PM */
3188
3189 static struct pci_driver driver = {
3190         .name = "C-Media PCI",
3191         .id_table = snd_cmipci_ids,
3192         .probe = snd_cmipci_probe,
3193         .remove = __devexit_p(snd_cmipci_remove),
3194 #ifdef CONFIG_PM
3195         .suspend = snd_cmipci_suspend,
3196         .resume = snd_cmipci_resume,
3197 #endif
3198 };
3199         
3200 static int __init alsa_card_cmipci_init(void)
3201 {
3202         return pci_register_driver(&driver);
3203 }
3204
3205 static void __exit alsa_card_cmipci_exit(void)
3206 {
3207         pci_unregister_driver(&driver);
3208 }
3209
3210 module_init(alsa_card_cmipci_init)
3211 module_exit(alsa_card_cmipci_exit)