[ALSA] Remove xxx_t typedefs: PCI Intel8x0
[linux-2.6.git] / sound / pci / cmipci.c
1 /*
2  * Driver for C-Media CMI8338 and 8738 PCI soundcards.
3  * Copyright (c) 2000 by Takashi Iwai <tiwai@suse.de>
4  *
5  *   This program is free software; you can redistribute it and/or modify
6  *   it under the terms of the GNU General Public License as published by
7  *   the Free Software Foundation; either version 2 of the License, or
8  *   (at your option) any later version.
9  *
10  *   This program is distributed in the hope that it will be useful,
11  *   but WITHOUT ANY WARRANTY; without even the implied warranty of
12  *   MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
13  *   GNU General Public License for more details.
14  *
15  *   You should have received a copy of the GNU General Public License
16  *   along with this program; if not, write to the Free Software
17  *   Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307 USA
18  */
19  
20 /* Does not work. Warning may block system in capture mode */
21 /* #define USE_VAR48KRATE */
22
23 #include <sound/driver.h>
24 #include <asm/io.h>
25 #include <linux/delay.h>
26 #include <linux/interrupt.h>
27 #include <linux/init.h>
28 #include <linux/pci.h>
29 #include <linux/slab.h>
30 #include <linux/gameport.h>
31 #include <linux/moduleparam.h>
32 #include <sound/core.h>
33 #include <sound/info.h>
34 #include <sound/control.h>
35 #include <sound/pcm.h>
36 #include <sound/rawmidi.h>
37 #include <sound/mpu401.h>
38 #include <sound/opl3.h>
39 #include <sound/sb.h>
40 #include <sound/asoundef.h>
41 #include <sound/initval.h>
42
43 MODULE_AUTHOR("Takashi Iwai <tiwai@suse.de>");
44 MODULE_DESCRIPTION("C-Media CMI8x38 PCI");
45 MODULE_LICENSE("GPL");
46 MODULE_SUPPORTED_DEVICE("{{C-Media,CMI8738},"
47                 "{C-Media,CMI8738B},"
48                 "{C-Media,CMI8338A},"
49                 "{C-Media,CMI8338B}}");
50
51 #if defined(CONFIG_GAMEPORT) || (defined(MODULE) && defined(CONFIG_GAMEPORT_MODULE))
52 #define SUPPORT_JOYSTICK 1
53 #endif
54
55 static int index[SNDRV_CARDS] = SNDRV_DEFAULT_IDX;      /* Index 0-MAX */
56 static char *id[SNDRV_CARDS] = SNDRV_DEFAULT_STR;       /* ID for this card */
57 static int enable[SNDRV_CARDS] = SNDRV_DEFAULT_ENABLE_PNP;      /* Enable switches */
58 static long mpu_port[SNDRV_CARDS];
59 static long fm_port[SNDRV_CARDS];
60 static int soft_ac3[SNDRV_CARDS] = {[0 ... (SNDRV_CARDS-1)]=1};
61 #ifdef SUPPORT_JOYSTICK
62 static int joystick_port[SNDRV_CARDS];
63 #endif
64
65 module_param_array(index, int, NULL, 0444);
66 MODULE_PARM_DESC(index, "Index value for C-Media PCI soundcard.");
67 module_param_array(id, charp, NULL, 0444);
68 MODULE_PARM_DESC(id, "ID string for C-Media PCI soundcard.");
69 module_param_array(enable, bool, NULL, 0444);
70 MODULE_PARM_DESC(enable, "Enable C-Media PCI soundcard.");
71 module_param_array(mpu_port, long, NULL, 0444);
72 MODULE_PARM_DESC(mpu_port, "MPU-401 port.");
73 module_param_array(fm_port, long, NULL, 0444);
74 MODULE_PARM_DESC(fm_port, "FM port.");
75 module_param_array(soft_ac3, bool, NULL, 0444);
76 MODULE_PARM_DESC(soft_ac3, "Sofware-conversion of raw SPDIF packets (model 033 only).");
77 #ifdef SUPPORT_JOYSTICK
78 module_param_array(joystick_port, int, NULL, 0444);
79 MODULE_PARM_DESC(joystick_port, "Joystick port address.");
80 #endif
81
82 /*
83  * CM8x38 registers definition
84  */
85
86 #define CM_REG_FUNCTRL0         0x00
87 #define CM_RST_CH1              0x00080000
88 #define CM_RST_CH0              0x00040000
89 #define CM_CHEN1                0x00020000      /* ch1: enable */
90 #define CM_CHEN0                0x00010000      /* ch0: enable */
91 #define CM_PAUSE1               0x00000008      /* ch1: pause */
92 #define CM_PAUSE0               0x00000004      /* ch0: pause */
93 #define CM_CHADC1               0x00000002      /* ch1, 0:playback, 1:record */
94 #define CM_CHADC0               0x00000001      /* ch0, 0:playback, 1:record */
95
96 #define CM_REG_FUNCTRL1         0x04
97 #define CM_ASFC_MASK            0x0000E000      /* ADC sampling frequency */
98 #define CM_ASFC_SHIFT           13
99 #define CM_DSFC_MASK            0x00001C00      /* DAC sampling frequency */
100 #define CM_DSFC_SHIFT           10
101 #define CM_SPDF_1               0x00000200      /* SPDIF IN/OUT at channel B */
102 #define CM_SPDF_0               0x00000100      /* SPDIF OUT only channel A */
103 #define CM_SPDFLOOP             0x00000080      /* ext. SPDIIF/OUT -> IN loopback */
104 #define CM_SPDO2DAC             0x00000040      /* SPDIF/OUT can be heard from internal DAC */
105 #define CM_INTRM                0x00000020      /* master control block (MCB) interrupt enabled */
106 #define CM_BREQ                 0x00000010      /* bus master enabled */
107 #define CM_VOICE_EN             0x00000008      /* legacy voice (SB16,FM) */
108 #define CM_UART_EN              0x00000004      /* UART */
109 #define CM_JYSTK_EN             0x00000002      /* joy stick */
110
111 #define CM_REG_CHFORMAT         0x08
112
113 #define CM_CHB3D5C              0x80000000      /* 5,6 channels */
114 #define CM_CHB3D                0x20000000      /* 4 channels */
115
116 #define CM_CHIP_MASK1           0x1f000000
117 #define CM_CHIP_037             0x01000000
118
119 #define CM_SPDIF_SELECT1        0x00080000      /* for model <= 037 ? */
120 #define CM_AC3EN1               0x00100000      /* enable AC3: model 037 */
121 #define CM_SPD24SEL             0x00020000      /* 24bit spdif: model 037 */
122 /* #define CM_SPDIF_INVERSE     0x00010000 */ /* ??? */
123
124 #define CM_ADCBITLEN_MASK       0x0000C000      
125 #define CM_ADCBITLEN_16         0x00000000
126 #define CM_ADCBITLEN_15         0x00004000
127 #define CM_ADCBITLEN_14         0x00008000
128 #define CM_ADCBITLEN_13         0x0000C000
129
130 #define CM_ADCDACLEN_MASK       0x00003000
131 #define CM_ADCDACLEN_060        0x00000000
132 #define CM_ADCDACLEN_066        0x00001000
133 #define CM_ADCDACLEN_130        0x00002000
134 #define CM_ADCDACLEN_280        0x00003000
135
136 #define CM_CH1_SRATE_176K       0x00000800
137 #define CM_CH1_SRATE_88K        0x00000400
138 #define CM_CH0_SRATE_176K       0x00000200
139 #define CM_CH0_SRATE_88K        0x00000100
140
141 #define CM_SPDIF_INVERSE2       0x00000080      /* model 055? */
142
143 #define CM_CH1FMT_MASK          0x0000000C
144 #define CM_CH1FMT_SHIFT         2
145 #define CM_CH0FMT_MASK          0x00000003
146 #define CM_CH0FMT_SHIFT         0
147
148 #define CM_REG_INT_HLDCLR       0x0C
149 #define CM_CHIP_MASK2           0xff000000
150 #define CM_CHIP_039             0x04000000
151 #define CM_CHIP_039_6CH         0x01000000
152 #define CM_CHIP_055             0x08000000
153 #define CM_CHIP_8768            0x20000000
154 #define CM_TDMA_INT_EN          0x00040000
155 #define CM_CH1_INT_EN           0x00020000
156 #define CM_CH0_INT_EN           0x00010000
157 #define CM_INT_HOLD             0x00000002
158 #define CM_INT_CLEAR            0x00000001
159
160 #define CM_REG_INT_STATUS       0x10
161 #define CM_INTR                 0x80000000
162 #define CM_VCO                  0x08000000      /* Voice Control? CMI8738 */
163 #define CM_MCBINT               0x04000000      /* Master Control Block abort cond.? */
164 #define CM_UARTINT              0x00010000
165 #define CM_LTDMAINT             0x00008000
166 #define CM_HTDMAINT             0x00004000
167 #define CM_XDO46                0x00000080      /* Modell 033? Direct programming EEPROM (read data register) */
168 #define CM_LHBTOG               0x00000040      /* High/Low status from DMA ctrl register */
169 #define CM_LEG_HDMA             0x00000020      /* Legacy is in High DMA channel */
170 #define CM_LEG_STEREO           0x00000010      /* Legacy is in Stereo mode */
171 #define CM_CH1BUSY              0x00000008
172 #define CM_CH0BUSY              0x00000004
173 #define CM_CHINT1               0x00000002
174 #define CM_CHINT0               0x00000001
175
176 #define CM_REG_LEGACY_CTRL      0x14
177 #define CM_NXCHG                0x80000000      /* h/w multi channels? */
178 #define CM_VMPU_MASK            0x60000000      /* MPU401 i/o port address */
179 #define CM_VMPU_330             0x00000000
180 #define CM_VMPU_320             0x20000000
181 #define CM_VMPU_310             0x40000000
182 #define CM_VMPU_300             0x60000000
183 #define CM_VSBSEL_MASK          0x0C000000      /* SB16 base address */
184 #define CM_VSBSEL_220           0x00000000
185 #define CM_VSBSEL_240           0x04000000
186 #define CM_VSBSEL_260           0x08000000
187 #define CM_VSBSEL_280           0x0C000000
188 #define CM_FMSEL_MASK           0x03000000      /* FM OPL3 base address */
189 #define CM_FMSEL_388            0x00000000
190 #define CM_FMSEL_3C8            0x01000000
191 #define CM_FMSEL_3E0            0x02000000
192 #define CM_FMSEL_3E8            0x03000000
193 #define CM_ENSPDOUT             0x00800000      /* enable XPDIF/OUT to I/O interface */
194 #define CM_SPDCOPYRHT           0x00400000      /* set copyright spdif in/out */
195 #define CM_DAC2SPDO             0x00200000      /* enable wave+fm_midi -> SPDIF/OUT */
196 #define CM_SETRETRY             0x00010000      /* 0: legacy i/o wait (default), 1: legacy i/o bus retry */
197 #define CM_CHB3D6C              0x00008000      /* 5.1 channels support */
198 #define CM_LINE_AS_BASS         0x00006000      /* use line-in as bass */
199
200 #define CM_REG_MISC_CTRL        0x18
201 #define CM_PWD                  0x80000000
202 #define CM_RESET                0x40000000
203 #define CM_SFIL_MASK            0x30000000
204 #define CM_TXVX                 0x08000000
205 #define CM_N4SPK3D              0x04000000      /* 4ch output */
206 #define CM_SPDO5V               0x02000000      /* 5V spdif output (1 = 0.5v (coax)) */
207 #define CM_SPDIF48K             0x01000000      /* write */
208 #define CM_SPATUS48K            0x01000000      /* read */
209 #define CM_ENDBDAC              0x00800000      /* enable dual dac */
210 #define CM_XCHGDAC              0x00400000      /* 0: front=ch0, 1: front=ch1 */
211 #define CM_SPD32SEL             0x00200000      /* 0: 16bit SPDIF, 1: 32bit */
212 #define CM_SPDFLOOPI            0x00100000      /* int. SPDIF-IN -> int. OUT */
213 #define CM_FM_EN                0x00080000      /* enalbe FM */
214 #define CM_AC3EN2               0x00040000      /* enable AC3: model 039 */
215 #define CM_VIDWPDSB             0x00010000 
216 #define CM_SPDF_AC97            0x00008000      /* 0: SPDIF/OUT 44.1K, 1: 48K */
217 #define CM_MASK_EN              0x00004000
218 #define CM_VIDWPPRT             0x00002000
219 #define CM_SFILENB              0x00001000
220 #define CM_MMODE_MASK           0x00000E00
221 #define CM_SPDIF_SELECT2        0x00000100      /* for model > 039 ? */
222 #define CM_ENCENTER             0x00000080
223 #define CM_FLINKON              0x00000040
224 #define CM_FLINKOFF             0x00000020
225 #define CM_MIDSMP               0x00000010
226 #define CM_UPDDMA_MASK          0x0000000C
227 #define CM_TWAIT_MASK           0x00000003
228
229         /* byte */
230 #define CM_REG_MIXER0           0x20
231
232 #define CM_REG_SB16_DATA        0x22
233 #define CM_REG_SB16_ADDR        0x23
234
235 #define CM_REFFREQ_XIN          (315*1000*1000)/22      /* 14.31818 Mhz reference clock frequency pin XIN */
236 #define CM_ADCMULT_XIN          512                     /* Guessed (487 best for 44.1kHz, not for 88/176kHz) */
237 #define CM_TOLERANCE_RATE       0.001                   /* Tolerance sample rate pitch (1000ppm) */
238 #define CM_MAXIMUM_RATE         80000000                /* Note more than 80MHz */
239
240 #define CM_REG_MIXER1           0x24
241 #define CM_FMMUTE               0x80    /* mute FM */
242 #define CM_FMMUTE_SHIFT         7
243 #define CM_WSMUTE               0x40    /* mute PCM */
244 #define CM_WSMUTE_SHIFT         6
245 #define CM_SPK4                 0x20    /* lin-in -> rear line out */
246 #define CM_SPK4_SHIFT           5
247 #define CM_REAR2FRONT           0x10    /* exchange rear/front */
248 #define CM_REAR2FRONT_SHIFT     4
249 #define CM_WAVEINL              0x08    /* digital wave rec. left chan */
250 #define CM_WAVEINL_SHIFT        3
251 #define CM_WAVEINR              0x04    /* digical wave rec. right */
252 #define CM_WAVEINR_SHIFT        2
253 #define CM_X3DEN                0x02    /* 3D surround enable */
254 #define CM_X3DEN_SHIFT          1
255 #define CM_CDPLAY               0x01    /* enable SPDIF/IN PCM -> DAC */
256 #define CM_CDPLAY_SHIFT         0
257
258 #define CM_REG_MIXER2           0x25
259 #define CM_RAUXREN              0x80    /* AUX right capture */
260 #define CM_RAUXREN_SHIFT        7
261 #define CM_RAUXLEN              0x40    /* AUX left capture */
262 #define CM_RAUXLEN_SHIFT        6
263 #define CM_VAUXRM               0x20    /* AUX right mute */
264 #define CM_VAUXRM_SHIFT         5
265 #define CM_VAUXLM               0x10    /* AUX left mute */
266 #define CM_VAUXLM_SHIFT         4
267 #define CM_VADMIC_MASK          0x0e    /* mic gain level (0-3) << 1 */
268 #define CM_VADMIC_SHIFT         1
269 #define CM_MICGAINZ             0x01    /* mic boost */
270 #define CM_MICGAINZ_SHIFT       0
271
272 #define CM_REG_AUX_VOL          0x26
273 #define CM_VAUXL_MASK           0xf0
274 #define CM_VAUXR_MASK           0x0f
275
276 #define CM_REG_MISC             0x27
277 #define CM_XGPO1                0x20
278 // #define CM_XGPBIO            0x04
279 #define CM_MIC_CENTER_LFE       0x04    /* mic as center/lfe out? (model 039 or later?) */
280 #define CM_SPDIF_INVERSE        0x04    /* spdif input phase inverse (model 037) */
281 #define CM_SPDVALID             0x02    /* spdif input valid check */
282 #define CM_DMAUTO               0x01
283
284 #define CM_REG_AC97             0x28    /* hmmm.. do we have ac97 link? */
285 /*
286  * For CMI-8338 (0x28 - 0x2b) .. is this valid for CMI-8738
287  * or identical with AC97 codec?
288  */
289 #define CM_REG_EXTERN_CODEC     CM_REG_AC97
290
291 /*
292  * MPU401 pci port index address 0x40 - 0x4f (CMI-8738 spec ver. 0.6)
293  */
294 #define CM_REG_MPU_PCI          0x40
295
296 /*
297  * FM pci port index address 0x50 - 0x5f (CMI-8738 spec ver. 0.6)
298  */
299 #define CM_REG_FM_PCI           0x50
300
301 /*
302  * access from SB-mixer port
303  */
304 #define CM_REG_EXTENT_IND       0xf0
305 #define CM_VPHONE_MASK          0xe0    /* Phone volume control (0-3) << 5 */
306 #define CM_VPHONE_SHIFT         5
307 #define CM_VPHOM                0x10    /* Phone mute control */
308 #define CM_VSPKM                0x08    /* Speaker mute control, default high */
309 #define CM_RLOOPREN             0x04    /* Rec. R-channel enable */
310 #define CM_RLOOPLEN             0x02    /* Rec. L-channel enable */
311 #define CM_VADMIC3              0x01    /* Mic record boost */
312
313 /*
314  * CMI-8338 spec ver 0.5 (this is not valid for CMI-8738):
315  * the 8 registers 0xf8 - 0xff are used for programming m/n counter by the PLL
316  * unit (readonly?).
317  */
318 #define CM_REG_PLL              0xf8
319
320 /*
321  * extended registers
322  */
323 #define CM_REG_CH0_FRAME1       0x80    /* base address */
324 #define CM_REG_CH0_FRAME2       0x84
325 #define CM_REG_CH1_FRAME1       0x88    /* 0-15: count of samples at bus master; buffer size */
326 #define CM_REG_CH1_FRAME2       0x8C    /* 16-31: count of samples at codec; fragment size */
327 #define CM_REG_MISC_CTRL_8768   0x92    /* reg. name the same as 0x18 */
328 #define CM_CHB3D8C              0x20    /* 7.1 channels support */
329 #define CM_SPD32FMT             0x10    /* SPDIF/IN 32k */
330 #define CM_ADC2SPDIF            0x08    /* ADC output to SPDIF/OUT */
331 #define CM_SHAREADC             0x04    /* DAC in ADC as Center/LFE */
332 #define CM_REALTCMP             0x02    /* monitor the CMPL/CMPR of ADC */
333 #define CM_INVLRCK              0x01    /* invert ZVPORT's LRCK */
334
335 /*
336  * size of i/o region
337  */
338 #define CM_EXTENT_CODEC   0x100
339 #define CM_EXTENT_MIDI    0x2
340 #define CM_EXTENT_SYNTH   0x4
341
342
343 /*
344  * channels for playback / capture
345  */
346 #define CM_CH_PLAY      0
347 #define CM_CH_CAPT      1
348
349 /*
350  * flags to check device open/close
351  */
352 #define CM_OPEN_NONE    0
353 #define CM_OPEN_CH_MASK 0x01
354 #define CM_OPEN_DAC     0x10
355 #define CM_OPEN_ADC     0x20
356 #define CM_OPEN_SPDIF   0x40
357 #define CM_OPEN_MCHAN   0x80
358 #define CM_OPEN_PLAYBACK        (CM_CH_PLAY | CM_OPEN_DAC)
359 #define CM_OPEN_PLAYBACK2       (CM_CH_CAPT | CM_OPEN_DAC)
360 #define CM_OPEN_PLAYBACK_MULTI  (CM_CH_PLAY | CM_OPEN_DAC | CM_OPEN_MCHAN)
361 #define CM_OPEN_CAPTURE         (CM_CH_CAPT | CM_OPEN_ADC)
362 #define CM_OPEN_SPDIF_PLAYBACK  (CM_CH_PLAY | CM_OPEN_DAC | CM_OPEN_SPDIF)
363 #define CM_OPEN_SPDIF_CAPTURE   (CM_CH_CAPT | CM_OPEN_ADC | CM_OPEN_SPDIF)
364
365
366 #if CM_CH_PLAY == 1
367 #define CM_PLAYBACK_SRATE_176K  CM_CH1_SRATE_176K
368 #define CM_PLAYBACK_SPDF        CM_SPDF_1
369 #define CM_CAPTURE_SPDF         CM_SPDF_0
370 #else
371 #define CM_PLAYBACK_SRATE_176K CM_CH0_SRATE_176K
372 #define CM_PLAYBACK_SPDF        CM_SPDF_0
373 #define CM_CAPTURE_SPDF         CM_SPDF_1
374 #endif
375
376
377 /*
378  * driver data
379  */
380
381 struct cmipci_pcm {
382         struct snd_pcm_substream *substream;
383         int running;            /* dac/adc running? */
384         unsigned int dma_size;  /* in frames */
385         unsigned int period_size;       /* in frames */
386         unsigned int offset;    /* physical address of the buffer */
387         unsigned int fmt;       /* format bits */
388         int ch;                 /* channel (0/1) */
389         unsigned int is_dac;            /* is dac? */
390         int bytes_per_frame;
391         int shift;
392 };
393
394 /* mixer elements toggled/resumed during ac3 playback */
395 struct cmipci_mixer_auto_switches {
396         const char *name;       /* switch to toggle */
397         int toggle_on;          /* value to change when ac3 mode */
398 };
399 static const struct cmipci_mixer_auto_switches cm_saved_mixer[] = {
400         {"PCM Playback Switch", 0},
401         {"IEC958 Output Switch", 1},
402         {"IEC958 Mix Analog", 0},
403         // {"IEC958 Out To DAC", 1}, // no longer used
404         {"IEC958 Loop", 0},
405 };
406 #define CM_SAVED_MIXERS         ARRAY_SIZE(cm_saved_mixer)
407
408 struct cmipci {
409         struct snd_card *card;
410
411         struct pci_dev *pci;
412         unsigned int device;    /* device ID */
413         int irq;
414
415         unsigned long iobase;
416         unsigned int ctrl;      /* FUNCTRL0 current value */
417
418         struct snd_pcm *pcm;            /* DAC/ADC PCM */
419         struct snd_pcm *pcm2;   /* 2nd DAC */
420         struct snd_pcm *pcm_spdif;      /* SPDIF */
421
422         int chip_version;
423         int max_channels;
424         unsigned int has_dual_dac: 1;
425         unsigned int can_ac3_sw: 1;
426         unsigned int can_ac3_hw: 1;
427         unsigned int can_multi_ch: 1;
428         unsigned int do_soft_ac3: 1;
429
430         unsigned int spdif_playback_avail: 1;   /* spdif ready? */
431         unsigned int spdif_playback_enabled: 1; /* spdif switch enabled? */
432         int spdif_counter;      /* for software AC3 */
433
434         unsigned int dig_status;
435         unsigned int dig_pcm_status;
436
437         struct snd_pcm_hardware *hw_info[3]; /* for playbacks */
438
439         int opened[2];  /* open mode */
440         struct semaphore open_mutex;
441
442         unsigned int mixer_insensitive: 1;
443         struct snd_kcontrol *mixer_res_ctl[CM_SAVED_MIXERS];
444         int mixer_res_status[CM_SAVED_MIXERS];
445
446         struct cmipci_pcm channel[2];   /* ch0 - DAC, ch1 - ADC or 2nd DAC */
447
448         /* external MIDI */
449         struct snd_rawmidi *rmidi;
450
451 #ifdef SUPPORT_JOYSTICK
452         struct gameport *gameport;
453 #endif
454
455         spinlock_t reg_lock;
456 };
457
458
459 /* read/write operations for dword register */
460 static inline void snd_cmipci_write(struct cmipci *cm, unsigned int cmd, unsigned int data)
461 {
462         outl(data, cm->iobase + cmd);
463 }
464
465 static inline unsigned int snd_cmipci_read(struct cmipci *cm, unsigned int cmd)
466 {
467         return inl(cm->iobase + cmd);
468 }
469
470 /* read/write operations for word register */
471 static inline void snd_cmipci_write_w(struct cmipci *cm, unsigned int cmd, unsigned short data)
472 {
473         outw(data, cm->iobase + cmd);
474 }
475
476 static inline unsigned short snd_cmipci_read_w(struct cmipci *cm, unsigned int cmd)
477 {
478         return inw(cm->iobase + cmd);
479 }
480
481 /* read/write operations for byte register */
482 static inline void snd_cmipci_write_b(struct cmipci *cm, unsigned int cmd, unsigned char data)
483 {
484         outb(data, cm->iobase + cmd);
485 }
486
487 static inline unsigned char snd_cmipci_read_b(struct cmipci *cm, unsigned int cmd)
488 {
489         return inb(cm->iobase + cmd);
490 }
491
492 /* bit operations for dword register */
493 static int snd_cmipci_set_bit(struct cmipci *cm, unsigned int cmd, unsigned int flag)
494 {
495         unsigned int val, oval;
496         val = oval = inl(cm->iobase + cmd);
497         val |= flag;
498         if (val == oval)
499                 return 0;
500         outl(val, cm->iobase + cmd);
501         return 1;
502 }
503
504 static int snd_cmipci_clear_bit(struct cmipci *cm, unsigned int cmd, unsigned int flag)
505 {
506         unsigned int val, oval;
507         val = oval = inl(cm->iobase + cmd);
508         val &= ~flag;
509         if (val == oval)
510                 return 0;
511         outl(val, cm->iobase + cmd);
512         return 1;
513 }
514
515 /* bit operations for byte register */
516 static int snd_cmipci_set_bit_b(struct cmipci *cm, unsigned int cmd, unsigned char flag)
517 {
518         unsigned char val, oval;
519         val = oval = inb(cm->iobase + cmd);
520         val |= flag;
521         if (val == oval)
522                 return 0;
523         outb(val, cm->iobase + cmd);
524         return 1;
525 }
526
527 static int snd_cmipci_clear_bit_b(struct cmipci *cm, unsigned int cmd, unsigned char flag)
528 {
529         unsigned char val, oval;
530         val = oval = inb(cm->iobase + cmd);
531         val &= ~flag;
532         if (val == oval)
533                 return 0;
534         outb(val, cm->iobase + cmd);
535         return 1;
536 }
537
538
539 /*
540  * PCM interface
541  */
542
543 /*
544  * calculate frequency
545  */
546
547 static unsigned int rates[] = { 5512, 11025, 22050, 44100, 8000, 16000, 32000, 48000 };
548
549 static unsigned int snd_cmipci_rate_freq(unsigned int rate)
550 {
551         unsigned int i;
552         for (i = 0; i < ARRAY_SIZE(rates); i++) {
553                 if (rates[i] == rate)
554                         return i;
555         }
556         snd_BUG();
557         return 0;
558 }
559
560 #ifdef USE_VAR48KRATE
561 /*
562  * Determine PLL values for frequency setup, maybe the CMI8338 (CMI8738???)
563  * does it this way .. maybe not.  Never get any information from C-Media about
564  * that <werner@suse.de>.
565  */
566 static int snd_cmipci_pll_rmn(unsigned int rate, unsigned int adcmult, int *r, int *m, int *n)
567 {
568         unsigned int delta, tolerance;
569         int xm, xn, xr;
570
571         for (*r = 0; rate < CM_MAXIMUM_RATE/adcmult; *r += (1<<5))
572                 rate <<= 1;
573         *n = -1;
574         if (*r > 0xff)
575                 goto out;
576         tolerance = rate*CM_TOLERANCE_RATE;
577
578         for (xn = (1+2); xn < (0x1f+2); xn++) {
579                 for (xm = (1+2); xm < (0xff+2); xm++) {
580                         xr = ((CM_REFFREQ_XIN/adcmult) * xm) / xn;
581
582                         if (xr < rate)
583                                 delta = rate - xr;
584                         else
585                                 delta = xr - rate;
586
587                         /*
588                          * If we found one, remember this,
589                          * and try to find a closer one
590                          */
591                         if (delta < tolerance) {
592                                 tolerance = delta;
593                                 *m = xm - 2;
594                                 *n = xn - 2;
595                         }
596                 }
597         }
598 out:
599         return (*n > -1);
600 }
601
602 /*
603  * Program pll register bits, I assume that the 8 registers 0xf8 upto 0xff
604  * are mapped onto the 8 ADC/DAC sampling frequency which can be choosen
605  * at the register CM_REG_FUNCTRL1 (0x04).
606  * Problem: other ways are also possible (any information about that?)
607  */
608 static void snd_cmipci_set_pll(struct cmipci *cm, unsigned int rate, unsigned int slot)
609 {
610         unsigned int reg = CM_REG_PLL + slot;
611         /*
612          * Guess that this programs at reg. 0x04 the pos 15:13/12:10
613          * for DSFC/ASFC (000 upto 111).
614          */
615
616         /* FIXME: Init (Do we've to set an other register first before programming?) */
617
618         /* FIXME: Is this correct? Or shouldn't the m/n/r values be used for that? */
619         snd_cmipci_write_b(cm, reg, rate>>8);
620         snd_cmipci_write_b(cm, reg, rate&0xff);
621
622         /* FIXME: Setup (Do we've to set an other register first to enable this?) */
623 }
624 #endif /* USE_VAR48KRATE */
625
626 static int snd_cmipci_hw_params(struct snd_pcm_substream *substream,
627                                 struct snd_pcm_hw_params *hw_params)
628 {
629         return snd_pcm_lib_malloc_pages(substream, params_buffer_bytes(hw_params));
630 }
631
632 static int snd_cmipci_playback2_hw_params(struct snd_pcm_substream *substream,
633                                           struct snd_pcm_hw_params *hw_params)
634 {
635         struct cmipci *cm = snd_pcm_substream_chip(substream);
636         if (params_channels(hw_params) > 2) {
637                 down(&cm->open_mutex);
638                 if (cm->opened[CM_CH_PLAY]) {
639                         up(&cm->open_mutex);
640                         return -EBUSY;
641                 }
642                 /* reserve the channel A */
643                 cm->opened[CM_CH_PLAY] = CM_OPEN_PLAYBACK_MULTI;
644                 up(&cm->open_mutex);
645         }
646         return snd_pcm_lib_malloc_pages(substream, params_buffer_bytes(hw_params));
647 }
648
649 static void snd_cmipci_ch_reset(struct cmipci *cm, int ch)
650 {
651         int reset = CM_RST_CH0 << (cm->channel[ch].ch);
652         snd_cmipci_write(cm, CM_REG_FUNCTRL0, cm->ctrl | reset);
653         snd_cmipci_write(cm, CM_REG_FUNCTRL0, cm->ctrl & ~reset);
654         udelay(10);
655 }
656
657 static int snd_cmipci_hw_free(struct snd_pcm_substream *substream)
658 {
659         return snd_pcm_lib_free_pages(substream);
660 }
661
662
663 /*
664  */
665
666 static unsigned int hw_channels[] = {1, 2, 4, 5, 6, 8};
667 static struct snd_pcm_hw_constraint_list hw_constraints_channels_4 = {
668         .count = 3,
669         .list = hw_channels,
670         .mask = 0,
671 };
672 static struct snd_pcm_hw_constraint_list hw_constraints_channels_6 = {
673         .count = 5,
674         .list = hw_channels,
675         .mask = 0,
676 };
677 static struct snd_pcm_hw_constraint_list hw_constraints_channels_8 = {
678         .count = 6,
679         .list = hw_channels,
680         .mask = 0,
681 };
682
683 static int set_dac_channels(struct cmipci *cm, struct cmipci_pcm *rec, int channels)
684 {
685         if (channels > 2) {
686                 if (! cm->can_multi_ch)
687                         return -EINVAL;
688                 if (rec->fmt != 0x03) /* stereo 16bit only */
689                         return -EINVAL;
690
691                 spin_lock_irq(&cm->reg_lock);
692                 snd_cmipci_set_bit(cm, CM_REG_LEGACY_CTRL, CM_NXCHG);
693                 snd_cmipci_set_bit(cm, CM_REG_MISC_CTRL, CM_XCHGDAC);
694                 if (channels > 4) {
695                         snd_cmipci_clear_bit(cm, CM_REG_CHFORMAT, CM_CHB3D);
696                         snd_cmipci_set_bit(cm, CM_REG_CHFORMAT, CM_CHB3D5C);
697                 } else {
698                         snd_cmipci_clear_bit(cm, CM_REG_CHFORMAT, CM_CHB3D5C);
699                         snd_cmipci_set_bit(cm, CM_REG_CHFORMAT, CM_CHB3D);
700                 }
701                 if (channels >= 6) {
702                         snd_cmipci_set_bit(cm, CM_REG_LEGACY_CTRL, CM_CHB3D6C);
703                         snd_cmipci_set_bit(cm, CM_REG_MISC_CTRL, CM_ENCENTER);
704                 } else {
705                         snd_cmipci_clear_bit(cm, CM_REG_LEGACY_CTRL, CM_CHB3D6C);
706                         snd_cmipci_clear_bit(cm, CM_REG_MISC_CTRL, CM_ENCENTER);
707                 }
708                 if (cm->chip_version == 68) {
709                         if (channels == 8) {
710                                 snd_cmipci_set_bit(cm, CM_REG_MISC_CTRL_8768, CM_CHB3D8C);
711                         } else {
712                                 snd_cmipci_clear_bit(cm, CM_REG_MISC_CTRL_8768, CM_CHB3D8C);
713                         }
714                 }
715                 spin_unlock_irq(&cm->reg_lock);
716
717         } else {
718                 if (cm->can_multi_ch) {
719                         spin_lock_irq(&cm->reg_lock);
720                         snd_cmipci_clear_bit(cm, CM_REG_LEGACY_CTRL, CM_NXCHG);
721                         snd_cmipci_clear_bit(cm, CM_REG_CHFORMAT, CM_CHB3D);
722                         snd_cmipci_clear_bit(cm, CM_REG_CHFORMAT, CM_CHB3D5C);
723                         snd_cmipci_clear_bit(cm, CM_REG_LEGACY_CTRL, CM_CHB3D6C);
724                         snd_cmipci_clear_bit(cm, CM_REG_MISC_CTRL, CM_ENCENTER);
725                         snd_cmipci_clear_bit(cm, CM_REG_MISC_CTRL, CM_XCHGDAC);
726                         spin_unlock_irq(&cm->reg_lock);
727                 }
728         }
729         return 0;
730 }
731
732
733 /*
734  * prepare playback/capture channel
735  * channel to be used must have been set in rec->ch.
736  */
737 static int snd_cmipci_pcm_prepare(struct cmipci *cm, struct cmipci_pcm *rec,
738                                  struct snd_pcm_substream *substream)
739 {
740         unsigned int reg, freq, val;
741         struct snd_pcm_runtime *runtime = substream->runtime;
742
743         rec->fmt = 0;
744         rec->shift = 0;
745         if (snd_pcm_format_width(runtime->format) >= 16) {
746                 rec->fmt |= 0x02;
747                 if (snd_pcm_format_width(runtime->format) > 16)
748                         rec->shift++; /* 24/32bit */
749         }
750         if (runtime->channels > 1)
751                 rec->fmt |= 0x01;
752         if (rec->is_dac && set_dac_channels(cm, rec, runtime->channels) < 0) {
753                 snd_printd("cannot set dac channels\n");
754                 return -EINVAL;
755         }
756
757         rec->offset = runtime->dma_addr;
758         /* buffer and period sizes in frame */
759         rec->dma_size = runtime->buffer_size << rec->shift;
760         rec->period_size = runtime->period_size << rec->shift;
761         if (runtime->channels > 2) {
762                 /* multi-channels */
763                 rec->dma_size = (rec->dma_size * runtime->channels) / 2;
764                 rec->period_size = (rec->period_size * runtime->channels) / 2;
765         }
766
767         spin_lock_irq(&cm->reg_lock);
768
769         /* set buffer address */
770         reg = rec->ch ? CM_REG_CH1_FRAME1 : CM_REG_CH0_FRAME1;
771         snd_cmipci_write(cm, reg, rec->offset);
772         /* program sample counts */
773         reg = rec->ch ? CM_REG_CH1_FRAME2 : CM_REG_CH0_FRAME2;
774         snd_cmipci_write_w(cm, reg, rec->dma_size - 1);
775         snd_cmipci_write_w(cm, reg + 2, rec->period_size - 1);
776
777         /* set adc/dac flag */
778         val = rec->ch ? CM_CHADC1 : CM_CHADC0;
779         if (rec->is_dac)
780                 cm->ctrl &= ~val;
781         else
782                 cm->ctrl |= val;
783         snd_cmipci_write(cm, CM_REG_FUNCTRL0, cm->ctrl);
784         //snd_printd("cmipci: functrl0 = %08x\n", cm->ctrl);
785
786         /* set sample rate */
787         freq = snd_cmipci_rate_freq(runtime->rate);
788         val = snd_cmipci_read(cm, CM_REG_FUNCTRL1);
789         if (rec->ch) {
790                 val &= ~CM_ASFC_MASK;
791                 val |= (freq << CM_ASFC_SHIFT) & CM_ASFC_MASK;
792         } else {
793                 val &= ~CM_DSFC_MASK;
794                 val |= (freq << CM_DSFC_SHIFT) & CM_DSFC_MASK;
795         }
796         snd_cmipci_write(cm, CM_REG_FUNCTRL1, val);
797         //snd_printd("cmipci: functrl1 = %08x\n", val);
798
799         /* set format */
800         val = snd_cmipci_read(cm, CM_REG_CHFORMAT);
801         if (rec->ch) {
802                 val &= ~CM_CH1FMT_MASK;
803                 val |= rec->fmt << CM_CH1FMT_SHIFT;
804         } else {
805                 val &= ~CM_CH0FMT_MASK;
806                 val |= rec->fmt << CM_CH0FMT_SHIFT;
807         }
808         snd_cmipci_write(cm, CM_REG_CHFORMAT, val);
809         //snd_printd("cmipci: chformat = %08x\n", val);
810
811         rec->running = 0;
812         spin_unlock_irq(&cm->reg_lock);
813
814         return 0;
815 }
816
817 /*
818  * PCM trigger/stop
819  */
820 static int snd_cmipci_pcm_trigger(struct cmipci *cm, struct cmipci_pcm *rec,
821                                   struct snd_pcm_substream *substream, int cmd)
822 {
823         unsigned int inthld, chen, reset, pause;
824         int result = 0;
825
826         inthld = CM_CH0_INT_EN << rec->ch;
827         chen = CM_CHEN0 << rec->ch;
828         reset = CM_RST_CH0 << rec->ch;
829         pause = CM_PAUSE0 << rec->ch;
830
831         spin_lock(&cm->reg_lock);
832         switch (cmd) {
833         case SNDRV_PCM_TRIGGER_START:
834                 rec->running = 1;
835                 /* set interrupt */
836                 snd_cmipci_set_bit(cm, CM_REG_INT_HLDCLR, inthld);
837                 cm->ctrl |= chen;
838                 /* enable channel */
839                 snd_cmipci_write(cm, CM_REG_FUNCTRL0, cm->ctrl);
840                 //snd_printd("cmipci: functrl0 = %08x\n", cm->ctrl);
841                 break;
842         case SNDRV_PCM_TRIGGER_STOP:
843                 rec->running = 0;
844                 /* disable interrupt */
845                 snd_cmipci_clear_bit(cm, CM_REG_INT_HLDCLR, inthld);
846                 /* reset */
847                 cm->ctrl &= ~chen;
848                 snd_cmipci_write(cm, CM_REG_FUNCTRL0, cm->ctrl | reset);
849                 snd_cmipci_write(cm, CM_REG_FUNCTRL0, cm->ctrl & ~reset);
850                 break;
851         case SNDRV_PCM_TRIGGER_PAUSE_PUSH:
852                 cm->ctrl |= pause;
853                 snd_cmipci_write(cm, CM_REG_FUNCTRL0, cm->ctrl);
854                 break;
855         case SNDRV_PCM_TRIGGER_PAUSE_RELEASE:
856                 cm->ctrl &= ~pause;
857                 snd_cmipci_write(cm, CM_REG_FUNCTRL0, cm->ctrl);
858                 break;
859         default:
860                 result = -EINVAL;
861                 break;
862         }
863         spin_unlock(&cm->reg_lock);
864         return result;
865 }
866
867 /*
868  * return the current pointer
869  */
870 static snd_pcm_uframes_t snd_cmipci_pcm_pointer(struct cmipci *cm, struct cmipci_pcm *rec,
871                                                 struct snd_pcm_substream *substream)
872 {
873         size_t ptr;
874         unsigned int reg;
875         if (!rec->running)
876                 return 0;
877 #if 1 // this seems better..
878         reg = rec->ch ? CM_REG_CH1_FRAME2 : CM_REG_CH0_FRAME2;
879         ptr = rec->dma_size - (snd_cmipci_read_w(cm, reg) + 1);
880         ptr >>= rec->shift;
881 #else
882         reg = rec->ch ? CM_REG_CH1_FRAME1 : CM_REG_CH0_FRAME1;
883         ptr = snd_cmipci_read(cm, reg) - rec->offset;
884         ptr = bytes_to_frames(substream->runtime, ptr);
885 #endif
886         if (substream->runtime->channels > 2)
887                 ptr = (ptr * 2) / substream->runtime->channels;
888         return ptr;
889 }
890
891 /*
892  * playback
893  */
894
895 static int snd_cmipci_playback_trigger(struct snd_pcm_substream *substream,
896                                        int cmd)
897 {
898         struct cmipci *cm = snd_pcm_substream_chip(substream);
899         return snd_cmipci_pcm_trigger(cm, &cm->channel[CM_CH_PLAY], substream, cmd);
900 }
901
902 static snd_pcm_uframes_t snd_cmipci_playback_pointer(struct snd_pcm_substream *substream)
903 {
904         struct cmipci *cm = snd_pcm_substream_chip(substream);
905         return snd_cmipci_pcm_pointer(cm, &cm->channel[CM_CH_PLAY], substream);
906 }
907
908
909
910 /*
911  * capture
912  */
913
914 static int snd_cmipci_capture_trigger(struct snd_pcm_substream *substream,
915                                      int cmd)
916 {
917         struct cmipci *cm = snd_pcm_substream_chip(substream);
918         return snd_cmipci_pcm_trigger(cm, &cm->channel[CM_CH_CAPT], substream, cmd);
919 }
920
921 static snd_pcm_uframes_t snd_cmipci_capture_pointer(struct snd_pcm_substream *substream)
922 {
923         struct cmipci *cm = snd_pcm_substream_chip(substream);
924         return snd_cmipci_pcm_pointer(cm, &cm->channel[CM_CH_CAPT], substream);
925 }
926
927
928 /*
929  * hw preparation for spdif
930  */
931
932 static int snd_cmipci_spdif_default_info(struct snd_kcontrol *kcontrol,
933                                          struct snd_ctl_elem_info *uinfo)
934 {
935         uinfo->type = SNDRV_CTL_ELEM_TYPE_IEC958;
936         uinfo->count = 1;
937         return 0;
938 }
939
940 static int snd_cmipci_spdif_default_get(struct snd_kcontrol *kcontrol,
941                                         struct snd_ctl_elem_value *ucontrol)
942 {
943         struct cmipci *chip = snd_kcontrol_chip(kcontrol);
944         int i;
945
946         spin_lock_irq(&chip->reg_lock);
947         for (i = 0; i < 4; i++)
948                 ucontrol->value.iec958.status[i] = (chip->dig_status >> (i * 8)) & 0xff;
949         spin_unlock_irq(&chip->reg_lock);
950         return 0;
951 }
952
953 static int snd_cmipci_spdif_default_put(struct snd_kcontrol *kcontrol,
954                                          struct snd_ctl_elem_value *ucontrol)
955 {
956         struct cmipci *chip = snd_kcontrol_chip(kcontrol);
957         int i, change;
958         unsigned int val;
959
960         val = 0;
961         spin_lock_irq(&chip->reg_lock);
962         for (i = 0; i < 4; i++)
963                 val |= (unsigned int)ucontrol->value.iec958.status[i] << (i * 8);
964         change = val != chip->dig_status;
965         chip->dig_status = val;
966         spin_unlock_irq(&chip->reg_lock);
967         return change;
968 }
969
970 static struct snd_kcontrol_new snd_cmipci_spdif_default __devinitdata =
971 {
972         .iface =        SNDRV_CTL_ELEM_IFACE_PCM,
973         .name =         SNDRV_CTL_NAME_IEC958("",PLAYBACK,DEFAULT),
974         .info =         snd_cmipci_spdif_default_info,
975         .get =          snd_cmipci_spdif_default_get,
976         .put =          snd_cmipci_spdif_default_put
977 };
978
979 static int snd_cmipci_spdif_mask_info(struct snd_kcontrol *kcontrol,
980                                       struct snd_ctl_elem_info *uinfo)
981 {
982         uinfo->type = SNDRV_CTL_ELEM_TYPE_IEC958;
983         uinfo->count = 1;
984         return 0;
985 }
986
987 static int snd_cmipci_spdif_mask_get(struct snd_kcontrol *kcontrol,
988                                      struct snd_ctl_elem_value *ucontrol)
989 {
990         ucontrol->value.iec958.status[0] = 0xff;
991         ucontrol->value.iec958.status[1] = 0xff;
992         ucontrol->value.iec958.status[2] = 0xff;
993         ucontrol->value.iec958.status[3] = 0xff;
994         return 0;
995 }
996
997 static struct snd_kcontrol_new snd_cmipci_spdif_mask __devinitdata =
998 {
999         .access =       SNDRV_CTL_ELEM_ACCESS_READ,
1000         .iface =        SNDRV_CTL_ELEM_IFACE_PCM,
1001         .name =         SNDRV_CTL_NAME_IEC958("",PLAYBACK,CON_MASK),
1002         .info =         snd_cmipci_spdif_mask_info,
1003         .get =          snd_cmipci_spdif_mask_get,
1004 };
1005
1006 static int snd_cmipci_spdif_stream_info(struct snd_kcontrol *kcontrol,
1007                                         struct snd_ctl_elem_info *uinfo)
1008 {
1009         uinfo->type = SNDRV_CTL_ELEM_TYPE_IEC958;
1010         uinfo->count = 1;
1011         return 0;
1012 }
1013
1014 static int snd_cmipci_spdif_stream_get(struct snd_kcontrol *kcontrol,
1015                                        struct snd_ctl_elem_value *ucontrol)
1016 {
1017         struct cmipci *chip = snd_kcontrol_chip(kcontrol);
1018         int i;
1019
1020         spin_lock_irq(&chip->reg_lock);
1021         for (i = 0; i < 4; i++)
1022                 ucontrol->value.iec958.status[i] = (chip->dig_pcm_status >> (i * 8)) & 0xff;
1023         spin_unlock_irq(&chip->reg_lock);
1024         return 0;
1025 }
1026
1027 static int snd_cmipci_spdif_stream_put(struct snd_kcontrol *kcontrol,
1028                                        struct snd_ctl_elem_value *ucontrol)
1029 {
1030         struct cmipci *chip = snd_kcontrol_chip(kcontrol);
1031         int i, change;
1032         unsigned int val;
1033
1034         val = 0;
1035         spin_lock_irq(&chip->reg_lock);
1036         for (i = 0; i < 4; i++)
1037                 val |= (unsigned int)ucontrol->value.iec958.status[i] << (i * 8);
1038         change = val != chip->dig_pcm_status;
1039         chip->dig_pcm_status = val;
1040         spin_unlock_irq(&chip->reg_lock);
1041         return change;
1042 }
1043
1044 static struct snd_kcontrol_new snd_cmipci_spdif_stream __devinitdata =
1045 {
1046         .access =       SNDRV_CTL_ELEM_ACCESS_READWRITE | SNDRV_CTL_ELEM_ACCESS_INACTIVE,
1047         .iface =        SNDRV_CTL_ELEM_IFACE_PCM,
1048         .name =         SNDRV_CTL_NAME_IEC958("",PLAYBACK,PCM_STREAM),
1049         .info =         snd_cmipci_spdif_stream_info,
1050         .get =          snd_cmipci_spdif_stream_get,
1051         .put =          snd_cmipci_spdif_stream_put
1052 };
1053
1054 /*
1055  */
1056
1057 /* save mixer setting and mute for AC3 playback */
1058 static int save_mixer_state(struct cmipci *cm)
1059 {
1060         if (! cm->mixer_insensitive) {
1061                 struct snd_ctl_elem_value *val;
1062                 unsigned int i;
1063
1064                 val = kmalloc(sizeof(*val), GFP_ATOMIC);
1065                 if (!val)
1066                         return -ENOMEM;
1067                 for (i = 0; i < CM_SAVED_MIXERS; i++) {
1068                         struct snd_kcontrol *ctl = cm->mixer_res_ctl[i];
1069                         if (ctl) {
1070                                 int event;
1071                                 memset(val, 0, sizeof(*val));
1072                                 ctl->get(ctl, val);
1073                                 cm->mixer_res_status[i] = val->value.integer.value[0];
1074                                 val->value.integer.value[0] = cm_saved_mixer[i].toggle_on;
1075                                 event = SNDRV_CTL_EVENT_MASK_INFO;
1076                                 if (cm->mixer_res_status[i] != val->value.integer.value[0]) {
1077                                         ctl->put(ctl, val); /* toggle */
1078                                         event |= SNDRV_CTL_EVENT_MASK_VALUE;
1079                                 }
1080                                 ctl->vd[0].access |= SNDRV_CTL_ELEM_ACCESS_INACTIVE;
1081                                 snd_ctl_notify(cm->card, event, &ctl->id);
1082                         }
1083                 }
1084                 kfree(val);
1085                 cm->mixer_insensitive = 1;
1086         }
1087         return 0;
1088 }
1089
1090
1091 /* restore the previously saved mixer status */
1092 static void restore_mixer_state(struct cmipci *cm)
1093 {
1094         if (cm->mixer_insensitive) {
1095                 struct snd_ctl_elem_value *val;
1096                 unsigned int i;
1097
1098                 val = kmalloc(sizeof(*val), GFP_KERNEL);
1099                 if (!val)
1100                         return;
1101                 cm->mixer_insensitive = 0; /* at first clear this;
1102                                               otherwise the changes will be ignored */
1103                 for (i = 0; i < CM_SAVED_MIXERS; i++) {
1104                         struct snd_kcontrol *ctl = cm->mixer_res_ctl[i];
1105                         if (ctl) {
1106                                 int event;
1107
1108                                 memset(val, 0, sizeof(*val));
1109                                 ctl->vd[0].access &= ~SNDRV_CTL_ELEM_ACCESS_INACTIVE;
1110                                 ctl->get(ctl, val);
1111                                 event = SNDRV_CTL_EVENT_MASK_INFO;
1112                                 if (val->value.integer.value[0] != cm->mixer_res_status[i]) {
1113                                         val->value.integer.value[0] = cm->mixer_res_status[i];
1114                                         ctl->put(ctl, val);
1115                                         event |= SNDRV_CTL_EVENT_MASK_VALUE;
1116                                 }
1117                                 snd_ctl_notify(cm->card, event, &ctl->id);
1118                         }
1119                 }
1120                 kfree(val);
1121         }
1122 }
1123
1124 /* spinlock held! */
1125 static void setup_ac3(struct cmipci *cm, struct snd_pcm_substream *subs, int do_ac3, int rate)
1126 {
1127         if (do_ac3) {
1128                 /* AC3EN for 037 */
1129                 snd_cmipci_set_bit(cm, CM_REG_CHFORMAT, CM_AC3EN1);
1130                 /* AC3EN for 039 */
1131                 snd_cmipci_set_bit(cm, CM_REG_MISC_CTRL, CM_AC3EN2);
1132         
1133                 if (cm->can_ac3_hw) {
1134                         /* SPD24SEL for 037, 0x02 */
1135                         /* SPD24SEL for 039, 0x20, but cannot be set */
1136                         snd_cmipci_set_bit(cm, CM_REG_CHFORMAT, CM_SPD24SEL);
1137                         snd_cmipci_clear_bit(cm, CM_REG_MISC_CTRL, CM_SPD32SEL);
1138                 } else { /* can_ac3_sw */
1139                         /* SPD32SEL for 037 & 039, 0x20 */
1140                         snd_cmipci_set_bit(cm, CM_REG_MISC_CTRL, CM_SPD32SEL);
1141                         /* set 176K sample rate to fix 033 HW bug */
1142                         if (cm->chip_version == 33) {
1143                                 if (rate >= 48000) {
1144                                         snd_cmipci_set_bit(cm, CM_REG_CHFORMAT, CM_PLAYBACK_SRATE_176K);
1145                                 } else {
1146                                         snd_cmipci_clear_bit(cm, CM_REG_CHFORMAT, CM_PLAYBACK_SRATE_176K);
1147                                 }
1148                         }
1149                 }
1150
1151         } else {
1152                 snd_cmipci_clear_bit(cm, CM_REG_CHFORMAT, CM_AC3EN1);
1153                 snd_cmipci_clear_bit(cm, CM_REG_MISC_CTRL, CM_AC3EN2);
1154
1155                 if (cm->can_ac3_hw) {
1156                         /* chip model >= 37 */
1157                         if (snd_pcm_format_width(subs->runtime->format) > 16) {
1158                                 snd_cmipci_set_bit(cm, CM_REG_MISC_CTRL, CM_SPD32SEL);
1159                                 snd_cmipci_set_bit(cm, CM_REG_CHFORMAT, CM_SPD24SEL);
1160                         } else {
1161                                 snd_cmipci_clear_bit(cm, CM_REG_MISC_CTRL, CM_SPD32SEL);
1162                                 snd_cmipci_clear_bit(cm, CM_REG_CHFORMAT, CM_SPD24SEL);
1163                         }
1164                 } else {
1165                         snd_cmipci_clear_bit(cm, CM_REG_MISC_CTRL, CM_SPD32SEL);
1166                         snd_cmipci_clear_bit(cm, CM_REG_CHFORMAT, CM_SPD24SEL);
1167                         snd_cmipci_clear_bit(cm, CM_REG_CHFORMAT, CM_PLAYBACK_SRATE_176K);
1168                 }
1169         }
1170 }
1171
1172 static int setup_spdif_playback(struct cmipci *cm, struct snd_pcm_substream *subs, int up, int do_ac3)
1173 {
1174         int rate, err;
1175
1176         rate = subs->runtime->rate;
1177
1178         if (up && do_ac3)
1179                 if ((err = save_mixer_state(cm)) < 0)
1180                         return err;
1181
1182         spin_lock_irq(&cm->reg_lock);
1183         cm->spdif_playback_avail = up;
1184         if (up) {
1185                 /* they are controlled via "IEC958 Output Switch" */
1186                 /* snd_cmipci_set_bit(cm, CM_REG_LEGACY_CTRL, CM_ENSPDOUT); */
1187                 /* snd_cmipci_set_bit(cm, CM_REG_FUNCTRL1, CM_SPDO2DAC); */
1188                 if (cm->spdif_playback_enabled)
1189                         snd_cmipci_set_bit(cm, CM_REG_FUNCTRL1, CM_PLAYBACK_SPDF);
1190                 setup_ac3(cm, subs, do_ac3, rate);
1191
1192                 if (rate == 48000)
1193                         snd_cmipci_set_bit(cm, CM_REG_MISC_CTRL, CM_SPDIF48K | CM_SPDF_AC97);
1194                 else
1195                         snd_cmipci_clear_bit(cm, CM_REG_MISC_CTRL, CM_SPDIF48K | CM_SPDF_AC97);
1196
1197         } else {
1198                 /* they are controlled via "IEC958 Output Switch" */
1199                 /* snd_cmipci_clear_bit(cm, CM_REG_LEGACY_CTRL, CM_ENSPDOUT); */
1200                 /* snd_cmipci_clear_bit(cm, CM_REG_FUNCTRL1, CM_SPDO2DAC); */
1201                 snd_cmipci_clear_bit(cm, CM_REG_FUNCTRL1, CM_PLAYBACK_SPDF);
1202                 setup_ac3(cm, subs, 0, 0);
1203         }
1204         spin_unlock_irq(&cm->reg_lock);
1205         return 0;
1206 }
1207
1208
1209 /*
1210  * preparation
1211  */
1212
1213 /* playback - enable spdif only on the certain condition */
1214 static int snd_cmipci_playback_prepare(struct snd_pcm_substream *substream)
1215 {
1216         struct cmipci *cm = snd_pcm_substream_chip(substream);
1217         int rate = substream->runtime->rate;
1218         int err, do_spdif, do_ac3 = 0;
1219
1220         do_spdif = ((rate == 44100 || rate == 48000) &&
1221                     substream->runtime->format == SNDRV_PCM_FORMAT_S16_LE &&
1222                     substream->runtime->channels == 2);
1223         if (do_spdif && cm->can_ac3_hw) 
1224                 do_ac3 = cm->dig_pcm_status & IEC958_AES0_NONAUDIO;
1225         if ((err = setup_spdif_playback(cm, substream, do_spdif, do_ac3)) < 0)
1226                 return err;
1227         return snd_cmipci_pcm_prepare(cm, &cm->channel[CM_CH_PLAY], substream);
1228 }
1229
1230 /* playback  (via device #2) - enable spdif always */
1231 static int snd_cmipci_playback_spdif_prepare(struct snd_pcm_substream *substream)
1232 {
1233         struct cmipci *cm = snd_pcm_substream_chip(substream);
1234         int err, do_ac3;
1235
1236         if (cm->can_ac3_hw) 
1237                 do_ac3 = cm->dig_pcm_status & IEC958_AES0_NONAUDIO;
1238         else
1239                 do_ac3 = 1; /* doesn't matter */
1240         if ((err = setup_spdif_playback(cm, substream, 1, do_ac3)) < 0)
1241                 return err;
1242         return snd_cmipci_pcm_prepare(cm, &cm->channel[CM_CH_PLAY], substream);
1243 }
1244
1245 static int snd_cmipci_playback_hw_free(struct snd_pcm_substream *substream)
1246 {
1247         struct cmipci *cm = snd_pcm_substream_chip(substream);
1248         setup_spdif_playback(cm, substream, 0, 0);
1249         restore_mixer_state(cm);
1250         return snd_cmipci_hw_free(substream);
1251 }
1252
1253 /* capture */
1254 static int snd_cmipci_capture_prepare(struct snd_pcm_substream *substream)
1255 {
1256         struct cmipci *cm = snd_pcm_substream_chip(substream);
1257         return snd_cmipci_pcm_prepare(cm, &cm->channel[CM_CH_CAPT], substream);
1258 }
1259
1260 /* capture with spdif (via device #2) */
1261 static int snd_cmipci_capture_spdif_prepare(struct snd_pcm_substream *substream)
1262 {
1263         struct cmipci *cm = snd_pcm_substream_chip(substream);
1264
1265         spin_lock_irq(&cm->reg_lock);
1266         snd_cmipci_set_bit(cm, CM_REG_FUNCTRL1, CM_CAPTURE_SPDF);
1267         spin_unlock_irq(&cm->reg_lock);
1268
1269         return snd_cmipci_pcm_prepare(cm, &cm->channel[CM_CH_CAPT], substream);
1270 }
1271
1272 static int snd_cmipci_capture_spdif_hw_free(struct snd_pcm_substream *subs)
1273 {
1274         struct cmipci *cm = snd_pcm_substream_chip(subs);
1275
1276         spin_lock_irq(&cm->reg_lock);
1277         snd_cmipci_clear_bit(cm, CM_REG_FUNCTRL1, CM_CAPTURE_SPDF);
1278         spin_unlock_irq(&cm->reg_lock);
1279
1280         return snd_cmipci_hw_free(subs);
1281 }
1282
1283
1284 /*
1285  * interrupt handler
1286  */
1287 static irqreturn_t snd_cmipci_interrupt(int irq, void *dev_id, struct pt_regs *regs)
1288 {
1289         struct cmipci *cm = dev_id;
1290         unsigned int status, mask = 0;
1291         
1292         /* fastpath out, to ease interrupt sharing */
1293         status = snd_cmipci_read(cm, CM_REG_INT_STATUS);
1294         if (!(status & CM_INTR))
1295                 return IRQ_NONE;
1296
1297         /* acknowledge interrupt */
1298         spin_lock(&cm->reg_lock);
1299         if (status & CM_CHINT0)
1300                 mask |= CM_CH0_INT_EN;
1301         if (status & CM_CHINT1)
1302                 mask |= CM_CH1_INT_EN;
1303         snd_cmipci_clear_bit(cm, CM_REG_INT_HLDCLR, mask);
1304         snd_cmipci_set_bit(cm, CM_REG_INT_HLDCLR, mask);
1305         spin_unlock(&cm->reg_lock);
1306
1307         if (cm->rmidi && (status & CM_UARTINT))
1308                 snd_mpu401_uart_interrupt(irq, cm->rmidi->private_data, regs);
1309
1310         if (cm->pcm) {
1311                 if ((status & CM_CHINT0) && cm->channel[0].running)
1312                         snd_pcm_period_elapsed(cm->channel[0].substream);
1313                 if ((status & CM_CHINT1) && cm->channel[1].running)
1314                         snd_pcm_period_elapsed(cm->channel[1].substream);
1315         }
1316         return IRQ_HANDLED;
1317 }
1318
1319 /*
1320  * h/w infos
1321  */
1322
1323 /* playback on channel A */
1324 static struct snd_pcm_hardware snd_cmipci_playback =
1325 {
1326         .info =                 (SNDRV_PCM_INFO_MMAP | SNDRV_PCM_INFO_INTERLEAVED |
1327                                  SNDRV_PCM_INFO_BLOCK_TRANSFER | SNDRV_PCM_INFO_PAUSE |
1328                                  SNDRV_PCM_INFO_MMAP_VALID),
1329         .formats =              SNDRV_PCM_FMTBIT_U8 | SNDRV_PCM_FMTBIT_S16_LE,
1330         .rates =                SNDRV_PCM_RATE_5512 | SNDRV_PCM_RATE_8000_48000,
1331         .rate_min =             5512,
1332         .rate_max =             48000,
1333         .channels_min =         1,
1334         .channels_max =         2,
1335         .buffer_bytes_max =     (128*1024),
1336         .period_bytes_min =     64,
1337         .period_bytes_max =     (128*1024),
1338         .periods_min =          2,
1339         .periods_max =          1024,
1340         .fifo_size =            0,
1341 };
1342
1343 /* capture on channel B */
1344 static struct snd_pcm_hardware snd_cmipci_capture =
1345 {
1346         .info =                 (SNDRV_PCM_INFO_MMAP | SNDRV_PCM_INFO_INTERLEAVED |
1347                                  SNDRV_PCM_INFO_BLOCK_TRANSFER | SNDRV_PCM_INFO_PAUSE |
1348                                  SNDRV_PCM_INFO_MMAP_VALID),
1349         .formats =              SNDRV_PCM_FMTBIT_U8 | SNDRV_PCM_FMTBIT_S16_LE,
1350         .rates =                SNDRV_PCM_RATE_5512 | SNDRV_PCM_RATE_8000_48000,
1351         .rate_min =             5512,
1352         .rate_max =             48000,
1353         .channels_min =         1,
1354         .channels_max =         2,
1355         .buffer_bytes_max =     (128*1024),
1356         .period_bytes_min =     64,
1357         .period_bytes_max =     (128*1024),
1358         .periods_min =          2,
1359         .periods_max =          1024,
1360         .fifo_size =            0,
1361 };
1362
1363 /* playback on channel B - stereo 16bit only? */
1364 static struct snd_pcm_hardware snd_cmipci_playback2 =
1365 {
1366         .info =                 (SNDRV_PCM_INFO_MMAP | SNDRV_PCM_INFO_INTERLEAVED |
1367                                  SNDRV_PCM_INFO_BLOCK_TRANSFER | SNDRV_PCM_INFO_PAUSE |
1368                                  SNDRV_PCM_INFO_MMAP_VALID),
1369         .formats =              SNDRV_PCM_FMTBIT_S16_LE,
1370         .rates =                SNDRV_PCM_RATE_5512 | SNDRV_PCM_RATE_8000_48000,
1371         .rate_min =             5512,
1372         .rate_max =             48000,
1373         .channels_min =         2,
1374         .channels_max =         2,
1375         .buffer_bytes_max =     (128*1024),
1376         .period_bytes_min =     64,
1377         .period_bytes_max =     (128*1024),
1378         .periods_min =          2,
1379         .periods_max =          1024,
1380         .fifo_size =            0,
1381 };
1382
1383 /* spdif playback on channel A */
1384 static struct snd_pcm_hardware snd_cmipci_playback_spdif =
1385 {
1386         .info =                 (SNDRV_PCM_INFO_MMAP | SNDRV_PCM_INFO_INTERLEAVED |
1387                                  SNDRV_PCM_INFO_BLOCK_TRANSFER | SNDRV_PCM_INFO_PAUSE |
1388                                  SNDRV_PCM_INFO_MMAP_VALID),
1389         .formats =              SNDRV_PCM_FMTBIT_S16_LE,
1390         .rates =                SNDRV_PCM_RATE_44100 | SNDRV_PCM_RATE_48000,
1391         .rate_min =             44100,
1392         .rate_max =             48000,
1393         .channels_min =         2,
1394         .channels_max =         2,
1395         .buffer_bytes_max =     (128*1024),
1396         .period_bytes_min =     64,
1397         .period_bytes_max =     (128*1024),
1398         .periods_min =          2,
1399         .periods_max =          1024,
1400         .fifo_size =            0,
1401 };
1402
1403 /* spdif playback on channel A (32bit, IEC958 subframes) */
1404 static struct snd_pcm_hardware snd_cmipci_playback_iec958_subframe =
1405 {
1406         .info =                 (SNDRV_PCM_INFO_MMAP | SNDRV_PCM_INFO_INTERLEAVED |
1407                                  SNDRV_PCM_INFO_BLOCK_TRANSFER | SNDRV_PCM_INFO_PAUSE |
1408                                  SNDRV_PCM_INFO_MMAP_VALID),
1409         .formats =              SNDRV_PCM_FMTBIT_IEC958_SUBFRAME_LE,
1410         .rates =                SNDRV_PCM_RATE_44100 | SNDRV_PCM_RATE_48000,
1411         .rate_min =             44100,
1412         .rate_max =             48000,
1413         .channels_min =         2,
1414         .channels_max =         2,
1415         .buffer_bytes_max =     (128*1024),
1416         .period_bytes_min =     64,
1417         .period_bytes_max =     (128*1024),
1418         .periods_min =          2,
1419         .periods_max =          1024,
1420         .fifo_size =            0,
1421 };
1422
1423 /* spdif capture on channel B */
1424 static struct snd_pcm_hardware snd_cmipci_capture_spdif =
1425 {
1426         .info =                 (SNDRV_PCM_INFO_MMAP | SNDRV_PCM_INFO_INTERLEAVED |
1427                                  SNDRV_PCM_INFO_BLOCK_TRANSFER | SNDRV_PCM_INFO_PAUSE |
1428                                  SNDRV_PCM_INFO_MMAP_VALID),
1429         .formats =              SNDRV_PCM_FMTBIT_S16_LE,
1430         .rates =                SNDRV_PCM_RATE_44100 | SNDRV_PCM_RATE_48000,
1431         .rate_min =             44100,
1432         .rate_max =             48000,
1433         .channels_min =         2,
1434         .channels_max =         2,
1435         .buffer_bytes_max =     (128*1024),
1436         .period_bytes_min =     64,
1437         .period_bytes_max =     (128*1024),
1438         .periods_min =          2,
1439         .periods_max =          1024,
1440         .fifo_size =            0,
1441 };
1442
1443 /*
1444  * check device open/close
1445  */
1446 static int open_device_check(struct cmipci *cm, int mode, struct snd_pcm_substream *subs)
1447 {
1448         int ch = mode & CM_OPEN_CH_MASK;
1449
1450         /* FIXME: a file should wait until the device becomes free
1451          * when it's opened on blocking mode.  however, since the current
1452          * pcm framework doesn't pass file pointer before actually opened,
1453          * we can't know whether blocking mode or not in open callback..
1454          */
1455         down(&cm->open_mutex);
1456         if (cm->opened[ch]) {
1457                 up(&cm->open_mutex);
1458                 return -EBUSY;
1459         }
1460         cm->opened[ch] = mode;
1461         cm->channel[ch].substream = subs;
1462         if (! (mode & CM_OPEN_DAC)) {
1463                 /* disable dual DAC mode */
1464                 cm->channel[ch].is_dac = 0;
1465                 spin_lock_irq(&cm->reg_lock);
1466                 snd_cmipci_clear_bit(cm, CM_REG_MISC_CTRL, CM_ENDBDAC);
1467                 spin_unlock_irq(&cm->reg_lock);
1468         }
1469         up(&cm->open_mutex);
1470         return 0;
1471 }
1472
1473 static void close_device_check(struct cmipci *cm, int mode)
1474 {
1475         int ch = mode & CM_OPEN_CH_MASK;
1476
1477         down(&cm->open_mutex);
1478         if (cm->opened[ch] == mode) {
1479                 if (cm->channel[ch].substream) {
1480                         snd_cmipci_ch_reset(cm, ch);
1481                         cm->channel[ch].running = 0;
1482                         cm->channel[ch].substream = NULL;
1483                 }
1484                 cm->opened[ch] = 0;
1485                 if (! cm->channel[ch].is_dac) {
1486                         /* enable dual DAC mode again */
1487                         cm->channel[ch].is_dac = 1;
1488                         spin_lock_irq(&cm->reg_lock);
1489                         snd_cmipci_set_bit(cm, CM_REG_MISC_CTRL, CM_ENDBDAC);
1490                         spin_unlock_irq(&cm->reg_lock);
1491                 }
1492         }
1493         up(&cm->open_mutex);
1494 }
1495
1496 /*
1497  */
1498
1499 static int snd_cmipci_playback_open(struct snd_pcm_substream *substream)
1500 {
1501         struct cmipci *cm = snd_pcm_substream_chip(substream);
1502         struct snd_pcm_runtime *runtime = substream->runtime;
1503         int err;
1504
1505         if ((err = open_device_check(cm, CM_OPEN_PLAYBACK, substream)) < 0)
1506                 return err;
1507         runtime->hw = snd_cmipci_playback;
1508         runtime->hw.channels_max = cm->max_channels;
1509         snd_pcm_hw_constraint_minmax(runtime, SNDRV_PCM_HW_PARAM_BUFFER_SIZE, 0, 0x10000);
1510         cm->dig_pcm_status = cm->dig_status;
1511         return 0;
1512 }
1513
1514 static int snd_cmipci_capture_open(struct snd_pcm_substream *substream)
1515 {
1516         struct cmipci *cm = snd_pcm_substream_chip(substream);
1517         struct snd_pcm_runtime *runtime = substream->runtime;
1518         int err;
1519
1520         if ((err = open_device_check(cm, CM_OPEN_CAPTURE, substream)) < 0)
1521                 return err;
1522         runtime->hw = snd_cmipci_capture;
1523         if (cm->chip_version == 68) {   // 8768 only supports 44k/48k recording
1524                 runtime->hw.rate_min = 41000;
1525                 runtime->hw.rates = SNDRV_PCM_RATE_44100 | SNDRV_PCM_RATE_48000;
1526         }
1527         snd_pcm_hw_constraint_minmax(runtime, SNDRV_PCM_HW_PARAM_BUFFER_SIZE, 0, 0x10000);
1528         return 0;
1529 }
1530
1531 static int snd_cmipci_playback2_open(struct snd_pcm_substream *substream)
1532 {
1533         struct cmipci *cm = snd_pcm_substream_chip(substream);
1534         struct snd_pcm_runtime *runtime = substream->runtime;
1535         int err;
1536
1537         if ((err = open_device_check(cm, CM_OPEN_PLAYBACK2, substream)) < 0) /* use channel B */
1538                 return err;
1539         runtime->hw = snd_cmipci_playback2;
1540         down(&cm->open_mutex);
1541         if (! cm->opened[CM_CH_PLAY]) {
1542                 if (cm->can_multi_ch) {
1543                         runtime->hw.channels_max = cm->max_channels;
1544                         if (cm->max_channels == 4)
1545                                 snd_pcm_hw_constraint_list(runtime, 0, SNDRV_PCM_HW_PARAM_CHANNELS, &hw_constraints_channels_4);
1546                         else if (cm->max_channels == 6)
1547                                 snd_pcm_hw_constraint_list(runtime, 0, SNDRV_PCM_HW_PARAM_CHANNELS, &hw_constraints_channels_6);
1548                         else if (cm->max_channels == 8)
1549                                 snd_pcm_hw_constraint_list(runtime, 0, SNDRV_PCM_HW_PARAM_CHANNELS, &hw_constraints_channels_8);
1550                 }
1551                 snd_pcm_hw_constraint_minmax(runtime, SNDRV_PCM_HW_PARAM_BUFFER_SIZE, 0, 0x10000);
1552         }
1553         up(&cm->open_mutex);
1554         return 0;
1555 }
1556
1557 static int snd_cmipci_playback_spdif_open(struct snd_pcm_substream *substream)
1558 {
1559         struct cmipci *cm = snd_pcm_substream_chip(substream);
1560         struct snd_pcm_runtime *runtime = substream->runtime;
1561         int err;
1562
1563         if ((err = open_device_check(cm, CM_OPEN_SPDIF_PLAYBACK, substream)) < 0) /* use channel A */
1564                 return err;
1565         if (cm->can_ac3_hw) {
1566                 runtime->hw = snd_cmipci_playback_spdif;
1567                 if (cm->chip_version >= 37)
1568                         runtime->hw.formats |= SNDRV_PCM_FMTBIT_S32_LE;
1569         } else {
1570                 runtime->hw = snd_cmipci_playback_iec958_subframe;
1571         }
1572         snd_pcm_hw_constraint_minmax(runtime, SNDRV_PCM_HW_PARAM_BUFFER_SIZE, 0, 0x40000);
1573         cm->dig_pcm_status = cm->dig_status;
1574         return 0;
1575 }
1576
1577 static int snd_cmipci_capture_spdif_open(struct snd_pcm_substream *substream)
1578 {
1579         struct cmipci *cm = snd_pcm_substream_chip(substream);
1580         struct snd_pcm_runtime *runtime = substream->runtime;
1581         int err;
1582
1583         if ((err = open_device_check(cm, CM_OPEN_SPDIF_CAPTURE, substream)) < 0) /* use channel B */
1584                 return err;
1585         runtime->hw = snd_cmipci_capture_spdif;
1586         snd_pcm_hw_constraint_minmax(runtime, SNDRV_PCM_HW_PARAM_BUFFER_SIZE, 0, 0x40000);
1587         return 0;
1588 }
1589
1590
1591 /*
1592  */
1593
1594 static int snd_cmipci_playback_close(struct snd_pcm_substream *substream)
1595 {
1596         struct cmipci *cm = snd_pcm_substream_chip(substream);
1597         close_device_check(cm, CM_OPEN_PLAYBACK);
1598         return 0;
1599 }
1600
1601 static int snd_cmipci_capture_close(struct snd_pcm_substream *substream)
1602 {
1603         struct cmipci *cm = snd_pcm_substream_chip(substream);
1604         close_device_check(cm, CM_OPEN_CAPTURE);
1605         return 0;
1606 }
1607
1608 static int snd_cmipci_playback2_close(struct snd_pcm_substream *substream)
1609 {
1610         struct cmipci *cm = snd_pcm_substream_chip(substream);
1611         close_device_check(cm, CM_OPEN_PLAYBACK2);
1612         close_device_check(cm, CM_OPEN_PLAYBACK_MULTI);
1613         return 0;
1614 }
1615
1616 static int snd_cmipci_playback_spdif_close(struct snd_pcm_substream *substream)
1617 {
1618         struct cmipci *cm = snd_pcm_substream_chip(substream);
1619         close_device_check(cm, CM_OPEN_SPDIF_PLAYBACK);
1620         return 0;
1621 }
1622
1623 static int snd_cmipci_capture_spdif_close(struct snd_pcm_substream *substream)
1624 {
1625         struct cmipci *cm = snd_pcm_substream_chip(substream);
1626         close_device_check(cm, CM_OPEN_SPDIF_CAPTURE);
1627         return 0;
1628 }
1629
1630
1631 /*
1632  */
1633
1634 static struct snd_pcm_ops snd_cmipci_playback_ops = {
1635         .open =         snd_cmipci_playback_open,
1636         .close =        snd_cmipci_playback_close,
1637         .ioctl =        snd_pcm_lib_ioctl,
1638         .hw_params =    snd_cmipci_hw_params,
1639         .hw_free =      snd_cmipci_playback_hw_free,
1640         .prepare =      snd_cmipci_playback_prepare,
1641         .trigger =      snd_cmipci_playback_trigger,
1642         .pointer =      snd_cmipci_playback_pointer,
1643 };
1644
1645 static struct snd_pcm_ops snd_cmipci_capture_ops = {
1646         .open =         snd_cmipci_capture_open,
1647         .close =        snd_cmipci_capture_close,
1648         .ioctl =        snd_pcm_lib_ioctl,
1649         .hw_params =    snd_cmipci_hw_params,
1650         .hw_free =      snd_cmipci_hw_free,
1651         .prepare =      snd_cmipci_capture_prepare,
1652         .trigger =      snd_cmipci_capture_trigger,
1653         .pointer =      snd_cmipci_capture_pointer,
1654 };
1655
1656 static struct snd_pcm_ops snd_cmipci_playback2_ops = {
1657         .open =         snd_cmipci_playback2_open,
1658         .close =        snd_cmipci_playback2_close,
1659         .ioctl =        snd_pcm_lib_ioctl,
1660         .hw_params =    snd_cmipci_playback2_hw_params,
1661         .hw_free =      snd_cmipci_hw_free,
1662         .prepare =      snd_cmipci_capture_prepare,     /* channel B */
1663         .trigger =      snd_cmipci_capture_trigger,     /* channel B */
1664         .pointer =      snd_cmipci_capture_pointer,     /* channel B */
1665 };
1666
1667 static struct snd_pcm_ops snd_cmipci_playback_spdif_ops = {
1668         .open =         snd_cmipci_playback_spdif_open,
1669         .close =        snd_cmipci_playback_spdif_close,
1670         .ioctl =        snd_pcm_lib_ioctl,
1671         .hw_params =    snd_cmipci_hw_params,
1672         .hw_free =      snd_cmipci_playback_hw_free,
1673         .prepare =      snd_cmipci_playback_spdif_prepare,      /* set up rate */
1674         .trigger =      snd_cmipci_playback_trigger,
1675         .pointer =      snd_cmipci_playback_pointer,
1676 };
1677
1678 static struct snd_pcm_ops snd_cmipci_capture_spdif_ops = {
1679         .open =         snd_cmipci_capture_spdif_open,
1680         .close =        snd_cmipci_capture_spdif_close,
1681         .ioctl =        snd_pcm_lib_ioctl,
1682         .hw_params =    snd_cmipci_hw_params,
1683         .hw_free =      snd_cmipci_capture_spdif_hw_free,
1684         .prepare =      snd_cmipci_capture_spdif_prepare,
1685         .trigger =      snd_cmipci_capture_trigger,
1686         .pointer =      snd_cmipci_capture_pointer,
1687 };
1688
1689
1690 /*
1691  */
1692
1693 static int __devinit snd_cmipci_pcm_new(struct cmipci *cm, int device)
1694 {
1695         struct snd_pcm *pcm;
1696         int err;
1697
1698         err = snd_pcm_new(cm->card, cm->card->driver, device, 1, 1, &pcm);
1699         if (err < 0)
1700                 return err;
1701
1702         snd_pcm_set_ops(pcm, SNDRV_PCM_STREAM_PLAYBACK, &snd_cmipci_playback_ops);
1703         snd_pcm_set_ops(pcm, SNDRV_PCM_STREAM_CAPTURE, &snd_cmipci_capture_ops);
1704
1705         pcm->private_data = cm;
1706         pcm->info_flags = 0;
1707         strcpy(pcm->name, "C-Media PCI DAC/ADC");
1708         cm->pcm = pcm;
1709
1710         snd_pcm_lib_preallocate_pages_for_all(pcm, SNDRV_DMA_TYPE_DEV,
1711                                               snd_dma_pci_data(cm->pci), 64*1024, 128*1024);
1712
1713         return 0;
1714 }
1715
1716 static int __devinit snd_cmipci_pcm2_new(struct cmipci *cm, int device)
1717 {
1718         struct snd_pcm *pcm;
1719         int err;
1720
1721         err = snd_pcm_new(cm->card, cm->card->driver, device, 1, 0, &pcm);
1722         if (err < 0)
1723                 return err;
1724
1725         snd_pcm_set_ops(pcm, SNDRV_PCM_STREAM_PLAYBACK, &snd_cmipci_playback2_ops);
1726
1727         pcm->private_data = cm;
1728         pcm->info_flags = 0;
1729         strcpy(pcm->name, "C-Media PCI 2nd DAC");
1730         cm->pcm2 = pcm;
1731
1732         snd_pcm_lib_preallocate_pages_for_all(pcm, SNDRV_DMA_TYPE_DEV,
1733                                               snd_dma_pci_data(cm->pci), 64*1024, 128*1024);
1734
1735         return 0;
1736 }
1737
1738 static int __devinit snd_cmipci_pcm_spdif_new(struct cmipci *cm, int device)
1739 {
1740         struct snd_pcm *pcm;
1741         int err;
1742
1743         err = snd_pcm_new(cm->card, cm->card->driver, device, 1, 1, &pcm);
1744         if (err < 0)
1745                 return err;
1746
1747         snd_pcm_set_ops(pcm, SNDRV_PCM_STREAM_PLAYBACK, &snd_cmipci_playback_spdif_ops);
1748         snd_pcm_set_ops(pcm, SNDRV_PCM_STREAM_CAPTURE, &snd_cmipci_capture_spdif_ops);
1749
1750         pcm->private_data = cm;
1751         pcm->info_flags = 0;
1752         strcpy(pcm->name, "C-Media PCI IEC958");
1753         cm->pcm_spdif = pcm;
1754
1755         snd_pcm_lib_preallocate_pages_for_all(pcm, SNDRV_DMA_TYPE_DEV,
1756                                               snd_dma_pci_data(cm->pci), 64*1024, 128*1024);
1757
1758         return 0;
1759 }
1760
1761 /*
1762  * mixer interface:
1763  * - CM8338/8738 has a compatible mixer interface with SB16, but
1764  *   lack of some elements like tone control, i/o gain and AGC.
1765  * - Access to native registers:
1766  *   - A 3D switch
1767  *   - Output mute switches
1768  */
1769
1770 static void snd_cmipci_mixer_write(struct cmipci *s, unsigned char idx, unsigned char data)
1771 {
1772         outb(idx, s->iobase + CM_REG_SB16_ADDR);
1773         outb(data, s->iobase + CM_REG_SB16_DATA);
1774 }
1775
1776 static unsigned char snd_cmipci_mixer_read(struct cmipci *s, unsigned char idx)
1777 {
1778         unsigned char v;
1779
1780         outb(idx, s->iobase + CM_REG_SB16_ADDR);
1781         v = inb(s->iobase + CM_REG_SB16_DATA);
1782         return v;
1783 }
1784
1785 /*
1786  * general mixer element
1787  */
1788 struct cmipci_sb_reg {
1789         unsigned int left_reg, right_reg;
1790         unsigned int left_shift, right_shift;
1791         unsigned int mask;
1792         unsigned int invert: 1;
1793         unsigned int stereo: 1;
1794 };
1795
1796 #define COMPOSE_SB_REG(lreg,rreg,lshift,rshift,mask,invert,stereo) \
1797  ((lreg) | ((rreg) << 8) | (lshift << 16) | (rshift << 19) | (mask << 24) | (invert << 22) | (stereo << 23))
1798
1799 #define CMIPCI_DOUBLE(xname, left_reg, right_reg, left_shift, right_shift, mask, invert, stereo) \
1800 { .iface = SNDRV_CTL_ELEM_IFACE_MIXER, .name = xname, \
1801   .info = snd_cmipci_info_volume, \
1802   .get = snd_cmipci_get_volume, .put = snd_cmipci_put_volume, \
1803   .private_value = COMPOSE_SB_REG(left_reg, right_reg, left_shift, right_shift, mask, invert, stereo), \
1804 }
1805
1806 #define CMIPCI_SB_VOL_STEREO(xname,reg,shift,mask) CMIPCI_DOUBLE(xname, reg, reg+1, shift, shift, mask, 0, 1)
1807 #define CMIPCI_SB_VOL_MONO(xname,reg,shift,mask) CMIPCI_DOUBLE(xname, reg, reg, shift, shift, mask, 0, 0)
1808 #define CMIPCI_SB_SW_STEREO(xname,lshift,rshift) CMIPCI_DOUBLE(xname, SB_DSP4_OUTPUT_SW, SB_DSP4_OUTPUT_SW, lshift, rshift, 1, 0, 1)
1809 #define CMIPCI_SB_SW_MONO(xname,shift) CMIPCI_DOUBLE(xname, SB_DSP4_OUTPUT_SW, SB_DSP4_OUTPUT_SW, shift, shift, 1, 0, 0)
1810
1811 static void cmipci_sb_reg_decode(struct cmipci_sb_reg *r, unsigned long val)
1812 {
1813         r->left_reg = val & 0xff;
1814         r->right_reg = (val >> 8) & 0xff;
1815         r->left_shift = (val >> 16) & 0x07;
1816         r->right_shift = (val >> 19) & 0x07;
1817         r->invert = (val >> 22) & 1;
1818         r->stereo = (val >> 23) & 1;
1819         r->mask = (val >> 24) & 0xff;
1820 }
1821
1822 static int snd_cmipci_info_volume(struct snd_kcontrol *kcontrol,
1823                                   struct snd_ctl_elem_info *uinfo)
1824 {
1825         struct cmipci_sb_reg reg;
1826
1827         cmipci_sb_reg_decode(&reg, kcontrol->private_value);
1828         uinfo->type = reg.mask == 1 ? SNDRV_CTL_ELEM_TYPE_BOOLEAN : SNDRV_CTL_ELEM_TYPE_INTEGER;
1829         uinfo->count = reg.stereo + 1;
1830         uinfo->value.integer.min = 0;
1831         uinfo->value.integer.max = reg.mask;
1832         return 0;
1833 }
1834  
1835 static int snd_cmipci_get_volume(struct snd_kcontrol *kcontrol,
1836                                  struct snd_ctl_elem_value *ucontrol)
1837 {
1838         struct cmipci *cm = snd_kcontrol_chip(kcontrol);
1839         struct cmipci_sb_reg reg;
1840         int val;
1841
1842         cmipci_sb_reg_decode(&reg, kcontrol->private_value);
1843         spin_lock_irq(&cm->reg_lock);
1844         val = (snd_cmipci_mixer_read(cm, reg.left_reg) >> reg.left_shift) & reg.mask;
1845         if (reg.invert)
1846                 val = reg.mask - val;
1847         ucontrol->value.integer.value[0] = val;
1848         if (reg.stereo) {
1849                 val = (snd_cmipci_mixer_read(cm, reg.right_reg) >> reg.right_shift) & reg.mask;
1850                 if (reg.invert)
1851                         val = reg.mask - val;
1852                  ucontrol->value.integer.value[1] = val;
1853         }
1854         spin_unlock_irq(&cm->reg_lock);
1855         return 0;
1856 }
1857
1858 static int snd_cmipci_put_volume(struct snd_kcontrol *kcontrol,
1859                                  struct snd_ctl_elem_value *ucontrol)
1860 {
1861         struct cmipci *cm = snd_kcontrol_chip(kcontrol);
1862         struct cmipci_sb_reg reg;
1863         int change;
1864         int left, right, oleft, oright;
1865
1866         cmipci_sb_reg_decode(&reg, kcontrol->private_value);
1867         left = ucontrol->value.integer.value[0] & reg.mask;
1868         if (reg.invert)
1869                 left = reg.mask - left;
1870         left <<= reg.left_shift;
1871         if (reg.stereo) {
1872                 right = ucontrol->value.integer.value[1] & reg.mask;
1873                 if (reg.invert)
1874                         right = reg.mask - right;
1875                 right <<= reg.right_shift;
1876         } else
1877                 right = 0;
1878         spin_lock_irq(&cm->reg_lock);
1879         oleft = snd_cmipci_mixer_read(cm, reg.left_reg);
1880         left |= oleft & ~(reg.mask << reg.left_shift);
1881         change = left != oleft;
1882         if (reg.stereo) {
1883                 if (reg.left_reg != reg.right_reg) {
1884                         snd_cmipci_mixer_write(cm, reg.left_reg, left);
1885                         oright = snd_cmipci_mixer_read(cm, reg.right_reg);
1886                 } else
1887                         oright = left;
1888                 right |= oright & ~(reg.mask << reg.right_shift);
1889                 change |= right != oright;
1890                 snd_cmipci_mixer_write(cm, reg.right_reg, right);
1891         } else
1892                 snd_cmipci_mixer_write(cm, reg.left_reg, left);
1893         spin_unlock_irq(&cm->reg_lock);
1894         return change;
1895 }
1896
1897 /*
1898  * input route (left,right) -> (left,right)
1899  */
1900 #define CMIPCI_SB_INPUT_SW(xname, left_shift, right_shift) \
1901 { .iface = SNDRV_CTL_ELEM_IFACE_MIXER, .name = xname, \
1902   .info = snd_cmipci_info_input_sw, \
1903   .get = snd_cmipci_get_input_sw, .put = snd_cmipci_put_input_sw, \
1904   .private_value = COMPOSE_SB_REG(SB_DSP4_INPUT_LEFT, SB_DSP4_INPUT_RIGHT, left_shift, right_shift, 1, 0, 1), \
1905 }
1906
1907 static int snd_cmipci_info_input_sw(struct snd_kcontrol *kcontrol,
1908                                     struct snd_ctl_elem_info *uinfo)
1909 {
1910         uinfo->type = SNDRV_CTL_ELEM_TYPE_BOOLEAN;
1911         uinfo->count = 4;
1912         uinfo->value.integer.min = 0;
1913         uinfo->value.integer.max = 1;
1914         return 0;
1915 }
1916  
1917 static int snd_cmipci_get_input_sw(struct snd_kcontrol *kcontrol,
1918                                    struct snd_ctl_elem_value *ucontrol)
1919 {
1920         struct cmipci *cm = snd_kcontrol_chip(kcontrol);
1921         struct cmipci_sb_reg reg;
1922         int val1, val2;
1923
1924         cmipci_sb_reg_decode(&reg, kcontrol->private_value);
1925         spin_lock_irq(&cm->reg_lock);
1926         val1 = snd_cmipci_mixer_read(cm, reg.left_reg);
1927         val2 = snd_cmipci_mixer_read(cm, reg.right_reg);
1928         spin_unlock_irq(&cm->reg_lock);
1929         ucontrol->value.integer.value[0] = (val1 >> reg.left_shift) & 1;
1930         ucontrol->value.integer.value[1] = (val2 >> reg.left_shift) & 1;
1931         ucontrol->value.integer.value[2] = (val1 >> reg.right_shift) & 1;
1932         ucontrol->value.integer.value[3] = (val2 >> reg.right_shift) & 1;
1933         return 0;
1934 }
1935
1936 static int snd_cmipci_put_input_sw(struct snd_kcontrol *kcontrol,
1937                                    struct snd_ctl_elem_value *ucontrol)
1938 {
1939         struct cmipci *cm = snd_kcontrol_chip(kcontrol);
1940         struct cmipci_sb_reg reg;
1941         int change;
1942         int val1, val2, oval1, oval2;
1943
1944         cmipci_sb_reg_decode(&reg, kcontrol->private_value);
1945         spin_lock_irq(&cm->reg_lock);
1946         oval1 = snd_cmipci_mixer_read(cm, reg.left_reg);
1947         oval2 = snd_cmipci_mixer_read(cm, reg.right_reg);
1948         val1 = oval1 & ~((1 << reg.left_shift) | (1 << reg.right_shift));
1949         val2 = oval2 & ~((1 << reg.left_shift) | (1 << reg.right_shift));
1950         val1 |= (ucontrol->value.integer.value[0] & 1) << reg.left_shift;
1951         val2 |= (ucontrol->value.integer.value[1] & 1) << reg.left_shift;
1952         val1 |= (ucontrol->value.integer.value[2] & 1) << reg.right_shift;
1953         val2 |= (ucontrol->value.integer.value[3] & 1) << reg.right_shift;
1954         change = val1 != oval1 || val2 != oval2;
1955         snd_cmipci_mixer_write(cm, reg.left_reg, val1);
1956         snd_cmipci_mixer_write(cm, reg.right_reg, val2);
1957         spin_unlock_irq(&cm->reg_lock);
1958         return change;
1959 }
1960
1961 /*
1962  * native mixer switches/volumes
1963  */
1964
1965 #define CMIPCI_MIXER_SW_STEREO(xname, reg, lshift, rshift, invert) \
1966 { .iface = SNDRV_CTL_ELEM_IFACE_MIXER, .name = xname, \
1967   .info = snd_cmipci_info_native_mixer, \
1968   .get = snd_cmipci_get_native_mixer, .put = snd_cmipci_put_native_mixer, \
1969   .private_value = COMPOSE_SB_REG(reg, reg, lshift, rshift, 1, invert, 1), \
1970 }
1971
1972 #define CMIPCI_MIXER_SW_MONO(xname, reg, shift, invert) \
1973 { .iface = SNDRV_CTL_ELEM_IFACE_MIXER, .name = xname, \
1974   .info = snd_cmipci_info_native_mixer, \
1975   .get = snd_cmipci_get_native_mixer, .put = snd_cmipci_put_native_mixer, \
1976   .private_value = COMPOSE_SB_REG(reg, reg, shift, shift, 1, invert, 0), \
1977 }
1978
1979 #define CMIPCI_MIXER_VOL_STEREO(xname, reg, lshift, rshift, mask) \
1980 { .iface = SNDRV_CTL_ELEM_IFACE_MIXER, .name = xname, \
1981   .info = snd_cmipci_info_native_mixer, \
1982   .get = snd_cmipci_get_native_mixer, .put = snd_cmipci_put_native_mixer, \
1983   .private_value = COMPOSE_SB_REG(reg, reg, lshift, rshift, mask, 0, 1), \
1984 }
1985
1986 #define CMIPCI_MIXER_VOL_MONO(xname, reg, shift, mask) \
1987 { .iface = SNDRV_CTL_ELEM_IFACE_MIXER, .name = xname, \
1988   .info = snd_cmipci_info_native_mixer, \
1989   .get = snd_cmipci_get_native_mixer, .put = snd_cmipci_put_native_mixer, \
1990   .private_value = COMPOSE_SB_REG(reg, reg, shift, shift, mask, 0, 0), \
1991 }
1992
1993 static int snd_cmipci_info_native_mixer(struct snd_kcontrol *kcontrol,
1994                                         struct snd_ctl_elem_info *uinfo)
1995 {
1996         struct cmipci_sb_reg reg;
1997
1998         cmipci_sb_reg_decode(&reg, kcontrol->private_value);
1999         uinfo->type = reg.mask == 1 ? SNDRV_CTL_ELEM_TYPE_BOOLEAN : SNDRV_CTL_ELEM_TYPE_INTEGER;
2000         uinfo->count = reg.stereo + 1;
2001         uinfo->value.integer.min = 0;
2002         uinfo->value.integer.max = reg.mask;
2003         return 0;
2004
2005 }
2006
2007 static int snd_cmipci_get_native_mixer(struct snd_kcontrol *kcontrol,
2008                                        struct snd_ctl_elem_value *ucontrol)
2009 {
2010         struct cmipci *cm = snd_kcontrol_chip(kcontrol);
2011         struct cmipci_sb_reg reg;
2012         unsigned char oreg, val;
2013
2014         cmipci_sb_reg_decode(&reg, kcontrol->private_value);
2015         spin_lock_irq(&cm->reg_lock);
2016         oreg = inb(cm->iobase + reg.left_reg);
2017         val = (oreg >> reg.left_shift) & reg.mask;
2018         if (reg.invert)
2019                 val = reg.mask - val;
2020         ucontrol->value.integer.value[0] = val;
2021         if (reg.stereo) {
2022                 val = (oreg >> reg.right_shift) & reg.mask;
2023                 if (reg.invert)
2024                         val = reg.mask - val;
2025                 ucontrol->value.integer.value[1] = val;
2026         }
2027         spin_unlock_irq(&cm->reg_lock);
2028         return 0;
2029 }
2030
2031 static int snd_cmipci_put_native_mixer(struct snd_kcontrol *kcontrol,
2032                                        struct snd_ctl_elem_value *ucontrol)
2033 {
2034         struct cmipci *cm = snd_kcontrol_chip(kcontrol);
2035         struct cmipci_sb_reg reg;
2036         unsigned char oreg, nreg, val;
2037
2038         cmipci_sb_reg_decode(&reg, kcontrol->private_value);
2039         spin_lock_irq(&cm->reg_lock);
2040         oreg = inb(cm->iobase + reg.left_reg);
2041         val = ucontrol->value.integer.value[0] & reg.mask;
2042         if (reg.invert)
2043                 val = reg.mask - val;
2044         nreg = oreg & ~(reg.mask << reg.left_shift);
2045         nreg |= (val << reg.left_shift);
2046         if (reg.stereo) {
2047                 val = ucontrol->value.integer.value[1] & reg.mask;
2048                 if (reg.invert)
2049                         val = reg.mask - val;
2050                 nreg &= ~(reg.mask << reg.right_shift);
2051                 nreg |= (val << reg.right_shift);
2052         }
2053         outb(nreg, cm->iobase + reg.left_reg);
2054         spin_unlock_irq(&cm->reg_lock);
2055         return (nreg != oreg);
2056 }
2057
2058 /*
2059  * special case - check mixer sensitivity
2060  */
2061 static int snd_cmipci_get_native_mixer_sensitive(struct snd_kcontrol *kcontrol,
2062                                                  struct snd_ctl_elem_value *ucontrol)
2063 {
2064         //struct cmipci *cm = snd_kcontrol_chip(kcontrol);
2065         return snd_cmipci_get_native_mixer(kcontrol, ucontrol);
2066 }
2067
2068 static int snd_cmipci_put_native_mixer_sensitive(struct snd_kcontrol *kcontrol,
2069                                                  struct snd_ctl_elem_value *ucontrol)
2070 {
2071         struct cmipci *cm = snd_kcontrol_chip(kcontrol);
2072         if (cm->mixer_insensitive) {
2073                 /* ignored */
2074                 return 0;
2075         }
2076         return snd_cmipci_put_native_mixer(kcontrol, ucontrol);
2077 }
2078
2079
2080 static struct snd_kcontrol_new snd_cmipci_mixers[] __devinitdata = {
2081         CMIPCI_SB_VOL_STEREO("Master Playback Volume", SB_DSP4_MASTER_DEV, 3, 31),
2082         CMIPCI_MIXER_SW_MONO("3D Control - Switch", CM_REG_MIXER1, CM_X3DEN_SHIFT, 0),
2083         CMIPCI_SB_VOL_STEREO("PCM Playback Volume", SB_DSP4_PCM_DEV, 3, 31),
2084         //CMIPCI_MIXER_SW_MONO("PCM Playback Switch", CM_REG_MIXER1, CM_WSMUTE_SHIFT, 1),
2085         { /* switch with sensitivity */
2086                 .iface = SNDRV_CTL_ELEM_IFACE_MIXER,
2087                 .name = "PCM Playback Switch",
2088                 .info = snd_cmipci_info_native_mixer,
2089                 .get = snd_cmipci_get_native_mixer_sensitive,
2090                 .put = snd_cmipci_put_native_mixer_sensitive,
2091                 .private_value = COMPOSE_SB_REG(CM_REG_MIXER1, CM_REG_MIXER1, CM_WSMUTE_SHIFT, CM_WSMUTE_SHIFT, 1, 1, 0),
2092         },
2093         CMIPCI_MIXER_SW_STEREO("PCM Capture Switch", CM_REG_MIXER1, CM_WAVEINL_SHIFT, CM_WAVEINR_SHIFT, 0),
2094         CMIPCI_SB_VOL_STEREO("Synth Playback Volume", SB_DSP4_SYNTH_DEV, 3, 31),
2095         CMIPCI_MIXER_SW_MONO("Synth Playback Switch", CM_REG_MIXER1, CM_FMMUTE_SHIFT, 1),
2096         CMIPCI_SB_INPUT_SW("Synth Capture Route", 6, 5),
2097         CMIPCI_SB_VOL_STEREO("CD Playback Volume", SB_DSP4_CD_DEV, 3, 31),
2098         CMIPCI_SB_SW_STEREO("CD Playback Switch", 2, 1),
2099         CMIPCI_SB_INPUT_SW("CD Capture Route", 2, 1),
2100         CMIPCI_SB_VOL_STEREO("Line Playback Volume", SB_DSP4_LINE_DEV, 3, 31),
2101         CMIPCI_SB_SW_STEREO("Line Playback Switch", 4, 3),
2102         CMIPCI_SB_INPUT_SW("Line Capture Route", 4, 3),
2103         CMIPCI_SB_VOL_MONO("Mic Playback Volume", SB_DSP4_MIC_DEV, 3, 31),
2104         CMIPCI_SB_SW_MONO("Mic Playback Switch", 0),
2105         CMIPCI_DOUBLE("Mic Capture Switch", SB_DSP4_INPUT_LEFT, SB_DSP4_INPUT_RIGHT, 0, 0, 1, 0, 0),
2106         CMIPCI_SB_VOL_MONO("PC Speaker Playback Volume", SB_DSP4_SPEAKER_DEV, 6, 3),
2107         CMIPCI_MIXER_VOL_STEREO("Aux Playback Volume", CM_REG_AUX_VOL, 4, 0, 15),
2108         CMIPCI_MIXER_SW_STEREO("Aux Playback Switch", CM_REG_MIXER2, CM_VAUXLM_SHIFT, CM_VAUXRM_SHIFT, 0),
2109         CMIPCI_MIXER_SW_STEREO("Aux Capture Switch", CM_REG_MIXER2, CM_RAUXLEN_SHIFT, CM_RAUXREN_SHIFT, 0),
2110         CMIPCI_MIXER_SW_MONO("Mic Boost Playback Switch", CM_REG_MIXER2, CM_MICGAINZ_SHIFT, 1),
2111         CMIPCI_MIXER_VOL_MONO("Mic Capture Volume", CM_REG_MIXER2, CM_VADMIC_SHIFT, 7),
2112         CMIPCI_SB_VOL_MONO("Phone Playback Volume", CM_REG_EXTENT_IND, 5, 7),
2113         CMIPCI_DOUBLE("Phone Playback Switch", CM_REG_EXTENT_IND, CM_REG_EXTENT_IND, 4, 4, 1, 0, 0),
2114         CMIPCI_DOUBLE("PC Speaker Playnack Switch", CM_REG_EXTENT_IND, CM_REG_EXTENT_IND, 3, 3, 1, 0, 0),
2115         CMIPCI_DOUBLE("Mic Boost Capture Switch", CM_REG_EXTENT_IND, CM_REG_EXTENT_IND, 0, 0, 1, 0, 0),
2116 };
2117
2118 /*
2119  * other switches
2120  */
2121
2122 struct cmipci_switch_args {
2123         int reg;                /* register index */
2124         unsigned int mask;      /* mask bits */
2125         unsigned int mask_on;   /* mask bits to turn on */
2126         unsigned int is_byte: 1;                /* byte access? */
2127         unsigned int ac3_sensitive: 1;  /* access forbidden during
2128                                          * non-audio operation?
2129                                          */
2130 };
2131
2132 static int snd_cmipci_uswitch_info(struct snd_kcontrol *kcontrol,
2133                                    struct snd_ctl_elem_info *uinfo)
2134 {
2135         uinfo->type = SNDRV_CTL_ELEM_TYPE_BOOLEAN;
2136         uinfo->count = 1;
2137         uinfo->value.integer.min = 0;
2138         uinfo->value.integer.max = 1;
2139         return 0;
2140 }
2141
2142 static int _snd_cmipci_uswitch_get(struct snd_kcontrol *kcontrol,
2143                                    struct snd_ctl_elem_value *ucontrol,
2144                                    struct cmipci_switch_args *args)
2145 {
2146         unsigned int val;
2147         struct cmipci *cm = snd_kcontrol_chip(kcontrol);
2148
2149         spin_lock_irq(&cm->reg_lock);
2150         if (args->ac3_sensitive && cm->mixer_insensitive) {
2151                 ucontrol->value.integer.value[0] = 0;
2152                 spin_unlock_irq(&cm->reg_lock);
2153                 return 0;
2154         }
2155         if (args->is_byte)
2156                 val = inb(cm->iobase + args->reg);
2157         else
2158                 val = snd_cmipci_read(cm, args->reg);
2159         ucontrol->value.integer.value[0] = ((val & args->mask) == args->mask_on) ? 1 : 0;
2160         spin_unlock_irq(&cm->reg_lock);
2161         return 0;
2162 }
2163
2164 static int snd_cmipci_uswitch_get(struct snd_kcontrol *kcontrol,
2165                                   struct snd_ctl_elem_value *ucontrol)
2166 {
2167         struct cmipci_switch_args *args;
2168         args = (struct cmipci_switch_args *)kcontrol->private_value;
2169         snd_assert(args != NULL, return -EINVAL);
2170         return _snd_cmipci_uswitch_get(kcontrol, ucontrol, args);
2171 }
2172
2173 static int _snd_cmipci_uswitch_put(struct snd_kcontrol *kcontrol,
2174                                    struct snd_ctl_elem_value *ucontrol,
2175                                    struct cmipci_switch_args *args)
2176 {
2177         unsigned int val;
2178         int change;
2179         struct cmipci *cm = snd_kcontrol_chip(kcontrol);
2180
2181         spin_lock_irq(&cm->reg_lock);
2182         if (args->ac3_sensitive && cm->mixer_insensitive) {
2183                 /* ignored */
2184                 spin_unlock_irq(&cm->reg_lock);
2185                 return 0;
2186         }
2187         if (args->is_byte)
2188                 val = inb(cm->iobase + args->reg);
2189         else
2190                 val = snd_cmipci_read(cm, args->reg);
2191         change = (val & args->mask) != (ucontrol->value.integer.value[0] ? args->mask : 0);
2192         if (change) {
2193                 val &= ~args->mask;
2194                 if (ucontrol->value.integer.value[0])
2195                         val |= args->mask_on;
2196                 else
2197                         val |= (args->mask & ~args->mask_on);
2198                 if (args->is_byte)
2199                         outb((unsigned char)val, cm->iobase + args->reg);
2200                 else
2201                         snd_cmipci_write(cm, args->reg, val);
2202         }
2203         spin_unlock_irq(&cm->reg_lock);
2204         return change;
2205 }
2206
2207 static int snd_cmipci_uswitch_put(struct snd_kcontrol *kcontrol,
2208                                   struct snd_ctl_elem_value *ucontrol)
2209 {
2210         struct cmipci_switch_args *args;
2211         args = (struct cmipci_switch_args *)kcontrol->private_value;
2212         snd_assert(args != NULL, return -EINVAL);
2213         return _snd_cmipci_uswitch_put(kcontrol, ucontrol, args);
2214 }
2215
2216 #define DEFINE_SWITCH_ARG(sname, xreg, xmask, xmask_on, xis_byte, xac3) \
2217 static struct cmipci_switch_args cmipci_switch_arg_##sname = { \
2218   .reg = xreg, \
2219   .mask = xmask, \
2220   .mask_on = xmask_on, \
2221   .is_byte = xis_byte, \
2222   .ac3_sensitive = xac3, \
2223 }
2224         
2225 #define DEFINE_BIT_SWITCH_ARG(sname, xreg, xmask, xis_byte, xac3) \
2226         DEFINE_SWITCH_ARG(sname, xreg, xmask, xmask, xis_byte, xac3)
2227
2228 #if 0 /* these will be controlled in pcm device */
2229 DEFINE_BIT_SWITCH_ARG(spdif_in, CM_REG_FUNCTRL1, CM_SPDF_1, 0, 0);
2230 DEFINE_BIT_SWITCH_ARG(spdif_out, CM_REG_FUNCTRL1, CM_SPDF_0, 0, 0);
2231 #endif
2232 DEFINE_BIT_SWITCH_ARG(spdif_in_sel1, CM_REG_CHFORMAT, CM_SPDIF_SELECT1, 0, 0);
2233 DEFINE_BIT_SWITCH_ARG(spdif_in_sel2, CM_REG_MISC_CTRL, CM_SPDIF_SELECT2, 0, 0);
2234 DEFINE_BIT_SWITCH_ARG(spdif_enable, CM_REG_LEGACY_CTRL, CM_ENSPDOUT, 0, 0);
2235 DEFINE_BIT_SWITCH_ARG(spdo2dac, CM_REG_FUNCTRL1, CM_SPDO2DAC, 0, 1);
2236 DEFINE_BIT_SWITCH_ARG(spdi_valid, CM_REG_MISC, CM_SPDVALID, 1, 0);
2237 DEFINE_BIT_SWITCH_ARG(spdif_copyright, CM_REG_LEGACY_CTRL, CM_SPDCOPYRHT, 0, 0);
2238 DEFINE_BIT_SWITCH_ARG(spdif_dac_out, CM_REG_LEGACY_CTRL, CM_DAC2SPDO, 0, 1);
2239 DEFINE_SWITCH_ARG(spdo_5v, CM_REG_MISC_CTRL, CM_SPDO5V, 0, 0, 0); /* inverse: 0 = 5V */
2240 // DEFINE_BIT_SWITCH_ARG(spdo_48k, CM_REG_MISC_CTRL, CM_SPDF_AC97|CM_SPDIF48K, 0, 1);
2241 DEFINE_BIT_SWITCH_ARG(spdif_loop, CM_REG_FUNCTRL1, CM_SPDFLOOP, 0, 1);
2242 DEFINE_BIT_SWITCH_ARG(spdi_monitor, CM_REG_MIXER1, CM_CDPLAY, 1, 0);
2243 /* DEFINE_BIT_SWITCH_ARG(spdi_phase, CM_REG_CHFORMAT, CM_SPDIF_INVERSE, 0, 0); */
2244 DEFINE_BIT_SWITCH_ARG(spdi_phase, CM_REG_MISC, CM_SPDIF_INVERSE, 1, 0);
2245 DEFINE_BIT_SWITCH_ARG(spdi_phase2, CM_REG_CHFORMAT, CM_SPDIF_INVERSE2, 0, 0);
2246 #if CM_CH_PLAY == 1
2247 DEFINE_SWITCH_ARG(exchange_dac, CM_REG_MISC_CTRL, CM_XCHGDAC, 0, 0, 0); /* reversed */
2248 #else
2249 DEFINE_SWITCH_ARG(exchange_dac, CM_REG_MISC_CTRL, CM_XCHGDAC, CM_XCHGDAC, 0, 0);
2250 #endif
2251 DEFINE_BIT_SWITCH_ARG(fourch, CM_REG_MISC_CTRL, CM_N4SPK3D, 0, 0);
2252 // DEFINE_BIT_SWITCH_ARG(line_rear, CM_REG_MIXER1, CM_SPK4, 1, 0);
2253 // DEFINE_BIT_SWITCH_ARG(line_bass, CM_REG_LEGACY_CTRL, CM_LINE_AS_BASS, 0, 0);
2254 // DEFINE_BIT_SWITCH_ARG(joystick, CM_REG_FUNCTRL1, CM_JYSTK_EN, 0, 0); /* now module option */
2255 DEFINE_SWITCH_ARG(modem, CM_REG_MISC_CTRL, CM_FLINKON|CM_FLINKOFF, CM_FLINKON, 0, 0);
2256
2257 #define DEFINE_SWITCH(sname, stype, sarg) \
2258 { .name = sname, \
2259   .iface = stype, \
2260   .info = snd_cmipci_uswitch_info, \
2261   .get = snd_cmipci_uswitch_get, \
2262   .put = snd_cmipci_uswitch_put, \
2263   .private_value = (unsigned long)&cmipci_switch_arg_##sarg,\
2264 }
2265
2266 #define DEFINE_CARD_SWITCH(sname, sarg) DEFINE_SWITCH(sname, SNDRV_CTL_ELEM_IFACE_CARD, sarg)
2267 #define DEFINE_MIXER_SWITCH(sname, sarg) DEFINE_SWITCH(sname, SNDRV_CTL_ELEM_IFACE_MIXER, sarg)
2268
2269
2270 /*
2271  * callbacks for spdif output switch
2272  * needs toggle two registers..
2273  */
2274 static int snd_cmipci_spdout_enable_get(struct snd_kcontrol *kcontrol,
2275                                         struct snd_ctl_elem_value *ucontrol)
2276 {
2277         int changed;
2278         changed = _snd_cmipci_uswitch_get(kcontrol, ucontrol, &cmipci_switch_arg_spdif_enable);
2279         changed |= _snd_cmipci_uswitch_get(kcontrol, ucontrol, &cmipci_switch_arg_spdo2dac);
2280         return changed;
2281 }
2282
2283 static int snd_cmipci_spdout_enable_put(struct snd_kcontrol *kcontrol,
2284                                         struct snd_ctl_elem_value *ucontrol)
2285 {
2286         struct cmipci *chip = snd_kcontrol_chip(kcontrol);
2287         int changed;
2288         changed = _snd_cmipci_uswitch_put(kcontrol, ucontrol, &cmipci_switch_arg_spdif_enable);
2289         changed |= _snd_cmipci_uswitch_put(kcontrol, ucontrol, &cmipci_switch_arg_spdo2dac);
2290         if (changed) {
2291                 if (ucontrol->value.integer.value[0]) {
2292                         if (chip->spdif_playback_avail)
2293                                 snd_cmipci_set_bit(chip, CM_REG_FUNCTRL1, CM_PLAYBACK_SPDF);
2294                 } else {
2295                         if (chip->spdif_playback_avail)
2296                                 snd_cmipci_clear_bit(chip, CM_REG_FUNCTRL1, CM_PLAYBACK_SPDF);
2297                 }
2298         }
2299         chip->spdif_playback_enabled = ucontrol->value.integer.value[0];
2300         return changed;
2301 }
2302
2303
2304 static int snd_cmipci_line_in_mode_info(struct snd_kcontrol *kcontrol,
2305                                         struct snd_ctl_elem_info *uinfo)
2306 {
2307         struct cmipci *cm = snd_kcontrol_chip(kcontrol);
2308         static char *texts[3] = { "Line-In", "Rear Output", "Bass Output" };
2309         uinfo->type = SNDRV_CTL_ELEM_TYPE_ENUMERATED;
2310         uinfo->count = 1;
2311         uinfo->value.enumerated.items = cm->chip_version >= 39 ? 3 : 2;
2312         if (uinfo->value.enumerated.item >= uinfo->value.enumerated.items)
2313                 uinfo->value.enumerated.item = uinfo->value.enumerated.items - 1;
2314         strcpy(uinfo->value.enumerated.name, texts[uinfo->value.enumerated.item]);
2315         return 0;
2316 }
2317
2318 static inline unsigned int get_line_in_mode(struct cmipci *cm)
2319 {
2320         unsigned int val;
2321         if (cm->chip_version >= 39) {
2322                 val = snd_cmipci_read(cm, CM_REG_LEGACY_CTRL);
2323                 if (val & CM_LINE_AS_BASS)
2324                         return 2;
2325         }
2326         val = snd_cmipci_read_b(cm, CM_REG_MIXER1);
2327         if (val & CM_SPK4)
2328                 return 1;
2329         return 0;
2330 }
2331
2332 static int snd_cmipci_line_in_mode_get(struct snd_kcontrol *kcontrol,
2333                                        struct snd_ctl_elem_value *ucontrol)
2334 {
2335         struct cmipci *cm = snd_kcontrol_chip(kcontrol);
2336
2337         spin_lock_irq(&cm->reg_lock);
2338         ucontrol->value.enumerated.item[0] = get_line_in_mode(cm);
2339         spin_unlock_irq(&cm->reg_lock);
2340         return 0;
2341 }
2342
2343 static int snd_cmipci_line_in_mode_put(struct snd_kcontrol *kcontrol,
2344                                        struct snd_ctl_elem_value *ucontrol)
2345 {
2346         struct cmipci *cm = snd_kcontrol_chip(kcontrol);
2347         int change;
2348
2349         spin_lock_irq(&cm->reg_lock);
2350         if (ucontrol->value.enumerated.item[0] == 2)
2351                 change = snd_cmipci_set_bit(cm, CM_REG_LEGACY_CTRL, CM_LINE_AS_BASS);
2352         else
2353                 change = snd_cmipci_clear_bit(cm, CM_REG_LEGACY_CTRL, CM_LINE_AS_BASS);
2354         if (ucontrol->value.enumerated.item[0] == 1)
2355                 change |= snd_cmipci_set_bit_b(cm, CM_REG_MIXER1, CM_SPK4);
2356         else
2357                 change |= snd_cmipci_clear_bit_b(cm, CM_REG_MIXER1, CM_SPK4);
2358         spin_unlock_irq(&cm->reg_lock);
2359         return change;
2360 }
2361
2362 static int snd_cmipci_mic_in_mode_info(struct snd_kcontrol *kcontrol,
2363                                        struct snd_ctl_elem_info *uinfo)
2364 {
2365         static char *texts[2] = { "Mic-In", "Center/LFE Output" };
2366         uinfo->type = SNDRV_CTL_ELEM_TYPE_ENUMERATED;
2367         uinfo->count = 1;
2368         uinfo->value.enumerated.items = 2;
2369         if (uinfo->value.enumerated.item >= uinfo->value.enumerated.items)
2370                 uinfo->value.enumerated.item = uinfo->value.enumerated.items - 1;
2371         strcpy(uinfo->value.enumerated.name, texts[uinfo->value.enumerated.item]);
2372         return 0;
2373 }
2374
2375 static int snd_cmipci_mic_in_mode_get(struct snd_kcontrol *kcontrol,
2376                                       struct snd_ctl_elem_value *ucontrol)
2377 {
2378         struct cmipci *cm = snd_kcontrol_chip(kcontrol);
2379         /* same bit as spdi_phase */
2380         spin_lock_irq(&cm->reg_lock);
2381         ucontrol->value.enumerated.item[0] = 
2382                 (snd_cmipci_read_b(cm, CM_REG_MISC) & CM_SPDIF_INVERSE) ? 1 : 0;
2383         spin_unlock_irq(&cm->reg_lock);
2384         return 0;
2385 }
2386
2387 static int snd_cmipci_mic_in_mode_put(struct snd_kcontrol *kcontrol,
2388                                       struct snd_ctl_elem_value *ucontrol)
2389 {
2390         struct cmipci *cm = snd_kcontrol_chip(kcontrol);
2391         int change;
2392
2393         spin_lock_irq(&cm->reg_lock);
2394         if (ucontrol->value.enumerated.item[0])
2395                 change = snd_cmipci_set_bit_b(cm, CM_REG_MISC, CM_SPDIF_INVERSE);
2396         else
2397                 change = snd_cmipci_clear_bit_b(cm, CM_REG_MISC, CM_SPDIF_INVERSE);
2398         spin_unlock_irq(&cm->reg_lock);
2399         return change;
2400 }
2401
2402 /* both for CM8338/8738 */
2403 static struct snd_kcontrol_new snd_cmipci_mixer_switches[] __devinitdata = {
2404         DEFINE_MIXER_SWITCH("Four Channel Mode", fourch),
2405         {
2406                 .name = "Line-In Mode",
2407                 .iface = SNDRV_CTL_ELEM_IFACE_MIXER,
2408                 .info = snd_cmipci_line_in_mode_info,
2409                 .get = snd_cmipci_line_in_mode_get,
2410                 .put = snd_cmipci_line_in_mode_put,
2411         },
2412 };
2413
2414 /* for non-multichannel chips */
2415 static struct snd_kcontrol_new snd_cmipci_nomulti_switch __devinitdata =
2416 DEFINE_MIXER_SWITCH("Exchange DAC", exchange_dac);
2417
2418 /* only for CM8738 */
2419 static struct snd_kcontrol_new snd_cmipci_8738_mixer_switches[] __devinitdata = {
2420 #if 0 /* controlled in pcm device */
2421         DEFINE_MIXER_SWITCH("IEC958 In Record", spdif_in),
2422         DEFINE_MIXER_SWITCH("IEC958 Out", spdif_out),
2423         DEFINE_MIXER_SWITCH("IEC958 Out To DAC", spdo2dac),
2424 #endif
2425         // DEFINE_MIXER_SWITCH("IEC958 Output Switch", spdif_enable),
2426         { .name = "IEC958 Output Switch",
2427           .iface = SNDRV_CTL_ELEM_IFACE_MIXER,
2428           .info = snd_cmipci_uswitch_info,
2429           .get = snd_cmipci_spdout_enable_get,
2430           .put = snd_cmipci_spdout_enable_put,
2431         },
2432         DEFINE_MIXER_SWITCH("IEC958 In Valid", spdi_valid),
2433         DEFINE_MIXER_SWITCH("IEC958 Copyright", spdif_copyright),
2434         DEFINE_MIXER_SWITCH("IEC958 5V", spdo_5v),
2435 //      DEFINE_MIXER_SWITCH("IEC958 In/Out 48KHz", spdo_48k),
2436         DEFINE_MIXER_SWITCH("IEC958 Loop", spdif_loop),
2437         DEFINE_MIXER_SWITCH("IEC958 In Monitor", spdi_monitor),
2438 };
2439
2440 /* only for model 033/037 */
2441 static struct snd_kcontrol_new snd_cmipci_old_mixer_switches[] __devinitdata = {
2442         DEFINE_MIXER_SWITCH("IEC958 Mix Analog", spdif_dac_out),
2443         DEFINE_MIXER_SWITCH("IEC958 In Phase Inverse", spdi_phase),
2444         DEFINE_MIXER_SWITCH("IEC958 In Select", spdif_in_sel1),
2445 };
2446
2447 /* only for model 039 or later */
2448 static struct snd_kcontrol_new snd_cmipci_extra_mixer_switches[] __devinitdata = {
2449         DEFINE_MIXER_SWITCH("IEC958 In Select", spdif_in_sel2),
2450         DEFINE_MIXER_SWITCH("IEC958 In Phase Inverse", spdi_phase2),
2451         {
2452                 .name = "Mic-In Mode",
2453                 .iface = SNDRV_CTL_ELEM_IFACE_MIXER,
2454                 .info = snd_cmipci_mic_in_mode_info,
2455                 .get = snd_cmipci_mic_in_mode_get,
2456                 .put = snd_cmipci_mic_in_mode_put,
2457         }
2458 };
2459
2460 /* card control switches */
2461 static struct snd_kcontrol_new snd_cmipci_control_switches[] __devinitdata = {
2462         // DEFINE_CARD_SWITCH("Joystick", joystick), /* now module option */
2463         DEFINE_CARD_SWITCH("Modem", modem),
2464 };
2465
2466
2467 static int __devinit snd_cmipci_mixer_new(struct cmipci *cm, int pcm_spdif_device)
2468 {
2469         struct snd_card *card;
2470         struct snd_kcontrol_new *sw;
2471         struct snd_kcontrol *kctl;
2472         unsigned int idx;
2473         int err;
2474
2475         snd_assert(cm != NULL && cm->card != NULL, return -EINVAL);
2476
2477         card = cm->card;
2478
2479         strcpy(card->mixername, "CMedia PCI");
2480
2481         spin_lock_irq(&cm->reg_lock);
2482         snd_cmipci_mixer_write(cm, 0x00, 0x00);         /* mixer reset */
2483         spin_unlock_irq(&cm->reg_lock);
2484
2485         for (idx = 0; idx < ARRAY_SIZE(snd_cmipci_mixers); idx++) {
2486                 if (cm->chip_version == 68) {   // 8768 has no PCM volume
2487                         if (!strcmp(snd_cmipci_mixers[idx].name,
2488                                 "PCM Playback Volume"))
2489                                 continue;
2490                 }
2491                 if ((err = snd_ctl_add(card, snd_ctl_new1(&snd_cmipci_mixers[idx], cm))) < 0)
2492                         return err;
2493         }
2494
2495         /* mixer switches */
2496         sw = snd_cmipci_mixer_switches;
2497         for (idx = 0; idx < ARRAY_SIZE(snd_cmipci_mixer_switches); idx++, sw++) {
2498                 err = snd_ctl_add(cm->card, snd_ctl_new1(sw, cm));
2499                 if (err < 0)
2500                         return err;
2501         }
2502         if (! cm->can_multi_ch) {
2503                 err = snd_ctl_add(cm->card, snd_ctl_new1(&snd_cmipci_nomulti_switch, cm));
2504                 if (err < 0)
2505                         return err;
2506         }
2507         if (cm->device == PCI_DEVICE_ID_CMEDIA_CM8738 ||
2508             cm->device == PCI_DEVICE_ID_CMEDIA_CM8738B) {
2509                 sw = snd_cmipci_8738_mixer_switches;
2510                 for (idx = 0; idx < ARRAY_SIZE(snd_cmipci_8738_mixer_switches); idx++, sw++) {
2511                         err = snd_ctl_add(cm->card, snd_ctl_new1(sw, cm));
2512                         if (err < 0)
2513                                 return err;
2514                 }
2515                 if (cm->can_ac3_hw) {
2516                         if ((err = snd_ctl_add(card, kctl = snd_ctl_new1(&snd_cmipci_spdif_default, cm))) < 0)
2517                                 return err;
2518                         kctl->id.device = pcm_spdif_device;
2519                         if ((err = snd_ctl_add(card, kctl = snd_ctl_new1(&snd_cmipci_spdif_mask, cm))) < 0)
2520                                 return err;
2521                         kctl->id.device = pcm_spdif_device;
2522                         if ((err = snd_ctl_add(card, kctl = snd_ctl_new1(&snd_cmipci_spdif_stream, cm))) < 0)
2523                                 return err;
2524                         kctl->id.device = pcm_spdif_device;
2525                 }
2526                 if (cm->chip_version <= 37) {
2527                         sw = snd_cmipci_old_mixer_switches;
2528                         for (idx = 0; idx < ARRAY_SIZE(snd_cmipci_old_mixer_switches); idx++, sw++) {
2529                                 err = snd_ctl_add(cm->card, snd_ctl_new1(sw, cm));
2530                                 if (err < 0)
2531                                         return err;
2532                         }
2533                 }
2534         }
2535         if (cm->chip_version >= 39) {
2536                 sw = snd_cmipci_extra_mixer_switches;
2537                 for (idx = 0; idx < ARRAY_SIZE(snd_cmipci_extra_mixer_switches); idx++, sw++) {
2538                         err = snd_ctl_add(cm->card, snd_ctl_new1(sw, cm));
2539                         if (err < 0)
2540                                 return err;
2541                 }
2542         }
2543
2544         /* card switches */
2545         sw = snd_cmipci_control_switches;
2546         for (idx = 0; idx < ARRAY_SIZE(snd_cmipci_control_switches); idx++, sw++) {
2547                 err = snd_ctl_add(cm->card, snd_ctl_new1(sw, cm));
2548                 if (err < 0)
2549                         return err;
2550         }
2551
2552         for (idx = 0; idx < CM_SAVED_MIXERS; idx++) {
2553                 struct snd_ctl_elem_id id;
2554                 struct snd_kcontrol *ctl;
2555                 memset(&id, 0, sizeof(id));
2556                 id.iface = SNDRV_CTL_ELEM_IFACE_MIXER;
2557                 strcpy(id.name, cm_saved_mixer[idx].name);
2558                 if ((ctl = snd_ctl_find_id(cm->card, &id)) != NULL)
2559                         cm->mixer_res_ctl[idx] = ctl;
2560         }
2561
2562         return 0;
2563 }
2564
2565
2566 /*
2567  * proc interface
2568  */
2569
2570 #ifdef CONFIG_PROC_FS
2571 static void snd_cmipci_proc_read(struct snd_info_entry *entry, 
2572                                  struct snd_info_buffer *buffer)
2573 {
2574         struct cmipci *cm = entry->private_data;
2575         int i;
2576         
2577         snd_iprintf(buffer, "%s\n\n", cm->card->longname);
2578         for (i = 0; i < 0x40; i++) {
2579                 int v = inb(cm->iobase + i);
2580                 if (i % 4 == 0)
2581                         snd_iprintf(buffer, "%02x: ", i);
2582                 snd_iprintf(buffer, "%02x", v);
2583                 if (i % 4 == 3)
2584                         snd_iprintf(buffer, "\n");
2585                 else
2586                         snd_iprintf(buffer, " ");
2587         }
2588 }
2589
2590 static void __devinit snd_cmipci_proc_init(struct cmipci *cm)
2591 {
2592         struct snd_info_entry *entry;
2593
2594         if (! snd_card_proc_new(cm->card, "cmipci", &entry))
2595                 snd_info_set_text_ops(entry, cm, 1024, snd_cmipci_proc_read);
2596 }
2597 #else /* !CONFIG_PROC_FS */
2598 static inline void snd_cmipci_proc_init(struct cmipci *cm) {}
2599 #endif
2600
2601
2602 static struct pci_device_id snd_cmipci_ids[] = {
2603         {PCI_VENDOR_ID_CMEDIA, PCI_DEVICE_ID_CMEDIA_CM8338A, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
2604         {PCI_VENDOR_ID_CMEDIA, PCI_DEVICE_ID_CMEDIA_CM8338B, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
2605         {PCI_VENDOR_ID_CMEDIA, PCI_DEVICE_ID_CMEDIA_CM8738, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
2606         {PCI_VENDOR_ID_CMEDIA, PCI_DEVICE_ID_CMEDIA_CM8738B, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
2607         {PCI_VENDOR_ID_AL, PCI_DEVICE_ID_CMEDIA_CM8738, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
2608         {0,},
2609 };
2610
2611
2612 /*
2613  * check chip version and capabilities
2614  * driver name is modified according to the chip model
2615  */
2616 static void __devinit query_chip(struct cmipci *cm)
2617 {
2618         unsigned int detect;
2619
2620         /* check reg 0Ch, bit 24-31 */
2621         detect = snd_cmipci_read(cm, CM_REG_INT_HLDCLR) & CM_CHIP_MASK2;
2622         if (! detect) {
2623                 /* check reg 08h, bit 24-28 */
2624                 detect = snd_cmipci_read(cm, CM_REG_CHFORMAT) & CM_CHIP_MASK1;
2625                 if (! detect) {
2626                         cm->chip_version = 33;
2627                         cm->max_channels = 2;
2628                         if (cm->do_soft_ac3)
2629                                 cm->can_ac3_sw = 1;
2630                         else
2631                                 cm->can_ac3_hw = 1;
2632                         cm->has_dual_dac = 1;
2633                 } else {
2634                         cm->chip_version = 37;
2635                         cm->max_channels = 2;
2636                         cm->can_ac3_hw = 1;
2637                         cm->has_dual_dac = 1;
2638                 }
2639         } else {
2640                 /* check reg 0Ch, bit 26 */
2641                 if (detect & CM_CHIP_8768) {
2642                         cm->chip_version = 68;
2643                         cm->max_channels = 8;
2644                         cm->can_ac3_hw = 1;
2645                         cm->has_dual_dac = 1;
2646                         cm->can_multi_ch = 1;
2647                 } else if (detect & CM_CHIP_055) {
2648                         cm->chip_version = 55;
2649                         cm->max_channels = 6;
2650                         cm->can_ac3_hw = 1;
2651                         cm->has_dual_dac = 1;
2652                         cm->can_multi_ch = 1;
2653                 } else if (detect & CM_CHIP_039) {
2654                         cm->chip_version = 39;
2655                         if (detect & CM_CHIP_039_6CH) /* 4 or 6 channels */
2656                                 cm->max_channels = 6;
2657                         else
2658                                 cm->max_channels = 4;
2659                         cm->can_ac3_hw = 1;
2660                         cm->has_dual_dac = 1;
2661                         cm->can_multi_ch = 1;
2662                 } else {
2663                         printk(KERN_ERR "chip %x version not supported\n", detect);
2664                 }
2665         }
2666 }
2667
2668 #ifdef SUPPORT_JOYSTICK
2669 static int __devinit snd_cmipci_create_gameport(struct cmipci *cm, int dev)
2670 {
2671         static int ports[] = { 0x201, 0x200, 0 }; /* FIXME: majority is 0x201? */
2672         struct gameport *gp;
2673         struct resource *r = NULL;
2674         int i, io_port = 0;
2675
2676         if (joystick_port[dev] == 0)
2677                 return -ENODEV;
2678
2679         if (joystick_port[dev] == 1) { /* auto-detect */
2680                 for (i = 0; ports[i]; i++) {
2681                         io_port = ports[i];
2682                         r = request_region(io_port, 1, "CMIPCI gameport");
2683                         if (r)
2684                                 break;
2685                 }
2686         } else {
2687                 io_port = joystick_port[dev];
2688                 r = request_region(io_port, 1, "CMIPCI gameport");
2689         }
2690
2691         if (!r) {
2692                 printk(KERN_WARNING "cmipci: cannot reserve joystick ports\n");
2693                 return -EBUSY;
2694         }
2695
2696         cm->gameport = gp = gameport_allocate_port();
2697         if (!gp) {
2698                 printk(KERN_ERR "cmipci: cannot allocate memory for gameport\n");
2699                 release_and_free_resource(r);
2700                 return -ENOMEM;
2701         }
2702         gameport_set_name(gp, "C-Media Gameport");
2703         gameport_set_phys(gp, "pci%s/gameport0", pci_name(cm->pci));
2704         gameport_set_dev_parent(gp, &cm->pci->dev);
2705         gp->io = io_port;
2706         gameport_set_port_data(gp, r);
2707
2708         snd_cmipci_set_bit(cm, CM_REG_FUNCTRL1, CM_JYSTK_EN);
2709
2710         gameport_register_port(cm->gameport);
2711
2712         return 0;
2713 }
2714
2715 static void snd_cmipci_free_gameport(struct cmipci *cm)
2716 {
2717         if (cm->gameport) {
2718                 struct resource *r = gameport_get_port_data(cm->gameport);
2719
2720                 gameport_unregister_port(cm->gameport);
2721                 cm->gameport = NULL;
2722
2723                 snd_cmipci_clear_bit(cm, CM_REG_FUNCTRL1, CM_JYSTK_EN);
2724                 release_and_free_resource(r);
2725         }
2726 }
2727 #else
2728 static inline int snd_cmipci_create_gameport(struct cmipci *cm, int dev) { return -ENOSYS; }
2729 static inline void snd_cmipci_free_gameport(struct cmipci *cm) { }
2730 #endif
2731
2732 static int snd_cmipci_free(struct cmipci *cm)
2733 {
2734         if (cm->irq >= 0) {
2735                 snd_cmipci_clear_bit(cm, CM_REG_MISC_CTRL, CM_FM_EN);
2736                 snd_cmipci_clear_bit(cm, CM_REG_LEGACY_CTRL, CM_ENSPDOUT);
2737                 snd_cmipci_write(cm, CM_REG_INT_HLDCLR, 0);  /* disable ints */
2738                 snd_cmipci_ch_reset(cm, CM_CH_PLAY);
2739                 snd_cmipci_ch_reset(cm, CM_CH_CAPT);
2740                 snd_cmipci_write(cm, CM_REG_FUNCTRL0, 0); /* disable channels */
2741                 snd_cmipci_write(cm, CM_REG_FUNCTRL1, 0);
2742
2743                 /* reset mixer */
2744                 snd_cmipci_mixer_write(cm, 0, 0);
2745
2746                 synchronize_irq(cm->irq);
2747
2748                 free_irq(cm->irq, cm);
2749         }
2750
2751         snd_cmipci_free_gameport(cm);
2752         pci_release_regions(cm->pci);
2753         pci_disable_device(cm->pci);
2754         kfree(cm);
2755         return 0;
2756 }
2757
2758 static int snd_cmipci_dev_free(struct snd_device *device)
2759 {
2760         struct cmipci *cm = device->device_data;
2761         return snd_cmipci_free(cm);
2762 }
2763
2764 static int __devinit snd_cmipci_create_fm(struct cmipci *cm, long fm_port)
2765 {
2766         long iosynth;
2767         unsigned int val;
2768         struct snd_opl3 *opl3;
2769         int err;
2770
2771         /* first try FM regs in PCI port range */
2772         iosynth = cm->iobase + CM_REG_FM_PCI;
2773         err = snd_opl3_create(cm->card, iosynth, iosynth + 2,
2774                               OPL3_HW_OPL3, 1, &opl3);
2775         if (err < 0) {
2776                 /* then try legacy ports */
2777                 val = snd_cmipci_read(cm, CM_REG_LEGACY_CTRL) & ~CM_FMSEL_MASK;
2778                 iosynth = fm_port;
2779                 switch (iosynth) {
2780                 case 0x3E8: val |= CM_FMSEL_3E8; break;
2781                 case 0x3E0: val |= CM_FMSEL_3E0; break;
2782                 case 0x3C8: val |= CM_FMSEL_3C8; break;
2783                 case 0x388: val |= CM_FMSEL_388; break;
2784                 default:
2785                             return 0;
2786                 }
2787                 snd_cmipci_write(cm, CM_REG_LEGACY_CTRL, val);
2788                 /* enable FM */
2789                 snd_cmipci_set_bit(cm, CM_REG_MISC_CTRL, CM_FM_EN);
2790
2791                 if (snd_opl3_create(cm->card, iosynth, iosynth + 2,
2792                                     OPL3_HW_OPL3, 0, &opl3) < 0) {
2793                         printk(KERN_ERR "cmipci: no OPL device at %#lx, "
2794                                "skipping...\n", iosynth);
2795                         /* disable FM */
2796                         snd_cmipci_write(cm, CM_REG_LEGACY_CTRL,
2797                                          val & ~CM_FMSEL_MASK);
2798                         snd_cmipci_clear_bit(cm, CM_REG_MISC_CTRL, CM_FM_EN);
2799                         return 0;
2800                 }
2801         }
2802         if ((err = snd_opl3_hwdep_new(opl3, 0, 1, NULL)) < 0) {
2803                 printk(KERN_ERR "cmipci: cannot create OPL3 hwdep\n");
2804                 return err;
2805         }
2806         return 0;
2807 }
2808
2809 static int __devinit snd_cmipci_create(struct snd_card *card, struct pci_dev *pci,
2810                                        int dev, struct cmipci **rcmipci)
2811 {
2812         struct cmipci *cm;
2813         int err;
2814         static struct snd_device_ops ops = {
2815                 .dev_free =     snd_cmipci_dev_free,
2816         };
2817         unsigned int val = 0;
2818         long iomidi;
2819         int integrated_midi;
2820         int pcm_index, pcm_spdif_index;
2821         static struct pci_device_id intel_82437vx[] = {
2822                 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82437VX) },
2823                 { },
2824         };
2825
2826         *rcmipci = NULL;
2827
2828         if ((err = pci_enable_device(pci)) < 0)
2829                 return err;
2830
2831         cm = kzalloc(sizeof(*cm), GFP_KERNEL);
2832         if (cm == NULL) {
2833                 pci_disable_device(pci);
2834                 return -ENOMEM;
2835         }
2836
2837         spin_lock_init(&cm->reg_lock);
2838         init_MUTEX(&cm->open_mutex);
2839         cm->device = pci->device;
2840         cm->card = card;
2841         cm->pci = pci;
2842         cm->irq = -1;
2843         cm->channel[0].ch = 0;
2844         cm->channel[1].ch = 1;
2845         cm->channel[0].is_dac = cm->channel[1].is_dac = 1; /* dual DAC mode */
2846
2847         if ((err = pci_request_regions(pci, card->driver)) < 0) {
2848                 kfree(cm);
2849                 pci_disable_device(pci);
2850                 return err;
2851         }
2852         cm->iobase = pci_resource_start(pci, 0);
2853
2854         if (request_irq(pci->irq, snd_cmipci_interrupt,
2855                         SA_INTERRUPT|SA_SHIRQ, card->driver, cm)) {
2856                 snd_printk(KERN_ERR "unable to grab IRQ %d\n", pci->irq);
2857                 snd_cmipci_free(cm);
2858                 return -EBUSY;
2859         }
2860         cm->irq = pci->irq;
2861
2862         pci_set_master(cm->pci);
2863
2864         /*
2865          * check chip version, max channels and capabilities
2866          */
2867
2868         cm->chip_version = 0;
2869         cm->max_channels = 2;
2870         cm->do_soft_ac3 = soft_ac3[dev];
2871
2872         if (pci->device != PCI_DEVICE_ID_CMEDIA_CM8338A &&
2873             pci->device != PCI_DEVICE_ID_CMEDIA_CM8338B)
2874                 query_chip(cm);
2875         /* added -MCx suffix for chip supporting multi-channels */
2876         if (cm->can_multi_ch)
2877                 sprintf(cm->card->driver + strlen(cm->card->driver),
2878                         "-MC%d", cm->max_channels);
2879         else if (cm->can_ac3_sw)
2880                 strcpy(cm->card->driver + strlen(cm->card->driver), "-SWIEC");
2881
2882         cm->dig_status = SNDRV_PCM_DEFAULT_CON_SPDIF;
2883         cm->dig_pcm_status = SNDRV_PCM_DEFAULT_CON_SPDIF;
2884
2885 #if CM_CH_PLAY == 1
2886         cm->ctrl = CM_CHADC0;   /* default FUNCNTRL0 */
2887 #else
2888         cm->ctrl = CM_CHADC1;   /* default FUNCNTRL0 */
2889 #endif
2890
2891         /* initialize codec registers */
2892         snd_cmipci_write(cm, CM_REG_INT_HLDCLR, 0);     /* disable ints */
2893         snd_cmipci_ch_reset(cm, CM_CH_PLAY);
2894         snd_cmipci_ch_reset(cm, CM_CH_CAPT);
2895         snd_cmipci_write(cm, CM_REG_FUNCTRL0, 0);       /* disable channels */
2896         snd_cmipci_write(cm, CM_REG_FUNCTRL1, 0);
2897
2898         snd_cmipci_write(cm, CM_REG_CHFORMAT, 0);
2899         snd_cmipci_set_bit(cm, CM_REG_MISC_CTRL, CM_ENDBDAC|CM_N4SPK3D);
2900 #if CM_CH_PLAY == 1
2901         snd_cmipci_set_bit(cm, CM_REG_MISC_CTRL, CM_XCHGDAC);
2902 #else
2903         snd_cmipci_clear_bit(cm, CM_REG_MISC_CTRL, CM_XCHGDAC);
2904 #endif
2905         /* Set Bus Master Request */
2906         snd_cmipci_set_bit(cm, CM_REG_FUNCTRL1, CM_BREQ);
2907
2908         /* Assume TX and compatible chip set (Autodetection required for VX chip sets) */
2909         switch (pci->device) {
2910         case PCI_DEVICE_ID_CMEDIA_CM8738:
2911         case PCI_DEVICE_ID_CMEDIA_CM8738B:
2912                 if (!pci_dev_present(intel_82437vx)) 
2913                         snd_cmipci_set_bit(cm, CM_REG_MISC_CTRL, CM_TXVX);
2914                 break;
2915         default:
2916                 break;
2917         }
2918
2919         if ((err = snd_device_new(card, SNDRV_DEV_LOWLEVEL, cm, &ops)) < 0) {
2920                 snd_cmipci_free(cm);
2921                 return err;
2922         }
2923
2924         integrated_midi = snd_cmipci_read_b(cm, CM_REG_MPU_PCI) != 0xff;
2925         if (integrated_midi)
2926                 iomidi = cm->iobase + CM_REG_MPU_PCI;
2927         else {
2928                 iomidi = mpu_port[dev];
2929                 switch (iomidi) {
2930                 case 0x320: val = CM_VMPU_320; break;
2931                 case 0x310: val = CM_VMPU_310; break;
2932                 case 0x300: val = CM_VMPU_300; break;
2933                 case 0x330: val = CM_VMPU_330; break;
2934                 default:
2935                             iomidi = 0; break;
2936                 }
2937                 if (iomidi > 0) {
2938                         snd_cmipci_write(cm, CM_REG_LEGACY_CTRL, val);
2939                         /* enable UART */
2940                         snd_cmipci_set_bit(cm, CM_REG_FUNCTRL1, CM_UART_EN);
2941                 }
2942         }
2943
2944         if ((err = snd_cmipci_create_fm(cm, fm_port[dev])) < 0)
2945                 return err;
2946
2947         /* reset mixer */
2948         snd_cmipci_mixer_write(cm, 0, 0);
2949
2950         snd_cmipci_proc_init(cm);
2951
2952         /* create pcm devices */
2953         pcm_index = pcm_spdif_index = 0;
2954         if ((err = snd_cmipci_pcm_new(cm, pcm_index)) < 0)
2955                 return err;
2956         pcm_index++;
2957         if (cm->has_dual_dac) {
2958                 if ((err = snd_cmipci_pcm2_new(cm, pcm_index)) < 0)
2959                         return err;
2960                 pcm_index++;
2961         }
2962         if (cm->can_ac3_hw || cm->can_ac3_sw) {
2963                 pcm_spdif_index = pcm_index;
2964                 if ((err = snd_cmipci_pcm_spdif_new(cm, pcm_index)) < 0)
2965                         return err;
2966         }
2967
2968         /* create mixer interface & switches */
2969         if ((err = snd_cmipci_mixer_new(cm, pcm_spdif_index)) < 0)
2970                 return err;
2971
2972         if (iomidi > 0) {
2973                 if ((err = snd_mpu401_uart_new(card, 0, MPU401_HW_CMIPCI,
2974                                                iomidi, integrated_midi,
2975                                                cm->irq, 0, &cm->rmidi)) < 0) {
2976                         printk(KERN_ERR "cmipci: no UART401 device at 0x%lx\n", iomidi);
2977                 }
2978         }
2979
2980 #ifdef USE_VAR48KRATE
2981         for (val = 0; val < ARRAY_SIZE(rates); val++)
2982                 snd_cmipci_set_pll(cm, rates[val], val);
2983
2984         /*
2985          * (Re-)Enable external switch spdo_48k
2986          */
2987         snd_cmipci_set_bit(cm, CM_REG_MISC_CTRL, CM_SPDIF48K|CM_SPDF_AC97);
2988 #endif /* USE_VAR48KRATE */
2989
2990         if (snd_cmipci_create_gameport(cm, dev) < 0)
2991                 snd_cmipci_clear_bit(cm, CM_REG_FUNCTRL1, CM_JYSTK_EN);
2992
2993         snd_card_set_dev(card, &pci->dev);
2994
2995         *rcmipci = cm;
2996         return 0;
2997 }
2998
2999 /*
3000  */
3001
3002 MODULE_DEVICE_TABLE(pci, snd_cmipci_ids);
3003
3004 static int __devinit snd_cmipci_probe(struct pci_dev *pci,
3005                                       const struct pci_device_id *pci_id)
3006 {
3007         static int dev;
3008         struct snd_card *card;
3009         struct cmipci *cm;
3010         int err;
3011
3012         if (dev >= SNDRV_CARDS)
3013                 return -ENODEV;
3014         if (! enable[dev]) {
3015                 dev++;
3016                 return -ENOENT;
3017         }
3018
3019         card = snd_card_new(index[dev], id[dev], THIS_MODULE, 0);
3020         if (card == NULL)
3021                 return -ENOMEM;
3022         
3023         switch (pci->device) {
3024         case PCI_DEVICE_ID_CMEDIA_CM8738:
3025         case PCI_DEVICE_ID_CMEDIA_CM8738B:
3026                 strcpy(card->driver, "CMI8738");
3027                 break;
3028         case PCI_DEVICE_ID_CMEDIA_CM8338A:
3029         case PCI_DEVICE_ID_CMEDIA_CM8338B:
3030                 strcpy(card->driver, "CMI8338");
3031                 break;
3032         default:
3033                 strcpy(card->driver, "CMIPCI");
3034                 break;
3035         }
3036
3037         if ((err = snd_cmipci_create(card, pci, dev, &cm)) < 0) {
3038                 snd_card_free(card);
3039                 return err;
3040         }
3041
3042         sprintf(card->shortname, "C-Media PCI %s", card->driver);
3043         sprintf(card->longname, "%s (model %d) at 0x%lx, irq %i",
3044                 card->shortname,
3045                 cm->chip_version,
3046                 cm->iobase,
3047                 cm->irq);
3048
3049         //snd_printd("%s is detected\n", card->longname);
3050
3051         if ((err = snd_card_register(card)) < 0) {
3052                 snd_card_free(card);
3053                 return err;
3054         }
3055         pci_set_drvdata(pci, card);
3056         dev++;
3057         return 0;
3058
3059 }
3060
3061 static void __devexit snd_cmipci_remove(struct pci_dev *pci)
3062 {
3063         snd_card_free(pci_get_drvdata(pci));
3064         pci_set_drvdata(pci, NULL);
3065 }
3066
3067
3068 static struct pci_driver driver = {
3069         .name = "C-Media PCI",
3070         .id_table = snd_cmipci_ids,
3071         .probe = snd_cmipci_probe,
3072         .remove = __devexit_p(snd_cmipci_remove),
3073 };
3074         
3075 static int __init alsa_card_cmipci_init(void)
3076 {
3077         return pci_register_driver(&driver);
3078 }
3079
3080 static void __exit alsa_card_cmipci_exit(void)
3081 {
3082         pci_unregister_driver(&driver);
3083 }
3084
3085 module_init(alsa_card_cmipci_init)
3086 module_exit(alsa_card_cmipci_exit)