sound: oss: au1550_ac97.c removed duplicated #include
[linux-2.6.git] / sound / oss / au1550_ac97.c
1 /*
2  * au1550_ac97.c  --  Sound driver for Alchemy Au1550 MIPS Internet Edge
3  *                    Processor.
4  *
5  * Copyright 2004 Embedded Edge, LLC
6  *      dan@embeddededge.com
7  *
8  * Mostly copied from the au1000.c driver and some from the
9  * PowerMac dbdma driver.
10  * We assume the processor can do memory coherent DMA.
11  *
12  * Ported to 2.6 by Matt Porter <mporter@kernel.crashing.org>
13  *
14  *  This program is free software; you can redistribute  it and/or modify it
15  *  under  the terms of  the GNU General  Public License as published by the
16  *  Free Software Foundation;  either version 2 of the  License, or (at your
17  *  option) any later version.
18  *
19  *  THIS  SOFTWARE  IS PROVIDED   ``AS  IS'' AND   ANY  EXPRESS OR IMPLIED
20  *  WARRANTIES,   INCLUDING, BUT NOT  LIMITED  TO, THE IMPLIED WARRANTIES OF
21  *  MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.  IN
22  *  NO  EVENT  SHALL   THE AUTHOR  BE    LIABLE FOR ANY   DIRECT, INDIRECT,
23  *  INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
24  *  NOT LIMITED   TO, PROCUREMENT OF  SUBSTITUTE GOODS  OR SERVICES; LOSS OF
25  *  USE, DATA,  OR PROFITS; OR  BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
26  *  ANY THEORY OF LIABILITY, WHETHER IN  CONTRACT, STRICT LIABILITY, OR TORT
27  *  (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
28  *  THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
29  *
30  *  You should have received a copy of the  GNU General Public License along
31  *  with this program; if not, write  to the Free Software Foundation, Inc.,
32  *  675 Mass Ave, Cambridge, MA 02139, USA.
33  *
34  */
35
36 #undef DEBUG
37
38 #include <linux/module.h>
39 #include <linux/string.h>
40 #include <linux/ioport.h>
41 #include <linux/sched.h>
42 #include <linux/delay.h>
43 #include <linux/sound.h>
44 #include <linux/slab.h>
45 #include <linux/soundcard.h>
46 #include <linux/smp_lock.h>
47 #include <linux/init.h>
48 #include <linux/interrupt.h>
49 #include <linux/kernel.h>
50 #include <linux/poll.h>
51 #include <linux/bitops.h>
52 #include <linux/spinlock.h>
53 #include <linux/ac97_codec.h>
54 #include <linux/mutex.h>
55
56 #include <asm/io.h>
57 #include <asm/uaccess.h>
58 #include <asm/hardirq.h>
59 #include <asm/mach-au1x00/au1xxx_psc.h>
60 #include <asm/mach-au1x00/au1xxx_dbdma.h>
61 #include <asm/mach-au1x00/au1xxx.h>
62
63 #undef OSS_DOCUMENTED_MIXER_SEMANTICS
64
65 /* misc stuff */
66 #define POLL_COUNT   0x50000
67 #define AC97_EXT_DACS (AC97_EXTID_SDAC | AC97_EXTID_CDAC | AC97_EXTID_LDAC)
68
69 /* The number of DBDMA ring descriptors to allocate.  No sense making
70  * this too large....if you can't keep up with a few you aren't likely
71  * to be able to with lots of them, either.
72  */
73 #define NUM_DBDMA_DESCRIPTORS 4
74
75 #define err(format, arg...) printk(KERN_ERR format "\n" , ## arg)
76
77 /* Boot options
78  * 0 = no VRA, 1 = use VRA if codec supports it
79  */
80 static int      vra = 1;
81 module_param(vra, bool, 0);
82 MODULE_PARM_DESC(vra, "if 1 use VRA if codec supports it");
83
84 static struct au1550_state {
85         /* soundcore stuff */
86         int             dev_audio;
87
88         struct ac97_codec *codec;
89         unsigned        codec_base_caps; /* AC'97 reg 00h, "Reset Register" */
90         unsigned        codec_ext_caps;  /* AC'97 reg 28h, "Extended Audio ID" */
91         int             no_vra;         /* do not use VRA */
92
93         spinlock_t      lock;
94         struct mutex open_mutex;
95         struct mutex sem;
96         fmode_t          open_mode;
97         wait_queue_head_t open_wait;
98
99         struct dmabuf {
100                 u32             dmanr;
101                 unsigned        sample_rate;
102                 unsigned        src_factor;
103                 unsigned        sample_size;
104                 int             num_channels;
105                 int             dma_bytes_per_sample;
106                 int             user_bytes_per_sample;
107                 int             cnt_factor;
108
109                 void            *rawbuf;
110                 unsigned        buforder;
111                 unsigned        numfrag;
112                 unsigned        fragshift;
113                 void            *nextIn;
114                 void            *nextOut;
115                 int             count;
116                 unsigned        total_bytes;
117                 unsigned        error;
118                 wait_queue_head_t wait;
119
120                 /* redundant, but makes calculations easier */
121                 unsigned        fragsize;
122                 unsigned        dma_fragsize;
123                 unsigned        dmasize;
124                 unsigned        dma_qcount;
125
126                 /* OSS stuff */
127                 unsigned        mapped:1;
128                 unsigned        ready:1;
129                 unsigned        stopped:1;
130                 unsigned        ossfragshift;
131                 int             ossmaxfrags;
132                 unsigned        subdivision;
133         } dma_dac, dma_adc;
134 } au1550_state;
135
136 static unsigned
137 ld2(unsigned int x)
138 {
139         unsigned        r = 0;
140
141         if (x >= 0x10000) {
142                 x >>= 16;
143                 r += 16;
144         }
145         if (x >= 0x100) {
146                 x >>= 8;
147                 r += 8;
148         }
149         if (x >= 0x10) {
150                 x >>= 4;
151                 r += 4;
152         }
153         if (x >= 4) {
154                 x >>= 2;
155                 r += 2;
156         }
157         if (x >= 2)
158                 r++;
159         return r;
160 }
161
162 static void
163 au1550_delay(int msec)
164 {
165         if (in_interrupt())
166                 return;
167
168         schedule_timeout_uninterruptible(msecs_to_jiffies(msec));
169 }
170
171 static u16
172 rdcodec(struct ac97_codec *codec, u8 addr)
173 {
174         struct au1550_state *s = (struct au1550_state *)codec->private_data;
175         unsigned long   flags;
176         u32             cmd, val;
177         u16             data;
178         int             i;
179
180         spin_lock_irqsave(&s->lock, flags);
181
182         for (i = 0; i < POLL_COUNT; i++) {
183                 val = au_readl(PSC_AC97STAT);
184                 au_sync();
185                 if (!(val & PSC_AC97STAT_CP))
186                         break;
187         }
188         if (i == POLL_COUNT)
189                 err("rdcodec: codec cmd pending expired!");
190
191         cmd = (u32)PSC_AC97CDC_INDX(addr);
192         cmd |= PSC_AC97CDC_RD;  /* read command */
193         au_writel(cmd, PSC_AC97CDC);
194         au_sync();
195
196         /* now wait for the data
197         */
198         for (i = 0; i < POLL_COUNT; i++) {
199                 val = au_readl(PSC_AC97STAT);
200                 au_sync();
201                 if (!(val & PSC_AC97STAT_CP))
202                         break;
203         }
204         if (i == POLL_COUNT) {
205                 err("rdcodec: read poll expired!");
206                 data = 0;
207                 goto out;
208         }
209
210         /* wait for command done?
211         */
212         for (i = 0; i < POLL_COUNT; i++) {
213                 val = au_readl(PSC_AC97EVNT);
214                 au_sync();
215                 if (val & PSC_AC97EVNT_CD)
216                         break;
217         }
218         if (i == POLL_COUNT) {
219                 err("rdcodec: read cmdwait expired!");
220                 data = 0;
221                 goto out;
222         }
223
224         data = au_readl(PSC_AC97CDC) & 0xffff;
225         au_sync();
226
227         /* Clear command done event.
228         */
229         au_writel(PSC_AC97EVNT_CD, PSC_AC97EVNT);
230         au_sync();
231
232  out:
233         spin_unlock_irqrestore(&s->lock, flags);
234
235         return data;
236 }
237
238
239 static void
240 wrcodec(struct ac97_codec *codec, u8 addr, u16 data)
241 {
242         struct au1550_state *s = (struct au1550_state *)codec->private_data;
243         unsigned long   flags;
244         u32             cmd, val;
245         int             i;
246
247         spin_lock_irqsave(&s->lock, flags);
248
249         for (i = 0; i < POLL_COUNT; i++) {
250                 val = au_readl(PSC_AC97STAT);
251                 au_sync();
252                 if (!(val & PSC_AC97STAT_CP))
253                         break;
254         }
255         if (i == POLL_COUNT)
256                 err("wrcodec: codec cmd pending expired!");
257
258         cmd = (u32)PSC_AC97CDC_INDX(addr);
259         cmd |= (u32)data;
260         au_writel(cmd, PSC_AC97CDC);
261         au_sync();
262
263         for (i = 0; i < POLL_COUNT; i++) {
264                 val = au_readl(PSC_AC97STAT);
265                 au_sync();
266                 if (!(val & PSC_AC97STAT_CP))
267                         break;
268         }
269         if (i == POLL_COUNT)
270                 err("wrcodec: codec cmd pending expired!");
271
272         for (i = 0; i < POLL_COUNT; i++) {
273                 val = au_readl(PSC_AC97EVNT);
274                 au_sync();
275                 if (val & PSC_AC97EVNT_CD)
276                         break;
277         }
278         if (i == POLL_COUNT)
279                 err("wrcodec: read cmdwait expired!");
280
281         /* Clear command done event.
282         */
283         au_writel(PSC_AC97EVNT_CD, PSC_AC97EVNT);
284         au_sync();
285
286         spin_unlock_irqrestore(&s->lock, flags);
287 }
288
289 static void
290 waitcodec(struct ac97_codec *codec)
291 {
292         u16     temp;
293         u32     val;
294         int     i;
295
296         /* codec_wait is used to wait for a ready state after
297          * an AC97C_RESET.
298          */
299         au1550_delay(10);
300
301         /* first poll the CODEC_READY tag bit
302         */
303         for (i = 0; i < POLL_COUNT; i++) {
304                 val = au_readl(PSC_AC97STAT);
305                 au_sync();
306                 if (val & PSC_AC97STAT_CR)
307                         break;
308         }
309         if (i == POLL_COUNT) {
310                 err("waitcodec: CODEC_READY poll expired!");
311                 return;
312         }
313
314         /* get AC'97 powerdown control/status register
315         */
316         temp = rdcodec(codec, AC97_POWER_CONTROL);
317
318         /* If anything is powered down, power'em up
319         */
320         if (temp & 0x7f00) {
321                 /* Power on
322                 */
323                 wrcodec(codec, AC97_POWER_CONTROL, 0);
324                 au1550_delay(100);
325
326                 /* Reread
327                 */
328                 temp = rdcodec(codec, AC97_POWER_CONTROL);
329         }
330
331         /* Check if Codec REF,ANL,DAC,ADC ready
332         */
333         if ((temp & 0x7f0f) != 0x000f)
334                 err("codec reg 26 status (0x%x) not ready!!", temp);
335 }
336
337 /* stop the ADC before calling */
338 static void
339 set_adc_rate(struct au1550_state *s, unsigned rate)
340 {
341         struct dmabuf  *adc = &s->dma_adc;
342         struct dmabuf  *dac = &s->dma_dac;
343         unsigned        adc_rate, dac_rate;
344         u16             ac97_extstat;
345
346         if (s->no_vra) {
347                 /* calc SRC factor
348                 */
349                 adc->src_factor = ((96000 / rate) + 1) >> 1;
350                 adc->sample_rate = 48000 / adc->src_factor;
351                 return;
352         }
353
354         adc->src_factor = 1;
355
356         ac97_extstat = rdcodec(s->codec, AC97_EXTENDED_STATUS);
357
358         rate = rate > 48000 ? 48000 : rate;
359
360         /* enable VRA
361         */
362         wrcodec(s->codec, AC97_EXTENDED_STATUS,
363                 ac97_extstat | AC97_EXTSTAT_VRA);
364
365         /* now write the sample rate
366         */
367         wrcodec(s->codec, AC97_PCM_LR_ADC_RATE, (u16) rate);
368
369         /* read it back for actual supported rate
370         */
371         adc_rate = rdcodec(s->codec, AC97_PCM_LR_ADC_RATE);
372
373         pr_debug("set_adc_rate: set to %d Hz\n", adc_rate);
374
375         /* some codec's don't allow unequal DAC and ADC rates, in which case
376          * writing one rate reg actually changes both.
377          */
378         dac_rate = rdcodec(s->codec, AC97_PCM_FRONT_DAC_RATE);
379         if (dac->num_channels > 2)
380                 wrcodec(s->codec, AC97_PCM_SURR_DAC_RATE, dac_rate);
381         if (dac->num_channels > 4)
382                 wrcodec(s->codec, AC97_PCM_LFE_DAC_RATE, dac_rate);
383
384         adc->sample_rate = adc_rate;
385         dac->sample_rate = dac_rate;
386 }
387
388 /* stop the DAC before calling */
389 static void
390 set_dac_rate(struct au1550_state *s, unsigned rate)
391 {
392         struct dmabuf  *dac = &s->dma_dac;
393         struct dmabuf  *adc = &s->dma_adc;
394         unsigned        adc_rate, dac_rate;
395         u16             ac97_extstat;
396
397         if (s->no_vra) {
398                 /* calc SRC factor
399                 */
400                 dac->src_factor = ((96000 / rate) + 1) >> 1;
401                 dac->sample_rate = 48000 / dac->src_factor;
402                 return;
403         }
404
405         dac->src_factor = 1;
406
407         ac97_extstat = rdcodec(s->codec, AC97_EXTENDED_STATUS);
408
409         rate = rate > 48000 ? 48000 : rate;
410
411         /* enable VRA
412         */
413         wrcodec(s->codec, AC97_EXTENDED_STATUS,
414                 ac97_extstat | AC97_EXTSTAT_VRA);
415
416         /* now write the sample rate
417         */
418         wrcodec(s->codec, AC97_PCM_FRONT_DAC_RATE, (u16) rate);
419
420         /* I don't support different sample rates for multichannel,
421          * so make these channels the same.
422          */
423         if (dac->num_channels > 2)
424                 wrcodec(s->codec, AC97_PCM_SURR_DAC_RATE, (u16) rate);
425         if (dac->num_channels > 4)
426                 wrcodec(s->codec, AC97_PCM_LFE_DAC_RATE, (u16) rate);
427         /* read it back for actual supported rate
428         */
429         dac_rate = rdcodec(s->codec, AC97_PCM_FRONT_DAC_RATE);
430
431         pr_debug("set_dac_rate: set to %d Hz\n", dac_rate);
432
433         /* some codec's don't allow unequal DAC and ADC rates, in which case
434          * writing one rate reg actually changes both.
435          */
436         adc_rate = rdcodec(s->codec, AC97_PCM_LR_ADC_RATE);
437
438         dac->sample_rate = dac_rate;
439         adc->sample_rate = adc_rate;
440 }
441
442 static void
443 stop_dac(struct au1550_state *s)
444 {
445         struct dmabuf  *db = &s->dma_dac;
446         u32             stat;
447         unsigned long   flags;
448
449         if (db->stopped)
450                 return;
451
452         spin_lock_irqsave(&s->lock, flags);
453
454         au_writel(PSC_AC97PCR_TP, PSC_AC97PCR);
455         au_sync();
456
457         /* Wait for Transmit Busy to show disabled.
458         */
459         do {
460                 stat = au_readl(PSC_AC97STAT);
461                 au_sync();
462         } while ((stat & PSC_AC97STAT_TB) != 0);
463
464         au1xxx_dbdma_reset(db->dmanr);
465
466         db->stopped = 1;
467
468         spin_unlock_irqrestore(&s->lock, flags);
469 }
470
471 static void
472 stop_adc(struct au1550_state *s)
473 {
474         struct dmabuf  *db = &s->dma_adc;
475         unsigned long   flags;
476         u32             stat;
477
478         if (db->stopped)
479                 return;
480
481         spin_lock_irqsave(&s->lock, flags);
482
483         au_writel(PSC_AC97PCR_RP, PSC_AC97PCR);
484         au_sync();
485
486         /* Wait for Receive Busy to show disabled.
487         */
488         do {
489                 stat = au_readl(PSC_AC97STAT);
490                 au_sync();
491         } while ((stat & PSC_AC97STAT_RB) != 0);
492
493         au1xxx_dbdma_reset(db->dmanr);
494
495         db->stopped = 1;
496
497         spin_unlock_irqrestore(&s->lock, flags);
498 }
499
500
501 static void
502 set_xmit_slots(int num_channels)
503 {
504         u32     ac97_config, stat;
505
506         ac97_config = au_readl(PSC_AC97CFG);
507         au_sync();
508         ac97_config &= ~(PSC_AC97CFG_TXSLOT_MASK | PSC_AC97CFG_DE_ENABLE);
509         au_writel(ac97_config, PSC_AC97CFG);
510         au_sync();
511
512         switch (num_channels) {
513         case 6:         /* stereo with surround and center/LFE,
514                          * slots 3,4,6,7,8,9
515                          */
516                 ac97_config |= PSC_AC97CFG_TXSLOT_ENA(6);
517                 ac97_config |= PSC_AC97CFG_TXSLOT_ENA(9);
518
519         case 4:         /* stereo with surround, slots 3,4,7,8 */
520                 ac97_config |= PSC_AC97CFG_TXSLOT_ENA(7);
521                 ac97_config |= PSC_AC97CFG_TXSLOT_ENA(8);
522
523         case 2:         /* stereo, slots 3,4 */
524         case 1:         /* mono */
525                 ac97_config |= PSC_AC97CFG_TXSLOT_ENA(3);
526                 ac97_config |= PSC_AC97CFG_TXSLOT_ENA(4);
527         }
528
529         au_writel(ac97_config, PSC_AC97CFG);
530         au_sync();
531
532         ac97_config |= PSC_AC97CFG_DE_ENABLE;
533         au_writel(ac97_config, PSC_AC97CFG);
534         au_sync();
535
536         /* Wait for Device ready.
537         */
538         do {
539                 stat = au_readl(PSC_AC97STAT);
540                 au_sync();
541         } while ((stat & PSC_AC97STAT_DR) == 0);
542 }
543
544 static void
545 set_recv_slots(int num_channels)
546 {
547         u32     ac97_config, stat;
548
549         ac97_config = au_readl(PSC_AC97CFG);
550         au_sync();
551         ac97_config &= ~(PSC_AC97CFG_RXSLOT_MASK | PSC_AC97CFG_DE_ENABLE);
552         au_writel(ac97_config, PSC_AC97CFG);
553         au_sync();
554
555         /* Always enable slots 3 and 4 (stereo). Slot 6 is
556          * optional Mic ADC, which we don't support yet.
557          */
558         ac97_config |= PSC_AC97CFG_RXSLOT_ENA(3);
559         ac97_config |= PSC_AC97CFG_RXSLOT_ENA(4);
560
561         au_writel(ac97_config, PSC_AC97CFG);
562         au_sync();
563
564         ac97_config |= PSC_AC97CFG_DE_ENABLE;
565         au_writel(ac97_config, PSC_AC97CFG);
566         au_sync();
567
568         /* Wait for Device ready.
569         */
570         do {
571                 stat = au_readl(PSC_AC97STAT);
572                 au_sync();
573         } while ((stat & PSC_AC97STAT_DR) == 0);
574 }
575
576 /* Hold spinlock for both start_dac() and start_adc() calls */
577 static void
578 start_dac(struct au1550_state *s)
579 {
580         struct dmabuf  *db = &s->dma_dac;
581
582         if (!db->stopped)
583                 return;
584
585         set_xmit_slots(db->num_channels);
586         au_writel(PSC_AC97PCR_TC, PSC_AC97PCR);
587         au_sync();
588         au_writel(PSC_AC97PCR_TS, PSC_AC97PCR);
589         au_sync();
590
591         au1xxx_dbdma_start(db->dmanr);
592
593         db->stopped = 0;
594 }
595
596 static void
597 start_adc(struct au1550_state *s)
598 {
599         struct dmabuf  *db = &s->dma_adc;
600         int     i;
601
602         if (!db->stopped)
603                 return;
604
605         /* Put two buffers on the ring to get things started.
606         */
607         for (i=0; i<2; i++) {
608                 au1xxx_dbdma_put_dest(db->dmanr, virt_to_phys(db->nextIn),
609                                 db->dma_fragsize, DDMA_FLAGS_IE);
610
611                 db->nextIn += db->dma_fragsize;
612                 if (db->nextIn >= db->rawbuf + db->dmasize)
613                         db->nextIn -= db->dmasize;
614         }
615
616         set_recv_slots(db->num_channels);
617         au1xxx_dbdma_start(db->dmanr);
618         au_writel(PSC_AC97PCR_RC, PSC_AC97PCR);
619         au_sync();
620         au_writel(PSC_AC97PCR_RS, PSC_AC97PCR);
621         au_sync();
622
623         db->stopped = 0;
624 }
625
626 static int
627 prog_dmabuf(struct au1550_state *s, struct dmabuf *db)
628 {
629         unsigned user_bytes_per_sec;
630         unsigned        bufs;
631         unsigned        rate = db->sample_rate;
632
633         if (!db->rawbuf) {
634                 db->ready = db->mapped = 0;
635                 db->buforder = 5;       /* 32 * PAGE_SIZE */
636                 db->rawbuf = kmalloc((PAGE_SIZE << db->buforder), GFP_KERNEL);
637                 if (!db->rawbuf)
638                         return -ENOMEM;
639         }
640
641         db->cnt_factor = 1;
642         if (db->sample_size == 8)
643                 db->cnt_factor *= 2;
644         if (db->num_channels == 1)
645                 db->cnt_factor *= 2;
646         db->cnt_factor *= db->src_factor;
647
648         db->count = 0;
649         db->dma_qcount = 0;
650         db->nextIn = db->nextOut = db->rawbuf;
651
652         db->user_bytes_per_sample = (db->sample_size>>3) * db->num_channels;
653         db->dma_bytes_per_sample = 2 * ((db->num_channels == 1) ?
654                                         2 : db->num_channels);
655
656         user_bytes_per_sec = rate * db->user_bytes_per_sample;
657         bufs = PAGE_SIZE << db->buforder;
658         if (db->ossfragshift) {
659                 if ((1000 << db->ossfragshift) < user_bytes_per_sec)
660                         db->fragshift = ld2(user_bytes_per_sec/1000);
661                 else
662                         db->fragshift = db->ossfragshift;
663         } else {
664                 db->fragshift = ld2(user_bytes_per_sec / 100 /
665                                     (db->subdivision ? db->subdivision : 1));
666                 if (db->fragshift < 3)
667                         db->fragshift = 3;
668         }
669
670         db->fragsize = 1 << db->fragshift;
671         db->dma_fragsize = db->fragsize * db->cnt_factor;
672         db->numfrag = bufs / db->dma_fragsize;
673
674         while (db->numfrag < 4 && db->fragshift > 3) {
675                 db->fragshift--;
676                 db->fragsize = 1 << db->fragshift;
677                 db->dma_fragsize = db->fragsize * db->cnt_factor;
678                 db->numfrag = bufs / db->dma_fragsize;
679         }
680
681         if (db->ossmaxfrags >= 4 && db->ossmaxfrags < db->numfrag)
682                 db->numfrag = db->ossmaxfrags;
683
684         db->dmasize = db->dma_fragsize * db->numfrag;
685         memset(db->rawbuf, 0, bufs);
686
687         pr_debug("prog_dmabuf: rate=%d, samplesize=%d, channels=%d\n",
688             rate, db->sample_size, db->num_channels);
689         pr_debug("prog_dmabuf: fragsize=%d, cnt_factor=%d, dma_fragsize=%d\n",
690             db->fragsize, db->cnt_factor, db->dma_fragsize);
691         pr_debug("prog_dmabuf: numfrag=%d, dmasize=%d\n", db->numfrag, db->dmasize);
692
693         db->ready = 1;
694         return 0;
695 }
696
697 static int
698 prog_dmabuf_adc(struct au1550_state *s)
699 {
700         stop_adc(s);
701         return prog_dmabuf(s, &s->dma_adc);
702
703 }
704
705 static int
706 prog_dmabuf_dac(struct au1550_state *s)
707 {
708         stop_dac(s);
709         return prog_dmabuf(s, &s->dma_dac);
710 }
711
712
713 static void dac_dma_interrupt(int irq, void *dev_id)
714 {
715         struct au1550_state *s = (struct au1550_state *) dev_id;
716         struct dmabuf  *db = &s->dma_dac;
717         u32     ac97c_stat;
718
719         spin_lock(&s->lock);
720
721         ac97c_stat = au_readl(PSC_AC97STAT);
722         if (ac97c_stat & (AC97C_XU | AC97C_XO | AC97C_TE))
723                 pr_debug("AC97C status = 0x%08x\n", ac97c_stat);
724         db->dma_qcount--;
725
726         if (db->count >= db->fragsize) {
727                 if (au1xxx_dbdma_put_source(db->dmanr,
728                                 virt_to_phys(db->nextOut), db->fragsize,
729                                 DDMA_FLAGS_IE) == 0) {
730                         err("qcount < 2 and no ring room!");
731                 }
732                 db->nextOut += db->fragsize;
733                 if (db->nextOut >= db->rawbuf + db->dmasize)
734                         db->nextOut -= db->dmasize;
735                 db->count -= db->fragsize;
736                 db->total_bytes += db->dma_fragsize;
737                 db->dma_qcount++;
738         }
739
740         /* wake up anybody listening */
741         if (waitqueue_active(&db->wait))
742                 wake_up(&db->wait);
743
744         spin_unlock(&s->lock);
745 }
746
747
748 static void adc_dma_interrupt(int irq, void *dev_id)
749 {
750         struct  au1550_state *s = (struct au1550_state *)dev_id;
751         struct  dmabuf  *dp = &s->dma_adc;
752         u32     obytes;
753         char    *obuf;
754
755         spin_lock(&s->lock);
756
757         /* Pull the buffer from the dma queue.
758         */
759         au1xxx_dbdma_get_dest(dp->dmanr, (void *)(&obuf), &obytes);
760
761         if ((dp->count + obytes) > dp->dmasize) {
762                 /* Overrun. Stop ADC and log the error
763                 */
764                 spin_unlock(&s->lock);
765                 stop_adc(s);
766                 dp->error++;
767                 err("adc overrun");
768                 return;
769         }
770
771         /* Put a new empty buffer on the destination DMA.
772         */
773         au1xxx_dbdma_put_dest(dp->dmanr, virt_to_phys(dp->nextIn),
774                               dp->dma_fragsize, DDMA_FLAGS_IE);
775
776         dp->nextIn += dp->dma_fragsize;
777         if (dp->nextIn >= dp->rawbuf + dp->dmasize)
778                 dp->nextIn -= dp->dmasize;
779
780         dp->count += obytes;
781         dp->total_bytes += obytes;
782
783         /* wake up anybody listening
784         */
785         if (waitqueue_active(&dp->wait))
786                 wake_up(&dp->wait);
787
788         spin_unlock(&s->lock);
789 }
790
791 static loff_t
792 au1550_llseek(struct file *file, loff_t offset, int origin)
793 {
794         return -ESPIPE;
795 }
796
797
798 static int
799 au1550_open_mixdev(struct inode *inode, struct file *file)
800 {
801         lock_kernel();
802         file->private_data = &au1550_state;
803         unlock_kernel();
804         return 0;
805 }
806
807 static int
808 au1550_release_mixdev(struct inode *inode, struct file *file)
809 {
810         return 0;
811 }
812
813 static int
814 mixdev_ioctl(struct ac97_codec *codec, unsigned int cmd,
815                         unsigned long arg)
816 {
817         return codec->mixer_ioctl(codec, cmd, arg);
818 }
819
820 static long
821 au1550_ioctl_mixdev(struct file *file, unsigned int cmd, unsigned long arg)
822 {
823         struct au1550_state *s = (struct au1550_state *)file->private_data;
824         struct ac97_codec *codec = s->codec;
825         int ret;
826
827         lock_kernel();
828         ret = mixdev_ioctl(codec, cmd, arg);
829         unlock_kernel();
830
831         return ret;
832 }
833
834 static /*const */ struct file_operations au1550_mixer_fops = {
835         .owner          = THIS_MODULE,
836         .llseek         = au1550_llseek,
837         .unlocked_ioctl = au1550_ioctl_mixdev,
838         .open           = au1550_open_mixdev,
839         .release        = au1550_release_mixdev,
840 };
841
842 static int
843 drain_dac(struct au1550_state *s, int nonblock)
844 {
845         unsigned long   flags;
846         int             count, tmo;
847
848         if (s->dma_dac.mapped || !s->dma_dac.ready || s->dma_dac.stopped)
849                 return 0;
850
851         for (;;) {
852                 spin_lock_irqsave(&s->lock, flags);
853                 count = s->dma_dac.count;
854                 spin_unlock_irqrestore(&s->lock, flags);
855                 if (count <= s->dma_dac.fragsize)
856                         break;
857                 if (signal_pending(current))
858                         break;
859                 if (nonblock)
860                         return -EBUSY;
861                 tmo = 1000 * count / (s->no_vra ?
862                                       48000 : s->dma_dac.sample_rate);
863                 tmo /= s->dma_dac.dma_bytes_per_sample;
864                 au1550_delay(tmo);
865         }
866         if (signal_pending(current))
867                 return -ERESTARTSYS;
868         return 0;
869 }
870
871 static inline u8 S16_TO_U8(s16 ch)
872 {
873         return (u8) (ch >> 8) + 0x80;
874 }
875 static inline s16 U8_TO_S16(u8 ch)
876 {
877         return (s16) (ch - 0x80) << 8;
878 }
879
880 /*
881  * Translates user samples to dma buffer suitable for AC'97 DAC data:
882  *     If mono, copy left channel to right channel in dma buffer.
883  *     If 8 bit samples, cvt to 16-bit before writing to dma buffer.
884  *     If interpolating (no VRA), duplicate every audio frame src_factor times.
885  */
886 static int
887 translate_from_user(struct dmabuf *db, char* dmabuf, char* userbuf,
888                                                                int dmacount)
889 {
890         int             sample, i;
891         int             interp_bytes_per_sample;
892         int             num_samples;
893         int             mono = (db->num_channels == 1);
894         char            usersample[12];
895         s16             ch, dmasample[6];
896
897         if (db->sample_size == 16 && !mono && db->src_factor == 1) {
898                 /* no translation necessary, just copy
899                 */
900                 if (copy_from_user(dmabuf, userbuf, dmacount))
901                         return -EFAULT;
902                 return dmacount;
903         }
904
905         interp_bytes_per_sample = db->dma_bytes_per_sample * db->src_factor;
906         num_samples = dmacount / interp_bytes_per_sample;
907
908         for (sample = 0; sample < num_samples; sample++) {
909                 if (copy_from_user(usersample, userbuf,
910                                    db->user_bytes_per_sample)) {
911                         return -EFAULT;
912                 }
913
914                 for (i = 0; i < db->num_channels; i++) {
915                         if (db->sample_size == 8)
916                                 ch = U8_TO_S16(usersample[i]);
917                         else
918                                 ch = *((s16 *) (&usersample[i * 2]));
919                         dmasample[i] = ch;
920                         if (mono)
921                                 dmasample[i + 1] = ch;  /* right channel */
922                 }
923
924                 /* duplicate every audio frame src_factor times
925                 */
926                 for (i = 0; i < db->src_factor; i++)
927                         memcpy(dmabuf, dmasample, db->dma_bytes_per_sample);
928
929                 userbuf += db->user_bytes_per_sample;
930                 dmabuf += interp_bytes_per_sample;
931         }
932
933         return num_samples * interp_bytes_per_sample;
934 }
935
936 /*
937  * Translates AC'97 ADC samples to user buffer:
938  *     If mono, send only left channel to user buffer.
939  *     If 8 bit samples, cvt from 16 to 8 bit before writing to user buffer.
940  *     If decimating (no VRA), skip over src_factor audio frames.
941  */
942 static int
943 translate_to_user(struct dmabuf *db, char* userbuf, char* dmabuf,
944                                                              int dmacount)
945 {
946         int             sample, i;
947         int             interp_bytes_per_sample;
948         int             num_samples;
949         int             mono = (db->num_channels == 1);
950         char            usersample[12];
951
952         if (db->sample_size == 16 && !mono && db->src_factor == 1) {
953                 /* no translation necessary, just copy
954                 */
955                 if (copy_to_user(userbuf, dmabuf, dmacount))
956                         return -EFAULT;
957                 return dmacount;
958         }
959
960         interp_bytes_per_sample = db->dma_bytes_per_sample * db->src_factor;
961         num_samples = dmacount / interp_bytes_per_sample;
962
963         for (sample = 0; sample < num_samples; sample++) {
964                 for (i = 0; i < db->num_channels; i++) {
965                         if (db->sample_size == 8)
966                                 usersample[i] =
967                                         S16_TO_U8(*((s16 *) (&dmabuf[i * 2])));
968                         else
969                                 *((s16 *) (&usersample[i * 2])) =
970                                         *((s16 *) (&dmabuf[i * 2]));
971                 }
972
973                 if (copy_to_user(userbuf, usersample,
974                                  db->user_bytes_per_sample)) {
975                         return -EFAULT;
976                 }
977
978                 userbuf += db->user_bytes_per_sample;
979                 dmabuf += interp_bytes_per_sample;
980         }
981
982         return num_samples * interp_bytes_per_sample;
983 }
984
985 /*
986  * Copy audio data to/from user buffer from/to dma buffer, taking care
987  * that we wrap when reading/writing the dma buffer. Returns actual byte
988  * count written to or read from the dma buffer.
989  */
990 static int
991 copy_dmabuf_user(struct dmabuf *db, char* userbuf, int count, int to_user)
992 {
993         char           *bufptr = to_user ? db->nextOut : db->nextIn;
994         char           *bufend = db->rawbuf + db->dmasize;
995         int             cnt, ret;
996
997         if (bufptr + count > bufend) {
998                 int             partial = (int) (bufend - bufptr);
999                 if (to_user) {
1000                         if ((cnt = translate_to_user(db, userbuf,
1001                                                      bufptr, partial)) < 0)
1002                                 return cnt;
1003                         ret = cnt;
1004                         if ((cnt = translate_to_user(db, userbuf + partial,
1005                                                      db->rawbuf,
1006                                                      count - partial)) < 0)
1007                                 return cnt;
1008                         ret += cnt;
1009                 } else {
1010                         if ((cnt = translate_from_user(db, bufptr, userbuf,
1011                                                        partial)) < 0)
1012                                 return cnt;
1013                         ret = cnt;
1014                         if ((cnt = translate_from_user(db, db->rawbuf,
1015                                                        userbuf + partial,
1016                                                        count - partial)) < 0)
1017                                 return cnt;
1018                         ret += cnt;
1019                 }
1020         } else {
1021                 if (to_user)
1022                         ret = translate_to_user(db, userbuf, bufptr, count);
1023                 else
1024                         ret = translate_from_user(db, bufptr, userbuf, count);
1025         }
1026
1027         return ret;
1028 }
1029
1030
1031 static ssize_t
1032 au1550_read(struct file *file, char *buffer, size_t count, loff_t *ppos)
1033 {
1034         struct au1550_state *s = (struct au1550_state *)file->private_data;
1035         struct dmabuf  *db = &s->dma_adc;
1036         DECLARE_WAITQUEUE(wait, current);
1037         ssize_t         ret;
1038         unsigned long   flags;
1039         int             cnt, usercnt, avail;
1040
1041         if (db->mapped)
1042                 return -ENXIO;
1043         if (!access_ok(VERIFY_WRITE, buffer, count))
1044                 return -EFAULT;
1045         ret = 0;
1046
1047         count *= db->cnt_factor;
1048
1049         mutex_lock(&s->sem);
1050         add_wait_queue(&db->wait, &wait);
1051
1052         while (count > 0) {
1053                 /* wait for samples in ADC dma buffer
1054                 */
1055                 do {
1056                         spin_lock_irqsave(&s->lock, flags);
1057                         if (db->stopped)
1058                                 start_adc(s);
1059                         avail = db->count;
1060                         if (avail <= 0)
1061                                 __set_current_state(TASK_INTERRUPTIBLE);
1062                         spin_unlock_irqrestore(&s->lock, flags);
1063                         if (avail <= 0) {
1064                                 if (file->f_flags & O_NONBLOCK) {
1065                                         if (!ret)
1066                                                 ret = -EAGAIN;
1067                                         goto out;
1068                                 }
1069                                 mutex_unlock(&s->sem);
1070                                 schedule();
1071                                 if (signal_pending(current)) {
1072                                         if (!ret)
1073                                                 ret = -ERESTARTSYS;
1074                                         goto out2;
1075                                 }
1076                                 mutex_lock(&s->sem);
1077                         }
1078                 } while (avail <= 0);
1079
1080                 /* copy from nextOut to user
1081                 */
1082                 if ((cnt = copy_dmabuf_user(db, buffer,
1083                                             count > avail ?
1084                                             avail : count, 1)) < 0) {
1085                         if (!ret)
1086                                 ret = -EFAULT;
1087                         goto out;
1088                 }
1089
1090                 spin_lock_irqsave(&s->lock, flags);
1091                 db->count -= cnt;
1092                 db->nextOut += cnt;
1093                 if (db->nextOut >= db->rawbuf + db->dmasize)
1094                         db->nextOut -= db->dmasize;
1095                 spin_unlock_irqrestore(&s->lock, flags);
1096
1097                 count -= cnt;
1098                 usercnt = cnt / db->cnt_factor;
1099                 buffer += usercnt;
1100                 ret += usercnt;
1101         }                       /* while (count > 0) */
1102
1103 out:
1104         mutex_unlock(&s->sem);
1105 out2:
1106         remove_wait_queue(&db->wait, &wait);
1107         set_current_state(TASK_RUNNING);
1108         return ret;
1109 }
1110
1111 static ssize_t
1112 au1550_write(struct file *file, const char *buffer, size_t count, loff_t * ppos)
1113 {
1114         struct au1550_state *s = (struct au1550_state *)file->private_data;
1115         struct dmabuf  *db = &s->dma_dac;
1116         DECLARE_WAITQUEUE(wait, current);
1117         ssize_t         ret = 0;
1118         unsigned long   flags;
1119         int             cnt, usercnt, avail;
1120
1121         pr_debug("write: count=%d\n", count);
1122
1123         if (db->mapped)
1124                 return -ENXIO;
1125         if (!access_ok(VERIFY_READ, buffer, count))
1126                 return -EFAULT;
1127
1128         count *= db->cnt_factor;
1129
1130         mutex_lock(&s->sem);
1131         add_wait_queue(&db->wait, &wait);
1132
1133         while (count > 0) {
1134                 /* wait for space in playback buffer
1135                 */
1136                 do {
1137                         spin_lock_irqsave(&s->lock, flags);
1138                         avail = (int) db->dmasize - db->count;
1139                         if (avail <= 0)
1140                                 __set_current_state(TASK_INTERRUPTIBLE);
1141                         spin_unlock_irqrestore(&s->lock, flags);
1142                         if (avail <= 0) {
1143                                 if (file->f_flags & O_NONBLOCK) {
1144                                         if (!ret)
1145                                                 ret = -EAGAIN;
1146                                         goto out;
1147                                 }
1148                                 mutex_unlock(&s->sem);
1149                                 schedule();
1150                                 if (signal_pending(current)) {
1151                                         if (!ret)
1152                                                 ret = -ERESTARTSYS;
1153                                         goto out2;
1154                                 }
1155                                 mutex_lock(&s->sem);
1156                         }
1157                 } while (avail <= 0);
1158
1159                 /* copy from user to nextIn
1160                 */
1161                 if ((cnt = copy_dmabuf_user(db, (char *) buffer,
1162                                             count > avail ?
1163                                             avail : count, 0)) < 0) {
1164                         if (!ret)
1165                                 ret = -EFAULT;
1166                         goto out;
1167                 }
1168
1169                 spin_lock_irqsave(&s->lock, flags);
1170                 db->count += cnt;
1171                 db->nextIn += cnt;
1172                 if (db->nextIn >= db->rawbuf + db->dmasize)
1173                         db->nextIn -= db->dmasize;
1174
1175                 /* If the data is available, we want to keep two buffers
1176                  * on the dma queue.  If the queue count reaches zero,
1177                  * we know the dma has stopped.
1178                  */
1179                 while ((db->dma_qcount < 2) && (db->count >= db->fragsize)) {
1180                         if (au1xxx_dbdma_put_source(db->dmanr,
1181                                 virt_to_phys(db->nextOut), db->fragsize,
1182                                 DDMA_FLAGS_IE) == 0) {
1183                                 err("qcount < 2 and no ring room!");
1184                         }
1185                         db->nextOut += db->fragsize;
1186                         if (db->nextOut >= db->rawbuf + db->dmasize)
1187                                 db->nextOut -= db->dmasize;
1188                         db->total_bytes += db->dma_fragsize;
1189                         if (db->dma_qcount == 0)
1190                                 start_dac(s);
1191                         db->dma_qcount++;
1192                 }
1193                 spin_unlock_irqrestore(&s->lock, flags);
1194
1195                 count -= cnt;
1196                 usercnt = cnt / db->cnt_factor;
1197                 buffer += usercnt;
1198                 ret += usercnt;
1199         }                       /* while (count > 0) */
1200
1201 out:
1202         mutex_unlock(&s->sem);
1203 out2:
1204         remove_wait_queue(&db->wait, &wait);
1205         set_current_state(TASK_RUNNING);
1206         return ret;
1207 }
1208
1209
1210 /* No kernel lock - we have our own spinlock */
1211 static unsigned int
1212 au1550_poll(struct file *file, struct poll_table_struct *wait)
1213 {
1214         struct au1550_state *s = (struct au1550_state *)file->private_data;
1215         unsigned long   flags;
1216         unsigned int    mask = 0;
1217
1218         if (file->f_mode & FMODE_WRITE) {
1219                 if (!s->dma_dac.ready)
1220                         return 0;
1221                 poll_wait(file, &s->dma_dac.wait, wait);
1222         }
1223         if (file->f_mode & FMODE_READ) {
1224                 if (!s->dma_adc.ready)
1225                         return 0;
1226                 poll_wait(file, &s->dma_adc.wait, wait);
1227         }
1228
1229         spin_lock_irqsave(&s->lock, flags);
1230
1231         if (file->f_mode & FMODE_READ) {
1232                 if (s->dma_adc.count >= (signed)s->dma_adc.dma_fragsize)
1233                         mask |= POLLIN | POLLRDNORM;
1234         }
1235         if (file->f_mode & FMODE_WRITE) {
1236                 if (s->dma_dac.mapped) {
1237                         if (s->dma_dac.count >=
1238                             (signed)s->dma_dac.dma_fragsize)
1239                                 mask |= POLLOUT | POLLWRNORM;
1240                 } else {
1241                         if ((signed) s->dma_dac.dmasize >=
1242                             s->dma_dac.count + (signed)s->dma_dac.dma_fragsize)
1243                                 mask |= POLLOUT | POLLWRNORM;
1244                 }
1245         }
1246         spin_unlock_irqrestore(&s->lock, flags);
1247         return mask;
1248 }
1249
1250 static int
1251 au1550_mmap(struct file *file, struct vm_area_struct *vma)
1252 {
1253         struct au1550_state *s = (struct au1550_state *)file->private_data;
1254         struct dmabuf  *db;
1255         unsigned long   size;
1256         int ret = 0;
1257
1258         lock_kernel();
1259         mutex_lock(&s->sem);
1260         if (vma->vm_flags & VM_WRITE)
1261                 db = &s->dma_dac;
1262         else if (vma->vm_flags & VM_READ)
1263                 db = &s->dma_adc;
1264         else {
1265                 ret = -EINVAL;
1266                 goto out;
1267         }
1268         if (vma->vm_pgoff != 0) {
1269                 ret = -EINVAL;
1270                 goto out;
1271         }
1272         size = vma->vm_end - vma->vm_start;
1273         if (size > (PAGE_SIZE << db->buforder)) {
1274                 ret = -EINVAL;
1275                 goto out;
1276         }
1277         if (remap_pfn_range(vma, vma->vm_start, page_to_pfn(virt_to_page(db->rawbuf)),
1278                              size, vma->vm_page_prot)) {
1279                 ret = -EAGAIN;
1280                 goto out;
1281         }
1282         vma->vm_flags &= ~VM_IO;
1283         db->mapped = 1;
1284 out:
1285         mutex_unlock(&s->sem);
1286         unlock_kernel();
1287         return ret;
1288 }
1289
1290 #ifdef DEBUG
1291 static struct ioctl_str_t {
1292         unsigned int    cmd;
1293         const char     *str;
1294 } ioctl_str[] = {
1295         {SNDCTL_DSP_RESET, "SNDCTL_DSP_RESET"},
1296         {SNDCTL_DSP_SYNC, "SNDCTL_DSP_SYNC"},
1297         {SNDCTL_DSP_SPEED, "SNDCTL_DSP_SPEED"},
1298         {SNDCTL_DSP_STEREO, "SNDCTL_DSP_STEREO"},
1299         {SNDCTL_DSP_GETBLKSIZE, "SNDCTL_DSP_GETBLKSIZE"},
1300         {SNDCTL_DSP_SAMPLESIZE, "SNDCTL_DSP_SAMPLESIZE"},
1301         {SNDCTL_DSP_CHANNELS, "SNDCTL_DSP_CHANNELS"},
1302         {SOUND_PCM_WRITE_CHANNELS, "SOUND_PCM_WRITE_CHANNELS"},
1303         {SOUND_PCM_WRITE_FILTER, "SOUND_PCM_WRITE_FILTER"},
1304         {SNDCTL_DSP_POST, "SNDCTL_DSP_POST"},
1305         {SNDCTL_DSP_SUBDIVIDE, "SNDCTL_DSP_SUBDIVIDE"},
1306         {SNDCTL_DSP_SETFRAGMENT, "SNDCTL_DSP_SETFRAGMENT"},
1307         {SNDCTL_DSP_GETFMTS, "SNDCTL_DSP_GETFMTS"},
1308         {SNDCTL_DSP_SETFMT, "SNDCTL_DSP_SETFMT"},
1309         {SNDCTL_DSP_GETOSPACE, "SNDCTL_DSP_GETOSPACE"},
1310         {SNDCTL_DSP_GETISPACE, "SNDCTL_DSP_GETISPACE"},
1311         {SNDCTL_DSP_NONBLOCK, "SNDCTL_DSP_NONBLOCK"},
1312         {SNDCTL_DSP_GETCAPS, "SNDCTL_DSP_GETCAPS"},
1313         {SNDCTL_DSP_GETTRIGGER, "SNDCTL_DSP_GETTRIGGER"},
1314         {SNDCTL_DSP_SETTRIGGER, "SNDCTL_DSP_SETTRIGGER"},
1315         {SNDCTL_DSP_GETIPTR, "SNDCTL_DSP_GETIPTR"},
1316         {SNDCTL_DSP_GETOPTR, "SNDCTL_DSP_GETOPTR"},
1317         {SNDCTL_DSP_MAPINBUF, "SNDCTL_DSP_MAPINBUF"},
1318         {SNDCTL_DSP_MAPOUTBUF, "SNDCTL_DSP_MAPOUTBUF"},
1319         {SNDCTL_DSP_SETSYNCRO, "SNDCTL_DSP_SETSYNCRO"},
1320         {SNDCTL_DSP_SETDUPLEX, "SNDCTL_DSP_SETDUPLEX"},
1321         {SNDCTL_DSP_GETODELAY, "SNDCTL_DSP_GETODELAY"},
1322         {SNDCTL_DSP_GETCHANNELMASK, "SNDCTL_DSP_GETCHANNELMASK"},
1323         {SNDCTL_DSP_BIND_CHANNEL, "SNDCTL_DSP_BIND_CHANNEL"},
1324         {OSS_GETVERSION, "OSS_GETVERSION"},
1325         {SOUND_PCM_READ_RATE, "SOUND_PCM_READ_RATE"},
1326         {SOUND_PCM_READ_CHANNELS, "SOUND_PCM_READ_CHANNELS"},
1327         {SOUND_PCM_READ_BITS, "SOUND_PCM_READ_BITS"},
1328         {SOUND_PCM_READ_FILTER, "SOUND_PCM_READ_FILTER"}
1329 };
1330 #endif
1331
1332 static int
1333 dma_count_done(struct dmabuf *db)
1334 {
1335         if (db->stopped)
1336                 return 0;
1337
1338         return db->dma_fragsize - au1xxx_get_dma_residue(db->dmanr);
1339 }
1340
1341
1342 static int
1343 au1550_ioctl(struct file *file, unsigned int cmd, unsigned long arg)
1344 {
1345         struct au1550_state *s = (struct au1550_state *)file->private_data;
1346         unsigned long   flags;
1347         audio_buf_info  abinfo;
1348         count_info      cinfo;
1349         int             count;
1350         int             val, mapped, ret, diff;
1351
1352         mapped = ((file->f_mode & FMODE_WRITE) && s->dma_dac.mapped) ||
1353                 ((file->f_mode & FMODE_READ) && s->dma_adc.mapped);
1354
1355 #ifdef DEBUG
1356         for (count = 0; count < ARRAY_SIZE(ioctl_str); count++) {
1357                 if (ioctl_str[count].cmd == cmd)
1358                         break;
1359         }
1360         if (count < ARRAY_SIZE(ioctl_str))
1361                 pr_debug("ioctl %s, arg=0x%lxn", ioctl_str[count].str, arg);
1362         else
1363                 pr_debug("ioctl 0x%x unknown, arg=0x%lx\n", cmd, arg);
1364 #endif
1365
1366         switch (cmd) {
1367         case OSS_GETVERSION:
1368                 return put_user(SOUND_VERSION, (int *) arg);
1369
1370         case SNDCTL_DSP_SYNC:
1371                 if (file->f_mode & FMODE_WRITE)
1372                         return drain_dac(s, file->f_flags & O_NONBLOCK);
1373                 return 0;
1374
1375         case SNDCTL_DSP_SETDUPLEX:
1376                 return 0;
1377
1378         case SNDCTL_DSP_GETCAPS:
1379                 return put_user(DSP_CAP_DUPLEX | DSP_CAP_REALTIME |
1380                                 DSP_CAP_TRIGGER | DSP_CAP_MMAP, (int *)arg);
1381
1382         case SNDCTL_DSP_RESET:
1383                 if (file->f_mode & FMODE_WRITE) {
1384                         stop_dac(s);
1385                         synchronize_irq();
1386                         s->dma_dac.count = s->dma_dac.total_bytes = 0;
1387                         s->dma_dac.nextIn = s->dma_dac.nextOut =
1388                                 s->dma_dac.rawbuf;
1389                 }
1390                 if (file->f_mode & FMODE_READ) {
1391                         stop_adc(s);
1392                         synchronize_irq();
1393                         s->dma_adc.count = s->dma_adc.total_bytes = 0;
1394                         s->dma_adc.nextIn = s->dma_adc.nextOut =
1395                                 s->dma_adc.rawbuf;
1396                 }
1397                 return 0;
1398
1399         case SNDCTL_DSP_SPEED:
1400                 if (get_user(val, (int *) arg))
1401                         return -EFAULT;
1402                 if (val >= 0) {
1403                         if (file->f_mode & FMODE_READ) {
1404                                 stop_adc(s);
1405                                 set_adc_rate(s, val);
1406                         }
1407                         if (file->f_mode & FMODE_WRITE) {
1408                                 stop_dac(s);
1409                                 set_dac_rate(s, val);
1410                         }
1411                         if (s->open_mode & FMODE_READ)
1412                                 if ((ret = prog_dmabuf_adc(s)))
1413                                         return ret;
1414                         if (s->open_mode & FMODE_WRITE)
1415                                 if ((ret = prog_dmabuf_dac(s)))
1416                                         return ret;
1417                 }
1418                 return put_user((file->f_mode & FMODE_READ) ?
1419                                 s->dma_adc.sample_rate :
1420                                 s->dma_dac.sample_rate,
1421                                 (int *)arg);
1422
1423         case SNDCTL_DSP_STEREO:
1424                 if (get_user(val, (int *) arg))
1425                         return -EFAULT;
1426                 if (file->f_mode & FMODE_READ) {
1427                         stop_adc(s);
1428                         s->dma_adc.num_channels = val ? 2 : 1;
1429                         if ((ret = prog_dmabuf_adc(s)))
1430                                 return ret;
1431                 }
1432                 if (file->f_mode & FMODE_WRITE) {
1433                         stop_dac(s);
1434                         s->dma_dac.num_channels = val ? 2 : 1;
1435                         if (s->codec_ext_caps & AC97_EXT_DACS) {
1436                                 /* disable surround and center/lfe in AC'97
1437                                 */
1438                                 u16 ext_stat = rdcodec(s->codec,
1439                                                        AC97_EXTENDED_STATUS);
1440                                 wrcodec(s->codec, AC97_EXTENDED_STATUS,
1441                                         ext_stat | (AC97_EXTSTAT_PRI |
1442                                                     AC97_EXTSTAT_PRJ |
1443                                                     AC97_EXTSTAT_PRK));
1444                         }
1445                         if ((ret = prog_dmabuf_dac(s)))
1446                                 return ret;
1447                 }
1448                 return 0;
1449
1450         case SNDCTL_DSP_CHANNELS:
1451                 if (get_user(val, (int *) arg))
1452                         return -EFAULT;
1453                 if (val != 0) {
1454                         if (file->f_mode & FMODE_READ) {
1455                                 if (val < 0 || val > 2)
1456                                         return -EINVAL;
1457                                 stop_adc(s);
1458                                 s->dma_adc.num_channels = val;
1459                                 if ((ret = prog_dmabuf_adc(s)))
1460                                         return ret;
1461                         }
1462                         if (file->f_mode & FMODE_WRITE) {
1463                                 switch (val) {
1464                                 case 1:
1465                                 case 2:
1466                                         break;
1467                                 case 3:
1468                                 case 5:
1469                                         return -EINVAL;
1470                                 case 4:
1471                                         if (!(s->codec_ext_caps &
1472                                               AC97_EXTID_SDAC))
1473                                                 return -EINVAL;
1474                                         break;
1475                                 case 6:
1476                                         if ((s->codec_ext_caps &
1477                                              AC97_EXT_DACS) != AC97_EXT_DACS)
1478                                                 return -EINVAL;
1479                                         break;
1480                                 default:
1481                                         return -EINVAL;
1482                                 }
1483
1484                                 stop_dac(s);
1485                                 if (val <= 2 &&
1486                                     (s->codec_ext_caps & AC97_EXT_DACS)) {
1487                                         /* disable surround and center/lfe
1488                                          * channels in AC'97
1489                                          */
1490                                         u16             ext_stat =
1491                                                 rdcodec(s->codec,
1492                                                         AC97_EXTENDED_STATUS);
1493                                         wrcodec(s->codec,
1494                                                 AC97_EXTENDED_STATUS,
1495                                                 ext_stat | (AC97_EXTSTAT_PRI |
1496                                                             AC97_EXTSTAT_PRJ |
1497                                                             AC97_EXTSTAT_PRK));
1498                                 } else if (val >= 4) {
1499                                         /* enable surround, center/lfe
1500                                          * channels in AC'97
1501                                          */
1502                                         u16             ext_stat =
1503                                                 rdcodec(s->codec,
1504                                                         AC97_EXTENDED_STATUS);
1505                                         ext_stat &= ~AC97_EXTSTAT_PRJ;
1506                                         if (val == 6)
1507                                                 ext_stat &=
1508                                                         ~(AC97_EXTSTAT_PRI |
1509                                                           AC97_EXTSTAT_PRK);
1510                                         wrcodec(s->codec,
1511                                                 AC97_EXTENDED_STATUS,
1512                                                 ext_stat);
1513                                 }
1514
1515                                 s->dma_dac.num_channels = val;
1516                                 if ((ret = prog_dmabuf_dac(s)))
1517                                         return ret;
1518                         }
1519                 }
1520                 return put_user(val, (int *) arg);
1521
1522         case SNDCTL_DSP_GETFMTS:        /* Returns a mask */
1523                 return put_user(AFMT_S16_LE | AFMT_U8, (int *) arg);
1524
1525         case SNDCTL_DSP_SETFMT: /* Selects ONE fmt */
1526                 if (get_user(val, (int *) arg))
1527                         return -EFAULT;
1528                 if (val != AFMT_QUERY) {
1529                         if (file->f_mode & FMODE_READ) {
1530                                 stop_adc(s);
1531                                 if (val == AFMT_S16_LE)
1532                                         s->dma_adc.sample_size = 16;
1533                                 else {
1534                                         val = AFMT_U8;
1535                                         s->dma_adc.sample_size = 8;
1536                                 }
1537                                 if ((ret = prog_dmabuf_adc(s)))
1538                                         return ret;
1539                         }
1540                         if (file->f_mode & FMODE_WRITE) {
1541                                 stop_dac(s);
1542                                 if (val == AFMT_S16_LE)
1543                                         s->dma_dac.sample_size = 16;
1544                                 else {
1545                                         val = AFMT_U8;
1546                                         s->dma_dac.sample_size = 8;
1547                                 }
1548                                 if ((ret = prog_dmabuf_dac(s)))
1549                                         return ret;
1550                         }
1551                 } else {
1552                         if (file->f_mode & FMODE_READ)
1553                                 val = (s->dma_adc.sample_size == 16) ?
1554                                         AFMT_S16_LE : AFMT_U8;
1555                         else
1556                                 val = (s->dma_dac.sample_size == 16) ?
1557                                         AFMT_S16_LE : AFMT_U8;
1558                 }
1559                 return put_user(val, (int *) arg);
1560
1561         case SNDCTL_DSP_POST:
1562                 return 0;
1563
1564         case SNDCTL_DSP_GETTRIGGER:
1565                 val = 0;
1566                 spin_lock_irqsave(&s->lock, flags);
1567                 if (file->f_mode & FMODE_READ && !s->dma_adc.stopped)
1568                         val |= PCM_ENABLE_INPUT;
1569                 if (file->f_mode & FMODE_WRITE && !s->dma_dac.stopped)
1570                         val |= PCM_ENABLE_OUTPUT;
1571                 spin_unlock_irqrestore(&s->lock, flags);
1572                 return put_user(val, (int *) arg);
1573
1574         case SNDCTL_DSP_SETTRIGGER:
1575                 if (get_user(val, (int *) arg))
1576                         return -EFAULT;
1577                 if (file->f_mode & FMODE_READ) {
1578                         if (val & PCM_ENABLE_INPUT) {
1579                                 spin_lock_irqsave(&s->lock, flags);
1580                                 start_adc(s);
1581                                 spin_unlock_irqrestore(&s->lock, flags);
1582                         } else
1583                                 stop_adc(s);
1584                 }
1585                 if (file->f_mode & FMODE_WRITE) {
1586                         if (val & PCM_ENABLE_OUTPUT) {
1587                                 spin_lock_irqsave(&s->lock, flags);
1588                                 start_dac(s);
1589                                 spin_unlock_irqrestore(&s->lock, flags);
1590                         } else
1591                                 stop_dac(s);
1592                 }
1593                 return 0;
1594
1595         case SNDCTL_DSP_GETOSPACE:
1596                 if (!(file->f_mode & FMODE_WRITE))
1597                         return -EINVAL;
1598                 abinfo.fragsize = s->dma_dac.fragsize;
1599                 spin_lock_irqsave(&s->lock, flags);
1600                 count = s->dma_dac.count;
1601                 count -= dma_count_done(&s->dma_dac);
1602                 spin_unlock_irqrestore(&s->lock, flags);
1603                 if (count < 0)
1604                         count = 0;
1605                 abinfo.bytes = (s->dma_dac.dmasize - count) /
1606                         s->dma_dac.cnt_factor;
1607                 abinfo.fragstotal = s->dma_dac.numfrag;
1608                 abinfo.fragments = abinfo.bytes >> s->dma_dac.fragshift;
1609                 pr_debug("ioctl SNDCTL_DSP_GETOSPACE: bytes=%d, fragments=%d\n", abinfo.bytes, abinfo.fragments);
1610                 return copy_to_user((void *) arg, &abinfo,
1611                                     sizeof(abinfo)) ? -EFAULT : 0;
1612
1613         case SNDCTL_DSP_GETISPACE:
1614                 if (!(file->f_mode & FMODE_READ))
1615                         return -EINVAL;
1616                 abinfo.fragsize = s->dma_adc.fragsize;
1617                 spin_lock_irqsave(&s->lock, flags);
1618                 count = s->dma_adc.count;
1619                 count += dma_count_done(&s->dma_adc);
1620                 spin_unlock_irqrestore(&s->lock, flags);
1621                 if (count < 0)
1622                         count = 0;
1623                 abinfo.bytes = count / s->dma_adc.cnt_factor;
1624                 abinfo.fragstotal = s->dma_adc.numfrag;
1625                 abinfo.fragments = abinfo.bytes >> s->dma_adc.fragshift;
1626                 return copy_to_user((void *) arg, &abinfo,
1627                                     sizeof(abinfo)) ? -EFAULT : 0;
1628
1629         case SNDCTL_DSP_NONBLOCK:
1630                 spin_lock(&file->f_lock);
1631                 file->f_flags |= O_NONBLOCK;
1632                 spin_unlock(&file->f_lock);
1633                 return 0;
1634
1635         case SNDCTL_DSP_GETODELAY:
1636                 if (!(file->f_mode & FMODE_WRITE))
1637                         return -EINVAL;
1638                 spin_lock_irqsave(&s->lock, flags);
1639                 count = s->dma_dac.count;
1640                 count -= dma_count_done(&s->dma_dac);
1641                 spin_unlock_irqrestore(&s->lock, flags);
1642                 if (count < 0)
1643                         count = 0;
1644                 count /= s->dma_dac.cnt_factor;
1645                 return put_user(count, (int *) arg);
1646
1647         case SNDCTL_DSP_GETIPTR:
1648                 if (!(file->f_mode & FMODE_READ))
1649                         return -EINVAL;
1650                 spin_lock_irqsave(&s->lock, flags);
1651                 cinfo.bytes = s->dma_adc.total_bytes;
1652                 count = s->dma_adc.count;
1653                 if (!s->dma_adc.stopped) {
1654                         diff = dma_count_done(&s->dma_adc);
1655                         count += diff;
1656                         cinfo.bytes += diff;
1657                         cinfo.ptr =  virt_to_phys(s->dma_adc.nextIn) + diff -
1658                                 virt_to_phys(s->dma_adc.rawbuf);
1659                 } else
1660                         cinfo.ptr = virt_to_phys(s->dma_adc.nextIn) -
1661                                 virt_to_phys(s->dma_adc.rawbuf);
1662                 if (s->dma_adc.mapped)
1663                         s->dma_adc.count &= (s->dma_adc.dma_fragsize-1);
1664                 spin_unlock_irqrestore(&s->lock, flags);
1665                 if (count < 0)
1666                         count = 0;
1667                 cinfo.blocks = count >> s->dma_adc.fragshift;
1668                 return copy_to_user((void *) arg, &cinfo, sizeof(cinfo));
1669
1670         case SNDCTL_DSP_GETOPTR:
1671                 if (!(file->f_mode & FMODE_READ))
1672                         return -EINVAL;
1673                 spin_lock_irqsave(&s->lock, flags);
1674                 cinfo.bytes = s->dma_dac.total_bytes;
1675                 count = s->dma_dac.count;
1676                 if (!s->dma_dac.stopped) {
1677                         diff = dma_count_done(&s->dma_dac);
1678                         count -= diff;
1679                         cinfo.bytes += diff;
1680                         cinfo.ptr = virt_to_phys(s->dma_dac.nextOut) + diff -
1681                                 virt_to_phys(s->dma_dac.rawbuf);
1682                 } else
1683                         cinfo.ptr = virt_to_phys(s->dma_dac.nextOut) -
1684                                 virt_to_phys(s->dma_dac.rawbuf);
1685                 if (s->dma_dac.mapped)
1686                         s->dma_dac.count &= (s->dma_dac.dma_fragsize-1);
1687                 spin_unlock_irqrestore(&s->lock, flags);
1688                 if (count < 0)
1689                         count = 0;
1690                 cinfo.blocks = count >> s->dma_dac.fragshift;
1691                 return copy_to_user((void *) arg, &cinfo, sizeof(cinfo));
1692
1693         case SNDCTL_DSP_GETBLKSIZE:
1694                 if (file->f_mode & FMODE_WRITE)
1695                         return put_user(s->dma_dac.fragsize, (int *) arg);
1696                 else
1697                         return put_user(s->dma_adc.fragsize, (int *) arg);
1698
1699         case SNDCTL_DSP_SETFRAGMENT:
1700                 if (get_user(val, (int *) arg))
1701                         return -EFAULT;
1702                 if (file->f_mode & FMODE_READ) {
1703                         stop_adc(s);
1704                         s->dma_adc.ossfragshift = val & 0xffff;
1705                         s->dma_adc.ossmaxfrags = (val >> 16) & 0xffff;
1706                         if (s->dma_adc.ossfragshift < 4)
1707                                 s->dma_adc.ossfragshift = 4;
1708                         if (s->dma_adc.ossfragshift > 15)
1709                                 s->dma_adc.ossfragshift = 15;
1710                         if (s->dma_adc.ossmaxfrags < 4)
1711                                 s->dma_adc.ossmaxfrags = 4;
1712                         if ((ret = prog_dmabuf_adc(s)))
1713                                 return ret;
1714                 }
1715                 if (file->f_mode & FMODE_WRITE) {
1716                         stop_dac(s);
1717                         s->dma_dac.ossfragshift = val & 0xffff;
1718                         s->dma_dac.ossmaxfrags = (val >> 16) & 0xffff;
1719                         if (s->dma_dac.ossfragshift < 4)
1720                                 s->dma_dac.ossfragshift = 4;
1721                         if (s->dma_dac.ossfragshift > 15)
1722                                 s->dma_dac.ossfragshift = 15;
1723                         if (s->dma_dac.ossmaxfrags < 4)
1724                                 s->dma_dac.ossmaxfrags = 4;
1725                         if ((ret = prog_dmabuf_dac(s)))
1726                                 return ret;
1727                 }
1728                 return 0;
1729
1730         case SNDCTL_DSP_SUBDIVIDE:
1731                 if ((file->f_mode & FMODE_READ && s->dma_adc.subdivision) ||
1732                     (file->f_mode & FMODE_WRITE && s->dma_dac.subdivision))
1733                         return -EINVAL;
1734                 if (get_user(val, (int *) arg))
1735                         return -EFAULT;
1736                 if (val != 1 && val != 2 && val != 4)
1737                         return -EINVAL;
1738                 if (file->f_mode & FMODE_READ) {
1739                         stop_adc(s);
1740                         s->dma_adc.subdivision = val;
1741                         if ((ret = prog_dmabuf_adc(s)))
1742                                 return ret;
1743                 }
1744                 if (file->f_mode & FMODE_WRITE) {
1745                         stop_dac(s);
1746                         s->dma_dac.subdivision = val;
1747                         if ((ret = prog_dmabuf_dac(s)))
1748                                 return ret;
1749                 }
1750                 return 0;
1751
1752         case SOUND_PCM_READ_RATE:
1753                 return put_user((file->f_mode & FMODE_READ) ?
1754                                 s->dma_adc.sample_rate :
1755                                 s->dma_dac.sample_rate,
1756                                 (int *)arg);
1757
1758         case SOUND_PCM_READ_CHANNELS:
1759                 if (file->f_mode & FMODE_READ)
1760                         return put_user(s->dma_adc.num_channels, (int *)arg);
1761                 else
1762                         return put_user(s->dma_dac.num_channels, (int *)arg);
1763
1764         case SOUND_PCM_READ_BITS:
1765                 if (file->f_mode & FMODE_READ)
1766                         return put_user(s->dma_adc.sample_size, (int *)arg);
1767                 else
1768                         return put_user(s->dma_dac.sample_size, (int *)arg);
1769
1770         case SOUND_PCM_WRITE_FILTER:
1771         case SNDCTL_DSP_SETSYNCRO:
1772         case SOUND_PCM_READ_FILTER:
1773                 return -EINVAL;
1774         }
1775
1776         return mixdev_ioctl(s->codec, cmd, arg);
1777 }
1778
1779 static long
1780 au1550_unlocked_ioctl(struct file *file, unsigned int cmd, unsigned long arg)
1781 {
1782         int ret;
1783
1784         lock_kernel();
1785         ret = au1550_ioctl(file, cmd, arg);
1786         unlock_kernel();
1787
1788         return ret;
1789 }
1790
1791 static int
1792 au1550_open(struct inode *inode, struct file *file)
1793 {
1794         int             minor = MINOR(inode->i_rdev);
1795         DECLARE_WAITQUEUE(wait, current);
1796         struct au1550_state *s = &au1550_state;
1797         int             ret;
1798
1799 #ifdef DEBUG
1800         if (file->f_flags & O_NONBLOCK)
1801                 pr_debug("open: non-blocking\n");
1802         else
1803                 pr_debug("open: blocking\n");
1804 #endif
1805
1806         file->private_data = s;
1807         lock_kernel();
1808         /* wait for device to become free */
1809         mutex_lock(&s->open_mutex);
1810         while (s->open_mode & file->f_mode) {
1811                 ret = -EBUSY;
1812                 if (file->f_flags & O_NONBLOCK)
1813                         goto out;
1814                 add_wait_queue(&s->open_wait, &wait);
1815                 __set_current_state(TASK_INTERRUPTIBLE);
1816                 mutex_unlock(&s->open_mutex);
1817                 schedule();
1818                 remove_wait_queue(&s->open_wait, &wait);
1819                 set_current_state(TASK_RUNNING);
1820                 ret = -ERESTARTSYS;
1821                 if (signal_pending(current))
1822                         goto out2;
1823                 mutex_lock(&s->open_mutex);
1824         }
1825
1826         stop_dac(s);
1827         stop_adc(s);
1828
1829         if (file->f_mode & FMODE_READ) {
1830                 s->dma_adc.ossfragshift = s->dma_adc.ossmaxfrags =
1831                         s->dma_adc.subdivision = s->dma_adc.total_bytes = 0;
1832                 s->dma_adc.num_channels = 1;
1833                 s->dma_adc.sample_size = 8;
1834                 set_adc_rate(s, 8000);
1835                 if ((minor & 0xf) == SND_DEV_DSP16)
1836                         s->dma_adc.sample_size = 16;
1837         }
1838
1839         if (file->f_mode & FMODE_WRITE) {
1840                 s->dma_dac.ossfragshift = s->dma_dac.ossmaxfrags =
1841                         s->dma_dac.subdivision = s->dma_dac.total_bytes = 0;
1842                 s->dma_dac.num_channels = 1;
1843                 s->dma_dac.sample_size = 8;
1844                 set_dac_rate(s, 8000);
1845                 if ((minor & 0xf) == SND_DEV_DSP16)
1846                         s->dma_dac.sample_size = 16;
1847         }
1848
1849         if (file->f_mode & FMODE_READ) {
1850                 if ((ret = prog_dmabuf_adc(s)))
1851                         goto out;
1852         }
1853         if (file->f_mode & FMODE_WRITE) {
1854                 if ((ret = prog_dmabuf_dac(s)))
1855                         goto out;
1856         }
1857
1858         s->open_mode |= file->f_mode & (FMODE_READ | FMODE_WRITE);
1859         mutex_init(&s->sem);
1860         ret = 0;
1861 out:
1862         mutex_unlock(&s->open_mutex);
1863 out2:
1864         unlock_kernel();
1865         return ret;
1866 }
1867
1868 static int
1869 au1550_release(struct inode *inode, struct file *file)
1870 {
1871         struct au1550_state *s = (struct au1550_state *)file->private_data;
1872
1873         lock_kernel();
1874
1875         if (file->f_mode & FMODE_WRITE) {
1876                 unlock_kernel();
1877                 drain_dac(s, file->f_flags & O_NONBLOCK);
1878                 lock_kernel();
1879         }
1880
1881         mutex_lock(&s->open_mutex);
1882         if (file->f_mode & FMODE_WRITE) {
1883                 stop_dac(s);
1884                 kfree(s->dma_dac.rawbuf);
1885                 s->dma_dac.rawbuf = NULL;
1886         }
1887         if (file->f_mode & FMODE_READ) {
1888                 stop_adc(s);
1889                 kfree(s->dma_adc.rawbuf);
1890                 s->dma_adc.rawbuf = NULL;
1891         }
1892         s->open_mode &= ((~file->f_mode) & (FMODE_READ|FMODE_WRITE));
1893         mutex_unlock(&s->open_mutex);
1894         wake_up(&s->open_wait);
1895         unlock_kernel();
1896         return 0;
1897 }
1898
1899 static /*const */ struct file_operations au1550_audio_fops = {
1900         .owner          = THIS_MODULE,
1901         .llseek         = au1550_llseek,
1902         .read           = au1550_read,
1903         .write          = au1550_write,
1904         .poll           = au1550_poll,
1905         .unlocked_ioctl = au1550_unlocked_ioctl,
1906         .mmap           = au1550_mmap,
1907         .open           = au1550_open,
1908         .release        = au1550_release,
1909 };
1910
1911 MODULE_AUTHOR("Advanced Micro Devices (AMD), dan@embeddededge.com");
1912 MODULE_DESCRIPTION("Au1550 AC97 Audio Driver");
1913 MODULE_LICENSE("GPL");
1914
1915
1916 static int __devinit
1917 au1550_probe(void)
1918 {
1919         struct au1550_state *s = &au1550_state;
1920         int             val;
1921
1922         memset(s, 0, sizeof(struct au1550_state));
1923
1924         init_waitqueue_head(&s->dma_adc.wait);
1925         init_waitqueue_head(&s->dma_dac.wait);
1926         init_waitqueue_head(&s->open_wait);
1927         mutex_init(&s->open_mutex);
1928         spin_lock_init(&s->lock);
1929
1930         s->codec = ac97_alloc_codec();
1931         if(s->codec == NULL) {
1932                 err("Out of memory");
1933                 return -1;
1934         }
1935         s->codec->private_data = s;
1936         s->codec->id = 0;
1937         s->codec->codec_read = rdcodec;
1938         s->codec->codec_write = wrcodec;
1939         s->codec->codec_wait = waitcodec;
1940
1941         if (!request_mem_region(CPHYSADDR(AC97_PSC_SEL),
1942                             0x30, "Au1550 AC97")) {
1943                 err("AC'97 ports in use");
1944         }
1945
1946         /* Allocate the DMA Channels
1947         */
1948         if ((s->dma_dac.dmanr = au1xxx_dbdma_chan_alloc(DBDMA_MEM_CHAN,
1949             DBDMA_AC97_TX_CHAN, dac_dma_interrupt, (void *)s)) == 0) {
1950                 err("Can't get DAC DMA");
1951                 goto err_dma1;
1952         }
1953         au1xxx_dbdma_set_devwidth(s->dma_dac.dmanr, 16);
1954         if (au1xxx_dbdma_ring_alloc(s->dma_dac.dmanr,
1955                                         NUM_DBDMA_DESCRIPTORS) == 0) {
1956                 err("Can't get DAC DMA descriptors");
1957                 goto err_dma1;
1958         }
1959
1960         if ((s->dma_adc.dmanr = au1xxx_dbdma_chan_alloc(DBDMA_AC97_RX_CHAN,
1961             DBDMA_MEM_CHAN, adc_dma_interrupt, (void *)s)) == 0) {
1962                 err("Can't get ADC DMA");
1963                 goto err_dma2;
1964         }
1965         au1xxx_dbdma_set_devwidth(s->dma_adc.dmanr, 16);
1966         if (au1xxx_dbdma_ring_alloc(s->dma_adc.dmanr,
1967                                         NUM_DBDMA_DESCRIPTORS) == 0) {
1968                 err("Can't get ADC DMA descriptors");
1969                 goto err_dma2;
1970         }
1971
1972         pr_info("DAC: DMA%d, ADC: DMA%d", DBDMA_AC97_TX_CHAN, DBDMA_AC97_RX_CHAN);
1973
1974         /* register devices */
1975
1976         if ((s->dev_audio = register_sound_dsp(&au1550_audio_fops, -1)) < 0)
1977                 goto err_dev1;
1978         if ((s->codec->dev_mixer =
1979              register_sound_mixer(&au1550_mixer_fops, -1)) < 0)
1980                 goto err_dev2;
1981
1982         /* The GPIO for the appropriate PSC was configured by the
1983          * board specific start up.
1984          *
1985          * configure PSC for AC'97
1986          */
1987         au_writel(0, AC97_PSC_CTRL);    /* Disable PSC */
1988         au_sync();
1989         au_writel((PSC_SEL_CLK_SERCLK | PSC_SEL_PS_AC97MODE), AC97_PSC_SEL);
1990         au_sync();
1991
1992         /* cold reset the AC'97
1993         */
1994         au_writel(PSC_AC97RST_RST, PSC_AC97RST);
1995         au_sync();
1996         au1550_delay(10);
1997         au_writel(0, PSC_AC97RST);
1998         au_sync();
1999
2000         /* need to delay around 500msec(bleech) to give
2001            some CODECs enough time to wakeup */
2002         au1550_delay(500);
2003
2004         /* warm reset the AC'97 to start the bitclk
2005         */
2006         au_writel(PSC_AC97RST_SNC, PSC_AC97RST);
2007         au_sync();
2008         udelay(100);
2009         au_writel(0, PSC_AC97RST);
2010         au_sync();
2011
2012         /* Enable PSC
2013         */
2014         au_writel(PSC_CTRL_ENABLE, AC97_PSC_CTRL);
2015         au_sync();
2016
2017         /* Wait for PSC ready.
2018         */
2019         do {
2020                 val = au_readl(PSC_AC97STAT);
2021                 au_sync();
2022         } while ((val & PSC_AC97STAT_SR) == 0);
2023
2024         /* Configure AC97 controller.
2025          * Deep FIFO, 16-bit sample, DMA, make sure DMA matches fifo size.
2026          */
2027         val = PSC_AC97CFG_SET_LEN(16);
2028         val |= PSC_AC97CFG_RT_FIFO8 | PSC_AC97CFG_TT_FIFO8;
2029
2030         /* Enable device so we can at least
2031          * talk over the AC-link.
2032          */
2033         au_writel(val, PSC_AC97CFG);
2034         au_writel(PSC_AC97MSK_ALLMASK, PSC_AC97MSK);
2035         au_sync();
2036         val |= PSC_AC97CFG_DE_ENABLE;
2037         au_writel(val, PSC_AC97CFG);
2038         au_sync();
2039
2040         /* Wait for Device ready.
2041         */
2042         do {
2043                 val = au_readl(PSC_AC97STAT);
2044                 au_sync();
2045         } while ((val & PSC_AC97STAT_DR) == 0);
2046
2047         /* codec init */
2048         if (!ac97_probe_codec(s->codec))
2049                 goto err_dev3;
2050
2051         s->codec_base_caps = rdcodec(s->codec, AC97_RESET);
2052         s->codec_ext_caps = rdcodec(s->codec, AC97_EXTENDED_ID);
2053         pr_info("AC'97 Base/Extended ID = %04x/%04x",
2054              s->codec_base_caps, s->codec_ext_caps);
2055
2056         if (!(s->codec_ext_caps & AC97_EXTID_VRA)) {
2057                 /* codec does not support VRA
2058                 */
2059                 s->no_vra = 1;
2060         } else if (!vra) {
2061                 /* Boot option says disable VRA
2062                 */
2063                 u16 ac97_extstat = rdcodec(s->codec, AC97_EXTENDED_STATUS);
2064                 wrcodec(s->codec, AC97_EXTENDED_STATUS,
2065                         ac97_extstat & ~AC97_EXTSTAT_VRA);
2066                 s->no_vra = 1;
2067         }
2068         if (s->no_vra)
2069                 pr_info("no VRA, interpolating and decimating");
2070
2071         /* set mic to be the recording source */
2072         val = SOUND_MASK_MIC;
2073         mixdev_ioctl(s->codec, SOUND_MIXER_WRITE_RECSRC,
2074                      (unsigned long) &val);
2075
2076         return 0;
2077
2078  err_dev3:
2079         unregister_sound_mixer(s->codec->dev_mixer);
2080  err_dev2:
2081         unregister_sound_dsp(s->dev_audio);
2082  err_dev1:
2083         au1xxx_dbdma_chan_free(s->dma_adc.dmanr);
2084  err_dma2:
2085         au1xxx_dbdma_chan_free(s->dma_dac.dmanr);
2086  err_dma1:
2087         release_mem_region(CPHYSADDR(AC97_PSC_SEL), 0x30);
2088
2089         ac97_release_codec(s->codec);
2090         return -1;
2091 }
2092
2093 static void __devinit
2094 au1550_remove(void)
2095 {
2096         struct au1550_state *s = &au1550_state;
2097
2098         if (!s)
2099                 return;
2100         synchronize_irq();
2101         au1xxx_dbdma_chan_free(s->dma_adc.dmanr);
2102         au1xxx_dbdma_chan_free(s->dma_dac.dmanr);
2103         release_mem_region(CPHYSADDR(AC97_PSC_SEL), 0x30);
2104         unregister_sound_dsp(s->dev_audio);
2105         unregister_sound_mixer(s->codec->dev_mixer);
2106         ac97_release_codec(s->codec);
2107 }
2108
2109 static int __init
2110 init_au1550(void)
2111 {
2112         return au1550_probe();
2113 }
2114
2115 static void __exit
2116 cleanup_au1550(void)
2117 {
2118         au1550_remove();
2119 }
2120
2121 module_init(init_au1550);
2122 module_exit(cleanup_au1550);
2123
2124 #ifndef MODULE
2125
2126 static int __init
2127 au1550_setup(char *options)
2128 {
2129         char           *this_opt;
2130
2131         if (!options || !*options)
2132                 return 0;
2133
2134         while ((this_opt = strsep(&options, ","))) {
2135                 if (!*this_opt)
2136                         continue;
2137                 if (!strncmp(this_opt, "vra", 3)) {
2138                         vra = 1;
2139                 }
2140         }
2141
2142         return 1;
2143 }
2144
2145 __setup("au1550_audio=", au1550_setup);
2146
2147 #endif /* MODULE */