c4a4cdc07ab9de2a1c33384d18f4f55e8b8f28a6
[linux-2.6.git] / sound / oss / au1550_ac97.c
1 /*
2  * au1550_ac97.c  --  Sound driver for Alchemy Au1550 MIPS Internet Edge
3  *                    Processor.
4  *
5  * Copyright 2004 Embedded Edge, LLC
6  *      dan@embeddededge.com
7  *
8  * Mostly copied from the au1000.c driver and some from the
9  * PowerMac dbdma driver.
10  * We assume the processor can do memory coherent DMA.
11  *
12  * Ported to 2.6 by Matt Porter <mporter@kernel.crashing.org>
13  *
14  *  This program is free software; you can redistribute  it and/or modify it
15  *  under  the terms of  the GNU General  Public License as published by the
16  *  Free Software Foundation;  either version 2 of the  License, or (at your
17  *  option) any later version.
18  *
19  *  THIS  SOFTWARE  IS PROVIDED   ``AS  IS'' AND   ANY  EXPRESS OR IMPLIED
20  *  WARRANTIES,   INCLUDING, BUT NOT  LIMITED  TO, THE IMPLIED WARRANTIES OF
21  *  MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.  IN
22  *  NO  EVENT  SHALL   THE AUTHOR  BE    LIABLE FOR ANY   DIRECT, INDIRECT,
23  *  INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
24  *  NOT LIMITED   TO, PROCUREMENT OF  SUBSTITUTE GOODS  OR SERVICES; LOSS OF
25  *  USE, DATA,  OR PROFITS; OR  BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
26  *  ANY THEORY OF LIABILITY, WHETHER IN  CONTRACT, STRICT LIABILITY, OR TORT
27  *  (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
28  *  THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
29  *
30  *  You should have received a copy of the  GNU General Public License along
31  *  with this program; if not, write  to the Free Software Foundation, Inc.,
32  *  675 Mass Ave, Cambridge, MA 02139, USA.
33  *
34  */
35
36 #undef DEBUG
37
38 #include <linux/module.h>
39 #include <linux/string.h>
40 #include <linux/ioport.h>
41 #include <linux/sched.h>
42 #include <linux/delay.h>
43 #include <linux/sound.h>
44 #include <linux/slab.h>
45 #include <linux/soundcard.h>
46 #include <linux/smp_lock.h>
47 #include <linux/init.h>
48 #include <linux/interrupt.h>
49 #include <linux/kernel.h>
50 #include <linux/poll.h>
51 #include <linux/bitops.h>
52 #include <linux/spinlock.h>
53 #include <linux/smp_lock.h>
54 #include <linux/ac97_codec.h>
55 #include <linux/mutex.h>
56
57 #include <asm/io.h>
58 #include <asm/uaccess.h>
59 #include <asm/hardirq.h>
60 #include <asm/mach-au1x00/au1xxx_psc.h>
61 #include <asm/mach-au1x00/au1xxx_dbdma.h>
62 #include <asm/mach-au1x00/au1xxx.h>
63
64 #undef OSS_DOCUMENTED_MIXER_SEMANTICS
65
66 /* misc stuff */
67 #define POLL_COUNT   0x50000
68 #define AC97_EXT_DACS (AC97_EXTID_SDAC | AC97_EXTID_CDAC | AC97_EXTID_LDAC)
69
70 /* The number of DBDMA ring descriptors to allocate.  No sense making
71  * this too large....if you can't keep up with a few you aren't likely
72  * to be able to with lots of them, either.
73  */
74 #define NUM_DBDMA_DESCRIPTORS 4
75
76 #define err(format, arg...) printk(KERN_ERR format "\n" , ## arg)
77
78 /* Boot options
79  * 0 = no VRA, 1 = use VRA if codec supports it
80  */
81 static int      vra = 1;
82 module_param(vra, bool, 0);
83 MODULE_PARM_DESC(vra, "if 1 use VRA if codec supports it");
84
85 static struct au1550_state {
86         /* soundcore stuff */
87         int             dev_audio;
88
89         struct ac97_codec *codec;
90         unsigned        codec_base_caps; /* AC'97 reg 00h, "Reset Register" */
91         unsigned        codec_ext_caps;  /* AC'97 reg 28h, "Extended Audio ID" */
92         int             no_vra;         /* do not use VRA */
93
94         spinlock_t      lock;
95         struct mutex open_mutex;
96         struct mutex sem;
97         fmode_t          open_mode;
98         wait_queue_head_t open_wait;
99
100         struct dmabuf {
101                 u32             dmanr;
102                 unsigned        sample_rate;
103                 unsigned        src_factor;
104                 unsigned        sample_size;
105                 int             num_channels;
106                 int             dma_bytes_per_sample;
107                 int             user_bytes_per_sample;
108                 int             cnt_factor;
109
110                 void            *rawbuf;
111                 unsigned        buforder;
112                 unsigned        numfrag;
113                 unsigned        fragshift;
114                 void            *nextIn;
115                 void            *nextOut;
116                 int             count;
117                 unsigned        total_bytes;
118                 unsigned        error;
119                 wait_queue_head_t wait;
120
121                 /* redundant, but makes calculations easier */
122                 unsigned        fragsize;
123                 unsigned        dma_fragsize;
124                 unsigned        dmasize;
125                 unsigned        dma_qcount;
126
127                 /* OSS stuff */
128                 unsigned        mapped:1;
129                 unsigned        ready:1;
130                 unsigned        stopped:1;
131                 unsigned        ossfragshift;
132                 int             ossmaxfrags;
133                 unsigned        subdivision;
134         } dma_dac, dma_adc;
135 } au1550_state;
136
137 static unsigned
138 ld2(unsigned int x)
139 {
140         unsigned        r = 0;
141
142         if (x >= 0x10000) {
143                 x >>= 16;
144                 r += 16;
145         }
146         if (x >= 0x100) {
147                 x >>= 8;
148                 r += 8;
149         }
150         if (x >= 0x10) {
151                 x >>= 4;
152                 r += 4;
153         }
154         if (x >= 4) {
155                 x >>= 2;
156                 r += 2;
157         }
158         if (x >= 2)
159                 r++;
160         return r;
161 }
162
163 static void
164 au1550_delay(int msec)
165 {
166         if (in_interrupt())
167                 return;
168
169         schedule_timeout_uninterruptible(msecs_to_jiffies(msec));
170 }
171
172 static u16
173 rdcodec(struct ac97_codec *codec, u8 addr)
174 {
175         struct au1550_state *s = (struct au1550_state *)codec->private_data;
176         unsigned long   flags;
177         u32             cmd, val;
178         u16             data;
179         int             i;
180
181         spin_lock_irqsave(&s->lock, flags);
182
183         for (i = 0; i < POLL_COUNT; i++) {
184                 val = au_readl(PSC_AC97STAT);
185                 au_sync();
186                 if (!(val & PSC_AC97STAT_CP))
187                         break;
188         }
189         if (i == POLL_COUNT)
190                 err("rdcodec: codec cmd pending expired!");
191
192         cmd = (u32)PSC_AC97CDC_INDX(addr);
193         cmd |= PSC_AC97CDC_RD;  /* read command */
194         au_writel(cmd, PSC_AC97CDC);
195         au_sync();
196
197         /* now wait for the data
198         */
199         for (i = 0; i < POLL_COUNT; i++) {
200                 val = au_readl(PSC_AC97STAT);
201                 au_sync();
202                 if (!(val & PSC_AC97STAT_CP))
203                         break;
204         }
205         if (i == POLL_COUNT) {
206                 err("rdcodec: read poll expired!");
207                 data = 0;
208                 goto out;
209         }
210
211         /* wait for command done?
212         */
213         for (i = 0; i < POLL_COUNT; i++) {
214                 val = au_readl(PSC_AC97EVNT);
215                 au_sync();
216                 if (val & PSC_AC97EVNT_CD)
217                         break;
218         }
219         if (i == POLL_COUNT) {
220                 err("rdcodec: read cmdwait expired!");
221                 data = 0;
222                 goto out;
223         }
224
225         data = au_readl(PSC_AC97CDC) & 0xffff;
226         au_sync();
227
228         /* Clear command done event.
229         */
230         au_writel(PSC_AC97EVNT_CD, PSC_AC97EVNT);
231         au_sync();
232
233  out:
234         spin_unlock_irqrestore(&s->lock, flags);
235
236         return data;
237 }
238
239
240 static void
241 wrcodec(struct ac97_codec *codec, u8 addr, u16 data)
242 {
243         struct au1550_state *s = (struct au1550_state *)codec->private_data;
244         unsigned long   flags;
245         u32             cmd, val;
246         int             i;
247
248         spin_lock_irqsave(&s->lock, flags);
249
250         for (i = 0; i < POLL_COUNT; i++) {
251                 val = au_readl(PSC_AC97STAT);
252                 au_sync();
253                 if (!(val & PSC_AC97STAT_CP))
254                         break;
255         }
256         if (i == POLL_COUNT)
257                 err("wrcodec: codec cmd pending expired!");
258
259         cmd = (u32)PSC_AC97CDC_INDX(addr);
260         cmd |= (u32)data;
261         au_writel(cmd, PSC_AC97CDC);
262         au_sync();
263
264         for (i = 0; i < POLL_COUNT; i++) {
265                 val = au_readl(PSC_AC97STAT);
266                 au_sync();
267                 if (!(val & PSC_AC97STAT_CP))
268                         break;
269         }
270         if (i == POLL_COUNT)
271                 err("wrcodec: codec cmd pending expired!");
272
273         for (i = 0; i < POLL_COUNT; i++) {
274                 val = au_readl(PSC_AC97EVNT);
275                 au_sync();
276                 if (val & PSC_AC97EVNT_CD)
277                         break;
278         }
279         if (i == POLL_COUNT)
280                 err("wrcodec: read cmdwait expired!");
281
282         /* Clear command done event.
283         */
284         au_writel(PSC_AC97EVNT_CD, PSC_AC97EVNT);
285         au_sync();
286
287         spin_unlock_irqrestore(&s->lock, flags);
288 }
289
290 static void
291 waitcodec(struct ac97_codec *codec)
292 {
293         u16     temp;
294         u32     val;
295         int     i;
296
297         /* codec_wait is used to wait for a ready state after
298          * an AC97C_RESET.
299          */
300         au1550_delay(10);
301
302         /* first poll the CODEC_READY tag bit
303         */
304         for (i = 0; i < POLL_COUNT; i++) {
305                 val = au_readl(PSC_AC97STAT);
306                 au_sync();
307                 if (val & PSC_AC97STAT_CR)
308                         break;
309         }
310         if (i == POLL_COUNT) {
311                 err("waitcodec: CODEC_READY poll expired!");
312                 return;
313         }
314
315         /* get AC'97 powerdown control/status register
316         */
317         temp = rdcodec(codec, AC97_POWER_CONTROL);
318
319         /* If anything is powered down, power'em up
320         */
321         if (temp & 0x7f00) {
322                 /* Power on
323                 */
324                 wrcodec(codec, AC97_POWER_CONTROL, 0);
325                 au1550_delay(100);
326
327                 /* Reread
328                 */
329                 temp = rdcodec(codec, AC97_POWER_CONTROL);
330         }
331
332         /* Check if Codec REF,ANL,DAC,ADC ready
333         */
334         if ((temp & 0x7f0f) != 0x000f)
335                 err("codec reg 26 status (0x%x) not ready!!", temp);
336 }
337
338 /* stop the ADC before calling */
339 static void
340 set_adc_rate(struct au1550_state *s, unsigned rate)
341 {
342         struct dmabuf  *adc = &s->dma_adc;
343         struct dmabuf  *dac = &s->dma_dac;
344         unsigned        adc_rate, dac_rate;
345         u16             ac97_extstat;
346
347         if (s->no_vra) {
348                 /* calc SRC factor
349                 */
350                 adc->src_factor = ((96000 / rate) + 1) >> 1;
351                 adc->sample_rate = 48000 / adc->src_factor;
352                 return;
353         }
354
355         adc->src_factor = 1;
356
357         ac97_extstat = rdcodec(s->codec, AC97_EXTENDED_STATUS);
358
359         rate = rate > 48000 ? 48000 : rate;
360
361         /* enable VRA
362         */
363         wrcodec(s->codec, AC97_EXTENDED_STATUS,
364                 ac97_extstat | AC97_EXTSTAT_VRA);
365
366         /* now write the sample rate
367         */
368         wrcodec(s->codec, AC97_PCM_LR_ADC_RATE, (u16) rate);
369
370         /* read it back for actual supported rate
371         */
372         adc_rate = rdcodec(s->codec, AC97_PCM_LR_ADC_RATE);
373
374         pr_debug("set_adc_rate: set to %d Hz\n", adc_rate);
375
376         /* some codec's don't allow unequal DAC and ADC rates, in which case
377          * writing one rate reg actually changes both.
378          */
379         dac_rate = rdcodec(s->codec, AC97_PCM_FRONT_DAC_RATE);
380         if (dac->num_channels > 2)
381                 wrcodec(s->codec, AC97_PCM_SURR_DAC_RATE, dac_rate);
382         if (dac->num_channels > 4)
383                 wrcodec(s->codec, AC97_PCM_LFE_DAC_RATE, dac_rate);
384
385         adc->sample_rate = adc_rate;
386         dac->sample_rate = dac_rate;
387 }
388
389 /* stop the DAC before calling */
390 static void
391 set_dac_rate(struct au1550_state *s, unsigned rate)
392 {
393         struct dmabuf  *dac = &s->dma_dac;
394         struct dmabuf  *adc = &s->dma_adc;
395         unsigned        adc_rate, dac_rate;
396         u16             ac97_extstat;
397
398         if (s->no_vra) {
399                 /* calc SRC factor
400                 */
401                 dac->src_factor = ((96000 / rate) + 1) >> 1;
402                 dac->sample_rate = 48000 / dac->src_factor;
403                 return;
404         }
405
406         dac->src_factor = 1;
407
408         ac97_extstat = rdcodec(s->codec, AC97_EXTENDED_STATUS);
409
410         rate = rate > 48000 ? 48000 : rate;
411
412         /* enable VRA
413         */
414         wrcodec(s->codec, AC97_EXTENDED_STATUS,
415                 ac97_extstat | AC97_EXTSTAT_VRA);
416
417         /* now write the sample rate
418         */
419         wrcodec(s->codec, AC97_PCM_FRONT_DAC_RATE, (u16) rate);
420
421         /* I don't support different sample rates for multichannel,
422          * so make these channels the same.
423          */
424         if (dac->num_channels > 2)
425                 wrcodec(s->codec, AC97_PCM_SURR_DAC_RATE, (u16) rate);
426         if (dac->num_channels > 4)
427                 wrcodec(s->codec, AC97_PCM_LFE_DAC_RATE, (u16) rate);
428         /* read it back for actual supported rate
429         */
430         dac_rate = rdcodec(s->codec, AC97_PCM_FRONT_DAC_RATE);
431
432         pr_debug("set_dac_rate: set to %d Hz\n", dac_rate);
433
434         /* some codec's don't allow unequal DAC and ADC rates, in which case
435          * writing one rate reg actually changes both.
436          */
437         adc_rate = rdcodec(s->codec, AC97_PCM_LR_ADC_RATE);
438
439         dac->sample_rate = dac_rate;
440         adc->sample_rate = adc_rate;
441 }
442
443 static void
444 stop_dac(struct au1550_state *s)
445 {
446         struct dmabuf  *db = &s->dma_dac;
447         u32             stat;
448         unsigned long   flags;
449
450         if (db->stopped)
451                 return;
452
453         spin_lock_irqsave(&s->lock, flags);
454
455         au_writel(PSC_AC97PCR_TP, PSC_AC97PCR);
456         au_sync();
457
458         /* Wait for Transmit Busy to show disabled.
459         */
460         do {
461                 stat = au_readl(PSC_AC97STAT);
462                 au_sync();
463         } while ((stat & PSC_AC97STAT_TB) != 0);
464
465         au1xxx_dbdma_reset(db->dmanr);
466
467         db->stopped = 1;
468
469         spin_unlock_irqrestore(&s->lock, flags);
470 }
471
472 static void
473 stop_adc(struct au1550_state *s)
474 {
475         struct dmabuf  *db = &s->dma_adc;
476         unsigned long   flags;
477         u32             stat;
478
479         if (db->stopped)
480                 return;
481
482         spin_lock_irqsave(&s->lock, flags);
483
484         au_writel(PSC_AC97PCR_RP, PSC_AC97PCR);
485         au_sync();
486
487         /* Wait for Receive Busy to show disabled.
488         */
489         do {
490                 stat = au_readl(PSC_AC97STAT);
491                 au_sync();
492         } while ((stat & PSC_AC97STAT_RB) != 0);
493
494         au1xxx_dbdma_reset(db->dmanr);
495
496         db->stopped = 1;
497
498         spin_unlock_irqrestore(&s->lock, flags);
499 }
500
501
502 static void
503 set_xmit_slots(int num_channels)
504 {
505         u32     ac97_config, stat;
506
507         ac97_config = au_readl(PSC_AC97CFG);
508         au_sync();
509         ac97_config &= ~(PSC_AC97CFG_TXSLOT_MASK | PSC_AC97CFG_DE_ENABLE);
510         au_writel(ac97_config, PSC_AC97CFG);
511         au_sync();
512
513         switch (num_channels) {
514         case 6:         /* stereo with surround and center/LFE,
515                          * slots 3,4,6,7,8,9
516                          */
517                 ac97_config |= PSC_AC97CFG_TXSLOT_ENA(6);
518                 ac97_config |= PSC_AC97CFG_TXSLOT_ENA(9);
519
520         case 4:         /* stereo with surround, slots 3,4,7,8 */
521                 ac97_config |= PSC_AC97CFG_TXSLOT_ENA(7);
522                 ac97_config |= PSC_AC97CFG_TXSLOT_ENA(8);
523
524         case 2:         /* stereo, slots 3,4 */
525         case 1:         /* mono */
526                 ac97_config |= PSC_AC97CFG_TXSLOT_ENA(3);
527                 ac97_config |= PSC_AC97CFG_TXSLOT_ENA(4);
528         }
529
530         au_writel(ac97_config, PSC_AC97CFG);
531         au_sync();
532
533         ac97_config |= PSC_AC97CFG_DE_ENABLE;
534         au_writel(ac97_config, PSC_AC97CFG);
535         au_sync();
536
537         /* Wait for Device ready.
538         */
539         do {
540                 stat = au_readl(PSC_AC97STAT);
541                 au_sync();
542         } while ((stat & PSC_AC97STAT_DR) == 0);
543 }
544
545 static void
546 set_recv_slots(int num_channels)
547 {
548         u32     ac97_config, stat;
549
550         ac97_config = au_readl(PSC_AC97CFG);
551         au_sync();
552         ac97_config &= ~(PSC_AC97CFG_RXSLOT_MASK | PSC_AC97CFG_DE_ENABLE);
553         au_writel(ac97_config, PSC_AC97CFG);
554         au_sync();
555
556         /* Always enable slots 3 and 4 (stereo). Slot 6 is
557          * optional Mic ADC, which we don't support yet.
558          */
559         ac97_config |= PSC_AC97CFG_RXSLOT_ENA(3);
560         ac97_config |= PSC_AC97CFG_RXSLOT_ENA(4);
561
562         au_writel(ac97_config, PSC_AC97CFG);
563         au_sync();
564
565         ac97_config |= PSC_AC97CFG_DE_ENABLE;
566         au_writel(ac97_config, PSC_AC97CFG);
567         au_sync();
568
569         /* Wait for Device ready.
570         */
571         do {
572                 stat = au_readl(PSC_AC97STAT);
573                 au_sync();
574         } while ((stat & PSC_AC97STAT_DR) == 0);
575 }
576
577 /* Hold spinlock for both start_dac() and start_adc() calls */
578 static void
579 start_dac(struct au1550_state *s)
580 {
581         struct dmabuf  *db = &s->dma_dac;
582
583         if (!db->stopped)
584                 return;
585
586         set_xmit_slots(db->num_channels);
587         au_writel(PSC_AC97PCR_TC, PSC_AC97PCR);
588         au_sync();
589         au_writel(PSC_AC97PCR_TS, PSC_AC97PCR);
590         au_sync();
591
592         au1xxx_dbdma_start(db->dmanr);
593
594         db->stopped = 0;
595 }
596
597 static void
598 start_adc(struct au1550_state *s)
599 {
600         struct dmabuf  *db = &s->dma_adc;
601         int     i;
602
603         if (!db->stopped)
604                 return;
605
606         /* Put two buffers on the ring to get things started.
607         */
608         for (i=0; i<2; i++) {
609                 au1xxx_dbdma_put_dest(db->dmanr, virt_to_phys(db->nextIn),
610                                 db->dma_fragsize, DDMA_FLAGS_IE);
611
612                 db->nextIn += db->dma_fragsize;
613                 if (db->nextIn >= db->rawbuf + db->dmasize)
614                         db->nextIn -= db->dmasize;
615         }
616
617         set_recv_slots(db->num_channels);
618         au1xxx_dbdma_start(db->dmanr);
619         au_writel(PSC_AC97PCR_RC, PSC_AC97PCR);
620         au_sync();
621         au_writel(PSC_AC97PCR_RS, PSC_AC97PCR);
622         au_sync();
623
624         db->stopped = 0;
625 }
626
627 static int
628 prog_dmabuf(struct au1550_state *s, struct dmabuf *db)
629 {
630         unsigned user_bytes_per_sec;
631         unsigned        bufs;
632         unsigned        rate = db->sample_rate;
633
634         if (!db->rawbuf) {
635                 db->ready = db->mapped = 0;
636                 db->buforder = 5;       /* 32 * PAGE_SIZE */
637                 db->rawbuf = kmalloc((PAGE_SIZE << db->buforder), GFP_KERNEL);
638                 if (!db->rawbuf)
639                         return -ENOMEM;
640         }
641
642         db->cnt_factor = 1;
643         if (db->sample_size == 8)
644                 db->cnt_factor *= 2;
645         if (db->num_channels == 1)
646                 db->cnt_factor *= 2;
647         db->cnt_factor *= db->src_factor;
648
649         db->count = 0;
650         db->dma_qcount = 0;
651         db->nextIn = db->nextOut = db->rawbuf;
652
653         db->user_bytes_per_sample = (db->sample_size>>3) * db->num_channels;
654         db->dma_bytes_per_sample = 2 * ((db->num_channels == 1) ?
655                                         2 : db->num_channels);
656
657         user_bytes_per_sec = rate * db->user_bytes_per_sample;
658         bufs = PAGE_SIZE << db->buforder;
659         if (db->ossfragshift) {
660                 if ((1000 << db->ossfragshift) < user_bytes_per_sec)
661                         db->fragshift = ld2(user_bytes_per_sec/1000);
662                 else
663                         db->fragshift = db->ossfragshift;
664         } else {
665                 db->fragshift = ld2(user_bytes_per_sec / 100 /
666                                     (db->subdivision ? db->subdivision : 1));
667                 if (db->fragshift < 3)
668                         db->fragshift = 3;
669         }
670
671         db->fragsize = 1 << db->fragshift;
672         db->dma_fragsize = db->fragsize * db->cnt_factor;
673         db->numfrag = bufs / db->dma_fragsize;
674
675         while (db->numfrag < 4 && db->fragshift > 3) {
676                 db->fragshift--;
677                 db->fragsize = 1 << db->fragshift;
678                 db->dma_fragsize = db->fragsize * db->cnt_factor;
679                 db->numfrag = bufs / db->dma_fragsize;
680         }
681
682         if (db->ossmaxfrags >= 4 && db->ossmaxfrags < db->numfrag)
683                 db->numfrag = db->ossmaxfrags;
684
685         db->dmasize = db->dma_fragsize * db->numfrag;
686         memset(db->rawbuf, 0, bufs);
687
688         pr_debug("prog_dmabuf: rate=%d, samplesize=%d, channels=%d\n",
689             rate, db->sample_size, db->num_channels);
690         pr_debug("prog_dmabuf: fragsize=%d, cnt_factor=%d, dma_fragsize=%d\n",
691             db->fragsize, db->cnt_factor, db->dma_fragsize);
692         pr_debug("prog_dmabuf: numfrag=%d, dmasize=%d\n", db->numfrag, db->dmasize);
693
694         db->ready = 1;
695         return 0;
696 }
697
698 static int
699 prog_dmabuf_adc(struct au1550_state *s)
700 {
701         stop_adc(s);
702         return prog_dmabuf(s, &s->dma_adc);
703
704 }
705
706 static int
707 prog_dmabuf_dac(struct au1550_state *s)
708 {
709         stop_dac(s);
710         return prog_dmabuf(s, &s->dma_dac);
711 }
712
713
714 static void dac_dma_interrupt(int irq, void *dev_id)
715 {
716         struct au1550_state *s = (struct au1550_state *) dev_id;
717         struct dmabuf  *db = &s->dma_dac;
718         u32     ac97c_stat;
719
720         spin_lock(&s->lock);
721
722         ac97c_stat = au_readl(PSC_AC97STAT);
723         if (ac97c_stat & (AC97C_XU | AC97C_XO | AC97C_TE))
724                 pr_debug("AC97C status = 0x%08x\n", ac97c_stat);
725         db->dma_qcount--;
726
727         if (db->count >= db->fragsize) {
728                 if (au1xxx_dbdma_put_source(db->dmanr,
729                                 virt_to_phys(db->nextOut), db->fragsize,
730                                 DDMA_FLAGS_IE) == 0) {
731                         err("qcount < 2 and no ring room!");
732                 }
733                 db->nextOut += db->fragsize;
734                 if (db->nextOut >= db->rawbuf + db->dmasize)
735                         db->nextOut -= db->dmasize;
736                 db->count -= db->fragsize;
737                 db->total_bytes += db->dma_fragsize;
738                 db->dma_qcount++;
739         }
740
741         /* wake up anybody listening */
742         if (waitqueue_active(&db->wait))
743                 wake_up(&db->wait);
744
745         spin_unlock(&s->lock);
746 }
747
748
749 static void adc_dma_interrupt(int irq, void *dev_id)
750 {
751         struct  au1550_state *s = (struct au1550_state *)dev_id;
752         struct  dmabuf  *dp = &s->dma_adc;
753         u32     obytes;
754         char    *obuf;
755
756         spin_lock(&s->lock);
757
758         /* Pull the buffer from the dma queue.
759         */
760         au1xxx_dbdma_get_dest(dp->dmanr, (void *)(&obuf), &obytes);
761
762         if ((dp->count + obytes) > dp->dmasize) {
763                 /* Overrun. Stop ADC and log the error
764                 */
765                 spin_unlock(&s->lock);
766                 stop_adc(s);
767                 dp->error++;
768                 err("adc overrun");
769                 return;
770         }
771
772         /* Put a new empty buffer on the destination DMA.
773         */
774         au1xxx_dbdma_put_dest(dp->dmanr, virt_to_phys(dp->nextIn),
775                               dp->dma_fragsize, DDMA_FLAGS_IE);
776
777         dp->nextIn += dp->dma_fragsize;
778         if (dp->nextIn >= dp->rawbuf + dp->dmasize)
779                 dp->nextIn -= dp->dmasize;
780
781         dp->count += obytes;
782         dp->total_bytes += obytes;
783
784         /* wake up anybody listening
785         */
786         if (waitqueue_active(&dp->wait))
787                 wake_up(&dp->wait);
788
789         spin_unlock(&s->lock);
790 }
791
792 static loff_t
793 au1550_llseek(struct file *file, loff_t offset, int origin)
794 {
795         return -ESPIPE;
796 }
797
798
799 static int
800 au1550_open_mixdev(struct inode *inode, struct file *file)
801 {
802         lock_kernel();
803         file->private_data = &au1550_state;
804         unlock_kernel();
805         return 0;
806 }
807
808 static int
809 au1550_release_mixdev(struct inode *inode, struct file *file)
810 {
811         return 0;
812 }
813
814 static int
815 mixdev_ioctl(struct ac97_codec *codec, unsigned int cmd,
816                         unsigned long arg)
817 {
818         return codec->mixer_ioctl(codec, cmd, arg);
819 }
820
821 static long
822 au1550_ioctl_mixdev(struct file *file, unsigned int cmd, unsigned long arg)
823 {
824         struct au1550_state *s = (struct au1550_state *)file->private_data;
825         struct ac97_codec *codec = s->codec;
826         int ret;
827
828         lock_kernel();
829         ret = mixdev_ioctl(codec, cmd, arg);
830         unlock_kernel();
831
832         return ret;
833 }
834
835 static /*const */ struct file_operations au1550_mixer_fops = {
836         .owner          = THIS_MODULE,
837         .llseek         = au1550_llseek,
838         .unlocked_ioctl = au1550_ioctl_mixdev,
839         .open           = au1550_open_mixdev,
840         .release        = au1550_release_mixdev,
841 };
842
843 static int
844 drain_dac(struct au1550_state *s, int nonblock)
845 {
846         unsigned long   flags;
847         int             count, tmo;
848
849         if (s->dma_dac.mapped || !s->dma_dac.ready || s->dma_dac.stopped)
850                 return 0;
851
852         for (;;) {
853                 spin_lock_irqsave(&s->lock, flags);
854                 count = s->dma_dac.count;
855                 spin_unlock_irqrestore(&s->lock, flags);
856                 if (count <= s->dma_dac.fragsize)
857                         break;
858                 if (signal_pending(current))
859                         break;
860                 if (nonblock)
861                         return -EBUSY;
862                 tmo = 1000 * count / (s->no_vra ?
863                                       48000 : s->dma_dac.sample_rate);
864                 tmo /= s->dma_dac.dma_bytes_per_sample;
865                 au1550_delay(tmo);
866         }
867         if (signal_pending(current))
868                 return -ERESTARTSYS;
869         return 0;
870 }
871
872 static inline u8 S16_TO_U8(s16 ch)
873 {
874         return (u8) (ch >> 8) + 0x80;
875 }
876 static inline s16 U8_TO_S16(u8 ch)
877 {
878         return (s16) (ch - 0x80) << 8;
879 }
880
881 /*
882  * Translates user samples to dma buffer suitable for AC'97 DAC data:
883  *     If mono, copy left channel to right channel in dma buffer.
884  *     If 8 bit samples, cvt to 16-bit before writing to dma buffer.
885  *     If interpolating (no VRA), duplicate every audio frame src_factor times.
886  */
887 static int
888 translate_from_user(struct dmabuf *db, char* dmabuf, char* userbuf,
889                                                                int dmacount)
890 {
891         int             sample, i;
892         int             interp_bytes_per_sample;
893         int             num_samples;
894         int             mono = (db->num_channels == 1);
895         char            usersample[12];
896         s16             ch, dmasample[6];
897
898         if (db->sample_size == 16 && !mono && db->src_factor == 1) {
899                 /* no translation necessary, just copy
900                 */
901                 if (copy_from_user(dmabuf, userbuf, dmacount))
902                         return -EFAULT;
903                 return dmacount;
904         }
905
906         interp_bytes_per_sample = db->dma_bytes_per_sample * db->src_factor;
907         num_samples = dmacount / interp_bytes_per_sample;
908
909         for (sample = 0; sample < num_samples; sample++) {
910                 if (copy_from_user(usersample, userbuf,
911                                    db->user_bytes_per_sample)) {
912                         return -EFAULT;
913                 }
914
915                 for (i = 0; i < db->num_channels; i++) {
916                         if (db->sample_size == 8)
917                                 ch = U8_TO_S16(usersample[i]);
918                         else
919                                 ch = *((s16 *) (&usersample[i * 2]));
920                         dmasample[i] = ch;
921                         if (mono)
922                                 dmasample[i + 1] = ch;  /* right channel */
923                 }
924
925                 /* duplicate every audio frame src_factor times
926                 */
927                 for (i = 0; i < db->src_factor; i++)
928                         memcpy(dmabuf, dmasample, db->dma_bytes_per_sample);
929
930                 userbuf += db->user_bytes_per_sample;
931                 dmabuf += interp_bytes_per_sample;
932         }
933
934         return num_samples * interp_bytes_per_sample;
935 }
936
937 /*
938  * Translates AC'97 ADC samples to user buffer:
939  *     If mono, send only left channel to user buffer.
940  *     If 8 bit samples, cvt from 16 to 8 bit before writing to user buffer.
941  *     If decimating (no VRA), skip over src_factor audio frames.
942  */
943 static int
944 translate_to_user(struct dmabuf *db, char* userbuf, char* dmabuf,
945                                                              int dmacount)
946 {
947         int             sample, i;
948         int             interp_bytes_per_sample;
949         int             num_samples;
950         int             mono = (db->num_channels == 1);
951         char            usersample[12];
952
953         if (db->sample_size == 16 && !mono && db->src_factor == 1) {
954                 /* no translation necessary, just copy
955                 */
956                 if (copy_to_user(userbuf, dmabuf, dmacount))
957                         return -EFAULT;
958                 return dmacount;
959         }
960
961         interp_bytes_per_sample = db->dma_bytes_per_sample * db->src_factor;
962         num_samples = dmacount / interp_bytes_per_sample;
963
964         for (sample = 0; sample < num_samples; sample++) {
965                 for (i = 0; i < db->num_channels; i++) {
966                         if (db->sample_size == 8)
967                                 usersample[i] =
968                                         S16_TO_U8(*((s16 *) (&dmabuf[i * 2])));
969                         else
970                                 *((s16 *) (&usersample[i * 2])) =
971                                         *((s16 *) (&dmabuf[i * 2]));
972                 }
973
974                 if (copy_to_user(userbuf, usersample,
975                                  db->user_bytes_per_sample)) {
976                         return -EFAULT;
977                 }
978
979                 userbuf += db->user_bytes_per_sample;
980                 dmabuf += interp_bytes_per_sample;
981         }
982
983         return num_samples * interp_bytes_per_sample;
984 }
985
986 /*
987  * Copy audio data to/from user buffer from/to dma buffer, taking care
988  * that we wrap when reading/writing the dma buffer. Returns actual byte
989  * count written to or read from the dma buffer.
990  */
991 static int
992 copy_dmabuf_user(struct dmabuf *db, char* userbuf, int count, int to_user)
993 {
994         char           *bufptr = to_user ? db->nextOut : db->nextIn;
995         char           *bufend = db->rawbuf + db->dmasize;
996         int             cnt, ret;
997
998         if (bufptr + count > bufend) {
999                 int             partial = (int) (bufend - bufptr);
1000                 if (to_user) {
1001                         if ((cnt = translate_to_user(db, userbuf,
1002                                                      bufptr, partial)) < 0)
1003                                 return cnt;
1004                         ret = cnt;
1005                         if ((cnt = translate_to_user(db, userbuf + partial,
1006                                                      db->rawbuf,
1007                                                      count - partial)) < 0)
1008                                 return cnt;
1009                         ret += cnt;
1010                 } else {
1011                         if ((cnt = translate_from_user(db, bufptr, userbuf,
1012                                                        partial)) < 0)
1013                                 return cnt;
1014                         ret = cnt;
1015                         if ((cnt = translate_from_user(db, db->rawbuf,
1016                                                        userbuf + partial,
1017                                                        count - partial)) < 0)
1018                                 return cnt;
1019                         ret += cnt;
1020                 }
1021         } else {
1022                 if (to_user)
1023                         ret = translate_to_user(db, userbuf, bufptr, count);
1024                 else
1025                         ret = translate_from_user(db, bufptr, userbuf, count);
1026         }
1027
1028         return ret;
1029 }
1030
1031
1032 static ssize_t
1033 au1550_read(struct file *file, char *buffer, size_t count, loff_t *ppos)
1034 {
1035         struct au1550_state *s = (struct au1550_state *)file->private_data;
1036         struct dmabuf  *db = &s->dma_adc;
1037         DECLARE_WAITQUEUE(wait, current);
1038         ssize_t         ret;
1039         unsigned long   flags;
1040         int             cnt, usercnt, avail;
1041
1042         if (db->mapped)
1043                 return -ENXIO;
1044         if (!access_ok(VERIFY_WRITE, buffer, count))
1045                 return -EFAULT;
1046         ret = 0;
1047
1048         count *= db->cnt_factor;
1049
1050         mutex_lock(&s->sem);
1051         add_wait_queue(&db->wait, &wait);
1052
1053         while (count > 0) {
1054                 /* wait for samples in ADC dma buffer
1055                 */
1056                 do {
1057                         spin_lock_irqsave(&s->lock, flags);
1058                         if (db->stopped)
1059                                 start_adc(s);
1060                         avail = db->count;
1061                         if (avail <= 0)
1062                                 __set_current_state(TASK_INTERRUPTIBLE);
1063                         spin_unlock_irqrestore(&s->lock, flags);
1064                         if (avail <= 0) {
1065                                 if (file->f_flags & O_NONBLOCK) {
1066                                         if (!ret)
1067                                                 ret = -EAGAIN;
1068                                         goto out;
1069                                 }
1070                                 mutex_unlock(&s->sem);
1071                                 schedule();
1072                                 if (signal_pending(current)) {
1073                                         if (!ret)
1074                                                 ret = -ERESTARTSYS;
1075                                         goto out2;
1076                                 }
1077                                 mutex_lock(&s->sem);
1078                         }
1079                 } while (avail <= 0);
1080
1081                 /* copy from nextOut to user
1082                 */
1083                 if ((cnt = copy_dmabuf_user(db, buffer,
1084                                             count > avail ?
1085                                             avail : count, 1)) < 0) {
1086                         if (!ret)
1087                                 ret = -EFAULT;
1088                         goto out;
1089                 }
1090
1091                 spin_lock_irqsave(&s->lock, flags);
1092                 db->count -= cnt;
1093                 db->nextOut += cnt;
1094                 if (db->nextOut >= db->rawbuf + db->dmasize)
1095                         db->nextOut -= db->dmasize;
1096                 spin_unlock_irqrestore(&s->lock, flags);
1097
1098                 count -= cnt;
1099                 usercnt = cnt / db->cnt_factor;
1100                 buffer += usercnt;
1101                 ret += usercnt;
1102         }                       /* while (count > 0) */
1103
1104 out:
1105         mutex_unlock(&s->sem);
1106 out2:
1107         remove_wait_queue(&db->wait, &wait);
1108         set_current_state(TASK_RUNNING);
1109         return ret;
1110 }
1111
1112 static ssize_t
1113 au1550_write(struct file *file, const char *buffer, size_t count, loff_t * ppos)
1114 {
1115         struct au1550_state *s = (struct au1550_state *)file->private_data;
1116         struct dmabuf  *db = &s->dma_dac;
1117         DECLARE_WAITQUEUE(wait, current);
1118         ssize_t         ret = 0;
1119         unsigned long   flags;
1120         int             cnt, usercnt, avail;
1121
1122         pr_debug("write: count=%d\n", count);
1123
1124         if (db->mapped)
1125                 return -ENXIO;
1126         if (!access_ok(VERIFY_READ, buffer, count))
1127                 return -EFAULT;
1128
1129         count *= db->cnt_factor;
1130
1131         mutex_lock(&s->sem);
1132         add_wait_queue(&db->wait, &wait);
1133
1134         while (count > 0) {
1135                 /* wait for space in playback buffer
1136                 */
1137                 do {
1138                         spin_lock_irqsave(&s->lock, flags);
1139                         avail = (int) db->dmasize - db->count;
1140                         if (avail <= 0)
1141                                 __set_current_state(TASK_INTERRUPTIBLE);
1142                         spin_unlock_irqrestore(&s->lock, flags);
1143                         if (avail <= 0) {
1144                                 if (file->f_flags & O_NONBLOCK) {
1145                                         if (!ret)
1146                                                 ret = -EAGAIN;
1147                                         goto out;
1148                                 }
1149                                 mutex_unlock(&s->sem);
1150                                 schedule();
1151                                 if (signal_pending(current)) {
1152                                         if (!ret)
1153                                                 ret = -ERESTARTSYS;
1154                                         goto out2;
1155                                 }
1156                                 mutex_lock(&s->sem);
1157                         }
1158                 } while (avail <= 0);
1159
1160                 /* copy from user to nextIn
1161                 */
1162                 if ((cnt = copy_dmabuf_user(db, (char *) buffer,
1163                                             count > avail ?
1164                                             avail : count, 0)) < 0) {
1165                         if (!ret)
1166                                 ret = -EFAULT;
1167                         goto out;
1168                 }
1169
1170                 spin_lock_irqsave(&s->lock, flags);
1171                 db->count += cnt;
1172                 db->nextIn += cnt;
1173                 if (db->nextIn >= db->rawbuf + db->dmasize)
1174                         db->nextIn -= db->dmasize;
1175
1176                 /* If the data is available, we want to keep two buffers
1177                  * on the dma queue.  If the queue count reaches zero,
1178                  * we know the dma has stopped.
1179                  */
1180                 while ((db->dma_qcount < 2) && (db->count >= db->fragsize)) {
1181                         if (au1xxx_dbdma_put_source(db->dmanr,
1182                                 virt_to_phys(db->nextOut), db->fragsize,
1183                                 DDMA_FLAGS_IE) == 0) {
1184                                 err("qcount < 2 and no ring room!");
1185                         }
1186                         db->nextOut += db->fragsize;
1187                         if (db->nextOut >= db->rawbuf + db->dmasize)
1188                                 db->nextOut -= db->dmasize;
1189                         db->total_bytes += db->dma_fragsize;
1190                         if (db->dma_qcount == 0)
1191                                 start_dac(s);
1192                         db->dma_qcount++;
1193                 }
1194                 spin_unlock_irqrestore(&s->lock, flags);
1195
1196                 count -= cnt;
1197                 usercnt = cnt / db->cnt_factor;
1198                 buffer += usercnt;
1199                 ret += usercnt;
1200         }                       /* while (count > 0) */
1201
1202 out:
1203         mutex_unlock(&s->sem);
1204 out2:
1205         remove_wait_queue(&db->wait, &wait);
1206         set_current_state(TASK_RUNNING);
1207         return ret;
1208 }
1209
1210
1211 /* No kernel lock - we have our own spinlock */
1212 static unsigned int
1213 au1550_poll(struct file *file, struct poll_table_struct *wait)
1214 {
1215         struct au1550_state *s = (struct au1550_state *)file->private_data;
1216         unsigned long   flags;
1217         unsigned int    mask = 0;
1218
1219         if (file->f_mode & FMODE_WRITE) {
1220                 if (!s->dma_dac.ready)
1221                         return 0;
1222                 poll_wait(file, &s->dma_dac.wait, wait);
1223         }
1224         if (file->f_mode & FMODE_READ) {
1225                 if (!s->dma_adc.ready)
1226                         return 0;
1227                 poll_wait(file, &s->dma_adc.wait, wait);
1228         }
1229
1230         spin_lock_irqsave(&s->lock, flags);
1231
1232         if (file->f_mode & FMODE_READ) {
1233                 if (s->dma_adc.count >= (signed)s->dma_adc.dma_fragsize)
1234                         mask |= POLLIN | POLLRDNORM;
1235         }
1236         if (file->f_mode & FMODE_WRITE) {
1237                 if (s->dma_dac.mapped) {
1238                         if (s->dma_dac.count >=
1239                             (signed)s->dma_dac.dma_fragsize)
1240                                 mask |= POLLOUT | POLLWRNORM;
1241                 } else {
1242                         if ((signed) s->dma_dac.dmasize >=
1243                             s->dma_dac.count + (signed)s->dma_dac.dma_fragsize)
1244                                 mask |= POLLOUT | POLLWRNORM;
1245                 }
1246         }
1247         spin_unlock_irqrestore(&s->lock, flags);
1248         return mask;
1249 }
1250
1251 static int
1252 au1550_mmap(struct file *file, struct vm_area_struct *vma)
1253 {
1254         struct au1550_state *s = (struct au1550_state *)file->private_data;
1255         struct dmabuf  *db;
1256         unsigned long   size;
1257         int ret = 0;
1258
1259         lock_kernel();
1260         mutex_lock(&s->sem);
1261         if (vma->vm_flags & VM_WRITE)
1262                 db = &s->dma_dac;
1263         else if (vma->vm_flags & VM_READ)
1264                 db = &s->dma_adc;
1265         else {
1266                 ret = -EINVAL;
1267                 goto out;
1268         }
1269         if (vma->vm_pgoff != 0) {
1270                 ret = -EINVAL;
1271                 goto out;
1272         }
1273         size = vma->vm_end - vma->vm_start;
1274         if (size > (PAGE_SIZE << db->buforder)) {
1275                 ret = -EINVAL;
1276                 goto out;
1277         }
1278         if (remap_pfn_range(vma, vma->vm_start, page_to_pfn(virt_to_page(db->rawbuf)),
1279                              size, vma->vm_page_prot)) {
1280                 ret = -EAGAIN;
1281                 goto out;
1282         }
1283         vma->vm_flags &= ~VM_IO;
1284         db->mapped = 1;
1285 out:
1286         mutex_unlock(&s->sem);
1287         unlock_kernel();
1288         return ret;
1289 }
1290
1291 #ifdef DEBUG
1292 static struct ioctl_str_t {
1293         unsigned int    cmd;
1294         const char     *str;
1295 } ioctl_str[] = {
1296         {SNDCTL_DSP_RESET, "SNDCTL_DSP_RESET"},
1297         {SNDCTL_DSP_SYNC, "SNDCTL_DSP_SYNC"},
1298         {SNDCTL_DSP_SPEED, "SNDCTL_DSP_SPEED"},
1299         {SNDCTL_DSP_STEREO, "SNDCTL_DSP_STEREO"},
1300         {SNDCTL_DSP_GETBLKSIZE, "SNDCTL_DSP_GETBLKSIZE"},
1301         {SNDCTL_DSP_SAMPLESIZE, "SNDCTL_DSP_SAMPLESIZE"},
1302         {SNDCTL_DSP_CHANNELS, "SNDCTL_DSP_CHANNELS"},
1303         {SOUND_PCM_WRITE_CHANNELS, "SOUND_PCM_WRITE_CHANNELS"},
1304         {SOUND_PCM_WRITE_FILTER, "SOUND_PCM_WRITE_FILTER"},
1305         {SNDCTL_DSP_POST, "SNDCTL_DSP_POST"},
1306         {SNDCTL_DSP_SUBDIVIDE, "SNDCTL_DSP_SUBDIVIDE"},
1307         {SNDCTL_DSP_SETFRAGMENT, "SNDCTL_DSP_SETFRAGMENT"},
1308         {SNDCTL_DSP_GETFMTS, "SNDCTL_DSP_GETFMTS"},
1309         {SNDCTL_DSP_SETFMT, "SNDCTL_DSP_SETFMT"},
1310         {SNDCTL_DSP_GETOSPACE, "SNDCTL_DSP_GETOSPACE"},
1311         {SNDCTL_DSP_GETISPACE, "SNDCTL_DSP_GETISPACE"},
1312         {SNDCTL_DSP_NONBLOCK, "SNDCTL_DSP_NONBLOCK"},
1313         {SNDCTL_DSP_GETCAPS, "SNDCTL_DSP_GETCAPS"},
1314         {SNDCTL_DSP_GETTRIGGER, "SNDCTL_DSP_GETTRIGGER"},
1315         {SNDCTL_DSP_SETTRIGGER, "SNDCTL_DSP_SETTRIGGER"},
1316         {SNDCTL_DSP_GETIPTR, "SNDCTL_DSP_GETIPTR"},
1317         {SNDCTL_DSP_GETOPTR, "SNDCTL_DSP_GETOPTR"},
1318         {SNDCTL_DSP_MAPINBUF, "SNDCTL_DSP_MAPINBUF"},
1319         {SNDCTL_DSP_MAPOUTBUF, "SNDCTL_DSP_MAPOUTBUF"},
1320         {SNDCTL_DSP_SETSYNCRO, "SNDCTL_DSP_SETSYNCRO"},
1321         {SNDCTL_DSP_SETDUPLEX, "SNDCTL_DSP_SETDUPLEX"},
1322         {SNDCTL_DSP_GETODELAY, "SNDCTL_DSP_GETODELAY"},
1323         {SNDCTL_DSP_GETCHANNELMASK, "SNDCTL_DSP_GETCHANNELMASK"},
1324         {SNDCTL_DSP_BIND_CHANNEL, "SNDCTL_DSP_BIND_CHANNEL"},
1325         {OSS_GETVERSION, "OSS_GETVERSION"},
1326         {SOUND_PCM_READ_RATE, "SOUND_PCM_READ_RATE"},
1327         {SOUND_PCM_READ_CHANNELS, "SOUND_PCM_READ_CHANNELS"},
1328         {SOUND_PCM_READ_BITS, "SOUND_PCM_READ_BITS"},
1329         {SOUND_PCM_READ_FILTER, "SOUND_PCM_READ_FILTER"}
1330 };
1331 #endif
1332
1333 static int
1334 dma_count_done(struct dmabuf *db)
1335 {
1336         if (db->stopped)
1337                 return 0;
1338
1339         return db->dma_fragsize - au1xxx_get_dma_residue(db->dmanr);
1340 }
1341
1342
1343 static int
1344 au1550_ioctl(struct file *file, unsigned int cmd, unsigned long arg)
1345 {
1346         struct au1550_state *s = (struct au1550_state *)file->private_data;
1347         unsigned long   flags;
1348         audio_buf_info  abinfo;
1349         count_info      cinfo;
1350         int             count;
1351         int             val, mapped, ret, diff;
1352
1353         mapped = ((file->f_mode & FMODE_WRITE) && s->dma_dac.mapped) ||
1354                 ((file->f_mode & FMODE_READ) && s->dma_adc.mapped);
1355
1356 #ifdef DEBUG
1357         for (count = 0; count < ARRAY_SIZE(ioctl_str); count++) {
1358                 if (ioctl_str[count].cmd == cmd)
1359                         break;
1360         }
1361         if (count < ARRAY_SIZE(ioctl_str))
1362                 pr_debug("ioctl %s, arg=0x%lxn", ioctl_str[count].str, arg);
1363         else
1364                 pr_debug("ioctl 0x%x unknown, arg=0x%lx\n", cmd, arg);
1365 #endif
1366
1367         switch (cmd) {
1368         case OSS_GETVERSION:
1369                 return put_user(SOUND_VERSION, (int *) arg);
1370
1371         case SNDCTL_DSP_SYNC:
1372                 if (file->f_mode & FMODE_WRITE)
1373                         return drain_dac(s, file->f_flags & O_NONBLOCK);
1374                 return 0;
1375
1376         case SNDCTL_DSP_SETDUPLEX:
1377                 return 0;
1378
1379         case SNDCTL_DSP_GETCAPS:
1380                 return put_user(DSP_CAP_DUPLEX | DSP_CAP_REALTIME |
1381                                 DSP_CAP_TRIGGER | DSP_CAP_MMAP, (int *)arg);
1382
1383         case SNDCTL_DSP_RESET:
1384                 if (file->f_mode & FMODE_WRITE) {
1385                         stop_dac(s);
1386                         synchronize_irq();
1387                         s->dma_dac.count = s->dma_dac.total_bytes = 0;
1388                         s->dma_dac.nextIn = s->dma_dac.nextOut =
1389                                 s->dma_dac.rawbuf;
1390                 }
1391                 if (file->f_mode & FMODE_READ) {
1392                         stop_adc(s);
1393                         synchronize_irq();
1394                         s->dma_adc.count = s->dma_adc.total_bytes = 0;
1395                         s->dma_adc.nextIn = s->dma_adc.nextOut =
1396                                 s->dma_adc.rawbuf;
1397                 }
1398                 return 0;
1399
1400         case SNDCTL_DSP_SPEED:
1401                 if (get_user(val, (int *) arg))
1402                         return -EFAULT;
1403                 if (val >= 0) {
1404                         if (file->f_mode & FMODE_READ) {
1405                                 stop_adc(s);
1406                                 set_adc_rate(s, val);
1407                         }
1408                         if (file->f_mode & FMODE_WRITE) {
1409                                 stop_dac(s);
1410                                 set_dac_rate(s, val);
1411                         }
1412                         if (s->open_mode & FMODE_READ)
1413                                 if ((ret = prog_dmabuf_adc(s)))
1414                                         return ret;
1415                         if (s->open_mode & FMODE_WRITE)
1416                                 if ((ret = prog_dmabuf_dac(s)))
1417                                         return ret;
1418                 }
1419                 return put_user((file->f_mode & FMODE_READ) ?
1420                                 s->dma_adc.sample_rate :
1421                                 s->dma_dac.sample_rate,
1422                                 (int *)arg);
1423
1424         case SNDCTL_DSP_STEREO:
1425                 if (get_user(val, (int *) arg))
1426                         return -EFAULT;
1427                 if (file->f_mode & FMODE_READ) {
1428                         stop_adc(s);
1429                         s->dma_adc.num_channels = val ? 2 : 1;
1430                         if ((ret = prog_dmabuf_adc(s)))
1431                                 return ret;
1432                 }
1433                 if (file->f_mode & FMODE_WRITE) {
1434                         stop_dac(s);
1435                         s->dma_dac.num_channels = val ? 2 : 1;
1436                         if (s->codec_ext_caps & AC97_EXT_DACS) {
1437                                 /* disable surround and center/lfe in AC'97
1438                                 */
1439                                 u16 ext_stat = rdcodec(s->codec,
1440                                                        AC97_EXTENDED_STATUS);
1441                                 wrcodec(s->codec, AC97_EXTENDED_STATUS,
1442                                         ext_stat | (AC97_EXTSTAT_PRI |
1443                                                     AC97_EXTSTAT_PRJ |
1444                                                     AC97_EXTSTAT_PRK));
1445                         }
1446                         if ((ret = prog_dmabuf_dac(s)))
1447                                 return ret;
1448                 }
1449                 return 0;
1450
1451         case SNDCTL_DSP_CHANNELS:
1452                 if (get_user(val, (int *) arg))
1453                         return -EFAULT;
1454                 if (val != 0) {
1455                         if (file->f_mode & FMODE_READ) {
1456                                 if (val < 0 || val > 2)
1457                                         return -EINVAL;
1458                                 stop_adc(s);
1459                                 s->dma_adc.num_channels = val;
1460                                 if ((ret = prog_dmabuf_adc(s)))
1461                                         return ret;
1462                         }
1463                         if (file->f_mode & FMODE_WRITE) {
1464                                 switch (val) {
1465                                 case 1:
1466                                 case 2:
1467                                         break;
1468                                 case 3:
1469                                 case 5:
1470                                         return -EINVAL;
1471                                 case 4:
1472                                         if (!(s->codec_ext_caps &
1473                                               AC97_EXTID_SDAC))
1474                                                 return -EINVAL;
1475                                         break;
1476                                 case 6:
1477                                         if ((s->codec_ext_caps &
1478                                              AC97_EXT_DACS) != AC97_EXT_DACS)
1479                                                 return -EINVAL;
1480                                         break;
1481                                 default:
1482                                         return -EINVAL;
1483                                 }
1484
1485                                 stop_dac(s);
1486                                 if (val <= 2 &&
1487                                     (s->codec_ext_caps & AC97_EXT_DACS)) {
1488                                         /* disable surround and center/lfe
1489                                          * channels in AC'97
1490                                          */
1491                                         u16             ext_stat =
1492                                                 rdcodec(s->codec,
1493                                                         AC97_EXTENDED_STATUS);
1494                                         wrcodec(s->codec,
1495                                                 AC97_EXTENDED_STATUS,
1496                                                 ext_stat | (AC97_EXTSTAT_PRI |
1497                                                             AC97_EXTSTAT_PRJ |
1498                                                             AC97_EXTSTAT_PRK));
1499                                 } else if (val >= 4) {
1500                                         /* enable surround, center/lfe
1501                                          * channels in AC'97
1502                                          */
1503                                         u16             ext_stat =
1504                                                 rdcodec(s->codec,
1505                                                         AC97_EXTENDED_STATUS);
1506                                         ext_stat &= ~AC97_EXTSTAT_PRJ;
1507                                         if (val == 6)
1508                                                 ext_stat &=
1509                                                         ~(AC97_EXTSTAT_PRI |
1510                                                           AC97_EXTSTAT_PRK);
1511                                         wrcodec(s->codec,
1512                                                 AC97_EXTENDED_STATUS,
1513                                                 ext_stat);
1514                                 }
1515
1516                                 s->dma_dac.num_channels = val;
1517                                 if ((ret = prog_dmabuf_dac(s)))
1518                                         return ret;
1519                         }
1520                 }
1521                 return put_user(val, (int *) arg);
1522
1523         case SNDCTL_DSP_GETFMTS:        /* Returns a mask */
1524                 return put_user(AFMT_S16_LE | AFMT_U8, (int *) arg);
1525
1526         case SNDCTL_DSP_SETFMT: /* Selects ONE fmt */
1527                 if (get_user(val, (int *) arg))
1528                         return -EFAULT;
1529                 if (val != AFMT_QUERY) {
1530                         if (file->f_mode & FMODE_READ) {
1531                                 stop_adc(s);
1532                                 if (val == AFMT_S16_LE)
1533                                         s->dma_adc.sample_size = 16;
1534                                 else {
1535                                         val = AFMT_U8;
1536                                         s->dma_adc.sample_size = 8;
1537                                 }
1538                                 if ((ret = prog_dmabuf_adc(s)))
1539                                         return ret;
1540                         }
1541                         if (file->f_mode & FMODE_WRITE) {
1542                                 stop_dac(s);
1543                                 if (val == AFMT_S16_LE)
1544                                         s->dma_dac.sample_size = 16;
1545                                 else {
1546                                         val = AFMT_U8;
1547                                         s->dma_dac.sample_size = 8;
1548                                 }
1549                                 if ((ret = prog_dmabuf_dac(s)))
1550                                         return ret;
1551                         }
1552                 } else {
1553                         if (file->f_mode & FMODE_READ)
1554                                 val = (s->dma_adc.sample_size == 16) ?
1555                                         AFMT_S16_LE : AFMT_U8;
1556                         else
1557                                 val = (s->dma_dac.sample_size == 16) ?
1558                                         AFMT_S16_LE : AFMT_U8;
1559                 }
1560                 return put_user(val, (int *) arg);
1561
1562         case SNDCTL_DSP_POST:
1563                 return 0;
1564
1565         case SNDCTL_DSP_GETTRIGGER:
1566                 val = 0;
1567                 spin_lock_irqsave(&s->lock, flags);
1568                 if (file->f_mode & FMODE_READ && !s->dma_adc.stopped)
1569                         val |= PCM_ENABLE_INPUT;
1570                 if (file->f_mode & FMODE_WRITE && !s->dma_dac.stopped)
1571                         val |= PCM_ENABLE_OUTPUT;
1572                 spin_unlock_irqrestore(&s->lock, flags);
1573                 return put_user(val, (int *) arg);
1574
1575         case SNDCTL_DSP_SETTRIGGER:
1576                 if (get_user(val, (int *) arg))
1577                         return -EFAULT;
1578                 if (file->f_mode & FMODE_READ) {
1579                         if (val & PCM_ENABLE_INPUT) {
1580                                 spin_lock_irqsave(&s->lock, flags);
1581                                 start_adc(s);
1582                                 spin_unlock_irqrestore(&s->lock, flags);
1583                         } else
1584                                 stop_adc(s);
1585                 }
1586                 if (file->f_mode & FMODE_WRITE) {
1587                         if (val & PCM_ENABLE_OUTPUT) {
1588                                 spin_lock_irqsave(&s->lock, flags);
1589                                 start_dac(s);
1590                                 spin_unlock_irqrestore(&s->lock, flags);
1591                         } else
1592                                 stop_dac(s);
1593                 }
1594                 return 0;
1595
1596         case SNDCTL_DSP_GETOSPACE:
1597                 if (!(file->f_mode & FMODE_WRITE))
1598                         return -EINVAL;
1599                 abinfo.fragsize = s->dma_dac.fragsize;
1600                 spin_lock_irqsave(&s->lock, flags);
1601                 count = s->dma_dac.count;
1602                 count -= dma_count_done(&s->dma_dac);
1603                 spin_unlock_irqrestore(&s->lock, flags);
1604                 if (count < 0)
1605                         count = 0;
1606                 abinfo.bytes = (s->dma_dac.dmasize - count) /
1607                         s->dma_dac.cnt_factor;
1608                 abinfo.fragstotal = s->dma_dac.numfrag;
1609                 abinfo.fragments = abinfo.bytes >> s->dma_dac.fragshift;
1610                 pr_debug("ioctl SNDCTL_DSP_GETOSPACE: bytes=%d, fragments=%d\n", abinfo.bytes, abinfo.fragments);
1611                 return copy_to_user((void *) arg, &abinfo,
1612                                     sizeof(abinfo)) ? -EFAULT : 0;
1613
1614         case SNDCTL_DSP_GETISPACE:
1615                 if (!(file->f_mode & FMODE_READ))
1616                         return -EINVAL;
1617                 abinfo.fragsize = s->dma_adc.fragsize;
1618                 spin_lock_irqsave(&s->lock, flags);
1619                 count = s->dma_adc.count;
1620                 count += dma_count_done(&s->dma_adc);
1621                 spin_unlock_irqrestore(&s->lock, flags);
1622                 if (count < 0)
1623                         count = 0;
1624                 abinfo.bytes = count / s->dma_adc.cnt_factor;
1625                 abinfo.fragstotal = s->dma_adc.numfrag;
1626                 abinfo.fragments = abinfo.bytes >> s->dma_adc.fragshift;
1627                 return copy_to_user((void *) arg, &abinfo,
1628                                     sizeof(abinfo)) ? -EFAULT : 0;
1629
1630         case SNDCTL_DSP_NONBLOCK:
1631                 spin_lock(&file->f_lock);
1632                 file->f_flags |= O_NONBLOCK;
1633                 spin_unlock(&file->f_lock);
1634                 return 0;
1635
1636         case SNDCTL_DSP_GETODELAY:
1637                 if (!(file->f_mode & FMODE_WRITE))
1638                         return -EINVAL;
1639                 spin_lock_irqsave(&s->lock, flags);
1640                 count = s->dma_dac.count;
1641                 count -= dma_count_done(&s->dma_dac);
1642                 spin_unlock_irqrestore(&s->lock, flags);
1643                 if (count < 0)
1644                         count = 0;
1645                 count /= s->dma_dac.cnt_factor;
1646                 return put_user(count, (int *) arg);
1647
1648         case SNDCTL_DSP_GETIPTR:
1649                 if (!(file->f_mode & FMODE_READ))
1650                         return -EINVAL;
1651                 spin_lock_irqsave(&s->lock, flags);
1652                 cinfo.bytes = s->dma_adc.total_bytes;
1653                 count = s->dma_adc.count;
1654                 if (!s->dma_adc.stopped) {
1655                         diff = dma_count_done(&s->dma_adc);
1656                         count += diff;
1657                         cinfo.bytes += diff;
1658                         cinfo.ptr =  virt_to_phys(s->dma_adc.nextIn) + diff -
1659                                 virt_to_phys(s->dma_adc.rawbuf);
1660                 } else
1661                         cinfo.ptr = virt_to_phys(s->dma_adc.nextIn) -
1662                                 virt_to_phys(s->dma_adc.rawbuf);
1663                 if (s->dma_adc.mapped)
1664                         s->dma_adc.count &= (s->dma_adc.dma_fragsize-1);
1665                 spin_unlock_irqrestore(&s->lock, flags);
1666                 if (count < 0)
1667                         count = 0;
1668                 cinfo.blocks = count >> s->dma_adc.fragshift;
1669                 return copy_to_user((void *) arg, &cinfo, sizeof(cinfo));
1670
1671         case SNDCTL_DSP_GETOPTR:
1672                 if (!(file->f_mode & FMODE_READ))
1673                         return -EINVAL;
1674                 spin_lock_irqsave(&s->lock, flags);
1675                 cinfo.bytes = s->dma_dac.total_bytes;
1676                 count = s->dma_dac.count;
1677                 if (!s->dma_dac.stopped) {
1678                         diff = dma_count_done(&s->dma_dac);
1679                         count -= diff;
1680                         cinfo.bytes += diff;
1681                         cinfo.ptr = virt_to_phys(s->dma_dac.nextOut) + diff -
1682                                 virt_to_phys(s->dma_dac.rawbuf);
1683                 } else
1684                         cinfo.ptr = virt_to_phys(s->dma_dac.nextOut) -
1685                                 virt_to_phys(s->dma_dac.rawbuf);
1686                 if (s->dma_dac.mapped)
1687                         s->dma_dac.count &= (s->dma_dac.dma_fragsize-1);
1688                 spin_unlock_irqrestore(&s->lock, flags);
1689                 if (count < 0)
1690                         count = 0;
1691                 cinfo.blocks = count >> s->dma_dac.fragshift;
1692                 return copy_to_user((void *) arg, &cinfo, sizeof(cinfo));
1693
1694         case SNDCTL_DSP_GETBLKSIZE:
1695                 if (file->f_mode & FMODE_WRITE)
1696                         return put_user(s->dma_dac.fragsize, (int *) arg);
1697                 else
1698                         return put_user(s->dma_adc.fragsize, (int *) arg);
1699
1700         case SNDCTL_DSP_SETFRAGMENT:
1701                 if (get_user(val, (int *) arg))
1702                         return -EFAULT;
1703                 if (file->f_mode & FMODE_READ) {
1704                         stop_adc(s);
1705                         s->dma_adc.ossfragshift = val & 0xffff;
1706                         s->dma_adc.ossmaxfrags = (val >> 16) & 0xffff;
1707                         if (s->dma_adc.ossfragshift < 4)
1708                                 s->dma_adc.ossfragshift = 4;
1709                         if (s->dma_adc.ossfragshift > 15)
1710                                 s->dma_adc.ossfragshift = 15;
1711                         if (s->dma_adc.ossmaxfrags < 4)
1712                                 s->dma_adc.ossmaxfrags = 4;
1713                         if ((ret = prog_dmabuf_adc(s)))
1714                                 return ret;
1715                 }
1716                 if (file->f_mode & FMODE_WRITE) {
1717                         stop_dac(s);
1718                         s->dma_dac.ossfragshift = val & 0xffff;
1719                         s->dma_dac.ossmaxfrags = (val >> 16) & 0xffff;
1720                         if (s->dma_dac.ossfragshift < 4)
1721                                 s->dma_dac.ossfragshift = 4;
1722                         if (s->dma_dac.ossfragshift > 15)
1723                                 s->dma_dac.ossfragshift = 15;
1724                         if (s->dma_dac.ossmaxfrags < 4)
1725                                 s->dma_dac.ossmaxfrags = 4;
1726                         if ((ret = prog_dmabuf_dac(s)))
1727                                 return ret;
1728                 }
1729                 return 0;
1730
1731         case SNDCTL_DSP_SUBDIVIDE:
1732                 if ((file->f_mode & FMODE_READ && s->dma_adc.subdivision) ||
1733                     (file->f_mode & FMODE_WRITE && s->dma_dac.subdivision))
1734                         return -EINVAL;
1735                 if (get_user(val, (int *) arg))
1736                         return -EFAULT;
1737                 if (val != 1 && val != 2 && val != 4)
1738                         return -EINVAL;
1739                 if (file->f_mode & FMODE_READ) {
1740                         stop_adc(s);
1741                         s->dma_adc.subdivision = val;
1742                         if ((ret = prog_dmabuf_adc(s)))
1743                                 return ret;
1744                 }
1745                 if (file->f_mode & FMODE_WRITE) {
1746                         stop_dac(s);
1747                         s->dma_dac.subdivision = val;
1748                         if ((ret = prog_dmabuf_dac(s)))
1749                                 return ret;
1750                 }
1751                 return 0;
1752
1753         case SOUND_PCM_READ_RATE:
1754                 return put_user((file->f_mode & FMODE_READ) ?
1755                                 s->dma_adc.sample_rate :
1756                                 s->dma_dac.sample_rate,
1757                                 (int *)arg);
1758
1759         case SOUND_PCM_READ_CHANNELS:
1760                 if (file->f_mode & FMODE_READ)
1761                         return put_user(s->dma_adc.num_channels, (int *)arg);
1762                 else
1763                         return put_user(s->dma_dac.num_channels, (int *)arg);
1764
1765         case SOUND_PCM_READ_BITS:
1766                 if (file->f_mode & FMODE_READ)
1767                         return put_user(s->dma_adc.sample_size, (int *)arg);
1768                 else
1769                         return put_user(s->dma_dac.sample_size, (int *)arg);
1770
1771         case SOUND_PCM_WRITE_FILTER:
1772         case SNDCTL_DSP_SETSYNCRO:
1773         case SOUND_PCM_READ_FILTER:
1774                 return -EINVAL;
1775         }
1776
1777         return mixdev_ioctl(s->codec, cmd, arg);
1778 }
1779
1780 static long
1781 au1550_unlocked_ioctl(struct file *file, unsigned int cmd, unsigned long arg)
1782 {
1783         int ret;
1784
1785         lock_kernel();
1786         ret = au1550_ioctl(file, cmd, arg);
1787         unlock_kernel();
1788
1789         return ret;
1790 }
1791
1792 static int
1793 au1550_open(struct inode *inode, struct file *file)
1794 {
1795         int             minor = MINOR(inode->i_rdev);
1796         DECLARE_WAITQUEUE(wait, current);
1797         struct au1550_state *s = &au1550_state;
1798         int             ret;
1799
1800 #ifdef DEBUG
1801         if (file->f_flags & O_NONBLOCK)
1802                 pr_debug("open: non-blocking\n");
1803         else
1804                 pr_debug("open: blocking\n");
1805 #endif
1806
1807         file->private_data = s;
1808         lock_kernel();
1809         /* wait for device to become free */
1810         mutex_lock(&s->open_mutex);
1811         while (s->open_mode & file->f_mode) {
1812                 ret = -EBUSY;
1813                 if (file->f_flags & O_NONBLOCK)
1814                         goto out;
1815                 add_wait_queue(&s->open_wait, &wait);
1816                 __set_current_state(TASK_INTERRUPTIBLE);
1817                 mutex_unlock(&s->open_mutex);
1818                 schedule();
1819                 remove_wait_queue(&s->open_wait, &wait);
1820                 set_current_state(TASK_RUNNING);
1821                 ret = -ERESTARTSYS;
1822                 if (signal_pending(current))
1823                         goto out2;
1824                 mutex_lock(&s->open_mutex);
1825         }
1826
1827         stop_dac(s);
1828         stop_adc(s);
1829
1830         if (file->f_mode & FMODE_READ) {
1831                 s->dma_adc.ossfragshift = s->dma_adc.ossmaxfrags =
1832                         s->dma_adc.subdivision = s->dma_adc.total_bytes = 0;
1833                 s->dma_adc.num_channels = 1;
1834                 s->dma_adc.sample_size = 8;
1835                 set_adc_rate(s, 8000);
1836                 if ((minor & 0xf) == SND_DEV_DSP16)
1837                         s->dma_adc.sample_size = 16;
1838         }
1839
1840         if (file->f_mode & FMODE_WRITE) {
1841                 s->dma_dac.ossfragshift = s->dma_dac.ossmaxfrags =
1842                         s->dma_dac.subdivision = s->dma_dac.total_bytes = 0;
1843                 s->dma_dac.num_channels = 1;
1844                 s->dma_dac.sample_size = 8;
1845                 set_dac_rate(s, 8000);
1846                 if ((minor & 0xf) == SND_DEV_DSP16)
1847                         s->dma_dac.sample_size = 16;
1848         }
1849
1850         if (file->f_mode & FMODE_READ) {
1851                 if ((ret = prog_dmabuf_adc(s)))
1852                         goto out;
1853         }
1854         if (file->f_mode & FMODE_WRITE) {
1855                 if ((ret = prog_dmabuf_dac(s)))
1856                         goto out;
1857         }
1858
1859         s->open_mode |= file->f_mode & (FMODE_READ | FMODE_WRITE);
1860         mutex_init(&s->sem);
1861         ret = 0;
1862 out:
1863         mutex_unlock(&s->open_mutex);
1864 out2:
1865         unlock_kernel();
1866         return ret;
1867 }
1868
1869 static int
1870 au1550_release(struct inode *inode, struct file *file)
1871 {
1872         struct au1550_state *s = (struct au1550_state *)file->private_data;
1873
1874         lock_kernel();
1875
1876         if (file->f_mode & FMODE_WRITE) {
1877                 unlock_kernel();
1878                 drain_dac(s, file->f_flags & O_NONBLOCK);
1879                 lock_kernel();
1880         }
1881
1882         mutex_lock(&s->open_mutex);
1883         if (file->f_mode & FMODE_WRITE) {
1884                 stop_dac(s);
1885                 kfree(s->dma_dac.rawbuf);
1886                 s->dma_dac.rawbuf = NULL;
1887         }
1888         if (file->f_mode & FMODE_READ) {
1889                 stop_adc(s);
1890                 kfree(s->dma_adc.rawbuf);
1891                 s->dma_adc.rawbuf = NULL;
1892         }
1893         s->open_mode &= ((~file->f_mode) & (FMODE_READ|FMODE_WRITE));
1894         mutex_unlock(&s->open_mutex);
1895         wake_up(&s->open_wait);
1896         unlock_kernel();
1897         return 0;
1898 }
1899
1900 static /*const */ struct file_operations au1550_audio_fops = {
1901         .owner          = THIS_MODULE,
1902         .llseek         = au1550_llseek,
1903         .read           = au1550_read,
1904         .write          = au1550_write,
1905         .poll           = au1550_poll,
1906         .unlocked_ioctl = au1550_unlocked_ioctl,
1907         .mmap           = au1550_mmap,
1908         .open           = au1550_open,
1909         .release        = au1550_release,
1910 };
1911
1912 MODULE_AUTHOR("Advanced Micro Devices (AMD), dan@embeddededge.com");
1913 MODULE_DESCRIPTION("Au1550 AC97 Audio Driver");
1914 MODULE_LICENSE("GPL");
1915
1916
1917 static int __devinit
1918 au1550_probe(void)
1919 {
1920         struct au1550_state *s = &au1550_state;
1921         int             val;
1922
1923         memset(s, 0, sizeof(struct au1550_state));
1924
1925         init_waitqueue_head(&s->dma_adc.wait);
1926         init_waitqueue_head(&s->dma_dac.wait);
1927         init_waitqueue_head(&s->open_wait);
1928         mutex_init(&s->open_mutex);
1929         spin_lock_init(&s->lock);
1930
1931         s->codec = ac97_alloc_codec();
1932         if(s->codec == NULL) {
1933                 err("Out of memory");
1934                 return -1;
1935         }
1936         s->codec->private_data = s;
1937         s->codec->id = 0;
1938         s->codec->codec_read = rdcodec;
1939         s->codec->codec_write = wrcodec;
1940         s->codec->codec_wait = waitcodec;
1941
1942         if (!request_mem_region(CPHYSADDR(AC97_PSC_SEL),
1943                             0x30, "Au1550 AC97")) {
1944                 err("AC'97 ports in use");
1945         }
1946
1947         /* Allocate the DMA Channels
1948         */
1949         if ((s->dma_dac.dmanr = au1xxx_dbdma_chan_alloc(DBDMA_MEM_CHAN,
1950             DBDMA_AC97_TX_CHAN, dac_dma_interrupt, (void *)s)) == 0) {
1951                 err("Can't get DAC DMA");
1952                 goto err_dma1;
1953         }
1954         au1xxx_dbdma_set_devwidth(s->dma_dac.dmanr, 16);
1955         if (au1xxx_dbdma_ring_alloc(s->dma_dac.dmanr,
1956                                         NUM_DBDMA_DESCRIPTORS) == 0) {
1957                 err("Can't get DAC DMA descriptors");
1958                 goto err_dma1;
1959         }
1960
1961         if ((s->dma_adc.dmanr = au1xxx_dbdma_chan_alloc(DBDMA_AC97_RX_CHAN,
1962             DBDMA_MEM_CHAN, adc_dma_interrupt, (void *)s)) == 0) {
1963                 err("Can't get ADC DMA");
1964                 goto err_dma2;
1965         }
1966         au1xxx_dbdma_set_devwidth(s->dma_adc.dmanr, 16);
1967         if (au1xxx_dbdma_ring_alloc(s->dma_adc.dmanr,
1968                                         NUM_DBDMA_DESCRIPTORS) == 0) {
1969                 err("Can't get ADC DMA descriptors");
1970                 goto err_dma2;
1971         }
1972
1973         pr_info("DAC: DMA%d, ADC: DMA%d", DBDMA_AC97_TX_CHAN, DBDMA_AC97_RX_CHAN);
1974
1975         /* register devices */
1976
1977         if ((s->dev_audio = register_sound_dsp(&au1550_audio_fops, -1)) < 0)
1978                 goto err_dev1;
1979         if ((s->codec->dev_mixer =
1980              register_sound_mixer(&au1550_mixer_fops, -1)) < 0)
1981                 goto err_dev2;
1982
1983         /* The GPIO for the appropriate PSC was configured by the
1984          * board specific start up.
1985          *
1986          * configure PSC for AC'97
1987          */
1988         au_writel(0, AC97_PSC_CTRL);    /* Disable PSC */
1989         au_sync();
1990         au_writel((PSC_SEL_CLK_SERCLK | PSC_SEL_PS_AC97MODE), AC97_PSC_SEL);
1991         au_sync();
1992
1993         /* cold reset the AC'97
1994         */
1995         au_writel(PSC_AC97RST_RST, PSC_AC97RST);
1996         au_sync();
1997         au1550_delay(10);
1998         au_writel(0, PSC_AC97RST);
1999         au_sync();
2000
2001         /* need to delay around 500msec(bleech) to give
2002            some CODECs enough time to wakeup */
2003         au1550_delay(500);
2004
2005         /* warm reset the AC'97 to start the bitclk
2006         */
2007         au_writel(PSC_AC97RST_SNC, PSC_AC97RST);
2008         au_sync();
2009         udelay(100);
2010         au_writel(0, PSC_AC97RST);
2011         au_sync();
2012
2013         /* Enable PSC
2014         */
2015         au_writel(PSC_CTRL_ENABLE, AC97_PSC_CTRL);
2016         au_sync();
2017
2018         /* Wait for PSC ready.
2019         */
2020         do {
2021                 val = au_readl(PSC_AC97STAT);
2022                 au_sync();
2023         } while ((val & PSC_AC97STAT_SR) == 0);
2024
2025         /* Configure AC97 controller.
2026          * Deep FIFO, 16-bit sample, DMA, make sure DMA matches fifo size.
2027          */
2028         val = PSC_AC97CFG_SET_LEN(16);
2029         val |= PSC_AC97CFG_RT_FIFO8 | PSC_AC97CFG_TT_FIFO8;
2030
2031         /* Enable device so we can at least
2032          * talk over the AC-link.
2033          */
2034         au_writel(val, PSC_AC97CFG);
2035         au_writel(PSC_AC97MSK_ALLMASK, PSC_AC97MSK);
2036         au_sync();
2037         val |= PSC_AC97CFG_DE_ENABLE;
2038         au_writel(val, PSC_AC97CFG);
2039         au_sync();
2040
2041         /* Wait for Device ready.
2042         */
2043         do {
2044                 val = au_readl(PSC_AC97STAT);
2045                 au_sync();
2046         } while ((val & PSC_AC97STAT_DR) == 0);
2047
2048         /* codec init */
2049         if (!ac97_probe_codec(s->codec))
2050                 goto err_dev3;
2051
2052         s->codec_base_caps = rdcodec(s->codec, AC97_RESET);
2053         s->codec_ext_caps = rdcodec(s->codec, AC97_EXTENDED_ID);
2054         pr_info("AC'97 Base/Extended ID = %04x/%04x",
2055              s->codec_base_caps, s->codec_ext_caps);
2056
2057         if (!(s->codec_ext_caps & AC97_EXTID_VRA)) {
2058                 /* codec does not support VRA
2059                 */
2060                 s->no_vra = 1;
2061         } else if (!vra) {
2062                 /* Boot option says disable VRA
2063                 */
2064                 u16 ac97_extstat = rdcodec(s->codec, AC97_EXTENDED_STATUS);
2065                 wrcodec(s->codec, AC97_EXTENDED_STATUS,
2066                         ac97_extstat & ~AC97_EXTSTAT_VRA);
2067                 s->no_vra = 1;
2068         }
2069         if (s->no_vra)
2070                 pr_info("no VRA, interpolating and decimating");
2071
2072         /* set mic to be the recording source */
2073         val = SOUND_MASK_MIC;
2074         mixdev_ioctl(s->codec, SOUND_MIXER_WRITE_RECSRC,
2075                      (unsigned long) &val);
2076
2077         return 0;
2078
2079  err_dev3:
2080         unregister_sound_mixer(s->codec->dev_mixer);
2081  err_dev2:
2082         unregister_sound_dsp(s->dev_audio);
2083  err_dev1:
2084         au1xxx_dbdma_chan_free(s->dma_adc.dmanr);
2085  err_dma2:
2086         au1xxx_dbdma_chan_free(s->dma_dac.dmanr);
2087  err_dma1:
2088         release_mem_region(CPHYSADDR(AC97_PSC_SEL), 0x30);
2089
2090         ac97_release_codec(s->codec);
2091         return -1;
2092 }
2093
2094 static void __devinit
2095 au1550_remove(void)
2096 {
2097         struct au1550_state *s = &au1550_state;
2098
2099         if (!s)
2100                 return;
2101         synchronize_irq();
2102         au1xxx_dbdma_chan_free(s->dma_adc.dmanr);
2103         au1xxx_dbdma_chan_free(s->dma_dac.dmanr);
2104         release_mem_region(CPHYSADDR(AC97_PSC_SEL), 0x30);
2105         unregister_sound_dsp(s->dev_audio);
2106         unregister_sound_mixer(s->codec->dev_mixer);
2107         ac97_release_codec(s->codec);
2108 }
2109
2110 static int __init
2111 init_au1550(void)
2112 {
2113         return au1550_probe();
2114 }
2115
2116 static void __exit
2117 cleanup_au1550(void)
2118 {
2119         au1550_remove();
2120 }
2121
2122 module_init(init_au1550);
2123 module_exit(cleanup_au1550);
2124
2125 #ifndef MODULE
2126
2127 static int __init
2128 au1550_setup(char *options)
2129 {
2130         char           *this_opt;
2131
2132         if (!options || !*options)
2133                 return 0;
2134
2135         while ((this_opt = strsep(&options, ","))) {
2136                 if (!*this_opt)
2137                         continue;
2138                 if (!strncmp(this_opt, "vra", 3)) {
2139                         vra = 1;
2140                 }
2141         }
2142
2143         return 1;
2144 }
2145
2146 __setup("au1550_audio=", au1550_setup);
2147
2148 #endif /* MODULE */