3 * Copyright (c) 2011, NVIDIA Corporation.
5 * This software is licensed under the terms of the GNU General Public
6 * License version 2, as published by the Free Software Foundation, and
7 * may be copied, distributed, and modified under those terms.
9 * This program is distributed in the hope that it will be useful,
10 * but WITHOUT ANY WARRANTY; without even the implied warranty of
11 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
12 * GNU General Public License for more details.
16 #ifndef __TEGRA_DTV_H__
17 #define __TEGRA_DTV_H__
19 #include <linux/ioctl.h>
21 #define TEGRA_DTV_MAGIC 'v'
23 #define TEGRA_DTV_IOCTL_START _IO(TEGRA_DTV_MAGIC, 0)
24 #define TEGRA_DTV_IOCTL_STOP _IO(TEGRA_DTV_MAGIC, 1)
26 struct tegra_dtv_hw_config {
42 #define TEGRA_DTV_IOCTL_SET_HW_CONFIG _IOW(TEGRA_DTV_MAGIC, 2, \
43 const struct tegra_dtv_hw_config *)
44 #define TEGRA_DTV_IOCTL_GET_HW_CONFIG _IOR(TEGRA_DTV_MAGIC, 3, \
45 struct tegra_dtv_hw_config *)
47 /* for selecting the pin configuration for VD(valid).
48 * NONE : ERROR is tied to 0, PSYNC is tied to 0
49 * ERROR: ERROR is tied to VD, PSYNC is tied to 0
50 * PSYNC: ERROR is tied to 0, PSYNC is tied to VD
53 TEGRA_DTV_PROTOCOL_NONE = 0,
54 TEGRA_DTV_PROTOCOL_ERROR,
55 TEGRA_DTV_PROTOCOL_PSYNC,
59 TEGRA_DTV_CLK_DISCONTINUOUS = 0,
60 TEGRA_DTV_CLK_CONTINUOUS,
64 TEGRA_DTV_BODY_VALID_IGNORE = 0,
65 TEGRA_DTV_BODY_VALID_GATE,
69 TEGRA_DTV_START_RESERVED = 0, /* never use this */
70 TEGRA_DTV_START_PSYNC,
71 TEGRA_DTV_START_VALID,
76 TEGRA_DTV_ERROR_POLARITY_HIGH = 0,
77 TEGRA_DTV_ERROR_POLARITY_LOW,
81 TEGRA_DTV_PSYNC_POLARITY_HIGH = 0,
82 TEGRA_DTV_PSYNC_POLARITY_LOW,
86 TEGRA_DTV_VALID_POLARITY_HIGH = 0,
87 TEGRA_DTV_VALID_POLARITY_LOW,
92 TEGRA_DTV_CLK_POSEDGE,
93 TEGRA_DTV_CLK_NEGEDGE,
96 struct tegra_dtv_platform_data {
97 unsigned int dma_buf_size;
99 bool byte_swz_enabled;
100 bool bit_swz_enabled;
102 #endif /* __KERNEL__ */
104 #endif /* __TEGRA_DTV_H__ */