video: tegra: host: Access nvhost_master via drvdata
[linux-2.6.git] / include / linux / sm501-regs.h
1 /* sm501-regs.h
2  *
3  * Copyright 2006 Simtec Electronics
4  *
5  * This program is free software; you can redistribute it and/or modify
6  * it under the terms of the GNU General Public License version 2 as
7  * published by the Free Software Foundation.
8  *
9  * Silicon Motion SM501 register definitions
10 */
11
12 /* System Configuration area */
13 /* System config base */
14 #define SM501_SYS_CONFIG                (0x000000)
15
16 /* config 1 */
17 #define SM501_SYSTEM_CONTROL            (0x000000)
18
19 #define SM501_SYSCTRL_PANEL_TRISTATE    (1<<0)
20 #define SM501_SYSCTRL_MEM_TRISTATE      (1<<1)
21 #define SM501_SYSCTRL_CRT_TRISTATE      (1<<2)
22
23 #define SM501_SYSCTRL_PCI_SLAVE_BURST_MASK (3<<4)
24 #define SM501_SYSCTRL_PCI_SLAVE_BURST_1 (0<<4)
25 #define SM501_SYSCTRL_PCI_SLAVE_BURST_2 (1<<4)
26 #define SM501_SYSCTRL_PCI_SLAVE_BURST_4 (2<<4)
27 #define SM501_SYSCTRL_PCI_SLAVE_BURST_8 (3<<4)
28
29 #define SM501_SYSCTRL_PCI_CLOCK_RUN_EN  (1<<6)
30 #define SM501_SYSCTRL_PCI_RETRY_DISABLE (1<<7)
31 #define SM501_SYSCTRL_PCI_SUBSYS_LOCK   (1<<11)
32 #define SM501_SYSCTRL_PCI_BURST_READ_EN (1<<15)
33
34 #define SM501_SYSCTRL_2D_ENGINE_STATUS  (1<<19)
35
36 /* miscellaneous control */
37
38 #define SM501_MISC_CONTROL              (0x000004)
39
40 #define SM501_MISC_BUS_SH               (0x0)
41 #define SM501_MISC_BUS_PCI              (0x1)
42 #define SM501_MISC_BUS_XSCALE           (0x2)
43 #define SM501_MISC_BUS_NEC              (0x6)
44 #define SM501_MISC_BUS_MASK             (0x7)
45
46 #define SM501_MISC_VR_62MB              (1<<3)
47 #define SM501_MISC_CDR_RESET            (1<<7)
48 #define SM501_MISC_USB_LB               (1<<8)
49 #define SM501_MISC_USB_SLAVE            (1<<9)
50 #define SM501_MISC_BL_1                 (1<<10)
51 #define SM501_MISC_MC                   (1<<11)
52 #define SM501_MISC_DAC_POWER            (1<<12)
53 #define SM501_MISC_IRQ_INVERT           (1<<16)
54 #define SM501_MISC_SH                   (1<<17)
55
56 #define SM501_MISC_HOLD_EMPTY           (0<<18)
57 #define SM501_MISC_HOLD_8               (1<<18)
58 #define SM501_MISC_HOLD_16              (2<<18)
59 #define SM501_MISC_HOLD_24              (3<<18)
60 #define SM501_MISC_HOLD_32              (4<<18)
61 #define SM501_MISC_HOLD_MASK            (7<<18)
62
63 #define SM501_MISC_FREQ_12              (1<<24)
64 #define SM501_MISC_PNL_24BIT            (1<<25)
65 #define SM501_MISC_8051_LE              (1<<26)
66
67
68
69 #define SM501_GPIO31_0_CONTROL          (0x000008)
70 #define SM501_GPIO63_32_CONTROL         (0x00000C)
71 #define SM501_DRAM_CONTROL              (0x000010)
72
73 /* command list */
74 #define SM501_ARBTRTN_CONTROL           (0x000014)
75
76 /* command list */
77 #define SM501_COMMAND_LIST_STATUS       (0x000024)
78
79 /* interrupt debug */
80 #define SM501_RAW_IRQ_STATUS            (0x000028)
81 #define SM501_RAW_IRQ_CLEAR             (0x000028)
82 #define SM501_IRQ_STATUS                (0x00002C)
83 #define SM501_IRQ_MASK                  (0x000030)
84 #define SM501_DEBUG_CONTROL             (0x000034)
85
86 /* power management */
87 #define SM501_POWERMODE_P2X_SRC         (1<<29)
88 #define SM501_POWERMODE_V2X_SRC         (1<<20)
89 #define SM501_POWERMODE_M_SRC           (1<<12)
90 #define SM501_POWERMODE_M1_SRC          (1<<4)
91
92 #define SM501_CURRENT_GATE              (0x000038)
93 #define SM501_CURRENT_CLOCK             (0x00003C)
94 #define SM501_POWER_MODE_0_GATE         (0x000040)
95 #define SM501_POWER_MODE_0_CLOCK        (0x000044)
96 #define SM501_POWER_MODE_1_GATE         (0x000048)
97 #define SM501_POWER_MODE_1_CLOCK        (0x00004C)
98 #define SM501_SLEEP_MODE_GATE           (0x000050)
99 #define SM501_POWER_MODE_CONTROL        (0x000054)
100
101 /* power gates for units within the 501 */
102 #define SM501_GATE_HOST                 (0)
103 #define SM501_GATE_MEMORY               (1)
104 #define SM501_GATE_DISPLAY              (2)
105 #define SM501_GATE_2D_ENGINE            (3)
106 #define SM501_GATE_CSC                  (4)
107 #define SM501_GATE_ZVPORT               (5)
108 #define SM501_GATE_GPIO                 (6)
109 #define SM501_GATE_UART0                (7)
110 #define SM501_GATE_UART1                (8)
111 #define SM501_GATE_SSP                  (10)
112 #define SM501_GATE_USB_HOST             (11)
113 #define SM501_GATE_USB_GADGET           (12)
114 #define SM501_GATE_UCONTROLLER          (17)
115 #define SM501_GATE_AC97                 (18)
116
117 /* panel clock */
118 #define SM501_CLOCK_P2XCLK              (24)
119 /* crt clock */
120 #define SM501_CLOCK_V2XCLK              (16)
121 /* main clock */
122 #define SM501_CLOCK_MCLK                (8)
123 /* SDRAM controller clock */
124 #define SM501_CLOCK_M1XCLK              (0)
125
126 /* config 2 */
127 #define SM501_PCI_MASTER_BASE           (0x000058)
128 #define SM501_ENDIAN_CONTROL            (0x00005C)
129 #define SM501_DEVICEID                  (0x000060)
130 /* 0x050100A0 */
131
132 #define SM501_DEVICEID_SM501            (0x05010000)
133 #define SM501_DEVICEID_IDMASK           (0xffff0000)
134 #define SM501_DEVICEID_REVMASK          (0x000000ff)
135
136 #define SM501_PLLCLOCK_COUNT            (0x000064)
137 #define SM501_MISC_TIMING               (0x000068)
138 #define SM501_CURRENT_SDRAM_CLOCK       (0x00006C)
139
140 #define SM501_PROGRAMMABLE_PLL_CONTROL  (0x000074)
141
142 /* GPIO base */
143 #define SM501_GPIO                      (0x010000)
144 #define SM501_GPIO_DATA_LOW             (0x00)
145 #define SM501_GPIO_DATA_HIGH            (0x04)
146 #define SM501_GPIO_DDR_LOW              (0x08)
147 #define SM501_GPIO_DDR_HIGH             (0x0C)
148 #define SM501_GPIO_IRQ_SETUP            (0x10)
149 #define SM501_GPIO_IRQ_STATUS           (0x14)
150 #define SM501_GPIO_IRQ_RESET            (0x14)
151
152 /* I2C controller base */
153 #define SM501_I2C                       (0x010040)
154 #define SM501_I2C_BYTE_COUNT            (0x00)
155 #define SM501_I2C_CONTROL               (0x01)
156 #define SM501_I2C_STATUS                (0x02)
157 #define SM501_I2C_RESET                 (0x02)
158 #define SM501_I2C_SLAVE_ADDRESS         (0x03)
159 #define SM501_I2C_DATA                  (0x04)
160
161 /* SSP base */
162 #define SM501_SSP                       (0x020000)
163
164 /* Uart 0 base */
165 #define SM501_UART0                     (0x030000)
166
167 /* Uart 1 base */
168 #define SM501_UART1                     (0x030020)
169
170 /* USB host port base */
171 #define SM501_USB_HOST                  (0x040000)
172
173 /* USB slave/gadget base */
174 #define SM501_USB_GADGET                (0x060000)
175
176 /* USB slave/gadget data port base */
177 #define SM501_USB_GADGET_DATA           (0x070000)
178
179 /* Display controller/video engine base */
180 #define SM501_DC                        (0x080000)
181
182 /* common defines for the SM501 address registers */
183 #define SM501_ADDR_FLIP                 (1<<31)
184 #define SM501_ADDR_EXT                  (1<<27)
185 #define SM501_ADDR_CS1                  (1<<26)
186 #define SM501_ADDR_MASK                 (0x3f << 26)
187
188 #define SM501_FIFO_MASK                 (0x3 << 16)
189 #define SM501_FIFO_1                    (0x0 << 16)
190 #define SM501_FIFO_3                    (0x1 << 16)
191 #define SM501_FIFO_7                    (0x2 << 16)
192 #define SM501_FIFO_11                   (0x3 << 16)
193
194 /* common registers for panel and the crt */
195 #define SM501_OFF_DC_H_TOT              (0x000)
196 #define SM501_OFF_DC_V_TOT              (0x008)
197 #define SM501_OFF_DC_H_SYNC             (0x004)
198 #define SM501_OFF_DC_V_SYNC             (0x00C)
199
200 #define SM501_DC_PANEL_CONTROL          (0x000)
201
202 #define SM501_DC_PANEL_CONTROL_FPEN     (1<<27)
203 #define SM501_DC_PANEL_CONTROL_BIAS     (1<<26)
204 #define SM501_DC_PANEL_CONTROL_DATA     (1<<25)
205 #define SM501_DC_PANEL_CONTROL_VDD      (1<<24)
206 #define SM501_DC_PANEL_CONTROL_DP       (1<<23)
207
208 #define SM501_DC_PANEL_CONTROL_TFT_888  (0<<21)
209 #define SM501_DC_PANEL_CONTROL_TFT_333  (1<<21)
210 #define SM501_DC_PANEL_CONTROL_TFT_444  (2<<21)
211
212 #define SM501_DC_PANEL_CONTROL_DE       (1<<20)
213
214 #define SM501_DC_PANEL_CONTROL_LCD_TFT  (0<<18)
215 #define SM501_DC_PANEL_CONTROL_LCD_STN8 (1<<18)
216 #define SM501_DC_PANEL_CONTROL_LCD_STN12 (2<<18)
217
218 #define SM501_DC_PANEL_CONTROL_CP       (1<<14)
219 #define SM501_DC_PANEL_CONTROL_VSP      (1<<13)
220 #define SM501_DC_PANEL_CONTROL_HSP      (1<<12)
221 #define SM501_DC_PANEL_CONTROL_CK       (1<<9)
222 #define SM501_DC_PANEL_CONTROL_TE       (1<<8)
223 #define SM501_DC_PANEL_CONTROL_VPD      (1<<7)
224 #define SM501_DC_PANEL_CONTROL_VP       (1<<6)
225 #define SM501_DC_PANEL_CONTROL_HPD      (1<<5)
226 #define SM501_DC_PANEL_CONTROL_HP       (1<<4)
227 #define SM501_DC_PANEL_CONTROL_GAMMA    (1<<3)
228 #define SM501_DC_PANEL_CONTROL_EN       (1<<2)
229
230 #define SM501_DC_PANEL_CONTROL_8BPP     (0<<0)
231 #define SM501_DC_PANEL_CONTROL_16BPP    (1<<0)
232 #define SM501_DC_PANEL_CONTROL_32BPP    (2<<0)
233
234
235 #define SM501_DC_PANEL_PANNING_CONTROL  (0x004)
236 #define SM501_DC_PANEL_COLOR_KEY        (0x008)
237 #define SM501_DC_PANEL_FB_ADDR          (0x00C)
238 #define SM501_DC_PANEL_FB_OFFSET        (0x010)
239 #define SM501_DC_PANEL_FB_WIDTH         (0x014)
240 #define SM501_DC_PANEL_FB_HEIGHT        (0x018)
241 #define SM501_DC_PANEL_TL_LOC           (0x01C)
242 #define SM501_DC_PANEL_BR_LOC           (0x020)
243 #define SM501_DC_PANEL_H_TOT            (0x024)
244 #define SM501_DC_PANEL_H_SYNC           (0x028)
245 #define SM501_DC_PANEL_V_TOT            (0x02C)
246 #define SM501_DC_PANEL_V_SYNC           (0x030)
247 #define SM501_DC_PANEL_CUR_LINE         (0x034)
248
249 #define SM501_DC_VIDEO_CONTROL          (0x040)
250 #define SM501_DC_VIDEO_FB0_ADDR         (0x044)
251 #define SM501_DC_VIDEO_FB_WIDTH         (0x048)
252 #define SM501_DC_VIDEO_FB0_LAST_ADDR    (0x04C)
253 #define SM501_DC_VIDEO_TL_LOC           (0x050)
254 #define SM501_DC_VIDEO_BR_LOC           (0x054)
255 #define SM501_DC_VIDEO_SCALE            (0x058)
256 #define SM501_DC_VIDEO_INIT_SCALE       (0x05C)
257 #define SM501_DC_VIDEO_YUV_CONSTANTS    (0x060)
258 #define SM501_DC_VIDEO_FB1_ADDR         (0x064)
259 #define SM501_DC_VIDEO_FB1_LAST_ADDR    (0x068)
260
261 #define SM501_DC_VIDEO_ALPHA_CONTROL    (0x080)
262 #define SM501_DC_VIDEO_ALPHA_FB_ADDR    (0x084)
263 #define SM501_DC_VIDEO_ALPHA_FB_OFFSET  (0x088)
264 #define SM501_DC_VIDEO_ALPHA_FB_LAST_ADDR       (0x08C)
265 #define SM501_DC_VIDEO_ALPHA_TL_LOC     (0x090)
266 #define SM501_DC_VIDEO_ALPHA_BR_LOC     (0x094)
267 #define SM501_DC_VIDEO_ALPHA_SCALE      (0x098)
268 #define SM501_DC_VIDEO_ALPHA_INIT_SCALE (0x09C)
269 #define SM501_DC_VIDEO_ALPHA_CHROMA_KEY (0x0A0)
270 #define SM501_DC_VIDEO_ALPHA_COLOR_LOOKUP       (0x0A4)
271
272 #define SM501_DC_PANEL_HWC_BASE         (0x0F0)
273 #define SM501_DC_PANEL_HWC_ADDR         (0x0F0)
274 #define SM501_DC_PANEL_HWC_LOC          (0x0F4)
275 #define SM501_DC_PANEL_HWC_COLOR_1_2    (0x0F8)
276 #define SM501_DC_PANEL_HWC_COLOR_3      (0x0FC)
277
278 #define SM501_HWC_EN                    (1<<31)
279
280 #define SM501_OFF_HWC_ADDR              (0x00)
281 #define SM501_OFF_HWC_LOC               (0x04)
282 #define SM501_OFF_HWC_COLOR_1_2         (0x08)
283 #define SM501_OFF_HWC_COLOR_3           (0x0C)
284
285 #define SM501_DC_ALPHA_CONTROL          (0x100)
286 #define SM501_DC_ALPHA_FB_ADDR          (0x104)
287 #define SM501_DC_ALPHA_FB_OFFSET        (0x108)
288 #define SM501_DC_ALPHA_TL_LOC           (0x10C)
289 #define SM501_DC_ALPHA_BR_LOC           (0x110)
290 #define SM501_DC_ALPHA_CHROMA_KEY       (0x114)
291 #define SM501_DC_ALPHA_COLOR_LOOKUP     (0x118)
292
293 #define SM501_DC_CRT_CONTROL            (0x200)
294
295 #define SM501_DC_CRT_CONTROL_TVP        (1<<15)
296 #define SM501_DC_CRT_CONTROL_CP         (1<<14)
297 #define SM501_DC_CRT_CONTROL_VSP        (1<<13)
298 #define SM501_DC_CRT_CONTROL_HSP        (1<<12)
299 #define SM501_DC_CRT_CONTROL_VS         (1<<11)
300 #define SM501_DC_CRT_CONTROL_BLANK      (1<<10)
301 #define SM501_DC_CRT_CONTROL_SEL        (1<<9)
302 #define SM501_DC_CRT_CONTROL_TE         (1<<8)
303 #define SM501_DC_CRT_CONTROL_PIXEL_MASK (0xF << 4)
304 #define SM501_DC_CRT_CONTROL_GAMMA      (1<<3)
305 #define SM501_DC_CRT_CONTROL_ENABLE     (1<<2)
306
307 #define SM501_DC_CRT_CONTROL_8BPP       (0<<0)
308 #define SM501_DC_CRT_CONTROL_16BPP      (1<<0)
309 #define SM501_DC_CRT_CONTROL_32BPP      (2<<0)
310
311 #define SM501_DC_CRT_FB_ADDR            (0x204)
312 #define SM501_DC_CRT_FB_OFFSET          (0x208)
313 #define SM501_DC_CRT_H_TOT              (0x20C)
314 #define SM501_DC_CRT_H_SYNC             (0x210)
315 #define SM501_DC_CRT_V_TOT              (0x214)
316 #define SM501_DC_CRT_V_SYNC             (0x218)
317 #define SM501_DC_CRT_SIGNATURE_ANALYZER (0x21C)
318 #define SM501_DC_CRT_CUR_LINE           (0x220)
319 #define SM501_DC_CRT_MONITOR_DETECT     (0x224)
320
321 #define SM501_DC_CRT_HWC_BASE           (0x230)
322 #define SM501_DC_CRT_HWC_ADDR           (0x230)
323 #define SM501_DC_CRT_HWC_LOC            (0x234)
324 #define SM501_DC_CRT_HWC_COLOR_1_2      (0x238)
325 #define SM501_DC_CRT_HWC_COLOR_3        (0x23C)
326
327 #define SM501_DC_PANEL_PALETTE          (0x400)
328
329 #define SM501_DC_VIDEO_PALETTE          (0x800)
330
331 #define SM501_DC_CRT_PALETTE            (0xC00)
332
333 /* Zoom Video port base */
334 #define SM501_ZVPORT                    (0x090000)
335
336 /* AC97/I2S base */
337 #define SM501_AC97                      (0x0A0000)
338
339 /* 8051 micro controller base */
340 #define SM501_UCONTROLLER               (0x0B0000)
341
342 /* 8051 micro controller SRAM base */
343 #define SM501_UCONTROLLER_SRAM          (0x0C0000)
344
345 /* DMA base */
346 #define SM501_DMA                       (0x0D0000)
347
348 /* 2d engine base */
349 #define SM501_2D_ENGINE                 (0x100000)
350 #define SM501_2D_SOURCE                 (0x00)
351 #define SM501_2D_DESTINATION            (0x04)
352 #define SM501_2D_DIMENSION              (0x08)
353 #define SM501_2D_CONTROL                (0x0C)
354 #define SM501_2D_PITCH                  (0x10)
355 #define SM501_2D_FOREGROUND             (0x14)
356 #define SM501_2D_BACKGROUND             (0x18)
357 #define SM501_2D_STRETCH                (0x1C)
358 #define SM501_2D_COLOR_COMPARE          (0x20)
359 #define SM501_2D_COLOR_COMPARE_MASK     (0x24)
360 #define SM501_2D_MASK                   (0x28)
361 #define SM501_2D_CLIP_TL                (0x2C)
362 #define SM501_2D_CLIP_BR                (0x30)
363 #define SM501_2D_MONO_PATTERN_LOW       (0x34)
364 #define SM501_2D_MONO_PATTERN_HIGH      (0x38)
365 #define SM501_2D_WINDOW_WIDTH           (0x3C)
366 #define SM501_2D_SOURCE_BASE            (0x40)
367 #define SM501_2D_DESTINATION_BASE       (0x44)
368 #define SM501_2D_ALPHA                  (0x48)
369 #define SM501_2D_WRAP                   (0x4C)
370 #define SM501_2D_STATUS                 (0x50)
371
372 #define SM501_CSC_Y_SOURCE_BASE         (0xC8)
373 #define SM501_CSC_CONSTANTS             (0xCC)
374 #define SM501_CSC_Y_SOURCE_X            (0xD0)
375 #define SM501_CSC_Y_SOURCE_Y            (0xD4)
376 #define SM501_CSC_U_SOURCE_BASE         (0xD8)
377 #define SM501_CSC_V_SOURCE_BASE         (0xDC)
378 #define SM501_CSC_SOURCE_DIMENSION      (0xE0)
379 #define SM501_CSC_SOURCE_PITCH          (0xE4)
380 #define SM501_CSC_DESTINATION           (0xE8)
381 #define SM501_CSC_DESTINATION_DIMENSION (0xEC)
382 #define SM501_CSC_DESTINATION_PITCH     (0xF0)
383 #define SM501_CSC_SCALE_FACTOR          (0xF4)
384 #define SM501_CSC_DESTINATION_BASE      (0xF8)
385 #define SM501_CSC_CONTROL               (0xFC)
386
387 /* 2d engine data port base */
388 #define SM501_2D_ENGINE_DATA            (0x110000)