Merge tag 'gpio-for-linus' of git://git.secretlab.ca/git/linux-2.6
[linux-2.6.git] / include / linux / mfd / rc5t583.h
1 /*
2  * Core driver interface to access RICOH_RC5T583 power management chip.
3  *
4  * Copyright (c) 2011-2012, NVIDIA CORPORATION.  All rights reserved.
5  * Author: Laxman dewangan <ldewangan@nvidia.com>
6  *
7  * Based on code
8  *      Copyright (C) 2011 RICOH COMPANY,LTD
9  *
10  * This program is free software; you can redistribute it and/or modify it
11  * under the terms and conditions of the GNU General Public License,
12  * version 2, as published by the Free Software Foundation.
13  *
14  * This program is distributed in the hope it will be useful, but WITHOUT
15  * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
16  * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
17  * more details.
18  *
19  * You should have received a copy of the GNU General Public License
20  * along with this program.  If not, see <http://www.gnu.org/licenses/>.
21  *
22  */
23
24 #ifndef __LINUX_MFD_RC5T583_H
25 #define __LINUX_MFD_RC5T583_H
26
27 #include <linux/mutex.h>
28 #include <linux/types.h>
29
30 #define RC5T583_MAX_REGS                0xF8
31
32 /* Maximum number of main interrupts */
33 #define MAX_MAIN_INTERRUPT              5
34 #define RC5T583_MAX_GPEDGE_REG          2
35 #define RC5T583_MAX_INTERRUPT_MASK_REGS 9
36
37 /* Interrupt enable register */
38 #define RC5T583_INT_EN_SYS1     0x19
39 #define RC5T583_INT_EN_SYS2     0x1D
40 #define RC5T583_INT_EN_DCDC     0x41
41 #define RC5T583_INT_EN_RTC      0xED
42 #define RC5T583_INT_EN_ADC1     0x90
43 #define RC5T583_INT_EN_ADC2     0x91
44 #define RC5T583_INT_EN_ADC3     0x92
45
46 /* Interrupt status registers (monitor regs in Ricoh)*/
47 #define RC5T583_INTC_INTPOL     0xAD
48 #define RC5T583_INTC_INTEN      0xAE
49 #define RC5T583_INTC_INTMON     0xAF
50
51 #define RC5T583_INT_MON_GRP     0xAF
52 #define RC5T583_INT_MON_SYS1    0x1B
53 #define RC5T583_INT_MON_SYS2    0x1F
54 #define RC5T583_INT_MON_DCDC    0x43
55 #define RC5T583_INT_MON_RTC     0xEE
56
57 /* Interrupt clearing registers */
58 #define RC5T583_INT_IR_SYS1     0x1A
59 #define RC5T583_INT_IR_SYS2     0x1E
60 #define RC5T583_INT_IR_DCDC     0x42
61 #define RC5T583_INT_IR_RTC      0xEE
62 #define RC5T583_INT_IR_ADCL     0x94
63 #define RC5T583_INT_IR_ADCH     0x95
64 #define RC5T583_INT_IR_ADCEND   0x96
65 #define RC5T583_INT_IR_GPIOR    0xA9
66 #define RC5T583_INT_IR_GPIOF    0xAA
67
68 /* Sleep sequence registers */
69 #define RC5T583_SLPSEQ1         0x21
70 #define RC5T583_SLPSEQ2         0x22
71 #define RC5T583_SLPSEQ3         0x23
72 #define RC5T583_SLPSEQ4         0x24
73 #define RC5T583_SLPSEQ5         0x25
74 #define RC5T583_SLPSEQ6         0x26
75 #define RC5T583_SLPSEQ7         0x27
76 #define RC5T583_SLPSEQ8         0x28
77 #define RC5T583_SLPSEQ9         0x29
78 #define RC5T583_SLPSEQ10        0x2A
79 #define RC5T583_SLPSEQ11        0x2B
80
81 /* Regulator registers */
82 #define RC5T583_REG_DC0CTL      0x30
83 #define RC5T583_REG_DC0DAC      0x31
84 #define RC5T583_REG_DC0LATCTL   0x32
85 #define RC5T583_REG_SR0CTL      0x33
86
87 #define RC5T583_REG_DC1CTL      0x34
88 #define RC5T583_REG_DC1DAC      0x35
89 #define RC5T583_REG_DC1LATCTL   0x36
90 #define RC5T583_REG_SR1CTL      0x37
91
92 #define RC5T583_REG_DC2CTL      0x38
93 #define RC5T583_REG_DC2DAC      0x39
94 #define RC5T583_REG_DC2LATCTL   0x3A
95 #define RC5T583_REG_SR2CTL      0x3B
96
97 #define RC5T583_REG_DC3CTL      0x3C
98 #define RC5T583_REG_DC3DAC      0x3D
99 #define RC5T583_REG_DC3LATCTL   0x3E
100 #define RC5T583_REG_SR3CTL      0x3F
101
102
103 #define RC5T583_REG_LDOEN1      0x50
104 #define RC5T583_REG_LDOEN2      0x51
105 #define RC5T583_REG_LDODIS1     0x52
106 #define RC5T583_REG_LDODIS2     0x53
107
108 #define RC5T583_REG_LDO0DAC     0x54
109 #define RC5T583_REG_LDO1DAC     0x55
110 #define RC5T583_REG_LDO2DAC     0x56
111 #define RC5T583_REG_LDO3DAC     0x57
112 #define RC5T583_REG_LDO4DAC     0x58
113 #define RC5T583_REG_LDO5DAC     0x59
114 #define RC5T583_REG_LDO6DAC     0x5A
115 #define RC5T583_REG_LDO7DAC     0x5B
116 #define RC5T583_REG_LDO8DAC     0x5C
117 #define RC5T583_REG_LDO9DAC     0x5D
118
119 #define RC5T583_REG_DC0DAC_DS   0x60
120 #define RC5T583_REG_DC1DAC_DS   0x61
121 #define RC5T583_REG_DC2DAC_DS   0x62
122 #define RC5T583_REG_DC3DAC_DS   0x63
123
124 #define RC5T583_REG_LDO0DAC_DS  0x64
125 #define RC5T583_REG_LDO1DAC_DS  0x65
126 #define RC5T583_REG_LDO2DAC_DS  0x66
127 #define RC5T583_REG_LDO3DAC_DS  0x67
128 #define RC5T583_REG_LDO4DAC_DS  0x68
129 #define RC5T583_REG_LDO5DAC_DS  0x69
130 #define RC5T583_REG_LDO6DAC_DS  0x6A
131 #define RC5T583_REG_LDO7DAC_DS  0x6B
132 #define RC5T583_REG_LDO8DAC_DS  0x6C
133 #define RC5T583_REG_LDO9DAC_DS  0x6D
134
135 /* GPIO register base address */
136 #define RC5T583_GPIO_IOSEL      0xA0
137 #define RC5T583_GPIO_PDEN       0xA1
138 #define RC5T583_GPIO_IOOUT      0xA2
139 #define RC5T583_GPIO_PGSEL      0xA3
140 #define RC5T583_GPIO_GPINV      0xA4
141 #define RC5T583_GPIO_GPDEB      0xA5
142 #define RC5T583_GPIO_GPEDGE1    0xA6
143 #define RC5T583_GPIO_GPEDGE2    0xA7
144 #define RC5T583_GPIO_EN_INT     0xA8
145 #define RC5T583_GPIO_MON_IOIN   0xAB
146 #define RC5T583_GPIO_GPOFUNC    0xAC
147
148 /* RICOH_RC5T583 IRQ definitions */
149 enum {
150         RC5T583_IRQ_ONKEY,
151         RC5T583_IRQ_ACOK,
152         RC5T583_IRQ_LIDOPEN,
153         RC5T583_IRQ_PREOT,
154         RC5T583_IRQ_CLKSTP,
155         RC5T583_IRQ_ONKEY_OFF,
156         RC5T583_IRQ_WD,
157         RC5T583_IRQ_EN_PWRREQ1,
158         RC5T583_IRQ_EN_PWRREQ2,
159         RC5T583_IRQ_PRE_VINDET,
160
161         RC5T583_IRQ_DC0LIM,
162         RC5T583_IRQ_DC1LIM,
163         RC5T583_IRQ_DC2LIM,
164         RC5T583_IRQ_DC3LIM,
165
166         RC5T583_IRQ_CTC,
167         RC5T583_IRQ_YALE,
168         RC5T583_IRQ_DALE,
169         RC5T583_IRQ_WALE,
170
171         RC5T583_IRQ_AIN1L,
172         RC5T583_IRQ_AIN2L,
173         RC5T583_IRQ_AIN3L,
174         RC5T583_IRQ_VBATL,
175         RC5T583_IRQ_VIN3L,
176         RC5T583_IRQ_VIN8L,
177         RC5T583_IRQ_AIN1H,
178         RC5T583_IRQ_AIN2H,
179         RC5T583_IRQ_AIN3H,
180         RC5T583_IRQ_VBATH,
181         RC5T583_IRQ_VIN3H,
182         RC5T583_IRQ_VIN8H,
183         RC5T583_IRQ_ADCEND,
184
185         RC5T583_IRQ_GPIO0,
186         RC5T583_IRQ_GPIO1,
187         RC5T583_IRQ_GPIO2,
188         RC5T583_IRQ_GPIO3,
189         RC5T583_IRQ_GPIO4,
190         RC5T583_IRQ_GPIO5,
191         RC5T583_IRQ_GPIO6,
192         RC5T583_IRQ_GPIO7,
193
194         /* Should be last entry */
195         RC5T583_MAX_IRQS,
196 };
197
198 /* Ricoh583 gpio definitions */
199 enum {
200         RC5T583_GPIO0,
201         RC5T583_GPIO1,
202         RC5T583_GPIO2,
203         RC5T583_GPIO3,
204         RC5T583_GPIO4,
205         RC5T583_GPIO5,
206         RC5T583_GPIO6,
207         RC5T583_GPIO7,
208
209         /* Should be last entry */
210         RC5T583_MAX_GPIO,
211 };
212
213 enum {
214         RC5T583_DS_NONE,
215         RC5T583_DS_DC0,
216         RC5T583_DS_DC1,
217         RC5T583_DS_DC2,
218         RC5T583_DS_DC3,
219         RC5T583_DS_LDO0,
220         RC5T583_DS_LDO1,
221         RC5T583_DS_LDO2,
222         RC5T583_DS_LDO3,
223         RC5T583_DS_LDO4,
224         RC5T583_DS_LDO5,
225         RC5T583_DS_LDO6,
226         RC5T583_DS_LDO7,
227         RC5T583_DS_LDO8,
228         RC5T583_DS_LDO9,
229         RC5T583_DS_PSO0,
230         RC5T583_DS_PSO1,
231         RC5T583_DS_PSO2,
232         RC5T583_DS_PSO3,
233         RC5T583_DS_PSO4,
234         RC5T583_DS_PSO5,
235         RC5T583_DS_PSO6,
236         RC5T583_DS_PSO7,
237
238         /* Should be last entry */
239         RC5T583_DS_MAX,
240 };
241
242 /*
243  * Ricoh pmic RC5T583 supports sleep through two external controls.
244  * The output of gpios and regulator can be enable/disable through
245  * this external signals.
246  */
247 enum {
248         RC5T583_EXT_PWRREQ1_CONTROL = 0x1,
249         RC5T583_EXT_PWRREQ2_CONTROL = 0x2,
250 };
251
252 struct rc5t583 {
253         struct device   *dev;
254         struct regmap   *regmap;
255         int             chip_irq;
256         int             irq_base;
257         struct mutex    irq_lock;
258         unsigned long   group_irq_en[MAX_MAIN_INTERRUPT];
259
260         /* For main interrupt bits in INTC */
261         uint8_t         intc_inten_reg;
262
263         /* For group interrupt bits and address */
264         uint8_t         irq_en_reg[RC5T583_MAX_INTERRUPT_MASK_REGS];
265
266         /* For gpio edge */
267         uint8_t         gpedge_reg[RC5T583_MAX_GPEDGE_REG];
268 };
269
270 /*
271  * rc5t583_platform_data: Platform data for ricoh rc5t583 pmu.
272  * The board specific data is provided through this structure.
273  * @irq_base: Irq base number on which this device registers their interrupts.
274  * @enable_shutdown: Enable shutdown through the input pin "shutdown".
275  */
276
277 struct rc5t583_platform_data {
278         int             irq_base;
279         bool            enable_shutdown;
280 };
281
282 int rc5t583_write(struct device *dev, u8 reg, uint8_t val);
283 int rc5t583_read(struct device *dev, uint8_t reg, uint8_t *val);
284 int rc5t583_set_bits(struct device *dev, unsigned int reg,
285                 unsigned int bit_mask);
286 int rc5t583_clear_bits(struct device *dev, unsigned int reg,
287                 unsigned int bit_mask);
288 int rc5t583_update(struct device *dev, unsigned int reg,
289                 unsigned int val, unsigned int mask);
290 int rc5t583_ext_power_req_config(struct device *dev, int deepsleep_id,
291         int ext_pwr_req, int deepsleep_slot_nr);
292 int rc5t583_irq_init(struct rc5t583 *rc5t583, int irq, int irq_base);
293 int rc5t583_irq_exit(struct rc5t583 *rc5t583);
294
295 #endif