c536453618f456ff82903add00f574b8dd8a5e4d
[linux-2.6.git] / include / linux / mfd / palmas.h
1 /*
2  * TI Palmas
3  *
4  * Copyright 2011 Texas Instruments Inc.
5  *
6  * Author: Graeme Gregory <gg@slimlogic.co.uk>
7  *
8  *  This program is free software; you can redistribute it and/or modify it
9  *  under  the terms of the GNU General  Public License as published by the
10  *  Free Software Foundation;  either version 2 of the License, or (at your
11  *  option) any later version.
12  *
13  */
14
15 #ifndef __LINUX_MFD_PALMAS_H
16 #define __LINUX_MFD_PALMAS_H
17
18 #include <linux/usb/otg.h>
19 #include <linux/leds.h>
20 #include <linux/regmap.h>
21 #include <linux/regulator/driver.h>
22
23 #define PALMAS_NUM_CLIENTS              3
24
25 struct palmas_pmic;
26 struct palmas_rtc;
27
28 #define palmas_rails(_name) "palmas_"#_name
29
30 struct palmas {
31         struct device *dev;
32
33         struct i2c_client *i2c_clients[PALMAS_NUM_CLIENTS];
34         struct regmap *regmap[PALMAS_NUM_CLIENTS];
35
36         /* Stored chip id */
37         int id;
38
39         /* IRQ Data */
40         int irq;
41         u32 irq_mask;
42         struct palmas_irq_chip_data *irq_chip_data;
43
44         /* Child Devices */
45         struct palmas_pmic *pmic;
46         struct palmas_rtc *rtc;
47
48         /* GPIO MUXing */
49         u8 gpio_muxed;
50         u8 led_muxed;
51         u8 pwm_muxed;
52
53         int design_revision;
54         int sw_otp_version;
55         int es_minor_version;
56         int es_major_version;
57 };
58
59 struct palmas_reg_init {
60         /* warm_rest controls the voltage levels after a warm reset
61          *
62          * 0: reload default values from OTP on warm reset
63          * 1: maintain voltage from VSEL on warm reset
64          */
65         int warm_reset;
66
67         /* roof_floor controls whether the regulator uses the i2c style
68          * of DVS or uses the method where a GPIO or other control method is
69          * attached to the NSLEEP/ENABLE1/ENABLE2 pins
70          *
71          * For SMPS
72          *
73          * 0: i2c selection of voltage
74          * 1: pin selection of voltage.
75          *
76          * For LDO unused
77          */
78         int roof_floor;
79
80         /* sleep_mode is the mode loaded to MODE_SLEEP bits as defined in
81          * the data sheet.
82          *
83          * For SMPS
84          *
85          * 0: Off
86          * 1: AUTO
87          * 2: ECO
88          * 3: Forced PWM
89          *
90          * For LDO
91          *
92          * 0: Off
93          * 1: On
94          */
95         int mode_sleep;
96
97         /* tstep is the timestep loaded to the TSTEP register
98          *
99          * For SMPS
100          *
101          * 0: Jump (no slope control)
102          * 1: 10mV/us
103          * 2: 5mV/us
104          * 3: 2.5mV/us
105          *
106          * For LDO unused
107          */
108         int tstep;
109
110         /* voltage_sel is the bitfield loaded onto the SMPSX_VOLTAGE
111          * register. Set this is the default voltage set in OTP needs
112          * to be overridden.
113          */
114         u8 vsel;
115
116 };
117
118 enum palmas_regulators {
119         /* SMPS regulators */
120         PALMAS_REG_SMPS12,
121         PALMAS_REG_SMPS123,
122         PALMAS_REG_SMPS3,
123         PALMAS_REG_SMPS45,
124         PALMAS_REG_SMPS457,
125         PALMAS_REG_SMPS6,
126         PALMAS_REG_SMPS7,
127         PALMAS_REG_SMPS8,
128         PALMAS_REG_SMPS9,
129         PALMAS_REG_SMPS10,
130         /* LDO regulators */
131         PALMAS_REG_LDO1,
132         PALMAS_REG_LDO2,
133         PALMAS_REG_LDO3,
134         PALMAS_REG_LDO4,
135         PALMAS_REG_LDO5,
136         PALMAS_REG_LDO6,
137         PALMAS_REG_LDO7,
138         PALMAS_REG_LDO8,
139         PALMAS_REG_LDO9,
140         PALMAS_REG_LDOLN,
141         PALMAS_REG_LDOUSB,
142         /* External regulators */
143         PALMAS_REG_REGEN1,
144         PALMAS_REG_REGEN2,
145         PALMAS_REG_REGEN3,
146         PALMAS_REG_SYSEN1,
147         PALMAS_REG_SYSEN2,
148         /* Total number of regulators */
149         PALMAS_NUM_REGS,
150 };
151
152 enum PALMAS_CLOCK32K {
153         PALMAS_CLOCK32KG,
154         PALMAS_CLOCK32KG_AUDIO,
155
156         /* Last entry */
157         PALMAS_CLOCK32K_NR,
158 };
159
160 struct palmas_clk32k_init_data {
161         int clk32k_id;
162         bool enable;
163         int sleep_control;
164 };
165
166 struct palmas_dvfs_init_data {
167         bool    en_pwm;
168         int     ext_ctrl;
169         int     reg_id;
170         bool    step_20mV;
171         int     base_voltage_uV;
172         int     max_voltage_uV;
173 };
174
175 struct palmas_pmic_platform_data {
176         /* An array of pointers to regulator init data indexed by regulator
177          * ID
178          */
179         struct regulator_init_data *reg_data[PALMAS_NUM_REGS];
180
181         /* An array of pointers to structures containing sleep mode and DVS
182          * configuration for regulators indexed by ID
183          */
184         struct palmas_reg_init *reg_init[PALMAS_NUM_REGS];
185
186         /* CL DVFS init data */
187         struct palmas_dvfs_init_data *dvfs_init_data;
188         int dvfs_init_data_size;
189
190         /* use LDO6 for vibrator control */
191         int ldo6_vibrator;
192
193         bool enable_ldo8_tracking;
194         bool disabe_ldo8_tracking_suspend;
195         bool disable_smps10_boost_suspend;
196
197
198 };
199
200 struct palmas_rtc_platform_data {
201         unsigned enable_charging:1;
202         unsigned charging_current_ua;
203 };
204
205 struct palmas_gpadc_platform_data {
206         int channel0_current_uA;
207         int channel3_current_uA;
208 };
209
210 struct palmas_pinctrl_config {
211         int pin_name;
212         int pin_mux_option;
213         int open_drain_state;
214         int pin_pull_up_dn;
215 };
216
217 struct palmas_pinctrl_platform_data {
218         struct palmas_pinctrl_config *pincfg;
219         int num_pinctrl;
220         bool dvfs1_enable;
221         bool dvfs2_enable;
222 };
223
224 struct palmas_extcon_platform_data {
225         const char *connection_name;
226         bool enable_vbus_detection;
227         bool enable_id_pin_detection;
228 };
229
230 struct palmas_platform_data {
231         int gpio_base;
232         int irq_base;
233         int irq_type;
234
235         /* bit value to be loaded to the POWER_CTRL register */
236         u8 power_ctrl;
237
238         struct palmas_pmic_platform_data *pmic_pdata;
239         struct palmas_rtc_platform_data *rtc_pdata;
240         struct palmas_gpadc_platform_data *adc_pdata;
241
242         struct palmas_clk32k_init_data  *clk32k_init_data;
243         int clk32k_init_data_size;
244         bool use_power_off;
245
246         struct palmas_pinctrl_platform_data *pinctrl_pdata;
247         struct palmas_extcon_platform_data *extcon_pdata;
248
249         int watchdog_timer_initial_period;
250 };
251
252 /* Define the palmas IRQ numbers */
253 enum palmas_irqs {
254         /* INT1 registers */
255         PALMAS_CHARG_DET_N_VBUS_OVV_IRQ,
256         PALMAS_PWRON_IRQ,
257         PALMAS_LONG_PRESS_KEY_IRQ,
258         PALMAS_RPWRON_IRQ,
259         PALMAS_PWRDOWN_IRQ,
260         PALMAS_HOTDIE_IRQ,
261         PALMAS_VSYS_MON_IRQ,
262         PALMAS_VBAT_MON_IRQ,
263         /* INT2 registers */
264         PALMAS_RTC_ALARM_IRQ,
265         PALMAS_RTC_TIMER_IRQ,
266         PALMAS_WDT_IRQ,
267         PALMAS_BATREMOVAL_IRQ,
268         PALMAS_RESET_IN_IRQ,
269         PALMAS_FBI_BB_IRQ,
270         PALMAS_SHORT_IRQ,
271         PALMAS_VAC_ACOK_IRQ,
272         /* INT3 registers */
273         PALMAS_GPADC_AUTO_0_IRQ,
274         PALMAS_GPADC_AUTO_1_IRQ,
275         PALMAS_GPADC_EOC_SW_IRQ,
276         PALMAS_GPADC_EOC_RT_IRQ,
277         PALMAS_ID_OTG_IRQ,
278         PALMAS_ID_IRQ,
279         PALMAS_VBUS_OTG_IRQ,
280         PALMAS_VBUS_IRQ,
281         /* INT4 registers */
282         PALMAS_GPIO_0_IRQ,
283         PALMAS_GPIO_1_IRQ,
284         PALMAS_GPIO_2_IRQ,
285         PALMAS_GPIO_3_IRQ,
286         PALMAS_GPIO_4_IRQ,
287         PALMAS_GPIO_5_IRQ,
288         PALMAS_GPIO_6_IRQ,
289         PALMAS_GPIO_7_IRQ,
290         /* Total Number IRQs */
291         PALMAS_NUM_IRQ,
292 };
293
294 struct palmas_pmic {
295         struct palmas *palmas;
296         struct device *dev;
297         struct regulator_desc desc[PALMAS_NUM_REGS];
298         struct regulator_dev *rdev[PALMAS_NUM_REGS];
299         struct mutex mutex;
300
301         int smps123;
302         int smps457;
303
304         unsigned int ramp_delay[PALMAS_NUM_REGS];
305         unsigned int current_mode_reg[PALMAS_NUM_REGS];
306
307         int range[PALMAS_REG_SMPS10];
308 };
309
310 /* defines so we can store the mux settings */
311 #define PALMAS_GPIO_0_MUXED                                     (1 << 0)
312 #define PALMAS_GPIO_1_MUXED                                     (1 << 1)
313 #define PALMAS_GPIO_2_MUXED                                     (1 << 2)
314 #define PALMAS_GPIO_3_MUXED                                     (1 << 3)
315 #define PALMAS_GPIO_4_MUXED                                     (1 << 4)
316 #define PALMAS_GPIO_5_MUXED                                     (1 << 5)
317 #define PALMAS_GPIO_6_MUXED                                     (1 << 6)
318 #define PALMAS_GPIO_7_MUXED                                     (1 << 7)
319
320 #define PALMAS_LED1_MUXED                                       (1 << 0)
321 #define PALMAS_LED2_MUXED                                       (1 << 1)
322
323 #define PALMAS_PWM1_MUXED                                       (1 << 0)
324 #define PALMAS_PWM2_MUXED                                       (1 << 1)
325
326 /* helper macro to get correct slave number */
327 #define PALMAS_BASE_TO_SLAVE(x)         ((x >> 8) - 1)
328 #define PALMAS_BASE_TO_REG(x, y)        ((x & 0xff) + y)
329 #define RTC_SLAVE                       0
330
331 /* Base addresses of IP blocks in Palmas */
332 #define PALMAS_SMPS_DVS_BASE                                    0x20
333 #define PALMAS_RTC_BASE                                         0x100
334 #define PALMAS_VALIDITY_BASE                                    0x118
335 #define PALMAS_SMPS_BASE                                        0x120
336 #define PALMAS_LDO_BASE                                         0x150
337 #define PALMAS_DVFS_BASE                                        0x180
338 #define PALMAS_PMU_CONTROL_BASE                                 0x1A0
339 #define PALMAS_RESOURCE_BASE                                    0x1D4
340 #define PALMAS_PU_PD_OD_BASE                                    0x1F4
341 #define PALMAS_LED_BASE                                         0x200
342 #define PALMAS_INTERRUPT_BASE                                   0x210
343 #define PALMAS_USB_OTG_BASE                                     0x250
344 #define PALMAS_VIBRATOR_BASE                                    0x270
345 #define PALMAS_GPIO_BASE                                        0x280
346 #define PALMAS_USB_BASE                                         0x290
347 #define PALMAS_GPADC_BASE                                       0x2C0
348 #define PALMAS_TRIM_GPADC_BASE                                  0x3CD
349 #define PALMAS_PAGE3_BASE                                       0x300
350
351 /* Registers for function RTC */
352 #define PALMAS_SECONDS_REG                                      0x0
353 #define PALMAS_MINUTES_REG                                      0x1
354 #define PALMAS_HOURS_REG                                        0x2
355 #define PALMAS_DAYS_REG                                         0x3
356 #define PALMAS_MONTHS_REG                                       0x4
357 #define PALMAS_YEARS_REG                                        0x5
358 #define PALMAS_WEEKS_REG                                        0x6
359 #define PALMAS_ALARM_SECONDS_REG                                0x8
360 #define PALMAS_ALARM_MINUTES_REG                                0x9
361 #define PALMAS_ALARM_HOURS_REG                                  0xA
362 #define PALMAS_ALARM_DAYS_REG                                   0xB
363 #define PALMAS_ALARM_MONTHS_REG                                 0xC
364 #define PALMAS_ALARM_YEARS_REG                                  0xD
365 #define PALMAS_RTC_CTRL_REG                                     0x10
366 #define PALMAS_RTC_STATUS_REG                                   0x11
367 #define PALMAS_RTC_INTERRUPTS_REG                               0x12
368 #define PALMAS_RTC_COMP_LSB_REG                                 0x13
369 #define PALMAS_RTC_COMP_MSB_REG                                 0x14
370 #define PALMAS_RTC_RES_PROG_REG                                 0x15
371 #define PALMAS_RTC_RESET_STATUS_REG                             0x16
372
373 /* Bit definitions for SECONDS_REG */
374 #define PALMAS_SECONDS_REG_SEC1_MASK                            0x70
375 #define PALMAS_SECONDS_REG_SEC1_SHIFT                           4
376 #define PALMAS_SECONDS_REG_SEC0_MASK                            0x0f
377 #define PALMAS_SECONDS_REG_SEC0_SHIFT                           0
378
379 /* Bit definitions for MINUTES_REG */
380 #define PALMAS_MINUTES_REG_MIN1_MASK                            0x70
381 #define PALMAS_MINUTES_REG_MIN1_SHIFT                           4
382 #define PALMAS_MINUTES_REG_MIN0_MASK                            0x0f
383 #define PALMAS_MINUTES_REG_MIN0_SHIFT                           0
384
385 /* Bit definitions for HOURS_REG */
386 #define PALMAS_HOURS_REG_PM_NAM                                 0x80
387 #define PALMAS_HOURS_REG_PM_NAM_SHIFT                           7
388 #define PALMAS_HOURS_REG_HOUR1_MASK                             0x30
389 #define PALMAS_HOURS_REG_HOUR1_SHIFT                            4
390 #define PALMAS_HOURS_REG_HOUR0_MASK                             0x0f
391 #define PALMAS_HOURS_REG_HOUR0_SHIFT                            0
392
393 /* Bit definitions for DAYS_REG */
394 #define PALMAS_DAYS_REG_DAY1_MASK                               0x30
395 #define PALMAS_DAYS_REG_DAY1_SHIFT                              4
396 #define PALMAS_DAYS_REG_DAY0_MASK                               0x0f
397 #define PALMAS_DAYS_REG_DAY0_SHIFT                              0
398
399 /* Bit definitions for MONTHS_REG */
400 #define PALMAS_MONTHS_REG_MONTH1                                0x10
401 #define PALMAS_MONTHS_REG_MONTH1_SHIFT                          4
402 #define PALMAS_MONTHS_REG_MONTH0_MASK                           0x0f
403 #define PALMAS_MONTHS_REG_MONTH0_SHIFT                          0
404
405 /* Bit definitions for YEARS_REG */
406 #define PALMAS_YEARS_REG_YEAR1_MASK                             0xf0
407 #define PALMAS_YEARS_REG_YEAR1_SHIFT                            4
408 #define PALMAS_YEARS_REG_YEAR0_MASK                             0x0f
409 #define PALMAS_YEARS_REG_YEAR0_SHIFT                            0
410
411 /* Bit definitions for WEEKS_REG */
412 #define PALMAS_WEEKS_REG_WEEK_MASK                              0x07
413 #define PALMAS_WEEKS_REG_WEEK_SHIFT                             0
414
415 /* Bit definitions for ALARM_SECONDS_REG */
416 #define PALMAS_ALARM_SECONDS_REG_ALARM_SEC1_MASK                0x70
417 #define PALMAS_ALARM_SECONDS_REG_ALARM_SEC1_SHIFT               4
418 #define PALMAS_ALARM_SECONDS_REG_ALARM_SEC0_MASK                0x0f
419 #define PALMAS_ALARM_SECONDS_REG_ALARM_SEC0_SHIFT               0
420
421 /* Bit definitions for ALARM_MINUTES_REG */
422 #define PALMAS_ALARM_MINUTES_REG_ALARM_MIN1_MASK                0x70
423 #define PALMAS_ALARM_MINUTES_REG_ALARM_MIN1_SHIFT               4
424 #define PALMAS_ALARM_MINUTES_REG_ALARM_MIN0_MASK                0x0f
425 #define PALMAS_ALARM_MINUTES_REG_ALARM_MIN0_SHIFT               0
426
427 /* Bit definitions for ALARM_HOURS_REG */
428 #define PALMAS_ALARM_HOURS_REG_ALARM_PM_NAM                     0x80
429 #define PALMAS_ALARM_HOURS_REG_ALARM_PM_NAM_SHIFT               7
430 #define PALMAS_ALARM_HOURS_REG_ALARM_HOUR1_MASK                 0x30
431 #define PALMAS_ALARM_HOURS_REG_ALARM_HOUR1_SHIFT                4
432 #define PALMAS_ALARM_HOURS_REG_ALARM_HOUR0_MASK                 0x0f
433 #define PALMAS_ALARM_HOURS_REG_ALARM_HOUR0_SHIFT                0
434
435 /* Bit definitions for ALARM_DAYS_REG */
436 #define PALMAS_ALARM_DAYS_REG_ALARM_DAY1_MASK                   0x30
437 #define PALMAS_ALARM_DAYS_REG_ALARM_DAY1_SHIFT                  4
438 #define PALMAS_ALARM_DAYS_REG_ALARM_DAY0_MASK                   0x0f
439 #define PALMAS_ALARM_DAYS_REG_ALARM_DAY0_SHIFT                  0
440
441 /* Bit definitions for ALARM_MONTHS_REG */
442 #define PALMAS_ALARM_MONTHS_REG_ALARM_MONTH1                    0x10
443 #define PALMAS_ALARM_MONTHS_REG_ALARM_MONTH1_SHIFT              4
444 #define PALMAS_ALARM_MONTHS_REG_ALARM_MONTH0_MASK               0x0f
445 #define PALMAS_ALARM_MONTHS_REG_ALARM_MONTH0_SHIFT              0
446
447 /* Bit definitions for ALARM_YEARS_REG */
448 #define PALMAS_ALARM_YEARS_REG_ALARM_YEAR1_MASK                 0xf0
449 #define PALMAS_ALARM_YEARS_REG_ALARM_YEAR1_SHIFT                4
450 #define PALMAS_ALARM_YEARS_REG_ALARM_YEAR0_MASK                 0x0f
451 #define PALMAS_ALARM_YEARS_REG_ALARM_YEAR0_SHIFT                0
452
453 /* Bit definitions for RTC_CTRL_REG */
454 #define PALMAS_RTC_CTRL_REG_RTC_V_OPT                           0x80
455 #define PALMAS_RTC_CTRL_REG_RTC_V_OPT_SHIFT                     7
456 #define PALMAS_RTC_CTRL_REG_GET_TIME                            0x40
457 #define PALMAS_RTC_CTRL_REG_GET_TIME_SHIFT                      6
458 #define PALMAS_RTC_CTRL_REG_SET_32_COUNTER                      0x20
459 #define PALMAS_RTC_CTRL_REG_SET_32_COUNTER_SHIFT                5
460 #define PALMAS_RTC_CTRL_REG_TEST_MODE                           0x10
461 #define PALMAS_RTC_CTRL_REG_TEST_MODE_SHIFT                     4
462 #define PALMAS_RTC_CTRL_REG_MODE_12_24                          0x08
463 #define PALMAS_RTC_CTRL_REG_MODE_12_24_SHIFT                    3
464 #define PALMAS_RTC_CTRL_REG_AUTO_COMP                           0x04
465 #define PALMAS_RTC_CTRL_REG_AUTO_COMP_SHIFT                     2
466 #define PALMAS_RTC_CTRL_REG_ROUND_30S                           0x02
467 #define PALMAS_RTC_CTRL_REG_ROUND_30S_SHIFT                     1
468 #define PALMAS_RTC_CTRL_REG_STOP_RTC                            0x01
469 #define PALMAS_RTC_CTRL_REG_STOP_RTC_SHIFT                      0
470
471 /* Bit definitions for RTC_STATUS_REG */
472 #define PALMAS_RTC_STATUS_REG_POWER_UP                          0x80
473 #define PALMAS_RTC_STATUS_REG_POWER_UP_SHIFT                    7
474 #define PALMAS_RTC_STATUS_REG_ALARM                             0x40
475 #define PALMAS_RTC_STATUS_REG_ALARM_SHIFT                       6
476 #define PALMAS_RTC_STATUS_REG_EVENT_1D                          0x20
477 #define PALMAS_RTC_STATUS_REG_EVENT_1D_SHIFT                    5
478 #define PALMAS_RTC_STATUS_REG_EVENT_1H                          0x10
479 #define PALMAS_RTC_STATUS_REG_EVENT_1H_SHIFT                    4
480 #define PALMAS_RTC_STATUS_REG_EVENT_1M                          0x08
481 #define PALMAS_RTC_STATUS_REG_EVENT_1M_SHIFT                    3
482 #define PALMAS_RTC_STATUS_REG_EVENT_1S                          0x04
483 #define PALMAS_RTC_STATUS_REG_EVENT_1S_SHIFT                    2
484 #define PALMAS_RTC_STATUS_REG_RUN                               0x02
485 #define PALMAS_RTC_STATUS_REG_RUN_SHIFT                         1
486
487 /* Bit definitions for RTC_INTERRUPTS_REG */
488 #define PALMAS_RTC_INTERRUPTS_REG_IT_SLEEP_MASK_EN              0x10
489 #define PALMAS_RTC_INTERRUPTS_REG_IT_SLEEP_MASK_EN_SHIFT        4
490 #define PALMAS_RTC_INTERRUPTS_REG_IT_ALARM                      0x08
491 #define PALMAS_RTC_INTERRUPTS_REG_IT_ALARM_SHIFT                3
492 #define PALMAS_RTC_INTERRUPTS_REG_IT_TIMER                      0x04
493 #define PALMAS_RTC_INTERRUPTS_REG_IT_TIMER_SHIFT                2
494 #define PALMAS_RTC_INTERRUPTS_REG_EVERY_MASK                    0x03
495 #define PALMAS_RTC_INTERRUPTS_REG_EVERY_SHIFT                   0
496
497 /* Bit definitions for RTC_COMP_LSB_REG */
498 #define PALMAS_RTC_COMP_LSB_REG_RTC_COMP_LSB_MASK               0xff
499 #define PALMAS_RTC_COMP_LSB_REG_RTC_COMP_LSB_SHIFT              0
500
501 /* Bit definitions for RTC_COMP_MSB_REG */
502 #define PALMAS_RTC_COMP_MSB_REG_RTC_COMP_MSB_MASK               0xff
503 #define PALMAS_RTC_COMP_MSB_REG_RTC_COMP_MSB_SHIFT              0
504
505 /* Bit definitions for RTC_RES_PROG_REG */
506 #define PALMAS_RTC_RES_PROG_REG_SW_RES_PROG_MASK                0x3f
507 #define PALMAS_RTC_RES_PROG_REG_SW_RES_PROG_SHIFT               0
508
509 /* Bit definitions for RTC_RESET_STATUS_REG */
510 #define PALMAS_RTC_RESET_STATUS_REG_RESET_STATUS                0x01
511 #define PALMAS_RTC_RESET_STATUS_REG_RESET_STATUS_SHIFT          0
512
513 /* Registers for function BACKUP */
514 #define PALMAS_BACKUP0                                          0x0
515 #define PALMAS_BACKUP1                                          0x1
516 #define PALMAS_BACKUP2                                          0x2
517 #define PALMAS_BACKUP3                                          0x3
518 #define PALMAS_BACKUP4                                          0x4
519 #define PALMAS_BACKUP5                                          0x5
520 #define PALMAS_BACKUP6                                          0x6
521 #define PALMAS_BACKUP7                                          0x7
522
523 /* Bit definitions for BACKUP0 */
524 #define PALMAS_BACKUP0_BACKUP_MASK                              0xff
525 #define PALMAS_BACKUP0_BACKUP_SHIFT                             0
526
527 /* Bit definitions for BACKUP1 */
528 #define PALMAS_BACKUP1_BACKUP_MASK                              0xff
529 #define PALMAS_BACKUP1_BACKUP_SHIFT                             0
530
531 /* Bit definitions for BACKUP2 */
532 #define PALMAS_BACKUP2_BACKUP_MASK                              0xff
533 #define PALMAS_BACKUP2_BACKUP_SHIFT                             0
534
535 /* Bit definitions for BACKUP3 */
536 #define PALMAS_BACKUP3_BACKUP_MASK                              0xff
537 #define PALMAS_BACKUP3_BACKUP_SHIFT                             0
538
539 /* Bit definitions for BACKUP4 */
540 #define PALMAS_BACKUP4_BACKUP_MASK                              0xff
541 #define PALMAS_BACKUP4_BACKUP_SHIFT                             0
542
543 /* Bit definitions for BACKUP5 */
544 #define PALMAS_BACKUP5_BACKUP_MASK                              0xff
545 #define PALMAS_BACKUP5_BACKUP_SHIFT                             0
546
547 /* Bit definitions for BACKUP6 */
548 #define PALMAS_BACKUP6_BACKUP_MASK                              0xff
549 #define PALMAS_BACKUP6_BACKUP_SHIFT                             0
550
551 /* Bit definitions for BACKUP7 */
552 #define PALMAS_BACKUP7_BACKUP_MASK                              0xff
553 #define PALMAS_BACKUP7_BACKUP_SHIFT                             0
554
555 /* Registers for function SMPS */
556 #define PALMAS_SMPS12_CTRL                                      0x0
557 #define PALMAS_SMPS12_TSTEP                                     0x1
558 #define PALMAS_SMPS12_FORCE                                     0x2
559 #define PALMAS_SMPS12_VOLTAGE                                   0x3
560 #define PALMAS_SMPS3_CTRL                                       0x4
561 #define PALMAS_SMPS3_VOLTAGE                                    0x7
562 #define PALMAS_SMPS45_CTRL                                      0x8
563 #define PALMAS_SMPS45_TSTEP                                     0x9
564 #define PALMAS_SMPS45_FORCE                                     0xA
565 #define PALMAS_SMPS45_VOLTAGE                                   0xB
566 #define PALMAS_SMPS6_CTRL                                       0xC
567 #define PALMAS_SMPS6_TSTEP                                      0xD
568 #define PALMAS_SMPS6_FORCE                                      0xE
569 #define PALMAS_SMPS6_VOLTAGE                                    0xF
570 #define PALMAS_SMPS7_CTRL                                       0x10
571 #define PALMAS_SMPS7_VOLTAGE                                    0x13
572 #define PALMAS_SMPS8_CTRL                                       0x14
573 #define PALMAS_SMPS8_TSTEP                                      0x15
574 #define PALMAS_SMPS8_FORCE                                      0x16
575 #define PALMAS_SMPS8_VOLTAGE                                    0x17
576 #define PALMAS_SMPS9_CTRL                                       0x18
577 #define PALMAS_SMPS9_VOLTAGE                                    0x1B
578 #define PALMAS_SMPS10_CTRL                                      0x1C
579 #define PALMAS_SMPS10_STATUS                                    0x1F
580 #define PALMAS_SMPS_CTRL                                        0x24
581 #define PALMAS_SMPS_PD_CTRL                                     0x25
582 #define PALMAS_SMPS_DITHER_EN                                   0x26
583 #define PALMAS_SMPS_THERMAL_EN                                  0x27
584 #define PALMAS_SMPS_THERMAL_STATUS                              0x28
585 #define PALMAS_SMPS_SHORT_STATUS                                0x29
586 #define PALMAS_SMPS_NEGATIVE_CURRENT_LIMIT_EN                   0x2A
587 #define PALMAS_SMPS_POWERGOOD_MASK1                             0x2B
588 #define PALMAS_SMPS_POWERGOOD_MASK2                             0x2C
589
590 /* Bit definitions for SMPS12_CTRL */
591 #define PALMAS_SMPS12_CTRL_WR_S                                 0x80
592 #define PALMAS_SMPS12_CTRL_WR_S_SHIFT                           7
593 #define PALMAS_SMPS12_CTRL_ROOF_FLOOR_EN                        0x40
594 #define PALMAS_SMPS12_CTRL_ROOF_FLOOR_EN_SHIFT                  6
595 #define PALMAS_SMPS12_CTRL_STATUS_MASK                          0x30
596 #define PALMAS_SMPS12_CTRL_STATUS_SHIFT                         4
597 #define PALMAS_SMPS12_CTRL_MODE_SLEEP_MASK                      0x0c
598 #define PALMAS_SMPS12_CTRL_MODE_SLEEP_SHIFT                     2
599 #define PALMAS_SMPS12_CTRL_MODE_ACTIVE_MASK                     0x03
600 #define PALMAS_SMPS12_CTRL_MODE_ACTIVE_SHIFT                    0
601
602 /* Bit definitions for SMPS12_TSTEP */
603 #define PALMAS_SMPS12_TSTEP_TSTEP_MASK                          0x03
604 #define PALMAS_SMPS12_TSTEP_TSTEP_SHIFT                         0
605
606 /* Bit definitions for SMPS12_FORCE */
607 #define PALMAS_SMPS12_FORCE_CMD                                 0x80
608 #define PALMAS_SMPS12_FORCE_CMD_SHIFT                           7
609 #define PALMAS_SMPS12_FORCE_VSEL_MASK                           0x7f
610 #define PALMAS_SMPS12_FORCE_VSEL_SHIFT                          0
611
612 /* Bit definitions for SMPS12_VOLTAGE */
613 #define PALMAS_SMPS12_VOLTAGE_RANGE                             0x80
614 #define PALMAS_SMPS12_VOLTAGE_RANGE_SHIFT                       7
615 #define PALMAS_SMPS12_VOLTAGE_VSEL_MASK                         0x7f
616 #define PALMAS_SMPS12_VOLTAGE_VSEL_SHIFT                        0
617
618 /* Bit definitions for SMPS3_CTRL */
619 #define PALMAS_SMPS3_CTRL_WR_S                                  0x80
620 #define PALMAS_SMPS3_CTRL_WR_S_SHIFT                            7
621 #define PALMAS_SMPS3_CTRL_STATUS_MASK                           0x30
622 #define PALMAS_SMPS3_CTRL_STATUS_SHIFT                          4
623 #define PALMAS_SMPS3_CTRL_MODE_SLEEP_MASK                       0x0c
624 #define PALMAS_SMPS3_CTRL_MODE_SLEEP_SHIFT                      2
625 #define PALMAS_SMPS3_CTRL_MODE_ACTIVE_MASK                      0x03
626 #define PALMAS_SMPS3_CTRL_MODE_ACTIVE_SHIFT                     0
627
628 /* Bit definitions for SMPS3_VOLTAGE */
629 #define PALMAS_SMPS3_VOLTAGE_RANGE                              0x80
630 #define PALMAS_SMPS3_VOLTAGE_RANGE_SHIFT                        7
631 #define PALMAS_SMPS3_VOLTAGE_VSEL_MASK                          0x7f
632 #define PALMAS_SMPS3_VOLTAGE_VSEL_SHIFT                         0
633
634 /* Bit definitions for SMPS45_CTRL */
635 #define PALMAS_SMPS45_CTRL_WR_S                                 0x80
636 #define PALMAS_SMPS45_CTRL_WR_S_SHIFT                           7
637 #define PALMAS_SMPS45_CTRL_ROOF_FLOOR_EN                        0x40
638 #define PALMAS_SMPS45_CTRL_ROOF_FLOOR_EN_SHIFT                  6
639 #define PALMAS_SMPS45_CTRL_STATUS_MASK                          0x30
640 #define PALMAS_SMPS45_CTRL_STATUS_SHIFT                         4
641 #define PALMAS_SMPS45_CTRL_MODE_SLEEP_MASK                      0x0c
642 #define PALMAS_SMPS45_CTRL_MODE_SLEEP_SHIFT                     2
643 #define PALMAS_SMPS45_CTRL_MODE_ACTIVE_MASK                     0x03
644 #define PALMAS_SMPS45_CTRL_MODE_ACTIVE_SHIFT                    0
645
646 /* Bit definitions for SMPS45_TSTEP */
647 #define PALMAS_SMPS45_TSTEP_TSTEP_MASK                          0x03
648 #define PALMAS_SMPS45_TSTEP_TSTEP_SHIFT                         0
649
650 /* Bit definitions for SMPS45_FORCE */
651 #define PALMAS_SMPS45_FORCE_CMD                                 0x80
652 #define PALMAS_SMPS45_FORCE_CMD_SHIFT                           7
653 #define PALMAS_SMPS45_FORCE_VSEL_MASK                           0x7f
654 #define PALMAS_SMPS45_FORCE_VSEL_SHIFT                          0
655
656 /* Bit definitions for SMPS45_VOLTAGE */
657 #define PALMAS_SMPS45_VOLTAGE_RANGE                             0x80
658 #define PALMAS_SMPS45_VOLTAGE_RANGE_SHIFT                       7
659 #define PALMAS_SMPS45_VOLTAGE_VSEL_MASK                         0x7f
660 #define PALMAS_SMPS45_VOLTAGE_VSEL_SHIFT                        0
661
662 /* Bit definitions for SMPS6_CTRL */
663 #define PALMAS_SMPS6_CTRL_WR_S                                  0x80
664 #define PALMAS_SMPS6_CTRL_WR_S_SHIFT                            7
665 #define PALMAS_SMPS6_CTRL_ROOF_FLOOR_EN                         0x40
666 #define PALMAS_SMPS6_CTRL_ROOF_FLOOR_EN_SHIFT                   6
667 #define PALMAS_SMPS6_CTRL_STATUS_MASK                           0x30
668 #define PALMAS_SMPS6_CTRL_STATUS_SHIFT                          4
669 #define PALMAS_SMPS6_CTRL_MODE_SLEEP_MASK                       0x0c
670 #define PALMAS_SMPS6_CTRL_MODE_SLEEP_SHIFT                      2
671 #define PALMAS_SMPS6_CTRL_MODE_ACTIVE_MASK                      0x03
672 #define PALMAS_SMPS6_CTRL_MODE_ACTIVE_SHIFT                     0
673
674 /* Bit definitions for SMPS6_TSTEP */
675 #define PALMAS_SMPS6_TSTEP_TSTEP_MASK                           0x03
676 #define PALMAS_SMPS6_TSTEP_TSTEP_SHIFT                          0
677
678 /* Bit definitions for SMPS6_FORCE */
679 #define PALMAS_SMPS6_FORCE_CMD                                  0x80
680 #define PALMAS_SMPS6_FORCE_CMD_SHIFT                            7
681 #define PALMAS_SMPS6_FORCE_VSEL_MASK                            0x7f
682 #define PALMAS_SMPS6_FORCE_VSEL_SHIFT                           0
683
684 /* Bit definitions for SMPS6_VOLTAGE */
685 #define PALMAS_SMPS6_VOLTAGE_RANGE                              0x80
686 #define PALMAS_SMPS6_VOLTAGE_RANGE_SHIFT                        7
687 #define PALMAS_SMPS6_VOLTAGE_VSEL_MASK                          0x7f
688 #define PALMAS_SMPS6_VOLTAGE_VSEL_SHIFT                         0
689
690 /* Bit definitions for SMPS7_CTRL */
691 #define PALMAS_SMPS7_CTRL_WR_S                                  0x80
692 #define PALMAS_SMPS7_CTRL_WR_S_SHIFT                            7
693 #define PALMAS_SMPS7_CTRL_STATUS_MASK                           0x30
694 #define PALMAS_SMPS7_CTRL_STATUS_SHIFT                          4
695 #define PALMAS_SMPS7_CTRL_MODE_SLEEP_MASK                       0x0c
696 #define PALMAS_SMPS7_CTRL_MODE_SLEEP_SHIFT                      2
697 #define PALMAS_SMPS7_CTRL_MODE_ACTIVE_MASK                      0x03
698 #define PALMAS_SMPS7_CTRL_MODE_ACTIVE_SHIFT                     0
699
700 /* Bit definitions for SMPS7_VOLTAGE */
701 #define PALMAS_SMPS7_VOLTAGE_RANGE                              0x80
702 #define PALMAS_SMPS7_VOLTAGE_RANGE_SHIFT                        7
703 #define PALMAS_SMPS7_VOLTAGE_VSEL_MASK                          0x7f
704 #define PALMAS_SMPS7_VOLTAGE_VSEL_SHIFT                         0
705
706 /* Bit definitions for SMPS8_CTRL */
707 #define PALMAS_SMPS8_CTRL_WR_S                                  0x80
708 #define PALMAS_SMPS8_CTRL_WR_S_SHIFT                            7
709 #define PALMAS_SMPS8_CTRL_ROOF_FLOOR_EN                         0x40
710 #define PALMAS_SMPS8_CTRL_ROOF_FLOOR_EN_SHIFT                   6
711 #define PALMAS_SMPS8_CTRL_STATUS_MASK                           0x30
712 #define PALMAS_SMPS8_CTRL_STATUS_SHIFT                          4
713 #define PALMAS_SMPS8_CTRL_MODE_SLEEP_MASK                       0x0c
714 #define PALMAS_SMPS8_CTRL_MODE_SLEEP_SHIFT                      2
715 #define PALMAS_SMPS8_CTRL_MODE_ACTIVE_MASK                      0x03
716 #define PALMAS_SMPS8_CTRL_MODE_ACTIVE_SHIFT                     0
717
718 /* Bit definitions for SMPS8_TSTEP */
719 #define PALMAS_SMPS8_TSTEP_TSTEP_MASK                           0x03
720 #define PALMAS_SMPS8_TSTEP_TSTEP_SHIFT                          0
721
722 /* Bit definitions for SMPS8_FORCE */
723 #define PALMAS_SMPS8_FORCE_CMD                                  0x80
724 #define PALMAS_SMPS8_FORCE_CMD_SHIFT                            7
725 #define PALMAS_SMPS8_FORCE_VSEL_MASK                            0x7f
726 #define PALMAS_SMPS8_FORCE_VSEL_SHIFT                           0
727
728 /* Bit definitions for SMPS8_VOLTAGE */
729 #define PALMAS_SMPS8_VOLTAGE_RANGE                              0x80
730 #define PALMAS_SMPS8_VOLTAGE_RANGE_SHIFT                        7
731 #define PALMAS_SMPS8_VOLTAGE_VSEL_MASK                          0x7f
732 #define PALMAS_SMPS8_VOLTAGE_VSEL_SHIFT                         0
733
734 /* Bit definitions for SMPS9_CTRL */
735 #define PALMAS_SMPS9_CTRL_WR_S                                  0x80
736 #define PALMAS_SMPS9_CTRL_WR_S_SHIFT                            7
737 #define PALMAS_SMPS9_CTRL_STATUS_MASK                           0x30
738 #define PALMAS_SMPS9_CTRL_STATUS_SHIFT                          4
739 #define PALMAS_SMPS9_CTRL_MODE_SLEEP_MASK                       0x0c
740 #define PALMAS_SMPS9_CTRL_MODE_SLEEP_SHIFT                      2
741 #define PALMAS_SMPS9_CTRL_MODE_ACTIVE_MASK                      0x03
742 #define PALMAS_SMPS9_CTRL_MODE_ACTIVE_SHIFT                     0
743
744 /* Bit definitions for SMPS9_VOLTAGE */
745 #define PALMAS_SMPS9_VOLTAGE_RANGE                              0x80
746 #define PALMAS_SMPS9_VOLTAGE_RANGE_SHIFT                        7
747 #define PALMAS_SMPS9_VOLTAGE_VSEL_MASK                          0x7f
748 #define PALMAS_SMPS9_VOLTAGE_VSEL_SHIFT                         0
749
750 /* Bit definitions for SMPS10_CTRL */
751 #define PALMAS_SMPS10_CTRL_MODE_SLEEP_MASK                      0xf0
752 #define PALMAS_SMPS10_CTRL_MODE_SLEEP_SHIFT                     4
753 #define PALMAS_SMPS10_CTRL_MODE_ACTIVE_MASK                     0x0f
754 #define PALMAS_SMPS10_CTRL_MODE_ACTIVE_SHIFT                    0
755
756 /* Bit definitions for SMPS10_STATUS */
757 #define PALMAS_SMPS10_STATUS_STATUS_MASK                        0x0f
758 #define PALMAS_SMPS10_STATUS_STATUS_SHIFT                       0
759
760 /* Bit definitions for SMPS_CTRL */
761 #define PALMAS_SMPS_CTRL_SMPS45_SMPS457_EN                      0x20
762 #define PALMAS_SMPS_CTRL_SMPS45_SMPS457_EN_SHIFT                5
763 #define PALMAS_SMPS_CTRL_SMPS12_SMPS123_EN                      0x10
764 #define PALMAS_SMPS_CTRL_SMPS12_SMPS123_EN_SHIFT                4
765 #define PALMAS_SMPS_CTRL_SMPS45_PHASE_CTRL_MASK                 0x0c
766 #define PALMAS_SMPS_CTRL_SMPS45_PHASE_CTRL_SHIFT                2
767 #define PALMAS_SMPS_CTRL_SMPS123_PHASE_CTRL_MASK                0x03
768 #define PALMAS_SMPS_CTRL_SMPS123_PHASE_CTRL_SHIFT               0
769
770 /* Bit definitions for SMPS_PD_CTRL */
771 #define PALMAS_SMPS_PD_CTRL_SMPS9                               0x40
772 #define PALMAS_SMPS_PD_CTRL_SMPS9_SHIFT                         6
773 #define PALMAS_SMPS_PD_CTRL_SMPS8                               0x20
774 #define PALMAS_SMPS_PD_CTRL_SMPS8_SHIFT                         5
775 #define PALMAS_SMPS_PD_CTRL_SMPS7                               0x10
776 #define PALMAS_SMPS_PD_CTRL_SMPS7_SHIFT                         4
777 #define PALMAS_SMPS_PD_CTRL_SMPS6                               0x08
778 #define PALMAS_SMPS_PD_CTRL_SMPS6_SHIFT                         3
779 #define PALMAS_SMPS_PD_CTRL_SMPS45                              0x04
780 #define PALMAS_SMPS_PD_CTRL_SMPS45_SHIFT                        2
781 #define PALMAS_SMPS_PD_CTRL_SMPS3                               0x02
782 #define PALMAS_SMPS_PD_CTRL_SMPS3_SHIFT                         1
783 #define PALMAS_SMPS_PD_CTRL_SMPS12                              0x01
784 #define PALMAS_SMPS_PD_CTRL_SMPS12_SHIFT                        0
785
786 /* Bit definitions for SMPS_THERMAL_EN */
787 #define PALMAS_SMPS_THERMAL_EN_SMPS9                            0x40
788 #define PALMAS_SMPS_THERMAL_EN_SMPS9_SHIFT                      6
789 #define PALMAS_SMPS_THERMAL_EN_SMPS8                            0x20
790 #define PALMAS_SMPS_THERMAL_EN_SMPS8_SHIFT                      5
791 #define PALMAS_SMPS_THERMAL_EN_SMPS6                            0x08
792 #define PALMAS_SMPS_THERMAL_EN_SMPS6_SHIFT                      3
793 #define PALMAS_SMPS_THERMAL_EN_SMPS457                          0x04
794 #define PALMAS_SMPS_THERMAL_EN_SMPS457_SHIFT                    2
795 #define PALMAS_SMPS_THERMAL_EN_SMPS123                          0x01
796 #define PALMAS_SMPS_THERMAL_EN_SMPS123_SHIFT                    0
797
798 /* Bit definitions for SMPS_THERMAL_STATUS */
799 #define PALMAS_SMPS_THERMAL_STATUS_SMPS9                        0x40
800 #define PALMAS_SMPS_THERMAL_STATUS_SMPS9_SHIFT                  6
801 #define PALMAS_SMPS_THERMAL_STATUS_SMPS8                        0x20
802 #define PALMAS_SMPS_THERMAL_STATUS_SMPS8_SHIFT                  5
803 #define PALMAS_SMPS_THERMAL_STATUS_SMPS6                        0x08
804 #define PALMAS_SMPS_THERMAL_STATUS_SMPS6_SHIFT                  3
805 #define PALMAS_SMPS_THERMAL_STATUS_SMPS457                      0x04
806 #define PALMAS_SMPS_THERMAL_STATUS_SMPS457_SHIFT                2
807 #define PALMAS_SMPS_THERMAL_STATUS_SMPS123                      0x01
808 #define PALMAS_SMPS_THERMAL_STATUS_SMPS123_SHIFT                0
809
810 /* Bit definitions for SMPS_SHORT_STATUS */
811 #define PALMAS_SMPS_SHORT_STATUS_SMPS10                         0x80
812 #define PALMAS_SMPS_SHORT_STATUS_SMPS10_SHIFT                   7
813 #define PALMAS_SMPS_SHORT_STATUS_SMPS9                          0x40
814 #define PALMAS_SMPS_SHORT_STATUS_SMPS9_SHIFT                    6
815 #define PALMAS_SMPS_SHORT_STATUS_SMPS8                          0x20
816 #define PALMAS_SMPS_SHORT_STATUS_SMPS8_SHIFT                    5
817 #define PALMAS_SMPS_SHORT_STATUS_SMPS7                          0x10
818 #define PALMAS_SMPS_SHORT_STATUS_SMPS7_SHIFT                    4
819 #define PALMAS_SMPS_SHORT_STATUS_SMPS6                          0x08
820 #define PALMAS_SMPS_SHORT_STATUS_SMPS6_SHIFT                    3
821 #define PALMAS_SMPS_SHORT_STATUS_SMPS45                         0x04
822 #define PALMAS_SMPS_SHORT_STATUS_SMPS45_SHIFT                   2
823 #define PALMAS_SMPS_SHORT_STATUS_SMPS3                          0x02
824 #define PALMAS_SMPS_SHORT_STATUS_SMPS3_SHIFT                    1
825 #define PALMAS_SMPS_SHORT_STATUS_SMPS12                         0x01
826 #define PALMAS_SMPS_SHORT_STATUS_SMPS12_SHIFT                   0
827
828 /* Bit definitions for SMPS_NEGATIVE_CURRENT_LIMIT_EN */
829 #define PALMAS_SMPS_NEGATIVE_CURRENT_LIMIT_EN_SMPS9             0x40
830 #define PALMAS_SMPS_NEGATIVE_CURRENT_LIMIT_EN_SMPS9_SHIFT       6
831 #define PALMAS_SMPS_NEGATIVE_CURRENT_LIMIT_EN_SMPS8             0x20
832 #define PALMAS_SMPS_NEGATIVE_CURRENT_LIMIT_EN_SMPS8_SHIFT       5
833 #define PALMAS_SMPS_NEGATIVE_CURRENT_LIMIT_EN_SMPS7             0x10
834 #define PALMAS_SMPS_NEGATIVE_CURRENT_LIMIT_EN_SMPS7_SHIFT       4
835 #define PALMAS_SMPS_NEGATIVE_CURRENT_LIMIT_EN_SMPS6             0x08
836 #define PALMAS_SMPS_NEGATIVE_CURRENT_LIMIT_EN_SMPS6_SHIFT       3
837 #define PALMAS_SMPS_NEGATIVE_CURRENT_LIMIT_EN_SMPS45            0x04
838 #define PALMAS_SMPS_NEGATIVE_CURRENT_LIMIT_EN_SMPS45_SHIFT      2
839 #define PALMAS_SMPS_NEGATIVE_CURRENT_LIMIT_EN_SMPS3             0x02
840 #define PALMAS_SMPS_NEGATIVE_CURRENT_LIMIT_EN_SMPS3_SHIFT       1
841 #define PALMAS_SMPS_NEGATIVE_CURRENT_LIMIT_EN_SMPS12            0x01
842 #define PALMAS_SMPS_NEGATIVE_CURRENT_LIMIT_EN_SMPS12_SHIFT      0
843
844 /* Bit definitions for SMPS_POWERGOOD_MASK1 */
845 #define PALMAS_SMPS_POWERGOOD_MASK1_SMPS10                      0x80
846 #define PALMAS_SMPS_POWERGOOD_MASK1_SMPS10_SHIFT                7
847 #define PALMAS_SMPS_POWERGOOD_MASK1_SMPS9                       0x40
848 #define PALMAS_SMPS_POWERGOOD_MASK1_SMPS9_SHIFT                 6
849 #define PALMAS_SMPS_POWERGOOD_MASK1_SMPS8                       0x20
850 #define PALMAS_SMPS_POWERGOOD_MASK1_SMPS8_SHIFT                 5
851 #define PALMAS_SMPS_POWERGOOD_MASK1_SMPS7                       0x10
852 #define PALMAS_SMPS_POWERGOOD_MASK1_SMPS7_SHIFT                 4
853 #define PALMAS_SMPS_POWERGOOD_MASK1_SMPS6                       0x08
854 #define PALMAS_SMPS_POWERGOOD_MASK1_SMPS6_SHIFT                 3
855 #define PALMAS_SMPS_POWERGOOD_MASK1_SMPS45                      0x04
856 #define PALMAS_SMPS_POWERGOOD_MASK1_SMPS45_SHIFT                2
857 #define PALMAS_SMPS_POWERGOOD_MASK1_SMPS3                       0x02
858 #define PALMAS_SMPS_POWERGOOD_MASK1_SMPS3_SHIFT                 1
859 #define PALMAS_SMPS_POWERGOOD_MASK1_SMPS12                      0x01
860 #define PALMAS_SMPS_POWERGOOD_MASK1_SMPS12_SHIFT                0
861
862 /* Bit definitions for SMPS_POWERGOOD_MASK2 */
863 #define PALMAS_SMPS_POWERGOOD_MASK2_POWERGOOD_TYPE_SELECT       0x80
864 #define PALMAS_SMPS_POWERGOOD_MASK2_POWERGOOD_TYPE_SELECT_SHIFT 7
865 #define PALMAS_SMPS_POWERGOOD_MASK2_GPIO_7                      0x04
866 #define PALMAS_SMPS_POWERGOOD_MASK2_GPIO_7_SHIFT                2
867 #define PALMAS_SMPS_POWERGOOD_MASK2_VBUS                        0x02
868 #define PALMAS_SMPS_POWERGOOD_MASK2_VBUS_SHIFT                  1
869 #define PALMAS_SMPS_POWERGOOD_MASK2_ACOK                        0x01
870 #define PALMAS_SMPS_POWERGOOD_MASK2_ACOK_SHIFT                  0
871
872 /* Registers for function LDO */
873 #define PALMAS_LDO1_CTRL                                        0x0
874 #define PALMAS_LDO1_VOLTAGE                                     0x1
875 #define PALMAS_LDO2_CTRL                                        0x2
876 #define PALMAS_LDO2_VOLTAGE                                     0x3
877 #define PALMAS_LDO3_CTRL                                        0x4
878 #define PALMAS_LDO3_VOLTAGE                                     0x5
879 #define PALMAS_LDO4_CTRL                                        0x6
880 #define PALMAS_LDO4_VOLTAGE                                     0x7
881 #define PALMAS_LDO5_CTRL                                        0x8
882 #define PALMAS_LDO5_VOLTAGE                                     0x9
883 #define PALMAS_LDO6_CTRL                                        0xA
884 #define PALMAS_LDO6_VOLTAGE                                     0xB
885 #define PALMAS_LDO7_CTRL                                        0xC
886 #define PALMAS_LDO7_VOLTAGE                                     0xD
887 #define PALMAS_LDO8_CTRL                                        0xE
888 #define PALMAS_LDO8_VOLTAGE                                     0xF
889 #define PALMAS_LDO9_CTRL                                        0x10
890 #define PALMAS_LDO9_VOLTAGE                                     0x11
891 #define PALMAS_LDOLN_CTRL                                       0x12
892 #define PALMAS_LDOLN_VOLTAGE                                    0x13
893 #define PALMAS_LDOUSB_CTRL                                      0x14
894 #define PALMAS_LDOUSB_VOLTAGE                                   0x15
895 #define PALMAS_LDO_CTRL                                         0x1A
896 #define PALMAS_LDO_PD_CTRL1                                     0x1B
897 #define PALMAS_LDO_PD_CTRL2                                     0x1C
898 #define PALMAS_LDO_SHORT_STATUS1                                0x1D
899 #define PALMAS_LDO_SHORT_STATUS2                                0x1E
900
901 /* Bit definitions for LDO1_CTRL */
902 #define PALMAS_LDO1_CTRL_WR_S                                   0x80
903 #define PALMAS_LDO1_CTRL_WR_S_SHIFT                             7
904 #define PALMAS_LDO1_CTRL_STATUS                                 0x10
905 #define PALMAS_LDO1_CTRL_STATUS_SHIFT                           4
906 #define PALMAS_LDO1_CTRL_MODE_SLEEP                             0x04
907 #define PALMAS_LDO1_CTRL_MODE_SLEEP_SHIFT                       2
908 #define PALMAS_LDO1_CTRL_MODE_ACTIVE                            0x01
909 #define PALMAS_LDO1_CTRL_MODE_ACTIVE_SHIFT                      0
910
911 /* Bit definitions for LDO1_VOLTAGE */
912 #define PALMAS_LDO1_VOLTAGE_VSEL_MASK                           0x3f
913 #define PALMAS_LDO1_VOLTAGE_VSEL_SHIFT                          0
914
915 /* Bit definitions for LDO2_CTRL */
916 #define PALMAS_LDO2_CTRL_WR_S                                   0x80
917 #define PALMAS_LDO2_CTRL_WR_S_SHIFT                             7
918 #define PALMAS_LDO2_CTRL_STATUS                                 0x10
919 #define PALMAS_LDO2_CTRL_STATUS_SHIFT                           4
920 #define PALMAS_LDO2_CTRL_MODE_SLEEP                             0x04
921 #define PALMAS_LDO2_CTRL_MODE_SLEEP_SHIFT                       2
922 #define PALMAS_LDO2_CTRL_MODE_ACTIVE                            0x01
923 #define PALMAS_LDO2_CTRL_MODE_ACTIVE_SHIFT                      0
924
925 /* Bit definitions for LDO2_VOLTAGE */
926 #define PALMAS_LDO2_VOLTAGE_VSEL_MASK                           0x3f
927 #define PALMAS_LDO2_VOLTAGE_VSEL_SHIFT                          0
928
929 /* Bit definitions for LDO3_CTRL */
930 #define PALMAS_LDO3_CTRL_WR_S                                   0x80
931 #define PALMAS_LDO3_CTRL_WR_S_SHIFT                             7
932 #define PALMAS_LDO3_CTRL_STATUS                                 0x10
933 #define PALMAS_LDO3_CTRL_STATUS_SHIFT                           4
934 #define PALMAS_LDO3_CTRL_MODE_SLEEP                             0x04
935 #define PALMAS_LDO3_CTRL_MODE_SLEEP_SHIFT                       2
936 #define PALMAS_LDO3_CTRL_MODE_ACTIVE                            0x01
937 #define PALMAS_LDO3_CTRL_MODE_ACTIVE_SHIFT                      0
938
939 /* Bit definitions for LDO3_VOLTAGE */
940 #define PALMAS_LDO3_VOLTAGE_VSEL_MASK                           0x3f
941 #define PALMAS_LDO3_VOLTAGE_VSEL_SHIFT                          0
942
943 /* Bit definitions for LDO4_CTRL */
944 #define PALMAS_LDO4_CTRL_WR_S                                   0x80
945 #define PALMAS_LDO4_CTRL_WR_S_SHIFT                             7
946 #define PALMAS_LDO4_CTRL_STATUS                                 0x10
947 #define PALMAS_LDO4_CTRL_STATUS_SHIFT                           4
948 #define PALMAS_LDO4_CTRL_MODE_SLEEP                             0x04
949 #define PALMAS_LDO4_CTRL_MODE_SLEEP_SHIFT                       2
950 #define PALMAS_LDO4_CTRL_MODE_ACTIVE                            0x01
951 #define PALMAS_LDO4_CTRL_MODE_ACTIVE_SHIFT                      0
952
953 /* Bit definitions for LDO4_VOLTAGE */
954 #define PALMAS_LDO4_VOLTAGE_VSEL_MASK                           0x3f
955 #define PALMAS_LDO4_VOLTAGE_VSEL_SHIFT                          0
956
957 /* Bit definitions for LDO5_CTRL */
958 #define PALMAS_LDO5_CTRL_WR_S                                   0x80
959 #define PALMAS_LDO5_CTRL_WR_S_SHIFT                             7
960 #define PALMAS_LDO5_CTRL_STATUS                                 0x10
961 #define PALMAS_LDO5_CTRL_STATUS_SHIFT                           4
962 #define PALMAS_LDO5_CTRL_MODE_SLEEP                             0x04
963 #define PALMAS_LDO5_CTRL_MODE_SLEEP_SHIFT                       2
964 #define PALMAS_LDO5_CTRL_MODE_ACTIVE                            0x01
965 #define PALMAS_LDO5_CTRL_MODE_ACTIVE_SHIFT                      0
966
967 /* Bit definitions for LDO5_VOLTAGE */
968 #define PALMAS_LDO5_VOLTAGE_VSEL_MASK                           0x3f
969 #define PALMAS_LDO5_VOLTAGE_VSEL_SHIFT                          0
970
971 /* Bit definitions for LDO6_CTRL */
972 #define PALMAS_LDO6_CTRL_WR_S                                   0x80
973 #define PALMAS_LDO6_CTRL_WR_S_SHIFT                             7
974 #define PALMAS_LDO6_CTRL_LDO_VIB_EN                             0x40
975 #define PALMAS_LDO6_CTRL_LDO_VIB_EN_SHIFT                       6
976 #define PALMAS_LDO6_CTRL_STATUS                                 0x10
977 #define PALMAS_LDO6_CTRL_STATUS_SHIFT                           4
978 #define PALMAS_LDO6_CTRL_MODE_SLEEP                             0x04
979 #define PALMAS_LDO6_CTRL_MODE_SLEEP_SHIFT                       2
980 #define PALMAS_LDO6_CTRL_MODE_ACTIVE                            0x01
981 #define PALMAS_LDO6_CTRL_MODE_ACTIVE_SHIFT                      0
982
983 /* Bit definitions for LDO6_VOLTAGE */
984 #define PALMAS_LDO6_VOLTAGE_VSEL_MASK                           0x3f
985 #define PALMAS_LDO6_VOLTAGE_VSEL_SHIFT                          0
986
987 /* Bit definitions for LDO7_CTRL */
988 #define PALMAS_LDO7_CTRL_WR_S                                   0x80
989 #define PALMAS_LDO7_CTRL_WR_S_SHIFT                             7
990 #define PALMAS_LDO7_CTRL_STATUS                                 0x10
991 #define PALMAS_LDO7_CTRL_STATUS_SHIFT                           4
992 #define PALMAS_LDO7_CTRL_MODE_SLEEP                             0x04
993 #define PALMAS_LDO7_CTRL_MODE_SLEEP_SHIFT                       2
994 #define PALMAS_LDO7_CTRL_MODE_ACTIVE                            0x01
995 #define PALMAS_LDO7_CTRL_MODE_ACTIVE_SHIFT                      0
996
997 /* Bit definitions for LDO7_VOLTAGE */
998 #define PALMAS_LDO7_VOLTAGE_VSEL_MASK                           0x3f
999 #define PALMAS_LDO7_VOLTAGE_VSEL_SHIFT                          0
1000
1001 /* Bit definitions for LDO8_CTRL */
1002 #define PALMAS_LDO8_CTRL_WR_S                                   0x80
1003 #define PALMAS_LDO8_CTRL_WR_S_SHIFT                             7
1004 #define PALMAS_LDO8_CTRL_LDO_TRACKING_EN                        0x40
1005 #define PALMAS_LDO8_CTRL_LDO_TRACKING_EN_SHIFT                  6
1006 #define PALMAS_LDO8_CTRL_STATUS                                 0x10
1007 #define PALMAS_LDO8_CTRL_STATUS_SHIFT                           4
1008 #define PALMAS_LDO8_CTRL_MODE_SLEEP                             0x04
1009 #define PALMAS_LDO8_CTRL_MODE_SLEEP_SHIFT                       2
1010 #define PALMAS_LDO8_CTRL_MODE_ACTIVE                            0x01
1011 #define PALMAS_LDO8_CTRL_MODE_ACTIVE_SHIFT                      0
1012
1013 /* Bit definitions for LDO8_VOLTAGE */
1014 #define PALMAS_LDO8_VOLTAGE_VSEL_MASK                           0x3f
1015 #define PALMAS_LDO8_VOLTAGE_VSEL_SHIFT                          0
1016
1017 /* Bit definitions for LDO9_CTRL */
1018 #define PALMAS_LDO9_CTRL_WR_S                                   0x80
1019 #define PALMAS_LDO9_CTRL_WR_S_SHIFT                             7
1020 #define PALMAS_LDO9_CTRL_LDO_BYPASS_EN                          0x40
1021 #define PALMAS_LDO9_CTRL_LDO_BYPASS_EN_SHIFT                    6
1022 #define PALMAS_LDO9_CTRL_STATUS                                 0x10
1023 #define PALMAS_LDO9_CTRL_STATUS_SHIFT                           4
1024 #define PALMAS_LDO9_CTRL_MODE_SLEEP                             0x04
1025 #define PALMAS_LDO9_CTRL_MODE_SLEEP_SHIFT                       2
1026 #define PALMAS_LDO9_CTRL_MODE_ACTIVE                            0x01
1027 #define PALMAS_LDO9_CTRL_MODE_ACTIVE_SHIFT                      0
1028
1029 /* Bit definitions for LDO9_VOLTAGE */
1030 #define PALMAS_LDO9_VOLTAGE_VSEL_MASK                           0x3f
1031 #define PALMAS_LDO9_VOLTAGE_VSEL_SHIFT                          0
1032
1033 /* Bit definitions for LDOLN_CTRL */
1034 #define PALMAS_LDOLN_CTRL_WR_S                                  0x80
1035 #define PALMAS_LDOLN_CTRL_WR_S_SHIFT                            7
1036 #define PALMAS_LDOLN_CTRL_STATUS                                0x10
1037 #define PALMAS_LDOLN_CTRL_STATUS_SHIFT                          4
1038 #define PALMAS_LDOLN_CTRL_MODE_SLEEP                            0x04
1039 #define PALMAS_LDOLN_CTRL_MODE_SLEEP_SHIFT                      2
1040 #define PALMAS_LDOLN_CTRL_MODE_ACTIVE                           0x01
1041 #define PALMAS_LDOLN_CTRL_MODE_ACTIVE_SHIFT                     0
1042
1043 /* Bit definitions for LDOLN_VOLTAGE */
1044 #define PALMAS_LDOLN_VOLTAGE_VSEL_MASK                          0x3f
1045 #define PALMAS_LDOLN_VOLTAGE_VSEL_SHIFT                         0
1046
1047 /* Bit definitions for LDOUSB_CTRL */
1048 #define PALMAS_LDOUSB_CTRL_WR_S                                 0x80
1049 #define PALMAS_LDOUSB_CTRL_WR_S_SHIFT                           7
1050 #define PALMAS_LDOUSB_CTRL_STATUS                               0x10
1051 #define PALMAS_LDOUSB_CTRL_STATUS_SHIFT                         4
1052 #define PALMAS_LDOUSB_CTRL_MODE_SLEEP                           0x04
1053 #define PALMAS_LDOUSB_CTRL_MODE_SLEEP_SHIFT                     2
1054 #define PALMAS_LDOUSB_CTRL_MODE_ACTIVE                          0x01
1055 #define PALMAS_LDOUSB_CTRL_MODE_ACTIVE_SHIFT                    0
1056
1057 /* Bit definitions for LDOUSB_VOLTAGE */
1058 #define PALMAS_LDOUSB_VOLTAGE_VSEL_MASK                         0x3f
1059 #define PALMAS_LDOUSB_VOLTAGE_VSEL_SHIFT                        0
1060
1061 /* Bit definitions for LDO_CTRL */
1062 #define PALMAS_LDO_CTRL_LDOUSB_ON_VBUS_VSYS                     0x01
1063 #define PALMAS_LDO_CTRL_LDOUSB_ON_VBUS_VSYS_SHIFT               0
1064
1065 /* Bit definitions for LDO_PD_CTRL1 */
1066 #define PALMAS_LDO_PD_CTRL1_LDO8                                0x80
1067 #define PALMAS_LDO_PD_CTRL1_LDO8_SHIFT                          7
1068 #define PALMAS_LDO_PD_CTRL1_LDO7                                0x40
1069 #define PALMAS_LDO_PD_CTRL1_LDO7_SHIFT                          6
1070 #define PALMAS_LDO_PD_CTRL1_LDO6                                0x20
1071 #define PALMAS_LDO_PD_CTRL1_LDO6_SHIFT                          5
1072 #define PALMAS_LDO_PD_CTRL1_LDO5                                0x10
1073 #define PALMAS_LDO_PD_CTRL1_LDO5_SHIFT                          4
1074 #define PALMAS_LDO_PD_CTRL1_LDO4                                0x08
1075 #define PALMAS_LDO_PD_CTRL1_LDO4_SHIFT                          3
1076 #define PALMAS_LDO_PD_CTRL1_LDO3                                0x04
1077 #define PALMAS_LDO_PD_CTRL1_LDO3_SHIFT                          2
1078 #define PALMAS_LDO_PD_CTRL1_LDO2                                0x02
1079 #define PALMAS_LDO_PD_CTRL1_LDO2_SHIFT                          1
1080 #define PALMAS_LDO_PD_CTRL1_LDO1                                0x01
1081 #define PALMAS_LDO_PD_CTRL1_LDO1_SHIFT                          0
1082
1083 /* Bit definitions for LDO_PD_CTRL2 */
1084 #define PALMAS_LDO_PD_CTRL2_LDOUSB                              0x04
1085 #define PALMAS_LDO_PD_CTRL2_LDOUSB_SHIFT                        2
1086 #define PALMAS_LDO_PD_CTRL2_LDOLN                               0x02
1087 #define PALMAS_LDO_PD_CTRL2_LDOLN_SHIFT                         1
1088 #define PALMAS_LDO_PD_CTRL2_LDO9                                0x01
1089 #define PALMAS_LDO_PD_CTRL2_LDO9_SHIFT                          0
1090
1091 /* Bit definitions for LDO_SHORT_STATUS1 */
1092 #define PALMAS_LDO_SHORT_STATUS1_LDO8                           0x80
1093 #define PALMAS_LDO_SHORT_STATUS1_LDO8_SHIFT                     7
1094 #define PALMAS_LDO_SHORT_STATUS1_LDO7                           0x40
1095 #define PALMAS_LDO_SHORT_STATUS1_LDO7_SHIFT                     6
1096 #define PALMAS_LDO_SHORT_STATUS1_LDO6                           0x20
1097 #define PALMAS_LDO_SHORT_STATUS1_LDO6_SHIFT                     5
1098 #define PALMAS_LDO_SHORT_STATUS1_LDO5                           0x10
1099 #define PALMAS_LDO_SHORT_STATUS1_LDO5_SHIFT                     4
1100 #define PALMAS_LDO_SHORT_STATUS1_LDO4                           0x08
1101 #define PALMAS_LDO_SHORT_STATUS1_LDO4_SHIFT                     3
1102 #define PALMAS_LDO_SHORT_STATUS1_LDO3                           0x04
1103 #define PALMAS_LDO_SHORT_STATUS1_LDO3_SHIFT                     2
1104 #define PALMAS_LDO_SHORT_STATUS1_LDO2                           0x02
1105 #define PALMAS_LDO_SHORT_STATUS1_LDO2_SHIFT                     1
1106 #define PALMAS_LDO_SHORT_STATUS1_LDO1                           0x01
1107 #define PALMAS_LDO_SHORT_STATUS1_LDO1_SHIFT                     0
1108
1109 /* Bit definitions for LDO_SHORT_STATUS2 */
1110 #define PALMAS_LDO_SHORT_STATUS2_LDOVANA                        0x08
1111 #define PALMAS_LDO_SHORT_STATUS2_LDOVANA_SHIFT                  3
1112 #define PALMAS_LDO_SHORT_STATUS2_LDOUSB                         0x04
1113 #define PALMAS_LDO_SHORT_STATUS2_LDOUSB_SHIFT                   2
1114 #define PALMAS_LDO_SHORT_STATUS2_LDOLN                          0x02
1115 #define PALMAS_LDO_SHORT_STATUS2_LDOLN_SHIFT                    1
1116 #define PALMAS_LDO_SHORT_STATUS2_LDO9                           0x01
1117 #define PALMAS_LDO_SHORT_STATUS2_LDO9_SHIFT                     0
1118
1119 /* Registers for function DVFS Func */
1120 #define PALMAS_SMPS_DVFS1_CTRL                                  0x0
1121 #define PALMAS_SMPS_DVFS1_ENABLE_SHIFT                          0
1122 #define PALMAS_SMPS_DVFS1_OFFSET_STEP_SHIFT                     1
1123 #define PALMAS_SMPS_DVFS1_ENABLE_RST_SHIFT                      2
1124 #define PALMAS_SMPS_DVFS1_RESTORE_VALUE_SHIFT                   3
1125 #define PALMAS_SMPS_DVFS1_VOLTAGE_MAX                           0x1
1126 #define PALMAS_SMPS_DVFS1_STATUS                                0x2
1127
1128 #define DVFS_BASE_VOLTAGE_UV                                    500000
1129 #define DVFS_MAX_VOLTAGE_UV                                     1650000
1130 #define DVFS_VOLTAGE_STEP_UV                                    10000
1131
1132 /* Registers for function PMU_CONTROL */
1133 #define PALMAS_DEV_CTRL                                         0x0
1134 #define PALMAS_POWER_CTRL                                       0x1
1135 #define PALMAS_VSYS_LO                                          0x2
1136 #define PALMAS_VSYS_MON                                         0x3
1137 #define PALMAS_VBAT_MON                                         0x4
1138 #define PALMAS_WATCHDOG                                         0x5
1139 #define PALMAS_BOOT_STATUS                                      0x6
1140 #define PALMAS_BATTERY_BOUNCE                                   0x7
1141 #define PALMAS_BACKUP_BATTERY_CTRL                              0x8
1142 #define PALMAS_LONG_PRESS_KEY                                   0x9
1143 #define PALMAS_OSC_THERM_CTRL                                   0xA
1144 #define PALMAS_BATDEBOUNCING                                    0xB
1145 #define PALMAS_SWOFF_HWRST                                      0xF
1146 #define PALMAS_SWOFF_COLDRST                                    0x10
1147 #define PALMAS_SWOFF_STATUS                                     0x11
1148 #define PALMAS_PMU_CONFIG                                       0x12
1149 #define PALMAS_SPARE                                            0x14
1150 #define PALMAS_PMU_SECONDARY_INT                                0x15
1151 #define PALMAS_SW_REVISION                                      0x17
1152 #define PALMAS_EXT_CHRG_CTRL                                    0x18
1153 #define PALMAS_PMU_SECONDARY_INT2                               0x19
1154
1155 /* Bit definitions for DEV_CTRL */
1156 #define PALMAS_DEV_CTRL_DEV_STATUS_MASK                         0x0c
1157 #define PALMAS_DEV_CTRL_DEV_STATUS_SHIFT                        2
1158 #define PALMAS_DEV_CTRL_SW_RST                                  0x02
1159 #define PALMAS_DEV_CTRL_SW_RST_SHIFT                            1
1160 #define PALMAS_DEV_CTRL_DEV_ON                                  0x01
1161 #define PALMAS_DEV_CTRL_DEV_ON_SHIFT                            0
1162
1163 /* Bit definitions for POWER_CTRL */
1164 #define PALMAS_POWER_CTRL_ENABLE2_MASK                          0x04
1165 #define PALMAS_POWER_CTRL_ENABLE2_MASK_SHIFT                    2
1166 #define PALMAS_POWER_CTRL_ENABLE1_MASK                          0x02
1167 #define PALMAS_POWER_CTRL_ENABLE1_MASK_SHIFT                    1
1168 #define PALMAS_POWER_CTRL_NSLEEP_MASK                           0x01
1169 #define PALMAS_POWER_CTRL_NSLEEP_MASK_SHIFT                     0
1170
1171 /* Bit definitions for VSYS_LO */
1172 #define PALMAS_VSYS_LO_THRESHOLD_MASK                           0x1f
1173 #define PALMAS_VSYS_LO_THRESHOLD_SHIFT                          0
1174
1175 /* Bit definitions for VSYS_MON */
1176 #define PALMAS_VSYS_MON_ENABLE                                  0x80
1177 #define PALMAS_VSYS_MON_ENABLE_SHIFT                            7
1178 #define PALMAS_VSYS_MON_THRESHOLD_MASK                          0x3f
1179 #define PALMAS_VSYS_MON_THRESHOLD_SHIFT                         0
1180
1181 /* Bit definitions for VBAT_MON */
1182 #define PALMAS_VBAT_MON_ENABLE                                  0x80
1183 #define PALMAS_VBAT_MON_ENABLE_SHIFT                            7
1184 #define PALMAS_VBAT_MON_THRESHOLD_MASK                          0x3f
1185 #define PALMAS_VBAT_MON_THRESHOLD_SHIFT                         0
1186
1187 /* Bit definitions for WATCHDOG */
1188 #define PALMAS_WATCHDOG_LOCK                                    0x20
1189 #define PALMAS_WATCHDOG_LOCK_SHIFT                              5
1190 #define PALMAS_WATCHDOG_ENABLE                                  0x10
1191 #define PALMAS_WATCHDOG_ENABLE_SHIFT                            4
1192 #define PALMAS_WATCHDOG_MODE                                    0x08
1193 #define PALMAS_WATCHDOG_MODE_SHIFT                              3
1194 #define PALMAS_WATCHDOG_TIMER_MASK                              0x07
1195 #define PALMAS_WATCHDOG_TIMER_SHIFT                             0
1196
1197 /* Bit definitions for BOOT_STATUS */
1198 #define PALMAS_BOOT_STATUS_BOOT1                                0x02
1199 #define PALMAS_BOOT_STATUS_BOOT1_SHIFT                          1
1200 #define PALMAS_BOOT_STATUS_BOOT0                                0x01
1201 #define PALMAS_BOOT_STATUS_BOOT0_SHIFT                          0
1202
1203 /* Bit definitions for BATTERY_BOUNCE */
1204 #define PALMAS_BATTERY_BOUNCE_BB_DELAY_MASK                     0x3f
1205 #define PALMAS_BATTERY_BOUNCE_BB_DELAY_SHIFT                    0
1206
1207 /* Bit definitions for BACKUP_BATTERY_CTRL */
1208 #define PALMAS_BACKUP_BATTERY_CTRL_VRTC_18_15                   0x80
1209 #define PALMAS_BACKUP_BATTERY_CTRL_VRTC_18_15_SHIFT             7
1210 #define PALMAS_BACKUP_BATTERY_CTRL_VRTC_EN_SLP                  0x40
1211 #define PALMAS_BACKUP_BATTERY_CTRL_VRTC_EN_SLP_SHIFT            6
1212 #define PALMAS_BACKUP_BATTERY_CTRL_VRTC_EN_OFF                  0x20
1213 #define PALMAS_BACKUP_BATTERY_CTRL_VRTC_EN_OFF_SHIFT            5
1214 #define PALMAS_BACKUP_BATTERY_CTRL_VRTC_PWEN                    0x10
1215 #define PALMAS_BACKUP_BATTERY_CTRL_VRTC_PWEN_SHIFT              4
1216 #define PALMAS_BACKUP_BATTERY_CTRL_BBS_BBC_LOW_ICHRG            0x08
1217 #define PALMAS_BACKUP_BATTERY_CTRL_BBS_BBC_LOW_ICHRG_SHIFT      3
1218 #define PALMAS_BACKUP_BATTERY_CTRL_BB_SEL_MASK                  0x06
1219 #define PALMAS_BACKUP_BATTERY_CTRL_BB_SEL_SHIFT                 1
1220 #define PALMAS_BACKUP_BATTERY_CTRL_BB_CHG_EN                    0x01
1221 #define PALMAS_BACKUP_BATTERY_CTRL_BB_CHG_EN_SHIFT              0
1222
1223 /* Bit definitions for LONG_PRESS_KEY */
1224 #define PALMAS_LONG_PRESS_KEY_LPK_LOCK                          0x80
1225 #define PALMAS_LONG_PRESS_KEY_LPK_LOCK_SHIFT                    7
1226 #define PALMAS_LONG_PRESS_KEY_LPK_INT_CLR                       0x10
1227 #define PALMAS_LONG_PRESS_KEY_LPK_INT_CLR_SHIFT                 4
1228 #define PALMAS_LONG_PRESS_KEY_LPK_TIME_MASK                     0x0c
1229 #define PALMAS_LONG_PRESS_KEY_LPK_TIME_SHIFT                    2
1230 #define PALMAS_LONG_PRESS_KEY_PWRON_DEBOUNCE_MASK               0x03
1231 #define PALMAS_LONG_PRESS_KEY_PWRON_DEBOUNCE_SHIFT              0
1232
1233 /* Bit definitions for OSC_THERM_CTRL */
1234 #define PALMAS_OSC_THERM_CTRL_VANA_ON_IN_SLEEP                  0x80
1235 #define PALMAS_OSC_THERM_CTRL_VANA_ON_IN_SLEEP_SHIFT            7
1236 #define PALMAS_OSC_THERM_CTRL_INT_MASK_IN_SLEEP                 0x40
1237 #define PALMAS_OSC_THERM_CTRL_INT_MASK_IN_SLEEP_SHIFT           6
1238 #define PALMAS_OSC_THERM_CTRL_RC15MHZ_ON_IN_SLEEP               0x20
1239 #define PALMAS_OSC_THERM_CTRL_RC15MHZ_ON_IN_SLEEP_SHIFT         5
1240 #define PALMAS_OSC_THERM_CTRL_THERM_OFF_IN_SLEEP                0x10
1241 #define PALMAS_OSC_THERM_CTRL_THERM_OFF_IN_SLEEP_SHIFT          4
1242 #define PALMAS_OSC_THERM_CTRL_THERM_HD_SEL_MASK                 0x0c
1243 #define PALMAS_OSC_THERM_CTRL_THERM_HD_SEL_SHIFT                2
1244 #define PALMAS_OSC_THERM_CTRL_OSC_BYPASS                        0x02
1245 #define PALMAS_OSC_THERM_CTRL_OSC_BYPASS_SHIFT                  1
1246 #define PALMAS_OSC_THERM_CTRL_OSC_HPMODE                        0x01
1247 #define PALMAS_OSC_THERM_CTRL_OSC_HPMODE_SHIFT                  0
1248
1249 /* Bit definitions for BATDEBOUNCING */
1250 #define PALMAS_BATDEBOUNCING_BAT_DEB_BYPASS                     0x80
1251 #define PALMAS_BATDEBOUNCING_BAT_DEB_BYPASS_SHIFT               7
1252 #define PALMAS_BATDEBOUNCING_BINS_DEB_MASK                      0x78
1253 #define PALMAS_BATDEBOUNCING_BINS_DEB_SHIFT                     3
1254 #define PALMAS_BATDEBOUNCING_BEXT_DEB_MASK                      0x07
1255 #define PALMAS_BATDEBOUNCING_BEXT_DEB_SHIFT                     0
1256
1257 /* Bit definitions for SWOFF_HWRST */
1258 #define PALMAS_SWOFF_HWRST_PWRON_LPK                            0x80
1259 #define PALMAS_SWOFF_HWRST_PWRON_LPK_SHIFT                      7
1260 #define PALMAS_SWOFF_HWRST_PWRDOWN                              0x40
1261 #define PALMAS_SWOFF_HWRST_PWRDOWN_SHIFT                        6
1262 #define PALMAS_SWOFF_HWRST_WTD                                  0x20
1263 #define PALMAS_SWOFF_HWRST_WTD_SHIFT                            5
1264 #define PALMAS_SWOFF_HWRST_TSHUT                                0x10
1265 #define PALMAS_SWOFF_HWRST_TSHUT_SHIFT                          4
1266 #define PALMAS_SWOFF_HWRST_RESET_IN                             0x08
1267 #define PALMAS_SWOFF_HWRST_RESET_IN_SHIFT                       3
1268 #define PALMAS_SWOFF_HWRST_SW_RST                               0x04
1269 #define PALMAS_SWOFF_HWRST_SW_RST_SHIFT                         2
1270 #define PALMAS_SWOFF_HWRST_VSYS_LO                              0x02
1271 #define PALMAS_SWOFF_HWRST_VSYS_LO_SHIFT                        1
1272 #define PALMAS_SWOFF_HWRST_GPADC_SHUTDOWN                       0x01
1273 #define PALMAS_SWOFF_HWRST_GPADC_SHUTDOWN_SHIFT                 0
1274
1275 /* Bit definitions for SWOFF_COLDRST */
1276 #define PALMAS_SWOFF_COLDRST_PWRON_LPK                          0x80
1277 #define PALMAS_SWOFF_COLDRST_PWRON_LPK_SHIFT                    7
1278 #define PALMAS_SWOFF_COLDRST_PWRDOWN                            0x40
1279 #define PALMAS_SWOFF_COLDRST_PWRDOWN_SHIFT                      6
1280 #define PALMAS_SWOFF_COLDRST_WTD                                0x20
1281 #define PALMAS_SWOFF_COLDRST_WTD_SHIFT                          5
1282 #define PALMAS_SWOFF_COLDRST_TSHUT                              0x10
1283 #define PALMAS_SWOFF_COLDRST_TSHUT_SHIFT                        4
1284 #define PALMAS_SWOFF_COLDRST_RESET_IN                           0x08
1285 #define PALMAS_SWOFF_COLDRST_RESET_IN_SHIFT                     3
1286 #define PALMAS_SWOFF_COLDRST_SW_RST                             0x04
1287 #define PALMAS_SWOFF_COLDRST_SW_RST_SHIFT                       2
1288 #define PALMAS_SWOFF_COLDRST_VSYS_LO                            0x02
1289 #define PALMAS_SWOFF_COLDRST_VSYS_LO_SHIFT                      1
1290 #define PALMAS_SWOFF_COLDRST_GPADC_SHUTDOWN                     0x01
1291 #define PALMAS_SWOFF_COLDRST_GPADC_SHUTDOWN_SHIFT               0
1292
1293 /* Bit definitions for SWOFF_STATUS */
1294 #define PALMAS_SWOFF_STATUS_PWRON_LPK                           0x80
1295 #define PALMAS_SWOFF_STATUS_PWRON_LPK_SHIFT                     7
1296 #define PALMAS_SWOFF_STATUS_PWRDOWN                             0x40
1297 #define PALMAS_SWOFF_STATUS_PWRDOWN_SHIFT                       6
1298 #define PALMAS_SWOFF_STATUS_WTD                                 0x20
1299 #define PALMAS_SWOFF_STATUS_WTD_SHIFT                           5
1300 #define PALMAS_SWOFF_STATUS_TSHUT                               0x10
1301 #define PALMAS_SWOFF_STATUS_TSHUT_SHIFT                         4
1302 #define PALMAS_SWOFF_STATUS_RESET_IN                            0x08
1303 #define PALMAS_SWOFF_STATUS_RESET_IN_SHIFT                      3
1304 #define PALMAS_SWOFF_STATUS_SW_RST                              0x04
1305 #define PALMAS_SWOFF_STATUS_SW_RST_SHIFT                        2
1306 #define PALMAS_SWOFF_STATUS_VSYS_LO                             0x02
1307 #define PALMAS_SWOFF_STATUS_VSYS_LO_SHIFT                       1
1308 #define PALMAS_SWOFF_STATUS_GPADC_SHUTDOWN                      0x01
1309 #define PALMAS_SWOFF_STATUS_GPADC_SHUTDOWN_SHIFT                0
1310
1311 /* Bit definitions for PMU_CONFIG */
1312 #define PALMAS_PMU_CONFIG_MULTI_CELL_EN                         0x40
1313 #define PALMAS_PMU_CONFIG_MULTI_CELL_EN_SHIFT                   6
1314 #define PALMAS_PMU_CONFIG_SPARE_MASK                            0x30
1315 #define PALMAS_PMU_CONFIG_SPARE_SHIFT                           4
1316 #define PALMAS_PMU_CONFIG_SWOFF_DLY_MASK                        0x0c
1317 #define PALMAS_PMU_CONFIG_SWOFF_DLY_SHIFT                       2
1318 #define PALMAS_PMU_CONFIG_GATE_RESET_OUT                        0x02
1319 #define PALMAS_PMU_CONFIG_GATE_RESET_OUT_SHIFT                  1
1320 #define PALMAS_PMU_CONFIG_AUTODEVON                             0x01
1321 #define PALMAS_PMU_CONFIG_AUTODEVON_SHIFT                       0
1322
1323 /* Bit definitions for SPARE */
1324 #define PALMAS_SPARE_SPARE_MASK                                 0xf8
1325 #define PALMAS_SPARE_SPARE_SHIFT                                3
1326 #define PALMAS_SPARE_REGEN3_OD                                  0x04
1327 #define PALMAS_SPARE_REGEN3_OD_SHIFT                            2
1328 #define PALMAS_SPARE_REGEN2_OD                                  0x02
1329 #define PALMAS_SPARE_REGEN2_OD_SHIFT                            1
1330 #define PALMAS_SPARE_REGEN1_OD                                  0x01
1331 #define PALMAS_SPARE_REGEN1_OD_SHIFT                            0
1332
1333 /* Bit definitions for PMU_SECONDARY_INT */
1334 #define PALMAS_PMU_SECONDARY_INT_VBUS_OVV_INT_SRC               0x80
1335 #define PALMAS_PMU_SECONDARY_INT_VBUS_OVV_INT_SRC_SHIFT         7
1336 #define PALMAS_PMU_SECONDARY_INT_CHARG_DET_N_INT_SRC            0x40
1337 #define PALMAS_PMU_SECONDARY_INT_CHARG_DET_N_INT_SRC_SHIFT      6
1338 #define PALMAS_PMU_SECONDARY_INT_BB_INT_SRC                     0x20
1339 #define PALMAS_PMU_SECONDARY_INT_BB_INT_SRC_SHIFT               5
1340 #define PALMAS_PMU_SECONDARY_INT_FBI_INT_SRC                    0x10
1341 #define PALMAS_PMU_SECONDARY_INT_FBI_INT_SRC_SHIFT              4
1342 #define PALMAS_PMU_SECONDARY_INT_VBUS_OVV_MASK                  0x08
1343 #define PALMAS_PMU_SECONDARY_INT_VBUS_OVV_MASK_SHIFT            3
1344 #define PALMAS_PMU_SECONDARY_INT_CHARG_DET_N_MASK               0x04
1345 #define PALMAS_PMU_SECONDARY_INT_CHARG_DET_N_MASK_SHIFT         2
1346 #define PALMAS_PMU_SECONDARY_INT_BB_MASK                        0x02
1347 #define PALMAS_PMU_SECONDARY_INT_BB_MASK_SHIFT                  1
1348 #define PALMAS_PMU_SECONDARY_INT_FBI_MASK                       0x01
1349 #define PALMAS_PMU_SECONDARY_INT_FBI_MASK_SHIFT                 0
1350
1351 /* Bit definitions for SW_REVISION */
1352 #define PALMAS_SW_REVISION_SW_REVISION_MASK                     0xff
1353 #define PALMAS_SW_REVISION_SW_REVISION_SHIFT                    0
1354
1355 /* Bit definitions for EXT_CHRG_CTRL */
1356 #define PALMAS_EXT_CHRG_CTRL_VBUS_OVV_STATUS                    0x80
1357 #define PALMAS_EXT_CHRG_CTRL_VBUS_OVV_STATUS_SHIFT              7
1358 #define PALMAS_EXT_CHRG_CTRL_CHARG_DET_N_STATUS                 0x40
1359 #define PALMAS_EXT_CHRG_CTRL_CHARG_DET_N_STATUS_SHIFT           6
1360 #define PALMAS_EXT_CHRG_CTRL_VSYS_DEBOUNCE_DELAY                0x08
1361 #define PALMAS_EXT_CHRG_CTRL_VSYS_DEBOUNCE_DELAY_SHIFT          3
1362 #define PALMAS_EXT_CHRG_CTRL_CHRG_DET_N                         0x04
1363 #define PALMAS_EXT_CHRG_CTRL_CHRG_DET_N_SHIFT                   2
1364 #define PALMAS_EXT_CHRG_CTRL_AUTO_ACA_EN                        0x02
1365 #define PALMAS_EXT_CHRG_CTRL_AUTO_ACA_EN_SHIFT                  1
1366 #define PALMAS_EXT_CHRG_CTRL_AUTO_LDOUSB_EN                     0x01
1367 #define PALMAS_EXT_CHRG_CTRL_AUTO_LDOUSB_EN_SHIFT               0
1368
1369 /* Bit definitions for PMU_SECONDARY_INT2 */
1370 #define PALMAS_PMU_SECONDARY_INT2_DVFS2_INT_SRC                 0x20
1371 #define PALMAS_PMU_SECONDARY_INT2_DVFS2_INT_SRC_SHIFT           5
1372 #define PALMAS_PMU_SECONDARY_INT2_DVFS1_INT_SRC                 0x10
1373 #define PALMAS_PMU_SECONDARY_INT2_DVFS1_INT_SRC_SHIFT           4
1374 #define PALMAS_PMU_SECONDARY_INT2_DVFS2_MASK                    0x02
1375 #define PALMAS_PMU_SECONDARY_INT2_DVFS2_MASK_SHIFT              1
1376 #define PALMAS_PMU_SECONDARY_INT2_DVFS1_MASK                    0x01
1377 #define PALMAS_PMU_SECONDARY_INT2_DVFS1_MASK_SHIFT              0
1378
1379 /* Registers for function RESOURCE */
1380 #define PALMAS_CLK32KG_CTRL                                     0x0
1381 #define PALMAS_CLK32KGAUDIO_CTRL                                0x1
1382 #define PALMAS_REGEN1_CTRL                                      0x2
1383 #define PALMAS_REGEN2_CTRL                                      0x3
1384 #define PALMAS_SYSEN1_CTRL                                      0x4
1385 #define PALMAS_SYSEN2_CTRL                                      0x5
1386 #define PALMAS_NSLEEP_RES_ASSIGN                                0x6
1387 #define PALMAS_NSLEEP_SMPS_ASSIGN                               0x7
1388 #define PALMAS_NSLEEP_LDO_ASSIGN1                               0x8
1389 #define PALMAS_NSLEEP_LDO_ASSIGN2                               0x9
1390 #define PALMAS_ENABLE1_RES_ASSIGN                               0xA
1391 #define PALMAS_ENABLE1_SMPS_ASSIGN                              0xB
1392 #define PALMAS_ENABLE1_LDO_ASSIGN1                              0xC
1393 #define PALMAS_ENABLE1_LDO_ASSIGN2                              0xD
1394 #define PALMAS_ENABLE2_RES_ASSIGN                               0xE
1395 #define PALMAS_ENABLE2_SMPS_ASSIGN                              0xF
1396 #define PALMAS_ENABLE2_LDO_ASSIGN1                              0x10
1397 #define PALMAS_ENABLE2_LDO_ASSIGN2                              0x11
1398 #define PALMAS_REGEN3_CTRL                                      0x12
1399
1400 /* Bit definitions for CLK32KG_CTRL */
1401 #define PALMAS_CLK32KG_CTRL_STATUS                              0x10
1402 #define PALMAS_CLK32KG_CTRL_STATUS_SHIFT                        4
1403 #define PALMAS_CLK32KG_CTRL_MODE_SLEEP                          0x04
1404 #define PALMAS_CLK32KG_CTRL_MODE_SLEEP_SHIFT                    2
1405 #define PALMAS_CLK32KG_CTRL_MODE_ACTIVE                         0x01
1406 #define PALMAS_CLK32KG_CTRL_MODE_ACTIVE_SHIFT                   0
1407
1408 /* Bit definitions for CLK32KGAUDIO_CTRL */
1409 #define PALMAS_CLK32KGAUDIO_CTRL_STATUS                         0x10
1410 #define PALMAS_CLK32KGAUDIO_CTRL_STATUS_SHIFT                   4
1411 #define PALMAS_CLK32KGAUDIO_CTRL_RESERVED3                      0x08
1412 #define PALMAS_CLK32KGAUDIO_CTRL_RESERVED3_SHIFT                3
1413 #define PALMAS_CLK32KGAUDIO_CTRL_MODE_SLEEP                     0x04
1414 #define PALMAS_CLK32KGAUDIO_CTRL_MODE_SLEEP_SHIFT               2
1415 #define PALMAS_CLK32KGAUDIO_CTRL_MODE_ACTIVE                    0x01
1416 #define PALMAS_CLK32KGAUDIO_CTRL_MODE_ACTIVE_SHIFT              0
1417
1418 /* Bit definitions for REGEN1_CTRL */
1419 #define PALMAS_REGEN1_CTRL_STATUS                               0x10
1420 #define PALMAS_REGEN1_CTRL_STATUS_SHIFT                         4
1421 #define PALMAS_REGEN1_CTRL_MODE_SLEEP                           0x04
1422 #define PALMAS_REGEN1_CTRL_MODE_SLEEP_SHIFT                     2
1423 #define PALMAS_REGEN1_CTRL_MODE_ACTIVE                          0x01
1424 #define PALMAS_REGEN1_CTRL_MODE_ACTIVE_SHIFT                    0
1425
1426 /* Bit definitions for REGEN2_CTRL */
1427 #define PALMAS_REGEN2_CTRL_STATUS                               0x10
1428 #define PALMAS_REGEN2_CTRL_STATUS_SHIFT                         4
1429 #define PALMAS_REGEN2_CTRL_MODE_SLEEP                           0x04
1430 #define PALMAS_REGEN2_CTRL_MODE_SLEEP_SHIFT                     2
1431 #define PALMAS_REGEN2_CTRL_MODE_ACTIVE                          0x01
1432 #define PALMAS_REGEN2_CTRL_MODE_ACTIVE_SHIFT                    0
1433
1434 /* Bit definitions for SYSEN1_CTRL */
1435 #define PALMAS_SYSEN1_CTRL_STATUS                               0x10
1436 #define PALMAS_SYSEN1_CTRL_STATUS_SHIFT                         4
1437 #define PALMAS_SYSEN1_CTRL_MODE_SLEEP                           0x04
1438 #define PALMAS_SYSEN1_CTRL_MODE_SLEEP_SHIFT                     2
1439 #define PALMAS_SYSEN1_CTRL_MODE_ACTIVE                          0x01
1440 #define PALMAS_SYSEN1_CTRL_MODE_ACTIVE_SHIFT                    0
1441
1442 /* Bit definitions for SYSEN2_CTRL */
1443 #define PALMAS_SYSEN2_CTRL_STATUS                               0x10
1444 #define PALMAS_SYSEN2_CTRL_STATUS_SHIFT                         4
1445 #define PALMAS_SYSEN2_CTRL_MODE_SLEEP                           0x04
1446 #define PALMAS_SYSEN2_CTRL_MODE_SLEEP_SHIFT                     2
1447 #define PALMAS_SYSEN2_CTRL_MODE_ACTIVE                          0x01
1448 #define PALMAS_SYSEN2_CTRL_MODE_ACTIVE_SHIFT                    0
1449
1450 /* Bit definitions for NSLEEP_RES_ASSIGN */
1451 #define PALMAS_NSLEEP_RES_ASSIGN_REGEN3                         0x40
1452 #define PALMAS_NSLEEP_RES_ASSIGN_REGEN3_SHIFT                   6
1453 #define PALMAS_NSLEEP_RES_ASSIGN_CLK32KGAUDIO                   0x20
1454 #define PALMAS_NSLEEP_RES_ASSIGN_CLK32KGAUDIO_SHIFT             5
1455 #define PALMAS_NSLEEP_RES_ASSIGN_CLK32KG                        0x10
1456 #define PALMAS_NSLEEP_RES_ASSIGN_CLK32KG_SHIFT                  4
1457 #define PALMAS_NSLEEP_RES_ASSIGN_SYSEN2                         0x08
1458 #define PALMAS_NSLEEP_RES_ASSIGN_SYSEN2_SHIFT                   3
1459 #define PALMAS_NSLEEP_RES_ASSIGN_SYSEN1                         0x04
1460 #define PALMAS_NSLEEP_RES_ASSIGN_SYSEN1_SHIFT                   2
1461 #define PALMAS_NSLEEP_RES_ASSIGN_REGEN2                         0x02
1462 #define PALMAS_NSLEEP_RES_ASSIGN_REGEN2_SHIFT                   1
1463 #define PALMAS_NSLEEP_RES_ASSIGN_REGEN1                         0x01
1464 #define PALMAS_NSLEEP_RES_ASSIGN_REGEN1_SHIFT                   0
1465
1466 /* Bit definitions for NSLEEP_SMPS_ASSIGN */
1467 #define PALMAS_NSLEEP_SMPS_ASSIGN_SMPS10                        0x80
1468 #define PALMAS_NSLEEP_SMPS_ASSIGN_SMPS10_SHIFT                  7
1469 #define PALMAS_NSLEEP_SMPS_ASSIGN_SMPS9                         0x40
1470 #define PALMAS_NSLEEP_SMPS_ASSIGN_SMPS9_SHIFT                   6
1471 #define PALMAS_NSLEEP_SMPS_ASSIGN_SMPS8                         0x20
1472 #define PALMAS_NSLEEP_SMPS_ASSIGN_SMPS8_SHIFT                   5
1473 #define PALMAS_NSLEEP_SMPS_ASSIGN_SMPS7                         0x10
1474 #define PALMAS_NSLEEP_SMPS_ASSIGN_SMPS7_SHIFT                   4
1475 #define PALMAS_NSLEEP_SMPS_ASSIGN_SMPS6                         0x08
1476 #define PALMAS_NSLEEP_SMPS_ASSIGN_SMPS6_SHIFT                   3
1477 #define PALMAS_NSLEEP_SMPS_ASSIGN_SMPS45                        0x04
1478 #define PALMAS_NSLEEP_SMPS_ASSIGN_SMPS45_SHIFT                  2
1479 #define PALMAS_NSLEEP_SMPS_ASSIGN_SMPS3                         0x02
1480 #define PALMAS_NSLEEP_SMPS_ASSIGN_SMPS3_SHIFT                   1
1481 #define PALMAS_NSLEEP_SMPS_ASSIGN_SMPS12                        0x01
1482 #define PALMAS_NSLEEP_SMPS_ASSIGN_SMPS12_SHIFT                  0
1483
1484 /* Bit definitions for NSLEEP_LDO_ASSIGN1 */
1485 #define PALMAS_NSLEEP_LDO_ASSIGN1_LDO8                          0x80
1486 #define PALMAS_NSLEEP_LDO_ASSIGN1_LDO8_SHIFT                    7
1487 #define PALMAS_NSLEEP_LDO_ASSIGN1_LDO7                          0x40
1488 #define PALMAS_NSLEEP_LDO_ASSIGN1_LDO7_SHIFT                    6
1489 #define PALMAS_NSLEEP_LDO_ASSIGN1_LDO6                          0x20
1490 #define PALMAS_NSLEEP_LDO_ASSIGN1_LDO6_SHIFT                    5
1491 #define PALMAS_NSLEEP_LDO_ASSIGN1_LDO5                          0x10
1492 #define PALMAS_NSLEEP_LDO_ASSIGN1_LDO5_SHIFT                    4
1493 #define PALMAS_NSLEEP_LDO_ASSIGN1_LDO4                          0x08
1494 #define PALMAS_NSLEEP_LDO_ASSIGN1_LDO4_SHIFT                    3
1495 #define PALMAS_NSLEEP_LDO_ASSIGN1_LDO3                          0x04
1496 #define PALMAS_NSLEEP_LDO_ASSIGN1_LDO3_SHIFT                    2
1497 #define PALMAS_NSLEEP_LDO_ASSIGN1_LDO2                          0x02
1498 #define PALMAS_NSLEEP_LDO_ASSIGN1_LDO2_SHIFT                    1
1499 #define PALMAS_NSLEEP_LDO_ASSIGN1_LDO1                          0x01
1500 #define PALMAS_NSLEEP_LDO_ASSIGN1_LDO1_SHIFT                    0
1501
1502 /* Bit definitions for NSLEEP_LDO_ASSIGN2 */
1503 #define PALMAS_NSLEEP_LDO_ASSIGN2_LDOUSB                        0x04
1504 #define PALMAS_NSLEEP_LDO_ASSIGN2_LDOUSB_SHIFT                  2
1505 #define PALMAS_NSLEEP_LDO_ASSIGN2_LDOLN                         0x02
1506 #define PALMAS_NSLEEP_LDO_ASSIGN2_LDOLN_SHIFT                   1
1507 #define PALMAS_NSLEEP_LDO_ASSIGN2_LDO9                          0x01
1508 #define PALMAS_NSLEEP_LDO_ASSIGN2_LDO9_SHIFT                    0
1509
1510 /* Bit definitions for ENABLE1_RES_ASSIGN */
1511 #define PALMAS_ENABLE1_RES_ASSIGN_REGEN3                        0x40
1512 #define PALMAS_ENABLE1_RES_ASSIGN_REGEN3_SHIFT                  6
1513 #define PALMAS_ENABLE1_RES_ASSIGN_CLK32KGAUDIO                  0x20
1514 #define PALMAS_ENABLE1_RES_ASSIGN_CLK32KGAUDIO_SHIFT            5
1515 #define PALMAS_ENABLE1_RES_ASSIGN_CLK32KG                       0x10
1516 #define PALMAS_ENABLE1_RES_ASSIGN_CLK32KG_SHIFT                 4
1517 #define PALMAS_ENABLE1_RES_ASSIGN_SYSEN2                        0x08
1518 #define PALMAS_ENABLE1_RES_ASSIGN_SYSEN2_SHIFT                  3
1519 #define PALMAS_ENABLE1_RES_ASSIGN_SYSEN1                        0x04
1520 #define PALMAS_ENABLE1_RES_ASSIGN_SYSEN1_SHIFT                  2
1521 #define PALMAS_ENABLE1_RES_ASSIGN_REGEN2                        0x02
1522 #define PALMAS_ENABLE1_RES_ASSIGN_REGEN2_SHIFT                  1
1523 #define PALMAS_ENABLE1_RES_ASSIGN_REGEN1                        0x01
1524 #define PALMAS_ENABLE1_RES_ASSIGN_REGEN1_SHIFT                  0
1525
1526 /* Bit definitions for ENABLE1_SMPS_ASSIGN */
1527 #define PALMAS_ENABLE1_SMPS_ASSIGN_SMPS10                       0x80
1528 #define PALMAS_ENABLE1_SMPS_ASSIGN_SMPS10_SHIFT                 7
1529 #define PALMAS_ENABLE1_SMPS_ASSIGN_SMPS9                        0x40
1530 #define PALMAS_ENABLE1_SMPS_ASSIGN_SMPS9_SHIFT                  6
1531 #define PALMAS_ENABLE1_SMPS_ASSIGN_SMPS8                        0x20
1532 #define PALMAS_ENABLE1_SMPS_ASSIGN_SMPS8_SHIFT                  5
1533 #define PALMAS_ENABLE1_SMPS_ASSIGN_SMPS7                        0x10
1534 #define PALMAS_ENABLE1_SMPS_ASSIGN_SMPS7_SHIFT                  4
1535 #define PALMAS_ENABLE1_SMPS_ASSIGN_SMPS6                        0x08
1536 #define PALMAS_ENABLE1_SMPS_ASSIGN_SMPS6_SHIFT                  3
1537 #define PALMAS_ENABLE1_SMPS_ASSIGN_SMPS45                       0x04
1538 #define PALMAS_ENABLE1_SMPS_ASSIGN_SMPS45_SHIFT                 2
1539 #define PALMAS_ENABLE1_SMPS_ASSIGN_SMPS3                        0x02
1540 #define PALMAS_ENABLE1_SMPS_ASSIGN_SMPS3_SHIFT                  1
1541 #define PALMAS_ENABLE1_SMPS_ASSIGN_SMPS12                       0x01
1542 #define PALMAS_ENABLE1_SMPS_ASSIGN_SMPS12_SHIFT                 0
1543
1544 /* Bit definitions for ENABLE1_LDO_ASSIGN1 */
1545 #define PALMAS_ENABLE1_LDO_ASSIGN1_LDO8                         0x80
1546 #define PALMAS_ENABLE1_LDO_ASSIGN1_LDO8_SHIFT                   7
1547 #define PALMAS_ENABLE1_LDO_ASSIGN1_LDO7                         0x40
1548 #define PALMAS_ENABLE1_LDO_ASSIGN1_LDO7_SHIFT                   6
1549 #define PALMAS_ENABLE1_LDO_ASSIGN1_LDO6                         0x20
1550 #define PALMAS_ENABLE1_LDO_ASSIGN1_LDO6_SHIFT                   5
1551 #define PALMAS_ENABLE1_LDO_ASSIGN1_LDO5                         0x10
1552 #define PALMAS_ENABLE1_LDO_ASSIGN1_LDO5_SHIFT                   4
1553 #define PALMAS_ENABLE1_LDO_ASSIGN1_LDO4                         0x08
1554 #define PALMAS_ENABLE1_LDO_ASSIGN1_LDO4_SHIFT                   3
1555 #define PALMAS_ENABLE1_LDO_ASSIGN1_LDO3                         0x04
1556 #define PALMAS_ENABLE1_LDO_ASSIGN1_LDO3_SHIFT                   2
1557 #define PALMAS_ENABLE1_LDO_ASSIGN1_LDO2                         0x02
1558 #define PALMAS_ENABLE1_LDO_ASSIGN1_LDO2_SHIFT                   1
1559 #define PALMAS_ENABLE1_LDO_ASSIGN1_LDO1                         0x01
1560 #define PALMAS_ENABLE1_LDO_ASSIGN1_LDO1_SHIFT                   0
1561
1562 /* Bit definitions for ENABLE1_LDO_ASSIGN2 */
1563 #define PALMAS_ENABLE1_LDO_ASSIGN2_LDOUSB                       0x04
1564 #define PALMAS_ENABLE1_LDO_ASSIGN2_LDOUSB_SHIFT                 2
1565 #define PALMAS_ENABLE1_LDO_ASSIGN2_LDOLN                        0x02
1566 #define PALMAS_ENABLE1_LDO_ASSIGN2_LDOLN_SHIFT                  1
1567 #define PALMAS_ENABLE1_LDO_ASSIGN2_LDO9                         0x01
1568 #define PALMAS_ENABLE1_LDO_ASSIGN2_LDO9_SHIFT                   0
1569
1570 /* Bit definitions for ENABLE2_RES_ASSIGN */
1571 #define PALMAS_ENABLE2_RES_ASSIGN_REGEN3                        0x40
1572 #define PALMAS_ENABLE2_RES_ASSIGN_REGEN3_SHIFT                  6
1573 #define PALMAS_ENABLE2_RES_ASSIGN_CLK32KGAUDIO                  0x20
1574 #define PALMAS_ENABLE2_RES_ASSIGN_CLK32KGAUDIO_SHIFT            5
1575 #define PALMAS_ENABLE2_RES_ASSIGN_CLK32KG                       0x10
1576 #define PALMAS_ENABLE2_RES_ASSIGN_CLK32KG_SHIFT                 4
1577 #define PALMAS_ENABLE2_RES_ASSIGN_SYSEN2                        0x08
1578 #define PALMAS_ENABLE2_RES_ASSIGN_SYSEN2_SHIFT                  3
1579 #define PALMAS_ENABLE2_RES_ASSIGN_SYSEN1                        0x04
1580 #define PALMAS_ENABLE2_RES_ASSIGN_SYSEN1_SHIFT                  2
1581 #define PALMAS_ENABLE2_RES_ASSIGN_REGEN2                        0x02
1582 #define PALMAS_ENABLE2_RES_ASSIGN_REGEN2_SHIFT                  1
1583 #define PALMAS_ENABLE2_RES_ASSIGN_REGEN1                        0x01
1584 #define PALMAS_ENABLE2_RES_ASSIGN_REGEN1_SHIFT                  0
1585
1586 /* Bit definitions for ENABLE2_SMPS_ASSIGN */
1587 #define PALMAS_ENABLE2_SMPS_ASSIGN_SMPS10                       0x80
1588 #define PALMAS_ENABLE2_SMPS_ASSIGN_SMPS10_SHIFT                 7
1589 #define PALMAS_ENABLE2_SMPS_ASSIGN_SMPS9                        0x40
1590 #define PALMAS_ENABLE2_SMPS_ASSIGN_SMPS9_SHIFT                  6
1591 #define PALMAS_ENABLE2_SMPS_ASSIGN_SMPS8                        0x20
1592 #define PALMAS_ENABLE2_SMPS_ASSIGN_SMPS8_SHIFT                  5
1593 #define PALMAS_ENABLE2_SMPS_ASSIGN_SMPS7                        0x10
1594 #define PALMAS_ENABLE2_SMPS_ASSIGN_SMPS7_SHIFT                  4
1595 #define PALMAS_ENABLE2_SMPS_ASSIGN_SMPS6                        0x08
1596 #define PALMAS_ENABLE2_SMPS_ASSIGN_SMPS6_SHIFT                  3
1597 #define PALMAS_ENABLE2_SMPS_ASSIGN_SMPS45                       0x04
1598 #define PALMAS_ENABLE2_SMPS_ASSIGN_SMPS45_SHIFT                 2
1599 #define PALMAS_ENABLE2_SMPS_ASSIGN_SMPS3                        0x02
1600 #define PALMAS_ENABLE2_SMPS_ASSIGN_SMPS3_SHIFT                  1
1601 #define PALMAS_ENABLE2_SMPS_ASSIGN_SMPS12                       0x01
1602 #define PALMAS_ENABLE2_SMPS_ASSIGN_SMPS12_SHIFT                 0
1603
1604 /* Bit definitions for ENABLE2_LDO_ASSIGN1 */
1605 #define PALMAS_ENABLE2_LDO_ASSIGN1_LDO8                         0x80
1606 #define PALMAS_ENABLE2_LDO_ASSIGN1_LDO8_SHIFT                   7
1607 #define PALMAS_ENABLE2_LDO_ASSIGN1_LDO7                         0x40
1608 #define PALMAS_ENABLE2_LDO_ASSIGN1_LDO7_SHIFT                   6
1609 #define PALMAS_ENABLE2_LDO_ASSIGN1_LDO6                         0x20
1610 #define PALMAS_ENABLE2_LDO_ASSIGN1_LDO6_SHIFT                   5
1611 #define PALMAS_ENABLE2_LDO_ASSIGN1_LDO5                         0x10
1612 #define PALMAS_ENABLE2_LDO_ASSIGN1_LDO5_SHIFT                   4
1613 #define PALMAS_ENABLE2_LDO_ASSIGN1_LDO4                         0x08
1614 #define PALMAS_ENABLE2_LDO_ASSIGN1_LDO4_SHIFT                   3
1615 #define PALMAS_ENABLE2_LDO_ASSIGN1_LDO3                         0x04
1616 #define PALMAS_ENABLE2_LDO_ASSIGN1_LDO3_SHIFT                   2
1617 #define PALMAS_ENABLE2_LDO_ASSIGN1_LDO2                         0x02
1618 #define PALMAS_ENABLE2_LDO_ASSIGN1_LDO2_SHIFT                   1
1619 #define PALMAS_ENABLE2_LDO_ASSIGN1_LDO1                         0x01
1620 #define PALMAS_ENABLE2_LDO_ASSIGN1_LDO1_SHIFT                   0
1621
1622 /* Bit definitions for ENABLE2_LDO_ASSIGN2 */
1623 #define PALMAS_ENABLE2_LDO_ASSIGN2_LDOUSB                       0x04
1624 #define PALMAS_ENABLE2_LDO_ASSIGN2_LDOUSB_SHIFT                 2
1625 #define PALMAS_ENABLE2_LDO_ASSIGN2_LDOLN                        0x02
1626 #define PALMAS_ENABLE2_LDO_ASSIGN2_LDOLN_SHIFT                  1
1627 #define PALMAS_ENABLE2_LDO_ASSIGN2_LDO9                         0x01
1628 #define PALMAS_ENABLE2_LDO_ASSIGN2_LDO9_SHIFT                   0
1629
1630 /* Bit definitions for REGEN3_CTRL */
1631 #define PALMAS_REGEN3_CTRL_STATUS                               0x10
1632 #define PALMAS_REGEN3_CTRL_STATUS_SHIFT                         4
1633 #define PALMAS_REGEN3_CTRL_MODE_SLEEP                           0x04
1634 #define PALMAS_REGEN3_CTRL_MODE_SLEEP_SHIFT                     2
1635 #define PALMAS_REGEN3_CTRL_MODE_ACTIVE                          0x01
1636 #define PALMAS_REGEN3_CTRL_MODE_ACTIVE_SHIFT                    0
1637
1638 /* Registers for function PAD_CONTROL */
1639 #define PALMAS_PU_PD_INPUT_CTRL1                                0x0
1640 #define PALMAS_PU_PD_INPUT_CTRL2                                0x1
1641 #define PALMAS_PU_PD_INPUT_CTRL3                                0x2
1642 #define PALMAS_OD_OUTPUT_CTRL                                   0x4
1643 #define PALMAS_POLARITY_CTRL                                    0x5
1644 #define PALMAS_PRIMARY_SECONDARY_PAD1                           0x6
1645 #define PALMAS_PRIMARY_SECONDARY_PAD2                           0x7
1646 #define PALMAS_I2C_SPI                                          0x8
1647 #define PALMAS_PU_PD_INPUT_CTRL4                                0x9
1648 #define PALMAS_PRIMARY_SECONDARY_PAD3                           0xA
1649
1650 /* Bit definitions for PU_PD_INPUT_CTRL1 */
1651 #define PALMAS_PU_PD_INPUT_CTRL1_RESET_IN_PD                    0x40
1652 #define PALMAS_PU_PD_INPUT_CTRL1_RESET_IN_PD_SHIFT              6
1653 #define PALMAS_PU_PD_INPUT_CTRL1_GPADC_START_PU                 0x20
1654 #define PALMAS_PU_PD_INPUT_CTRL1_GPADC_START_PU_SHIFT           5
1655 #define PALMAS_PU_PD_INPUT_CTRL1_GPADC_START_PD                 0x10
1656 #define PALMAS_PU_PD_INPUT_CTRL1_GPADC_START_PD_SHIFT           4
1657 #define PALMAS_PU_PD_INPUT_CTRL1_PWRDOWN_PD                     0x04
1658 #define PALMAS_PU_PD_INPUT_CTRL1_PWRDOWN_PD_SHIFT               2
1659 #define PALMAS_PU_PD_INPUT_CTRL1_NRESWARM_PU                    0x02
1660 #define PALMAS_PU_PD_INPUT_CTRL1_NRESWARM_PU_SHIFT              1
1661
1662 /* Bit definitions for PU_PD_INPUT_CTRL2 */
1663 #define PALMAS_PU_PD_INPUT_CTRL2_ENABLE2_PU                     0x20
1664 #define PALMAS_PU_PD_INPUT_CTRL2_ENABLE2_PU_SHIFT               5
1665 #define PALMAS_PU_PD_INPUT_CTRL2_ENABLE2_PD                     0x10
1666 #define PALMAS_PU_PD_INPUT_CTRL2_ENABLE2_PD_SHIFT               4
1667 #define PALMAS_PU_PD_INPUT_CTRL2_ENABLE1_PU                     0x08
1668 #define PALMAS_PU_PD_INPUT_CTRL2_ENABLE1_PU_SHIFT               3
1669 #define PALMAS_PU_PD_INPUT_CTRL2_ENABLE1_PD                     0x04
1670 #define PALMAS_PU_PD_INPUT_CTRL2_ENABLE1_PD_SHIFT               2
1671 #define PALMAS_PU_PD_INPUT_CTRL2_NSLEEP_PU                      0x02
1672 #define PALMAS_PU_PD_INPUT_CTRL2_NSLEEP_PU_SHIFT                1
1673 #define PALMAS_PU_PD_INPUT_CTRL2_NSLEEP_PD                      0x01
1674 #define PALMAS_PU_PD_INPUT_CTRL2_NSLEEP_PD_SHIFT                0
1675
1676 /* Bit definitions for PU_PD_INPUT_CTRL3 */
1677 #define PALMAS_PU_PD_INPUT_CTRL3_ACOK_PD                        0x40
1678 #define PALMAS_PU_PD_INPUT_CTRL3_ACOK_PD_SHIFT                  6
1679 #define PALMAS_PU_PD_INPUT_CTRL3_CHRG_DET_N_PD                  0x10
1680 #define PALMAS_PU_PD_INPUT_CTRL3_CHRG_DET_N_PD_SHIFT            4
1681 #define PALMAS_PU_PD_INPUT_CTRL3_POWERHOLD_PD                   0x04
1682 #define PALMAS_PU_PD_INPUT_CTRL3_POWERHOLD_PD_SHIFT             2
1683 #define PALMAS_PU_PD_INPUT_CTRL3_MSECURE_PD                     0x01
1684 #define PALMAS_PU_PD_INPUT_CTRL3_MSECURE_PD_SHIFT               0
1685
1686 /* Bit definitions for OD_OUTPUT_CTRL */
1687 #define PALMAS_OD_OUTPUT_CTRL_PWM_2_OD                          0x80
1688 #define PALMAS_OD_OUTPUT_CTRL_PWM_2_OD_SHIFT                    7
1689 #define PALMAS_OD_OUTPUT_CTRL_VBUSDET_OD                        0x40
1690 #define PALMAS_OD_OUTPUT_CTRL_VBUSDET_OD_SHIFT                  6
1691 #define PALMAS_OD_OUTPUT_CTRL_PWM_1_OD                          0x20
1692 #define PALMAS_OD_OUTPUT_CTRL_PWM_1_OD_SHIFT                    5
1693 #define PALMAS_OD_OUTPUT_CTRL_INT_OD                            0x08
1694 #define PALMAS_OD_OUTPUT_CTRL_INT_OD_SHIFT                      3
1695
1696 /* Bit definitions for POLARITY_CTRL */
1697 #define PALMAS_POLARITY_CTRL_INT_POLARITY                       0x80
1698 #define PALMAS_POLARITY_CTRL_INT_POLARITY_SHIFT                 7
1699 #define PALMAS_POLARITY_CTRL_ENABLE2_POLARITY                   0x40
1700 #define PALMAS_POLARITY_CTRL_ENABLE2_POLARITY_SHIFT             6
1701 #define PALMAS_POLARITY_CTRL_ENABLE1_POLARITY                   0x20
1702 #define PALMAS_POLARITY_CTRL_ENABLE1_POLARITY_SHIFT             5
1703 #define PALMAS_POLARITY_CTRL_NSLEEP_POLARITY                    0x10
1704 #define PALMAS_POLARITY_CTRL_NSLEEP_POLARITY_SHIFT              4
1705 #define PALMAS_POLARITY_CTRL_RESET_IN_POLARITY                  0x08
1706 #define PALMAS_POLARITY_CTRL_RESET_IN_POLARITY_SHIFT            3
1707 #define PALMAS_POLARITY_CTRL_GPIO_3_CHRG_DET_N_POLARITY         0x04
1708 #define PALMAS_POLARITY_CTRL_GPIO_3_CHRG_DET_N_POLARITY_SHIFT   2
1709 #define PALMAS_POLARITY_CTRL_POWERGOOD_USB_PSEL_POLARITY        0x02
1710 #define PALMAS_POLARITY_CTRL_POWERGOOD_USB_PSEL_POLARITY_SHIFT  1
1711 #define PALMAS_POLARITY_CTRL_PWRDOWN_POLARITY                   0x01
1712 #define PALMAS_POLARITY_CTRL_PWRDOWN_POLARITY_SHIFT             0
1713
1714 /* Bit definitions for PRIMARY_SECONDARY_PAD1 */
1715 #define PALMAS_PRIMARY_SECONDARY_PAD1_GPIO_3                    0x80
1716 #define PALMAS_PRIMARY_SECONDARY_PAD1_GPIO_3_SHIFT              7
1717 #define PALMAS_PRIMARY_SECONDARY_PAD1_GPIO_2_MASK               0x60
1718 #define PALMAS_PRIMARY_SECONDARY_PAD1_GPIO_2_SHIFT              5
1719 #define PALMAS_PRIMARY_SECONDARY_PAD1_GPIO_1_MASK               0x18
1720 #define PALMAS_PRIMARY_SECONDARY_PAD1_GPIO_1_SHIFT              3
1721 #define PALMAS_PRIMARY_SECONDARY_PAD1_GPIO_0                    0x04
1722 #define PALMAS_PRIMARY_SECONDARY_PAD1_GPIO_0_SHIFT              2
1723 #define PALMAS_PRIMARY_SECONDARY_PAD1_VAC                       0x02
1724 #define PALMAS_PRIMARY_SECONDARY_PAD1_VAC_SHIFT                 1
1725 #define PALMAS_PRIMARY_SECONDARY_PAD1_POWERGOOD                 0x01
1726 #define PALMAS_PRIMARY_SECONDARY_PAD1_POWERGOOD_SHIFT           0
1727
1728 /* Bit definitions for PRIMARY_SECONDARY_PAD2 */
1729 #define PALMAS_PRIMARY_SECONDARY_PAD2_GPIO_7_MASK               0x30
1730 #define PALMAS_PRIMARY_SECONDARY_PAD2_GPIO_7_SHIFT              4
1731 #define PALMAS_PRIMARY_SECONDARY_PAD2_GPIO_6                    0x08
1732 #define PALMAS_PRIMARY_SECONDARY_PAD2_GPIO_6_SHIFT              3
1733 #define PALMAS_PRIMARY_SECONDARY_PAD2_GPIO_5_MASK               0x06
1734 #define PALMAS_PRIMARY_SECONDARY_PAD2_GPIO_5_SHIFT              1
1735 #define PALMAS_PRIMARY_SECONDARY_PAD2_GPIO_4                    0x01
1736 #define PALMAS_PRIMARY_SECONDARY_PAD2_GPIO_4_SHIFT              0
1737
1738 /* Bit definitions for I2C_SPI */
1739 #define PALMAS_I2C_SPI_I2C2OTP_EN                               0x80
1740 #define PALMAS_I2C_SPI_I2C2OTP_EN_SHIFT                         7
1741 #define PALMAS_I2C_SPI_I2C2OTP_PAGESEL                          0x40
1742 #define PALMAS_I2C_SPI_I2C2OTP_PAGESEL_SHIFT                    6
1743 #define PALMAS_I2C_SPI_ID_I2C2                                  0x20
1744 #define PALMAS_I2C_SPI_ID_I2C2_SHIFT                            5
1745 #define PALMAS_I2C_SPI_I2C_SPI                                  0x10
1746 #define PALMAS_I2C_SPI_I2C_SPI_SHIFT                            4
1747 #define PALMAS_I2C_SPI_ID_I2C1_MASK                             0x0f
1748 #define PALMAS_I2C_SPI_ID_I2C1_SHIFT                            0
1749
1750 /* Bit definitions for PU_PD_INPUT_CTRL4 */
1751 #define PALMAS_PU_PD_INPUT_CTRL4_DVFS2_DAT_PD                   0x40
1752 #define PALMAS_PU_PD_INPUT_CTRL4_DVFS2_DAT_PD_SHIFT             6
1753 #define PALMAS_PU_PD_INPUT_CTRL4_DVFS2_CLK_PD                   0x10
1754 #define PALMAS_PU_PD_INPUT_CTRL4_DVFS2_CLK_PD_SHIFT             4
1755 #define PALMAS_PU_PD_INPUT_CTRL4_DVFS1_DAT_PD                   0x04
1756 #define PALMAS_PU_PD_INPUT_CTRL4_DVFS1_DAT_PD_SHIFT             2
1757 #define PALMAS_PU_PD_INPUT_CTRL4_DVFS1_CLK_PD                   0x01
1758 #define PALMAS_PU_PD_INPUT_CTRL4_DVFS1_CLK_PD_SHIFT             0
1759
1760 /* Bit definitions for PRIMARY_SECONDARY_PAD3 */
1761 #define PALMAS_PRIMARY_SECONDARY_PAD3_DVFS2                     0x02
1762 #define PALMAS_PRIMARY_SECONDARY_PAD3_DVFS2_SHIFT               1
1763 #define PALMAS_PRIMARY_SECONDARY_PAD3_DVFS1                     0x01
1764 #define PALMAS_PRIMARY_SECONDARY_PAD3_DVFS1_SHIFT               0
1765
1766 /* Registers for function LED_PWM */
1767 #define PALMAS_LED_PERIOD_CTRL                                  0x0
1768 #define PALMAS_LED_CTRL                                         0x1
1769 #define PALMAS_PWM_CTRL1                                        0x2
1770 #define PALMAS_PWM_CTRL2                                        0x3
1771
1772 /* Bit definitions for LED_PERIOD_CTRL */
1773 #define PALMAS_LED_PERIOD_CTRL_LED_2_PERIOD_MASK                0x38
1774 #define PALMAS_LED_PERIOD_CTRL_LED_2_PERIOD_SHIFT               3
1775 #define PALMAS_LED_PERIOD_CTRL_LED_1_PERIOD_MASK                0x07
1776 #define PALMAS_LED_PERIOD_CTRL_LED_1_PERIOD_SHIFT               0
1777
1778 /* Bit definitions for LED_CTRL */
1779 #define PALMAS_LED_CTRL_LED_2_SEQ                               0x20
1780 #define PALMAS_LED_CTRL_LED_2_SEQ_SHIFT                         5
1781 #define PALMAS_LED_CTRL_LED_1_SEQ                               0x10
1782 #define PALMAS_LED_CTRL_LED_1_SEQ_SHIFT                         4
1783 #define PALMAS_LED_CTRL_LED_2_ON_TIME_MASK                      0x0c
1784 #define PALMAS_LED_CTRL_LED_2_ON_TIME_SHIFT                     2
1785 #define PALMAS_LED_CTRL_LED_1_ON_TIME_MASK                      0x03
1786 #define PALMAS_LED_CTRL_LED_1_ON_TIME_SHIFT                     0
1787
1788 /* Bit definitions for PWM_CTRL1 */
1789 #define PALMAS_PWM_CTRL1_PWM_FREQ_EN                            0x02
1790 #define PALMAS_PWM_CTRL1_PWM_FREQ_EN_SHIFT                      1
1791 #define PALMAS_PWM_CTRL1_PWM_FREQ_SEL                           0x01
1792 #define PALMAS_PWM_CTRL1_PWM_FREQ_SEL_SHIFT                     0
1793
1794 /* Bit definitions for PWM_CTRL2 */
1795 #define PALMAS_PWM_CTRL2_PWM_DUTY_SEL_MASK                      0xff
1796 #define PALMAS_PWM_CTRL2_PWM_DUTY_SEL_SHIFT                     0
1797
1798 /* Maximum INT mask/edge regsiter */
1799 #define PALMAS_MAX_INTERRUPT_MASK_REG                           4
1800 #define PALMAS_MAX_INTERRUPT_EDGE_REG                           8
1801
1802 /* Registers for function INTERRUPT */
1803 #define PALMAS_INT1_STATUS                                      0x0
1804 #define PALMAS_INT1_MASK                                        0x1
1805 #define PALMAS_INT1_LINE_STATE                                  0x2
1806 #define PALMAS_INT1_EDGE_DETECT1_RESERVED                       0x3
1807 #define PALMAS_INT1_EDGE_DETECT2_RESERVED                       0x4
1808 #define PALMAS_INT2_STATUS                                      0x5
1809 #define PALMAS_INT2_MASK                                        0x6
1810 #define PALMAS_INT2_LINE_STATE                                  0x7
1811 #define PALMAS_INT2_EDGE_DETECT1_RESERVED                       0x8
1812 #define PALMAS_INT2_EDGE_DETECT2_RESERVED                       0x9
1813 #define PALMAS_INT3_STATUS                                      0xA
1814 #define PALMAS_INT3_MASK                                        0xB
1815 #define PALMAS_INT3_LINE_STATE                                  0xC
1816 #define PALMAS_INT3_EDGE_DETECT1_RESERVED                       0xD
1817 #define PALMAS_INT3_EDGE_DETECT2_RESERVED                       0xE
1818 #define PALMAS_INT4_STATUS                                      0xF
1819 #define PALMAS_INT4_MASK                                        0x10
1820 #define PALMAS_INT4_LINE_STATE                                  0x11
1821 #define PALMAS_INT4_EDGE_DETECT1                                0x12
1822 #define PALMAS_INT4_EDGE_DETECT2                                0x13
1823 #define PALMAS_INT_CTRL                                         0x14
1824
1825 /* Bit definitions for INT1_STATUS */
1826 #define PALMAS_INT1_STATUS_VBAT_MON                             0x80
1827 #define PALMAS_INT1_STATUS_VBAT_MON_SHIFT                       7
1828 #define PALMAS_INT1_STATUS_VSYS_MON                             0x40
1829 #define PALMAS_INT1_STATUS_VSYS_MON_SHIFT                       6
1830 #define PALMAS_INT1_STATUS_HOTDIE                               0x20
1831 #define PALMAS_INT1_STATUS_HOTDIE_SHIFT                         5
1832 #define PALMAS_INT1_STATUS_PWRDOWN                              0x10
1833 #define PALMAS_INT1_STATUS_PWRDOWN_SHIFT                        4
1834 #define PALMAS_INT1_STATUS_RPWRON                               0x08
1835 #define PALMAS_INT1_STATUS_RPWRON_SHIFT                         3
1836 #define PALMAS_INT1_STATUS_LONG_PRESS_KEY                       0x04
1837 #define PALMAS_INT1_STATUS_LONG_PRESS_KEY_SHIFT                 2
1838 #define PALMAS_INT1_STATUS_PWRON                                0x02
1839 #define PALMAS_INT1_STATUS_PWRON_SHIFT                          1
1840 #define PALMAS_INT1_STATUS_CHARG_DET_N_VBUS_OVV                 0x01
1841 #define PALMAS_INT1_STATUS_CHARG_DET_N_VBUS_OVV_SHIFT           0
1842
1843 /* Bit definitions for INT1_MASK */
1844 #define PALMAS_INT1_MASK_VBAT_MON                               0x80
1845 #define PALMAS_INT1_MASK_VBAT_MON_SHIFT                         7
1846 #define PALMAS_INT1_MASK_VSYS_MON                               0x40
1847 #define PALMAS_INT1_MASK_VSYS_MON_SHIFT                         6
1848 #define PALMAS_INT1_MASK_HOTDIE                                 0x20
1849 #define PALMAS_INT1_MASK_HOTDIE_SHIFT                           5
1850 #define PALMAS_INT1_MASK_PWRDOWN                                0x10
1851 #define PALMAS_INT1_MASK_PWRDOWN_SHIFT                          4
1852 #define PALMAS_INT1_MASK_RPWRON                                 0x08
1853 #define PALMAS_INT1_MASK_RPWRON_SHIFT                           3
1854 #define PALMAS_INT1_MASK_LONG_PRESS_KEY                         0x04
1855 #define PALMAS_INT1_MASK_LONG_PRESS_KEY_SHIFT                   2
1856 #define PALMAS_INT1_MASK_PWRON                                  0x02
1857 #define PALMAS_INT1_MASK_PWRON_SHIFT                            1
1858 #define PALMAS_INT1_MASK_CHARG_DET_N_VBUS_OVV                   0x01
1859 #define PALMAS_INT1_MASK_CHARG_DET_N_VBUS_OVV_SHIFT             0
1860
1861 /* Bit definitions for INT1_LINE_STATE */
1862 #define PALMAS_INT1_LINE_STATE_VBAT_MON                         0x80
1863 #define PALMAS_INT1_LINE_STATE_VBAT_MON_SHIFT                   7
1864 #define PALMAS_INT1_LINE_STATE_VSYS_MON                         0x40
1865 #define PALMAS_INT1_LINE_STATE_VSYS_MON_SHIFT                   6
1866 #define PALMAS_INT1_LINE_STATE_HOTDIE                           0x20
1867 #define PALMAS_INT1_LINE_STATE_HOTDIE_SHIFT                     5
1868 #define PALMAS_INT1_LINE_STATE_PWRDOWN                          0x10
1869 #define PALMAS_INT1_LINE_STATE_PWRDOWN_SHIFT                    4
1870 #define PALMAS_INT1_LINE_STATE_RPWRON                           0x08
1871 #define PALMAS_INT1_LINE_STATE_RPWRON_SHIFT                     3
1872 #define PALMAS_INT1_LINE_STATE_LONG_PRESS_KEY                   0x04
1873 #define PALMAS_INT1_LINE_STATE_LONG_PRESS_KEY_SHIFT             2
1874 #define PALMAS_INT1_LINE_STATE_PWRON                            0x02
1875 #define PALMAS_INT1_LINE_STATE_PWRON_SHIFT                      1
1876 #define PALMAS_INT1_LINE_STATE_CHARG_DET_N_VBUS_OVV             0x01
1877 #define PALMAS_INT1_LINE_STATE_CHARG_DET_N_VBUS_OVV_SHIFT       0
1878
1879 /* Bit definitions for INT2_STATUS */
1880 #define PALMAS_INT2_STATUS_VAC_ACOK                             0x80
1881 #define PALMAS_INT2_STATUS_VAC_ACOK_SHIFT                       7
1882 #define PALMAS_INT2_STATUS_SHORT                                0x40
1883 #define PALMAS_INT2_STATUS_SHORT_SHIFT                          6
1884 #define PALMAS_INT2_STATUS_FBI_BB                               0x20
1885 #define PALMAS_INT2_STATUS_FBI_BB_SHIFT                         5
1886 #define PALMAS_INT2_STATUS_RESET_IN                             0x10
1887 #define PALMAS_INT2_STATUS_RESET_IN_SHIFT                       4
1888 #define PALMAS_INT2_STATUS_BATREMOVAL                           0x08
1889 #define PALMAS_INT2_STATUS_BATREMOVAL_SHIFT                     3
1890 #define PALMAS_INT2_STATUS_WDT                                  0x04
1891 #define PALMAS_INT2_STATUS_WDT_SHIFT                            2
1892 #define PALMAS_INT2_STATUS_RTC_TIMER                            0x02
1893 #define PALMAS_INT2_STATUS_RTC_TIMER_SHIFT                      1
1894 #define PALMAS_INT2_STATUS_RTC_ALARM                            0x01
1895 #define PALMAS_INT2_STATUS_RTC_ALARM_SHIFT                      0
1896
1897 /* Bit definitions for INT2_MASK */
1898 #define PALMAS_INT2_MASK_VAC_ACOK                               0x80
1899 #define PALMAS_INT2_MASK_VAC_ACOK_SHIFT                         7
1900 #define PALMAS_INT2_MASK_SHORT                                  0x40
1901 #define PALMAS_INT2_MASK_SHORT_SHIFT                            6
1902 #define PALMAS_INT2_MASK_FBI_BB                                 0x20
1903 #define PALMAS_INT2_MASK_FBI_BB_SHIFT                           5
1904 #define PALMAS_INT2_MASK_RESET_IN                               0x10
1905 #define PALMAS_INT2_MASK_RESET_IN_SHIFT                         4
1906 #define PALMAS_INT2_MASK_BATREMOVAL                             0x08
1907 #define PALMAS_INT2_MASK_BATREMOVAL_SHIFT                       3
1908 #define PALMAS_INT2_MASK_WDT                                    0x04
1909 #define PALMAS_INT2_MASK_WDT_SHIFT                              2
1910 #define PALMAS_INT2_MASK_RTC_TIMER                              0x02
1911 #define PALMAS_INT2_MASK_RTC_TIMER_SHIFT                        1
1912 #define PALMAS_INT2_MASK_RTC_ALARM                              0x01
1913 #define PALMAS_INT2_MASK_RTC_ALARM_SHIFT                        0
1914
1915 /* Bit definitions for INT2_LINE_STATE */
1916 #define PALMAS_INT2_LINE_STATE_VAC_ACOK                         0x80
1917 #define PALMAS_INT2_LINE_STATE_VAC_ACOK_SHIFT                   7
1918 #define PALMAS_INT2_LINE_STATE_SHORT                            0x40
1919 #define PALMAS_INT2_LINE_STATE_SHORT_SHIFT                      6
1920 #define PALMAS_INT2_LINE_STATE_FBI_BB                           0x20
1921 #define PALMAS_INT2_LINE_STATE_FBI_BB_SHIFT                     5
1922 #define PALMAS_INT2_LINE_STATE_RESET_IN                         0x10
1923 #define PALMAS_INT2_LINE_STATE_RESET_IN_SHIFT                   4
1924 #define PALMAS_INT2_LINE_STATE_BATREMOVAL                       0x08
1925 #define PALMAS_INT2_LINE_STATE_BATREMOVAL_SHIFT                 3
1926 #define PALMAS_INT2_LINE_STATE_WDT                              0x04
1927 #define PALMAS_INT2_LINE_STATE_WDT_SHIFT                        2
1928 #define PALMAS_INT2_LINE_STATE_RTC_TIMER                        0x02
1929 #define PALMAS_INT2_LINE_STATE_RTC_TIMER_SHIFT                  1
1930 #define PALMAS_INT2_LINE_STATE_RTC_ALARM                        0x01
1931 #define PALMAS_INT2_LINE_STATE_RTC_ALARM_SHIFT                  0
1932
1933 /* Bit definitions for INT3_STATUS */
1934 #define PALMAS_INT3_STATUS_VBUS                                 0x80
1935 #define PALMAS_INT3_STATUS_VBUS_SHIFT                           7
1936 #define PALMAS_INT3_STATUS_VBUS_OTG                             0x40
1937 #define PALMAS_INT3_STATUS_VBUS_OTG_SHIFT                       6
1938 #define PALMAS_INT3_STATUS_ID                                   0x20
1939 #define PALMAS_INT3_STATUS_ID_SHIFT                             5
1940 #define PALMAS_INT3_STATUS_ID_OTG                               0x10
1941 #define PALMAS_INT3_STATUS_ID_OTG_SHIFT                         4
1942 #define PALMAS_INT3_STATUS_GPADC_EOC_RT                         0x08
1943 #define PALMAS_INT3_STATUS_GPADC_EOC_RT_SHIFT                   3
1944 #define PALMAS_INT3_STATUS_GPADC_EOC_SW                         0x04
1945 #define PALMAS_INT3_STATUS_GPADC_EOC_SW_SHIFT                   2
1946 #define PALMAS_INT3_STATUS_GPADC_AUTO_1                         0x02
1947 #define PALMAS_INT3_STATUS_GPADC_AUTO_1_SHIFT                   1
1948 #define PALMAS_INT3_STATUS_GPADC_AUTO_0                         0x01
1949 #define PALMAS_INT3_STATUS_GPADC_AUTO_0_SHIFT                   0
1950
1951 /* Bit definitions for INT3_MASK */
1952 #define PALMAS_INT3_MASK_VBUS                                   0x80
1953 #define PALMAS_INT3_MASK_VBUS_SHIFT                             7
1954 #define PALMAS_INT3_MASK_VBUS_OTG                               0x40
1955 #define PALMAS_INT3_MASK_VBUS_OTG_SHIFT                         6
1956 #define PALMAS_INT3_MASK_ID                                     0x20
1957 #define PALMAS_INT3_MASK_ID_SHIFT                               5
1958 #define PALMAS_INT3_MASK_ID_OTG                                 0x10
1959 #define PALMAS_INT3_MASK_ID_OTG_SHIFT                           4
1960 #define PALMAS_INT3_MASK_GPADC_EOC_RT                           0x08
1961 #define PALMAS_INT3_MASK_GPADC_EOC_RT_SHIFT                     3
1962 #define PALMAS_INT3_MASK_GPADC_EOC_SW                           0x04
1963 #define PALMAS_INT3_MASK_GPADC_EOC_SW_SHIFT                     2
1964 #define PALMAS_INT3_MASK_GPADC_AUTO_1                           0x02
1965 #define PALMAS_INT3_MASK_GPADC_AUTO_1_SHIFT                     1
1966 #define PALMAS_INT3_MASK_GPADC_AUTO_0                           0x01
1967 #define PALMAS_INT3_MASK_GPADC_AUTO_0_SHIFT                     0
1968
1969 /* Bit definitions for INT3_LINE_STATE */
1970 #define PALMAS_INT3_LINE_STATE_VBUS                             0x80
1971 #define PALMAS_INT3_LINE_STATE_VBUS_SHIFT                       7
1972 #define PALMAS_INT3_LINE_STATE_VBUS_OTG                         0x40
1973 #define PALMAS_INT3_LINE_STATE_VBUS_OTG_SHIFT                   6
1974 #define PALMAS_INT3_LINE_STATE_ID                               0x20
1975 #define PALMAS_INT3_LINE_STATE_ID_SHIFT                         5
1976 #define PALMAS_INT3_LINE_STATE_ID_OTG                           0x10
1977 #define PALMAS_INT3_LINE_STATE_ID_OTG_SHIFT                     4
1978 #define PALMAS_INT3_LINE_STATE_GPADC_EOC_RT                     0x08
1979 #define PALMAS_INT3_LINE_STATE_GPADC_EOC_RT_SHIFT               3
1980 #define PALMAS_INT3_LINE_STATE_GPADC_EOC_SW                     0x04
1981 #define PALMAS_INT3_LINE_STATE_GPADC_EOC_SW_SHIFT               2
1982 #define PALMAS_INT3_LINE_STATE_GPADC_AUTO_1                     0x02
1983 #define PALMAS_INT3_LINE_STATE_GPADC_AUTO_1_SHIFT               1
1984 #define PALMAS_INT3_LINE_STATE_GPADC_AUTO_0                     0x01
1985 #define PALMAS_INT3_LINE_STATE_GPADC_AUTO_0_SHIFT               0
1986
1987 /* Bit definitions for INT4_STATUS */
1988 #define PALMAS_INT4_STATUS_GPIO_7                               0x80
1989 #define PALMAS_INT4_STATUS_GPIO_7_SHIFT                         7
1990 #define PALMAS_INT4_STATUS_GPIO_6                               0x40
1991 #define PALMAS_INT4_STATUS_GPIO_6_SHIFT                         6
1992 #define PALMAS_INT4_STATUS_GPIO_5                               0x20
1993 #define PALMAS_INT4_STATUS_GPIO_5_SHIFT                         5
1994 #define PALMAS_INT4_STATUS_GPIO_4                               0x10
1995 #define PALMAS_INT4_STATUS_GPIO_4_SHIFT                         4
1996 #define PALMAS_INT4_STATUS_GPIO_3                               0x08
1997 #define PALMAS_INT4_STATUS_GPIO_3_SHIFT                         3
1998 #define PALMAS_INT4_STATUS_GPIO_2                               0x04
1999 #define PALMAS_INT4_STATUS_GPIO_2_SHIFT                         2
2000 #define PALMAS_INT4_STATUS_GPIO_1                               0x02
2001 #define PALMAS_INT4_STATUS_GPIO_1_SHIFT                         1
2002 #define PALMAS_INT4_STATUS_GPIO_0                               0x01
2003 #define PALMAS_INT4_STATUS_GPIO_0_SHIFT                         0
2004
2005 /* Bit definitions for INT4_MASK */
2006 #define PALMAS_INT4_MASK_GPIO_7                                 0x80
2007 #define PALMAS_INT4_MASK_GPIO_7_SHIFT                           7
2008 #define PALMAS_INT4_MASK_GPIO_6                                 0x40
2009 #define PALMAS_INT4_MASK_GPIO_6_SHIFT                           6
2010 #define PALMAS_INT4_MASK_GPIO_5                                 0x20
2011 #define PALMAS_INT4_MASK_GPIO_5_SHIFT                           5
2012 #define PALMAS_INT4_MASK_GPIO_4                                 0x10
2013 #define PALMAS_INT4_MASK_GPIO_4_SHIFT                           4
2014 #define PALMAS_INT4_MASK_GPIO_3                                 0x08
2015 #define PALMAS_INT4_MASK_GPIO_3_SHIFT                           3
2016 #define PALMAS_INT4_MASK_GPIO_2                                 0x04
2017 #define PALMAS_INT4_MASK_GPIO_2_SHIFT                           2
2018 #define PALMAS_INT4_MASK_GPIO_1                                 0x02
2019 #define PALMAS_INT4_MASK_GPIO_1_SHIFT                           1
2020 #define PALMAS_INT4_MASK_GPIO_0                                 0x01
2021 #define PALMAS_INT4_MASK_GPIO_0_SHIFT                           0
2022
2023 /* Bit definitions for INT4_LINE_STATE */
2024 #define PALMAS_INT4_LINE_STATE_GPIO_7                           0x80
2025 #define PALMAS_INT4_LINE_STATE_GPIO_7_SHIFT                     7
2026 #define PALMAS_INT4_LINE_STATE_GPIO_6                           0x40
2027 #define PALMAS_INT4_LINE_STATE_GPIO_6_SHIFT                     6
2028 #define PALMAS_INT4_LINE_STATE_GPIO_5                           0x20
2029 #define PALMAS_INT4_LINE_STATE_GPIO_5_SHIFT                     5
2030 #define PALMAS_INT4_LINE_STATE_GPIO_4                           0x10
2031 #define PALMAS_INT4_LINE_STATE_GPIO_4_SHIFT                     4
2032 #define PALMAS_INT4_LINE_STATE_GPIO_3                           0x08
2033 #define PALMAS_INT4_LINE_STATE_GPIO_3_SHIFT                     3
2034 #define PALMAS_INT4_LINE_STATE_GPIO_2                           0x04
2035 #define PALMAS_INT4_LINE_STATE_GPIO_2_SHIFT                     2
2036 #define PALMAS_INT4_LINE_STATE_GPIO_1                           0x02
2037 #define PALMAS_INT4_LINE_STATE_GPIO_1_SHIFT                     1
2038 #define PALMAS_INT4_LINE_STATE_GPIO_0                           0x01
2039 #define PALMAS_INT4_LINE_STATE_GPIO_0_SHIFT                     0
2040
2041 /* Bit definitions for INT4_EDGE_DETECT1 */
2042 #define PALMAS_INT4_EDGE_DETECT1_GPIO_3_RISING                  0x80
2043 #define PALMAS_INT4_EDGE_DETECT1_GPIO_3_RISING_SHIFT            7
2044 #define PALMAS_INT4_EDGE_DETECT1_GPIO_3_FALLING                 0x40
2045 #define PALMAS_INT4_EDGE_DETECT1_GPIO_3_FALLING_SHIFT           6
2046 #define PALMAS_INT4_EDGE_DETECT1_GPIO_2_RISING                  0x20
2047 #define PALMAS_INT4_EDGE_DETECT1_GPIO_2_RISING_SHIFT            5
2048 #define PALMAS_INT4_EDGE_DETECT1_GPIO_2_FALLING                 0x10
2049 #define PALMAS_INT4_EDGE_DETECT1_GPIO_2_FALLING_SHIFT           4
2050 #define PALMAS_INT4_EDGE_DETECT1_GPIO_1_RISING                  0x08
2051 #define PALMAS_INT4_EDGE_DETECT1_GPIO_1_RISING_SHIFT            3
2052 #define PALMAS_INT4_EDGE_DETECT1_GPIO_1_FALLING                 0x04
2053 #define PALMAS_INT4_EDGE_DETECT1_GPIO_1_FALLING_SHIFT           2
2054 #define PALMAS_INT4_EDGE_DETECT1_GPIO_0_RISING                  0x02
2055 #define PALMAS_INT4_EDGE_DETECT1_GPIO_0_RISING_SHIFT            1
2056 #define PALMAS_INT4_EDGE_DETECT1_GPIO_0_FALLING                 0x01
2057 #define PALMAS_INT4_EDGE_DETECT1_GPIO_0_FALLING_SHIFT           0
2058
2059 /* Bit definitions for INT4_EDGE_DETECT2 */
2060 #define PALMAS_INT4_EDGE_DETECT2_GPIO_7_RISING                  0x80
2061 #define PALMAS_INT4_EDGE_DETECT2_GPIO_7_RISING_SHIFT            7
2062 #define PALMAS_INT4_EDGE_DETECT2_GPIO_7_FALLING                 0x40
2063 #define PALMAS_INT4_EDGE_DETECT2_GPIO_7_FALLING_SHIFT           6
2064 #define PALMAS_INT4_EDGE_DETECT2_GPIO_6_RISING                  0x20
2065 #define PALMAS_INT4_EDGE_DETECT2_GPIO_6_RISING_SHIFT            5
2066 #define PALMAS_INT4_EDGE_DETECT2_GPIO_6_FALLING                 0x10
2067 #define PALMAS_INT4_EDGE_DETECT2_GPIO_6_FALLING_SHIFT           4
2068 #define PALMAS_INT4_EDGE_DETECT2_GPIO_5_RISING                  0x08
2069 #define PALMAS_INT4_EDGE_DETECT2_GPIO_5_RISING_SHIFT            3
2070 #define PALMAS_INT4_EDGE_DETECT2_GPIO_5_FALLING                 0x04
2071 #define PALMAS_INT4_EDGE_DETECT2_GPIO_5_FALLING_SHIFT           2
2072 #define PALMAS_INT4_EDGE_DETECT2_GPIO_4_RISING                  0x02
2073 #define PALMAS_INT4_EDGE_DETECT2_GPIO_4_RISING_SHIFT            1
2074 #define PALMAS_INT4_EDGE_DETECT2_GPIO_4_FALLING                 0x01
2075 #define PALMAS_INT4_EDGE_DETECT2_GPIO_4_FALLING_SHIFT           0
2076
2077 /* Bit definitions for INT_CTRL */
2078 #define PALMAS_INT_CTRL_INT_PENDING                             0x04
2079 #define PALMAS_INT_CTRL_INT_PENDING_SHIFT                       2
2080 #define PALMAS_INT_CTRL_INT_CLEAR                               0x01
2081 #define PALMAS_INT_CTRL_INT_CLEAR_SHIFT                         0
2082
2083 /* Registers for function USB_OTG */
2084 #define PALMAS_USB_WAKEUP                                       0x3
2085 #define PALMAS_USB_VBUS_CTRL_SET                                0x4
2086 #define PALMAS_USB_VBUS_CTRL_CLR                                0x5
2087 #define PALMAS_USB_ID_CTRL_SET                                  0x6
2088 #define PALMAS_USB_ID_CTRL_CLEAR                                0x7
2089 #define PALMAS_USB_VBUS_INT_SRC                                 0x8
2090 #define PALMAS_USB_VBUS_INT_LATCH_SET                           0x9
2091 #define PALMAS_USB_VBUS_INT_LATCH_CLR                           0xA
2092 #define PALMAS_USB_VBUS_INT_EN_LO_SET                           0xB
2093 #define PALMAS_USB_VBUS_INT_EN_LO_CLR                           0xC
2094 #define PALMAS_USB_VBUS_INT_EN_HI_SET                           0xD
2095 #define PALMAS_USB_VBUS_INT_EN_HI_CLR                           0xE
2096 #define PALMAS_USB_ID_INT_SRC                                   0xF
2097 #define PALMAS_USB_ID_INT_LATCH_SET                             0x10
2098 #define PALMAS_USB_ID_INT_LATCH_CLR                             0x11
2099 #define PALMAS_USB_ID_INT_EN_LO_SET                             0x12
2100 #define PALMAS_USB_ID_INT_EN_LO_CLR                             0x13
2101 #define PALMAS_USB_ID_INT_EN_HI_SET                             0x14
2102 #define PALMAS_USB_ID_INT_EN_HI_CLR                             0x15
2103 #define PALMAS_USB_OTG_ADP_CTRL                                 0x16
2104 #define PALMAS_USB_OTG_ADP_HIGH                                 0x17
2105 #define PALMAS_USB_OTG_ADP_LOW                                  0x18
2106 #define PALMAS_USB_OTG_ADP_RISE                                 0x19
2107 #define PALMAS_USB_OTG_REVISION                                 0x1A
2108
2109 /* Bit definitions for USB_WAKEUP */
2110 #define PALMAS_USB_WAKEUP_ID_WK_UP_COMP                         0x01
2111 #define PALMAS_USB_WAKEUP_ID_WK_UP_COMP_SHIFT                   0
2112
2113 /* Bit definitions for USB_VBUS_CTRL_SET */
2114 #define PALMAS_USB_VBUS_CTRL_SET_VBUS_CHRG_VSYS                 0x80
2115 #define PALMAS_USB_VBUS_CTRL_SET_VBUS_CHRG_VSYS_SHIFT           7
2116 #define PALMAS_USB_VBUS_CTRL_SET_VBUS_DISCHRG                   0x20
2117 #define PALMAS_USB_VBUS_CTRL_SET_VBUS_DISCHRG_SHIFT             5
2118 #define PALMAS_USB_VBUS_CTRL_SET_VBUS_IADP_SRC                  0x10
2119 #define PALMAS_USB_VBUS_CTRL_SET_VBUS_IADP_SRC_SHIFT            4
2120 #define PALMAS_USB_VBUS_CTRL_SET_VBUS_IADP_SINK                 0x08
2121 #define PALMAS_USB_VBUS_CTRL_SET_VBUS_IADP_SINK_SHIFT           3
2122 #define PALMAS_USB_VBUS_CTRL_SET_VBUS_ACT_COMP                  0x04
2123 #define PALMAS_USB_VBUS_CTRL_SET_VBUS_ACT_COMP_SHIFT            2
2124
2125 /* Bit definitions for USB_VBUS_CTRL_CLR */
2126 #define PALMAS_USB_VBUS_CTRL_CLR_VBUS_CHRG_VSYS                 0x80
2127 #define PALMAS_USB_VBUS_CTRL_CLR_VBUS_CHRG_VSYS_SHIFT           7
2128 #define PALMAS_USB_VBUS_CTRL_CLR_VBUS_DISCHRG                   0x20
2129 #define PALMAS_USB_VBUS_CTRL_CLR_VBUS_DISCHRG_SHIFT             5
2130 #define PALMAS_USB_VBUS_CTRL_CLR_VBUS_IADP_SRC                  0x10
2131 #define PALMAS_USB_VBUS_CTRL_CLR_VBUS_IADP_SRC_SHIFT            4
2132 #define PALMAS_USB_VBUS_CTRL_CLR_VBUS_IADP_SINK                 0x08
2133 #define PALMAS_USB_VBUS_CTRL_CLR_VBUS_IADP_SINK_SHIFT           3
2134 #define PALMAS_USB_VBUS_CTRL_CLR_VBUS_ACT_COMP                  0x04
2135 #define PALMAS_USB_VBUS_CTRL_CLR_VBUS_ACT_COMP_SHIFT            2
2136
2137 /* Bit definitions for USB_ID_CTRL_SET */
2138 #define PALMAS_USB_ID_CTRL_SET_ID_PU_220K                       0x80
2139 #define PALMAS_USB_ID_CTRL_SET_ID_PU_220K_SHIFT                 7
2140 #define PALMAS_USB_ID_CTRL_SET_ID_PU_100K                       0x40
2141 #define PALMAS_USB_ID_CTRL_SET_ID_PU_100K_SHIFT                 6
2142 #define PALMAS_USB_ID_CTRL_SET_ID_GND_DRV                       0x20
2143 #define PALMAS_USB_ID_CTRL_SET_ID_GND_DRV_SHIFT                 5
2144 #define PALMAS_USB_ID_CTRL_SET_ID_SRC_16U                       0x10
2145 #define PALMAS_USB_ID_CTRL_SET_ID_SRC_16U_SHIFT                 4
2146 #define PALMAS_USB_ID_CTRL_SET_ID_SRC_5U                        0x08
2147 #define PALMAS_USB_ID_CTRL_SET_ID_SRC_5U_SHIFT                  3
2148 #define PALMAS_USB_ID_CTRL_SET_ID_ACT_COMP                      0x04
2149 #define PALMAS_USB_ID_CTRL_SET_ID_ACT_COMP_SHIFT                2
2150
2151 /* Bit definitions for USB_ID_CTRL_CLEAR */
2152 #define PALMAS_USB_ID_CTRL_CLEAR_ID_PU_220K                     0x80
2153 #define PALMAS_USB_ID_CTRL_CLEAR_ID_PU_220K_SHIFT               7
2154 #define PALMAS_USB_ID_CTRL_CLEAR_ID_PU_100K                     0x40
2155 #define PALMAS_USB_ID_CTRL_CLEAR_ID_PU_100K_SHIFT               6
2156 #define PALMAS_USB_ID_CTRL_CLEAR_ID_GND_DRV                     0x20
2157 #define PALMAS_USB_ID_CTRL_CLEAR_ID_GND_DRV_SHIFT               5
2158 #define PALMAS_USB_ID_CTRL_CLEAR_ID_SRC_16U                     0x10
2159 #define PALMAS_USB_ID_CTRL_CLEAR_ID_SRC_16U_SHIFT               4
2160 #define PALMAS_USB_ID_CTRL_CLEAR_ID_SRC_5U                      0x08
2161 #define PALMAS_USB_ID_CTRL_CLEAR_ID_SRC_5U_SHIFT                3
2162 #define PALMAS_USB_ID_CTRL_CLEAR_ID_ACT_COMP                    0x04
2163 #define PALMAS_USB_ID_CTRL_CLEAR_ID_ACT_COMP_SHIFT              2
2164
2165 /* Bit definitions for USB_VBUS_INT_SRC */
2166 #define PALMAS_USB_VBUS_INT_SRC_VOTG_SESS_VLD                   0x80
2167 #define PALMAS_USB_VBUS_INT_SRC_VOTG_SESS_VLD_SHIFT             7
2168 #define PALMAS_USB_VBUS_INT_SRC_VADP_PRB                        0x40
2169 #define PALMAS_USB_VBUS_INT_SRC_VADP_PRB_SHIFT                  6
2170 #define PALMAS_USB_VBUS_INT_SRC_VADP_SNS                        0x20
2171 #define PALMAS_USB_VBUS_INT_SRC_VADP_SNS_SHIFT                  5
2172 #define PALMAS_USB_VBUS_INT_SRC_VA_VBUS_VLD                     0x08
2173 #define PALMAS_USB_VBUS_INT_SRC_VA_VBUS_VLD_SHIFT               3
2174 #define PALMAS_USB_VBUS_INT_SRC_VA_SESS_VLD                     0x04
2175 #define PALMAS_USB_VBUS_INT_SRC_VA_SESS_VLD_SHIFT               2
2176 #define PALMAS_USB_VBUS_INT_SRC_VB_SESS_VLD                     0x02
2177 #define PALMAS_USB_VBUS_INT_SRC_VB_SESS_VLD_SHIFT               1
2178 #define PALMAS_USB_VBUS_INT_SRC_VB_SESS_END                     0x01
2179 #define PALMAS_USB_VBUS_INT_SRC_VB_SESS_END_SHIFT               0
2180
2181 /* Bit definitions for USB_VBUS_INT_LATCH_SET */
2182 #define PALMAS_USB_VBUS_INT_LATCH_SET_VOTG_SESS_VLD             0x80
2183 #define PALMAS_USB_VBUS_INT_LATCH_SET_VOTG_SESS_VLD_SHIFT       7
2184 #define PALMAS_USB_VBUS_INT_LATCH_SET_VADP_PRB                  0x40
2185 #define PALMAS_USB_VBUS_INT_LATCH_SET_VADP_PRB_SHIFT            6
2186 #define PALMAS_USB_VBUS_INT_LATCH_SET_VADP_SNS                  0x20
2187 #define PALMAS_USB_VBUS_INT_LATCH_SET_VADP_SNS_SHIFT            5
2188 #define PALMAS_USB_VBUS_INT_LATCH_SET_ADP                       0x10
2189 #define PALMAS_USB_VBUS_INT_LATCH_SET_ADP_SHIFT                 4
2190 #define PALMAS_USB_VBUS_INT_LATCH_SET_VA_VBUS_VLD               0x08
2191 #define PALMAS_USB_VBUS_INT_LATCH_SET_VA_VBUS_VLD_SHIFT         3
2192 #define PALMAS_USB_VBUS_INT_LATCH_SET_VA_SESS_VLD               0x04
2193 #define PALMAS_USB_VBUS_INT_LATCH_SET_VA_SESS_VLD_SHIFT         2
2194 #define PALMAS_USB_VBUS_INT_LATCH_SET_VB_SESS_VLD               0x02
2195 #define PALMAS_USB_VBUS_INT_LATCH_SET_VB_SESS_VLD_SHIFT         1
2196 #define PALMAS_USB_VBUS_INT_LATCH_SET_VB_SESS_END               0x01
2197 #define PALMAS_USB_VBUS_INT_LATCH_SET_VB_SESS_END_SHIFT         0
2198
2199 /* Bit definitions for USB_VBUS_INT_LATCH_CLR */
2200 #define PALMAS_USB_VBUS_INT_LATCH_CLR_VOTG_SESS_VLD             0x80
2201 #define PALMAS_USB_VBUS_INT_LATCH_CLR_VOTG_SESS_VLD_SHIFT       7
2202 #define PALMAS_USB_VBUS_INT_LATCH_CLR_VADP_PRB                  0x40
2203 #define PALMAS_USB_VBUS_INT_LATCH_CLR_VADP_PRB_SHIFT            6
2204 #define PALMAS_USB_VBUS_INT_LATCH_CLR_VADP_SNS                  0x20
2205 #define PALMAS_USB_VBUS_INT_LATCH_CLR_VADP_SNS_SHIFT            5
2206 #define PALMAS_USB_VBUS_INT_LATCH_CLR_ADP                       0x10
2207 #define PALMAS_USB_VBUS_INT_LATCH_CLR_ADP_SHIFT                 4
2208 #define PALMAS_USB_VBUS_INT_LATCH_CLR_VA_VBUS_VLD               0x08
2209 #define PALMAS_USB_VBUS_INT_LATCH_CLR_VA_VBUS_VLD_SHIFT         3
2210 #define PALMAS_USB_VBUS_INT_LATCH_CLR_VA_SESS_VLD               0x04
2211 #define PALMAS_USB_VBUS_INT_LATCH_CLR_VA_SESS_VLD_SHIFT         2
2212 #define PALMAS_USB_VBUS_INT_LATCH_CLR_VB_SESS_VLD               0x02
2213 #define PALMAS_USB_VBUS_INT_LATCH_CLR_VB_SESS_VLD_SHIFT         1
2214 #define PALMAS_USB_VBUS_INT_LATCH_CLR_VB_SESS_END               0x01
2215 #define PALMAS_USB_VBUS_INT_LATCH_CLR_VB_SESS_END_SHIFT         0
2216
2217 /* Bit definitions for USB_VBUS_INT_EN_LO_SET */
2218 #define PALMAS_USB_VBUS_INT_EN_LO_SET_VOTG_SESS_VLD             0x80
2219 #define PALMAS_USB_VBUS_INT_EN_LO_SET_VOTG_SESS_VLD_SHIFT       7
2220 #define PALMAS_USB_VBUS_INT_EN_LO_SET_VADP_PRB                  0x40
2221 #define PALMAS_USB_VBUS_INT_EN_LO_SET_VADP_PRB_SHIFT            6
2222 #define PALMAS_USB_VBUS_INT_EN_LO_SET_VADP_SNS                  0x20
2223 #define PALMAS_USB_VBUS_INT_EN_LO_SET_VADP_SNS_SHIFT            5
2224 #define PALMAS_USB_VBUS_INT_EN_LO_SET_VA_VBUS_VLD               0x08
2225 #define PALMAS_USB_VBUS_INT_EN_LO_SET_VA_VBUS_VLD_SHIFT         3
2226 #define PALMAS_USB_VBUS_INT_EN_LO_SET_VA_SESS_VLD               0x04
2227 #define PALMAS_USB_VBUS_INT_EN_LO_SET_VA_SESS_VLD_SHIFT         2
2228 #define PALMAS_USB_VBUS_INT_EN_LO_SET_VB_SESS_VLD               0x02
2229 #define PALMAS_USB_VBUS_INT_EN_LO_SET_VB_SESS_VLD_SHIFT         1
2230 #define PALMAS_USB_VBUS_INT_EN_LO_SET_VB_SESS_END               0x01
2231 #define PALMAS_USB_VBUS_INT_EN_LO_SET_VB_SESS_END_SHIFT         0
2232
2233 /* Bit definitions for USB_VBUS_INT_EN_LO_CLR */
2234 #define PALMAS_USB_VBUS_INT_EN_LO_CLR_VOTG_SESS_VLD             0x80
2235 #define PALMAS_USB_VBUS_INT_EN_LO_CLR_VOTG_SESS_VLD_SHIFT       7
2236 #define PALMAS_USB_VBUS_INT_EN_LO_CLR_VADP_PRB                  0x40
2237 #define PALMAS_USB_VBUS_INT_EN_LO_CLR_VADP_PRB_SHIFT            6
2238 #define PALMAS_USB_VBUS_INT_EN_LO_CLR_VADP_SNS                  0x20
2239 #define PALMAS_USB_VBUS_INT_EN_LO_CLR_VADP_SNS_SHIFT            5
2240 #define PALMAS_USB_VBUS_INT_EN_LO_CLR_VA_VBUS_VLD               0x08
2241 #define PALMAS_USB_VBUS_INT_EN_LO_CLR_VA_VBUS_VLD_SHIFT         3
2242 #define PALMAS_USB_VBUS_INT_EN_LO_CLR_VA_SESS_VLD               0x04
2243 #define PALMAS_USB_VBUS_INT_EN_LO_CLR_VA_SESS_VLD_SHIFT         2
2244 #define PALMAS_USB_VBUS_INT_EN_LO_CLR_VB_SESS_VLD               0x02
2245 #define PALMAS_USB_VBUS_INT_EN_LO_CLR_VB_SESS_VLD_SHIFT         1
2246 #define PALMAS_USB_VBUS_INT_EN_LO_CLR_VB_SESS_END               0x01
2247 #define PALMAS_USB_VBUS_INT_EN_LO_CLR_VB_SESS_END_SHIFT         0
2248
2249 /* Bit definitions for USB_VBUS_INT_EN_HI_SET */
2250 #define PALMAS_USB_VBUS_INT_EN_HI_SET_VOTG_SESS_VLD             0x80
2251 #define PALMAS_USB_VBUS_INT_EN_HI_SET_VOTG_SESS_VLD_SHIFT       7
2252 #define PALMAS_USB_VBUS_INT_EN_HI_SET_VADP_PRB                  0x40
2253 #define PALMAS_USB_VBUS_INT_EN_HI_SET_VADP_PRB_SHIFT            6
2254 #define PALMAS_USB_VBUS_INT_EN_HI_SET_VADP_SNS                  0x20
2255 #define PALMAS_USB_VBUS_INT_EN_HI_SET_VADP_SNS_SHIFT            5
2256 #define PALMAS_USB_VBUS_INT_EN_HI_SET_ADP                       0x10
2257 #define PALMAS_USB_VBUS_INT_EN_HI_SET_ADP_SHIFT                 4
2258 #define PALMAS_USB_VBUS_INT_EN_HI_SET_VA_VBUS_VLD               0x08
2259 #define PALMAS_USB_VBUS_INT_EN_HI_SET_VA_VBUS_VLD_SHIFT         3
2260 #define PALMAS_USB_VBUS_INT_EN_HI_SET_VA_SESS_VLD               0x04
2261 #define PALMAS_USB_VBUS_INT_EN_HI_SET_VA_SESS_VLD_SHIFT         2
2262 #define PALMAS_USB_VBUS_INT_EN_HI_SET_VB_SESS_VLD               0x02
2263 #define PALMAS_USB_VBUS_INT_EN_HI_SET_VB_SESS_VLD_SHIFT         1
2264 #define PALMAS_USB_VBUS_INT_EN_HI_SET_VB_SESS_END               0x01
2265 #define PALMAS_USB_VBUS_INT_EN_HI_SET_VB_SESS_END_SHIFT         0
2266
2267 /* Bit definitions for USB_VBUS_INT_EN_HI_CLR */
2268 #define PALMAS_USB_VBUS_INT_EN_HI_CLR_VOTG_SESS_VLD             0x80
2269 #define PALMAS_USB_VBUS_INT_EN_HI_CLR_VOTG_SESS_VLD_SHIFT       7
2270 #define PALMAS_USB_VBUS_INT_EN_HI_CLR_VADP_PRB                  0x40
2271 #define PALMAS_USB_VBUS_INT_EN_HI_CLR_VADP_PRB_SHIFT            6
2272 #define PALMAS_USB_VBUS_INT_EN_HI_CLR_VADP_SNS                  0x20
2273 #define PALMAS_USB_VBUS_INT_EN_HI_CLR_VADP_SNS_SHIFT            5
2274 #define PALMAS_USB_VBUS_INT_EN_HI_CLR_ADP                       0x10
2275 #define PALMAS_USB_VBUS_INT_EN_HI_CLR_ADP_SHIFT                 4
2276 #define PALMAS_USB_VBUS_INT_EN_HI_CLR_VA_VBUS_VLD               0x08
2277 #define PALMAS_USB_VBUS_INT_EN_HI_CLR_VA_VBUS_VLD_SHIFT         3
2278 #define PALMAS_USB_VBUS_INT_EN_HI_CLR_VA_SESS_VLD               0x04
2279 #define PALMAS_USB_VBUS_INT_EN_HI_CLR_VA_SESS_VLD_SHIFT         2
2280 #define PALMAS_USB_VBUS_INT_EN_HI_CLR_VB_SESS_VLD               0x02
2281 #define PALMAS_USB_VBUS_INT_EN_HI_CLR_VB_SESS_VLD_SHIFT         1
2282 #define PALMAS_USB_VBUS_INT_EN_HI_CLR_VB_SESS_END               0x01
2283 #define PALMAS_USB_VBUS_INT_EN_HI_CLR_VB_SESS_END_SHIFT         0
2284
2285 /* Bit definitions for USB_ID_INT_SRC */
2286 #define PALMAS_USB_ID_INT_SRC_ID_FLOAT                          0x10
2287 #define PALMAS_USB_ID_INT_SRC_ID_FLOAT_SHIFT                    4
2288 #define PALMAS_USB_ID_INT_SRC_ID_A                              0x08
2289 #define PALMAS_USB_ID_INT_SRC_ID_A_SHIFT                        3
2290 #define PALMAS_USB_ID_INT_SRC_ID_B                              0x04
2291 #define PALMAS_USB_ID_INT_SRC_ID_B_SHIFT                        2
2292 #define PALMAS_USB_ID_INT_SRC_ID_C                              0x02
2293 #define PALMAS_USB_ID_INT_SRC_ID_C_SHIFT                        1
2294 #define PALMAS_USB_ID_INT_SRC_ID_GND                            0x01
2295 #define PALMAS_USB_ID_INT_SRC_ID_GND_SHIFT                      0
2296
2297 /* Bit definitions for USB_ID_INT_LATCH_SET */
2298 #define PALMAS_USB_ID_INT_LATCH_SET_ID_FLOAT                    0x10
2299 #define PALMAS_USB_ID_INT_LATCH_SET_ID_FLOAT_SHIFT              4
2300 #define PALMAS_USB_ID_INT_LATCH_SET_ID_A                        0x08
2301 #define PALMAS_USB_ID_INT_LATCH_SET_ID_A_SHIFT                  3
2302 #define PALMAS_USB_ID_INT_LATCH_SET_ID_B                        0x04
2303 #define PALMAS_USB_ID_INT_LATCH_SET_ID_B_SHIFT                  2
2304 #define PALMAS_USB_ID_INT_LATCH_SET_ID_C                        0x02
2305 #define PALMAS_USB_ID_INT_LATCH_SET_ID_C_SHIFT                  1
2306 #define PALMAS_USB_ID_INT_LATCH_SET_ID_GND                      0x01
2307 #define PALMAS_USB_ID_INT_LATCH_SET_ID_GND_SHIFT                0
2308
2309 /* Bit definitions for USB_ID_INT_LATCH_CLR */
2310 #define PALMAS_USB_ID_INT_LATCH_CLR_ID_FLOAT                    0x10
2311 #define PALMAS_USB_ID_INT_LATCH_CLR_ID_FLOAT_SHIFT              4
2312 #define PALMAS_USB_ID_INT_LATCH_CLR_ID_A                        0x08
2313 #define PALMAS_USB_ID_INT_LATCH_CLR_ID_A_SHIFT                  3
2314 #define PALMAS_USB_ID_INT_LATCH_CLR_ID_B                        0x04
2315 #define PALMAS_USB_ID_INT_LATCH_CLR_ID_B_SHIFT                  2
2316 #define PALMAS_USB_ID_INT_LATCH_CLR_ID_C                        0x02
2317 #define PALMAS_USB_ID_INT_LATCH_CLR_ID_C_SHIFT                  1
2318 #define PALMAS_USB_ID_INT_LATCH_CLR_ID_GND                      0x01
2319 #define PALMAS_USB_ID_INT_LATCH_CLR_ID_GND_SHIFT                0
2320
2321 /* Bit definitions for USB_ID_INT_EN_LO_SET */
2322 #define PALMAS_USB_ID_INT_EN_LO_SET_ID_FLOAT                    0x10
2323 #define PALMAS_USB_ID_INT_EN_LO_SET_ID_FLOAT_SHIFT              4
2324 #define PALMAS_USB_ID_INT_EN_LO_SET_ID_A                        0x08
2325 #define PALMAS_USB_ID_INT_EN_LO_SET_ID_A_SHIFT                  3
2326 #define PALMAS_USB_ID_INT_EN_LO_SET_ID_B                        0x04
2327 #define PALMAS_USB_ID_INT_EN_LO_SET_ID_B_SHIFT                  2
2328 #define PALMAS_USB_ID_INT_EN_LO_SET_ID_C                        0x02
2329 #define PALMAS_USB_ID_INT_EN_LO_SET_ID_C_SHIFT                  1
2330 #define PALMAS_USB_ID_INT_EN_LO_SET_ID_GND                      0x01
2331 #define PALMAS_USB_ID_INT_EN_LO_SET_ID_GND_SHIFT                0
2332
2333 /* Bit definitions for USB_ID_INT_EN_LO_CLR */
2334 #define PALMAS_USB_ID_INT_EN_LO_CLR_ID_FLOAT                    0x10
2335 #define PALMAS_USB_ID_INT_EN_LO_CLR_ID_FLOAT_SHIFT              4
2336 #define PALMAS_USB_ID_INT_EN_LO_CLR_ID_A                        0x08
2337 #define PALMAS_USB_ID_INT_EN_LO_CLR_ID_A_SHIFT                  3
2338 #define PALMAS_USB_ID_INT_EN_LO_CLR_ID_B                        0x04
2339 #define PALMAS_USB_ID_INT_EN_LO_CLR_ID_B_SHIFT                  2
2340 #define PALMAS_USB_ID_INT_EN_LO_CLR_ID_C                        0x02
2341 #define PALMAS_USB_ID_INT_EN_LO_CLR_ID_C_SHIFT                  1
2342 #define PALMAS_USB_ID_INT_EN_LO_CLR_ID_GND                      0x01
2343 #define PALMAS_USB_ID_INT_EN_LO_CLR_ID_GND_SHIFT                0
2344
2345 /* Bit definitions for USB_ID_INT_EN_HI_SET */
2346 #define PALMAS_USB_ID_INT_EN_HI_SET_ID_FLOAT                    0x10
2347 #define PALMAS_USB_ID_INT_EN_HI_SET_ID_FLOAT_SHIFT              4
2348 #define PALMAS_USB_ID_INT_EN_HI_SET_ID_A                        0x08
2349 #define PALMAS_USB_ID_INT_EN_HI_SET_ID_A_SHIFT                  3
2350 #define PALMAS_USB_ID_INT_EN_HI_SET_ID_B                        0x04
2351 #define PALMAS_USB_ID_INT_EN_HI_SET_ID_B_SHIFT                  2
2352 #define PALMAS_USB_ID_INT_EN_HI_SET_ID_C                        0x02
2353 #define PALMAS_USB_ID_INT_EN_HI_SET_ID_C_SHIFT                  1
2354 #define PALMAS_USB_ID_INT_EN_HI_SET_ID_GND                      0x01
2355 #define PALMAS_USB_ID_INT_EN_HI_SET_ID_GND_SHIFT                0
2356
2357 /* Bit definitions for USB_ID_INT_EN_HI_CLR */
2358 #define PALMAS_USB_ID_INT_EN_HI_CLR_ID_FLOAT                    0x10
2359 #define PALMAS_USB_ID_INT_EN_HI_CLR_ID_FLOAT_SHIFT              4
2360 #define PALMAS_USB_ID_INT_EN_HI_CLR_ID_A                        0x08
2361 #define PALMAS_USB_ID_INT_EN_HI_CLR_ID_A_SHIFT                  3
2362 #define PALMAS_USB_ID_INT_EN_HI_CLR_ID_B                        0x04
2363 #define PALMAS_USB_ID_INT_EN_HI_CLR_ID_B_SHIFT                  2
2364 #define PALMAS_USB_ID_INT_EN_HI_CLR_ID_C                        0x02
2365 #define PALMAS_USB_ID_INT_EN_HI_CLR_ID_C_SHIFT                  1
2366 #define PALMAS_USB_ID_INT_EN_HI_CLR_ID_GND                      0x01
2367 #define PALMAS_USB_ID_INT_EN_HI_CLR_ID_GND_SHIFT                0
2368
2369 /* Bit definitions for USB_OTG_ADP_CTRL */
2370 #define PALMAS_USB_OTG_ADP_CTRL_ADP_EN                          0x04
2371 #define PALMAS_USB_OTG_ADP_CTRL_ADP_EN_SHIFT                    2
2372 #define PALMAS_USB_OTG_ADP_CTRL_ADP_MODE_MASK                   0x03
2373 #define PALMAS_USB_OTG_ADP_CTRL_ADP_MODE_SHIFT                  0
2374
2375 /* Bit definitions for USB_OTG_ADP_HIGH */
2376 #define PALMAS_USB_OTG_ADP_HIGH_T_ADP_HIGH_MASK                 0xff
2377 #define PALMAS_USB_OTG_ADP_HIGH_T_ADP_HIGH_SHIFT                0
2378
2379 /* Bit definitions for USB_OTG_ADP_LOW */
2380 #define PALMAS_USB_OTG_ADP_LOW_T_ADP_LOW_MASK                   0xff
2381 #define PALMAS_USB_OTG_ADP_LOW_T_ADP_LOW_SHIFT                  0
2382
2383 /* Bit definitions for USB_OTG_ADP_RISE */
2384 #define PALMAS_USB_OTG_ADP_RISE_T_ADP_RISE_MASK                 0xff
2385 #define PALMAS_USB_OTG_ADP_RISE_T_ADP_RISE_SHIFT                0
2386
2387 /* Bit definitions for USB_OTG_REVISION */
2388 #define PALMAS_USB_OTG_REVISION_OTG_REV                         0x01
2389 #define PALMAS_USB_OTG_REVISION_OTG_REV_SHIFT                   0
2390
2391 /* Registers for function VIBRATOR */
2392 #define PALMAS_VIBRA_CTRL                                       0x0
2393
2394 /* Bit definitions for VIBRA_CTRL */
2395 #define PALMAS_VIBRA_CTRL_PWM_DUTY_SEL_MASK                     0x06
2396 #define PALMAS_VIBRA_CTRL_PWM_DUTY_SEL_SHIFT                    1
2397 #define PALMAS_VIBRA_CTRL_PWM_FREQ_SEL                          0x01
2398 #define PALMAS_VIBRA_CTRL_PWM_FREQ_SEL_SHIFT                    0
2399
2400 /* Registers for function GPIO */
2401 #define PALMAS_GPIO_DATA_IN                                     0x0
2402 #define PALMAS_GPIO_DATA_DIR                                    0x1
2403 #define PALMAS_GPIO_DATA_OUT                                    0x2
2404 #define PALMAS_GPIO_DEBOUNCE_EN                                 0x3
2405 #define PALMAS_GPIO_CLEAR_DATA_OUT                              0x4
2406 #define PALMAS_GPIO_SET_DATA_OUT                                0x5
2407 #define PALMAS_PU_PD_GPIO_CTRL1                                 0x6
2408 #define PALMAS_PU_PD_GPIO_CTRL2                                 0x7
2409 #define PALMAS_OD_OUTPUT_GPIO_CTRL                              0x8
2410
2411 /* Bit definitions for GPIO_DATA_IN */
2412 #define PALMAS_GPIO_DATA_IN_GPIO_7_IN                           0x80
2413 #define PALMAS_GPIO_DATA_IN_GPIO_7_IN_SHIFT                     7
2414 #define PALMAS_GPIO_DATA_IN_GPIO_6_IN                           0x40
2415 #define PALMAS_GPIO_DATA_IN_GPIO_6_IN_SHIFT                     6
2416 #define PALMAS_GPIO_DATA_IN_GPIO_5_IN                           0x20
2417 #define PALMAS_GPIO_DATA_IN_GPIO_5_IN_SHIFT                     5
2418 #define PALMAS_GPIO_DATA_IN_GPIO_4_IN                           0x10
2419 #define PALMAS_GPIO_DATA_IN_GPIO_4_IN_SHIFT                     4
2420 #define PALMAS_GPIO_DATA_IN_GPIO_3_IN                           0x08
2421 #define PALMAS_GPIO_DATA_IN_GPIO_3_IN_SHIFT                     3
2422 #define PALMAS_GPIO_DATA_IN_GPIO_2_IN                           0x04
2423 #define PALMAS_GPIO_DATA_IN_GPIO_2_IN_SHIFT                     2
2424 #define PALMAS_GPIO_DATA_IN_GPIO_1_IN                           0x02
2425 #define PALMAS_GPIO_DATA_IN_GPIO_1_IN_SHIFT                     1
2426 #define PALMAS_GPIO_DATA_IN_GPIO_0_IN                           0x01
2427 #define PALMAS_GPIO_DATA_IN_GPIO_0_IN_SHIFT                     0
2428
2429 /* Bit definitions for GPIO_DATA_DIR */
2430 #define PALMAS_GPIO_DATA_DIR_GPIO_7_DIR                         0x80
2431 #define PALMAS_GPIO_DATA_DIR_GPIO_7_DIR_SHIFT                   7
2432 #define PALMAS_GPIO_DATA_DIR_GPIO_6_DIR                         0x40
2433 #define PALMAS_GPIO_DATA_DIR_GPIO_6_DIR_SHIFT                   6
2434 #define PALMAS_GPIO_DATA_DIR_GPIO_5_DIR                         0x20
2435 #define PALMAS_GPIO_DATA_DIR_GPIO_5_DIR_SHIFT                   5
2436 #define PALMAS_GPIO_DATA_DIR_GPIO_4_DIR                         0x10
2437 #define PALMAS_GPIO_DATA_DIR_GPIO_4_DIR_SHIFT                   4
2438 #define PALMAS_GPIO_DATA_DIR_GPIO_3_DIR                         0x08
2439 #define PALMAS_GPIO_DATA_DIR_GPIO_3_DIR_SHIFT                   3
2440 #define PALMAS_GPIO_DATA_DIR_GPIO_2_DIR                         0x04
2441 #define PALMAS_GPIO_DATA_DIR_GPIO_2_DIR_SHIFT                   2
2442 #define PALMAS_GPIO_DATA_DIR_GPIO_1_DIR                         0x02
2443 #define PALMAS_GPIO_DATA_DIR_GPIO_1_DIR_SHIFT                   1
2444 #define PALMAS_GPIO_DATA_DIR_GPIO_0_DIR                         0x01
2445 #define PALMAS_GPIO_DATA_DIR_GPIO_0_DIR_SHIFT                   0
2446
2447 /* Bit definitions for GPIO_DATA_OUT */
2448 #define PALMAS_GPIO_DATA_OUT_GPIO_7_OUT                         0x80
2449 #define PALMAS_GPIO_DATA_OUT_GPIO_7_OUT_SHIFT                   7
2450 #define PALMAS_GPIO_DATA_OUT_GPIO_6_OUT                         0x40
2451 #define PALMAS_GPIO_DATA_OUT_GPIO_6_OUT_SHIFT                   6
2452 #define PALMAS_GPIO_DATA_OUT_GPIO_5_OUT                         0x20
2453 #define PALMAS_GPIO_DATA_OUT_GPIO_5_OUT_SHIFT                   5
2454 #define PALMAS_GPIO_DATA_OUT_GPIO_4_OUT                         0x10
2455 #define PALMAS_GPIO_DATA_OUT_GPIO_4_OUT_SHIFT                   4
2456 #define PALMAS_GPIO_DATA_OUT_GPIO_3_OUT                         0x08
2457 #define PALMAS_GPIO_DATA_OUT_GPIO_3_OUT_SHIFT                   3
2458 #define PALMAS_GPIO_DATA_OUT_GPIO_2_OUT                         0x04
2459 #define PALMAS_GPIO_DATA_OUT_GPIO_2_OUT_SHIFT                   2
2460 #define PALMAS_GPIO_DATA_OUT_GPIO_1_OUT                         0x02
2461 #define PALMAS_GPIO_DATA_OUT_GPIO_1_OUT_SHIFT                   1
2462 #define PALMAS_GPIO_DATA_OUT_GPIO_0_OUT                         0x01
2463 #define PALMAS_GPIO_DATA_OUT_GPIO_0_OUT_SHIFT                   0
2464
2465 /* Bit definitions for GPIO_DEBOUNCE_EN */
2466 #define PALMAS_GPIO_DEBOUNCE_EN_GPIO_7_DEBOUNCE_EN              0x80
2467 #define PALMAS_GPIO_DEBOUNCE_EN_GPIO_7_DEBOUNCE_EN_SHIFT        7
2468 #define PALMAS_GPIO_DEBOUNCE_EN_GPIO_6_DEBOUNCE_EN              0x40
2469 #define PALMAS_GPIO_DEBOUNCE_EN_GPIO_6_DEBOUNCE_EN_SHIFT        6
2470 #define PALMAS_GPIO_DEBOUNCE_EN_GPIO_5_DEBOUNCE_EN              0x20
2471 #define PALMAS_GPIO_DEBOUNCE_EN_GPIO_5_DEBOUNCE_EN_SHIFT        5
2472 #define PALMAS_GPIO_DEBOUNCE_EN_GPIO_4_DEBOUNCE_EN              0x10
2473 #define PALMAS_GPIO_DEBOUNCE_EN_GPIO_4_DEBOUNCE_EN_SHIFT        4
2474 #define PALMAS_GPIO_DEBOUNCE_EN_GPIO_3_DEBOUNCE_EN              0x08
2475 #define PALMAS_GPIO_DEBOUNCE_EN_GPIO_3_DEBOUNCE_EN_SHIFT        3
2476 #define PALMAS_GPIO_DEBOUNCE_EN_GPIO_2_DEBOUNCE_EN              0x04
2477 #define PALMAS_GPIO_DEBOUNCE_EN_GPIO_2_DEBOUNCE_EN_SHIFT        2
2478 #define PALMAS_GPIO_DEBOUNCE_EN_GPIO_1_DEBOUNCE_EN              0x02
2479 #define PALMAS_GPIO_DEBOUNCE_EN_GPIO_1_DEBOUNCE_EN_SHIFT        1
2480 #define PALMAS_GPIO_DEBOUNCE_EN_GPIO_0_DEBOUNCE_EN              0x01
2481 #define PALMAS_GPIO_DEBOUNCE_EN_GPIO_0_DEBOUNCE_EN_SHIFT        0
2482
2483 /* Bit definitions for GPIO_CLEAR_DATA_OUT */
2484 #define PALMAS_GPIO_CLEAR_DATA_OUT_GPIO_7_CLEAR_DATA_OUT        0x80
2485 #define PALMAS_GPIO_CLEAR_DATA_OUT_GPIO_7_CLEAR_DATA_OUT_SHIFT  7
2486 #define PALMAS_GPIO_CLEAR_DATA_OUT_GPIO_6_CLEAR_DATA_OUT        0x40
2487 #define PALMAS_GPIO_CLEAR_DATA_OUT_GPIO_6_CLEAR_DATA_OUT_SHIFT  6
2488 #define PALMAS_GPIO_CLEAR_DATA_OUT_GPIO_5_CLEAR_DATA_OUT        0x20
2489 #define PALMAS_GPIO_CLEAR_DATA_OUT_GPIO_5_CLEAR_DATA_OUT_SHIFT  5
2490 #define PALMAS_GPIO_CLEAR_DATA_OUT_GPIO_4_CLEAR_DATA_OUT        0x10
2491 #define PALMAS_GPIO_CLEAR_DATA_OUT_GPIO_4_CLEAR_DATA_OUT_SHIFT  4
2492 #define PALMAS_GPIO_CLEAR_DATA_OUT_GPIO_3_CLEAR_DATA_OUT        0x08
2493 #define PALMAS_GPIO_CLEAR_DATA_OUT_GPIO_3_CLEAR_DATA_OUT_SHIFT  3
2494 #define PALMAS_GPIO_CLEAR_DATA_OUT_GPIO_2_CLEAR_DATA_OUT        0x04
2495 #define PALMAS_GPIO_CLEAR_DATA_OUT_GPIO_2_CLEAR_DATA_OUT_SHIFT  2
2496 #define PALMAS_GPIO_CLEAR_DATA_OUT_GPIO_1_CLEAR_DATA_OUT        0x02
2497 #define PALMAS_GPIO_CLEAR_DATA_OUT_GPIO_1_CLEAR_DATA_OUT_SHIFT  1
2498 #define PALMAS_GPIO_CLEAR_DATA_OUT_GPIO_0_CLEAR_DATA_OUT        0x01
2499 #define PALMAS_GPIO_CLEAR_DATA_OUT_GPIO_0_CLEAR_DATA_OUT_SHIFT  0
2500
2501 /* Bit definitions for GPIO_SET_DATA_OUT */
2502 #define PALMAS_GPIO_SET_DATA_OUT_GPIO_7_SET_DATA_OUT            0x80
2503 #define PALMAS_GPIO_SET_DATA_OUT_GPIO_7_SET_DATA_OUT_SHIFT      7
2504 #define PALMAS_GPIO_SET_DATA_OUT_GPIO_6_SET_DATA_OUT            0x40
2505 #define PALMAS_GPIO_SET_DATA_OUT_GPIO_6_SET_DATA_OUT_SHIFT      6
2506 #define PALMAS_GPIO_SET_DATA_OUT_GPIO_5_SET_DATA_OUT            0x20
2507 #define PALMAS_GPIO_SET_DATA_OUT_GPIO_5_SET_DATA_OUT_SHIFT      5
2508 #define PALMAS_GPIO_SET_DATA_OUT_GPIO_4_SET_DATA_OUT            0x10
2509 #define PALMAS_GPIO_SET_DATA_OUT_GPIO_4_SET_DATA_OUT_SHIFT      4
2510 #define PALMAS_GPIO_SET_DATA_OUT_GPIO_3_SET_DATA_OUT            0x08
2511 #define PALMAS_GPIO_SET_DATA_OUT_GPIO_3_SET_DATA_OUT_SHIFT      3
2512 #define PALMAS_GPIO_SET_DATA_OUT_GPIO_2_SET_DATA_OUT            0x04
2513 #define PALMAS_GPIO_SET_DATA_OUT_GPIO_2_SET_DATA_OUT_SHIFT      2
2514 #define PALMAS_GPIO_SET_DATA_OUT_GPIO_1_SET_DATA_OUT            0x02
2515 #define PALMAS_GPIO_SET_DATA_OUT_GPIO_1_SET_DATA_OUT_SHIFT      1
2516 #define PALMAS_GPIO_SET_DATA_OUT_GPIO_0_SET_DATA_OUT            0x01
2517 #define PALMAS_GPIO_SET_DATA_OUT_GPIO_0_SET_DATA_OUT_SHIFT      0
2518
2519 /* Bit definitions for PU_PD_GPIO_CTRL1 */
2520 #define PALMAS_PU_PD_GPIO_CTRL1_GPIO_3_PD                       0x40
2521 #define PALMAS_PU_PD_GPIO_CTRL1_GPIO_3_PD_SHIFT                 6
2522 #define PALMAS_PU_PD_GPIO_CTRL1_GPIO_2_PU                       0x20
2523 #define PALMAS_PU_PD_GPIO_CTRL1_GPIO_2_PU_SHIFT                 5
2524 #define PALMAS_PU_PD_GPIO_CTRL1_GPIO_2_PD                       0x10
2525 #define PALMAS_PU_PD_GPIO_CTRL1_GPIO_2_PD_SHIFT                 4
2526 #define PALMAS_PU_PD_GPIO_CTRL1_GPIO_1_PU                       0x08
2527 #define PALMAS_PU_PD_GPIO_CTRL1_GPIO_1_PU_SHIFT                 3
2528 #define PALMAS_PU_PD_GPIO_CTRL1_GPIO_1_PD                       0x04
2529 #define PALMAS_PU_PD_GPIO_CTRL1_GPIO_1_PD_SHIFT                 2
2530 #define PALMAS_PU_PD_GPIO_CTRL1_GPIO_0_PD                       0x01
2531 #define PALMAS_PU_PD_GPIO_CTRL1_GPIO_0_PD_SHIFT                 0
2532
2533 /* Bit definitions for PU_PD_GPIO_CTRL2 */
2534 #define PALMAS_PU_PD_GPIO_CTRL2_GPIO_7_PD                       0x40
2535 #define PALMAS_PU_PD_GPIO_CTRL2_GPIO_7_PD_SHIFT                 6
2536 #define PALMAS_PU_PD_GPIO_CTRL2_GPIO_6_PU                       0x20
2537 #define PALMAS_PU_PD_GPIO_CTRL2_GPIO_6_PU_SHIFT                 5
2538 #define PALMAS_PU_PD_GPIO_CTRL2_GPIO_6_PD                       0x10
2539 #define PALMAS_PU_PD_GPIO_CTRL2_GPIO_6_PD_SHIFT                 4
2540 #define PALMAS_PU_PD_GPIO_CTRL2_GPIO_5_PU                       0x08
2541 #define PALMAS_PU_PD_GPIO_CTRL2_GPIO_5_PU_SHIFT                 3
2542 #define PALMAS_PU_PD_GPIO_CTRL2_GPIO_5_PD                       0x04
2543 #define PALMAS_PU_PD_GPIO_CTRL2_GPIO_5_PD_SHIFT                 2
2544 #define PALMAS_PU_PD_GPIO_CTRL2_GPIO_4_PU                       0x02
2545 #define PALMAS_PU_PD_GPIO_CTRL2_GPIO_4_PU_SHIFT                 1
2546 #define PALMAS_PU_PD_GPIO_CTRL2_GPIO_4_PD                       0x01
2547 #define PALMAS_PU_PD_GPIO_CTRL2_GPIO_4_PD_SHIFT                 0
2548
2549 /* Bit definitions for OD_OUTPUT_GPIO_CTRL */
2550 #define PALMAS_OD_OUTPUT_GPIO_CTRL_GPIO_5_OD                    0x20
2551 #define PALMAS_OD_OUTPUT_GPIO_CTRL_GPIO_5_OD_SHIFT              5
2552 #define PALMAS_OD_OUTPUT_GPIO_CTRL_GPIO_2_OD                    0x04
2553 #define PALMAS_OD_OUTPUT_GPIO_CTRL_GPIO_2_OD_SHIFT              2
2554 #define PALMAS_OD_OUTPUT_GPIO_CTRL_GPIO_1_OD                    0x02
2555 #define PALMAS_OD_OUTPUT_GPIO_CTRL_GPIO_1_OD_SHIFT              1
2556
2557 /* Registers for function GPADC */
2558 #define PALMAS_GPADC_CTRL1                                      0x0
2559 #define PALMAS_GPADC_CTRL2                                      0x1
2560 #define PALMAS_GPADC_RT_CTRL                                    0x2
2561 #define PALMAS_GPADC_AUTO_CTRL                                  0x3
2562 #define PALMAS_GPADC_STATUS                                     0x4
2563 #define PALMAS_GPADC_RT_SELECT                                  0x5
2564 #define PALMAS_GPADC_RT_CONV0_LSB                               0x6
2565 #define PALMAS_GPADC_RT_CONV0_MSB                               0x7
2566 #define PALMAS_GPADC_AUTO_SELECT                                0x8
2567 #define PALMAS_GPADC_AUTO_CONV0_LSB                             0x9
2568 #define PALMAS_GPADC_AUTO_CONV0_MSB                             0xA
2569 #define PALMAS_GPADC_AUTO_CONV1_LSB                             0xB
2570 #define PALMAS_GPADC_AUTO_CONV1_MSB                             0xC
2571 #define PALMAS_GPADC_SW_SELECT                                  0xD
2572 #define PALMAS_GPADC_SW_CONV0_LSB                               0xE
2573 #define PALMAS_GPADC_SW_CONV0_MSB                               0xF
2574 #define PALMAS_GPADC_THRES_CONV0_LSB                            0x10
2575 #define PALMAS_GPADC_THRES_CONV0_MSB                            0x11
2576 #define PALMAS_GPADC_THRES_CONV1_LSB                            0x12
2577 #define PALMAS_GPADC_THRES_CONV1_MSB                            0x13
2578 #define PALMAS_GPADC_SMPS_ILMONITOR_EN                          0x14
2579 #define PALMAS_GPADC_SMPS_VSEL_MONITORING                       0x15
2580
2581 /* Bit definitions for GPADC_CTRL1 */
2582 #define PALMAS_GPADC_CTRL1_RESERVED_MASK                        0xc0
2583 #define PALMAS_GPADC_CTRL1_RESERVED_SHIFT                       6
2584 #define PALMAS_GPADC_CTRL1_CURRENT_SRC_CH3_MASK                 0x30
2585 #define PALMAS_GPADC_CTRL1_CURRENT_SRC_CH3_SHIFT                4
2586 #define PALMAS_GPADC_CTRL1_CURRENT_SRC_CH0_MASK                 0x0c
2587 #define PALMAS_GPADC_CTRL1_CURRENT_SRC_CH0_SHIFT                2
2588 #define PALMAS_GPADC_CTRL1_BAT_REMOVAL_DET                      0x02
2589 #define PALMAS_GPADC_CTRL1_BAT_REMOVAL_DET_SHIFT                1
2590 #define PALMAS_GPADC_CTRL1_GPADC_FORCE                          0x01
2591 #define PALMAS_GPADC_CTRL1_GPADC_FORCE_SHIFT                    0
2592
2593 /* Bit definitions for GPADC_CTRL2 */
2594 #define PALMAS_GPADC_CTRL2_RESERVED_MASK                        0x06
2595 #define PALMAS_GPADC_CTRL2_RESERVED_SHIFT                       1
2596
2597 /* Bit definitions for GPADC_RT_CTRL */
2598 #define PALMAS_GPADC_RT_CTRL_EXTEND_DELAY                       0x02
2599 #define PALMAS_GPADC_RT_CTRL_EXTEND_DELAY_SHIFT                 1
2600 #define PALMAS_GPADC_RT_CTRL_START_POLARITY                     0x01
2601 #define PALMAS_GPADC_RT_CTRL_START_POLARITY_SHIFT               0
2602
2603 /* Bit definitions for GPADC_AUTO_CTRL */
2604 #define PALMAS_GPADC_AUTO_CTRL_SHUTDOWN_CONV1                   0x80
2605 #define PALMAS_GPADC_AUTO_CTRL_SHUTDOWN_CONV1_SHIFT             7
2606 #define PALMAS_GPADC_AUTO_CTRL_SHUTDOWN_CONV0                   0x40
2607 #define PALMAS_GPADC_AUTO_CTRL_SHUTDOWN_CONV0_SHIFT             6
2608 #define PALMAS_GPADC_AUTO_CTRL_AUTO_CONV1_EN                    0x20
2609 #define PALMAS_GPADC_AUTO_CTRL_AUTO_CONV1_EN_SHIFT              5
2610 #define PALMAS_GPADC_AUTO_CTRL_AUTO_CONV0_EN                    0x10
2611 #define PALMAS_GPADC_AUTO_CTRL_AUTO_CONV0_EN_SHIFT              4
2612 #define PALMAS_GPADC_AUTO_CTRL_COUNTER_CONV_MASK                0x0f
2613 #define PALMAS_GPADC_AUTO_CTRL_COUNTER_CONV_SHIFT               0
2614
2615 /* Bit definitions for GPADC_STATUS */
2616 #define PALMAS_GPADC_STATUS_GPADC_AVAILABLE                     0x10
2617 #define PALMAS_GPADC_STATUS_GPADC_AVAILABLE_SHIFT               4
2618
2619 /* Bit definitions for GPADC_RT_SELECT */
2620 #define PALMAS_GPADC_RT_SELECT_RT_CONV_EN                       0x80
2621 #define PALMAS_GPADC_RT_SELECT_RT_CONV_EN_SHIFT                 7
2622 #define PALMAS_GPADC_RT_SELECT_RT_CONV0_SEL_MASK                0x0f
2623 #define PALMAS_GPADC_RT_SELECT_RT_CONV0_SEL_SHIFT               0
2624
2625 /* Bit definitions for GPADC_RT_CONV0_LSB */
2626 #define PALMAS_GPADC_RT_CONV0_LSB_RT_CONV0_LSB_MASK             0xff
2627 #define PALMAS_GPADC_RT_CONV0_LSB_RT_CONV0_LSB_SHIFT            0
2628
2629 /* Bit definitions for GPADC_RT_CONV0_MSB */
2630 #define PALMAS_GPADC_RT_CONV0_MSB_RT_CONV0_MSB_MASK             0x0f
2631 #define PALMAS_GPADC_RT_CONV0_MSB_RT_CONV0_MSB_SHIFT            0
2632
2633 /* Bit definitions for GPADC_AUTO_SELECT */
2634 #define PALMAS_GPADC_AUTO_SELECT_AUTO_CONV1_SEL_MASK            0xf0
2635 #define PALMAS_GPADC_AUTO_SELECT_AUTO_CONV1_SEL_SHIFT           4
2636 #define PALMAS_GPADC_AUTO_SELECT_AUTO_CONV0_SEL_MASK            0x0f
2637 #define PALMAS_GPADC_AUTO_SELECT_AUTO_CONV0_SEL_SHIFT           0
2638
2639 /* Bit definitions for GPADC_AUTO_CONV0_LSB */
2640 #define PALMAS_GPADC_AUTO_CONV0_LSB_AUTO_CONV0_LSB_MASK         0xff
2641 #define PALMAS_GPADC_AUTO_CONV0_LSB_AUTO_CONV0_LSB_SHIFT        0
2642
2643 /* Bit definitions for GPADC_AUTO_CONV0_MSB */
2644 #define PALMAS_GPADC_AUTO_CONV0_MSB_AUTO_CONV0_MSB_MASK         0x0f
2645 #define PALMAS_GPADC_AUTO_CONV0_MSB_AUTO_CONV0_MSB_SHIFT        0
2646
2647 /* Bit definitions for GPADC_AUTO_CONV1_LSB */
2648 #define PALMAS_GPADC_AUTO_CONV1_LSB_AUTO_CONV1_LSB_MASK         0xff
2649 #define PALMAS_GPADC_AUTO_CONV1_LSB_AUTO_CONV1_LSB_SHIFT        0
2650
2651 /* Bit definitions for GPADC_AUTO_CONV1_MSB */
2652 #define PALMAS_GPADC_AUTO_CONV1_MSB_AUTO_CONV1_MSB_MASK         0x0f
2653 #define PALMAS_GPADC_AUTO_CONV1_MSB_AUTO_CONV1_MSB_SHIFT        0
2654
2655 /* Bit definitions for GPADC_SW_SELECT */
2656 #define PALMAS_GPADC_SW_SELECT_SW_CONV_EN                       0x80
2657 #define PALMAS_GPADC_SW_SELECT_SW_CONV_EN_SHIFT                 7
2658 #define PALMAS_GPADC_SW_SELECT_SW_START_CONV0                   0x10
2659 #define PALMAS_GPADC_SW_SELECT_SW_START_CONV0_SHIFT             4
2660 #define PALMAS_GPADC_SW_SELECT_SW_CONV0_SEL_MASK                0x0f
2661 #define PALMAS_GPADC_SW_SELECT_SW_CONV0_SEL_SHIFT               0
2662
2663 /* Bit definitions for GPADC_SW_CONV0_LSB */
2664 #define PALMAS_GPADC_SW_CONV0_LSB_SW_CONV0_LSB_MASK             0xff
2665 #define PALMAS_GPADC_SW_CONV0_LSB_SW_CONV0_LSB_SHIFT            0
2666
2667 /* Bit definitions for GPADC_SW_CONV0_MSB */
2668 #define PALMAS_GPADC_SW_CONV0_MSB_SW_CONV0_MSB_MASK             0x0f
2669 #define PALMAS_GPADC_SW_CONV0_MSB_SW_CONV0_MSB_SHIFT            0
2670
2671 /* Bit definitions for GPADC_THRES_CONV0_LSB */
2672 #define PALMAS_GPADC_THRES_CONV0_LSB_THRES_CONV0_LSB_MASK       0xff
2673 #define PALMAS_GPADC_THRES_CONV0_LSB_THRES_CONV0_LSB_SHIFT      0
2674
2675 /* Bit definitions for GPADC_THRES_CONV0_MSB */
2676 #define PALMAS_GPADC_THRES_CONV0_MSB_THRES_CONV0_POL            0x80
2677 #define PALMAS_GPADC_THRES_CONV0_MSB_THRES_CONV0_POL_SHIFT      7
2678 #define PALMAS_GPADC_THRES_CONV0_MSB_THRES_CONV0_MSB_MASK       0x0f
2679 #define PALMAS_GPADC_THRES_CONV0_MSB_THRES_CONV0_MSB_SHIFT      0
2680
2681 /* Bit definitions for GPADC_THRES_CONV1_LSB */
2682 #define PALMAS_GPADC_THRES_CONV1_LSB_THRES_CONV1_LSB_MASK       0xff
2683 #define PALMAS_GPADC_THRES_CONV1_LSB_THRES_CONV1_LSB_SHIFT      0
2684
2685 /* Bit definitions for GPADC_THRES_CONV1_MSB */
2686 #define PALMAS_GPADC_THRES_CONV1_MSB_THRES_CONV1_POL            0x80
2687 #define PALMAS_GPADC_THRES_CONV1_MSB_THRES_CONV1_POL_SHIFT      7
2688 #define PALMAS_GPADC_THRES_CONV1_MSB_THRES_CONV1_MSB_MASK       0x0f
2689 #define PALMAS_GPADC_THRES_CONV1_MSB_THRES_CONV1_MSB_SHIFT      0
2690
2691 /* Bit definitions for GPADC_SMPS_ILMONITOR_EN */
2692 #define PALMAS_GPADC_SMPS_ILMONITOR_EN_SMPS_ILMON_EN            0x20
2693 #define PALMAS_GPADC_SMPS_ILMONITOR_EN_SMPS_ILMON_EN_SHIFT      5
2694 #define PALMAS_GPADC_SMPS_ILMONITOR_EN_SMPS_ILMON_REXT          0x10
2695 #define PALMAS_GPADC_SMPS_ILMONITOR_EN_SMPS_ILMON_REXT_SHIFT    4
2696 #define PALMAS_GPADC_SMPS_ILMONITOR_EN_SMPS_ILMON_SEL_MASK      0x0f
2697 #define PALMAS_GPADC_SMPS_ILMONITOR_EN_SMPS_ILMON_SEL_SHIFT     0
2698
2699 /* Bit definitions for GPADC_SMPS_VSEL_MONITORING */
2700 #define PALMAS_GPADC_SMPS_VSEL_MONITORING_ACTIVE_PHASE          0x80
2701 #define PALMAS_GPADC_SMPS_VSEL_MONITORING_ACTIVE_PHASE_SHIFT    7
2702 #define PALMAS_GPADC_SMPS_VSEL_MONITORING_SMPS_VSEL_MONITORING_MASK     0x7f
2703 #define PALMAS_GPADC_SMPS_VSEL_MONITORING_SMPS_VSEL_MONITORING_SHIFT    0
2704
2705 #define PALMAS_INTERNAL_DESIGNREV                               0x57
2706 #define PALMAS_INTERNAL_DESIGNREV_DESIGNREV(val)                ((val) & 0xF)
2707
2708 /* Registers for function GPADC */
2709 #define PALMAS_GPADC_TRIM1                                      0x0
2710 #define PALMAS_GPADC_TRIM2                                      0x1
2711 #define PALMAS_GPADC_TRIM3                                      0x2
2712 #define PALMAS_GPADC_TRIM4                                      0x3
2713 #define PALMAS_GPADC_TRIM5                                      0x4
2714 #define PALMAS_GPADC_TRIM6                                      0x5
2715 #define PALMAS_GPADC_TRIM7                                      0x6
2716 #define PALMAS_GPADC_TRIM8                                      0x7
2717 #define PALMAS_GPADC_TRIM9                                      0x8
2718 #define PALMAS_GPADC_TRIM10                                     0x9
2719 #define PALMAS_GPADC_TRIM11                                     0xA
2720 #define PALMAS_GPADC_TRIM12                                     0xB
2721 #define PALMAS_GPADC_TRIM13                                     0xC
2722 #define PALMAS_GPADC_TRIM14                                     0xD
2723 #define PALMAS_GPADC_TRIM15                                     0xE
2724 #define PALMAS_GPADC_TRIM16                                     0xF
2725 #define PALMAS_GPADC_TRIMINVALID                                -1
2726
2727 enum {
2728         PALMAS_EXT_CONTROL_ENABLE1      = 0x1,
2729         PALMAS_EXT_CONTROL_ENABLE2      = 0x2,
2730         PALMAS_EXT_CONTROL_NSLEEP       = 0x4,
2731 };
2732
2733 /*
2734  *PALMAS GPIOs
2735  */
2736 enum {
2737         PALMAS_GPIO0,
2738         PALMAS_GPIO1,
2739         PALMAS_GPIO2,
2740         PALMAS_GPIO3,
2741         PALMAS_GPIO4,
2742         PALMAS_GPIO5,
2743         PALMAS_GPIO6,
2744         PALMAS_GPIO7,
2745
2746         PALMAS_GPIO_NR,
2747 };
2748
2749 /* Palma GPADC Channels */
2750 enum {
2751         PALMAS_ADC_CH_IN0,
2752         PALMAS_ADC_CH_IN1,
2753         PALMAS_ADC_CH_IN2,
2754         PALMAS_ADC_CH_IN3,
2755         PALMAS_ADC_CH_IN4,
2756         PALMAS_ADC_CH_IN5,
2757         PALMAS_ADC_CH_IN6,
2758         PALMAS_ADC_CH_IN7,
2759         PALMAS_ADC_CH_IN8,
2760         PALMAS_ADC_CH_IN9,
2761         PALMAS_ADC_CH_IN10,
2762         PALMAS_ADC_CH_IN11,
2763         PALMAS_ADC_CH_IN12,
2764         PALMAS_ADC_CH_IN13,
2765         PALMAS_ADC_CH_IN14,
2766         PALMAS_ADC_CH_IN15,
2767
2768         PALMAS_ADC_CH_MAX,
2769 };
2770
2771 /* Palma Sleep requestor IDs IDs */
2772 enum {
2773         PALMAS_SLEEP_REQSTR_ID_REGEN1,
2774         PALMAS_SLEEP_REQSTR_ID_REGEN2,
2775         PALMAS_SLEEP_REQSTR_ID_SYSEN1,
2776         PALMAS_SLEEP_REQSTR_ID_SYSEN2,
2777         PALMAS_SLEEP_REQSTR_ID_CLK32KG,
2778         PALMAS_SLEEP_REQSTR_ID_CLK32KGAUDIO,
2779         PALMAS_SLEEP_REQSTR_ID_REGEN3,
2780         PALMAS_SLEEP_REQSTR_ID_SMPS12,
2781         PALMAS_SLEEP_REQSTR_ID_SMPS3,
2782         PALMAS_SLEEP_REQSTR_ID_SMPS45,
2783         PALMAS_SLEEP_REQSTR_ID_SMPS6,
2784         PALMAS_SLEEP_REQSTR_ID_SMPS7,
2785         PALMAS_SLEEP_REQSTR_ID_SMPS8,
2786         PALMAS_SLEEP_REQSTR_ID_SMPS9,
2787         PALMAS_SLEEP_REQSTR_ID_SMPS10,
2788         PALMAS_SLEEP_REQSTR_ID_LDO1,
2789         PALMAS_SLEEP_REQSTR_ID_LDO2,
2790         PALMAS_SLEEP_REQSTR_ID_LDO3,
2791         PALMAS_SLEEP_REQSTR_ID_LDO4,
2792         PALMAS_SLEEP_REQSTR_ID_LDO5,
2793         PALMAS_SLEEP_REQSTR_ID_LDO6,
2794         PALMAS_SLEEP_REQSTR_ID_LDO7,
2795         PALMAS_SLEEP_REQSTR_ID_LDO8,
2796         PALMAS_SLEEP_REQSTR_ID_LDO9,
2797         PALMAS_SLEEP_REQSTR_ID_LDOLN,
2798         PALMAS_SLEEP_REQSTR_ID_LDOUSB,
2799
2800         /* Last entry */
2801         PALMAS_SLEEP_REQSTR_ID_MAX,
2802 };
2803
2804 /* Palmas Pinmux option */
2805 enum {
2806         PALMAS_PINMUX_GPIO = 0,
2807         PALMAS_PINMUX_LED,
2808         PALMAS_PINMUX_PWM,
2809         PALMAS_PINMUX_REGEN,
2810         PALMAS_PINMUX_SYSEN,
2811         PALMAS_PINMUX_CLK32KGAUDIO,
2812         PALMAS_PINMUX_ID,
2813         PALMAS_PINMUX_VBUS_DET,
2814         PALMAS_PINMUX_CHRG_DET,
2815         PALMAS_PINMUX_VAC,
2816         PALMAS_PINMUX_VACOK,
2817         PALMAS_PINMUX_POWERGOOD,
2818         PALMAS_PINMUX_USB_PSEL,
2819         PALMAS_PINMUX_MSECURE,
2820         PALMAS_PINMUX_PWRHOLD,
2821         PALMAS_PINMUX_INT,
2822         PALMAS_PINMUX_DVFS2,
2823         PALMAS_PINMUX_DVFS1,
2824         PALMAS_PINMUX_NRESWARM,
2825         PALMAS_PINMUX_PWRDOWN,
2826         PALMAS_PINMUX_GPADC_START,
2827         PALMAS_PINMUX_RESET_IN,
2828         PALMAS_PINMUX_NSLEEP,
2829         PALMAS_PINMUX_ENABLE1,
2830         PALMAS_PINMUX_ENABLE2,
2831         PALMAS_PINMUX_RESVD = 0x2000,
2832         PALMAS_PINMUX_DEFAULT = 0x4000,
2833         PALMAS_PINMUX_INVALID = 0x8000,
2834 };
2835
2836 /* Palmas Pinmux Pullup/pulldown/opendrain configuration. */
2837 enum {
2838         PALMAS_PIN_CONFIG_DEFAULT,
2839         PALMAS_PIN_CONFIG_NORMAL,
2840         PALMAS_PIN_CONFIG_PULL_UP,
2841         PALMAS_PIN_CONFIG_PULL_DOWN,
2842
2843         PALMAS_PIN_CONFIG_OD_DEFAULT,
2844         PALMAS_PIN_CONFIG_OD_ENABLE,
2845         PALMAS_PIN_CONFIG_OD_DISABLE,
2846 };
2847
2848 /* Palmas Pins name */
2849 enum {
2850         PALMAS_PIN_NAME_GPIO0,
2851         PALMAS_PIN_NAME_GPIO1,
2852         PALMAS_PIN_NAME_GPIO2,
2853         PALMAS_PIN_NAME_GPIO3,
2854         PALMAS_PIN_NAME_GPIO4,
2855         PALMAS_PIN_NAME_GPIO5,
2856         PALMAS_PIN_NAME_GPIO6,
2857         PALMAS_PIN_NAME_GPIO7,
2858         PALMAS_PIN_NAME_VAC,
2859         PALMAS_PIN_NAME_POWERGOOD,
2860         PALMAS_PIN_NAME_NRESWARM,
2861         PALMAS_PIN_NAME_PWRDOWN,
2862         PALMAS_PIN_NAME_GPADC_START,
2863         PALMAS_PIN_NAME_RESET_IN,
2864         PALMAS_PIN_NAME_NSLEEP,
2865         PALMAS_PIN_NAME_ENABLE1,
2866         PALMAS_PIN_NAME_ENABLE2,
2867         PALMAS_PIN_NAME_INT,
2868         PALMAS_PIN_NAME_MAX,
2869 };
2870
2871 extern int palmas_ext_power_req_config(struct palmas *palmas,
2872                 int id,  int ext_pwr_ctrl, bool enable);
2873
2874 static inline int palmas_read(struct palmas *palmas, unsigned int base,
2875                 unsigned int reg, unsigned int *val)
2876 {
2877         unsigned int addr =  PALMAS_BASE_TO_REG(base, reg);
2878         int slave_id = PALMAS_BASE_TO_SLAVE(base);
2879
2880         return regmap_read(palmas->regmap[slave_id], addr, val);
2881 }
2882
2883 static inline int palmas_write(struct palmas *palmas, unsigned int base,
2884                 unsigned int reg, unsigned int value)
2885 {
2886         unsigned int addr = PALMAS_BASE_TO_REG(base, reg);
2887         int slave_id = PALMAS_BASE_TO_SLAVE(base);
2888
2889         return regmap_write(palmas->regmap[slave_id], addr, value);
2890 }
2891
2892 static inline int palmas_bulk_write(struct palmas *palmas, unsigned int base,
2893         unsigned int reg, const void *val, size_t val_count)
2894 {
2895         unsigned int addr = PALMAS_BASE_TO_REG(base, reg);
2896         int slave_id = PALMAS_BASE_TO_SLAVE(base);
2897
2898         return regmap_bulk_write(palmas->regmap[slave_id], addr,
2899                         val, val_count);
2900 }
2901
2902 static inline int palmas_bulk_read(struct palmas *palmas, unsigned int base,
2903                 unsigned int reg, void *val, size_t val_count)
2904 {
2905         unsigned int addr = PALMAS_BASE_TO_REG(base, reg);
2906         int slave_id = PALMAS_BASE_TO_SLAVE(base);
2907
2908         return regmap_bulk_read(palmas->regmap[slave_id], addr,
2909                 val, val_count);
2910 }
2911
2912 static inline int palmas_update_bits(struct palmas *palmas, unsigned int base,
2913         unsigned int reg, unsigned int mask, unsigned int val)
2914 {
2915         unsigned int addr = PALMAS_BASE_TO_REG(base, reg);
2916         int slave_id = PALMAS_BASE_TO_SLAVE(base);
2917
2918         return regmap_update_bits(palmas->regmap[slave_id], addr, mask, val);
2919 }
2920
2921 extern int palmas_irq_get_virq(struct palmas *palmas, int irq);
2922
2923 static inline int palmas_is_es_version_or_less(struct palmas *palmas,
2924         int major, int minor)
2925 {
2926         if (palmas->es_major_version < major)
2927                 return true;
2928
2929         if ((palmas->es_major_version == major) &&
2930                 (palmas->es_minor_version <= minor))
2931                 return true;
2932
2933         return false;
2934 }
2935 #endif /*  __LINUX_MFD_PALMAS_H */