iio: staging: adc: palmas: Support for auto conversion shutdown
[linux-2.6.git] / include / linux / mfd / palmas.h
1 /*
2  * TI Palmas
3  *
4  * Copyright 2011 Texas Instruments Inc.
5  * Copyright (c) 2013, NVIDIA CORPORATION.  All rights reserved.
6  *
7  * Author: Graeme Gregory <gg@slimlogic.co.uk>
8  *
9  *  This program is free software; you can redistribute it and/or modify it
10  *  under  the terms of the GNU General  Public License as published by the
11  *  Free Software Foundation;  either version 2 of the License, or (at your
12  *  option) any later version.
13  *
14  */
15
16 #ifndef __LINUX_MFD_PALMAS_H
17 #define __LINUX_MFD_PALMAS_H
18
19 #include <linux/usb/otg.h>
20 #include <linux/leds.h>
21 #include <linux/regmap.h>
22 #include <linux/regulator/driver.h>
23 #include <linux/iio/machine.h>
24 #include <linux/thermal.h>
25
26 #define PALMAS_NUM_CLIENTS              3
27
28 struct palmas_pmic;
29 struct palmas_rtc;
30
31 #define palmas_rails(_name) "palmas_"#_name
32
33 struct palmas {
34         struct device *dev;
35
36         struct i2c_client *i2c_clients[PALMAS_NUM_CLIENTS];
37         struct regmap *regmap[PALMAS_NUM_CLIENTS];
38
39         /* Stored chip id */
40         int id;
41
42         /* IRQ Data */
43         int irq;
44         u32 irq_mask;
45         struct palmas_irq_chip_data *irq_chip_data;
46
47         /* Child Devices */
48         struct palmas_pmic *pmic;
49         struct palmas_rtc *rtc;
50
51         /* GPIO MUXing */
52         u8 gpio_muxed;
53         u8 led_muxed;
54         u8 pwm_muxed;
55
56         int design_revision;
57         int sw_otp_version;
58         int es_minor_version;
59         int es_major_version;
60 };
61
62 struct palmas_reg_init {
63         /* warm_rest controls the voltage levels after a warm reset
64          *
65          * 0: reload default values from OTP on warm reset
66          * 1: maintain voltage from VSEL on warm reset
67          */
68         int warm_reset;
69
70         /* roof_floor controls whether the regulator uses the i2c style
71          * of DVS or uses the method where a GPIO or other control method is
72          * attached to the NSLEEP/ENABLE1/ENABLE2 pins
73          *
74          * For SMPS
75          *
76          * 0: i2c selection of voltage
77          * 1: pin selection of voltage.
78          *
79          * For LDO unused
80          */
81         int roof_floor;
82
83         /* sleep_mode is the mode loaded to MODE_SLEEP bits as defined in
84          * the data sheet.
85          *
86          * For SMPS
87          *
88          * 0: Off
89          * 1: AUTO
90          * 2: ECO
91          * 3: Forced PWM
92          *
93          * For LDO
94          *
95          * 0: Off
96          * 1: On
97          */
98         int mode_sleep;
99
100         /* tstep is the timestep loaded to the TSTEP register
101          *
102          * For SMPS
103          *
104          * 0: Jump (no slope control)
105          * 1: 10mV/us
106          * 2: 5mV/us
107          * 3: 2.5mV/us
108          *
109          * For LDO unused
110          */
111         int tstep;
112
113         /* voltage_sel is the bitfield loaded onto the SMPSX_VOLTAGE
114          * register. Set this is the default voltage set in OTP needs
115          * to be overridden.
116          */
117         u8 vsel;
118
119         /* Configuration flags */
120         unsigned int config_flags;
121 };
122
123 enum palmas_regulators {
124         /* SMPS regulators */
125         PALMAS_REG_SMPS12,
126         PALMAS_REG_SMPS123,
127         PALMAS_REG_SMPS3,
128         PALMAS_REG_SMPS45,
129         PALMAS_REG_SMPS457,
130         PALMAS_REG_SMPS6,
131         PALMAS_REG_SMPS7,
132         PALMAS_REG_SMPS8,
133         PALMAS_REG_SMPS9,
134         PALMAS_REG_SMPS10,
135         /* LDO regulators */
136         PALMAS_REG_LDO1,
137         PALMAS_REG_LDO2,
138         PALMAS_REG_LDO3,
139         PALMAS_REG_LDO4,
140         PALMAS_REG_LDO5,
141         PALMAS_REG_LDO6,
142         PALMAS_REG_LDO7,
143         PALMAS_REG_LDO8,
144         PALMAS_REG_LDO9,
145         PALMAS_REG_LDOLN,
146         PALMAS_REG_LDOUSB,
147         /* External regulators */
148         PALMAS_REG_REGEN1,
149         PALMAS_REG_REGEN2,
150         PALMAS_REG_REGEN3,
151         PALMAS_REG_SYSEN1,
152         PALMAS_REG_SYSEN2,
153         /* Total number of regulators */
154         PALMAS_NUM_REGS,
155 };
156
157 enum PALMAS_CLOCK32K {
158         PALMAS_CLOCK32KG,
159         PALMAS_CLOCK32KG_AUDIO,
160
161         /* Last entry */
162         PALMAS_CLOCK32K_NR,
163 };
164
165 struct palmas_clk32k_init_data {
166         int clk32k_id;
167         bool enable;
168         int sleep_control;
169 };
170
171 struct palmas_dvfs_init_data {
172         bool    en_pwm;
173         int     ext_ctrl;
174         int     reg_id;
175         bool    step_20mV;
176         int     base_voltage_uV;
177         int     max_voltage_uV;
178 };
179
180 struct palmas_pmic_platform_data {
181         /* An array of pointers to regulator init data indexed by regulator
182          * ID
183          */
184         struct regulator_init_data *reg_data[PALMAS_NUM_REGS];
185
186         /* An array of pointers to structures containing sleep mode and DVS
187          * configuration for regulators indexed by ID
188          */
189         struct palmas_reg_init *reg_init[PALMAS_NUM_REGS];
190
191         /* CL DVFS init data */
192         struct palmas_dvfs_init_data *dvfs_init_data;
193         int dvfs_init_data_size;
194
195         /* use LDO6 for vibrator control */
196         int ldo6_vibrator;
197
198         bool enable_ldo8_tracking;
199         bool disabe_ldo8_tracking_suspend;
200         bool disable_smps10_boost_suspend;
201
202
203 };
204
205 struct palmas_rtc_platform_data {
206         unsigned enable_charging:1;
207         unsigned charging_current_ua;
208 };
209
210 /*
211  * ADC auto_conv property: Generate interrupt when threshold crossed.
212  * @adc_channel_number: ADC channel number for monitoring.
213  * @adc_high_threshold: ADC High raw data for upper threshold to generate int.
214  * @adc_low_threshold: ADC low raw data for lower threshold to generate int.
215  * @adc_shutdown: Shutdown when interrupt generated.
216  */
217 struct palmas_adc_auto_conv_property {
218         int adc_channel_number;
219         int adc_high_threshold;
220         int adc_low_threshold;
221         bool adc_shutdown;
222 };
223
224 struct palmas_gpadc_platform_data {
225         int ch0_current_uA;     /* 0uA, 5uA, 15uA, 20uA */
226         int ch3_current_uA;     /* 0uA, 10uA, 400uA, 800uA */
227         bool ch3_dual_current;
228         bool extended_delay;
229
230         struct iio_map *iio_maps;
231         int auto_conversion_period_ms;
232         struct palmas_adc_auto_conv_property *adc_auto_conv1_data;
233         struct palmas_adc_auto_conv_property *adc_auto_conv2_data;
234 };
235
236 struct palmas_pinctrl_config {
237         int pin_name;
238         int pin_mux_option;
239         int open_drain_state;
240         int pin_pull_up_dn;
241 };
242
243 struct palmas_pinctrl_platform_data {
244         struct palmas_pinctrl_config *pincfg;
245         int num_pinctrl;
246         bool dvfs1_enable;
247         bool dvfs2_enable;
248 };
249
250 struct palmas_extcon_platform_data {
251         const char *connection_name;
252         bool enable_vbus_detection;
253         bool enable_id_pin_detection;
254 };
255
256 struct palmas_platform_data {
257         int gpio_base;
258         int irq_base;
259         int irq_type;
260
261         /* bit value to be loaded to the POWER_CTRL register */
262         u8 power_ctrl;
263
264         struct palmas_pmic_platform_data *pmic_pdata;
265         struct palmas_rtc_platform_data *rtc_pdata;
266         struct palmas_gpadc_platform_data *adc_pdata;
267
268         struct palmas_clk32k_init_data  *clk32k_init_data;
269         int clk32k_init_data_size;
270         bool use_power_off;
271         /* LDOUSB is enabled or disabled on VBUS detection */
272         bool auto_ldousb_en;
273
274         struct palmas_pinctrl_platform_data *pinctrl_pdata;
275         struct palmas_extcon_platform_data *extcon_pdata;
276
277         int watchdog_timer_initial_period;
278
279         /* Hotdie Threshold temperature */
280         unsigned long hd_threshold_temp;
281         char *tz_name;
282
283         /* Long press delay for hard shutdown */
284         int long_press_delay;
285
286         /* system off type by long press key */
287         int poweron_lpk;
288 };
289
290 /* Define the palmas IRQ numbers */
291 enum palmas_irqs {
292         /* INT1 registers */
293         PALMAS_CHARG_DET_N_VBUS_OVV_IRQ,
294         PALMAS_PWRON_IRQ,
295         PALMAS_LONG_PRESS_KEY_IRQ,
296         PALMAS_RPWRON_IRQ,
297         PALMAS_PWRDOWN_IRQ,
298         PALMAS_HOTDIE_IRQ,
299         PALMAS_VSYS_MON_IRQ,
300         PALMAS_VBAT_MON_IRQ,
301         /* INT2 registers */
302         PALMAS_RTC_ALARM_IRQ,
303         PALMAS_RTC_TIMER_IRQ,
304         PALMAS_WDT_IRQ,
305         PALMAS_BATREMOVAL_IRQ,
306         PALMAS_RESET_IN_IRQ,
307         PALMAS_FBI_BB_IRQ,
308         PALMAS_SHORT_IRQ,
309         PALMAS_VAC_ACOK_IRQ,
310         /* INT3 registers */
311         PALMAS_GPADC_AUTO_0_IRQ,
312         PALMAS_GPADC_AUTO_1_IRQ,
313         PALMAS_GPADC_EOC_SW_IRQ,
314         PALMAS_GPADC_EOC_RT_IRQ,
315         PALMAS_ID_OTG_IRQ,
316         PALMAS_ID_IRQ,
317         PALMAS_VBUS_OTG_IRQ,
318         PALMAS_VBUS_IRQ,
319         /* INT4 registers */
320         PALMAS_GPIO_0_IRQ,
321         PALMAS_GPIO_1_IRQ,
322         PALMAS_GPIO_2_IRQ,
323         PALMAS_GPIO_3_IRQ,
324         PALMAS_GPIO_4_IRQ,
325         PALMAS_GPIO_5_IRQ,
326         PALMAS_GPIO_6_IRQ,
327         PALMAS_GPIO_7_IRQ,
328         /* Total Number IRQs */
329         PALMAS_NUM_IRQ,
330 };
331
332 struct palmas_pmic {
333         struct palmas *palmas;
334         struct device *dev;
335         struct regulator_desc desc[PALMAS_NUM_REGS];
336         struct regulator_dev *rdev[PALMAS_NUM_REGS];
337         struct mutex mutex;
338
339         int smps123;
340         int smps457;
341         bool smps10_regulator_enabled;
342         bool smps10_boost_disable_deferred;
343
344         unsigned int ramp_delay[PALMAS_NUM_REGS];
345         unsigned int current_mode_reg[PALMAS_NUM_REGS];
346
347         int range[PALMAS_REG_SMPS10];
348         unsigned long roof_floor[PALMAS_NUM_REGS];
349         unsigned long config_flags[PALMAS_NUM_REGS];
350 };
351
352 /* defines so we can store the mux settings */
353 #define PALMAS_GPIO_0_MUXED                                     (1 << 0)
354 #define PALMAS_GPIO_1_MUXED                                     (1 << 1)
355 #define PALMAS_GPIO_2_MUXED                                     (1 << 2)
356 #define PALMAS_GPIO_3_MUXED                                     (1 << 3)
357 #define PALMAS_GPIO_4_MUXED                                     (1 << 4)
358 #define PALMAS_GPIO_5_MUXED                                     (1 << 5)
359 #define PALMAS_GPIO_6_MUXED                                     (1 << 6)
360 #define PALMAS_GPIO_7_MUXED                                     (1 << 7)
361
362 #define PALMAS_LED1_MUXED                                       (1 << 0)
363 #define PALMAS_LED2_MUXED                                       (1 << 1)
364
365 #define PALMAS_PWM1_MUXED                                       (1 << 0)
366 #define PALMAS_PWM2_MUXED                                       (1 << 1)
367
368 /* helper macro to get correct slave number */
369 #define PALMAS_BASE_TO_SLAVE(x)         ((x >> 8) - 1)
370 #define PALMAS_BASE_TO_REG(x, y)        ((x & 0xff) + y)
371 #define RTC_SLAVE                       0
372
373 /* Base addresses of IP blocks in Palmas */
374 #define PALMAS_SMPS_DVS_BASE                                    0x20
375 #define PALMAS_RTC_BASE                                         0x100
376 #define PALMAS_VALIDITY_BASE                                    0x118
377 #define PALMAS_SMPS_BASE                                        0x120
378 #define PALMAS_LDO_BASE                                         0x150
379 #define PALMAS_DVFS_BASE                                        0x180
380 #define PALMAS_PMU_CONTROL_BASE                                 0x1A0
381 #define PALMAS_RESOURCE_BASE                                    0x1D4
382 #define PALMAS_PU_PD_OD_BASE                                    0x1F4
383 #define PALMAS_LED_BASE                                         0x200
384 #define PALMAS_INTERRUPT_BASE                                   0x210
385 #define PALMAS_USB_OTG_BASE                                     0x250
386 #define PALMAS_VIBRATOR_BASE                                    0x270
387 #define PALMAS_GPIO_BASE                                        0x280
388 #define PALMAS_USB_BASE                                         0x290
389 #define PALMAS_GPADC_BASE                                       0x2C0
390 #define PALMAS_TRIM_GPADC_BASE                                  0x3CD
391 #define PALMAS_PAGE3_BASE                                       0x300
392
393 /* Registers for function RTC */
394 #define PALMAS_SECONDS_REG                                      0x0
395 #define PALMAS_MINUTES_REG                                      0x1
396 #define PALMAS_HOURS_REG                                        0x2
397 #define PALMAS_DAYS_REG                                         0x3
398 #define PALMAS_MONTHS_REG                                       0x4
399 #define PALMAS_YEARS_REG                                        0x5
400 #define PALMAS_WEEKS_REG                                        0x6
401 #define PALMAS_ALARM_SECONDS_REG                                0x8
402 #define PALMAS_ALARM_MINUTES_REG                                0x9
403 #define PALMAS_ALARM_HOURS_REG                                  0xA
404 #define PALMAS_ALARM_DAYS_REG                                   0xB
405 #define PALMAS_ALARM_MONTHS_REG                                 0xC
406 #define PALMAS_ALARM_YEARS_REG                                  0xD
407 #define PALMAS_RTC_CTRL_REG                                     0x10
408 #define PALMAS_RTC_STATUS_REG                                   0x11
409 #define PALMAS_RTC_INTERRUPTS_REG                               0x12
410 #define PALMAS_RTC_COMP_LSB_REG                                 0x13
411 #define PALMAS_RTC_COMP_MSB_REG                                 0x14
412 #define PALMAS_RTC_RES_PROG_REG                                 0x15
413 #define PALMAS_RTC_RESET_STATUS_REG                             0x16
414
415 /* Bit definitions for SECONDS_REG */
416 #define PALMAS_SECONDS_REG_SEC1_MASK                            0x70
417 #define PALMAS_SECONDS_REG_SEC1_SHIFT                           4
418 #define PALMAS_SECONDS_REG_SEC0_MASK                            0x0f
419 #define PALMAS_SECONDS_REG_SEC0_SHIFT                           0
420
421 /* Bit definitions for MINUTES_REG */
422 #define PALMAS_MINUTES_REG_MIN1_MASK                            0x70
423 #define PALMAS_MINUTES_REG_MIN1_SHIFT                           4
424 #define PALMAS_MINUTES_REG_MIN0_MASK                            0x0f
425 #define PALMAS_MINUTES_REG_MIN0_SHIFT                           0
426
427 /* Bit definitions for HOURS_REG */
428 #define PALMAS_HOURS_REG_PM_NAM                                 0x80
429 #define PALMAS_HOURS_REG_PM_NAM_SHIFT                           7
430 #define PALMAS_HOURS_REG_HOUR1_MASK                             0x30
431 #define PALMAS_HOURS_REG_HOUR1_SHIFT                            4
432 #define PALMAS_HOURS_REG_HOUR0_MASK                             0x0f
433 #define PALMAS_HOURS_REG_HOUR0_SHIFT                            0
434
435 /* Bit definitions for DAYS_REG */
436 #define PALMAS_DAYS_REG_DAY1_MASK                               0x30
437 #define PALMAS_DAYS_REG_DAY1_SHIFT                              4
438 #define PALMAS_DAYS_REG_DAY0_MASK                               0x0f
439 #define PALMAS_DAYS_REG_DAY0_SHIFT                              0
440
441 /* Bit definitions for MONTHS_REG */
442 #define PALMAS_MONTHS_REG_MONTH1                                0x10
443 #define PALMAS_MONTHS_REG_MONTH1_SHIFT                          4
444 #define PALMAS_MONTHS_REG_MONTH0_MASK                           0x0f
445 #define PALMAS_MONTHS_REG_MONTH0_SHIFT                          0
446
447 /* Bit definitions for YEARS_REG */
448 #define PALMAS_YEARS_REG_YEAR1_MASK                             0xf0
449 #define PALMAS_YEARS_REG_YEAR1_SHIFT                            4
450 #define PALMAS_YEARS_REG_YEAR0_MASK                             0x0f
451 #define PALMAS_YEARS_REG_YEAR0_SHIFT                            0
452
453 /* Bit definitions for WEEKS_REG */
454 #define PALMAS_WEEKS_REG_WEEK_MASK                              0x07
455 #define PALMAS_WEEKS_REG_WEEK_SHIFT                             0
456
457 /* Bit definitions for ALARM_SECONDS_REG */
458 #define PALMAS_ALARM_SECONDS_REG_ALARM_SEC1_MASK                0x70
459 #define PALMAS_ALARM_SECONDS_REG_ALARM_SEC1_SHIFT               4
460 #define PALMAS_ALARM_SECONDS_REG_ALARM_SEC0_MASK                0x0f
461 #define PALMAS_ALARM_SECONDS_REG_ALARM_SEC0_SHIFT               0
462
463 /* Bit definitions for ALARM_MINUTES_REG */
464 #define PALMAS_ALARM_MINUTES_REG_ALARM_MIN1_MASK                0x70
465 #define PALMAS_ALARM_MINUTES_REG_ALARM_MIN1_SHIFT               4
466 #define PALMAS_ALARM_MINUTES_REG_ALARM_MIN0_MASK                0x0f
467 #define PALMAS_ALARM_MINUTES_REG_ALARM_MIN0_SHIFT               0
468
469 /* Bit definitions for ALARM_HOURS_REG */
470 #define PALMAS_ALARM_HOURS_REG_ALARM_PM_NAM                     0x80
471 #define PALMAS_ALARM_HOURS_REG_ALARM_PM_NAM_SHIFT               7
472 #define PALMAS_ALARM_HOURS_REG_ALARM_HOUR1_MASK                 0x30
473 #define PALMAS_ALARM_HOURS_REG_ALARM_HOUR1_SHIFT                4
474 #define PALMAS_ALARM_HOURS_REG_ALARM_HOUR0_MASK                 0x0f
475 #define PALMAS_ALARM_HOURS_REG_ALARM_HOUR0_SHIFT                0
476
477 /* Bit definitions for ALARM_DAYS_REG */
478 #define PALMAS_ALARM_DAYS_REG_ALARM_DAY1_MASK                   0x30
479 #define PALMAS_ALARM_DAYS_REG_ALARM_DAY1_SHIFT                  4
480 #define PALMAS_ALARM_DAYS_REG_ALARM_DAY0_MASK                   0x0f
481 #define PALMAS_ALARM_DAYS_REG_ALARM_DAY0_SHIFT                  0
482
483 /* Bit definitions for ALARM_MONTHS_REG */
484 #define PALMAS_ALARM_MONTHS_REG_ALARM_MONTH1                    0x10
485 #define PALMAS_ALARM_MONTHS_REG_ALARM_MONTH1_SHIFT              4
486 #define PALMAS_ALARM_MONTHS_REG_ALARM_MONTH0_MASK               0x0f
487 #define PALMAS_ALARM_MONTHS_REG_ALARM_MONTH0_SHIFT              0
488
489 /* Bit definitions for ALARM_YEARS_REG */
490 #define PALMAS_ALARM_YEARS_REG_ALARM_YEAR1_MASK                 0xf0
491 #define PALMAS_ALARM_YEARS_REG_ALARM_YEAR1_SHIFT                4
492 #define PALMAS_ALARM_YEARS_REG_ALARM_YEAR0_MASK                 0x0f
493 #define PALMAS_ALARM_YEARS_REG_ALARM_YEAR0_SHIFT                0
494
495 /* Bit definitions for RTC_CTRL_REG */
496 #define PALMAS_RTC_CTRL_REG_RTC_V_OPT                           0x80
497 #define PALMAS_RTC_CTRL_REG_RTC_V_OPT_SHIFT                     7
498 #define PALMAS_RTC_CTRL_REG_GET_TIME                            0x40
499 #define PALMAS_RTC_CTRL_REG_GET_TIME_SHIFT                      6
500 #define PALMAS_RTC_CTRL_REG_SET_32_COUNTER                      0x20
501 #define PALMAS_RTC_CTRL_REG_SET_32_COUNTER_SHIFT                5
502 #define PALMAS_RTC_CTRL_REG_TEST_MODE                           0x10
503 #define PALMAS_RTC_CTRL_REG_TEST_MODE_SHIFT                     4
504 #define PALMAS_RTC_CTRL_REG_MODE_12_24                          0x08
505 #define PALMAS_RTC_CTRL_REG_MODE_12_24_SHIFT                    3
506 #define PALMAS_RTC_CTRL_REG_AUTO_COMP                           0x04
507 #define PALMAS_RTC_CTRL_REG_AUTO_COMP_SHIFT                     2
508 #define PALMAS_RTC_CTRL_REG_ROUND_30S                           0x02
509 #define PALMAS_RTC_CTRL_REG_ROUND_30S_SHIFT                     1
510 #define PALMAS_RTC_CTRL_REG_STOP_RTC                            0x01
511 #define PALMAS_RTC_CTRL_REG_STOP_RTC_SHIFT                      0
512
513 /* Bit definitions for RTC_STATUS_REG */
514 #define PALMAS_RTC_STATUS_REG_POWER_UP                          0x80
515 #define PALMAS_RTC_STATUS_REG_POWER_UP_SHIFT                    7
516 #define PALMAS_RTC_STATUS_REG_ALARM                             0x40
517 #define PALMAS_RTC_STATUS_REG_ALARM_SHIFT                       6
518 #define PALMAS_RTC_STATUS_REG_EVENT_1D                          0x20
519 #define PALMAS_RTC_STATUS_REG_EVENT_1D_SHIFT                    5
520 #define PALMAS_RTC_STATUS_REG_EVENT_1H                          0x10
521 #define PALMAS_RTC_STATUS_REG_EVENT_1H_SHIFT                    4
522 #define PALMAS_RTC_STATUS_REG_EVENT_1M                          0x08
523 #define PALMAS_RTC_STATUS_REG_EVENT_1M_SHIFT                    3
524 #define PALMAS_RTC_STATUS_REG_EVENT_1S                          0x04
525 #define PALMAS_RTC_STATUS_REG_EVENT_1S_SHIFT                    2
526 #define PALMAS_RTC_STATUS_REG_RUN                               0x02
527 #define PALMAS_RTC_STATUS_REG_RUN_SHIFT                         1
528
529 /* Bit definitions for RTC_INTERRUPTS_REG */
530 #define PALMAS_RTC_INTERRUPTS_REG_IT_SLEEP_MASK_EN              0x10
531 #define PALMAS_RTC_INTERRUPTS_REG_IT_SLEEP_MASK_EN_SHIFT        4
532 #define PALMAS_RTC_INTERRUPTS_REG_IT_ALARM                      0x08
533 #define PALMAS_RTC_INTERRUPTS_REG_IT_ALARM_SHIFT                3
534 #define PALMAS_RTC_INTERRUPTS_REG_IT_TIMER                      0x04
535 #define PALMAS_RTC_INTERRUPTS_REG_IT_TIMER_SHIFT                2
536 #define PALMAS_RTC_INTERRUPTS_REG_EVERY_MASK                    0x03
537 #define PALMAS_RTC_INTERRUPTS_REG_EVERY_SHIFT                   0
538
539 /* Bit definitions for RTC_COMP_LSB_REG */
540 #define PALMAS_RTC_COMP_LSB_REG_RTC_COMP_LSB_MASK               0xff
541 #define PALMAS_RTC_COMP_LSB_REG_RTC_COMP_LSB_SHIFT              0
542
543 /* Bit definitions for RTC_COMP_MSB_REG */
544 #define PALMAS_RTC_COMP_MSB_REG_RTC_COMP_MSB_MASK               0xff
545 #define PALMAS_RTC_COMP_MSB_REG_RTC_COMP_MSB_SHIFT              0
546
547 /* Bit definitions for RTC_RES_PROG_REG */
548 #define PALMAS_RTC_RES_PROG_REG_SW_RES_PROG_MASK                0x3f
549 #define PALMAS_RTC_RES_PROG_REG_SW_RES_PROG_SHIFT               0
550
551 /* Bit definitions for RTC_RESET_STATUS_REG */
552 #define PALMAS_RTC_RESET_STATUS_REG_RESET_STATUS                0x01
553 #define PALMAS_RTC_RESET_STATUS_REG_RESET_STATUS_SHIFT          0
554
555 /* Registers for function BACKUP */
556 #define PALMAS_BACKUP0                                          0x0
557 #define PALMAS_BACKUP1                                          0x1
558 #define PALMAS_BACKUP2                                          0x2
559 #define PALMAS_BACKUP3                                          0x3
560 #define PALMAS_BACKUP4                                          0x4
561 #define PALMAS_BACKUP5                                          0x5
562 #define PALMAS_BACKUP6                                          0x6
563 #define PALMAS_BACKUP7                                          0x7
564
565 /* Bit definitions for BACKUP0 */
566 #define PALMAS_BACKUP0_BACKUP_MASK                              0xff
567 #define PALMAS_BACKUP0_BACKUP_SHIFT                             0
568
569 /* Bit definitions for BACKUP1 */
570 #define PALMAS_BACKUP1_BACKUP_MASK                              0xff
571 #define PALMAS_BACKUP1_BACKUP_SHIFT                             0
572
573 /* Bit definitions for BACKUP2 */
574 #define PALMAS_BACKUP2_BACKUP_MASK                              0xff
575 #define PALMAS_BACKUP2_BACKUP_SHIFT                             0
576
577 /* Bit definitions for BACKUP3 */
578 #define PALMAS_BACKUP3_BACKUP_MASK                              0xff
579 #define PALMAS_BACKUP3_BACKUP_SHIFT                             0
580
581 /* Bit definitions for BACKUP4 */
582 #define PALMAS_BACKUP4_BACKUP_MASK                              0xff
583 #define PALMAS_BACKUP4_BACKUP_SHIFT                             0
584
585 /* Bit definitions for BACKUP5 */
586 #define PALMAS_BACKUP5_BACKUP_MASK                              0xff
587 #define PALMAS_BACKUP5_BACKUP_SHIFT                             0
588
589 /* Bit definitions for BACKUP6 */
590 #define PALMAS_BACKUP6_BACKUP_MASK                              0xff
591 #define PALMAS_BACKUP6_BACKUP_SHIFT                             0
592
593 /* Bit definitions for BACKUP7 */
594 #define PALMAS_BACKUP7_BACKUP_MASK                              0xff
595 #define PALMAS_BACKUP7_BACKUP_SHIFT                             0
596
597 /* Registers for function SMPS */
598 #define PALMAS_SMPS12_CTRL                                      0x0
599 #define PALMAS_SMPS12_TSTEP                                     0x1
600 #define PALMAS_SMPS12_FORCE                                     0x2
601 #define PALMAS_SMPS12_VOLTAGE                                   0x3
602 #define PALMAS_SMPS3_CTRL                                       0x4
603 #define PALMAS_SMPS3_VOLTAGE                                    0x7
604 #define PALMAS_SMPS45_CTRL                                      0x8
605 #define PALMAS_SMPS45_TSTEP                                     0x9
606 #define PALMAS_SMPS45_FORCE                                     0xA
607 #define PALMAS_SMPS45_VOLTAGE                                   0xB
608 #define PALMAS_SMPS6_CTRL                                       0xC
609 #define PALMAS_SMPS6_TSTEP                                      0xD
610 #define PALMAS_SMPS6_FORCE                                      0xE
611 #define PALMAS_SMPS6_VOLTAGE                                    0xF
612 #define PALMAS_SMPS7_CTRL                                       0x10
613 #define PALMAS_SMPS7_VOLTAGE                                    0x13
614 #define PALMAS_SMPS8_CTRL                                       0x14
615 #define PALMAS_SMPS8_TSTEP                                      0x15
616 #define PALMAS_SMPS8_FORCE                                      0x16
617 #define PALMAS_SMPS8_VOLTAGE                                    0x17
618 #define PALMAS_SMPS9_CTRL                                       0x18
619 #define PALMAS_SMPS9_VOLTAGE                                    0x1B
620 #define PALMAS_SMPS10_CTRL                                      0x1C
621 #define PALMAS_SMPS10_STATUS                                    0x1F
622 #define PALMAS_SMPS_CTRL                                        0x24
623 #define PALMAS_SMPS_PD_CTRL                                     0x25
624 #define PALMAS_SMPS_DITHER_EN                                   0x26
625 #define PALMAS_SMPS_THERMAL_EN                                  0x27
626 #define PALMAS_SMPS_THERMAL_STATUS                              0x28
627 #define PALMAS_SMPS_SHORT_STATUS                                0x29
628 #define PALMAS_SMPS_NEGATIVE_CURRENT_LIMIT_EN                   0x2A
629 #define PALMAS_SMPS_POWERGOOD_MASK1                             0x2B
630 #define PALMAS_SMPS_POWERGOOD_MASK2                             0x2C
631
632 /* Bit definitions for SMPS12_CTRL */
633 #define PALMAS_SMPS12_CTRL_WR_S                                 0x80
634 #define PALMAS_SMPS12_CTRL_WR_S_SHIFT                           7
635 #define PALMAS_SMPS12_CTRL_ROOF_FLOOR_EN                        0x40
636 #define PALMAS_SMPS12_CTRL_ROOF_FLOOR_EN_SHIFT                  6
637 #define PALMAS_SMPS12_CTRL_STATUS_MASK                          0x30
638 #define PALMAS_SMPS12_CTRL_STATUS_SHIFT                         4
639 #define PALMAS_SMPS12_CTRL_MODE_SLEEP_MASK                      0x0c
640 #define PALMAS_SMPS12_CTRL_MODE_SLEEP_SHIFT                     2
641 #define PALMAS_SMPS12_CTRL_MODE_ACTIVE_MASK                     0x03
642 #define PALMAS_SMPS12_CTRL_MODE_ACTIVE_SHIFT                    0
643
644 /* Bit definitions for SMPS12_TSTEP */
645 #define PALMAS_SMPS12_TSTEP_TSTEP_MASK                          0x03
646 #define PALMAS_SMPS12_TSTEP_TSTEP_SHIFT                         0
647
648 /* Bit definitions for SMPS12_FORCE */
649 #define PALMAS_SMPS12_FORCE_CMD                                 0x80
650 #define PALMAS_SMPS12_FORCE_CMD_SHIFT                           7
651 #define PALMAS_SMPS12_FORCE_VSEL_MASK                           0x7f
652 #define PALMAS_SMPS12_FORCE_VSEL_SHIFT                          0
653
654 /* Bit definitions for SMPS12_VOLTAGE */
655 #define PALMAS_SMPS12_VOLTAGE_RANGE                             0x80
656 #define PALMAS_SMPS12_VOLTAGE_RANGE_SHIFT                       7
657 #define PALMAS_SMPS12_VOLTAGE_VSEL_MASK                         0x7f
658 #define PALMAS_SMPS12_VOLTAGE_VSEL_SHIFT                        0
659
660 /* Bit definitions for SMPS3_CTRL */
661 #define PALMAS_SMPS3_CTRL_WR_S                                  0x80
662 #define PALMAS_SMPS3_CTRL_WR_S_SHIFT                            7
663 #define PALMAS_SMPS3_CTRL_STATUS_MASK                           0x30
664 #define PALMAS_SMPS3_CTRL_STATUS_SHIFT                          4
665 #define PALMAS_SMPS3_CTRL_MODE_SLEEP_MASK                       0x0c
666 #define PALMAS_SMPS3_CTRL_MODE_SLEEP_SHIFT                      2
667 #define PALMAS_SMPS3_CTRL_MODE_ACTIVE_MASK                      0x03
668 #define PALMAS_SMPS3_CTRL_MODE_ACTIVE_SHIFT                     0
669
670 /* Bit definitions for SMPS3_VOLTAGE */
671 #define PALMAS_SMPS3_VOLTAGE_RANGE                              0x80
672 #define PALMAS_SMPS3_VOLTAGE_RANGE_SHIFT                        7
673 #define PALMAS_SMPS3_VOLTAGE_VSEL_MASK                          0x7f
674 #define PALMAS_SMPS3_VOLTAGE_VSEL_SHIFT                         0
675
676 /* Bit definitions for SMPS45_CTRL */
677 #define PALMAS_SMPS45_CTRL_WR_S                                 0x80
678 #define PALMAS_SMPS45_CTRL_WR_S_SHIFT                           7
679 #define PALMAS_SMPS45_CTRL_ROOF_FLOOR_EN                        0x40
680 #define PALMAS_SMPS45_CTRL_ROOF_FLOOR_EN_SHIFT                  6
681 #define PALMAS_SMPS45_CTRL_STATUS_MASK                          0x30
682 #define PALMAS_SMPS45_CTRL_STATUS_SHIFT                         4
683 #define PALMAS_SMPS45_CTRL_MODE_SLEEP_MASK                      0x0c
684 #define PALMAS_SMPS45_CTRL_MODE_SLEEP_SHIFT                     2
685 #define PALMAS_SMPS45_CTRL_MODE_ACTIVE_MASK                     0x03
686 #define PALMAS_SMPS45_CTRL_MODE_ACTIVE_SHIFT                    0
687
688 /* Bit definitions for SMPS45_TSTEP */
689 #define PALMAS_SMPS45_TSTEP_TSTEP_MASK                          0x03
690 #define PALMAS_SMPS45_TSTEP_TSTEP_SHIFT                         0
691
692 /* Bit definitions for SMPS45_FORCE */
693 #define PALMAS_SMPS45_FORCE_CMD                                 0x80
694 #define PALMAS_SMPS45_FORCE_CMD_SHIFT                           7
695 #define PALMAS_SMPS45_FORCE_VSEL_MASK                           0x7f
696 #define PALMAS_SMPS45_FORCE_VSEL_SHIFT                          0
697
698 /* Bit definitions for SMPS45_VOLTAGE */
699 #define PALMAS_SMPS45_VOLTAGE_RANGE                             0x80
700 #define PALMAS_SMPS45_VOLTAGE_RANGE_SHIFT                       7
701 #define PALMAS_SMPS45_VOLTAGE_VSEL_MASK                         0x7f
702 #define PALMAS_SMPS45_VOLTAGE_VSEL_SHIFT                        0
703
704 /* Bit definitions for SMPS6_CTRL */
705 #define PALMAS_SMPS6_CTRL_WR_S                                  0x80
706 #define PALMAS_SMPS6_CTRL_WR_S_SHIFT                            7
707 #define PALMAS_SMPS6_CTRL_ROOF_FLOOR_EN                         0x40
708 #define PALMAS_SMPS6_CTRL_ROOF_FLOOR_EN_SHIFT                   6
709 #define PALMAS_SMPS6_CTRL_STATUS_MASK                           0x30
710 #define PALMAS_SMPS6_CTRL_STATUS_SHIFT                          4
711 #define PALMAS_SMPS6_CTRL_MODE_SLEEP_MASK                       0x0c
712 #define PALMAS_SMPS6_CTRL_MODE_SLEEP_SHIFT                      2
713 #define PALMAS_SMPS6_CTRL_MODE_ACTIVE_MASK                      0x03
714 #define PALMAS_SMPS6_CTRL_MODE_ACTIVE_SHIFT                     0
715
716 /* Bit definitions for SMPS6_TSTEP */
717 #define PALMAS_SMPS6_TSTEP_TSTEP_MASK                           0x03
718 #define PALMAS_SMPS6_TSTEP_TSTEP_SHIFT                          0
719
720 /* Bit definitions for SMPS6_FORCE */
721 #define PALMAS_SMPS6_FORCE_CMD                                  0x80
722 #define PALMAS_SMPS6_FORCE_CMD_SHIFT                            7
723 #define PALMAS_SMPS6_FORCE_VSEL_MASK                            0x7f
724 #define PALMAS_SMPS6_FORCE_VSEL_SHIFT                           0
725
726 /* Bit definitions for SMPS6_VOLTAGE */
727 #define PALMAS_SMPS6_VOLTAGE_RANGE                              0x80
728 #define PALMAS_SMPS6_VOLTAGE_RANGE_SHIFT                        7
729 #define PALMAS_SMPS6_VOLTAGE_VSEL_MASK                          0x7f
730 #define PALMAS_SMPS6_VOLTAGE_VSEL_SHIFT                         0
731
732 /* Bit definitions for SMPS7_CTRL */
733 #define PALMAS_SMPS7_CTRL_WR_S                                  0x80
734 #define PALMAS_SMPS7_CTRL_WR_S_SHIFT                            7
735 #define PALMAS_SMPS7_CTRL_STATUS_MASK                           0x30
736 #define PALMAS_SMPS7_CTRL_STATUS_SHIFT                          4
737 #define PALMAS_SMPS7_CTRL_MODE_SLEEP_MASK                       0x0c
738 #define PALMAS_SMPS7_CTRL_MODE_SLEEP_SHIFT                      2
739 #define PALMAS_SMPS7_CTRL_MODE_ACTIVE_MASK                      0x03
740 #define PALMAS_SMPS7_CTRL_MODE_ACTIVE_SHIFT                     0
741
742 /* Bit definitions for SMPS7_VOLTAGE */
743 #define PALMAS_SMPS7_VOLTAGE_RANGE                              0x80
744 #define PALMAS_SMPS7_VOLTAGE_RANGE_SHIFT                        7
745 #define PALMAS_SMPS7_VOLTAGE_VSEL_MASK                          0x7f
746 #define PALMAS_SMPS7_VOLTAGE_VSEL_SHIFT                         0
747
748 /* Bit definitions for SMPS8_CTRL */
749 #define PALMAS_SMPS8_CTRL_WR_S                                  0x80
750 #define PALMAS_SMPS8_CTRL_WR_S_SHIFT                            7
751 #define PALMAS_SMPS8_CTRL_ROOF_FLOOR_EN                         0x40
752 #define PALMAS_SMPS8_CTRL_ROOF_FLOOR_EN_SHIFT                   6
753 #define PALMAS_SMPS8_CTRL_STATUS_MASK                           0x30
754 #define PALMAS_SMPS8_CTRL_STATUS_SHIFT                          4
755 #define PALMAS_SMPS8_CTRL_MODE_SLEEP_MASK                       0x0c
756 #define PALMAS_SMPS8_CTRL_MODE_SLEEP_SHIFT                      2
757 #define PALMAS_SMPS8_CTRL_MODE_ACTIVE_MASK                      0x03
758 #define PALMAS_SMPS8_CTRL_MODE_ACTIVE_SHIFT                     0
759
760 /* Bit definitions for SMPS8_TSTEP */
761 #define PALMAS_SMPS8_TSTEP_TSTEP_MASK                           0x03
762 #define PALMAS_SMPS8_TSTEP_TSTEP_SHIFT                          0
763
764 /* Bit definitions for SMPS8_FORCE */
765 #define PALMAS_SMPS8_FORCE_CMD                                  0x80
766 #define PALMAS_SMPS8_FORCE_CMD_SHIFT                            7
767 #define PALMAS_SMPS8_FORCE_VSEL_MASK                            0x7f
768 #define PALMAS_SMPS8_FORCE_VSEL_SHIFT                           0
769
770 /* Bit definitions for SMPS8_VOLTAGE */
771 #define PALMAS_SMPS8_VOLTAGE_RANGE                              0x80
772 #define PALMAS_SMPS8_VOLTAGE_RANGE_SHIFT                        7
773 #define PALMAS_SMPS8_VOLTAGE_VSEL_MASK                          0x7f
774 #define PALMAS_SMPS8_VOLTAGE_VSEL_SHIFT                         0
775
776 /* Bit definitions for SMPS9_CTRL */
777 #define PALMAS_SMPS9_CTRL_WR_S                                  0x80
778 #define PALMAS_SMPS9_CTRL_WR_S_SHIFT                            7
779 #define PALMAS_SMPS9_CTRL_STATUS_MASK                           0x30
780 #define PALMAS_SMPS9_CTRL_STATUS_SHIFT                          4
781 #define PALMAS_SMPS9_CTRL_MODE_SLEEP_MASK                       0x0c
782 #define PALMAS_SMPS9_CTRL_MODE_SLEEP_SHIFT                      2
783 #define PALMAS_SMPS9_CTRL_MODE_ACTIVE_MASK                      0x03
784 #define PALMAS_SMPS9_CTRL_MODE_ACTIVE_SHIFT                     0
785
786 /* Bit definitions for SMPS9_VOLTAGE */
787 #define PALMAS_SMPS9_VOLTAGE_RANGE                              0x80
788 #define PALMAS_SMPS9_VOLTAGE_RANGE_SHIFT                        7
789 #define PALMAS_SMPS9_VOLTAGE_VSEL_MASK                          0x7f
790 #define PALMAS_SMPS9_VOLTAGE_VSEL_SHIFT                         0
791
792 /* Bit definitions for SMPS10_CTRL */
793 #define PALMAS_SMPS10_CTRL_MODE_SLEEP_MASK                      0xf0
794 #define PALMAS_SMPS10_CTRL_MODE_SLEEP_SHIFT                     4
795 #define PALMAS_SMPS10_CTRL_MODE_ACTIVE_MASK                     0x0f
796 #define PALMAS_SMPS10_CTRL_MODE_ACTIVE_SHIFT                    0
797
798 /* Bit definitions for SMPS10_STATUS */
799 #define PALMAS_SMPS10_STATUS_STATUS_MASK                        0x0f
800 #define PALMAS_SMPS10_STATUS_STATUS_SHIFT                       0
801
802 /* Bit definitions for SMPS_CTRL */
803 #define PALMAS_SMPS_CTRL_SMPS45_SMPS457_EN                      0x20
804 #define PALMAS_SMPS_CTRL_SMPS45_SMPS457_EN_SHIFT                5
805 #define PALMAS_SMPS_CTRL_SMPS12_SMPS123_EN                      0x10
806 #define PALMAS_SMPS_CTRL_SMPS12_SMPS123_EN_SHIFT                4
807 #define PALMAS_SMPS_CTRL_SMPS45_PHASE_CTRL_MASK                 0x0c
808 #define PALMAS_SMPS_CTRL_SMPS45_PHASE_CTRL_SHIFT                2
809 #define PALMAS_SMPS_CTRL_SMPS123_PHASE_CTRL_MASK                0x03
810 #define PALMAS_SMPS_CTRL_SMPS123_PHASE_CTRL_SHIFT               0
811
812 /* Bit definitions for SMPS_PD_CTRL */
813 #define PALMAS_SMPS_PD_CTRL_SMPS9                               0x40
814 #define PALMAS_SMPS_PD_CTRL_SMPS9_SHIFT                         6
815 #define PALMAS_SMPS_PD_CTRL_SMPS8                               0x20
816 #define PALMAS_SMPS_PD_CTRL_SMPS8_SHIFT                         5
817 #define PALMAS_SMPS_PD_CTRL_SMPS7                               0x10
818 #define PALMAS_SMPS_PD_CTRL_SMPS7_SHIFT                         4
819 #define PALMAS_SMPS_PD_CTRL_SMPS6                               0x08
820 #define PALMAS_SMPS_PD_CTRL_SMPS6_SHIFT                         3
821 #define PALMAS_SMPS_PD_CTRL_SMPS45                              0x04
822 #define PALMAS_SMPS_PD_CTRL_SMPS45_SHIFT                        2
823 #define PALMAS_SMPS_PD_CTRL_SMPS3                               0x02
824 #define PALMAS_SMPS_PD_CTRL_SMPS3_SHIFT                         1
825 #define PALMAS_SMPS_PD_CTRL_SMPS12                              0x01
826 #define PALMAS_SMPS_PD_CTRL_SMPS12_SHIFT                        0
827
828 /* Bit definitions for SMPS_THERMAL_EN */
829 #define PALMAS_SMPS_THERMAL_EN_SMPS9                            0x40
830 #define PALMAS_SMPS_THERMAL_EN_SMPS9_SHIFT                      6
831 #define PALMAS_SMPS_THERMAL_EN_SMPS8                            0x20
832 #define PALMAS_SMPS_THERMAL_EN_SMPS8_SHIFT                      5
833 #define PALMAS_SMPS_THERMAL_EN_SMPS6                            0x08
834 #define PALMAS_SMPS_THERMAL_EN_SMPS6_SHIFT                      3
835 #define PALMAS_SMPS_THERMAL_EN_SMPS457                          0x04
836 #define PALMAS_SMPS_THERMAL_EN_SMPS457_SHIFT                    2
837 #define PALMAS_SMPS_THERMAL_EN_SMPS123                          0x01
838 #define PALMAS_SMPS_THERMAL_EN_SMPS123_SHIFT                    0
839
840 /* Bit definitions for SMPS_THERMAL_STATUS */
841 #define PALMAS_SMPS_THERMAL_STATUS_SMPS9                        0x40
842 #define PALMAS_SMPS_THERMAL_STATUS_SMPS9_SHIFT                  6
843 #define PALMAS_SMPS_THERMAL_STATUS_SMPS8                        0x20
844 #define PALMAS_SMPS_THERMAL_STATUS_SMPS8_SHIFT                  5
845 #define PALMAS_SMPS_THERMAL_STATUS_SMPS6                        0x08
846 #define PALMAS_SMPS_THERMAL_STATUS_SMPS6_SHIFT                  3
847 #define PALMAS_SMPS_THERMAL_STATUS_SMPS457                      0x04
848 #define PALMAS_SMPS_THERMAL_STATUS_SMPS457_SHIFT                2
849 #define PALMAS_SMPS_THERMAL_STATUS_SMPS123                      0x01
850 #define PALMAS_SMPS_THERMAL_STATUS_SMPS123_SHIFT                0
851
852 /* Bit definitions for SMPS_SHORT_STATUS */
853 #define PALMAS_SMPS_SHORT_STATUS_SMPS10                         0x80
854 #define PALMAS_SMPS_SHORT_STATUS_SMPS10_SHIFT                   7
855 #define PALMAS_SMPS_SHORT_STATUS_SMPS9                          0x40
856 #define PALMAS_SMPS_SHORT_STATUS_SMPS9_SHIFT                    6
857 #define PALMAS_SMPS_SHORT_STATUS_SMPS8                          0x20
858 #define PALMAS_SMPS_SHORT_STATUS_SMPS8_SHIFT                    5
859 #define PALMAS_SMPS_SHORT_STATUS_SMPS7                          0x10
860 #define PALMAS_SMPS_SHORT_STATUS_SMPS7_SHIFT                    4
861 #define PALMAS_SMPS_SHORT_STATUS_SMPS6                          0x08
862 #define PALMAS_SMPS_SHORT_STATUS_SMPS6_SHIFT                    3
863 #define PALMAS_SMPS_SHORT_STATUS_SMPS45                         0x04
864 #define PALMAS_SMPS_SHORT_STATUS_SMPS45_SHIFT                   2
865 #define PALMAS_SMPS_SHORT_STATUS_SMPS3                          0x02
866 #define PALMAS_SMPS_SHORT_STATUS_SMPS3_SHIFT                    1
867 #define PALMAS_SMPS_SHORT_STATUS_SMPS12                         0x01
868 #define PALMAS_SMPS_SHORT_STATUS_SMPS12_SHIFT                   0
869
870 /* Bit definitions for SMPS_NEGATIVE_CURRENT_LIMIT_EN */
871 #define PALMAS_SMPS_NEGATIVE_CURRENT_LIMIT_EN_SMPS9             0x40
872 #define PALMAS_SMPS_NEGATIVE_CURRENT_LIMIT_EN_SMPS9_SHIFT       6
873 #define PALMAS_SMPS_NEGATIVE_CURRENT_LIMIT_EN_SMPS8             0x20
874 #define PALMAS_SMPS_NEGATIVE_CURRENT_LIMIT_EN_SMPS8_SHIFT       5
875 #define PALMAS_SMPS_NEGATIVE_CURRENT_LIMIT_EN_SMPS7             0x10
876 #define PALMAS_SMPS_NEGATIVE_CURRENT_LIMIT_EN_SMPS7_SHIFT       4
877 #define PALMAS_SMPS_NEGATIVE_CURRENT_LIMIT_EN_SMPS6             0x08
878 #define PALMAS_SMPS_NEGATIVE_CURRENT_LIMIT_EN_SMPS6_SHIFT       3
879 #define PALMAS_SMPS_NEGATIVE_CURRENT_LIMIT_EN_SMPS45            0x04
880 #define PALMAS_SMPS_NEGATIVE_CURRENT_LIMIT_EN_SMPS45_SHIFT      2
881 #define PALMAS_SMPS_NEGATIVE_CURRENT_LIMIT_EN_SMPS3             0x02
882 #define PALMAS_SMPS_NEGATIVE_CURRENT_LIMIT_EN_SMPS3_SHIFT       1
883 #define PALMAS_SMPS_NEGATIVE_CURRENT_LIMIT_EN_SMPS12            0x01
884 #define PALMAS_SMPS_NEGATIVE_CURRENT_LIMIT_EN_SMPS12_SHIFT      0
885
886 /* Bit definitions for SMPS_POWERGOOD_MASK1 */
887 #define PALMAS_SMPS_POWERGOOD_MASK1_SMPS10                      0x80
888 #define PALMAS_SMPS_POWERGOOD_MASK1_SMPS10_SHIFT                7
889 #define PALMAS_SMPS_POWERGOOD_MASK1_SMPS9                       0x40
890 #define PALMAS_SMPS_POWERGOOD_MASK1_SMPS9_SHIFT                 6
891 #define PALMAS_SMPS_POWERGOOD_MASK1_SMPS8                       0x20
892 #define PALMAS_SMPS_POWERGOOD_MASK1_SMPS8_SHIFT                 5
893 #define PALMAS_SMPS_POWERGOOD_MASK1_SMPS7                       0x10
894 #define PALMAS_SMPS_POWERGOOD_MASK1_SMPS7_SHIFT                 4
895 #define PALMAS_SMPS_POWERGOOD_MASK1_SMPS6                       0x08
896 #define PALMAS_SMPS_POWERGOOD_MASK1_SMPS6_SHIFT                 3
897 #define PALMAS_SMPS_POWERGOOD_MASK1_SMPS45                      0x04
898 #define PALMAS_SMPS_POWERGOOD_MASK1_SMPS45_SHIFT                2
899 #define PALMAS_SMPS_POWERGOOD_MASK1_SMPS3                       0x02
900 #define PALMAS_SMPS_POWERGOOD_MASK1_SMPS3_SHIFT                 1
901 #define PALMAS_SMPS_POWERGOOD_MASK1_SMPS12                      0x01
902 #define PALMAS_SMPS_POWERGOOD_MASK1_SMPS12_SHIFT                0
903
904 /* Bit definitions for SMPS_POWERGOOD_MASK2 */
905 #define PALMAS_SMPS_POWERGOOD_MASK2_POWERGOOD_TYPE_SELECT       0x80
906 #define PALMAS_SMPS_POWERGOOD_MASK2_POWERGOOD_TYPE_SELECT_SHIFT 7
907 #define PALMAS_SMPS_POWERGOOD_MASK2_GPIO_7                      0x04
908 #define PALMAS_SMPS_POWERGOOD_MASK2_GPIO_7_SHIFT                2
909 #define PALMAS_SMPS_POWERGOOD_MASK2_VBUS                        0x02
910 #define PALMAS_SMPS_POWERGOOD_MASK2_VBUS_SHIFT                  1
911 #define PALMAS_SMPS_POWERGOOD_MASK2_ACOK                        0x01
912 #define PALMAS_SMPS_POWERGOOD_MASK2_ACOK_SHIFT                  0
913
914 /* Registers for function LDO */
915 #define PALMAS_LDO1_CTRL                                        0x0
916 #define PALMAS_LDO1_VOLTAGE                                     0x1
917 #define PALMAS_LDO2_CTRL                                        0x2
918 #define PALMAS_LDO2_VOLTAGE                                     0x3
919 #define PALMAS_LDO3_CTRL                                        0x4
920 #define PALMAS_LDO3_VOLTAGE                                     0x5
921 #define PALMAS_LDO4_CTRL                                        0x6
922 #define PALMAS_LDO4_VOLTAGE                                     0x7
923 #define PALMAS_LDO5_CTRL                                        0x8
924 #define PALMAS_LDO5_VOLTAGE                                     0x9
925 #define PALMAS_LDO6_CTRL                                        0xA
926 #define PALMAS_LDO6_VOLTAGE                                     0xB
927 #define PALMAS_LDO7_CTRL                                        0xC
928 #define PALMAS_LDO7_VOLTAGE                                     0xD
929 #define PALMAS_LDO8_CTRL                                        0xE
930 #define PALMAS_LDO8_VOLTAGE                                     0xF
931 #define PALMAS_LDO9_CTRL                                        0x10
932 #define PALMAS_LDO9_VOLTAGE                                     0x11
933 #define PALMAS_LDOLN_CTRL                                       0x12
934 #define PALMAS_LDOLN_VOLTAGE                                    0x13
935 #define PALMAS_LDOUSB_CTRL                                      0x14
936 #define PALMAS_LDOUSB_VOLTAGE                                   0x15
937 #define PALMAS_LDO_CTRL                                         0x1A
938 #define PALMAS_LDO_PD_CTRL1                                     0x1B
939 #define PALMAS_LDO_PD_CTRL2                                     0x1C
940 #define PALMAS_LDO_SHORT_STATUS1                                0x1D
941 #define PALMAS_LDO_SHORT_STATUS2                                0x1E
942
943 /* Bit definitions for LDO1_CTRL */
944 #define PALMAS_LDO1_CTRL_WR_S                                   0x80
945 #define PALMAS_LDO1_CTRL_WR_S_SHIFT                             7
946 #define PALMAS_LDO1_CTRL_STATUS                                 0x10
947 #define PALMAS_LDO1_CTRL_STATUS_SHIFT                           4
948 #define PALMAS_LDO1_CTRL_MODE_SLEEP                             0x04
949 #define PALMAS_LDO1_CTRL_MODE_SLEEP_SHIFT                       2
950 #define PALMAS_LDO1_CTRL_MODE_ACTIVE                            0x01
951 #define PALMAS_LDO1_CTRL_MODE_ACTIVE_SHIFT                      0
952
953 /* Bit definitions for LDO1_VOLTAGE */
954 #define PALMAS_LDO1_VOLTAGE_VSEL_MASK                           0x3f
955 #define PALMAS_LDO1_VOLTAGE_VSEL_SHIFT                          0
956
957 /* Bit definitions for LDO2_CTRL */
958 #define PALMAS_LDO2_CTRL_WR_S                                   0x80
959 #define PALMAS_LDO2_CTRL_WR_S_SHIFT                             7
960 #define PALMAS_LDO2_CTRL_STATUS                                 0x10
961 #define PALMAS_LDO2_CTRL_STATUS_SHIFT                           4
962 #define PALMAS_LDO2_CTRL_MODE_SLEEP                             0x04
963 #define PALMAS_LDO2_CTRL_MODE_SLEEP_SHIFT                       2
964 #define PALMAS_LDO2_CTRL_MODE_ACTIVE                            0x01
965 #define PALMAS_LDO2_CTRL_MODE_ACTIVE_SHIFT                      0
966
967 /* Bit definitions for LDO2_VOLTAGE */
968 #define PALMAS_LDO2_VOLTAGE_VSEL_MASK                           0x3f
969 #define PALMAS_LDO2_VOLTAGE_VSEL_SHIFT                          0
970
971 /* Bit definitions for LDO3_CTRL */
972 #define PALMAS_LDO3_CTRL_WR_S                                   0x80
973 #define PALMAS_LDO3_CTRL_WR_S_SHIFT                             7
974 #define PALMAS_LDO3_CTRL_STATUS                                 0x10
975 #define PALMAS_LDO3_CTRL_STATUS_SHIFT                           4
976 #define PALMAS_LDO3_CTRL_MODE_SLEEP                             0x04
977 #define PALMAS_LDO3_CTRL_MODE_SLEEP_SHIFT                       2
978 #define PALMAS_LDO3_CTRL_MODE_ACTIVE                            0x01
979 #define PALMAS_LDO3_CTRL_MODE_ACTIVE_SHIFT                      0
980
981 /* Bit definitions for LDO3_VOLTAGE */
982 #define PALMAS_LDO3_VOLTAGE_VSEL_MASK                           0x3f
983 #define PALMAS_LDO3_VOLTAGE_VSEL_SHIFT                          0
984
985 /* Bit definitions for LDO4_CTRL */
986 #define PALMAS_LDO4_CTRL_WR_S                                   0x80
987 #define PALMAS_LDO4_CTRL_WR_S_SHIFT                             7
988 #define PALMAS_LDO4_CTRL_STATUS                                 0x10
989 #define PALMAS_LDO4_CTRL_STATUS_SHIFT                           4
990 #define PALMAS_LDO4_CTRL_MODE_SLEEP                             0x04
991 #define PALMAS_LDO4_CTRL_MODE_SLEEP_SHIFT                       2
992 #define PALMAS_LDO4_CTRL_MODE_ACTIVE                            0x01
993 #define PALMAS_LDO4_CTRL_MODE_ACTIVE_SHIFT                      0
994
995 /* Bit definitions for LDO4_VOLTAGE */
996 #define PALMAS_LDO4_VOLTAGE_VSEL_MASK                           0x3f
997 #define PALMAS_LDO4_VOLTAGE_VSEL_SHIFT                          0
998
999 /* Bit definitions for LDO5_CTRL */
1000 #define PALMAS_LDO5_CTRL_WR_S                                   0x80
1001 #define PALMAS_LDO5_CTRL_WR_S_SHIFT                             7
1002 #define PALMAS_LDO5_CTRL_STATUS                                 0x10
1003 #define PALMAS_LDO5_CTRL_STATUS_SHIFT                           4
1004 #define PALMAS_LDO5_CTRL_MODE_SLEEP                             0x04
1005 #define PALMAS_LDO5_CTRL_MODE_SLEEP_SHIFT                       2
1006 #define PALMAS_LDO5_CTRL_MODE_ACTIVE                            0x01
1007 #define PALMAS_LDO5_CTRL_MODE_ACTIVE_SHIFT                      0
1008
1009 /* Bit definitions for LDO5_VOLTAGE */
1010 #define PALMAS_LDO5_VOLTAGE_VSEL_MASK                           0x3f
1011 #define PALMAS_LDO5_VOLTAGE_VSEL_SHIFT                          0
1012
1013 /* Bit definitions for LDO6_CTRL */
1014 #define PALMAS_LDO6_CTRL_WR_S                                   0x80
1015 #define PALMAS_LDO6_CTRL_WR_S_SHIFT                             7
1016 #define PALMAS_LDO6_CTRL_LDO_VIB_EN                             0x40
1017 #define PALMAS_LDO6_CTRL_LDO_VIB_EN_SHIFT                       6
1018 #define PALMAS_LDO6_CTRL_STATUS                                 0x10
1019 #define PALMAS_LDO6_CTRL_STATUS_SHIFT                           4
1020 #define PALMAS_LDO6_CTRL_MODE_SLEEP                             0x04
1021 #define PALMAS_LDO6_CTRL_MODE_SLEEP_SHIFT                       2
1022 #define PALMAS_LDO6_CTRL_MODE_ACTIVE                            0x01
1023 #define PALMAS_LDO6_CTRL_MODE_ACTIVE_SHIFT                      0
1024
1025 /* Bit definitions for LDO6_VOLTAGE */
1026 #define PALMAS_LDO6_VOLTAGE_VSEL_MASK                           0x3f
1027 #define PALMAS_LDO6_VOLTAGE_VSEL_SHIFT                          0
1028
1029 /* Bit definitions for LDO7_CTRL */
1030 #define PALMAS_LDO7_CTRL_WR_S                                   0x80
1031 #define PALMAS_LDO7_CTRL_WR_S_SHIFT                             7
1032 #define PALMAS_LDO7_CTRL_STATUS                                 0x10
1033 #define PALMAS_LDO7_CTRL_STATUS_SHIFT                           4
1034 #define PALMAS_LDO7_CTRL_MODE_SLEEP                             0x04
1035 #define PALMAS_LDO7_CTRL_MODE_SLEEP_SHIFT                       2
1036 #define PALMAS_LDO7_CTRL_MODE_ACTIVE                            0x01
1037 #define PALMAS_LDO7_CTRL_MODE_ACTIVE_SHIFT                      0
1038
1039 /* Bit definitions for LDO7_VOLTAGE */
1040 #define PALMAS_LDO7_VOLTAGE_VSEL_MASK                           0x3f
1041 #define PALMAS_LDO7_VOLTAGE_VSEL_SHIFT                          0
1042
1043 /* Bit definitions for LDO8_CTRL */
1044 #define PALMAS_LDO8_CTRL_WR_S                                   0x80
1045 #define PALMAS_LDO8_CTRL_WR_S_SHIFT                             7
1046 #define PALMAS_LDO8_CTRL_LDO_TRACKING_EN                        0x40
1047 #define PALMAS_LDO8_CTRL_LDO_TRACKING_EN_SHIFT                  6
1048 #define PALMAS_LDO8_CTRL_STATUS                                 0x10
1049 #define PALMAS_LDO8_CTRL_STATUS_SHIFT                           4
1050 #define PALMAS_LDO8_CTRL_MODE_SLEEP                             0x04
1051 #define PALMAS_LDO8_CTRL_MODE_SLEEP_SHIFT                       2
1052 #define PALMAS_LDO8_CTRL_MODE_ACTIVE                            0x01
1053 #define PALMAS_LDO8_CTRL_MODE_ACTIVE_SHIFT                      0
1054
1055 /* Bit definitions for LDO8_VOLTAGE */
1056 #define PALMAS_LDO8_VOLTAGE_VSEL_MASK                           0x3f
1057 #define PALMAS_LDO8_VOLTAGE_VSEL_SHIFT                          0
1058
1059 /* Bit definitions for LDO9_CTRL */
1060 #define PALMAS_LDO9_CTRL_WR_S                                   0x80
1061 #define PALMAS_LDO9_CTRL_WR_S_SHIFT                             7
1062 #define PALMAS_LDO9_CTRL_LDO_BYPASS_EN                          0x40
1063 #define PALMAS_LDO9_CTRL_LDO_BYPASS_EN_SHIFT                    6
1064 #define PALMAS_LDO9_CTRL_STATUS                                 0x10
1065 #define PALMAS_LDO9_CTRL_STATUS_SHIFT                           4
1066 #define PALMAS_LDO9_CTRL_MODE_SLEEP                             0x04
1067 #define PALMAS_LDO9_CTRL_MODE_SLEEP_SHIFT                       2
1068 #define PALMAS_LDO9_CTRL_MODE_ACTIVE                            0x01
1069 #define PALMAS_LDO9_CTRL_MODE_ACTIVE_SHIFT                      0
1070
1071 /* Bit definitions for LDO9_VOLTAGE */
1072 #define PALMAS_LDO9_VOLTAGE_VSEL_MASK                           0x3f
1073 #define PALMAS_LDO9_VOLTAGE_VSEL_SHIFT                          0
1074
1075 /* Bit definitions for LDOLN_CTRL */
1076 #define PALMAS_LDOLN_CTRL_WR_S                                  0x80
1077 #define PALMAS_LDOLN_CTRL_WR_S_SHIFT                            7
1078 #define PALMAS_LDOLN_CTRL_STATUS                                0x10
1079 #define PALMAS_LDOLN_CTRL_STATUS_SHIFT                          4
1080 #define PALMAS_LDOLN_CTRL_MODE_SLEEP                            0x04
1081 #define PALMAS_LDOLN_CTRL_MODE_SLEEP_SHIFT                      2
1082 #define PALMAS_LDOLN_CTRL_MODE_ACTIVE                           0x01
1083 #define PALMAS_LDOLN_CTRL_MODE_ACTIVE_SHIFT                     0
1084
1085 /* Bit definitions for LDOLN_VOLTAGE */
1086 #define PALMAS_LDOLN_VOLTAGE_VSEL_MASK                          0x3f
1087 #define PALMAS_LDOLN_VOLTAGE_VSEL_SHIFT                         0
1088
1089 /* Bit definitions for LDOUSB_CTRL */
1090 #define PALMAS_LDOUSB_CTRL_WR_S                                 0x80
1091 #define PALMAS_LDOUSB_CTRL_WR_S_SHIFT                           7
1092 #define PALMAS_LDOUSB_CTRL_STATUS                               0x10
1093 #define PALMAS_LDOUSB_CTRL_STATUS_SHIFT                         4
1094 #define PALMAS_LDOUSB_CTRL_MODE_SLEEP                           0x04
1095 #define PALMAS_LDOUSB_CTRL_MODE_SLEEP_SHIFT                     2
1096 #define PALMAS_LDOUSB_CTRL_MODE_ACTIVE                          0x01
1097 #define PALMAS_LDOUSB_CTRL_MODE_ACTIVE_SHIFT                    0
1098
1099 /* Bit definitions for LDOUSB_VOLTAGE */
1100 #define PALMAS_LDOUSB_VOLTAGE_VSEL_MASK                         0x3f
1101 #define PALMAS_LDOUSB_VOLTAGE_VSEL_SHIFT                        0
1102
1103 /* Bit definitions for LDO_CTRL */
1104 #define PALMAS_LDO_CTRL_LDOUSB_ON_VBUS_VSYS                     0x01
1105 #define PALMAS_LDO_CTRL_LDOUSB_ON_VBUS_VSYS_SHIFT               0
1106
1107 /* Bit definitions for LDO_PD_CTRL1 */
1108 #define PALMAS_LDO_PD_CTRL1_LDO8                                0x80
1109 #define PALMAS_LDO_PD_CTRL1_LDO8_SHIFT                          7
1110 #define PALMAS_LDO_PD_CTRL1_LDO7                                0x40
1111 #define PALMAS_LDO_PD_CTRL1_LDO7_SHIFT                          6
1112 #define PALMAS_LDO_PD_CTRL1_LDO6                                0x20
1113 #define PALMAS_LDO_PD_CTRL1_LDO6_SHIFT                          5
1114 #define PALMAS_LDO_PD_CTRL1_LDO5                                0x10
1115 #define PALMAS_LDO_PD_CTRL1_LDO5_SHIFT                          4
1116 #define PALMAS_LDO_PD_CTRL1_LDO4                                0x08
1117 #define PALMAS_LDO_PD_CTRL1_LDO4_SHIFT                          3
1118 #define PALMAS_LDO_PD_CTRL1_LDO3                                0x04
1119 #define PALMAS_LDO_PD_CTRL1_LDO3_SHIFT                          2
1120 #define PALMAS_LDO_PD_CTRL1_LDO2                                0x02
1121 #define PALMAS_LDO_PD_CTRL1_LDO2_SHIFT                          1
1122 #define PALMAS_LDO_PD_CTRL1_LDO1                                0x01
1123 #define PALMAS_LDO_PD_CTRL1_LDO1_SHIFT                          0
1124
1125 /* Bit definitions for LDO_PD_CTRL2 */
1126 #define PALMAS_LDO_PD_CTRL2_LDOUSB                              0x04
1127 #define PALMAS_LDO_PD_CTRL2_LDOUSB_SHIFT                        2
1128 #define PALMAS_LDO_PD_CTRL2_LDOLN                               0x02
1129 #define PALMAS_LDO_PD_CTRL2_LDOLN_SHIFT                         1
1130 #define PALMAS_LDO_PD_CTRL2_LDO9                                0x01
1131 #define PALMAS_LDO_PD_CTRL2_LDO9_SHIFT                          0
1132
1133 /* Bit definitions for LDO_SHORT_STATUS1 */
1134 #define PALMAS_LDO_SHORT_STATUS1_LDO8                           0x80
1135 #define PALMAS_LDO_SHORT_STATUS1_LDO8_SHIFT                     7
1136 #define PALMAS_LDO_SHORT_STATUS1_LDO7                           0x40
1137 #define PALMAS_LDO_SHORT_STATUS1_LDO7_SHIFT                     6
1138 #define PALMAS_LDO_SHORT_STATUS1_LDO6                           0x20
1139 #define PALMAS_LDO_SHORT_STATUS1_LDO6_SHIFT                     5
1140 #define PALMAS_LDO_SHORT_STATUS1_LDO5                           0x10
1141 #define PALMAS_LDO_SHORT_STATUS1_LDO5_SHIFT                     4
1142 #define PALMAS_LDO_SHORT_STATUS1_LDO4                           0x08
1143 #define PALMAS_LDO_SHORT_STATUS1_LDO4_SHIFT                     3
1144 #define PALMAS_LDO_SHORT_STATUS1_LDO3                           0x04
1145 #define PALMAS_LDO_SHORT_STATUS1_LDO3_SHIFT                     2
1146 #define PALMAS_LDO_SHORT_STATUS1_LDO2                           0x02
1147 #define PALMAS_LDO_SHORT_STATUS1_LDO2_SHIFT                     1
1148 #define PALMAS_LDO_SHORT_STATUS1_LDO1                           0x01
1149 #define PALMAS_LDO_SHORT_STATUS1_LDO1_SHIFT                     0
1150
1151 /* Bit definitions for LDO_SHORT_STATUS2 */
1152 #define PALMAS_LDO_SHORT_STATUS2_LDOVANA                        0x08
1153 #define PALMAS_LDO_SHORT_STATUS2_LDOVANA_SHIFT                  3
1154 #define PALMAS_LDO_SHORT_STATUS2_LDOUSB                         0x04
1155 #define PALMAS_LDO_SHORT_STATUS2_LDOUSB_SHIFT                   2
1156 #define PALMAS_LDO_SHORT_STATUS2_LDOLN                          0x02
1157 #define PALMAS_LDO_SHORT_STATUS2_LDOLN_SHIFT                    1
1158 #define PALMAS_LDO_SHORT_STATUS2_LDO9                           0x01
1159 #define PALMAS_LDO_SHORT_STATUS2_LDO9_SHIFT                     0
1160
1161 /* Registers for function DVFS Func */
1162 #define PALMAS_SMPS_DVFS1_CTRL                                  0x0
1163 #define PALMAS_SMPS_DVFS1_ENABLE_SHIFT                          0
1164 #define PALMAS_SMPS_DVFS1_OFFSET_STEP_SHIFT                     1
1165 #define PALMAS_SMPS_DVFS1_ENABLE_RST_SHIFT                      2
1166 #define PALMAS_SMPS_DVFS1_RESTORE_VALUE_SHIFT                   3
1167 #define PALMAS_SMPS_DVFS1_VOLTAGE_MAX                           0x1
1168 #define PALMAS_SMPS_DVFS1_STATUS                                0x2
1169
1170 #define DVFS_BASE_VOLTAGE_UV                                    500000
1171 #define DVFS_MAX_VOLTAGE_UV                                     1650000
1172 #define DVFS_VOLTAGE_STEP_UV                                    10000
1173
1174 /* Registers for function PMU_CONTROL */
1175 #define PALMAS_DEV_CTRL                                         0x0
1176 #define PALMAS_POWER_CTRL                                       0x1
1177 #define PALMAS_VSYS_LO                                          0x2
1178 #define PALMAS_VSYS_MON                                         0x3
1179 #define PALMAS_VBAT_MON                                         0x4
1180 #define PALMAS_WATCHDOG                                         0x5
1181 #define PALMAS_BOOT_STATUS                                      0x6
1182 #define PALMAS_BATTERY_BOUNCE                                   0x7
1183 #define PALMAS_BACKUP_BATTERY_CTRL                              0x8
1184 #define PALMAS_LONG_PRESS_KEY                                   0x9
1185 #define PALMAS_OSC_THERM_CTRL                                   0xA
1186 #define PALMAS_BATDEBOUNCING                                    0xB
1187 #define PALMAS_SWOFF_HWRST                                      0xF
1188 #define PALMAS_SWOFF_COLDRST                                    0x10
1189 #define PALMAS_SWOFF_STATUS                                     0x11
1190 #define PALMAS_PMU_CONFIG                                       0x12
1191 #define PALMAS_SPARE                                            0x14
1192 #define PALMAS_PMU_SECONDARY_INT                                0x15
1193 #define PALMAS_SW_REVISION                                      0x17
1194 #define PALMAS_EXT_CHRG_CTRL                                    0x18
1195 #define PALMAS_PMU_SECONDARY_INT2                               0x19
1196
1197 /* Bit definitions for DEV_CTRL */
1198 #define PALMAS_DEV_CTRL_DEV_STATUS_MASK                         0x0c
1199 #define PALMAS_DEV_CTRL_DEV_STATUS_SHIFT                        2
1200 #define PALMAS_DEV_CTRL_SW_RST                                  0x02
1201 #define PALMAS_DEV_CTRL_SW_RST_SHIFT                            1
1202 #define PALMAS_DEV_CTRL_DEV_ON                                  0x01
1203 #define PALMAS_DEV_CTRL_DEV_ON_SHIFT                            0
1204
1205 /* Bit definitions for POWER_CTRL */
1206 #define PALMAS_POWER_CTRL_ENABLE2_MASK                          0x04
1207 #define PALMAS_POWER_CTRL_ENABLE2_MASK_SHIFT                    2
1208 #define PALMAS_POWER_CTRL_ENABLE1_MASK                          0x02
1209 #define PALMAS_POWER_CTRL_ENABLE1_MASK_SHIFT                    1
1210 #define PALMAS_POWER_CTRL_NSLEEP_MASK                           0x01
1211 #define PALMAS_POWER_CTRL_NSLEEP_MASK_SHIFT                     0
1212
1213 /* Bit definitions for VSYS_LO */
1214 #define PALMAS_VSYS_LO_THRESHOLD_MASK                           0x1f
1215 #define PALMAS_VSYS_LO_THRESHOLD_SHIFT                          0
1216
1217 /* Bit definitions for VSYS_MON */
1218 #define PALMAS_VSYS_MON_ENABLE                                  0x80
1219 #define PALMAS_VSYS_MON_ENABLE_SHIFT                            7
1220 #define PALMAS_VSYS_MON_THRESHOLD_MASK                          0x3f
1221 #define PALMAS_VSYS_MON_THRESHOLD_SHIFT                         0
1222
1223 /* Bit definitions for VBAT_MON */
1224 #define PALMAS_VBAT_MON_ENABLE                                  0x80
1225 #define PALMAS_VBAT_MON_ENABLE_SHIFT                            7
1226 #define PALMAS_VBAT_MON_THRESHOLD_MASK                          0x3f
1227 #define PALMAS_VBAT_MON_THRESHOLD_SHIFT                         0
1228
1229 /* Bit definitions for WATCHDOG */
1230 #define PALMAS_WATCHDOG_LOCK                                    0x20
1231 #define PALMAS_WATCHDOG_LOCK_SHIFT                              5
1232 #define PALMAS_WATCHDOG_ENABLE                                  0x10
1233 #define PALMAS_WATCHDOG_ENABLE_SHIFT                            4
1234 #define PALMAS_WATCHDOG_MODE                                    0x08
1235 #define PALMAS_WATCHDOG_MODE_SHIFT                              3
1236 #define PALMAS_WATCHDOG_TIMER_MASK                              0x07
1237 #define PALMAS_WATCHDOG_TIMER_SHIFT                             0
1238
1239 /* Bit definitions for BOOT_STATUS */
1240 #define PALMAS_BOOT_STATUS_BOOT1                                0x02
1241 #define PALMAS_BOOT_STATUS_BOOT1_SHIFT                          1
1242 #define PALMAS_BOOT_STATUS_BOOT0                                0x01
1243 #define PALMAS_BOOT_STATUS_BOOT0_SHIFT                          0
1244
1245 /* Bit definitions for BATTERY_BOUNCE */
1246 #define PALMAS_BATTERY_BOUNCE_BB_DELAY_MASK                     0x3f
1247 #define PALMAS_BATTERY_BOUNCE_BB_DELAY_SHIFT                    0
1248
1249 /* Bit definitions for BACKUP_BATTERY_CTRL */
1250 #define PALMAS_BACKUP_BATTERY_CTRL_VRTC_18_15                   0x80
1251 #define PALMAS_BACKUP_BATTERY_CTRL_VRTC_18_15_SHIFT             7
1252 #define PALMAS_BACKUP_BATTERY_CTRL_VRTC_EN_SLP                  0x40
1253 #define PALMAS_BACKUP_BATTERY_CTRL_VRTC_EN_SLP_SHIFT            6
1254 #define PALMAS_BACKUP_BATTERY_CTRL_VRTC_EN_OFF                  0x20
1255 #define PALMAS_BACKUP_BATTERY_CTRL_VRTC_EN_OFF_SHIFT            5
1256 #define PALMAS_BACKUP_BATTERY_CTRL_VRTC_PWEN                    0x10
1257 #define PALMAS_BACKUP_BATTERY_CTRL_VRTC_PWEN_SHIFT              4
1258 #define PALMAS_BACKUP_BATTERY_CTRL_BBS_BBC_LOW_ICHRG            0x08
1259 #define PALMAS_BACKUP_BATTERY_CTRL_BBS_BBC_LOW_ICHRG_SHIFT      3
1260 #define PALMAS_BACKUP_BATTERY_CTRL_BB_SEL_MASK                  0x06
1261 #define PALMAS_BACKUP_BATTERY_CTRL_BB_SEL_SHIFT                 1
1262 #define PALMAS_BACKUP_BATTERY_CTRL_BB_CHG_EN                    0x01
1263 #define PALMAS_BACKUP_BATTERY_CTRL_BB_CHG_EN_SHIFT              0
1264
1265 /* Bit definitions for LONG_PRESS_KEY */
1266 #define PALMAS_LONG_PRESS_KEY_LPK_LOCK                          0x80
1267 #define PALMAS_LONG_PRESS_KEY_LPK_LOCK_SHIFT                    7
1268 #define PALMAS_LONG_PRESS_KEY_LPK_INT_CLR                       0x10
1269 #define PALMAS_LONG_PRESS_KEY_LPK_INT_CLR_SHIFT                 4
1270 #define PALMAS_LONG_PRESS_KEY_LPK_TIME_MASK                     0x0c
1271 #define PALMAS_LONG_PRESS_KEY_LPK_TIME_SHIFT                    2
1272 #define PALMAS_LONG_PRESS_KEY_PWRON_DEBOUNCE_MASK               0x03
1273 #define PALMAS_LONG_PRESS_KEY_PWRON_DEBOUNCE_SHIFT              0
1274
1275 /* Register bit values for various Long_Press_key durations */
1276 #define PALMAS_LONG_PRESS_KEY_TIME_DEFAULT      -1
1277 #define PALMAS_LONG_PRESS_KEY_TIME_6SECONDS     0
1278 #define PALMAS_LONG_PRESS_KEY_TIME_8SECONDS     1
1279 #define PALMAS_LONG_PRESS_KEY_TIME_10SECONDS    2
1280 #define PALMAS_LONG_PRESS_KEY_TIME_12SECONDS    3
1281
1282 /* Bit definitions for OSC_THERM_CTRL */
1283 #define PALMAS_OSC_THERM_CTRL_VANA_ON_IN_SLEEP                  0x80
1284 #define PALMAS_OSC_THERM_CTRL_VANA_ON_IN_SLEEP_SHIFT            7
1285 #define PALMAS_OSC_THERM_CTRL_INT_MASK_IN_SLEEP                 0x40
1286 #define PALMAS_OSC_THERM_CTRL_INT_MASK_IN_SLEEP_SHIFT           6
1287 #define PALMAS_OSC_THERM_CTRL_RC15MHZ_ON_IN_SLEEP               0x20
1288 #define PALMAS_OSC_THERM_CTRL_RC15MHZ_ON_IN_SLEEP_SHIFT         5
1289 #define PALMAS_OSC_THERM_CTRL_THERM_OFF_IN_SLEEP                0x10
1290 #define PALMAS_OSC_THERM_CTRL_THERM_OFF_IN_SLEEP_SHIFT          4
1291 #define PALMAS_OSC_THERM_CTRL_THERM_HD_SEL_MASK                 0x0c
1292 #define PALMAS_OSC_THERM_CTRL_THERM_HD_SEL_SHIFT                2
1293 #define PALMAS_OSC_THERM_CTRL_OSC_BYPASS                        0x02
1294 #define PALMAS_OSC_THERM_CTRL_OSC_BYPASS_SHIFT                  1
1295 #define PALMAS_OSC_THERM_CTRL_OSC_HPMODE                        0x01
1296 #define PALMAS_OSC_THERM_CTRL_OSC_HPMODE_SHIFT                  0
1297
1298 /* Bit definitions for BATDEBOUNCING */
1299 #define PALMAS_BATDEBOUNCING_BAT_DEB_BYPASS                     0x80
1300 #define PALMAS_BATDEBOUNCING_BAT_DEB_BYPASS_SHIFT               7
1301 #define PALMAS_BATDEBOUNCING_BINS_DEB_MASK                      0x78
1302 #define PALMAS_BATDEBOUNCING_BINS_DEB_SHIFT                     3
1303 #define PALMAS_BATDEBOUNCING_BEXT_DEB_MASK                      0x07
1304 #define PALMAS_BATDEBOUNCING_BEXT_DEB_SHIFT                     0
1305
1306 /* Bit definitions for SWOFF_HWRST */
1307 #define PALMAS_SWOFF_HWRST_PWRON_LPK                            0x80
1308 #define PALMAS_SWOFF_HWRST_PWRON_LPK_SHIFT                      7
1309 #define PALMAS_SWOFF_HWRST_PWRDOWN                              0x40
1310 #define PALMAS_SWOFF_HWRST_PWRDOWN_SHIFT                        6
1311 #define PALMAS_SWOFF_HWRST_WTD                                  0x20
1312 #define PALMAS_SWOFF_HWRST_WTD_SHIFT                            5
1313 #define PALMAS_SWOFF_HWRST_TSHUT                                0x10
1314 #define PALMAS_SWOFF_HWRST_TSHUT_SHIFT                          4
1315 #define PALMAS_SWOFF_HWRST_RESET_IN                             0x08
1316 #define PALMAS_SWOFF_HWRST_RESET_IN_SHIFT                       3
1317 #define PALMAS_SWOFF_HWRST_SW_RST                               0x04
1318 #define PALMAS_SWOFF_HWRST_SW_RST_SHIFT                         2
1319 #define PALMAS_SWOFF_HWRST_VSYS_LO                              0x02
1320 #define PALMAS_SWOFF_HWRST_VSYS_LO_SHIFT                        1
1321 #define PALMAS_SWOFF_HWRST_GPADC_SHUTDOWN                       0x01
1322 #define PALMAS_SWOFF_HWRST_GPADC_SHUTDOWN_SHIFT                 0
1323
1324 /* Register bit values for poweron_lpk */
1325 #define PALMAS_SWOFF_COLDRST_PWRON_LPK_DEFAULT          -1
1326 #define PALMAS_SWOFF_COLDRST_PWRON_LPK_SHUTDOWN 0
1327 #define PALMAS_SWOFF_COLDRST_PWRON_LPK_RESTART          1
1328
1329 /* Bit definitions for SWOFF_COLDRST */
1330 #define PALMAS_SWOFF_COLDRST_PWRON_LPK                          0x80
1331 #define PALMAS_SWOFF_COLDRST_PWRON_LPK_SHIFT                    7
1332 #define PALMAS_SWOFF_COLDRST_PWRDOWN                            0x40
1333 #define PALMAS_SWOFF_COLDRST_PWRDOWN_SHIFT                      6
1334 #define PALMAS_SWOFF_COLDRST_WTD                                0x20
1335 #define PALMAS_SWOFF_COLDRST_WTD_SHIFT                          5
1336 #define PALMAS_SWOFF_COLDRST_TSHUT                              0x10
1337 #define PALMAS_SWOFF_COLDRST_TSHUT_SHIFT                        4
1338 #define PALMAS_SWOFF_COLDRST_RESET_IN                           0x08
1339 #define PALMAS_SWOFF_COLDRST_RESET_IN_SHIFT                     3
1340 #define PALMAS_SWOFF_COLDRST_SW_RST                             0x04
1341 #define PALMAS_SWOFF_COLDRST_SW_RST_SHIFT                       2
1342 #define PALMAS_SWOFF_COLDRST_VSYS_LO                            0x02
1343 #define PALMAS_SWOFF_COLDRST_VSYS_LO_SHIFT                      1
1344 #define PALMAS_SWOFF_COLDRST_GPADC_SHUTDOWN                     0x01
1345 #define PALMAS_SWOFF_COLDRST_GPADC_SHUTDOWN_SHIFT               0
1346
1347 /* Bit definitions for SWOFF_STATUS */
1348 #define PALMAS_SWOFF_STATUS_PWRON_LPK                           0x80
1349 #define PALMAS_SWOFF_STATUS_PWRON_LPK_SHIFT                     7
1350 #define PALMAS_SWOFF_STATUS_PWRDOWN                             0x40
1351 #define PALMAS_SWOFF_STATUS_PWRDOWN_SHIFT                       6
1352 #define PALMAS_SWOFF_STATUS_WTD                                 0x20
1353 #define PALMAS_SWOFF_STATUS_WTD_SHIFT                           5
1354 #define PALMAS_SWOFF_STATUS_TSHUT                               0x10
1355 #define PALMAS_SWOFF_STATUS_TSHUT_SHIFT                         4
1356 #define PALMAS_SWOFF_STATUS_RESET_IN                            0x08
1357 #define PALMAS_SWOFF_STATUS_RESET_IN_SHIFT                      3
1358 #define PALMAS_SWOFF_STATUS_SW_RST                              0x04
1359 #define PALMAS_SWOFF_STATUS_SW_RST_SHIFT                        2
1360 #define PALMAS_SWOFF_STATUS_VSYS_LO                             0x02
1361 #define PALMAS_SWOFF_STATUS_VSYS_LO_SHIFT                       1
1362 #define PALMAS_SWOFF_STATUS_GPADC_SHUTDOWN                      0x01
1363 #define PALMAS_SWOFF_STATUS_GPADC_SHUTDOWN_SHIFT                0
1364
1365 /* Bit definitions for PMU_CONFIG */
1366 #define PALMAS_PMU_CONFIG_MULTI_CELL_EN                         0x40
1367 #define PALMAS_PMU_CONFIG_MULTI_CELL_EN_SHIFT                   6
1368 #define PALMAS_PMU_CONFIG_SPARE_MASK                            0x30
1369 #define PALMAS_PMU_CONFIG_SPARE_SHIFT                           4
1370 #define PALMAS_PMU_CONFIG_SWOFF_DLY_MASK                        0x0c
1371 #define PALMAS_PMU_CONFIG_SWOFF_DLY_SHIFT                       2
1372 #define PALMAS_PMU_CONFIG_GATE_RESET_OUT                        0x02
1373 #define PALMAS_PMU_CONFIG_GATE_RESET_OUT_SHIFT                  1
1374 #define PALMAS_PMU_CONFIG_AUTODEVON                             0x01
1375 #define PALMAS_PMU_CONFIG_AUTODEVON_SHIFT                       0
1376
1377 /* Bit definitions for SPARE */
1378 #define PALMAS_SPARE_SPARE_MASK                                 0xf8
1379 #define PALMAS_SPARE_SPARE_SHIFT                                3
1380 #define PALMAS_SPARE_REGEN3_OD                                  0x04
1381 #define PALMAS_SPARE_REGEN3_OD_SHIFT                            2
1382 #define PALMAS_SPARE_REGEN2_OD                                  0x02
1383 #define PALMAS_SPARE_REGEN2_OD_SHIFT                            1
1384 #define PALMAS_SPARE_REGEN1_OD                                  0x01
1385 #define PALMAS_SPARE_REGEN1_OD_SHIFT                            0
1386
1387 /* Bit definitions for PMU_SECONDARY_INT */
1388 #define PALMAS_PMU_SECONDARY_INT_VBUS_OVV_INT_SRC               0x80
1389 #define PALMAS_PMU_SECONDARY_INT_VBUS_OVV_INT_SRC_SHIFT         7
1390 #define PALMAS_PMU_SECONDARY_INT_CHARG_DET_N_INT_SRC            0x40
1391 #define PALMAS_PMU_SECONDARY_INT_CHARG_DET_N_INT_SRC_SHIFT      6
1392 #define PALMAS_PMU_SECONDARY_INT_BB_INT_SRC                     0x20
1393 #define PALMAS_PMU_SECONDARY_INT_BB_INT_SRC_SHIFT               5
1394 #define PALMAS_PMU_SECONDARY_INT_FBI_INT_SRC                    0x10
1395 #define PALMAS_PMU_SECONDARY_INT_FBI_INT_SRC_SHIFT              4
1396 #define PALMAS_PMU_SECONDARY_INT_VBUS_OVV_MASK                  0x08
1397 #define PALMAS_PMU_SECONDARY_INT_VBUS_OVV_MASK_SHIFT            3
1398 #define PALMAS_PMU_SECONDARY_INT_CHARG_DET_N_MASK               0x04
1399 #define PALMAS_PMU_SECONDARY_INT_CHARG_DET_N_MASK_SHIFT         2
1400 #define PALMAS_PMU_SECONDARY_INT_BB_MASK                        0x02
1401 #define PALMAS_PMU_SECONDARY_INT_BB_MASK_SHIFT                  1
1402 #define PALMAS_PMU_SECONDARY_INT_FBI_MASK                       0x01
1403 #define PALMAS_PMU_SECONDARY_INT_FBI_MASK_SHIFT                 0
1404
1405 /* Bit definitions for SW_REVISION */
1406 #define PALMAS_SW_REVISION_SW_REVISION_MASK                     0xff
1407 #define PALMAS_SW_REVISION_SW_REVISION_SHIFT                    0
1408
1409 /* Bit definitions for EXT_CHRG_CTRL */
1410 #define PALMAS_EXT_CHRG_CTRL_VBUS_OVV_STATUS                    0x80
1411 #define PALMAS_EXT_CHRG_CTRL_VBUS_OVV_STATUS_SHIFT              7
1412 #define PALMAS_EXT_CHRG_CTRL_CHARG_DET_N_STATUS                 0x40
1413 #define PALMAS_EXT_CHRG_CTRL_CHARG_DET_N_STATUS_SHIFT           6
1414 #define PALMAS_EXT_CHRG_CTRL_VSYS_DEBOUNCE_DELAY                0x08
1415 #define PALMAS_EXT_CHRG_CTRL_VSYS_DEBOUNCE_DELAY_SHIFT          3
1416 #define PALMAS_EXT_CHRG_CTRL_CHRG_DET_N                         0x04
1417 #define PALMAS_EXT_CHRG_CTRL_CHRG_DET_N_SHIFT                   2
1418 #define PALMAS_EXT_CHRG_CTRL_AUTO_ACA_EN                        0x02
1419 #define PALMAS_EXT_CHRG_CTRL_AUTO_ACA_EN_SHIFT                  1
1420 #define PALMAS_EXT_CHRG_CTRL_AUTO_LDOUSB_EN                     0x01
1421 #define PALMAS_EXT_CHRG_CTRL_AUTO_LDOUSB_EN_SHIFT               0
1422
1423 /* Bit definitions for PMU_SECONDARY_INT2 */
1424 #define PALMAS_PMU_SECONDARY_INT2_DVFS2_INT_SRC                 0x20
1425 #define PALMAS_PMU_SECONDARY_INT2_DVFS2_INT_SRC_SHIFT           5
1426 #define PALMAS_PMU_SECONDARY_INT2_DVFS1_INT_SRC                 0x10
1427 #define PALMAS_PMU_SECONDARY_INT2_DVFS1_INT_SRC_SHIFT           4
1428 #define PALMAS_PMU_SECONDARY_INT2_DVFS2_MASK                    0x02
1429 #define PALMAS_PMU_SECONDARY_INT2_DVFS2_MASK_SHIFT              1
1430 #define PALMAS_PMU_SECONDARY_INT2_DVFS1_MASK                    0x01
1431 #define PALMAS_PMU_SECONDARY_INT2_DVFS1_MASK_SHIFT              0
1432
1433 /* Registers for function RESOURCE */
1434 #define PALMAS_CLK32KG_CTRL                                     0x0
1435 #define PALMAS_CLK32KGAUDIO_CTRL                                0x1
1436 #define PALMAS_REGEN1_CTRL                                      0x2
1437 #define PALMAS_REGEN2_CTRL                                      0x3
1438 #define PALMAS_SYSEN1_CTRL                                      0x4
1439 #define PALMAS_SYSEN2_CTRL                                      0x5
1440 #define PALMAS_NSLEEP_RES_ASSIGN                                0x6
1441 #define PALMAS_NSLEEP_SMPS_ASSIGN                               0x7
1442 #define PALMAS_NSLEEP_LDO_ASSIGN1                               0x8
1443 #define PALMAS_NSLEEP_LDO_ASSIGN2                               0x9
1444 #define PALMAS_ENABLE1_RES_ASSIGN                               0xA
1445 #define PALMAS_ENABLE1_SMPS_ASSIGN                              0xB
1446 #define PALMAS_ENABLE1_LDO_ASSIGN1                              0xC
1447 #define PALMAS_ENABLE1_LDO_ASSIGN2                              0xD
1448 #define PALMAS_ENABLE2_RES_ASSIGN                               0xE
1449 #define PALMAS_ENABLE2_SMPS_ASSIGN                              0xF
1450 #define PALMAS_ENABLE2_LDO_ASSIGN1                              0x10
1451 #define PALMAS_ENABLE2_LDO_ASSIGN2                              0x11
1452 #define PALMAS_REGEN3_CTRL                                      0x12
1453
1454 /* Bit definitions for CLK32KG_CTRL */
1455 #define PALMAS_CLK32KG_CTRL_STATUS                              0x10
1456 #define PALMAS_CLK32KG_CTRL_STATUS_SHIFT                        4
1457 #define PALMAS_CLK32KG_CTRL_MODE_SLEEP                          0x04
1458 #define PALMAS_CLK32KG_CTRL_MODE_SLEEP_SHIFT                    2
1459 #define PALMAS_CLK32KG_CTRL_MODE_ACTIVE                         0x01
1460 #define PALMAS_CLK32KG_CTRL_MODE_ACTIVE_SHIFT                   0
1461
1462 /* Bit definitions for CLK32KGAUDIO_CTRL */
1463 #define PALMAS_CLK32KGAUDIO_CTRL_STATUS                         0x10
1464 #define PALMAS_CLK32KGAUDIO_CTRL_STATUS_SHIFT                   4
1465 #define PALMAS_CLK32KGAUDIO_CTRL_RESERVED3                      0x08
1466 #define PALMAS_CLK32KGAUDIO_CTRL_RESERVED3_SHIFT                3
1467 #define PALMAS_CLK32KGAUDIO_CTRL_MODE_SLEEP                     0x04
1468 #define PALMAS_CLK32KGAUDIO_CTRL_MODE_SLEEP_SHIFT               2
1469 #define PALMAS_CLK32KGAUDIO_CTRL_MODE_ACTIVE                    0x01
1470 #define PALMAS_CLK32KGAUDIO_CTRL_MODE_ACTIVE_SHIFT              0
1471
1472 /* Bit definitions for REGEN1_CTRL */
1473 #define PALMAS_REGEN1_CTRL_STATUS                               0x10
1474 #define PALMAS_REGEN1_CTRL_STATUS_SHIFT                         4
1475 #define PALMAS_REGEN1_CTRL_MODE_SLEEP                           0x04
1476 #define PALMAS_REGEN1_CTRL_MODE_SLEEP_SHIFT                     2
1477 #define PALMAS_REGEN1_CTRL_MODE_ACTIVE                          0x01
1478 #define PALMAS_REGEN1_CTRL_MODE_ACTIVE_SHIFT                    0
1479
1480 /* Bit definitions for REGEN2_CTRL */
1481 #define PALMAS_REGEN2_CTRL_STATUS                               0x10
1482 #define PALMAS_REGEN2_CTRL_STATUS_SHIFT                         4
1483 #define PALMAS_REGEN2_CTRL_MODE_SLEEP                           0x04
1484 #define PALMAS_REGEN2_CTRL_MODE_SLEEP_SHIFT                     2
1485 #define PALMAS_REGEN2_CTRL_MODE_ACTIVE                          0x01
1486 #define PALMAS_REGEN2_CTRL_MODE_ACTIVE_SHIFT                    0
1487
1488 /* Bit definitions for SYSEN1_CTRL */
1489 #define PALMAS_SYSEN1_CTRL_STATUS                               0x10
1490 #define PALMAS_SYSEN1_CTRL_STATUS_SHIFT                         4
1491 #define PALMAS_SYSEN1_CTRL_MODE_SLEEP                           0x04
1492 #define PALMAS_SYSEN1_CTRL_MODE_SLEEP_SHIFT                     2
1493 #define PALMAS_SYSEN1_CTRL_MODE_ACTIVE                          0x01
1494 #define PALMAS_SYSEN1_CTRL_MODE_ACTIVE_SHIFT                    0
1495
1496 /* Bit definitions for SYSEN2_CTRL */
1497 #define PALMAS_SYSEN2_CTRL_STATUS                               0x10
1498 #define PALMAS_SYSEN2_CTRL_STATUS_SHIFT                         4
1499 #define PALMAS_SYSEN2_CTRL_MODE_SLEEP                           0x04
1500 #define PALMAS_SYSEN2_CTRL_MODE_SLEEP_SHIFT                     2
1501 #define PALMAS_SYSEN2_CTRL_MODE_ACTIVE                          0x01
1502 #define PALMAS_SYSEN2_CTRL_MODE_ACTIVE_SHIFT                    0
1503
1504 /* Bit definitions for NSLEEP_RES_ASSIGN */
1505 #define PALMAS_NSLEEP_RES_ASSIGN_REGEN3                         0x40
1506 #define PALMAS_NSLEEP_RES_ASSIGN_REGEN3_SHIFT                   6
1507 #define PALMAS_NSLEEP_RES_ASSIGN_CLK32KGAUDIO                   0x20
1508 #define PALMAS_NSLEEP_RES_ASSIGN_CLK32KGAUDIO_SHIFT             5
1509 #define PALMAS_NSLEEP_RES_ASSIGN_CLK32KG                        0x10
1510 #define PALMAS_NSLEEP_RES_ASSIGN_CLK32KG_SHIFT                  4
1511 #define PALMAS_NSLEEP_RES_ASSIGN_SYSEN2                         0x08
1512 #define PALMAS_NSLEEP_RES_ASSIGN_SYSEN2_SHIFT                   3
1513 #define PALMAS_NSLEEP_RES_ASSIGN_SYSEN1                         0x04
1514 #define PALMAS_NSLEEP_RES_ASSIGN_SYSEN1_SHIFT                   2
1515 #define PALMAS_NSLEEP_RES_ASSIGN_REGEN2                         0x02
1516 #define PALMAS_NSLEEP_RES_ASSIGN_REGEN2_SHIFT                   1
1517 #define PALMAS_NSLEEP_RES_ASSIGN_REGEN1                         0x01
1518 #define PALMAS_NSLEEP_RES_ASSIGN_REGEN1_SHIFT                   0
1519
1520 /* Bit definitions for NSLEEP_SMPS_ASSIGN */
1521 #define PALMAS_NSLEEP_SMPS_ASSIGN_SMPS10                        0x80
1522 #define PALMAS_NSLEEP_SMPS_ASSIGN_SMPS10_SHIFT                  7
1523 #define PALMAS_NSLEEP_SMPS_ASSIGN_SMPS9                         0x40
1524 #define PALMAS_NSLEEP_SMPS_ASSIGN_SMPS9_SHIFT                   6
1525 #define PALMAS_NSLEEP_SMPS_ASSIGN_SMPS8                         0x20
1526 #define PALMAS_NSLEEP_SMPS_ASSIGN_SMPS8_SHIFT                   5
1527 #define PALMAS_NSLEEP_SMPS_ASSIGN_SMPS7                         0x10
1528 #define PALMAS_NSLEEP_SMPS_ASSIGN_SMPS7_SHIFT                   4
1529 #define PALMAS_NSLEEP_SMPS_ASSIGN_SMPS6                         0x08
1530 #define PALMAS_NSLEEP_SMPS_ASSIGN_SMPS6_SHIFT                   3
1531 #define PALMAS_NSLEEP_SMPS_ASSIGN_SMPS45                        0x04
1532 #define PALMAS_NSLEEP_SMPS_ASSIGN_SMPS45_SHIFT                  2
1533 #define PALMAS_NSLEEP_SMPS_ASSIGN_SMPS3                         0x02
1534 #define PALMAS_NSLEEP_SMPS_ASSIGN_SMPS3_SHIFT                   1
1535 #define PALMAS_NSLEEP_SMPS_ASSIGN_SMPS12                        0x01
1536 #define PALMAS_NSLEEP_SMPS_ASSIGN_SMPS12_SHIFT                  0
1537
1538 /* Bit definitions for NSLEEP_LDO_ASSIGN1 */
1539 #define PALMAS_NSLEEP_LDO_ASSIGN1_LDO8                          0x80
1540 #define PALMAS_NSLEEP_LDO_ASSIGN1_LDO8_SHIFT                    7
1541 #define PALMAS_NSLEEP_LDO_ASSIGN1_LDO7                          0x40
1542 #define PALMAS_NSLEEP_LDO_ASSIGN1_LDO7_SHIFT                    6
1543 #define PALMAS_NSLEEP_LDO_ASSIGN1_LDO6                          0x20
1544 #define PALMAS_NSLEEP_LDO_ASSIGN1_LDO6_SHIFT                    5
1545 #define PALMAS_NSLEEP_LDO_ASSIGN1_LDO5                          0x10
1546 #define PALMAS_NSLEEP_LDO_ASSIGN1_LDO5_SHIFT                    4
1547 #define PALMAS_NSLEEP_LDO_ASSIGN1_LDO4                          0x08
1548 #define PALMAS_NSLEEP_LDO_ASSIGN1_LDO4_SHIFT                    3
1549 #define PALMAS_NSLEEP_LDO_ASSIGN1_LDO3                          0x04
1550 #define PALMAS_NSLEEP_LDO_ASSIGN1_LDO3_SHIFT                    2
1551 #define PALMAS_NSLEEP_LDO_ASSIGN1_LDO2                          0x02
1552 #define PALMAS_NSLEEP_LDO_ASSIGN1_LDO2_SHIFT                    1
1553 #define PALMAS_NSLEEP_LDO_ASSIGN1_LDO1                          0x01
1554 #define PALMAS_NSLEEP_LDO_ASSIGN1_LDO1_SHIFT                    0
1555
1556 /* Bit definitions for NSLEEP_LDO_ASSIGN2 */
1557 #define PALMAS_NSLEEP_LDO_ASSIGN2_LDOUSB                        0x04
1558 #define PALMAS_NSLEEP_LDO_ASSIGN2_LDOUSB_SHIFT                  2
1559 #define PALMAS_NSLEEP_LDO_ASSIGN2_LDOLN                         0x02
1560 #define PALMAS_NSLEEP_LDO_ASSIGN2_LDOLN_SHIFT                   1
1561 #define PALMAS_NSLEEP_LDO_ASSIGN2_LDO9                          0x01
1562 #define PALMAS_NSLEEP_LDO_ASSIGN2_LDO9_SHIFT                    0
1563
1564 /* Bit definitions for ENABLE1_RES_ASSIGN */
1565 #define PALMAS_ENABLE1_RES_ASSIGN_REGEN3                        0x40
1566 #define PALMAS_ENABLE1_RES_ASSIGN_REGEN3_SHIFT                  6
1567 #define PALMAS_ENABLE1_RES_ASSIGN_CLK32KGAUDIO                  0x20
1568 #define PALMAS_ENABLE1_RES_ASSIGN_CLK32KGAUDIO_SHIFT            5
1569 #define PALMAS_ENABLE1_RES_ASSIGN_CLK32KG                       0x10
1570 #define PALMAS_ENABLE1_RES_ASSIGN_CLK32KG_SHIFT                 4
1571 #define PALMAS_ENABLE1_RES_ASSIGN_SYSEN2                        0x08
1572 #define PALMAS_ENABLE1_RES_ASSIGN_SYSEN2_SHIFT                  3
1573 #define PALMAS_ENABLE1_RES_ASSIGN_SYSEN1                        0x04
1574 #define PALMAS_ENABLE1_RES_ASSIGN_SYSEN1_SHIFT                  2
1575 #define PALMAS_ENABLE1_RES_ASSIGN_REGEN2                        0x02
1576 #define PALMAS_ENABLE1_RES_ASSIGN_REGEN2_SHIFT                  1
1577 #define PALMAS_ENABLE1_RES_ASSIGN_REGEN1                        0x01
1578 #define PALMAS_ENABLE1_RES_ASSIGN_REGEN1_SHIFT                  0
1579
1580 /* Bit definitions for ENABLE1_SMPS_ASSIGN */
1581 #define PALMAS_ENABLE1_SMPS_ASSIGN_SMPS10                       0x80
1582 #define PALMAS_ENABLE1_SMPS_ASSIGN_SMPS10_SHIFT                 7
1583 #define PALMAS_ENABLE1_SMPS_ASSIGN_SMPS9                        0x40
1584 #define PALMAS_ENABLE1_SMPS_ASSIGN_SMPS9_SHIFT                  6
1585 #define PALMAS_ENABLE1_SMPS_ASSIGN_SMPS8                        0x20
1586 #define PALMAS_ENABLE1_SMPS_ASSIGN_SMPS8_SHIFT                  5
1587 #define PALMAS_ENABLE1_SMPS_ASSIGN_SMPS7                        0x10
1588 #define PALMAS_ENABLE1_SMPS_ASSIGN_SMPS7_SHIFT                  4
1589 #define PALMAS_ENABLE1_SMPS_ASSIGN_SMPS6                        0x08
1590 #define PALMAS_ENABLE1_SMPS_ASSIGN_SMPS6_SHIFT                  3
1591 #define PALMAS_ENABLE1_SMPS_ASSIGN_SMPS45                       0x04
1592 #define PALMAS_ENABLE1_SMPS_ASSIGN_SMPS45_SHIFT                 2
1593 #define PALMAS_ENABLE1_SMPS_ASSIGN_SMPS3                        0x02
1594 #define PALMAS_ENABLE1_SMPS_ASSIGN_SMPS3_SHIFT                  1
1595 #define PALMAS_ENABLE1_SMPS_ASSIGN_SMPS12                       0x01
1596 #define PALMAS_ENABLE1_SMPS_ASSIGN_SMPS12_SHIFT                 0
1597
1598 /* Bit definitions for ENABLE1_LDO_ASSIGN1 */
1599 #define PALMAS_ENABLE1_LDO_ASSIGN1_LDO8                         0x80
1600 #define PALMAS_ENABLE1_LDO_ASSIGN1_LDO8_SHIFT                   7
1601 #define PALMAS_ENABLE1_LDO_ASSIGN1_LDO7                         0x40
1602 #define PALMAS_ENABLE1_LDO_ASSIGN1_LDO7_SHIFT                   6
1603 #define PALMAS_ENABLE1_LDO_ASSIGN1_LDO6                         0x20
1604 #define PALMAS_ENABLE1_LDO_ASSIGN1_LDO6_SHIFT                   5
1605 #define PALMAS_ENABLE1_LDO_ASSIGN1_LDO5                         0x10
1606 #define PALMAS_ENABLE1_LDO_ASSIGN1_LDO5_SHIFT                   4
1607 #define PALMAS_ENABLE1_LDO_ASSIGN1_LDO4                         0x08
1608 #define PALMAS_ENABLE1_LDO_ASSIGN1_LDO4_SHIFT                   3
1609 #define PALMAS_ENABLE1_LDO_ASSIGN1_LDO3                         0x04
1610 #define PALMAS_ENABLE1_LDO_ASSIGN1_LDO3_SHIFT                   2
1611 #define PALMAS_ENABLE1_LDO_ASSIGN1_LDO2                         0x02
1612 #define PALMAS_ENABLE1_LDO_ASSIGN1_LDO2_SHIFT                   1
1613 #define PALMAS_ENABLE1_LDO_ASSIGN1_LDO1                         0x01
1614 #define PALMAS_ENABLE1_LDO_ASSIGN1_LDO1_SHIFT                   0
1615
1616 /* Bit definitions for ENABLE1_LDO_ASSIGN2 */
1617 #define PALMAS_ENABLE1_LDO_ASSIGN2_LDOUSB                       0x04
1618 #define PALMAS_ENABLE1_LDO_ASSIGN2_LDOUSB_SHIFT                 2
1619 #define PALMAS_ENABLE1_LDO_ASSIGN2_LDOLN                        0x02
1620 #define PALMAS_ENABLE1_LDO_ASSIGN2_LDOLN_SHIFT                  1
1621 #define PALMAS_ENABLE1_LDO_ASSIGN2_LDO9                         0x01
1622 #define PALMAS_ENABLE1_LDO_ASSIGN2_LDO9_SHIFT                   0
1623
1624 /* Bit definitions for ENABLE2_RES_ASSIGN */
1625 #define PALMAS_ENABLE2_RES_ASSIGN_REGEN3                        0x40
1626 #define PALMAS_ENABLE2_RES_ASSIGN_REGEN3_SHIFT                  6
1627 #define PALMAS_ENABLE2_RES_ASSIGN_CLK32KGAUDIO                  0x20
1628 #define PALMAS_ENABLE2_RES_ASSIGN_CLK32KGAUDIO_SHIFT            5
1629 #define PALMAS_ENABLE2_RES_ASSIGN_CLK32KG                       0x10
1630 #define PALMAS_ENABLE2_RES_ASSIGN_CLK32KG_SHIFT                 4
1631 #define PALMAS_ENABLE2_RES_ASSIGN_SYSEN2                        0x08
1632 #define PALMAS_ENABLE2_RES_ASSIGN_SYSEN2_SHIFT                  3
1633 #define PALMAS_ENABLE2_RES_ASSIGN_SYSEN1                        0x04
1634 #define PALMAS_ENABLE2_RES_ASSIGN_SYSEN1_SHIFT                  2
1635 #define PALMAS_ENABLE2_RES_ASSIGN_REGEN2                        0x02
1636 #define PALMAS_ENABLE2_RES_ASSIGN_REGEN2_SHIFT                  1
1637 #define PALMAS_ENABLE2_RES_ASSIGN_REGEN1                        0x01
1638 #define PALMAS_ENABLE2_RES_ASSIGN_REGEN1_SHIFT                  0
1639
1640 /* Bit definitions for ENABLE2_SMPS_ASSIGN */
1641 #define PALMAS_ENABLE2_SMPS_ASSIGN_SMPS10                       0x80
1642 #define PALMAS_ENABLE2_SMPS_ASSIGN_SMPS10_SHIFT                 7
1643 #define PALMAS_ENABLE2_SMPS_ASSIGN_SMPS9                        0x40
1644 #define PALMAS_ENABLE2_SMPS_ASSIGN_SMPS9_SHIFT                  6
1645 #define PALMAS_ENABLE2_SMPS_ASSIGN_SMPS8                        0x20
1646 #define PALMAS_ENABLE2_SMPS_ASSIGN_SMPS8_SHIFT                  5
1647 #define PALMAS_ENABLE2_SMPS_ASSIGN_SMPS7                        0x10
1648 #define PALMAS_ENABLE2_SMPS_ASSIGN_SMPS7_SHIFT                  4
1649 #define PALMAS_ENABLE2_SMPS_ASSIGN_SMPS6                        0x08
1650 #define PALMAS_ENABLE2_SMPS_ASSIGN_SMPS6_SHIFT                  3
1651 #define PALMAS_ENABLE2_SMPS_ASSIGN_SMPS45                       0x04
1652 #define PALMAS_ENABLE2_SMPS_ASSIGN_SMPS45_SHIFT                 2
1653 #define PALMAS_ENABLE2_SMPS_ASSIGN_SMPS3                        0x02
1654 #define PALMAS_ENABLE2_SMPS_ASSIGN_SMPS3_SHIFT                  1
1655 #define PALMAS_ENABLE2_SMPS_ASSIGN_SMPS12                       0x01
1656 #define PALMAS_ENABLE2_SMPS_ASSIGN_SMPS12_SHIFT                 0
1657
1658 /* Bit definitions for ENABLE2_LDO_ASSIGN1 */
1659 #define PALMAS_ENABLE2_LDO_ASSIGN1_LDO8                         0x80
1660 #define PALMAS_ENABLE2_LDO_ASSIGN1_LDO8_SHIFT                   7
1661 #define PALMAS_ENABLE2_LDO_ASSIGN1_LDO7                         0x40
1662 #define PALMAS_ENABLE2_LDO_ASSIGN1_LDO7_SHIFT                   6
1663 #define PALMAS_ENABLE2_LDO_ASSIGN1_LDO6                         0x20
1664 #define PALMAS_ENABLE2_LDO_ASSIGN1_LDO6_SHIFT                   5
1665 #define PALMAS_ENABLE2_LDO_ASSIGN1_LDO5                         0x10
1666 #define PALMAS_ENABLE2_LDO_ASSIGN1_LDO5_SHIFT                   4
1667 #define PALMAS_ENABLE2_LDO_ASSIGN1_LDO4                         0x08
1668 #define PALMAS_ENABLE2_LDO_ASSIGN1_LDO4_SHIFT                   3
1669 #define PALMAS_ENABLE2_LDO_ASSIGN1_LDO3                         0x04
1670 #define PALMAS_ENABLE2_LDO_ASSIGN1_LDO3_SHIFT                   2
1671 #define PALMAS_ENABLE2_LDO_ASSIGN1_LDO2                         0x02
1672 #define PALMAS_ENABLE2_LDO_ASSIGN1_LDO2_SHIFT                   1
1673 #define PALMAS_ENABLE2_LDO_ASSIGN1_LDO1                         0x01
1674 #define PALMAS_ENABLE2_LDO_ASSIGN1_LDO1_SHIFT                   0
1675
1676 /* Bit definitions for ENABLE2_LDO_ASSIGN2 */
1677 #define PALMAS_ENABLE2_LDO_ASSIGN2_LDOUSB                       0x04
1678 #define PALMAS_ENABLE2_LDO_ASSIGN2_LDOUSB_SHIFT                 2
1679 #define PALMAS_ENABLE2_LDO_ASSIGN2_LDOLN                        0x02
1680 #define PALMAS_ENABLE2_LDO_ASSIGN2_LDOLN_SHIFT                  1
1681 #define PALMAS_ENABLE2_LDO_ASSIGN2_LDO9                         0x01
1682 #define PALMAS_ENABLE2_LDO_ASSIGN2_LDO9_SHIFT                   0
1683
1684 /* Bit definitions for REGEN3_CTRL */
1685 #define PALMAS_REGEN3_CTRL_STATUS                               0x10
1686 #define PALMAS_REGEN3_CTRL_STATUS_SHIFT                         4
1687 #define PALMAS_REGEN3_CTRL_MODE_SLEEP                           0x04
1688 #define PALMAS_REGEN3_CTRL_MODE_SLEEP_SHIFT                     2
1689 #define PALMAS_REGEN3_CTRL_MODE_ACTIVE                          0x01
1690 #define PALMAS_REGEN3_CTRL_MODE_ACTIVE_SHIFT                    0
1691
1692 /* Registers for function PAD_CONTROL */
1693 #define PALMAS_PU_PD_INPUT_CTRL1                                0x0
1694 #define PALMAS_PU_PD_INPUT_CTRL2                                0x1
1695 #define PALMAS_PU_PD_INPUT_CTRL3                                0x2
1696 #define PALMAS_OD_OUTPUT_CTRL                                   0x4
1697 #define PALMAS_POLARITY_CTRL                                    0x5
1698 #define PALMAS_PRIMARY_SECONDARY_PAD1                           0x6
1699 #define PALMAS_PRIMARY_SECONDARY_PAD2                           0x7
1700 #define PALMAS_I2C_SPI                                          0x8
1701 #define PALMAS_PU_PD_INPUT_CTRL4                                0x9
1702 #define PALMAS_PRIMARY_SECONDARY_PAD3                           0xA
1703
1704 /* Bit definitions for PU_PD_INPUT_CTRL1 */
1705 #define PALMAS_PU_PD_INPUT_CTRL1_RESET_IN_PD                    0x40
1706 #define PALMAS_PU_PD_INPUT_CTRL1_RESET_IN_PD_SHIFT              6
1707 #define PALMAS_PU_PD_INPUT_CTRL1_GPADC_START_PU                 0x20
1708 #define PALMAS_PU_PD_INPUT_CTRL1_GPADC_START_PU_SHIFT           5
1709 #define PALMAS_PU_PD_INPUT_CTRL1_GPADC_START_PD                 0x10
1710 #define PALMAS_PU_PD_INPUT_CTRL1_GPADC_START_PD_SHIFT           4
1711 #define PALMAS_PU_PD_INPUT_CTRL1_PWRDOWN_PD                     0x04
1712 #define PALMAS_PU_PD_INPUT_CTRL1_PWRDOWN_PD_SHIFT               2
1713 #define PALMAS_PU_PD_INPUT_CTRL1_NRESWARM_PU                    0x02
1714 #define PALMAS_PU_PD_INPUT_CTRL1_NRESWARM_PU_SHIFT              1
1715
1716 /* Bit definitions for PU_PD_INPUT_CTRL2 */
1717 #define PALMAS_PU_PD_INPUT_CTRL2_ENABLE2_PU                     0x20
1718 #define PALMAS_PU_PD_INPUT_CTRL2_ENABLE2_PU_SHIFT               5
1719 #define PALMAS_PU_PD_INPUT_CTRL2_ENABLE2_PD                     0x10
1720 #define PALMAS_PU_PD_INPUT_CTRL2_ENABLE2_PD_SHIFT               4
1721 #define PALMAS_PU_PD_INPUT_CTRL2_ENABLE1_PU                     0x08
1722 #define PALMAS_PU_PD_INPUT_CTRL2_ENABLE1_PU_SHIFT               3
1723 #define PALMAS_PU_PD_INPUT_CTRL2_ENABLE1_PD                     0x04
1724 #define PALMAS_PU_PD_INPUT_CTRL2_ENABLE1_PD_SHIFT               2
1725 #define PALMAS_PU_PD_INPUT_CTRL2_NSLEEP_PU                      0x02
1726 #define PALMAS_PU_PD_INPUT_CTRL2_NSLEEP_PU_SHIFT                1
1727 #define PALMAS_PU_PD_INPUT_CTRL2_NSLEEP_PD                      0x01
1728 #define PALMAS_PU_PD_INPUT_CTRL2_NSLEEP_PD_SHIFT                0
1729
1730 /* Bit definitions for PU_PD_INPUT_CTRL3 */
1731 #define PALMAS_PU_PD_INPUT_CTRL3_ACOK_PD                        0x40
1732 #define PALMAS_PU_PD_INPUT_CTRL3_ACOK_PD_SHIFT                  6
1733 #define PALMAS_PU_PD_INPUT_CTRL3_CHRG_DET_N_PD                  0x10
1734 #define PALMAS_PU_PD_INPUT_CTRL3_CHRG_DET_N_PD_SHIFT            4
1735 #define PALMAS_PU_PD_INPUT_CTRL3_POWERHOLD_PD                   0x04
1736 #define PALMAS_PU_PD_INPUT_CTRL3_POWERHOLD_PD_SHIFT             2
1737 #define PALMAS_PU_PD_INPUT_CTRL3_MSECURE_PD                     0x01
1738 #define PALMAS_PU_PD_INPUT_CTRL3_MSECURE_PD_SHIFT               0
1739
1740 /* Bit definitions for OD_OUTPUT_CTRL */
1741 #define PALMAS_OD_OUTPUT_CTRL_PWM_2_OD                          0x80
1742 #define PALMAS_OD_OUTPUT_CTRL_PWM_2_OD_SHIFT                    7
1743 #define PALMAS_OD_OUTPUT_CTRL_VBUSDET_OD                        0x40
1744 #define PALMAS_OD_OUTPUT_CTRL_VBUSDET_OD_SHIFT                  6
1745 #define PALMAS_OD_OUTPUT_CTRL_PWM_1_OD                          0x20
1746 #define PALMAS_OD_OUTPUT_CTRL_PWM_1_OD_SHIFT                    5
1747 #define PALMAS_OD_OUTPUT_CTRL_INT_OD                            0x08
1748 #define PALMAS_OD_OUTPUT_CTRL_INT_OD_SHIFT                      3
1749
1750 /* Bit definitions for POLARITY_CTRL */
1751 #define PALMAS_POLARITY_CTRL_INT_POLARITY                       0x80
1752 #define PALMAS_POLARITY_CTRL_INT_POLARITY_SHIFT                 7
1753 #define PALMAS_POLARITY_CTRL_ENABLE2_POLARITY                   0x40
1754 #define PALMAS_POLARITY_CTRL_ENABLE2_POLARITY_SHIFT             6
1755 #define PALMAS_POLARITY_CTRL_ENABLE1_POLARITY                   0x20
1756 #define PALMAS_POLARITY_CTRL_ENABLE1_POLARITY_SHIFT             5
1757 #define PALMAS_POLARITY_CTRL_NSLEEP_POLARITY                    0x10
1758 #define PALMAS_POLARITY_CTRL_NSLEEP_POLARITY_SHIFT              4
1759 #define PALMAS_POLARITY_CTRL_RESET_IN_POLARITY                  0x08
1760 #define PALMAS_POLARITY_CTRL_RESET_IN_POLARITY_SHIFT            3
1761 #define PALMAS_POLARITY_CTRL_GPIO_3_CHRG_DET_N_POLARITY         0x04
1762 #define PALMAS_POLARITY_CTRL_GPIO_3_CHRG_DET_N_POLARITY_SHIFT   2
1763 #define PALMAS_POLARITY_CTRL_POWERGOOD_USB_PSEL_POLARITY        0x02
1764 #define PALMAS_POLARITY_CTRL_POWERGOOD_USB_PSEL_POLARITY_SHIFT  1
1765 #define PALMAS_POLARITY_CTRL_PWRDOWN_POLARITY                   0x01
1766 #define PALMAS_POLARITY_CTRL_PWRDOWN_POLARITY_SHIFT             0
1767
1768 /* Bit definitions for PRIMARY_SECONDARY_PAD1 */
1769 #define PALMAS_PRIMARY_SECONDARY_PAD1_GPIO_3                    0x80
1770 #define PALMAS_PRIMARY_SECONDARY_PAD1_GPIO_3_SHIFT              7
1771 #define PALMAS_PRIMARY_SECONDARY_PAD1_GPIO_2_MASK               0x60
1772 #define PALMAS_PRIMARY_SECONDARY_PAD1_GPIO_2_SHIFT              5
1773 #define PALMAS_PRIMARY_SECONDARY_PAD1_GPIO_1_MASK               0x18
1774 #define PALMAS_PRIMARY_SECONDARY_PAD1_GPIO_1_SHIFT              3
1775 #define PALMAS_PRIMARY_SECONDARY_PAD1_GPIO_0                    0x04
1776 #define PALMAS_PRIMARY_SECONDARY_PAD1_GPIO_0_SHIFT              2
1777 #define PALMAS_PRIMARY_SECONDARY_PAD1_VAC                       0x02
1778 #define PALMAS_PRIMARY_SECONDARY_PAD1_VAC_SHIFT                 1
1779 #define PALMAS_PRIMARY_SECONDARY_PAD1_POWERGOOD                 0x01
1780 #define PALMAS_PRIMARY_SECONDARY_PAD1_POWERGOOD_SHIFT           0
1781
1782 /* Bit definitions for PRIMARY_SECONDARY_PAD2 */
1783 #define PALMAS_PRIMARY_SECONDARY_PAD2_GPIO_7_MASK               0x30
1784 #define PALMAS_PRIMARY_SECONDARY_PAD2_GPIO_7_SHIFT              4
1785 #define PALMAS_PRIMARY_SECONDARY_PAD2_GPIO_6                    0x08
1786 #define PALMAS_PRIMARY_SECONDARY_PAD2_GPIO_6_SHIFT              3
1787 #define PALMAS_PRIMARY_SECONDARY_PAD2_GPIO_5_MASK               0x06
1788 #define PALMAS_PRIMARY_SECONDARY_PAD2_GPIO_5_SHIFT              1
1789 #define PALMAS_PRIMARY_SECONDARY_PAD2_GPIO_4                    0x01
1790 #define PALMAS_PRIMARY_SECONDARY_PAD2_GPIO_4_SHIFT              0
1791
1792 /* Bit definitions for I2C_SPI */
1793 #define PALMAS_I2C_SPI_I2C2OTP_EN                               0x80
1794 #define PALMAS_I2C_SPI_I2C2OTP_EN_SHIFT                         7
1795 #define PALMAS_I2C_SPI_I2C2OTP_PAGESEL                          0x40
1796 #define PALMAS_I2C_SPI_I2C2OTP_PAGESEL_SHIFT                    6
1797 #define PALMAS_I2C_SPI_ID_I2C2                                  0x20
1798 #define PALMAS_I2C_SPI_ID_I2C2_SHIFT                            5
1799 #define PALMAS_I2C_SPI_I2C_SPI                                  0x10
1800 #define PALMAS_I2C_SPI_I2C_SPI_SHIFT                            4
1801 #define PALMAS_I2C_SPI_ID_I2C1_MASK                             0x0f
1802 #define PALMAS_I2C_SPI_ID_I2C1_SHIFT                            0
1803
1804 /* Bit definitions for PU_PD_INPUT_CTRL4 */
1805 #define PALMAS_PU_PD_INPUT_CTRL4_DVFS2_DAT_PD                   0x40
1806 #define PALMAS_PU_PD_INPUT_CTRL4_DVFS2_DAT_PD_SHIFT             6
1807 #define PALMAS_PU_PD_INPUT_CTRL4_DVFS2_CLK_PD                   0x10
1808 #define PALMAS_PU_PD_INPUT_CTRL4_DVFS2_CLK_PD_SHIFT             4
1809 #define PALMAS_PU_PD_INPUT_CTRL4_DVFS1_DAT_PD                   0x04
1810 #define PALMAS_PU_PD_INPUT_CTRL4_DVFS1_DAT_PD_SHIFT             2
1811 #define PALMAS_PU_PD_INPUT_CTRL4_DVFS1_CLK_PD                   0x01
1812 #define PALMAS_PU_PD_INPUT_CTRL4_DVFS1_CLK_PD_SHIFT             0
1813
1814 /* Bit definitions for PRIMARY_SECONDARY_PAD3 */
1815 #define PALMAS_PRIMARY_SECONDARY_PAD3_DVFS2                     0x02
1816 #define PALMAS_PRIMARY_SECONDARY_PAD3_DVFS2_SHIFT               1
1817 #define PALMAS_PRIMARY_SECONDARY_PAD3_DVFS1                     0x01
1818 #define PALMAS_PRIMARY_SECONDARY_PAD3_DVFS1_SHIFT               0
1819
1820 /* Registers for function LED_PWM */
1821 #define PALMAS_LED_PERIOD_CTRL                                  0x0
1822 #define PALMAS_LED_CTRL                                         0x1
1823 #define PALMAS_PWM_CTRL1                                        0x2
1824 #define PALMAS_PWM_CTRL2                                        0x3
1825
1826 /* Bit definitions for LED_PERIOD_CTRL */
1827 #define PALMAS_LED_PERIOD_CTRL_LED_2_PERIOD_MASK                0x38
1828 #define PALMAS_LED_PERIOD_CTRL_LED_2_PERIOD_SHIFT               3
1829 #define PALMAS_LED_PERIOD_CTRL_LED_1_PERIOD_MASK                0x07
1830 #define PALMAS_LED_PERIOD_CTRL_LED_1_PERIOD_SHIFT               0
1831
1832 /* Bit definitions for LED_CTRL */
1833 #define PALMAS_LED_CTRL_LED_2_SEQ                               0x20
1834 #define PALMAS_LED_CTRL_LED_2_SEQ_SHIFT                         5
1835 #define PALMAS_LED_CTRL_LED_1_SEQ                               0x10
1836 #define PALMAS_LED_CTRL_LED_1_SEQ_SHIFT                         4
1837 #define PALMAS_LED_CTRL_LED_2_ON_TIME_MASK                      0x0c
1838 #define PALMAS_LED_CTRL_LED_2_ON_TIME_SHIFT                     2
1839 #define PALMAS_LED_CTRL_LED_1_ON_TIME_MASK                      0x03
1840 #define PALMAS_LED_CTRL_LED_1_ON_TIME_SHIFT                     0
1841
1842 /* Bit definitions for PWM_CTRL1 */
1843 #define PALMAS_PWM_CTRL1_PWM_FREQ_EN                            0x02
1844 #define PALMAS_PWM_CTRL1_PWM_FREQ_EN_SHIFT                      1
1845 #define PALMAS_PWM_CTRL1_PWM_FREQ_SEL                           0x01
1846 #define PALMAS_PWM_CTRL1_PWM_FREQ_SEL_SHIFT                     0
1847
1848 /* Bit definitions for PWM_CTRL2 */
1849 #define PALMAS_PWM_CTRL2_PWM_DUTY_SEL_MASK                      0xff
1850 #define PALMAS_PWM_CTRL2_PWM_DUTY_SEL_SHIFT                     0
1851
1852 /* Maximum INT mask/edge regsiter */
1853 #define PALMAS_MAX_INTERRUPT_MASK_REG                           4
1854 #define PALMAS_MAX_INTERRUPT_EDGE_REG                           8
1855
1856 /* Registers for function INTERRUPT */
1857 #define PALMAS_INT1_STATUS                                      0x0
1858 #define PALMAS_INT1_MASK                                        0x1
1859 #define PALMAS_INT1_LINE_STATE                                  0x2
1860 #define PALMAS_INT1_EDGE_DETECT1_RESERVED                       0x3
1861 #define PALMAS_INT1_EDGE_DETECT2_RESERVED                       0x4
1862 #define PALMAS_INT2_STATUS                                      0x5
1863 #define PALMAS_INT2_MASK                                        0x6
1864 #define PALMAS_INT2_LINE_STATE                                  0x7
1865 #define PALMAS_INT2_EDGE_DETECT1_RESERVED                       0x8
1866 #define PALMAS_INT2_EDGE_DETECT2_RESERVED                       0x9
1867 #define PALMAS_INT3_STATUS                                      0xA
1868 #define PALMAS_INT3_MASK                                        0xB
1869 #define PALMAS_INT3_LINE_STATE                                  0xC
1870 #define PALMAS_INT3_EDGE_DETECT1_RESERVED                       0xD
1871 #define PALMAS_INT3_EDGE_DETECT2_RESERVED                       0xE
1872 #define PALMAS_INT4_STATUS                                      0xF
1873 #define PALMAS_INT4_MASK                                        0x10
1874 #define PALMAS_INT4_LINE_STATE                                  0x11
1875 #define PALMAS_INT4_EDGE_DETECT1                                0x12
1876 #define PALMAS_INT4_EDGE_DETECT2                                0x13
1877 #define PALMAS_INT_CTRL                                         0x14
1878
1879 /* Bit definitions for INT1_STATUS */
1880 #define PALMAS_INT1_STATUS_VBAT_MON                             0x80
1881 #define PALMAS_INT1_STATUS_VBAT_MON_SHIFT                       7
1882 #define PALMAS_INT1_STATUS_VSYS_MON                             0x40
1883 #define PALMAS_INT1_STATUS_VSYS_MON_SHIFT                       6
1884 #define PALMAS_INT1_STATUS_HOTDIE                               0x20
1885 #define PALMAS_INT1_STATUS_HOTDIE_SHIFT                         5
1886 #define PALMAS_INT1_STATUS_PWRDOWN                              0x10
1887 #define PALMAS_INT1_STATUS_PWRDOWN_SHIFT                        4
1888 #define PALMAS_INT1_STATUS_RPWRON                               0x08
1889 #define PALMAS_INT1_STATUS_RPWRON_SHIFT                         3
1890 #define PALMAS_INT1_STATUS_LONG_PRESS_KEY                       0x04
1891 #define PALMAS_INT1_STATUS_LONG_PRESS_KEY_SHIFT                 2
1892 #define PALMAS_INT1_STATUS_PWRON                                0x02
1893 #define PALMAS_INT1_STATUS_PWRON_SHIFT                          1
1894 #define PALMAS_INT1_STATUS_CHARG_DET_N_VBUS_OVV                 0x01
1895 #define PALMAS_INT1_STATUS_CHARG_DET_N_VBUS_OVV_SHIFT           0
1896
1897 /* Bit definitions for INT1_MASK */
1898 #define PALMAS_INT1_MASK_VBAT_MON                               0x80
1899 #define PALMAS_INT1_MASK_VBAT_MON_SHIFT                         7
1900 #define PALMAS_INT1_MASK_VSYS_MON                               0x40
1901 #define PALMAS_INT1_MASK_VSYS_MON_SHIFT                         6
1902 #define PALMAS_INT1_MASK_HOTDIE                                 0x20
1903 #define PALMAS_INT1_MASK_HOTDIE_SHIFT                           5
1904 #define PALMAS_INT1_MASK_PWRDOWN                                0x10
1905 #define PALMAS_INT1_MASK_PWRDOWN_SHIFT                          4
1906 #define PALMAS_INT1_MASK_RPWRON                                 0x08
1907 #define PALMAS_INT1_MASK_RPWRON_SHIFT                           3
1908 #define PALMAS_INT1_MASK_LONG_PRESS_KEY                         0x04
1909 #define PALMAS_INT1_MASK_LONG_PRESS_KEY_SHIFT                   2
1910 #define PALMAS_INT1_MASK_PWRON                                  0x02
1911 #define PALMAS_INT1_MASK_PWRON_SHIFT                            1
1912 #define PALMAS_INT1_MASK_CHARG_DET_N_VBUS_OVV                   0x01
1913 #define PALMAS_INT1_MASK_CHARG_DET_N_VBUS_OVV_SHIFT             0
1914
1915 /* Bit definitions for INT1_LINE_STATE */
1916 #define PALMAS_INT1_LINE_STATE_VBAT_MON                         0x80
1917 #define PALMAS_INT1_LINE_STATE_VBAT_MON_SHIFT                   7
1918 #define PALMAS_INT1_LINE_STATE_VSYS_MON                         0x40
1919 #define PALMAS_INT1_LINE_STATE_VSYS_MON_SHIFT                   6
1920 #define PALMAS_INT1_LINE_STATE_HOTDIE                           0x20
1921 #define PALMAS_INT1_LINE_STATE_HOTDIE_SHIFT                     5
1922 #define PALMAS_INT1_LINE_STATE_PWRDOWN                          0x10
1923 #define PALMAS_INT1_LINE_STATE_PWRDOWN_SHIFT                    4
1924 #define PALMAS_INT1_LINE_STATE_RPWRON                           0x08
1925 #define PALMAS_INT1_LINE_STATE_RPWRON_SHIFT                     3
1926 #define PALMAS_INT1_LINE_STATE_LONG_PRESS_KEY                   0x04
1927 #define PALMAS_INT1_LINE_STATE_LONG_PRESS_KEY_SHIFT             2
1928 #define PALMAS_INT1_LINE_STATE_PWRON                            0x02
1929 #define PALMAS_INT1_LINE_STATE_PWRON_SHIFT                      1
1930 #define PALMAS_INT1_LINE_STATE_CHARG_DET_N_VBUS_OVV             0x01
1931 #define PALMAS_INT1_LINE_STATE_CHARG_DET_N_VBUS_OVV_SHIFT       0
1932
1933 /* Bit definitions for INT2_STATUS */
1934 #define PALMAS_INT2_STATUS_VAC_ACOK                             0x80
1935 #define PALMAS_INT2_STATUS_VAC_ACOK_SHIFT                       7
1936 #define PALMAS_INT2_STATUS_SHORT                                0x40
1937 #define PALMAS_INT2_STATUS_SHORT_SHIFT                          6
1938 #define PALMAS_INT2_STATUS_FBI_BB                               0x20
1939 #define PALMAS_INT2_STATUS_FBI_BB_SHIFT                         5
1940 #define PALMAS_INT2_STATUS_RESET_IN                             0x10
1941 #define PALMAS_INT2_STATUS_RESET_IN_SHIFT                       4
1942 #define PALMAS_INT2_STATUS_BATREMOVAL                           0x08
1943 #define PALMAS_INT2_STATUS_BATREMOVAL_SHIFT                     3
1944 #define PALMAS_INT2_STATUS_WDT                                  0x04
1945 #define PALMAS_INT2_STATUS_WDT_SHIFT                            2
1946 #define PALMAS_INT2_STATUS_RTC_TIMER                            0x02
1947 #define PALMAS_INT2_STATUS_RTC_TIMER_SHIFT                      1
1948 #define PALMAS_INT2_STATUS_RTC_ALARM                            0x01
1949 #define PALMAS_INT2_STATUS_RTC_ALARM_SHIFT                      0
1950
1951 /* Bit definitions for INT2_MASK */
1952 #define PALMAS_INT2_MASK_VAC_ACOK                               0x80
1953 #define PALMAS_INT2_MASK_VAC_ACOK_SHIFT                         7
1954 #define PALMAS_INT2_MASK_SHORT                                  0x40
1955 #define PALMAS_INT2_MASK_SHORT_SHIFT                            6
1956 #define PALMAS_INT2_MASK_FBI_BB                                 0x20
1957 #define PALMAS_INT2_MASK_FBI_BB_SHIFT                           5
1958 #define PALMAS_INT2_MASK_RESET_IN                               0x10
1959 #define PALMAS_INT2_MASK_RESET_IN_SHIFT                         4
1960 #define PALMAS_INT2_MASK_BATREMOVAL                             0x08
1961 #define PALMAS_INT2_MASK_BATREMOVAL_SHIFT                       3
1962 #define PALMAS_INT2_MASK_WDT                                    0x04
1963 #define PALMAS_INT2_MASK_WDT_SHIFT                              2
1964 #define PALMAS_INT2_MASK_RTC_TIMER                              0x02
1965 #define PALMAS_INT2_MASK_RTC_TIMER_SHIFT                        1
1966 #define PALMAS_INT2_MASK_RTC_ALARM                              0x01
1967 #define PALMAS_INT2_MASK_RTC_ALARM_SHIFT                        0
1968
1969 /* Bit definitions for INT2_LINE_STATE */
1970 #define PALMAS_INT2_LINE_STATE_VAC_ACOK                         0x80
1971 #define PALMAS_INT2_LINE_STATE_VAC_ACOK_SHIFT                   7
1972 #define PALMAS_INT2_LINE_STATE_SHORT                            0x40
1973 #define PALMAS_INT2_LINE_STATE_SHORT_SHIFT                      6
1974 #define PALMAS_INT2_LINE_STATE_FBI_BB                           0x20
1975 #define PALMAS_INT2_LINE_STATE_FBI_BB_SHIFT                     5
1976 #define PALMAS_INT2_LINE_STATE_RESET_IN                         0x10
1977 #define PALMAS_INT2_LINE_STATE_RESET_IN_SHIFT                   4
1978 #define PALMAS_INT2_LINE_STATE_BATREMOVAL                       0x08
1979 #define PALMAS_INT2_LINE_STATE_BATREMOVAL_SHIFT                 3
1980 #define PALMAS_INT2_LINE_STATE_WDT                              0x04
1981 #define PALMAS_INT2_LINE_STATE_WDT_SHIFT                        2
1982 #define PALMAS_INT2_LINE_STATE_RTC_TIMER                        0x02
1983 #define PALMAS_INT2_LINE_STATE_RTC_TIMER_SHIFT                  1
1984 #define PALMAS_INT2_LINE_STATE_RTC_ALARM                        0x01
1985 #define PALMAS_INT2_LINE_STATE_RTC_ALARM_SHIFT                  0
1986
1987 /* Bit definitions for INT3_STATUS */
1988 #define PALMAS_INT3_STATUS_VBUS                                 0x80
1989 #define PALMAS_INT3_STATUS_VBUS_SHIFT                           7
1990 #define PALMAS_INT3_STATUS_VBUS_OTG                             0x40
1991 #define PALMAS_INT3_STATUS_VBUS_OTG_SHIFT                       6
1992 #define PALMAS_INT3_STATUS_ID                                   0x20
1993 #define PALMAS_INT3_STATUS_ID_SHIFT                             5
1994 #define PALMAS_INT3_STATUS_ID_OTG                               0x10
1995 #define PALMAS_INT3_STATUS_ID_OTG_SHIFT                         4
1996 #define PALMAS_INT3_STATUS_GPADC_EOC_RT                         0x08
1997 #define PALMAS_INT3_STATUS_GPADC_EOC_RT_SHIFT                   3
1998 #define PALMAS_INT3_STATUS_GPADC_EOC_SW                         0x04
1999 #define PALMAS_INT3_STATUS_GPADC_EOC_SW_SHIFT                   2
2000 #define PALMAS_INT3_STATUS_GPADC_AUTO_1                         0x02
2001 #define PALMAS_INT3_STATUS_GPADC_AUTO_1_SHIFT                   1
2002 #define PALMAS_INT3_STATUS_GPADC_AUTO_0                         0x01
2003 #define PALMAS_INT3_STATUS_GPADC_AUTO_0_SHIFT                   0
2004
2005 /* Bit definitions for INT3_MASK */
2006 #define PALMAS_INT3_MASK_VBUS                                   0x80
2007 #define PALMAS_INT3_MASK_VBUS_SHIFT                             7
2008 #define PALMAS_INT3_MASK_VBUS_OTG                               0x40
2009 #define PALMAS_INT3_MASK_VBUS_OTG_SHIFT                         6
2010 #define PALMAS_INT3_MASK_ID                                     0x20
2011 #define PALMAS_INT3_MASK_ID_SHIFT                               5
2012 #define PALMAS_INT3_MASK_ID_OTG                                 0x10
2013 #define PALMAS_INT3_MASK_ID_OTG_SHIFT                           4
2014 #define PALMAS_INT3_MASK_GPADC_EOC_RT                           0x08
2015 #define PALMAS_INT3_MASK_GPADC_EOC_RT_SHIFT                     3
2016 #define PALMAS_INT3_MASK_GPADC_EOC_SW                           0x04
2017 #define PALMAS_INT3_MASK_GPADC_EOC_SW_SHIFT                     2
2018 #define PALMAS_INT3_MASK_GPADC_AUTO_1                           0x02
2019 #define PALMAS_INT3_MASK_GPADC_AUTO_1_SHIFT                     1
2020 #define PALMAS_INT3_MASK_GPADC_AUTO_0                           0x01
2021 #define PALMAS_INT3_MASK_GPADC_AUTO_0_SHIFT                     0
2022
2023 /* Bit definitions for INT3_LINE_STATE */
2024 #define PALMAS_INT3_LINE_STATE_VBUS                             0x80
2025 #define PALMAS_INT3_LINE_STATE_VBUS_SHIFT                       7
2026 #define PALMAS_INT3_LINE_STATE_VBUS_OTG                         0x40
2027 #define PALMAS_INT3_LINE_STATE_VBUS_OTG_SHIFT                   6
2028 #define PALMAS_INT3_LINE_STATE_ID                               0x20
2029 #define PALMAS_INT3_LINE_STATE_ID_SHIFT                         5
2030 #define PALMAS_INT3_LINE_STATE_ID_OTG                           0x10
2031 #define PALMAS_INT3_LINE_STATE_ID_OTG_SHIFT                     4
2032 #define PALMAS_INT3_LINE_STATE_GPADC_EOC_RT                     0x08
2033 #define PALMAS_INT3_LINE_STATE_GPADC_EOC_RT_SHIFT               3
2034 #define PALMAS_INT3_LINE_STATE_GPADC_EOC_SW                     0x04
2035 #define PALMAS_INT3_LINE_STATE_GPADC_EOC_SW_SHIFT               2
2036 #define PALMAS_INT3_LINE_STATE_GPADC_AUTO_1                     0x02
2037 #define PALMAS_INT3_LINE_STATE_GPADC_AUTO_1_SHIFT               1
2038 #define PALMAS_INT3_LINE_STATE_GPADC_AUTO_0                     0x01
2039 #define PALMAS_INT3_LINE_STATE_GPADC_AUTO_0_SHIFT               0
2040
2041 /* Bit definitions for INT4_STATUS */
2042 #define PALMAS_INT4_STATUS_GPIO_7                               0x80
2043 #define PALMAS_INT4_STATUS_GPIO_7_SHIFT                         7
2044 #define PALMAS_INT4_STATUS_GPIO_6                               0x40
2045 #define PALMAS_INT4_STATUS_GPIO_6_SHIFT                         6
2046 #define PALMAS_INT4_STATUS_GPIO_5                               0x20
2047 #define PALMAS_INT4_STATUS_GPIO_5_SHIFT                         5
2048 #define PALMAS_INT4_STATUS_GPIO_4                               0x10
2049 #define PALMAS_INT4_STATUS_GPIO_4_SHIFT                         4
2050 #define PALMAS_INT4_STATUS_GPIO_3                               0x08
2051 #define PALMAS_INT4_STATUS_GPIO_3_SHIFT                         3
2052 #define PALMAS_INT4_STATUS_GPIO_2                               0x04
2053 #define PALMAS_INT4_STATUS_GPIO_2_SHIFT                         2
2054 #define PALMAS_INT4_STATUS_GPIO_1                               0x02
2055 #define PALMAS_INT4_STATUS_GPIO_1_SHIFT                         1
2056 #define PALMAS_INT4_STATUS_GPIO_0                               0x01
2057 #define PALMAS_INT4_STATUS_GPIO_0_SHIFT                         0
2058
2059 /* Bit definitions for INT4_MASK */
2060 #define PALMAS_INT4_MASK_GPIO_7                                 0x80
2061 #define PALMAS_INT4_MASK_GPIO_7_SHIFT                           7
2062 #define PALMAS_INT4_MASK_GPIO_6                                 0x40
2063 #define PALMAS_INT4_MASK_GPIO_6_SHIFT                           6
2064 #define PALMAS_INT4_MASK_GPIO_5                                 0x20
2065 #define PALMAS_INT4_MASK_GPIO_5_SHIFT                           5
2066 #define PALMAS_INT4_MASK_GPIO_4                                 0x10
2067 #define PALMAS_INT4_MASK_GPIO_4_SHIFT                           4
2068 #define PALMAS_INT4_MASK_GPIO_3                                 0x08
2069 #define PALMAS_INT4_MASK_GPIO_3_SHIFT                           3
2070 #define PALMAS_INT4_MASK_GPIO_2                                 0x04
2071 #define PALMAS_INT4_MASK_GPIO_2_SHIFT                           2
2072 #define PALMAS_INT4_MASK_GPIO_1                                 0x02
2073 #define PALMAS_INT4_MASK_GPIO_1_SHIFT                           1
2074 #define PALMAS_INT4_MASK_GPIO_0                                 0x01
2075 #define PALMAS_INT4_MASK_GPIO_0_SHIFT                           0
2076
2077 /* Bit definitions for INT4_LINE_STATE */
2078 #define PALMAS_INT4_LINE_STATE_GPIO_7                           0x80
2079 #define PALMAS_INT4_LINE_STATE_GPIO_7_SHIFT                     7
2080 #define PALMAS_INT4_LINE_STATE_GPIO_6                           0x40
2081 #define PALMAS_INT4_LINE_STATE_GPIO_6_SHIFT                     6
2082 #define PALMAS_INT4_LINE_STATE_GPIO_5                           0x20
2083 #define PALMAS_INT4_LINE_STATE_GPIO_5_SHIFT                     5
2084 #define PALMAS_INT4_LINE_STATE_GPIO_4                           0x10
2085 #define PALMAS_INT4_LINE_STATE_GPIO_4_SHIFT                     4
2086 #define PALMAS_INT4_LINE_STATE_GPIO_3                           0x08
2087 #define PALMAS_INT4_LINE_STATE_GPIO_3_SHIFT                     3
2088 #define PALMAS_INT4_LINE_STATE_GPIO_2                           0x04
2089 #define PALMAS_INT4_LINE_STATE_GPIO_2_SHIFT                     2
2090 #define PALMAS_INT4_LINE_STATE_GPIO_1                           0x02
2091 #define PALMAS_INT4_LINE_STATE_GPIO_1_SHIFT                     1
2092 #define PALMAS_INT4_LINE_STATE_GPIO_0                           0x01
2093 #define PALMAS_INT4_LINE_STATE_GPIO_0_SHIFT                     0
2094
2095 /* Bit definitions for INT4_EDGE_DETECT1 */
2096 #define PALMAS_INT4_EDGE_DETECT1_GPIO_3_RISING                  0x80
2097 #define PALMAS_INT4_EDGE_DETECT1_GPIO_3_RISING_SHIFT            7
2098 #define PALMAS_INT4_EDGE_DETECT1_GPIO_3_FALLING                 0x40
2099 #define PALMAS_INT4_EDGE_DETECT1_GPIO_3_FALLING_SHIFT           6
2100 #define PALMAS_INT4_EDGE_DETECT1_GPIO_2_RISING                  0x20
2101 #define PALMAS_INT4_EDGE_DETECT1_GPIO_2_RISING_SHIFT            5
2102 #define PALMAS_INT4_EDGE_DETECT1_GPIO_2_FALLING                 0x10
2103 #define PALMAS_INT4_EDGE_DETECT1_GPIO_2_FALLING_SHIFT           4
2104 #define PALMAS_INT4_EDGE_DETECT1_GPIO_1_RISING                  0x08
2105 #define PALMAS_INT4_EDGE_DETECT1_GPIO_1_RISING_SHIFT            3
2106 #define PALMAS_INT4_EDGE_DETECT1_GPIO_1_FALLING                 0x04
2107 #define PALMAS_INT4_EDGE_DETECT1_GPIO_1_FALLING_SHIFT           2
2108 #define PALMAS_INT4_EDGE_DETECT1_GPIO_0_RISING                  0x02
2109 #define PALMAS_INT4_EDGE_DETECT1_GPIO_0_RISING_SHIFT            1
2110 #define PALMAS_INT4_EDGE_DETECT1_GPIO_0_FALLING                 0x01
2111 #define PALMAS_INT4_EDGE_DETECT1_GPIO_0_FALLING_SHIFT           0
2112
2113 /* Bit definitions for INT4_EDGE_DETECT2 */
2114 #define PALMAS_INT4_EDGE_DETECT2_GPIO_7_RISING                  0x80
2115 #define PALMAS_INT4_EDGE_DETECT2_GPIO_7_RISING_SHIFT            7
2116 #define PALMAS_INT4_EDGE_DETECT2_GPIO_7_FALLING                 0x40
2117 #define PALMAS_INT4_EDGE_DETECT2_GPIO_7_FALLING_SHIFT           6
2118 #define PALMAS_INT4_EDGE_DETECT2_GPIO_6_RISING                  0x20
2119 #define PALMAS_INT4_EDGE_DETECT2_GPIO_6_RISING_SHIFT            5
2120 #define PALMAS_INT4_EDGE_DETECT2_GPIO_6_FALLING                 0x10
2121 #define PALMAS_INT4_EDGE_DETECT2_GPIO_6_FALLING_SHIFT           4
2122 #define PALMAS_INT4_EDGE_DETECT2_GPIO_5_RISING                  0x08
2123 #define PALMAS_INT4_EDGE_DETECT2_GPIO_5_RISING_SHIFT            3
2124 #define PALMAS_INT4_EDGE_DETECT2_GPIO_5_FALLING                 0x04
2125 #define PALMAS_INT4_EDGE_DETECT2_GPIO_5_FALLING_SHIFT           2
2126 #define PALMAS_INT4_EDGE_DETECT2_GPIO_4_RISING                  0x02
2127 #define PALMAS_INT4_EDGE_DETECT2_GPIO_4_RISING_SHIFT            1
2128 #define PALMAS_INT4_EDGE_DETECT2_GPIO_4_FALLING                 0x01
2129 #define PALMAS_INT4_EDGE_DETECT2_GPIO_4_FALLING_SHIFT           0
2130
2131 /* Bit definitions for INT_CTRL */
2132 #define PALMAS_INT_CTRL_INT_PENDING                             0x04
2133 #define PALMAS_INT_CTRL_INT_PENDING_SHIFT                       2
2134 #define PALMAS_INT_CTRL_INT_CLEAR                               0x01
2135 #define PALMAS_INT_CTRL_INT_CLEAR_SHIFT                         0
2136
2137 /* Registers for function USB_OTG */
2138 #define PALMAS_USB_WAKEUP                                       0x3
2139 #define PALMAS_USB_VBUS_CTRL_SET                                0x4
2140 #define PALMAS_USB_VBUS_CTRL_CLR                                0x5
2141 #define PALMAS_USB_ID_CTRL_SET                                  0x6
2142 #define PALMAS_USB_ID_CTRL_CLEAR                                0x7
2143 #define PALMAS_USB_VBUS_INT_SRC                                 0x8
2144 #define PALMAS_USB_VBUS_INT_LATCH_SET                           0x9
2145 #define PALMAS_USB_VBUS_INT_LATCH_CLR                           0xA
2146 #define PALMAS_USB_VBUS_INT_EN_LO_SET                           0xB
2147 #define PALMAS_USB_VBUS_INT_EN_LO_CLR                           0xC
2148 #define PALMAS_USB_VBUS_INT_EN_HI_SET                           0xD
2149 #define PALMAS_USB_VBUS_INT_EN_HI_CLR                           0xE
2150 #define PALMAS_USB_ID_INT_SRC                                   0xF
2151 #define PALMAS_USB_ID_INT_LATCH_SET                             0x10
2152 #define PALMAS_USB_ID_INT_LATCH_CLR                             0x11
2153 #define PALMAS_USB_ID_INT_EN_LO_SET                             0x12
2154 #define PALMAS_USB_ID_INT_EN_LO_CLR                             0x13
2155 #define PALMAS_USB_ID_INT_EN_HI_SET                             0x14
2156 #define PALMAS_USB_ID_INT_EN_HI_CLR                             0x15
2157 #define PALMAS_USB_OTG_ADP_CTRL                                 0x16
2158 #define PALMAS_USB_OTG_ADP_HIGH                                 0x17
2159 #define PALMAS_USB_OTG_ADP_LOW                                  0x18
2160 #define PALMAS_USB_OTG_ADP_RISE                                 0x19
2161 #define PALMAS_USB_OTG_REVISION                                 0x1A
2162
2163 /* Bit definitions for USB_WAKEUP */
2164 #define PALMAS_USB_WAKEUP_ID_WK_UP_COMP                         0x01
2165 #define PALMAS_USB_WAKEUP_ID_WK_UP_COMP_SHIFT                   0
2166
2167 /* Bit definitions for USB_VBUS_CTRL_SET */
2168 #define PALMAS_USB_VBUS_CTRL_SET_VBUS_CHRG_VSYS                 0x80
2169 #define PALMAS_USB_VBUS_CTRL_SET_VBUS_CHRG_VSYS_SHIFT           7
2170 #define PALMAS_USB_VBUS_CTRL_SET_VBUS_DISCHRG                   0x20
2171 #define PALMAS_USB_VBUS_CTRL_SET_VBUS_DISCHRG_SHIFT             5
2172 #define PALMAS_USB_VBUS_CTRL_SET_VBUS_IADP_SRC                  0x10
2173 #define PALMAS_USB_VBUS_CTRL_SET_VBUS_IADP_SRC_SHIFT            4
2174 #define PALMAS_USB_VBUS_CTRL_SET_VBUS_IADP_SINK                 0x08
2175 #define PALMAS_USB_VBUS_CTRL_SET_VBUS_IADP_SINK_SHIFT           3
2176 #define PALMAS_USB_VBUS_CTRL_SET_VBUS_ACT_COMP                  0x04
2177 #define PALMAS_USB_VBUS_CTRL_SET_VBUS_ACT_COMP_SHIFT            2
2178
2179 /* Bit definitions for USB_VBUS_CTRL_CLR */
2180 #define PALMAS_USB_VBUS_CTRL_CLR_VBUS_CHRG_VSYS                 0x80
2181 #define PALMAS_USB_VBUS_CTRL_CLR_VBUS_CHRG_VSYS_SHIFT           7
2182 #define PALMAS_USB_VBUS_CTRL_CLR_VBUS_DISCHRG                   0x20
2183 #define PALMAS_USB_VBUS_CTRL_CLR_VBUS_DISCHRG_SHIFT             5
2184 #define PALMAS_USB_VBUS_CTRL_CLR_VBUS_IADP_SRC                  0x10
2185 #define PALMAS_USB_VBUS_CTRL_CLR_VBUS_IADP_SRC_SHIFT            4
2186 #define PALMAS_USB_VBUS_CTRL_CLR_VBUS_IADP_SINK                 0x08
2187 #define PALMAS_USB_VBUS_CTRL_CLR_VBUS_IADP_SINK_SHIFT           3
2188 #define PALMAS_USB_VBUS_CTRL_CLR_VBUS_ACT_COMP                  0x04
2189 #define PALMAS_USB_VBUS_CTRL_CLR_VBUS_ACT_COMP_SHIFT            2
2190
2191 /* Bit definitions for USB_ID_CTRL_SET */
2192 #define PALMAS_USB_ID_CTRL_SET_ID_PU_220K                       0x80
2193 #define PALMAS_USB_ID_CTRL_SET_ID_PU_220K_SHIFT                 7
2194 #define PALMAS_USB_ID_CTRL_SET_ID_PU_100K                       0x40
2195 #define PALMAS_USB_ID_CTRL_SET_ID_PU_100K_SHIFT                 6
2196 #define PALMAS_USB_ID_CTRL_SET_ID_GND_DRV                       0x20
2197 #define PALMAS_USB_ID_CTRL_SET_ID_GND_DRV_SHIFT                 5
2198 #define PALMAS_USB_ID_CTRL_SET_ID_SRC_16U                       0x10
2199 #define PALMAS_USB_ID_CTRL_SET_ID_SRC_16U_SHIFT                 4
2200 #define PALMAS_USB_ID_CTRL_SET_ID_SRC_5U                        0x08
2201 #define PALMAS_USB_ID_CTRL_SET_ID_SRC_5U_SHIFT                  3
2202 #define PALMAS_USB_ID_CTRL_SET_ID_ACT_COMP                      0x04
2203 #define PALMAS_USB_ID_CTRL_SET_ID_ACT_COMP_SHIFT                2
2204
2205 /* Bit definitions for USB_ID_CTRL_CLEAR */
2206 #define PALMAS_USB_ID_CTRL_CLEAR_ID_PU_220K                     0x80
2207 #define PALMAS_USB_ID_CTRL_CLEAR_ID_PU_220K_SHIFT               7
2208 #define PALMAS_USB_ID_CTRL_CLEAR_ID_PU_100K                     0x40
2209 #define PALMAS_USB_ID_CTRL_CLEAR_ID_PU_100K_SHIFT               6
2210 #define PALMAS_USB_ID_CTRL_CLEAR_ID_GND_DRV                     0x20
2211 #define PALMAS_USB_ID_CTRL_CLEAR_ID_GND_DRV_SHIFT               5
2212 #define PALMAS_USB_ID_CTRL_CLEAR_ID_SRC_16U                     0x10
2213 #define PALMAS_USB_ID_CTRL_CLEAR_ID_SRC_16U_SHIFT               4
2214 #define PALMAS_USB_ID_CTRL_CLEAR_ID_SRC_5U                      0x08
2215 #define PALMAS_USB_ID_CTRL_CLEAR_ID_SRC_5U_SHIFT                3
2216 #define PALMAS_USB_ID_CTRL_CLEAR_ID_ACT_COMP                    0x04
2217 #define PALMAS_USB_ID_CTRL_CLEAR_ID_ACT_COMP_SHIFT              2
2218
2219 /* Bit definitions for USB_VBUS_INT_SRC */
2220 #define PALMAS_USB_VBUS_INT_SRC_VOTG_SESS_VLD                   0x80
2221 #define PALMAS_USB_VBUS_INT_SRC_VOTG_SESS_VLD_SHIFT             7
2222 #define PALMAS_USB_VBUS_INT_SRC_VADP_PRB                        0x40
2223 #define PALMAS_USB_VBUS_INT_SRC_VADP_PRB_SHIFT                  6
2224 #define PALMAS_USB_VBUS_INT_SRC_VADP_SNS                        0x20
2225 #define PALMAS_USB_VBUS_INT_SRC_VADP_SNS_SHIFT                  5
2226 #define PALMAS_USB_VBUS_INT_SRC_VA_VBUS_VLD                     0x08
2227 #define PALMAS_USB_VBUS_INT_SRC_VA_VBUS_VLD_SHIFT               3
2228 #define PALMAS_USB_VBUS_INT_SRC_VA_SESS_VLD                     0x04
2229 #define PALMAS_USB_VBUS_INT_SRC_VA_SESS_VLD_SHIFT               2
2230 #define PALMAS_USB_VBUS_INT_SRC_VB_SESS_VLD                     0x02
2231 #define PALMAS_USB_VBUS_INT_SRC_VB_SESS_VLD_SHIFT               1
2232 #define PALMAS_USB_VBUS_INT_SRC_VB_SESS_END                     0x01
2233 #define PALMAS_USB_VBUS_INT_SRC_VB_SESS_END_SHIFT               0
2234
2235 /* Bit definitions for USB_VBUS_INT_LATCH_SET */
2236 #define PALMAS_USB_VBUS_INT_LATCH_SET_VOTG_SESS_VLD             0x80
2237 #define PALMAS_USB_VBUS_INT_LATCH_SET_VOTG_SESS_VLD_SHIFT       7
2238 #define PALMAS_USB_VBUS_INT_LATCH_SET_VADP_PRB                  0x40
2239 #define PALMAS_USB_VBUS_INT_LATCH_SET_VADP_PRB_SHIFT            6
2240 #define PALMAS_USB_VBUS_INT_LATCH_SET_VADP_SNS                  0x20
2241 #define PALMAS_USB_VBUS_INT_LATCH_SET_VADP_SNS_SHIFT            5
2242 #define PALMAS_USB_VBUS_INT_LATCH_SET_ADP                       0x10
2243 #define PALMAS_USB_VBUS_INT_LATCH_SET_ADP_SHIFT                 4
2244 #define PALMAS_USB_VBUS_INT_LATCH_SET_VA_VBUS_VLD               0x08
2245 #define PALMAS_USB_VBUS_INT_LATCH_SET_VA_VBUS_VLD_SHIFT         3
2246 #define PALMAS_USB_VBUS_INT_LATCH_SET_VA_SESS_VLD               0x04
2247 #define PALMAS_USB_VBUS_INT_LATCH_SET_VA_SESS_VLD_SHIFT         2
2248 #define PALMAS_USB_VBUS_INT_LATCH_SET_VB_SESS_VLD               0x02
2249 #define PALMAS_USB_VBUS_INT_LATCH_SET_VB_SESS_VLD_SHIFT         1
2250 #define PALMAS_USB_VBUS_INT_LATCH_SET_VB_SESS_END               0x01
2251 #define PALMAS_USB_VBUS_INT_LATCH_SET_VB_SESS_END_SHIFT         0
2252
2253 /* Bit definitions for USB_VBUS_INT_LATCH_CLR */
2254 #define PALMAS_USB_VBUS_INT_LATCH_CLR_VOTG_SESS_VLD             0x80
2255 #define PALMAS_USB_VBUS_INT_LATCH_CLR_VOTG_SESS_VLD_SHIFT       7
2256 #define PALMAS_USB_VBUS_INT_LATCH_CLR_VADP_PRB                  0x40
2257 #define PALMAS_USB_VBUS_INT_LATCH_CLR_VADP_PRB_SHIFT            6
2258 #define PALMAS_USB_VBUS_INT_LATCH_CLR_VADP_SNS                  0x20
2259 #define PALMAS_USB_VBUS_INT_LATCH_CLR_VADP_SNS_SHIFT            5
2260 #define PALMAS_USB_VBUS_INT_LATCH_CLR_ADP                       0x10
2261 #define PALMAS_USB_VBUS_INT_LATCH_CLR_ADP_SHIFT                 4
2262 #define PALMAS_USB_VBUS_INT_LATCH_CLR_VA_VBUS_VLD               0x08
2263 #define PALMAS_USB_VBUS_INT_LATCH_CLR_VA_VBUS_VLD_SHIFT         3
2264 #define PALMAS_USB_VBUS_INT_LATCH_CLR_VA_SESS_VLD               0x04
2265 #define PALMAS_USB_VBUS_INT_LATCH_CLR_VA_SESS_VLD_SHIFT         2
2266 #define PALMAS_USB_VBUS_INT_LATCH_CLR_VB_SESS_VLD               0x02
2267 #define PALMAS_USB_VBUS_INT_LATCH_CLR_VB_SESS_VLD_SHIFT         1
2268 #define PALMAS_USB_VBUS_INT_LATCH_CLR_VB_SESS_END               0x01
2269 #define PALMAS_USB_VBUS_INT_LATCH_CLR_VB_SESS_END_SHIFT         0
2270
2271 /* Bit definitions for USB_VBUS_INT_EN_LO_SET */
2272 #define PALMAS_USB_VBUS_INT_EN_LO_SET_VOTG_SESS_VLD             0x80
2273 #define PALMAS_USB_VBUS_INT_EN_LO_SET_VOTG_SESS_VLD_SHIFT       7
2274 #define PALMAS_USB_VBUS_INT_EN_LO_SET_VADP_PRB                  0x40
2275 #define PALMAS_USB_VBUS_INT_EN_LO_SET_VADP_PRB_SHIFT            6
2276 #define PALMAS_USB_VBUS_INT_EN_LO_SET_VADP_SNS                  0x20
2277 #define PALMAS_USB_VBUS_INT_EN_LO_SET_VADP_SNS_SHIFT            5
2278 #define PALMAS_USB_VBUS_INT_EN_LO_SET_VA_VBUS_VLD               0x08
2279 #define PALMAS_USB_VBUS_INT_EN_LO_SET_VA_VBUS_VLD_SHIFT         3
2280 #define PALMAS_USB_VBUS_INT_EN_LO_SET_VA_SESS_VLD               0x04
2281 #define PALMAS_USB_VBUS_INT_EN_LO_SET_VA_SESS_VLD_SHIFT         2
2282 #define PALMAS_USB_VBUS_INT_EN_LO_SET_VB_SESS_VLD               0x02
2283 #define PALMAS_USB_VBUS_INT_EN_LO_SET_VB_SESS_VLD_SHIFT         1
2284 #define PALMAS_USB_VBUS_INT_EN_LO_SET_VB_SESS_END               0x01
2285 #define PALMAS_USB_VBUS_INT_EN_LO_SET_VB_SESS_END_SHIFT         0
2286
2287 /* Bit definitions for USB_VBUS_INT_EN_LO_CLR */
2288 #define PALMAS_USB_VBUS_INT_EN_LO_CLR_VOTG_SESS_VLD             0x80
2289 #define PALMAS_USB_VBUS_INT_EN_LO_CLR_VOTG_SESS_VLD_SHIFT       7
2290 #define PALMAS_USB_VBUS_INT_EN_LO_CLR_VADP_PRB                  0x40
2291 #define PALMAS_USB_VBUS_INT_EN_LO_CLR_VADP_PRB_SHIFT            6
2292 #define PALMAS_USB_VBUS_INT_EN_LO_CLR_VADP_SNS                  0x20
2293 #define PALMAS_USB_VBUS_INT_EN_LO_CLR_VADP_SNS_SHIFT            5
2294 #define PALMAS_USB_VBUS_INT_EN_LO_CLR_VA_VBUS_VLD               0x08
2295 #define PALMAS_USB_VBUS_INT_EN_LO_CLR_VA_VBUS_VLD_SHIFT         3
2296 #define PALMAS_USB_VBUS_INT_EN_LO_CLR_VA_SESS_VLD               0x04
2297 #define PALMAS_USB_VBUS_INT_EN_LO_CLR_VA_SESS_VLD_SHIFT         2
2298 #define PALMAS_USB_VBUS_INT_EN_LO_CLR_VB_SESS_VLD               0x02
2299 #define PALMAS_USB_VBUS_INT_EN_LO_CLR_VB_SESS_VLD_SHIFT         1
2300 #define PALMAS_USB_VBUS_INT_EN_LO_CLR_VB_SESS_END               0x01
2301 #define PALMAS_USB_VBUS_INT_EN_LO_CLR_VB_SESS_END_SHIFT         0
2302
2303 /* Bit definitions for USB_VBUS_INT_EN_HI_SET */
2304 #define PALMAS_USB_VBUS_INT_EN_HI_SET_VOTG_SESS_VLD             0x80
2305 #define PALMAS_USB_VBUS_INT_EN_HI_SET_VOTG_SESS_VLD_SHIFT       7
2306 #define PALMAS_USB_VBUS_INT_EN_HI_SET_VADP_PRB                  0x40
2307 #define PALMAS_USB_VBUS_INT_EN_HI_SET_VADP_PRB_SHIFT            6
2308 #define PALMAS_USB_VBUS_INT_EN_HI_SET_VADP_SNS                  0x20
2309 #define PALMAS_USB_VBUS_INT_EN_HI_SET_VADP_SNS_SHIFT            5
2310 #define PALMAS_USB_VBUS_INT_EN_HI_SET_ADP                       0x10
2311 #define PALMAS_USB_VBUS_INT_EN_HI_SET_ADP_SHIFT                 4
2312 #define PALMAS_USB_VBUS_INT_EN_HI_SET_VA_VBUS_VLD               0x08
2313 #define PALMAS_USB_VBUS_INT_EN_HI_SET_VA_VBUS_VLD_SHIFT         3
2314 #define PALMAS_USB_VBUS_INT_EN_HI_SET_VA_SESS_VLD               0x04
2315 #define PALMAS_USB_VBUS_INT_EN_HI_SET_VA_SESS_VLD_SHIFT         2
2316 #define PALMAS_USB_VBUS_INT_EN_HI_SET_VB_SESS_VLD               0x02
2317 #define PALMAS_USB_VBUS_INT_EN_HI_SET_VB_SESS_VLD_SHIFT         1
2318 #define PALMAS_USB_VBUS_INT_EN_HI_SET_VB_SESS_END               0x01
2319 #define PALMAS_USB_VBUS_INT_EN_HI_SET_VB_SESS_END_SHIFT         0
2320
2321 /* Bit definitions for USB_VBUS_INT_EN_HI_CLR */
2322 #define PALMAS_USB_VBUS_INT_EN_HI_CLR_VOTG_SESS_VLD             0x80
2323 #define PALMAS_USB_VBUS_INT_EN_HI_CLR_VOTG_SESS_VLD_SHIFT       7
2324 #define PALMAS_USB_VBUS_INT_EN_HI_CLR_VADP_PRB                  0x40
2325 #define PALMAS_USB_VBUS_INT_EN_HI_CLR_VADP_PRB_SHIFT            6
2326 #define PALMAS_USB_VBUS_INT_EN_HI_CLR_VADP_SNS                  0x20
2327 #define PALMAS_USB_VBUS_INT_EN_HI_CLR_VADP_SNS_SHIFT            5
2328 #define PALMAS_USB_VBUS_INT_EN_HI_CLR_ADP                       0x10
2329 #define PALMAS_USB_VBUS_INT_EN_HI_CLR_ADP_SHIFT                 4
2330 #define PALMAS_USB_VBUS_INT_EN_HI_CLR_VA_VBUS_VLD               0x08
2331 #define PALMAS_USB_VBUS_INT_EN_HI_CLR_VA_VBUS_VLD_SHIFT         3
2332 #define PALMAS_USB_VBUS_INT_EN_HI_CLR_VA_SESS_VLD               0x04
2333 #define PALMAS_USB_VBUS_INT_EN_HI_CLR_VA_SESS_VLD_SHIFT         2
2334 #define PALMAS_USB_VBUS_INT_EN_HI_CLR_VB_SESS_VLD               0x02
2335 #define PALMAS_USB_VBUS_INT_EN_HI_CLR_VB_SESS_VLD_SHIFT         1
2336 #define PALMAS_USB_VBUS_INT_EN_HI_CLR_VB_SESS_END               0x01
2337 #define PALMAS_USB_VBUS_INT_EN_HI_CLR_VB_SESS_END_SHIFT         0
2338
2339 /* Bit definitions for USB_ID_INT_SRC */
2340 #define PALMAS_USB_ID_INT_SRC_ID_FLOAT                          0x10
2341 #define PALMAS_USB_ID_INT_SRC_ID_FLOAT_SHIFT                    4
2342 #define PALMAS_USB_ID_INT_SRC_ID_A                              0x08
2343 #define PALMAS_USB_ID_INT_SRC_ID_A_SHIFT                        3
2344 #define PALMAS_USB_ID_INT_SRC_ID_B                              0x04
2345 #define PALMAS_USB_ID_INT_SRC_ID_B_SHIFT                        2
2346 #define PALMAS_USB_ID_INT_SRC_ID_C                              0x02
2347 #define PALMAS_USB_ID_INT_SRC_ID_C_SHIFT                        1
2348 #define PALMAS_USB_ID_INT_SRC_ID_GND                            0x01
2349 #define PALMAS_USB_ID_INT_SRC_ID_GND_SHIFT                      0
2350
2351 /* Bit definitions for USB_ID_INT_LATCH_SET */
2352 #define PALMAS_USB_ID_INT_LATCH_SET_ID_FLOAT                    0x10
2353 #define PALMAS_USB_ID_INT_LATCH_SET_ID_FLOAT_SHIFT              4
2354 #define PALMAS_USB_ID_INT_LATCH_SET_ID_A                        0x08
2355 #define PALMAS_USB_ID_INT_LATCH_SET_ID_A_SHIFT                  3
2356 #define PALMAS_USB_ID_INT_LATCH_SET_ID_B                        0x04
2357 #define PALMAS_USB_ID_INT_LATCH_SET_ID_B_SHIFT                  2
2358 #define PALMAS_USB_ID_INT_LATCH_SET_ID_C                        0x02
2359 #define PALMAS_USB_ID_INT_LATCH_SET_ID_C_SHIFT                  1
2360 #define PALMAS_USB_ID_INT_LATCH_SET_ID_GND                      0x01
2361 #define PALMAS_USB_ID_INT_LATCH_SET_ID_GND_SHIFT                0
2362
2363 /* Bit definitions for USB_ID_INT_LATCH_CLR */
2364 #define PALMAS_USB_ID_INT_LATCH_CLR_ID_FLOAT                    0x10
2365 #define PALMAS_USB_ID_INT_LATCH_CLR_ID_FLOAT_SHIFT              4
2366 #define PALMAS_USB_ID_INT_LATCH_CLR_ID_A                        0x08
2367 #define PALMAS_USB_ID_INT_LATCH_CLR_ID_A_SHIFT                  3
2368 #define PALMAS_USB_ID_INT_LATCH_CLR_ID_B                        0x04
2369 #define PALMAS_USB_ID_INT_LATCH_CLR_ID_B_SHIFT                  2
2370 #define PALMAS_USB_ID_INT_LATCH_CLR_ID_C                        0x02
2371 #define PALMAS_USB_ID_INT_LATCH_CLR_ID_C_SHIFT                  1
2372 #define PALMAS_USB_ID_INT_LATCH_CLR_ID_GND                      0x01
2373 #define PALMAS_USB_ID_INT_LATCH_CLR_ID_GND_SHIFT                0
2374
2375 /* Bit definitions for USB_ID_INT_EN_LO_SET */
2376 #define PALMAS_USB_ID_INT_EN_LO_SET_ID_FLOAT                    0x10
2377 #define PALMAS_USB_ID_INT_EN_LO_SET_ID_FLOAT_SHIFT              4
2378 #define PALMAS_USB_ID_INT_EN_LO_SET_ID_A                        0x08
2379 #define PALMAS_USB_ID_INT_EN_LO_SET_ID_A_SHIFT                  3
2380 #define PALMAS_USB_ID_INT_EN_LO_SET_ID_B                        0x04
2381 #define PALMAS_USB_ID_INT_EN_LO_SET_ID_B_SHIFT                  2
2382 #define PALMAS_USB_ID_INT_EN_LO_SET_ID_C                        0x02
2383 #define PALMAS_USB_ID_INT_EN_LO_SET_ID_C_SHIFT                  1
2384 #define PALMAS_USB_ID_INT_EN_LO_SET_ID_GND                      0x01
2385 #define PALMAS_USB_ID_INT_EN_LO_SET_ID_GND_SHIFT                0
2386
2387 /* Bit definitions for USB_ID_INT_EN_LO_CLR */
2388 #define PALMAS_USB_ID_INT_EN_LO_CLR_ID_FLOAT                    0x10
2389 #define PALMAS_USB_ID_INT_EN_LO_CLR_ID_FLOAT_SHIFT              4
2390 #define PALMAS_USB_ID_INT_EN_LO_CLR_ID_A                        0x08
2391 #define PALMAS_USB_ID_INT_EN_LO_CLR_ID_A_SHIFT                  3
2392 #define PALMAS_USB_ID_INT_EN_LO_CLR_ID_B                        0x04
2393 #define PALMAS_USB_ID_INT_EN_LO_CLR_ID_B_SHIFT                  2
2394 #define PALMAS_USB_ID_INT_EN_LO_CLR_ID_C                        0x02
2395 #define PALMAS_USB_ID_INT_EN_LO_CLR_ID_C_SHIFT                  1
2396 #define PALMAS_USB_ID_INT_EN_LO_CLR_ID_GND                      0x01
2397 #define PALMAS_USB_ID_INT_EN_LO_CLR_ID_GND_SHIFT                0
2398
2399 /* Bit definitions for USB_ID_INT_EN_HI_SET */
2400 #define PALMAS_USB_ID_INT_EN_HI_SET_ID_FLOAT                    0x10
2401 #define PALMAS_USB_ID_INT_EN_HI_SET_ID_FLOAT_SHIFT              4
2402 #define PALMAS_USB_ID_INT_EN_HI_SET_ID_A                        0x08
2403 #define PALMAS_USB_ID_INT_EN_HI_SET_ID_A_SHIFT                  3
2404 #define PALMAS_USB_ID_INT_EN_HI_SET_ID_B                        0x04
2405 #define PALMAS_USB_ID_INT_EN_HI_SET_ID_B_SHIFT                  2
2406 #define PALMAS_USB_ID_INT_EN_HI_SET_ID_C                        0x02
2407 #define PALMAS_USB_ID_INT_EN_HI_SET_ID_C_SHIFT                  1
2408 #define PALMAS_USB_ID_INT_EN_HI_SET_ID_GND                      0x01
2409 #define PALMAS_USB_ID_INT_EN_HI_SET_ID_GND_SHIFT                0
2410
2411 /* Bit definitions for USB_ID_INT_EN_HI_CLR */
2412 #define PALMAS_USB_ID_INT_EN_HI_CLR_ID_FLOAT                    0x10
2413 #define PALMAS_USB_ID_INT_EN_HI_CLR_ID_FLOAT_SHIFT              4
2414 #define PALMAS_USB_ID_INT_EN_HI_CLR_ID_A                        0x08
2415 #define PALMAS_USB_ID_INT_EN_HI_CLR_ID_A_SHIFT                  3
2416 #define PALMAS_USB_ID_INT_EN_HI_CLR_ID_B                        0x04
2417 #define PALMAS_USB_ID_INT_EN_HI_CLR_ID_B_SHIFT                  2
2418 #define PALMAS_USB_ID_INT_EN_HI_CLR_ID_C                        0x02
2419 #define PALMAS_USB_ID_INT_EN_HI_CLR_ID_C_SHIFT                  1
2420 #define PALMAS_USB_ID_INT_EN_HI_CLR_ID_GND                      0x01
2421 #define PALMAS_USB_ID_INT_EN_HI_CLR_ID_GND_SHIFT                0
2422
2423 /* Bit definitions for USB_OTG_ADP_CTRL */
2424 #define PALMAS_USB_OTG_ADP_CTRL_ADP_EN                          0x04
2425 #define PALMAS_USB_OTG_ADP_CTRL_ADP_EN_SHIFT                    2
2426 #define PALMAS_USB_OTG_ADP_CTRL_ADP_MODE_MASK                   0x03
2427 #define PALMAS_USB_OTG_ADP_CTRL_ADP_MODE_SHIFT                  0
2428
2429 /* Bit definitions for USB_OTG_ADP_HIGH */
2430 #define PALMAS_USB_OTG_ADP_HIGH_T_ADP_HIGH_MASK                 0xff
2431 #define PALMAS_USB_OTG_ADP_HIGH_T_ADP_HIGH_SHIFT                0
2432
2433 /* Bit definitions for USB_OTG_ADP_LOW */
2434 #define PALMAS_USB_OTG_ADP_LOW_T_ADP_LOW_MASK                   0xff
2435 #define PALMAS_USB_OTG_ADP_LOW_T_ADP_LOW_SHIFT                  0
2436
2437 /* Bit definitions for USB_OTG_ADP_RISE */
2438 #define PALMAS_USB_OTG_ADP_RISE_T_ADP_RISE_MASK                 0xff
2439 #define PALMAS_USB_OTG_ADP_RISE_T_ADP_RISE_SHIFT                0
2440
2441 /* Bit definitions for USB_OTG_REVISION */
2442 #define PALMAS_USB_OTG_REVISION_OTG_REV                         0x01
2443 #define PALMAS_USB_OTG_REVISION_OTG_REV_SHIFT                   0
2444
2445 /* Registers for function VIBRATOR */
2446 #define PALMAS_VIBRA_CTRL                                       0x0
2447
2448 /* Bit definitions for VIBRA_CTRL */
2449 #define PALMAS_VIBRA_CTRL_PWM_DUTY_SEL_MASK                     0x06
2450 #define PALMAS_VIBRA_CTRL_PWM_DUTY_SEL_SHIFT                    1
2451 #define PALMAS_VIBRA_CTRL_PWM_FREQ_SEL                          0x01
2452 #define PALMAS_VIBRA_CTRL_PWM_FREQ_SEL_SHIFT                    0
2453
2454 /* Registers for function GPIO */
2455 #define PALMAS_GPIO_DATA_IN                                     0x0
2456 #define PALMAS_GPIO_DATA_DIR                                    0x1
2457 #define PALMAS_GPIO_DATA_OUT                                    0x2
2458 #define PALMAS_GPIO_DEBOUNCE_EN                                 0x3
2459 #define PALMAS_GPIO_CLEAR_DATA_OUT                              0x4
2460 #define PALMAS_GPIO_SET_DATA_OUT                                0x5
2461 #define PALMAS_PU_PD_GPIO_CTRL1                                 0x6
2462 #define PALMAS_PU_PD_GPIO_CTRL2                                 0x7
2463 #define PALMAS_OD_OUTPUT_GPIO_CTRL                              0x8
2464
2465 /* Bit definitions for GPIO_DATA_IN */
2466 #define PALMAS_GPIO_DATA_IN_GPIO_7_IN                           0x80
2467 #define PALMAS_GPIO_DATA_IN_GPIO_7_IN_SHIFT                     7
2468 #define PALMAS_GPIO_DATA_IN_GPIO_6_IN                           0x40
2469 #define PALMAS_GPIO_DATA_IN_GPIO_6_IN_SHIFT                     6
2470 #define PALMAS_GPIO_DATA_IN_GPIO_5_IN                           0x20
2471 #define PALMAS_GPIO_DATA_IN_GPIO_5_IN_SHIFT                     5
2472 #define PALMAS_GPIO_DATA_IN_GPIO_4_IN                           0x10
2473 #define PALMAS_GPIO_DATA_IN_GPIO_4_IN_SHIFT                     4
2474 #define PALMAS_GPIO_DATA_IN_GPIO_3_IN                           0x08
2475 #define PALMAS_GPIO_DATA_IN_GPIO_3_IN_SHIFT                     3
2476 #define PALMAS_GPIO_DATA_IN_GPIO_2_IN                           0x04
2477 #define PALMAS_GPIO_DATA_IN_GPIO_2_IN_SHIFT                     2
2478 #define PALMAS_GPIO_DATA_IN_GPIO_1_IN                           0x02
2479 #define PALMAS_GPIO_DATA_IN_GPIO_1_IN_SHIFT                     1
2480 #define PALMAS_GPIO_DATA_IN_GPIO_0_IN                           0x01
2481 #define PALMAS_GPIO_DATA_IN_GPIO_0_IN_SHIFT                     0
2482
2483 /* Bit definitions for GPIO_DATA_DIR */
2484 #define PALMAS_GPIO_DATA_DIR_GPIO_7_DIR                         0x80
2485 #define PALMAS_GPIO_DATA_DIR_GPIO_7_DIR_SHIFT                   7
2486 #define PALMAS_GPIO_DATA_DIR_GPIO_6_DIR                         0x40
2487 #define PALMAS_GPIO_DATA_DIR_GPIO_6_DIR_SHIFT                   6
2488 #define PALMAS_GPIO_DATA_DIR_GPIO_5_DIR                         0x20
2489 #define PALMAS_GPIO_DATA_DIR_GPIO_5_DIR_SHIFT                   5
2490 #define PALMAS_GPIO_DATA_DIR_GPIO_4_DIR                         0x10
2491 #define PALMAS_GPIO_DATA_DIR_GPIO_4_DIR_SHIFT                   4
2492 #define PALMAS_GPIO_DATA_DIR_GPIO_3_DIR                         0x08
2493 #define PALMAS_GPIO_DATA_DIR_GPIO_3_DIR_SHIFT                   3
2494 #define PALMAS_GPIO_DATA_DIR_GPIO_2_DIR                         0x04
2495 #define PALMAS_GPIO_DATA_DIR_GPIO_2_DIR_SHIFT                   2
2496 #define PALMAS_GPIO_DATA_DIR_GPIO_1_DIR                         0x02
2497 #define PALMAS_GPIO_DATA_DIR_GPIO_1_DIR_SHIFT                   1
2498 #define PALMAS_GPIO_DATA_DIR_GPIO_0_DIR                         0x01
2499 #define PALMAS_GPIO_DATA_DIR_GPIO_0_DIR_SHIFT                   0
2500
2501 /* Bit definitions for GPIO_DATA_OUT */
2502 #define PALMAS_GPIO_DATA_OUT_GPIO_7_OUT                         0x80
2503 #define PALMAS_GPIO_DATA_OUT_GPIO_7_OUT_SHIFT                   7
2504 #define PALMAS_GPIO_DATA_OUT_GPIO_6_OUT                         0x40
2505 #define PALMAS_GPIO_DATA_OUT_GPIO_6_OUT_SHIFT                   6
2506 #define PALMAS_GPIO_DATA_OUT_GPIO_5_OUT                         0x20
2507 #define PALMAS_GPIO_DATA_OUT_GPIO_5_OUT_SHIFT                   5
2508 #define PALMAS_GPIO_DATA_OUT_GPIO_4_OUT                         0x10
2509 #define PALMAS_GPIO_DATA_OUT_GPIO_4_OUT_SHIFT                   4
2510 #define PALMAS_GPIO_DATA_OUT_GPIO_3_OUT                         0x08
2511 #define PALMAS_GPIO_DATA_OUT_GPIO_3_OUT_SHIFT                   3
2512 #define PALMAS_GPIO_DATA_OUT_GPIO_2_OUT                         0x04
2513 #define PALMAS_GPIO_DATA_OUT_GPIO_2_OUT_SHIFT                   2
2514 #define PALMAS_GPIO_DATA_OUT_GPIO_1_OUT                         0x02
2515 #define PALMAS_GPIO_DATA_OUT_GPIO_1_OUT_SHIFT                   1
2516 #define PALMAS_GPIO_DATA_OUT_GPIO_0_OUT                         0x01
2517 #define PALMAS_GPIO_DATA_OUT_GPIO_0_OUT_SHIFT                   0
2518
2519 /* Bit definitions for GPIO_DEBOUNCE_EN */
2520 #define PALMAS_GPIO_DEBOUNCE_EN_GPIO_7_DEBOUNCE_EN              0x80
2521 #define PALMAS_GPIO_DEBOUNCE_EN_GPIO_7_DEBOUNCE_EN_SHIFT        7
2522 #define PALMAS_GPIO_DEBOUNCE_EN_GPIO_6_DEBOUNCE_EN              0x40
2523 #define PALMAS_GPIO_DEBOUNCE_EN_GPIO_6_DEBOUNCE_EN_SHIFT        6
2524 #define PALMAS_GPIO_DEBOUNCE_EN_GPIO_5_DEBOUNCE_EN              0x20
2525 #define PALMAS_GPIO_DEBOUNCE_EN_GPIO_5_DEBOUNCE_EN_SHIFT        5
2526 #define PALMAS_GPIO_DEBOUNCE_EN_GPIO_4_DEBOUNCE_EN              0x10
2527 #define PALMAS_GPIO_DEBOUNCE_EN_GPIO_4_DEBOUNCE_EN_SHIFT        4
2528 #define PALMAS_GPIO_DEBOUNCE_EN_GPIO_3_DEBOUNCE_EN              0x08
2529 #define PALMAS_GPIO_DEBOUNCE_EN_GPIO_3_DEBOUNCE_EN_SHIFT        3
2530 #define PALMAS_GPIO_DEBOUNCE_EN_GPIO_2_DEBOUNCE_EN              0x04
2531 #define PALMAS_GPIO_DEBOUNCE_EN_GPIO_2_DEBOUNCE_EN_SHIFT        2
2532 #define PALMAS_GPIO_DEBOUNCE_EN_GPIO_1_DEBOUNCE_EN              0x02
2533 #define PALMAS_GPIO_DEBOUNCE_EN_GPIO_1_DEBOUNCE_EN_SHIFT        1
2534 #define PALMAS_GPIO_DEBOUNCE_EN_GPIO_0_DEBOUNCE_EN              0x01
2535 #define PALMAS_GPIO_DEBOUNCE_EN_GPIO_0_DEBOUNCE_EN_SHIFT        0
2536
2537 /* Bit definitions for GPIO_CLEAR_DATA_OUT */
2538 #define PALMAS_GPIO_CLEAR_DATA_OUT_GPIO_7_CLEAR_DATA_OUT        0x80
2539 #define PALMAS_GPIO_CLEAR_DATA_OUT_GPIO_7_CLEAR_DATA_OUT_SHIFT  7
2540 #define PALMAS_GPIO_CLEAR_DATA_OUT_GPIO_6_CLEAR_DATA_OUT        0x40
2541 #define PALMAS_GPIO_CLEAR_DATA_OUT_GPIO_6_CLEAR_DATA_OUT_SHIFT  6
2542 #define PALMAS_GPIO_CLEAR_DATA_OUT_GPIO_5_CLEAR_DATA_OUT        0x20
2543 #define PALMAS_GPIO_CLEAR_DATA_OUT_GPIO_5_CLEAR_DATA_OUT_SHIFT  5
2544 #define PALMAS_GPIO_CLEAR_DATA_OUT_GPIO_4_CLEAR_DATA_OUT        0x10
2545 #define PALMAS_GPIO_CLEAR_DATA_OUT_GPIO_4_CLEAR_DATA_OUT_SHIFT  4
2546 #define PALMAS_GPIO_CLEAR_DATA_OUT_GPIO_3_CLEAR_DATA_OUT        0x08
2547 #define PALMAS_GPIO_CLEAR_DATA_OUT_GPIO_3_CLEAR_DATA_OUT_SHIFT  3
2548 #define PALMAS_GPIO_CLEAR_DATA_OUT_GPIO_2_CLEAR_DATA_OUT        0x04
2549 #define PALMAS_GPIO_CLEAR_DATA_OUT_GPIO_2_CLEAR_DATA_OUT_SHIFT  2
2550 #define PALMAS_GPIO_CLEAR_DATA_OUT_GPIO_1_CLEAR_DATA_OUT        0x02
2551 #define PALMAS_GPIO_CLEAR_DATA_OUT_GPIO_1_CLEAR_DATA_OUT_SHIFT  1
2552 #define PALMAS_GPIO_CLEAR_DATA_OUT_GPIO_0_CLEAR_DATA_OUT        0x01
2553 #define PALMAS_GPIO_CLEAR_DATA_OUT_GPIO_0_CLEAR_DATA_OUT_SHIFT  0
2554
2555 /* Bit definitions for GPIO_SET_DATA_OUT */
2556 #define PALMAS_GPIO_SET_DATA_OUT_GPIO_7_SET_DATA_OUT            0x80
2557 #define PALMAS_GPIO_SET_DATA_OUT_GPIO_7_SET_DATA_OUT_SHIFT      7
2558 #define PALMAS_GPIO_SET_DATA_OUT_GPIO_6_SET_DATA_OUT            0x40
2559 #define PALMAS_GPIO_SET_DATA_OUT_GPIO_6_SET_DATA_OUT_SHIFT      6
2560 #define PALMAS_GPIO_SET_DATA_OUT_GPIO_5_SET_DATA_OUT            0x20
2561 #define PALMAS_GPIO_SET_DATA_OUT_GPIO_5_SET_DATA_OUT_SHIFT      5
2562 #define PALMAS_GPIO_SET_DATA_OUT_GPIO_4_SET_DATA_OUT            0x10
2563 #define PALMAS_GPIO_SET_DATA_OUT_GPIO_4_SET_DATA_OUT_SHIFT      4
2564 #define PALMAS_GPIO_SET_DATA_OUT_GPIO_3_SET_DATA_OUT            0x08
2565 #define PALMAS_GPIO_SET_DATA_OUT_GPIO_3_SET_DATA_OUT_SHIFT      3
2566 #define PALMAS_GPIO_SET_DATA_OUT_GPIO_2_SET_DATA_OUT            0x04
2567 #define PALMAS_GPIO_SET_DATA_OUT_GPIO_2_SET_DATA_OUT_SHIFT      2
2568 #define PALMAS_GPIO_SET_DATA_OUT_GPIO_1_SET_DATA_OUT            0x02
2569 #define PALMAS_GPIO_SET_DATA_OUT_GPIO_1_SET_DATA_OUT_SHIFT      1
2570 #define PALMAS_GPIO_SET_DATA_OUT_GPIO_0_SET_DATA_OUT            0x01
2571 #define PALMAS_GPIO_SET_DATA_OUT_GPIO_0_SET_DATA_OUT_SHIFT      0
2572
2573 /* Bit definitions for PU_PD_GPIO_CTRL1 */
2574 #define PALMAS_PU_PD_GPIO_CTRL1_GPIO_3_PD                       0x40
2575 #define PALMAS_PU_PD_GPIO_CTRL1_GPIO_3_PD_SHIFT                 6
2576 #define PALMAS_PU_PD_GPIO_CTRL1_GPIO_2_PU                       0x20
2577 #define PALMAS_PU_PD_GPIO_CTRL1_GPIO_2_PU_SHIFT                 5
2578 #define PALMAS_PU_PD_GPIO_CTRL1_GPIO_2_PD                       0x10
2579 #define PALMAS_PU_PD_GPIO_CTRL1_GPIO_2_PD_SHIFT                 4
2580 #define PALMAS_PU_PD_GPIO_CTRL1_GPIO_1_PU                       0x08
2581 #define PALMAS_PU_PD_GPIO_CTRL1_GPIO_1_PU_SHIFT                 3
2582 #define PALMAS_PU_PD_GPIO_CTRL1_GPIO_1_PD                       0x04
2583 #define PALMAS_PU_PD_GPIO_CTRL1_GPIO_1_PD_SHIFT                 2
2584 #define PALMAS_PU_PD_GPIO_CTRL1_GPIO_0_PD                       0x01
2585 #define PALMAS_PU_PD_GPIO_CTRL1_GPIO_0_PD_SHIFT                 0
2586
2587 /* Bit definitions for PU_PD_GPIO_CTRL2 */
2588 #define PALMAS_PU_PD_GPIO_CTRL2_GPIO_7_PD                       0x40
2589 #define PALMAS_PU_PD_GPIO_CTRL2_GPIO_7_PD_SHIFT                 6
2590 #define PALMAS_PU_PD_GPIO_CTRL2_GPIO_6_PU                       0x20
2591 #define PALMAS_PU_PD_GPIO_CTRL2_GPIO_6_PU_SHIFT                 5
2592 #define PALMAS_PU_PD_GPIO_CTRL2_GPIO_6_PD                       0x10
2593 #define PALMAS_PU_PD_GPIO_CTRL2_GPIO_6_PD_SHIFT                 4
2594 #define PALMAS_PU_PD_GPIO_CTRL2_GPIO_5_PU                       0x08
2595 #define PALMAS_PU_PD_GPIO_CTRL2_GPIO_5_PU_SHIFT                 3
2596 #define PALMAS_PU_PD_GPIO_CTRL2_GPIO_5_PD                       0x04
2597 #define PALMAS_PU_PD_GPIO_CTRL2_GPIO_5_PD_SHIFT                 2
2598 #define PALMAS_PU_PD_GPIO_CTRL2_GPIO_4_PU                       0x02
2599 #define PALMAS_PU_PD_GPIO_CTRL2_GPIO_4_PU_SHIFT                 1
2600 #define PALMAS_PU_PD_GPIO_CTRL2_GPIO_4_PD                       0x01
2601 #define PALMAS_PU_PD_GPIO_CTRL2_GPIO_4_PD_SHIFT                 0
2602
2603 /* Bit definitions for OD_OUTPUT_GPIO_CTRL */
2604 #define PALMAS_OD_OUTPUT_GPIO_CTRL_GPIO_5_OD                    0x20
2605 #define PALMAS_OD_OUTPUT_GPIO_CTRL_GPIO_5_OD_SHIFT              5
2606 #define PALMAS_OD_OUTPUT_GPIO_CTRL_GPIO_2_OD                    0x04
2607 #define PALMAS_OD_OUTPUT_GPIO_CTRL_GPIO_2_OD_SHIFT              2
2608 #define PALMAS_OD_OUTPUT_GPIO_CTRL_GPIO_1_OD                    0x02
2609 #define PALMAS_OD_OUTPUT_GPIO_CTRL_GPIO_1_OD_SHIFT              1
2610
2611 /* Registers for function GPADC */
2612 #define PALMAS_GPADC_CTRL1                                      0x0
2613 #define PALMAS_GPADC_CTRL2                                      0x1
2614 #define PALMAS_GPADC_RT_CTRL                                    0x2
2615 #define PALMAS_GPADC_AUTO_CTRL                                  0x3
2616 #define PALMAS_GPADC_STATUS                                     0x4
2617 #define PALMAS_GPADC_RT_SELECT                                  0x5
2618 #define PALMAS_GPADC_RT_CONV0_LSB                               0x6
2619 #define PALMAS_GPADC_RT_CONV0_MSB                               0x7
2620 #define PALMAS_GPADC_AUTO_SELECT                                0x8
2621 #define PALMAS_GPADC_AUTO_CONV0_LSB                             0x9
2622 #define PALMAS_GPADC_AUTO_CONV0_MSB                             0xA
2623 #define PALMAS_GPADC_AUTO_CONV1_LSB                             0xB
2624 #define PALMAS_GPADC_AUTO_CONV1_MSB                             0xC
2625 #define PALMAS_GPADC_SW_SELECT                                  0xD
2626 #define PALMAS_GPADC_SW_CONV0_LSB                               0xE
2627 #define PALMAS_GPADC_SW_CONV0_MSB                               0xF
2628 #define PALMAS_GPADC_THRES_CONV0_LSB                            0x10
2629 #define PALMAS_GPADC_THRES_CONV0_MSB                            0x11
2630 #define PALMAS_GPADC_THRES_CONV1_LSB                            0x12
2631 #define PALMAS_GPADC_THRES_CONV1_MSB                            0x13
2632 #define PALMAS_GPADC_SMPS_ILMONITOR_EN                          0x14
2633 #define PALMAS_GPADC_SMPS_VSEL_MONITORING                       0x15
2634
2635 /* Bit definitions for GPADC_CTRL1 */
2636 #define PALMAS_GPADC_CTRL1_RESERVED_MASK                        0xc0
2637 #define PALMAS_GPADC_CTRL1_RESERVED_SHIFT                       6
2638 #define PALMAS_GPADC_CTRL1_CURRENT_SRC_CH3_MASK                 0x30
2639 #define PALMAS_GPADC_CTRL1_CURRENT_SRC_CH3_SHIFT                4
2640 #define PALMAS_GPADC_CTRL1_CURRENT_SRC_CH0_MASK                 0x0c
2641 #define PALMAS_GPADC_CTRL1_CURRENT_SRC_CH0_SHIFT                2
2642 #define PALMAS_GPADC_CTRL1_BAT_REMOVAL_DET                      0x02
2643 #define PALMAS_GPADC_CTRL1_BAT_REMOVAL_DET_SHIFT                1
2644 #define PALMAS_GPADC_CTRL1_GPADC_FORCE                          0x01
2645 #define PALMAS_GPADC_CTRL1_GPADC_FORCE_SHIFT                    0
2646
2647 /* Bit definitions for GPADC_CTRL2 */
2648 #define PALMAS_GPADC_CTRL2_RESERVED_MASK                        0x06
2649 #define PALMAS_GPADC_CTRL2_RESERVED_SHIFT                       1
2650
2651 /* Bit definitions for GPADC_RT_CTRL */
2652 #define PALMAS_GPADC_RT_CTRL_EXTEND_DELAY                       0x02
2653 #define PALMAS_GPADC_RT_CTRL_EXTEND_DELAY_SHIFT                 1
2654 #define PALMAS_GPADC_RT_CTRL_START_POLARITY                     0x01
2655 #define PALMAS_GPADC_RT_CTRL_START_POLARITY_SHIFT               0
2656
2657 /* Bit definitions for GPADC_AUTO_CTRL */
2658 #define PALMAS_GPADC_AUTO_CTRL_SHUTDOWN_CONV1                   0x80
2659 #define PALMAS_GPADC_AUTO_CTRL_SHUTDOWN_CONV1_SHIFT             7
2660 #define PALMAS_GPADC_AUTO_CTRL_SHUTDOWN_CONV0                   0x40
2661 #define PALMAS_GPADC_AUTO_CTRL_SHUTDOWN_CONV0_SHIFT             6
2662 #define PALMAS_GPADC_AUTO_CTRL_AUTO_CONV1_EN                    0x20
2663 #define PALMAS_GPADC_AUTO_CTRL_AUTO_CONV1_EN_SHIFT              5
2664 #define PALMAS_GPADC_AUTO_CTRL_AUTO_CONV0_EN                    0x10
2665 #define PALMAS_GPADC_AUTO_CTRL_AUTO_CONV0_EN_SHIFT              4
2666 #define PALMAS_GPADC_AUTO_CTRL_COUNTER_CONV_MASK                0x0f
2667 #define PALMAS_GPADC_AUTO_CTRL_COUNTER_CONV_SHIFT               0
2668
2669 /* Bit definitions for GPADC_STATUS */
2670 #define PALMAS_GPADC_STATUS_GPADC_AVAILABLE                     0x10
2671 #define PALMAS_GPADC_STATUS_GPADC_AVAILABLE_SHIFT               4
2672
2673 /* Bit definitions for GPADC_RT_SELECT */
2674 #define PALMAS_GPADC_RT_SELECT_RT_CONV_EN                       0x80
2675 #define PALMAS_GPADC_RT_SELECT_RT_CONV_EN_SHIFT                 7
2676 #define PALMAS_GPADC_RT_SELECT_RT_CONV0_SEL_MASK                0x0f
2677 #define PALMAS_GPADC_RT_SELECT_RT_CONV0_SEL_SHIFT               0
2678
2679 /* Bit definitions for GPADC_RT_CONV0_LSB */
2680 #define PALMAS_GPADC_RT_CONV0_LSB_RT_CONV0_LSB_MASK             0xff
2681 #define PALMAS_GPADC_RT_CONV0_LSB_RT_CONV0_LSB_SHIFT            0
2682
2683 /* Bit definitions for GPADC_RT_CONV0_MSB */
2684 #define PALMAS_GPADC_RT_CONV0_MSB_RT_CONV0_MSB_MASK             0x0f
2685 #define PALMAS_GPADC_RT_CONV0_MSB_RT_CONV0_MSB_SHIFT            0
2686
2687 /* Bit definitions for GPADC_AUTO_SELECT */
2688 #define PALMAS_GPADC_AUTO_SELECT_AUTO_CONV1_SEL_MASK            0xf0
2689 #define PALMAS_GPADC_AUTO_SELECT_AUTO_CONV1_SEL_SHIFT           4
2690 #define PALMAS_GPADC_AUTO_SELECT_AUTO_CONV0_SEL_MASK            0x0f
2691 #define PALMAS_GPADC_AUTO_SELECT_AUTO_CONV0_SEL_SHIFT           0
2692
2693 /* Bit definitions for GPADC_AUTO_CONV0_LSB */
2694 #define PALMAS_GPADC_AUTO_CONV0_LSB_AUTO_CONV0_LSB_MASK         0xff
2695 #define PALMAS_GPADC_AUTO_CONV0_LSB_AUTO_CONV0_LSB_SHIFT        0
2696
2697 /* Bit definitions for GPADC_AUTO_CONV0_MSB */
2698 #define PALMAS_GPADC_AUTO_CONV0_MSB_AUTO_CONV0_MSB_MASK         0x0f
2699 #define PALMAS_GPADC_AUTO_CONV0_MSB_AUTO_CONV0_MSB_SHIFT        0
2700
2701 /* Bit definitions for GPADC_AUTO_CONV1_LSB */
2702 #define PALMAS_GPADC_AUTO_CONV1_LSB_AUTO_CONV1_LSB_MASK         0xff
2703 #define PALMAS_GPADC_AUTO_CONV1_LSB_AUTO_CONV1_LSB_SHIFT        0
2704
2705 /* Bit definitions for GPADC_AUTO_CONV1_MSB */
2706 #define PALMAS_GPADC_AUTO_CONV1_MSB_AUTO_CONV1_MSB_MASK         0x0f
2707 #define PALMAS_GPADC_AUTO_CONV1_MSB_AUTO_CONV1_MSB_SHIFT        0
2708
2709 /* Bit definitions for GPADC_SW_SELECT */
2710 #define PALMAS_GPADC_SW_SELECT_SW_CONV_EN                       0x80
2711 #define PALMAS_GPADC_SW_SELECT_SW_CONV_EN_SHIFT                 7
2712 #define PALMAS_GPADC_SW_SELECT_SW_START_CONV0                   0x10
2713 #define PALMAS_GPADC_SW_SELECT_SW_START_CONV0_SHIFT             4
2714 #define PALMAS_GPADC_SW_SELECT_SW_CONV0_SEL_MASK                0x0f
2715 #define PALMAS_GPADC_SW_SELECT_SW_CONV0_SEL_SHIFT               0
2716
2717 /* Bit definitions for GPADC_SW_CONV0_LSB */
2718 #define PALMAS_GPADC_SW_CONV0_LSB_SW_CONV0_LSB_MASK             0xff
2719 #define PALMAS_GPADC_SW_CONV0_LSB_SW_CONV0_LSB_SHIFT            0
2720
2721 /* Bit definitions for GPADC_SW_CONV0_MSB */
2722 #define PALMAS_GPADC_SW_CONV0_MSB_SW_CONV0_MSB_MASK             0x0f
2723 #define PALMAS_GPADC_SW_CONV0_MSB_SW_CONV0_MSB_SHIFT            0
2724
2725 /* Bit definitions for GPADC_THRES_CONV0_LSB */
2726 #define PALMAS_GPADC_THRES_CONV0_LSB_THRES_CONV0_LSB_MASK       0xff
2727 #define PALMAS_GPADC_THRES_CONV0_LSB_THRES_CONV0_LSB_SHIFT      0
2728
2729 /* Bit definitions for GPADC_THRES_CONV0_MSB */
2730 #define PALMAS_GPADC_THRES_CONV0_MSB_THRES_CONV0_POL            0x80
2731 #define PALMAS_GPADC_THRES_CONV0_MSB_THRES_CONV0_POL_SHIFT      7
2732 #define PALMAS_GPADC_THRES_CONV0_MSB_THRES_CONV0_MSB_MASK       0x0f
2733 #define PALMAS_GPADC_THRES_CONV0_MSB_THRES_CONV0_MSB_SHIFT      0
2734
2735 /* Bit definitions for GPADC_THRES_CONV1_LSB */
2736 #define PALMAS_GPADC_THRES_CONV1_LSB_THRES_CONV1_LSB_MASK       0xff
2737 #define PALMAS_GPADC_THRES_CONV1_LSB_THRES_CONV1_LSB_SHIFT      0
2738
2739 /* Bit definitions for GPADC_THRES_CONV1_MSB */
2740 #define PALMAS_GPADC_THRES_CONV1_MSB_THRES_CONV1_POL            0x80
2741 #define PALMAS_GPADC_THRES_CONV1_MSB_THRES_CONV1_POL_SHIFT      7
2742 #define PALMAS_GPADC_THRES_CONV1_MSB_THRES_CONV1_MSB_MASK       0x0f
2743 #define PALMAS_GPADC_THRES_CONV1_MSB_THRES_CONV1_MSB_SHIFT      0
2744
2745 /* Bit definitions for GPADC_SMPS_ILMONITOR_EN */
2746 #define PALMAS_GPADC_SMPS_ILMONITOR_EN_SMPS_ILMON_EN            0x20
2747 #define PALMAS_GPADC_SMPS_ILMONITOR_EN_SMPS_ILMON_EN_SHIFT      5
2748 #define PALMAS_GPADC_SMPS_ILMONITOR_EN_SMPS_ILMON_REXT          0x10
2749 #define PALMAS_GPADC_SMPS_ILMONITOR_EN_SMPS_ILMON_REXT_SHIFT    4
2750 #define PALMAS_GPADC_SMPS_ILMONITOR_EN_SMPS_ILMON_SEL_MASK      0x0f
2751 #define PALMAS_GPADC_SMPS_ILMONITOR_EN_SMPS_ILMON_SEL_SHIFT     0
2752
2753 /* Bit definitions for GPADC_SMPS_VSEL_MONITORING */
2754 #define PALMAS_GPADC_SMPS_VSEL_MONITORING_ACTIVE_PHASE          0x80
2755 #define PALMAS_GPADC_SMPS_VSEL_MONITORING_ACTIVE_PHASE_SHIFT    7
2756 #define PALMAS_GPADC_SMPS_VSEL_MONITORING_SMPS_VSEL_MONITORING_MASK     0x7f
2757 #define PALMAS_GPADC_SMPS_VSEL_MONITORING_SMPS_VSEL_MONITORING_SHIFT    0
2758
2759 #define PALMAS_INTERNAL_DESIGNREV                               0x57
2760 #define PALMAS_INTERNAL_DESIGNREV_DESIGNREV(val)                ((val) & 0xF)
2761
2762 /* Registers for function GPADC */
2763 #define PALMAS_GPADC_TRIM1                                      0x0
2764 #define PALMAS_GPADC_TRIM2                                      0x1
2765 #define PALMAS_GPADC_TRIM3                                      0x2
2766 #define PALMAS_GPADC_TRIM4                                      0x3
2767 #define PALMAS_GPADC_TRIM5                                      0x4
2768 #define PALMAS_GPADC_TRIM6                                      0x5
2769 #define PALMAS_GPADC_TRIM7                                      0x6
2770 #define PALMAS_GPADC_TRIM8                                      0x7
2771 #define PALMAS_GPADC_TRIM9                                      0x8
2772 #define PALMAS_GPADC_TRIM10                                     0x9
2773 #define PALMAS_GPADC_TRIM11                                     0xA
2774 #define PALMAS_GPADC_TRIM12                                     0xB
2775 #define PALMAS_GPADC_TRIM13                                     0xC
2776 #define PALMAS_GPADC_TRIM14                                     0xD
2777 #define PALMAS_GPADC_TRIM15                                     0xE
2778 #define PALMAS_GPADC_TRIM16                                     0xF
2779 #define PALMAS_GPADC_TRIMINVALID                                -1
2780
2781 enum {
2782         PALMAS_EXT_CONTROL_ENABLE1      = 0x1,
2783         PALMAS_EXT_CONTROL_ENABLE2      = 0x2,
2784         PALMAS_EXT_CONTROL_NSLEEP       = 0x4,
2785 };
2786
2787 /**
2788  * Palmas regulator configs
2789  * PALMAS_REGULATOR_CONFIG_SUSPEND_FORCE_OFF: Force off on suspend
2790  */
2791 enum {
2792         PALMAS_REGULATOR_CONFIG_SUSPEND_FORCE_OFF = 0x1,
2793 };
2794
2795 /*
2796  *PALMAS GPIOs
2797  */
2798 enum {
2799         PALMAS_GPIO0,
2800         PALMAS_GPIO1,
2801         PALMAS_GPIO2,
2802         PALMAS_GPIO3,
2803         PALMAS_GPIO4,
2804         PALMAS_GPIO5,
2805         PALMAS_GPIO6,
2806         PALMAS_GPIO7,
2807
2808         PALMAS_GPIO_NR,
2809 };
2810
2811 /* Palma GPADC Channels */
2812 enum {
2813         PALMAS_ADC_CH_IN0,
2814         PALMAS_ADC_CH_IN1,
2815         PALMAS_ADC_CH_IN2,
2816         PALMAS_ADC_CH_IN3,
2817         PALMAS_ADC_CH_IN4,
2818         PALMAS_ADC_CH_IN5,
2819         PALMAS_ADC_CH_IN6,
2820         PALMAS_ADC_CH_IN7,
2821         PALMAS_ADC_CH_IN8,
2822         PALMAS_ADC_CH_IN9,
2823         PALMAS_ADC_CH_IN10,
2824         PALMAS_ADC_CH_IN11,
2825         PALMAS_ADC_CH_IN12,
2826         PALMAS_ADC_CH_IN13,
2827         PALMAS_ADC_CH_IN14,
2828         PALMAS_ADC_CH_IN15,
2829
2830         PALMAS_ADC_CH_MAX,
2831 };
2832
2833 /* Palma GPADC Channel0 Current Source */
2834 enum {
2835         PALMAS_ADC_CH0_CURRENT_SRC_0,
2836         PALMAS_ADC_CH0_CURRENT_SRC_5,
2837         PALMAS_ADC_CH0_CURRENT_SRC_15,
2838         PALMAS_ADC_CH0_CURRENT_SRC_20,
2839 };
2840
2841 /* Palma GPADC Channel3 Current Source */
2842 enum {
2843         PALMAS_ADC_CH3_CURRENT_SRC_0,
2844         PALMAS_ADC_CH3_CURRENT_SRC_10,
2845         PALMAS_ADC_CH3_CURRENT_SRC_400,
2846         PALMAS_ADC_CH3_CURRENT_SRC_800,
2847 };
2848
2849 /* Palma Sleep requestor IDs IDs */
2850 enum {
2851         PALMAS_SLEEP_REQSTR_ID_REGEN1,
2852         PALMAS_SLEEP_REQSTR_ID_REGEN2,
2853         PALMAS_SLEEP_REQSTR_ID_SYSEN1,
2854         PALMAS_SLEEP_REQSTR_ID_SYSEN2,
2855         PALMAS_SLEEP_REQSTR_ID_CLK32KG,
2856         PALMAS_SLEEP_REQSTR_ID_CLK32KGAUDIO,
2857         PALMAS_SLEEP_REQSTR_ID_REGEN3,
2858         PALMAS_SLEEP_REQSTR_ID_SMPS12,
2859         PALMAS_SLEEP_REQSTR_ID_SMPS3,
2860         PALMAS_SLEEP_REQSTR_ID_SMPS45,
2861         PALMAS_SLEEP_REQSTR_ID_SMPS6,
2862         PALMAS_SLEEP_REQSTR_ID_SMPS7,
2863         PALMAS_SLEEP_REQSTR_ID_SMPS8,
2864         PALMAS_SLEEP_REQSTR_ID_SMPS9,
2865         PALMAS_SLEEP_REQSTR_ID_SMPS10,
2866         PALMAS_SLEEP_REQSTR_ID_LDO1,
2867         PALMAS_SLEEP_REQSTR_ID_LDO2,
2868         PALMAS_SLEEP_REQSTR_ID_LDO3,
2869         PALMAS_SLEEP_REQSTR_ID_LDO4,
2870         PALMAS_SLEEP_REQSTR_ID_LDO5,
2871         PALMAS_SLEEP_REQSTR_ID_LDO6,
2872         PALMAS_SLEEP_REQSTR_ID_LDO7,
2873         PALMAS_SLEEP_REQSTR_ID_LDO8,
2874         PALMAS_SLEEP_REQSTR_ID_LDO9,
2875         PALMAS_SLEEP_REQSTR_ID_LDOLN,
2876         PALMAS_SLEEP_REQSTR_ID_LDOUSB,
2877
2878         /* Last entry */
2879         PALMAS_SLEEP_REQSTR_ID_MAX,
2880 };
2881
2882 /* Palmas Pinmux option */
2883 enum {
2884         PALMAS_PINMUX_GPIO = 0,
2885         PALMAS_PINMUX_LED,
2886         PALMAS_PINMUX_PWM,
2887         PALMAS_PINMUX_REGEN,
2888         PALMAS_PINMUX_SYSEN,
2889         PALMAS_PINMUX_CLK32KGAUDIO,
2890         PALMAS_PINMUX_ID,
2891         PALMAS_PINMUX_VBUS_DET,
2892         PALMAS_PINMUX_CHRG_DET,
2893         PALMAS_PINMUX_VAC,
2894         PALMAS_PINMUX_VACOK,
2895         PALMAS_PINMUX_POWERGOOD,
2896         PALMAS_PINMUX_USB_PSEL,
2897         PALMAS_PINMUX_MSECURE,
2898         PALMAS_PINMUX_PWRHOLD,
2899         PALMAS_PINMUX_INT,
2900         PALMAS_PINMUX_DVFS2,
2901         PALMAS_PINMUX_DVFS1,
2902         PALMAS_PINMUX_NRESWARM,
2903         PALMAS_PINMUX_PWRDOWN,
2904         PALMAS_PINMUX_GPADC_START,
2905         PALMAS_PINMUX_RESET_IN,
2906         PALMAS_PINMUX_NSLEEP,
2907         PALMAS_PINMUX_ENABLE1,
2908         PALMAS_PINMUX_ENABLE2,
2909         PALMAS_PINMUX_RESVD = 0x2000,
2910         PALMAS_PINMUX_DEFAULT = 0x4000,
2911         PALMAS_PINMUX_INVALID = 0x8000,
2912 };
2913
2914 /* Palmas Pinmux Pullup/pulldown/opendrain configuration. */
2915 enum {
2916         PALMAS_PIN_CONFIG_DEFAULT,
2917         PALMAS_PIN_CONFIG_NORMAL,
2918         PALMAS_PIN_CONFIG_PULL_UP,
2919         PALMAS_PIN_CONFIG_PULL_DOWN,
2920
2921         PALMAS_PIN_CONFIG_OD_DEFAULT,
2922         PALMAS_PIN_CONFIG_OD_ENABLE,
2923         PALMAS_PIN_CONFIG_OD_DISABLE,
2924 };
2925
2926 /* Palmas Pins name */
2927 enum {
2928         PALMAS_PIN_NAME_GPIO0,
2929         PALMAS_PIN_NAME_GPIO1,
2930         PALMAS_PIN_NAME_GPIO2,
2931         PALMAS_PIN_NAME_GPIO3,
2932         PALMAS_PIN_NAME_GPIO4,
2933         PALMAS_PIN_NAME_GPIO5,
2934         PALMAS_PIN_NAME_GPIO6,
2935         PALMAS_PIN_NAME_GPIO7,
2936         PALMAS_PIN_NAME_VAC,
2937         PALMAS_PIN_NAME_POWERGOOD,
2938         PALMAS_PIN_NAME_NRESWARM,
2939         PALMAS_PIN_NAME_PWRDOWN,
2940         PALMAS_PIN_NAME_GPADC_START,
2941         PALMAS_PIN_NAME_RESET_IN,
2942         PALMAS_PIN_NAME_NSLEEP,
2943         PALMAS_PIN_NAME_ENABLE1,
2944         PALMAS_PIN_NAME_ENABLE2,
2945         PALMAS_PIN_NAME_INT,
2946         PALMAS_PIN_NAME_MAX,
2947 };
2948
2949 extern int palmas_ext_power_req_config(struct palmas *palmas,
2950                 int id,  int ext_pwr_ctrl, bool enable);
2951
2952 static inline int palmas_read(struct palmas *palmas, unsigned int base,
2953                 unsigned int reg, unsigned int *val)
2954 {
2955         unsigned int addr =  PALMAS_BASE_TO_REG(base, reg);
2956         int slave_id = PALMAS_BASE_TO_SLAVE(base);
2957
2958         return regmap_read(palmas->regmap[slave_id], addr, val);
2959 }
2960
2961 static inline int palmas_write(struct palmas *palmas, unsigned int base,
2962                 unsigned int reg, unsigned int value)
2963 {
2964         unsigned int addr = PALMAS_BASE_TO_REG(base, reg);
2965         int slave_id = PALMAS_BASE_TO_SLAVE(base);
2966
2967         return regmap_write(palmas->regmap[slave_id], addr, value);
2968 }
2969
2970 static inline int palmas_bulk_write(struct palmas *palmas, unsigned int base,
2971         unsigned int reg, const void *val, size_t val_count)
2972 {
2973         unsigned int addr = PALMAS_BASE_TO_REG(base, reg);
2974         int slave_id = PALMAS_BASE_TO_SLAVE(base);
2975
2976         return regmap_bulk_write(palmas->regmap[slave_id], addr,
2977                         val, val_count);
2978 }
2979
2980 static inline int palmas_bulk_read(struct palmas *palmas, unsigned int base,
2981                 unsigned int reg, void *val, size_t val_count)
2982 {
2983         unsigned int addr = PALMAS_BASE_TO_REG(base, reg);
2984         int slave_id = PALMAS_BASE_TO_SLAVE(base);
2985
2986         return regmap_bulk_read(palmas->regmap[slave_id], addr,
2987                 val, val_count);
2988 }
2989
2990 static inline int palmas_update_bits(struct palmas *palmas, unsigned int base,
2991         unsigned int reg, unsigned int mask, unsigned int val)
2992 {
2993         unsigned int addr = PALMAS_BASE_TO_REG(base, reg);
2994         int slave_id = PALMAS_BASE_TO_SLAVE(base);
2995
2996         return regmap_update_bits(palmas->regmap[slave_id], addr, mask, val);
2997 }
2998
2999 extern int palmas_irq_get_virq(struct palmas *palmas, int irq);
3000
3001 static inline int palmas_is_es_version_or_less(struct palmas *palmas,
3002         int major, int minor)
3003 {
3004         if (palmas->es_major_version < major)
3005                 return true;
3006
3007         if ((palmas->es_major_version == major) &&
3008                 (palmas->es_minor_version <= minor))
3009                 return true;
3010
3011         return false;
3012 }
3013
3014 extern void palmas_reset(void);
3015 #endif /*  __LINUX_MFD_PALMAS_H */