a3a65999d57b846f9087ac687d8ba1f39ee5b5fd
[linux-2.6.git] / include / linux / mfd / palmas.h
1 /*
2  * TI Palmas
3  *
4  * Copyright 2011 Texas Instruments Inc.
5  *
6  * Author: Graeme Gregory <gg@slimlogic.co.uk>
7  *
8  *  This program is free software; you can redistribute it and/or modify it
9  *  under  the terms of the GNU General  Public License as published by the
10  *  Free Software Foundation;  either version 2 of the License, or (at your
11  *  option) any later version.
12  *
13  */
14
15 #ifndef __LINUX_MFD_PALMAS_H
16 #define __LINUX_MFD_PALMAS_H
17
18 #include <linux/usb/otg.h>
19 #include <linux/leds.h>
20 #include <linux/regmap.h>
21 #include <linux/regulator/driver.h>
22
23 #define PALMAS_NUM_CLIENTS              3
24
25 struct palmas_pmic;
26 struct palmas_rtc;
27
28 #define palmas_rails(_name) "palmas_"#_name
29
30 struct palmas {
31         struct device *dev;
32
33         struct i2c_client *i2c_clients[PALMAS_NUM_CLIENTS];
34         struct regmap *regmap[PALMAS_NUM_CLIENTS];
35
36         /* Stored chip id */
37         int id;
38
39         /* IRQ Data */
40         int irq;
41         u32 irq_mask;
42         struct mutex irq_lock;
43         struct regmap_irq_chip_data *irq_data;
44
45         /* Child Devices */
46         struct palmas_pmic *pmic;
47         struct palmas_rtc *rtc;
48
49         /* GPIO MUXing */
50         u8 gpio_muxed;
51         u8 led_muxed;
52         u8 pwm_muxed;
53
54         int design_revision;
55         int sw_otp_version;
56         int es_minor_version;
57         int es_major_version;
58 };
59
60 struct palmas_reg_init {
61         /* warm_rest controls the voltage levels after a warm reset
62          *
63          * 0: reload default values from OTP on warm reset
64          * 1: maintain voltage from VSEL on warm reset
65          */
66         int warm_reset;
67
68         /* roof_floor controls whether the regulator uses the i2c style
69          * of DVS or uses the method where a GPIO or other control method is
70          * attached to the NSLEEP/ENABLE1/ENABLE2 pins
71          *
72          * For SMPS
73          *
74          * 0: i2c selection of voltage
75          * 1: pin selection of voltage.
76          *
77          * For LDO unused
78          */
79         int roof_floor;
80
81         /* sleep_mode is the mode loaded to MODE_SLEEP bits as defined in
82          * the data sheet.
83          *
84          * For SMPS
85          *
86          * 0: Off
87          * 1: AUTO
88          * 2: ECO
89          * 3: Forced PWM
90          *
91          * For LDO
92          *
93          * 0: Off
94          * 1: On
95          */
96         int mode_sleep;
97
98         /* tstep is the timestep loaded to the TSTEP register
99          *
100          * For SMPS
101          *
102          * 0: Jump (no slope control)
103          * 1: 10mV/us
104          * 2: 5mV/us
105          * 3: 2.5mV/us
106          *
107          * For LDO unused
108          */
109         int tstep;
110
111         /* voltage_sel is the bitfield loaded onto the SMPSX_VOLTAGE
112          * register. Set this is the default voltage set in OTP needs
113          * to be overridden.
114          */
115         u8 vsel;
116
117 };
118
119 enum palmas_regulators {
120         /* SMPS regulators */
121         PALMAS_REG_SMPS12,
122         PALMAS_REG_SMPS123,
123         PALMAS_REG_SMPS3,
124         PALMAS_REG_SMPS45,
125         PALMAS_REG_SMPS457,
126         PALMAS_REG_SMPS6,
127         PALMAS_REG_SMPS7,
128         PALMAS_REG_SMPS8,
129         PALMAS_REG_SMPS9,
130         PALMAS_REG_SMPS10,
131         /* LDO regulators */
132         PALMAS_REG_LDO1,
133         PALMAS_REG_LDO2,
134         PALMAS_REG_LDO3,
135         PALMAS_REG_LDO4,
136         PALMAS_REG_LDO5,
137         PALMAS_REG_LDO6,
138         PALMAS_REG_LDO7,
139         PALMAS_REG_LDO8,
140         PALMAS_REG_LDO9,
141         PALMAS_REG_LDOLN,
142         PALMAS_REG_LDOUSB,
143         /* External regulators */
144         PALMAS_REG_REGEN1,
145         PALMAS_REG_REGEN2,
146         PALMAS_REG_REGEN3,
147         PALMAS_REG_SYSEN1,
148         PALMAS_REG_SYSEN2,
149         /* Total number of regulators */
150         PALMAS_NUM_REGS,
151 };
152
153 enum PALMAS_CLOCK32K {
154         PALMAS_CLOCK32KG,
155         PALMAS_CLOCK32KG_AUDIO,
156
157         /* Last entry */
158         PALMAS_CLOCK32K_NR,
159 };
160
161 struct palmas_clk32k_init_data {
162         int clk32k_id;
163         bool enable;
164         int sleep_control;
165 };
166
167 struct palmas_dvfs_init_data {
168         bool    en_pwm;
169         int     ext_ctrl;
170         int     reg_id;
171         bool    step_20mV;
172         int     base_voltage_uV;
173         int     max_voltage_uV;
174 };
175
176 struct palmas_pmic_platform_data {
177         /* An array of pointers to regulator init data indexed by regulator
178          * ID
179          */
180         struct regulator_init_data *reg_data[PALMAS_NUM_REGS];
181
182         /* An array of pointers to structures containing sleep mode and DVS
183          * configuration for regulators indexed by ID
184          */
185         struct palmas_reg_init *reg_init[PALMAS_NUM_REGS];
186
187         /* CL DVFS init data */
188         struct palmas_dvfs_init_data *dvfs_init_data;
189         int dvfs_init_data_size;
190
191         /* use LDO6 for vibrator control */
192         int ldo6_vibrator;
193
194         bool enable_ldo8_tracking;
195         bool disabe_ldo8_tracking_suspend;
196         bool disable_smps10_boost_suspend;
197
198
199 };
200
201 struct palmas_rtc_platform_data {
202         unsigned enable_charging:1;
203         unsigned charging_current_ua;
204 };
205
206 struct palmas_platform_data {
207         int gpio_base;
208         int irq_base;
209         int irq_type;
210
211         /* bit value to be loaded to the POWER_CTRL register */
212         u8 power_ctrl;
213
214         /*
215          * boolean to select if we want to configure muxing here
216          * then the two value to load into the registers if true
217          */
218         int mux_from_pdata;
219         u8 pad1, pad2, pad3;
220
221         struct palmas_pmic_platform_data *pmic_pdata;
222         struct palmas_rtc_platform_data *rtc_pdata;
223
224         struct palmas_clk32k_init_data  *clk32k_init_data;
225         int clk32k_init_data_size;
226         bool use_power_off;
227 };
228
229 /* Define the palmas IRQ numbers */
230 enum palmas_irqs {
231         /* INT1 registers */
232         PALMAS_CHARG_DET_N_VBUS_OVV_IRQ,
233         PALMAS_PWRON_IRQ,
234         PALMAS_LONG_PRESS_KEY_IRQ,
235         PALMAS_RPWRON_IRQ,
236         PALMAS_PWRDOWN_IRQ,
237         PALMAS_HOTDIE_IRQ,
238         PALMAS_VSYS_MON_IRQ,
239         PALMAS_VBAT_MON_IRQ,
240         /* INT2 registers */
241         PALMAS_RTC_ALARM_IRQ,
242         PALMAS_RTC_TIMER_IRQ,
243         PALMAS_WDT_IRQ,
244         PALMAS_BATREMOVAL_IRQ,
245         PALMAS_RESET_IN_IRQ,
246         PALMAS_FBI_BB_IRQ,
247         PALMAS_SHORT_IRQ,
248         PALMAS_VAC_ACOK_IRQ,
249         /* INT3 registers */
250         PALMAS_GPADC_AUTO_0_IRQ,
251         PALMAS_GPADC_AUTO_1_IRQ,
252         PALMAS_GPADC_EOC_SW_IRQ,
253         PALMAS_GPADC_EOC_RT_IRQ,
254         PALMAS_ID_OTG_IRQ,
255         PALMAS_ID_IRQ,
256         PALMAS_VBUS_OTG_IRQ,
257         PALMAS_VBUS_IRQ,
258         /* INT4 registers */
259         PALMAS_GPIO_0_IRQ,
260         PALMAS_GPIO_1_IRQ,
261         PALMAS_GPIO_2_IRQ,
262         PALMAS_GPIO_3_IRQ,
263         PALMAS_GPIO_4_IRQ,
264         PALMAS_GPIO_5_IRQ,
265         PALMAS_GPIO_6_IRQ,
266         PALMAS_GPIO_7_IRQ,
267         /* Total Number IRQs */
268         PALMAS_NUM_IRQ,
269 };
270
271 struct palmas_pmic {
272         struct palmas *palmas;
273         struct device *dev;
274         struct regulator_desc desc[PALMAS_NUM_REGS];
275         struct regulator_dev *rdev[PALMAS_NUM_REGS];
276         struct mutex mutex;
277
278         int smps123;
279         int smps457;
280
281         unsigned int ramp_delay[PALMAS_NUM_REGS];
282
283         int range[PALMAS_REG_SMPS10];
284 };
285
286 /* defines so we can store the mux settings */
287 #define PALMAS_GPIO_0_MUXED                                     (1 << 0)
288 #define PALMAS_GPIO_1_MUXED                                     (1 << 1)
289 #define PALMAS_GPIO_2_MUXED                                     (1 << 2)
290 #define PALMAS_GPIO_3_MUXED                                     (1 << 3)
291 #define PALMAS_GPIO_4_MUXED                                     (1 << 4)
292 #define PALMAS_GPIO_5_MUXED                                     (1 << 5)
293 #define PALMAS_GPIO_6_MUXED                                     (1 << 6)
294 #define PALMAS_GPIO_7_MUXED                                     (1 << 7)
295
296 #define PALMAS_LED1_MUXED                                       (1 << 0)
297 #define PALMAS_LED2_MUXED                                       (1 << 1)
298
299 #define PALMAS_PWM1_MUXED                                       (1 << 0)
300 #define PALMAS_PWM2_MUXED                                       (1 << 1)
301
302 /* helper macro to get correct slave number */
303 #define PALMAS_BASE_TO_SLAVE(x)         ((x >> 8) - 1)
304 #define PALMAS_BASE_TO_REG(x, y)        ((x & 0xff) + y)
305 #define RTC_SLAVE                       0
306
307 /* Base addresses of IP blocks in Palmas */
308 #define PALMAS_SMPS_DVS_BASE                                    0x20
309 #define PALMAS_RTC_BASE                                         0x100
310 #define PALMAS_VALIDITY_BASE                                    0x118
311 #define PALMAS_SMPS_BASE                                        0x120
312 #define PALMAS_LDO_BASE                                         0x150
313 #define PALMAS_DVFS_BASE                                        0x180
314 #define PALMAS_PMU_CONTROL_BASE                                 0x1A0
315 #define PALMAS_RESOURCE_BASE                                    0x1D4
316 #define PALMAS_PU_PD_OD_BASE                                    0x1F4
317 #define PALMAS_LED_BASE                                         0x200
318 #define PALMAS_INTERRUPT_BASE                                   0x210
319 #define PALMAS_USB_OTG_BASE                                     0x250
320 #define PALMAS_VIBRATOR_BASE                                    0x270
321 #define PALMAS_GPIO_BASE                                        0x280
322 #define PALMAS_USB_BASE                                         0x290
323 #define PALMAS_GPADC_BASE                                       0x2C0
324 #define PALMAS_TRIM_GPADC_BASE                                  0x3CD
325 #define PALMAS_PAGE3_BASE                                       0x300
326
327 /* Registers for function RTC */
328 #define PALMAS_SECONDS_REG                                      0x0
329 #define PALMAS_MINUTES_REG                                      0x1
330 #define PALMAS_HOURS_REG                                        0x2
331 #define PALMAS_DAYS_REG                                         0x3
332 #define PALMAS_MONTHS_REG                                       0x4
333 #define PALMAS_YEARS_REG                                        0x5
334 #define PALMAS_WEEKS_REG                                        0x6
335 #define PALMAS_ALARM_SECONDS_REG                                0x8
336 #define PALMAS_ALARM_MINUTES_REG                                0x9
337 #define PALMAS_ALARM_HOURS_REG                                  0xA
338 #define PALMAS_ALARM_DAYS_REG                                   0xB
339 #define PALMAS_ALARM_MONTHS_REG                                 0xC
340 #define PALMAS_ALARM_YEARS_REG                                  0xD
341 #define PALMAS_RTC_CTRL_REG                                     0x10
342 #define PALMAS_RTC_STATUS_REG                                   0x11
343 #define PALMAS_RTC_INTERRUPTS_REG                               0x12
344 #define PALMAS_RTC_COMP_LSB_REG                                 0x13
345 #define PALMAS_RTC_COMP_MSB_REG                                 0x14
346 #define PALMAS_RTC_RES_PROG_REG                                 0x15
347 #define PALMAS_RTC_RESET_STATUS_REG                             0x16
348
349 /* Bit definitions for SECONDS_REG */
350 #define PALMAS_SECONDS_REG_SEC1_MASK                            0x70
351 #define PALMAS_SECONDS_REG_SEC1_SHIFT                           4
352 #define PALMAS_SECONDS_REG_SEC0_MASK                            0x0f
353 #define PALMAS_SECONDS_REG_SEC0_SHIFT                           0
354
355 /* Bit definitions for MINUTES_REG */
356 #define PALMAS_MINUTES_REG_MIN1_MASK                            0x70
357 #define PALMAS_MINUTES_REG_MIN1_SHIFT                           4
358 #define PALMAS_MINUTES_REG_MIN0_MASK                            0x0f
359 #define PALMAS_MINUTES_REG_MIN0_SHIFT                           0
360
361 /* Bit definitions for HOURS_REG */
362 #define PALMAS_HOURS_REG_PM_NAM                                 0x80
363 #define PALMAS_HOURS_REG_PM_NAM_SHIFT                           7
364 #define PALMAS_HOURS_REG_HOUR1_MASK                             0x30
365 #define PALMAS_HOURS_REG_HOUR1_SHIFT                            4
366 #define PALMAS_HOURS_REG_HOUR0_MASK                             0x0f
367 #define PALMAS_HOURS_REG_HOUR0_SHIFT                            0
368
369 /* Bit definitions for DAYS_REG */
370 #define PALMAS_DAYS_REG_DAY1_MASK                               0x30
371 #define PALMAS_DAYS_REG_DAY1_SHIFT                              4
372 #define PALMAS_DAYS_REG_DAY0_MASK                               0x0f
373 #define PALMAS_DAYS_REG_DAY0_SHIFT                              0
374
375 /* Bit definitions for MONTHS_REG */
376 #define PALMAS_MONTHS_REG_MONTH1                                0x10
377 #define PALMAS_MONTHS_REG_MONTH1_SHIFT                          4
378 #define PALMAS_MONTHS_REG_MONTH0_MASK                           0x0f
379 #define PALMAS_MONTHS_REG_MONTH0_SHIFT                          0
380
381 /* Bit definitions for YEARS_REG */
382 #define PALMAS_YEARS_REG_YEAR1_MASK                             0xf0
383 #define PALMAS_YEARS_REG_YEAR1_SHIFT                            4
384 #define PALMAS_YEARS_REG_YEAR0_MASK                             0x0f
385 #define PALMAS_YEARS_REG_YEAR0_SHIFT                            0
386
387 /* Bit definitions for WEEKS_REG */
388 #define PALMAS_WEEKS_REG_WEEK_MASK                              0x07
389 #define PALMAS_WEEKS_REG_WEEK_SHIFT                             0
390
391 /* Bit definitions for ALARM_SECONDS_REG */
392 #define PALMAS_ALARM_SECONDS_REG_ALARM_SEC1_MASK                0x70
393 #define PALMAS_ALARM_SECONDS_REG_ALARM_SEC1_SHIFT               4
394 #define PALMAS_ALARM_SECONDS_REG_ALARM_SEC0_MASK                0x0f
395 #define PALMAS_ALARM_SECONDS_REG_ALARM_SEC0_SHIFT               0
396
397 /* Bit definitions for ALARM_MINUTES_REG */
398 #define PALMAS_ALARM_MINUTES_REG_ALARM_MIN1_MASK                0x70
399 #define PALMAS_ALARM_MINUTES_REG_ALARM_MIN1_SHIFT               4
400 #define PALMAS_ALARM_MINUTES_REG_ALARM_MIN0_MASK                0x0f
401 #define PALMAS_ALARM_MINUTES_REG_ALARM_MIN0_SHIFT               0
402
403 /* Bit definitions for ALARM_HOURS_REG */
404 #define PALMAS_ALARM_HOURS_REG_ALARM_PM_NAM                     0x80
405 #define PALMAS_ALARM_HOURS_REG_ALARM_PM_NAM_SHIFT               7
406 #define PALMAS_ALARM_HOURS_REG_ALARM_HOUR1_MASK                 0x30
407 #define PALMAS_ALARM_HOURS_REG_ALARM_HOUR1_SHIFT                4
408 #define PALMAS_ALARM_HOURS_REG_ALARM_HOUR0_MASK                 0x0f
409 #define PALMAS_ALARM_HOURS_REG_ALARM_HOUR0_SHIFT                0
410
411 /* Bit definitions for ALARM_DAYS_REG */
412 #define PALMAS_ALARM_DAYS_REG_ALARM_DAY1_MASK                   0x30
413 #define PALMAS_ALARM_DAYS_REG_ALARM_DAY1_SHIFT                  4
414 #define PALMAS_ALARM_DAYS_REG_ALARM_DAY0_MASK                   0x0f
415 #define PALMAS_ALARM_DAYS_REG_ALARM_DAY0_SHIFT                  0
416
417 /* Bit definitions for ALARM_MONTHS_REG */
418 #define PALMAS_ALARM_MONTHS_REG_ALARM_MONTH1                    0x10
419 #define PALMAS_ALARM_MONTHS_REG_ALARM_MONTH1_SHIFT              4
420 #define PALMAS_ALARM_MONTHS_REG_ALARM_MONTH0_MASK               0x0f
421 #define PALMAS_ALARM_MONTHS_REG_ALARM_MONTH0_SHIFT              0
422
423 /* Bit definitions for ALARM_YEARS_REG */
424 #define PALMAS_ALARM_YEARS_REG_ALARM_YEAR1_MASK                 0xf0
425 #define PALMAS_ALARM_YEARS_REG_ALARM_YEAR1_SHIFT                4
426 #define PALMAS_ALARM_YEARS_REG_ALARM_YEAR0_MASK                 0x0f
427 #define PALMAS_ALARM_YEARS_REG_ALARM_YEAR0_SHIFT                0
428
429 /* Bit definitions for RTC_CTRL_REG */
430 #define PALMAS_RTC_CTRL_REG_RTC_V_OPT                           0x80
431 #define PALMAS_RTC_CTRL_REG_RTC_V_OPT_SHIFT                     7
432 #define PALMAS_RTC_CTRL_REG_GET_TIME                            0x40
433 #define PALMAS_RTC_CTRL_REG_GET_TIME_SHIFT                      6
434 #define PALMAS_RTC_CTRL_REG_SET_32_COUNTER                      0x20
435 #define PALMAS_RTC_CTRL_REG_SET_32_COUNTER_SHIFT                5
436 #define PALMAS_RTC_CTRL_REG_TEST_MODE                           0x10
437 #define PALMAS_RTC_CTRL_REG_TEST_MODE_SHIFT                     4
438 #define PALMAS_RTC_CTRL_REG_MODE_12_24                          0x08
439 #define PALMAS_RTC_CTRL_REG_MODE_12_24_SHIFT                    3
440 #define PALMAS_RTC_CTRL_REG_AUTO_COMP                           0x04
441 #define PALMAS_RTC_CTRL_REG_AUTO_COMP_SHIFT                     2
442 #define PALMAS_RTC_CTRL_REG_ROUND_30S                           0x02
443 #define PALMAS_RTC_CTRL_REG_ROUND_30S_SHIFT                     1
444 #define PALMAS_RTC_CTRL_REG_STOP_RTC                            0x01
445 #define PALMAS_RTC_CTRL_REG_STOP_RTC_SHIFT                      0
446
447 /* Bit definitions for RTC_STATUS_REG */
448 #define PALMAS_RTC_STATUS_REG_POWER_UP                          0x80
449 #define PALMAS_RTC_STATUS_REG_POWER_UP_SHIFT                    7
450 #define PALMAS_RTC_STATUS_REG_ALARM                             0x40
451 #define PALMAS_RTC_STATUS_REG_ALARM_SHIFT                       6
452 #define PALMAS_RTC_STATUS_REG_EVENT_1D                          0x20
453 #define PALMAS_RTC_STATUS_REG_EVENT_1D_SHIFT                    5
454 #define PALMAS_RTC_STATUS_REG_EVENT_1H                          0x10
455 #define PALMAS_RTC_STATUS_REG_EVENT_1H_SHIFT                    4
456 #define PALMAS_RTC_STATUS_REG_EVENT_1M                          0x08
457 #define PALMAS_RTC_STATUS_REG_EVENT_1M_SHIFT                    3
458 #define PALMAS_RTC_STATUS_REG_EVENT_1S                          0x04
459 #define PALMAS_RTC_STATUS_REG_EVENT_1S_SHIFT                    2
460 #define PALMAS_RTC_STATUS_REG_RUN                               0x02
461 #define PALMAS_RTC_STATUS_REG_RUN_SHIFT                         1
462
463 /* Bit definitions for RTC_INTERRUPTS_REG */
464 #define PALMAS_RTC_INTERRUPTS_REG_IT_SLEEP_MASK_EN              0x10
465 #define PALMAS_RTC_INTERRUPTS_REG_IT_SLEEP_MASK_EN_SHIFT        4
466 #define PALMAS_RTC_INTERRUPTS_REG_IT_ALARM                      0x08
467 #define PALMAS_RTC_INTERRUPTS_REG_IT_ALARM_SHIFT                3
468 #define PALMAS_RTC_INTERRUPTS_REG_IT_TIMER                      0x04
469 #define PALMAS_RTC_INTERRUPTS_REG_IT_TIMER_SHIFT                2
470 #define PALMAS_RTC_INTERRUPTS_REG_EVERY_MASK                    0x03
471 #define PALMAS_RTC_INTERRUPTS_REG_EVERY_SHIFT                   0
472
473 /* Bit definitions for RTC_COMP_LSB_REG */
474 #define PALMAS_RTC_COMP_LSB_REG_RTC_COMP_LSB_MASK               0xff
475 #define PALMAS_RTC_COMP_LSB_REG_RTC_COMP_LSB_SHIFT              0
476
477 /* Bit definitions for RTC_COMP_MSB_REG */
478 #define PALMAS_RTC_COMP_MSB_REG_RTC_COMP_MSB_MASK               0xff
479 #define PALMAS_RTC_COMP_MSB_REG_RTC_COMP_MSB_SHIFT              0
480
481 /* Bit definitions for RTC_RES_PROG_REG */
482 #define PALMAS_RTC_RES_PROG_REG_SW_RES_PROG_MASK                0x3f
483 #define PALMAS_RTC_RES_PROG_REG_SW_RES_PROG_SHIFT               0
484
485 /* Bit definitions for RTC_RESET_STATUS_REG */
486 #define PALMAS_RTC_RESET_STATUS_REG_RESET_STATUS                0x01
487 #define PALMAS_RTC_RESET_STATUS_REG_RESET_STATUS_SHIFT          0
488
489 /* Registers for function BACKUP */
490 #define PALMAS_BACKUP0                                          0x0
491 #define PALMAS_BACKUP1                                          0x1
492 #define PALMAS_BACKUP2                                          0x2
493 #define PALMAS_BACKUP3                                          0x3
494 #define PALMAS_BACKUP4                                          0x4
495 #define PALMAS_BACKUP5                                          0x5
496 #define PALMAS_BACKUP6                                          0x6
497 #define PALMAS_BACKUP7                                          0x7
498
499 /* Bit definitions for BACKUP0 */
500 #define PALMAS_BACKUP0_BACKUP_MASK                              0xff
501 #define PALMAS_BACKUP0_BACKUP_SHIFT                             0
502
503 /* Bit definitions for BACKUP1 */
504 #define PALMAS_BACKUP1_BACKUP_MASK                              0xff
505 #define PALMAS_BACKUP1_BACKUP_SHIFT                             0
506
507 /* Bit definitions for BACKUP2 */
508 #define PALMAS_BACKUP2_BACKUP_MASK                              0xff
509 #define PALMAS_BACKUP2_BACKUP_SHIFT                             0
510
511 /* Bit definitions for BACKUP3 */
512 #define PALMAS_BACKUP3_BACKUP_MASK                              0xff
513 #define PALMAS_BACKUP3_BACKUP_SHIFT                             0
514
515 /* Bit definitions for BACKUP4 */
516 #define PALMAS_BACKUP4_BACKUP_MASK                              0xff
517 #define PALMAS_BACKUP4_BACKUP_SHIFT                             0
518
519 /* Bit definitions for BACKUP5 */
520 #define PALMAS_BACKUP5_BACKUP_MASK                              0xff
521 #define PALMAS_BACKUP5_BACKUP_SHIFT                             0
522
523 /* Bit definitions for BACKUP6 */
524 #define PALMAS_BACKUP6_BACKUP_MASK                              0xff
525 #define PALMAS_BACKUP6_BACKUP_SHIFT                             0
526
527 /* Bit definitions for BACKUP7 */
528 #define PALMAS_BACKUP7_BACKUP_MASK                              0xff
529 #define PALMAS_BACKUP7_BACKUP_SHIFT                             0
530
531 /* Registers for function SMPS */
532 #define PALMAS_SMPS12_CTRL                                      0x0
533 #define PALMAS_SMPS12_TSTEP                                     0x1
534 #define PALMAS_SMPS12_FORCE                                     0x2
535 #define PALMAS_SMPS12_VOLTAGE                                   0x3
536 #define PALMAS_SMPS3_CTRL                                       0x4
537 #define PALMAS_SMPS3_VOLTAGE                                    0x7
538 #define PALMAS_SMPS45_CTRL                                      0x8
539 #define PALMAS_SMPS45_TSTEP                                     0x9
540 #define PALMAS_SMPS45_FORCE                                     0xA
541 #define PALMAS_SMPS45_VOLTAGE                                   0xB
542 #define PALMAS_SMPS6_CTRL                                       0xC
543 #define PALMAS_SMPS6_TSTEP                                      0xD
544 #define PALMAS_SMPS6_FORCE                                      0xE
545 #define PALMAS_SMPS6_VOLTAGE                                    0xF
546 #define PALMAS_SMPS7_CTRL                                       0x10
547 #define PALMAS_SMPS7_VOLTAGE                                    0x13
548 #define PALMAS_SMPS8_CTRL                                       0x14
549 #define PALMAS_SMPS8_TSTEP                                      0x15
550 #define PALMAS_SMPS8_FORCE                                      0x16
551 #define PALMAS_SMPS8_VOLTAGE                                    0x17
552 #define PALMAS_SMPS9_CTRL                                       0x18
553 #define PALMAS_SMPS9_VOLTAGE                                    0x1B
554 #define PALMAS_SMPS10_CTRL                                      0x1C
555 #define PALMAS_SMPS10_STATUS                                    0x1F
556 #define PALMAS_SMPS_CTRL                                        0x24
557 #define PALMAS_SMPS_PD_CTRL                                     0x25
558 #define PALMAS_SMPS_DITHER_EN                                   0x26
559 #define PALMAS_SMPS_THERMAL_EN                                  0x27
560 #define PALMAS_SMPS_THERMAL_STATUS                              0x28
561 #define PALMAS_SMPS_SHORT_STATUS                                0x29
562 #define PALMAS_SMPS_NEGATIVE_CURRENT_LIMIT_EN                   0x2A
563 #define PALMAS_SMPS_POWERGOOD_MASK1                             0x2B
564 #define PALMAS_SMPS_POWERGOOD_MASK2                             0x2C
565
566 /* Bit definitions for SMPS12_CTRL */
567 #define PALMAS_SMPS12_CTRL_WR_S                                 0x80
568 #define PALMAS_SMPS12_CTRL_WR_S_SHIFT                           7
569 #define PALMAS_SMPS12_CTRL_ROOF_FLOOR_EN                        0x40
570 #define PALMAS_SMPS12_CTRL_ROOF_FLOOR_EN_SHIFT                  6
571 #define PALMAS_SMPS12_CTRL_STATUS_MASK                          0x30
572 #define PALMAS_SMPS12_CTRL_STATUS_SHIFT                         4
573 #define PALMAS_SMPS12_CTRL_MODE_SLEEP_MASK                      0x0c
574 #define PALMAS_SMPS12_CTRL_MODE_SLEEP_SHIFT                     2
575 #define PALMAS_SMPS12_CTRL_MODE_ACTIVE_MASK                     0x03
576 #define PALMAS_SMPS12_CTRL_MODE_ACTIVE_SHIFT                    0
577
578 /* Bit definitions for SMPS12_TSTEP */
579 #define PALMAS_SMPS12_TSTEP_TSTEP_MASK                          0x03
580 #define PALMAS_SMPS12_TSTEP_TSTEP_SHIFT                         0
581
582 /* Bit definitions for SMPS12_FORCE */
583 #define PALMAS_SMPS12_FORCE_CMD                                 0x80
584 #define PALMAS_SMPS12_FORCE_CMD_SHIFT                           7
585 #define PALMAS_SMPS12_FORCE_VSEL_MASK                           0x7f
586 #define PALMAS_SMPS12_FORCE_VSEL_SHIFT                          0
587
588 /* Bit definitions for SMPS12_VOLTAGE */
589 #define PALMAS_SMPS12_VOLTAGE_RANGE                             0x80
590 #define PALMAS_SMPS12_VOLTAGE_RANGE_SHIFT                       7
591 #define PALMAS_SMPS12_VOLTAGE_VSEL_MASK                         0x7f
592 #define PALMAS_SMPS12_VOLTAGE_VSEL_SHIFT                        0
593
594 /* Bit definitions for SMPS3_CTRL */
595 #define PALMAS_SMPS3_CTRL_WR_S                                  0x80
596 #define PALMAS_SMPS3_CTRL_WR_S_SHIFT                            7
597 #define PALMAS_SMPS3_CTRL_STATUS_MASK                           0x30
598 #define PALMAS_SMPS3_CTRL_STATUS_SHIFT                          4
599 #define PALMAS_SMPS3_CTRL_MODE_SLEEP_MASK                       0x0c
600 #define PALMAS_SMPS3_CTRL_MODE_SLEEP_SHIFT                      2
601 #define PALMAS_SMPS3_CTRL_MODE_ACTIVE_MASK                      0x03
602 #define PALMAS_SMPS3_CTRL_MODE_ACTIVE_SHIFT                     0
603
604 /* Bit definitions for SMPS3_VOLTAGE */
605 #define PALMAS_SMPS3_VOLTAGE_RANGE                              0x80
606 #define PALMAS_SMPS3_VOLTAGE_RANGE_SHIFT                        7
607 #define PALMAS_SMPS3_VOLTAGE_VSEL_MASK                          0x7f
608 #define PALMAS_SMPS3_VOLTAGE_VSEL_SHIFT                         0
609
610 /* Bit definitions for SMPS45_CTRL */
611 #define PALMAS_SMPS45_CTRL_WR_S                                 0x80
612 #define PALMAS_SMPS45_CTRL_WR_S_SHIFT                           7
613 #define PALMAS_SMPS45_CTRL_ROOF_FLOOR_EN                        0x40
614 #define PALMAS_SMPS45_CTRL_ROOF_FLOOR_EN_SHIFT                  6
615 #define PALMAS_SMPS45_CTRL_STATUS_MASK                          0x30
616 #define PALMAS_SMPS45_CTRL_STATUS_SHIFT                         4
617 #define PALMAS_SMPS45_CTRL_MODE_SLEEP_MASK                      0x0c
618 #define PALMAS_SMPS45_CTRL_MODE_SLEEP_SHIFT                     2
619 #define PALMAS_SMPS45_CTRL_MODE_ACTIVE_MASK                     0x03
620 #define PALMAS_SMPS45_CTRL_MODE_ACTIVE_SHIFT                    0
621
622 /* Bit definitions for SMPS45_TSTEP */
623 #define PALMAS_SMPS45_TSTEP_TSTEP_MASK                          0x03
624 #define PALMAS_SMPS45_TSTEP_TSTEP_SHIFT                         0
625
626 /* Bit definitions for SMPS45_FORCE */
627 #define PALMAS_SMPS45_FORCE_CMD                                 0x80
628 #define PALMAS_SMPS45_FORCE_CMD_SHIFT                           7
629 #define PALMAS_SMPS45_FORCE_VSEL_MASK                           0x7f
630 #define PALMAS_SMPS45_FORCE_VSEL_SHIFT                          0
631
632 /* Bit definitions for SMPS45_VOLTAGE */
633 #define PALMAS_SMPS45_VOLTAGE_RANGE                             0x80
634 #define PALMAS_SMPS45_VOLTAGE_RANGE_SHIFT                       7
635 #define PALMAS_SMPS45_VOLTAGE_VSEL_MASK                         0x7f
636 #define PALMAS_SMPS45_VOLTAGE_VSEL_SHIFT                        0
637
638 /* Bit definitions for SMPS6_CTRL */
639 #define PALMAS_SMPS6_CTRL_WR_S                                  0x80
640 #define PALMAS_SMPS6_CTRL_WR_S_SHIFT                            7
641 #define PALMAS_SMPS6_CTRL_ROOF_FLOOR_EN                         0x40
642 #define PALMAS_SMPS6_CTRL_ROOF_FLOOR_EN_SHIFT                   6
643 #define PALMAS_SMPS6_CTRL_STATUS_MASK                           0x30
644 #define PALMAS_SMPS6_CTRL_STATUS_SHIFT                          4
645 #define PALMAS_SMPS6_CTRL_MODE_SLEEP_MASK                       0x0c
646 #define PALMAS_SMPS6_CTRL_MODE_SLEEP_SHIFT                      2
647 #define PALMAS_SMPS6_CTRL_MODE_ACTIVE_MASK                      0x03
648 #define PALMAS_SMPS6_CTRL_MODE_ACTIVE_SHIFT                     0
649
650 /* Bit definitions for SMPS6_TSTEP */
651 #define PALMAS_SMPS6_TSTEP_TSTEP_MASK                           0x03
652 #define PALMAS_SMPS6_TSTEP_TSTEP_SHIFT                          0
653
654 /* Bit definitions for SMPS6_FORCE */
655 #define PALMAS_SMPS6_FORCE_CMD                                  0x80
656 #define PALMAS_SMPS6_FORCE_CMD_SHIFT                            7
657 #define PALMAS_SMPS6_FORCE_VSEL_MASK                            0x7f
658 #define PALMAS_SMPS6_FORCE_VSEL_SHIFT                           0
659
660 /* Bit definitions for SMPS6_VOLTAGE */
661 #define PALMAS_SMPS6_VOLTAGE_RANGE                              0x80
662 #define PALMAS_SMPS6_VOLTAGE_RANGE_SHIFT                        7
663 #define PALMAS_SMPS6_VOLTAGE_VSEL_MASK                          0x7f
664 #define PALMAS_SMPS6_VOLTAGE_VSEL_SHIFT                         0
665
666 /* Bit definitions for SMPS7_CTRL */
667 #define PALMAS_SMPS7_CTRL_WR_S                                  0x80
668 #define PALMAS_SMPS7_CTRL_WR_S_SHIFT                            7
669 #define PALMAS_SMPS7_CTRL_STATUS_MASK                           0x30
670 #define PALMAS_SMPS7_CTRL_STATUS_SHIFT                          4
671 #define PALMAS_SMPS7_CTRL_MODE_SLEEP_MASK                       0x0c
672 #define PALMAS_SMPS7_CTRL_MODE_SLEEP_SHIFT                      2
673 #define PALMAS_SMPS7_CTRL_MODE_ACTIVE_MASK                      0x03
674 #define PALMAS_SMPS7_CTRL_MODE_ACTIVE_SHIFT                     0
675
676 /* Bit definitions for SMPS7_VOLTAGE */
677 #define PALMAS_SMPS7_VOLTAGE_RANGE                              0x80
678 #define PALMAS_SMPS7_VOLTAGE_RANGE_SHIFT                        7
679 #define PALMAS_SMPS7_VOLTAGE_VSEL_MASK                          0x7f
680 #define PALMAS_SMPS7_VOLTAGE_VSEL_SHIFT                         0
681
682 /* Bit definitions for SMPS8_CTRL */
683 #define PALMAS_SMPS8_CTRL_WR_S                                  0x80
684 #define PALMAS_SMPS8_CTRL_WR_S_SHIFT                            7
685 #define PALMAS_SMPS8_CTRL_ROOF_FLOOR_EN                         0x40
686 #define PALMAS_SMPS8_CTRL_ROOF_FLOOR_EN_SHIFT                   6
687 #define PALMAS_SMPS8_CTRL_STATUS_MASK                           0x30
688 #define PALMAS_SMPS8_CTRL_STATUS_SHIFT                          4
689 #define PALMAS_SMPS8_CTRL_MODE_SLEEP_MASK                       0x0c
690 #define PALMAS_SMPS8_CTRL_MODE_SLEEP_SHIFT                      2
691 #define PALMAS_SMPS8_CTRL_MODE_ACTIVE_MASK                      0x03
692 #define PALMAS_SMPS8_CTRL_MODE_ACTIVE_SHIFT                     0
693
694 /* Bit definitions for SMPS8_TSTEP */
695 #define PALMAS_SMPS8_TSTEP_TSTEP_MASK                           0x03
696 #define PALMAS_SMPS8_TSTEP_TSTEP_SHIFT                          0
697
698 /* Bit definitions for SMPS8_FORCE */
699 #define PALMAS_SMPS8_FORCE_CMD                                  0x80
700 #define PALMAS_SMPS8_FORCE_CMD_SHIFT                            7
701 #define PALMAS_SMPS8_FORCE_VSEL_MASK                            0x7f
702 #define PALMAS_SMPS8_FORCE_VSEL_SHIFT                           0
703
704 /* Bit definitions for SMPS8_VOLTAGE */
705 #define PALMAS_SMPS8_VOLTAGE_RANGE                              0x80
706 #define PALMAS_SMPS8_VOLTAGE_RANGE_SHIFT                        7
707 #define PALMAS_SMPS8_VOLTAGE_VSEL_MASK                          0x7f
708 #define PALMAS_SMPS8_VOLTAGE_VSEL_SHIFT                         0
709
710 /* Bit definitions for SMPS9_CTRL */
711 #define PALMAS_SMPS9_CTRL_WR_S                                  0x80
712 #define PALMAS_SMPS9_CTRL_WR_S_SHIFT                            7
713 #define PALMAS_SMPS9_CTRL_STATUS_MASK                           0x30
714 #define PALMAS_SMPS9_CTRL_STATUS_SHIFT                          4
715 #define PALMAS_SMPS9_CTRL_MODE_SLEEP_MASK                       0x0c
716 #define PALMAS_SMPS9_CTRL_MODE_SLEEP_SHIFT                      2
717 #define PALMAS_SMPS9_CTRL_MODE_ACTIVE_MASK                      0x03
718 #define PALMAS_SMPS9_CTRL_MODE_ACTIVE_SHIFT                     0
719
720 /* Bit definitions for SMPS9_VOLTAGE */
721 #define PALMAS_SMPS9_VOLTAGE_RANGE                              0x80
722 #define PALMAS_SMPS9_VOLTAGE_RANGE_SHIFT                        7
723 #define PALMAS_SMPS9_VOLTAGE_VSEL_MASK                          0x7f
724 #define PALMAS_SMPS9_VOLTAGE_VSEL_SHIFT                         0
725
726 /* Bit definitions for SMPS10_CTRL */
727 #define PALMAS_SMPS10_CTRL_MODE_SLEEP_MASK                      0xf0
728 #define PALMAS_SMPS10_CTRL_MODE_SLEEP_SHIFT                     4
729 #define PALMAS_SMPS10_CTRL_MODE_ACTIVE_MASK                     0x0f
730 #define PALMAS_SMPS10_CTRL_MODE_ACTIVE_SHIFT                    0
731
732 /* Bit definitions for SMPS10_STATUS */
733 #define PALMAS_SMPS10_STATUS_STATUS_MASK                        0x0f
734 #define PALMAS_SMPS10_STATUS_STATUS_SHIFT                       0
735
736 /* Bit definitions for SMPS_CTRL */
737 #define PALMAS_SMPS_CTRL_SMPS45_SMPS457_EN                      0x20
738 #define PALMAS_SMPS_CTRL_SMPS45_SMPS457_EN_SHIFT                5
739 #define PALMAS_SMPS_CTRL_SMPS12_SMPS123_EN                      0x10
740 #define PALMAS_SMPS_CTRL_SMPS12_SMPS123_EN_SHIFT                4
741 #define PALMAS_SMPS_CTRL_SMPS45_PHASE_CTRL_MASK                 0x0c
742 #define PALMAS_SMPS_CTRL_SMPS45_PHASE_CTRL_SHIFT                2
743 #define PALMAS_SMPS_CTRL_SMPS123_PHASE_CTRL_MASK                0x03
744 #define PALMAS_SMPS_CTRL_SMPS123_PHASE_CTRL_SHIFT               0
745
746 /* Bit definitions for SMPS_PD_CTRL */
747 #define PALMAS_SMPS_PD_CTRL_SMPS9                               0x40
748 #define PALMAS_SMPS_PD_CTRL_SMPS9_SHIFT                         6
749 #define PALMAS_SMPS_PD_CTRL_SMPS8                               0x20
750 #define PALMAS_SMPS_PD_CTRL_SMPS8_SHIFT                         5
751 #define PALMAS_SMPS_PD_CTRL_SMPS7                               0x10
752 #define PALMAS_SMPS_PD_CTRL_SMPS7_SHIFT                         4
753 #define PALMAS_SMPS_PD_CTRL_SMPS6                               0x08
754 #define PALMAS_SMPS_PD_CTRL_SMPS6_SHIFT                         3
755 #define PALMAS_SMPS_PD_CTRL_SMPS45                              0x04
756 #define PALMAS_SMPS_PD_CTRL_SMPS45_SHIFT                        2
757 #define PALMAS_SMPS_PD_CTRL_SMPS3                               0x02
758 #define PALMAS_SMPS_PD_CTRL_SMPS3_SHIFT                         1
759 #define PALMAS_SMPS_PD_CTRL_SMPS12                              0x01
760 #define PALMAS_SMPS_PD_CTRL_SMPS12_SHIFT                        0
761
762 /* Bit definitions for SMPS_THERMAL_EN */
763 #define PALMAS_SMPS_THERMAL_EN_SMPS9                            0x40
764 #define PALMAS_SMPS_THERMAL_EN_SMPS9_SHIFT                      6
765 #define PALMAS_SMPS_THERMAL_EN_SMPS8                            0x20
766 #define PALMAS_SMPS_THERMAL_EN_SMPS8_SHIFT                      5
767 #define PALMAS_SMPS_THERMAL_EN_SMPS6                            0x08
768 #define PALMAS_SMPS_THERMAL_EN_SMPS6_SHIFT                      3
769 #define PALMAS_SMPS_THERMAL_EN_SMPS457                          0x04
770 #define PALMAS_SMPS_THERMAL_EN_SMPS457_SHIFT                    2
771 #define PALMAS_SMPS_THERMAL_EN_SMPS123                          0x01
772 #define PALMAS_SMPS_THERMAL_EN_SMPS123_SHIFT                    0
773
774 /* Bit definitions for SMPS_THERMAL_STATUS */
775 #define PALMAS_SMPS_THERMAL_STATUS_SMPS9                        0x40
776 #define PALMAS_SMPS_THERMAL_STATUS_SMPS9_SHIFT                  6
777 #define PALMAS_SMPS_THERMAL_STATUS_SMPS8                        0x20
778 #define PALMAS_SMPS_THERMAL_STATUS_SMPS8_SHIFT                  5
779 #define PALMAS_SMPS_THERMAL_STATUS_SMPS6                        0x08
780 #define PALMAS_SMPS_THERMAL_STATUS_SMPS6_SHIFT                  3
781 #define PALMAS_SMPS_THERMAL_STATUS_SMPS457                      0x04
782 #define PALMAS_SMPS_THERMAL_STATUS_SMPS457_SHIFT                2
783 #define PALMAS_SMPS_THERMAL_STATUS_SMPS123                      0x01
784 #define PALMAS_SMPS_THERMAL_STATUS_SMPS123_SHIFT                0
785
786 /* Bit definitions for SMPS_SHORT_STATUS */
787 #define PALMAS_SMPS_SHORT_STATUS_SMPS10                         0x80
788 #define PALMAS_SMPS_SHORT_STATUS_SMPS10_SHIFT                   7
789 #define PALMAS_SMPS_SHORT_STATUS_SMPS9                          0x40
790 #define PALMAS_SMPS_SHORT_STATUS_SMPS9_SHIFT                    6
791 #define PALMAS_SMPS_SHORT_STATUS_SMPS8                          0x20
792 #define PALMAS_SMPS_SHORT_STATUS_SMPS8_SHIFT                    5
793 #define PALMAS_SMPS_SHORT_STATUS_SMPS7                          0x10
794 #define PALMAS_SMPS_SHORT_STATUS_SMPS7_SHIFT                    4
795 #define PALMAS_SMPS_SHORT_STATUS_SMPS6                          0x08
796 #define PALMAS_SMPS_SHORT_STATUS_SMPS6_SHIFT                    3
797 #define PALMAS_SMPS_SHORT_STATUS_SMPS45                         0x04
798 #define PALMAS_SMPS_SHORT_STATUS_SMPS45_SHIFT                   2
799 #define PALMAS_SMPS_SHORT_STATUS_SMPS3                          0x02
800 #define PALMAS_SMPS_SHORT_STATUS_SMPS3_SHIFT                    1
801 #define PALMAS_SMPS_SHORT_STATUS_SMPS12                         0x01
802 #define PALMAS_SMPS_SHORT_STATUS_SMPS12_SHIFT                   0
803
804 /* Bit definitions for SMPS_NEGATIVE_CURRENT_LIMIT_EN */
805 #define PALMAS_SMPS_NEGATIVE_CURRENT_LIMIT_EN_SMPS9             0x40
806 #define PALMAS_SMPS_NEGATIVE_CURRENT_LIMIT_EN_SMPS9_SHIFT       6
807 #define PALMAS_SMPS_NEGATIVE_CURRENT_LIMIT_EN_SMPS8             0x20
808 #define PALMAS_SMPS_NEGATIVE_CURRENT_LIMIT_EN_SMPS8_SHIFT       5
809 #define PALMAS_SMPS_NEGATIVE_CURRENT_LIMIT_EN_SMPS7             0x10
810 #define PALMAS_SMPS_NEGATIVE_CURRENT_LIMIT_EN_SMPS7_SHIFT       4
811 #define PALMAS_SMPS_NEGATIVE_CURRENT_LIMIT_EN_SMPS6             0x08
812 #define PALMAS_SMPS_NEGATIVE_CURRENT_LIMIT_EN_SMPS6_SHIFT       3
813 #define PALMAS_SMPS_NEGATIVE_CURRENT_LIMIT_EN_SMPS45            0x04
814 #define PALMAS_SMPS_NEGATIVE_CURRENT_LIMIT_EN_SMPS45_SHIFT      2
815 #define PALMAS_SMPS_NEGATIVE_CURRENT_LIMIT_EN_SMPS3             0x02
816 #define PALMAS_SMPS_NEGATIVE_CURRENT_LIMIT_EN_SMPS3_SHIFT       1
817 #define PALMAS_SMPS_NEGATIVE_CURRENT_LIMIT_EN_SMPS12            0x01
818 #define PALMAS_SMPS_NEGATIVE_CURRENT_LIMIT_EN_SMPS12_SHIFT      0
819
820 /* Bit definitions for SMPS_POWERGOOD_MASK1 */
821 #define PALMAS_SMPS_POWERGOOD_MASK1_SMPS10                      0x80
822 #define PALMAS_SMPS_POWERGOOD_MASK1_SMPS10_SHIFT                7
823 #define PALMAS_SMPS_POWERGOOD_MASK1_SMPS9                       0x40
824 #define PALMAS_SMPS_POWERGOOD_MASK1_SMPS9_SHIFT                 6
825 #define PALMAS_SMPS_POWERGOOD_MASK1_SMPS8                       0x20
826 #define PALMAS_SMPS_POWERGOOD_MASK1_SMPS8_SHIFT                 5
827 #define PALMAS_SMPS_POWERGOOD_MASK1_SMPS7                       0x10
828 #define PALMAS_SMPS_POWERGOOD_MASK1_SMPS7_SHIFT                 4
829 #define PALMAS_SMPS_POWERGOOD_MASK1_SMPS6                       0x08
830 #define PALMAS_SMPS_POWERGOOD_MASK1_SMPS6_SHIFT                 3
831 #define PALMAS_SMPS_POWERGOOD_MASK1_SMPS45                      0x04
832 #define PALMAS_SMPS_POWERGOOD_MASK1_SMPS45_SHIFT                2
833 #define PALMAS_SMPS_POWERGOOD_MASK1_SMPS3                       0x02
834 #define PALMAS_SMPS_POWERGOOD_MASK1_SMPS3_SHIFT                 1
835 #define PALMAS_SMPS_POWERGOOD_MASK1_SMPS12                      0x01
836 #define PALMAS_SMPS_POWERGOOD_MASK1_SMPS12_SHIFT                0
837
838 /* Bit definitions for SMPS_POWERGOOD_MASK2 */
839 #define PALMAS_SMPS_POWERGOOD_MASK2_POWERGOOD_TYPE_SELECT       0x80
840 #define PALMAS_SMPS_POWERGOOD_MASK2_POWERGOOD_TYPE_SELECT_SHIFT 7
841 #define PALMAS_SMPS_POWERGOOD_MASK2_GPIO_7                      0x04
842 #define PALMAS_SMPS_POWERGOOD_MASK2_GPIO_7_SHIFT                2
843 #define PALMAS_SMPS_POWERGOOD_MASK2_VBUS                        0x02
844 #define PALMAS_SMPS_POWERGOOD_MASK2_VBUS_SHIFT                  1
845 #define PALMAS_SMPS_POWERGOOD_MASK2_ACOK                        0x01
846 #define PALMAS_SMPS_POWERGOOD_MASK2_ACOK_SHIFT                  0
847
848 /* Registers for function LDO */
849 #define PALMAS_LDO1_CTRL                                        0x0
850 #define PALMAS_LDO1_VOLTAGE                                     0x1
851 #define PALMAS_LDO2_CTRL                                        0x2
852 #define PALMAS_LDO2_VOLTAGE                                     0x3
853 #define PALMAS_LDO3_CTRL                                        0x4
854 #define PALMAS_LDO3_VOLTAGE                                     0x5
855 #define PALMAS_LDO4_CTRL                                        0x6
856 #define PALMAS_LDO4_VOLTAGE                                     0x7
857 #define PALMAS_LDO5_CTRL                                        0x8
858 #define PALMAS_LDO5_VOLTAGE                                     0x9
859 #define PALMAS_LDO6_CTRL                                        0xA
860 #define PALMAS_LDO6_VOLTAGE                                     0xB
861 #define PALMAS_LDO7_CTRL                                        0xC
862 #define PALMAS_LDO7_VOLTAGE                                     0xD
863 #define PALMAS_LDO8_CTRL                                        0xE
864 #define PALMAS_LDO8_VOLTAGE                                     0xF
865 #define PALMAS_LDO9_CTRL                                        0x10
866 #define PALMAS_LDO9_VOLTAGE                                     0x11
867 #define PALMAS_LDOLN_CTRL                                       0x12
868 #define PALMAS_LDOLN_VOLTAGE                                    0x13
869 #define PALMAS_LDOUSB_CTRL                                      0x14
870 #define PALMAS_LDOUSB_VOLTAGE                                   0x15
871 #define PALMAS_LDO_CTRL                                         0x1A
872 #define PALMAS_LDO_PD_CTRL1                                     0x1B
873 #define PALMAS_LDO_PD_CTRL2                                     0x1C
874 #define PALMAS_LDO_SHORT_STATUS1                                0x1D
875 #define PALMAS_LDO_SHORT_STATUS2                                0x1E
876
877 /* Bit definitions for LDO1_CTRL */
878 #define PALMAS_LDO1_CTRL_WR_S                                   0x80
879 #define PALMAS_LDO1_CTRL_WR_S_SHIFT                             7
880 #define PALMAS_LDO1_CTRL_STATUS                                 0x10
881 #define PALMAS_LDO1_CTRL_STATUS_SHIFT                           4
882 #define PALMAS_LDO1_CTRL_MODE_SLEEP                             0x04
883 #define PALMAS_LDO1_CTRL_MODE_SLEEP_SHIFT                       2
884 #define PALMAS_LDO1_CTRL_MODE_ACTIVE                            0x01
885 #define PALMAS_LDO1_CTRL_MODE_ACTIVE_SHIFT                      0
886
887 /* Bit definitions for LDO1_VOLTAGE */
888 #define PALMAS_LDO1_VOLTAGE_VSEL_MASK                           0x3f
889 #define PALMAS_LDO1_VOLTAGE_VSEL_SHIFT                          0
890
891 /* Bit definitions for LDO2_CTRL */
892 #define PALMAS_LDO2_CTRL_WR_S                                   0x80
893 #define PALMAS_LDO2_CTRL_WR_S_SHIFT                             7
894 #define PALMAS_LDO2_CTRL_STATUS                                 0x10
895 #define PALMAS_LDO2_CTRL_STATUS_SHIFT                           4
896 #define PALMAS_LDO2_CTRL_MODE_SLEEP                             0x04
897 #define PALMAS_LDO2_CTRL_MODE_SLEEP_SHIFT                       2
898 #define PALMAS_LDO2_CTRL_MODE_ACTIVE                            0x01
899 #define PALMAS_LDO2_CTRL_MODE_ACTIVE_SHIFT                      0
900
901 /* Bit definitions for LDO2_VOLTAGE */
902 #define PALMAS_LDO2_VOLTAGE_VSEL_MASK                           0x3f
903 #define PALMAS_LDO2_VOLTAGE_VSEL_SHIFT                          0
904
905 /* Bit definitions for LDO3_CTRL */
906 #define PALMAS_LDO3_CTRL_WR_S                                   0x80
907 #define PALMAS_LDO3_CTRL_WR_S_SHIFT                             7
908 #define PALMAS_LDO3_CTRL_STATUS                                 0x10
909 #define PALMAS_LDO3_CTRL_STATUS_SHIFT                           4
910 #define PALMAS_LDO3_CTRL_MODE_SLEEP                             0x04
911 #define PALMAS_LDO3_CTRL_MODE_SLEEP_SHIFT                       2
912 #define PALMAS_LDO3_CTRL_MODE_ACTIVE                            0x01
913 #define PALMAS_LDO3_CTRL_MODE_ACTIVE_SHIFT                      0
914
915 /* Bit definitions for LDO3_VOLTAGE */
916 #define PALMAS_LDO3_VOLTAGE_VSEL_MASK                           0x3f
917 #define PALMAS_LDO3_VOLTAGE_VSEL_SHIFT                          0
918
919 /* Bit definitions for LDO4_CTRL */
920 #define PALMAS_LDO4_CTRL_WR_S                                   0x80
921 #define PALMAS_LDO4_CTRL_WR_S_SHIFT                             7
922 #define PALMAS_LDO4_CTRL_STATUS                                 0x10
923 #define PALMAS_LDO4_CTRL_STATUS_SHIFT                           4
924 #define PALMAS_LDO4_CTRL_MODE_SLEEP                             0x04
925 #define PALMAS_LDO4_CTRL_MODE_SLEEP_SHIFT                       2
926 #define PALMAS_LDO4_CTRL_MODE_ACTIVE                            0x01
927 #define PALMAS_LDO4_CTRL_MODE_ACTIVE_SHIFT                      0
928
929 /* Bit definitions for LDO4_VOLTAGE */
930 #define PALMAS_LDO4_VOLTAGE_VSEL_MASK                           0x3f
931 #define PALMAS_LDO4_VOLTAGE_VSEL_SHIFT                          0
932
933 /* Bit definitions for LDO5_CTRL */
934 #define PALMAS_LDO5_CTRL_WR_S                                   0x80
935 #define PALMAS_LDO5_CTRL_WR_S_SHIFT                             7
936 #define PALMAS_LDO5_CTRL_STATUS                                 0x10
937 #define PALMAS_LDO5_CTRL_STATUS_SHIFT                           4
938 #define PALMAS_LDO5_CTRL_MODE_SLEEP                             0x04
939 #define PALMAS_LDO5_CTRL_MODE_SLEEP_SHIFT                       2
940 #define PALMAS_LDO5_CTRL_MODE_ACTIVE                            0x01
941 #define PALMAS_LDO5_CTRL_MODE_ACTIVE_SHIFT                      0
942
943 /* Bit definitions for LDO5_VOLTAGE */
944 #define PALMAS_LDO5_VOLTAGE_VSEL_MASK                           0x3f
945 #define PALMAS_LDO5_VOLTAGE_VSEL_SHIFT                          0
946
947 /* Bit definitions for LDO6_CTRL */
948 #define PALMAS_LDO6_CTRL_WR_S                                   0x80
949 #define PALMAS_LDO6_CTRL_WR_S_SHIFT                             7
950 #define PALMAS_LDO6_CTRL_LDO_VIB_EN                             0x40
951 #define PALMAS_LDO6_CTRL_LDO_VIB_EN_SHIFT                       6
952 #define PALMAS_LDO6_CTRL_STATUS                                 0x10
953 #define PALMAS_LDO6_CTRL_STATUS_SHIFT                           4
954 #define PALMAS_LDO6_CTRL_MODE_SLEEP                             0x04
955 #define PALMAS_LDO6_CTRL_MODE_SLEEP_SHIFT                       2
956 #define PALMAS_LDO6_CTRL_MODE_ACTIVE                            0x01
957 #define PALMAS_LDO6_CTRL_MODE_ACTIVE_SHIFT                      0
958
959 /* Bit definitions for LDO6_VOLTAGE */
960 #define PALMAS_LDO6_VOLTAGE_VSEL_MASK                           0x3f
961 #define PALMAS_LDO6_VOLTAGE_VSEL_SHIFT                          0
962
963 /* Bit definitions for LDO7_CTRL */
964 #define PALMAS_LDO7_CTRL_WR_S                                   0x80
965 #define PALMAS_LDO7_CTRL_WR_S_SHIFT                             7
966 #define PALMAS_LDO7_CTRL_STATUS                                 0x10
967 #define PALMAS_LDO7_CTRL_STATUS_SHIFT                           4
968 #define PALMAS_LDO7_CTRL_MODE_SLEEP                             0x04
969 #define PALMAS_LDO7_CTRL_MODE_SLEEP_SHIFT                       2
970 #define PALMAS_LDO7_CTRL_MODE_ACTIVE                            0x01
971 #define PALMAS_LDO7_CTRL_MODE_ACTIVE_SHIFT                      0
972
973 /* Bit definitions for LDO7_VOLTAGE */
974 #define PALMAS_LDO7_VOLTAGE_VSEL_MASK                           0x3f
975 #define PALMAS_LDO7_VOLTAGE_VSEL_SHIFT                          0
976
977 /* Bit definitions for LDO8_CTRL */
978 #define PALMAS_LDO8_CTRL_WR_S                                   0x80
979 #define PALMAS_LDO8_CTRL_WR_S_SHIFT                             7
980 #define PALMAS_LDO8_CTRL_LDO_TRACKING_EN                        0x40
981 #define PALMAS_LDO8_CTRL_LDO_TRACKING_EN_SHIFT                  6
982 #define PALMAS_LDO8_CTRL_STATUS                                 0x10
983 #define PALMAS_LDO8_CTRL_STATUS_SHIFT                           4
984 #define PALMAS_LDO8_CTRL_MODE_SLEEP                             0x04
985 #define PALMAS_LDO8_CTRL_MODE_SLEEP_SHIFT                       2
986 #define PALMAS_LDO8_CTRL_MODE_ACTIVE                            0x01
987 #define PALMAS_LDO8_CTRL_MODE_ACTIVE_SHIFT                      0
988
989 /* Bit definitions for LDO8_VOLTAGE */
990 #define PALMAS_LDO8_VOLTAGE_VSEL_MASK                           0x3f
991 #define PALMAS_LDO8_VOLTAGE_VSEL_SHIFT                          0
992
993 /* Bit definitions for LDO9_CTRL */
994 #define PALMAS_LDO9_CTRL_WR_S                                   0x80
995 #define PALMAS_LDO9_CTRL_WR_S_SHIFT                             7
996 #define PALMAS_LDO9_CTRL_LDO_BYPASS_EN                          0x40
997 #define PALMAS_LDO9_CTRL_LDO_BYPASS_EN_SHIFT                    6
998 #define PALMAS_LDO9_CTRL_STATUS                                 0x10
999 #define PALMAS_LDO9_CTRL_STATUS_SHIFT                           4
1000 #define PALMAS_LDO9_CTRL_MODE_SLEEP                             0x04
1001 #define PALMAS_LDO9_CTRL_MODE_SLEEP_SHIFT                       2
1002 #define PALMAS_LDO9_CTRL_MODE_ACTIVE                            0x01
1003 #define PALMAS_LDO9_CTRL_MODE_ACTIVE_SHIFT                      0
1004
1005 /* Bit definitions for LDO9_VOLTAGE */
1006 #define PALMAS_LDO9_VOLTAGE_VSEL_MASK                           0x3f
1007 #define PALMAS_LDO9_VOLTAGE_VSEL_SHIFT                          0
1008
1009 /* Bit definitions for LDOLN_CTRL */
1010 #define PALMAS_LDOLN_CTRL_WR_S                                  0x80
1011 #define PALMAS_LDOLN_CTRL_WR_S_SHIFT                            7
1012 #define PALMAS_LDOLN_CTRL_STATUS                                0x10
1013 #define PALMAS_LDOLN_CTRL_STATUS_SHIFT                          4
1014 #define PALMAS_LDOLN_CTRL_MODE_SLEEP                            0x04
1015 #define PALMAS_LDOLN_CTRL_MODE_SLEEP_SHIFT                      2
1016 #define PALMAS_LDOLN_CTRL_MODE_ACTIVE                           0x01
1017 #define PALMAS_LDOLN_CTRL_MODE_ACTIVE_SHIFT                     0
1018
1019 /* Bit definitions for LDOLN_VOLTAGE */
1020 #define PALMAS_LDOLN_VOLTAGE_VSEL_MASK                          0x3f
1021 #define PALMAS_LDOLN_VOLTAGE_VSEL_SHIFT                         0
1022
1023 /* Bit definitions for LDOUSB_CTRL */
1024 #define PALMAS_LDOUSB_CTRL_WR_S                                 0x80
1025 #define PALMAS_LDOUSB_CTRL_WR_S_SHIFT                           7
1026 #define PALMAS_LDOUSB_CTRL_STATUS                               0x10
1027 #define PALMAS_LDOUSB_CTRL_STATUS_SHIFT                         4
1028 #define PALMAS_LDOUSB_CTRL_MODE_SLEEP                           0x04
1029 #define PALMAS_LDOUSB_CTRL_MODE_SLEEP_SHIFT                     2
1030 #define PALMAS_LDOUSB_CTRL_MODE_ACTIVE                          0x01
1031 #define PALMAS_LDOUSB_CTRL_MODE_ACTIVE_SHIFT                    0
1032
1033 /* Bit definitions for LDOUSB_VOLTAGE */
1034 #define PALMAS_LDOUSB_VOLTAGE_VSEL_MASK                         0x3f
1035 #define PALMAS_LDOUSB_VOLTAGE_VSEL_SHIFT                        0
1036
1037 /* Bit definitions for LDO_CTRL */
1038 #define PALMAS_LDO_CTRL_LDOUSB_ON_VBUS_VSYS                     0x01
1039 #define PALMAS_LDO_CTRL_LDOUSB_ON_VBUS_VSYS_SHIFT               0
1040
1041 /* Bit definitions for LDO_PD_CTRL1 */
1042 #define PALMAS_LDO_PD_CTRL1_LDO8                                0x80
1043 #define PALMAS_LDO_PD_CTRL1_LDO8_SHIFT                          7
1044 #define PALMAS_LDO_PD_CTRL1_LDO7                                0x40
1045 #define PALMAS_LDO_PD_CTRL1_LDO7_SHIFT                          6
1046 #define PALMAS_LDO_PD_CTRL1_LDO6                                0x20
1047 #define PALMAS_LDO_PD_CTRL1_LDO6_SHIFT                          5
1048 #define PALMAS_LDO_PD_CTRL1_LDO5                                0x10
1049 #define PALMAS_LDO_PD_CTRL1_LDO5_SHIFT                          4
1050 #define PALMAS_LDO_PD_CTRL1_LDO4                                0x08
1051 #define PALMAS_LDO_PD_CTRL1_LDO4_SHIFT                          3
1052 #define PALMAS_LDO_PD_CTRL1_LDO3                                0x04
1053 #define PALMAS_LDO_PD_CTRL1_LDO3_SHIFT                          2
1054 #define PALMAS_LDO_PD_CTRL1_LDO2                                0x02
1055 #define PALMAS_LDO_PD_CTRL1_LDO2_SHIFT                          1
1056 #define PALMAS_LDO_PD_CTRL1_LDO1                                0x01
1057 #define PALMAS_LDO_PD_CTRL1_LDO1_SHIFT                          0
1058
1059 /* Bit definitions for LDO_PD_CTRL2 */
1060 #define PALMAS_LDO_PD_CTRL2_LDOUSB                              0x04
1061 #define PALMAS_LDO_PD_CTRL2_LDOUSB_SHIFT                        2
1062 #define PALMAS_LDO_PD_CTRL2_LDOLN                               0x02
1063 #define PALMAS_LDO_PD_CTRL2_LDOLN_SHIFT                         1
1064 #define PALMAS_LDO_PD_CTRL2_LDO9                                0x01
1065 #define PALMAS_LDO_PD_CTRL2_LDO9_SHIFT                          0
1066
1067 /* Bit definitions for LDO_SHORT_STATUS1 */
1068 #define PALMAS_LDO_SHORT_STATUS1_LDO8                           0x80
1069 #define PALMAS_LDO_SHORT_STATUS1_LDO8_SHIFT                     7
1070 #define PALMAS_LDO_SHORT_STATUS1_LDO7                           0x40
1071 #define PALMAS_LDO_SHORT_STATUS1_LDO7_SHIFT                     6
1072 #define PALMAS_LDO_SHORT_STATUS1_LDO6                           0x20
1073 #define PALMAS_LDO_SHORT_STATUS1_LDO6_SHIFT                     5
1074 #define PALMAS_LDO_SHORT_STATUS1_LDO5                           0x10
1075 #define PALMAS_LDO_SHORT_STATUS1_LDO5_SHIFT                     4
1076 #define PALMAS_LDO_SHORT_STATUS1_LDO4                           0x08
1077 #define PALMAS_LDO_SHORT_STATUS1_LDO4_SHIFT                     3
1078 #define PALMAS_LDO_SHORT_STATUS1_LDO3                           0x04
1079 #define PALMAS_LDO_SHORT_STATUS1_LDO3_SHIFT                     2
1080 #define PALMAS_LDO_SHORT_STATUS1_LDO2                           0x02
1081 #define PALMAS_LDO_SHORT_STATUS1_LDO2_SHIFT                     1
1082 #define PALMAS_LDO_SHORT_STATUS1_LDO1                           0x01
1083 #define PALMAS_LDO_SHORT_STATUS1_LDO1_SHIFT                     0
1084
1085 /* Bit definitions for LDO_SHORT_STATUS2 */
1086 #define PALMAS_LDO_SHORT_STATUS2_LDOVANA                        0x08
1087 #define PALMAS_LDO_SHORT_STATUS2_LDOVANA_SHIFT                  3
1088 #define PALMAS_LDO_SHORT_STATUS2_LDOUSB                         0x04
1089 #define PALMAS_LDO_SHORT_STATUS2_LDOUSB_SHIFT                   2
1090 #define PALMAS_LDO_SHORT_STATUS2_LDOLN                          0x02
1091 #define PALMAS_LDO_SHORT_STATUS2_LDOLN_SHIFT                    1
1092 #define PALMAS_LDO_SHORT_STATUS2_LDO9                           0x01
1093 #define PALMAS_LDO_SHORT_STATUS2_LDO9_SHIFT                     0
1094
1095 /* Registers for function DVFS Func */
1096 #define PALMAS_SMPS_DVFS1_CTRL                                  0x0
1097 #define PALMAS_SMPS_DVFS1_ENABLE_SHIFT                          0
1098 #define PALMAS_SMPS_DVFS1_OFFSET_STEP_SHIFT                     1
1099 #define PALMAS_SMPS_DVFS1_ENABLE_RST_SHIFT                      2
1100 #define PALMAS_SMPS_DVFS1_RESTORE_VALUE_SHIFT                   3
1101 #define PALMAS_SMPS_DVFS1_VOLTAGE_MAX                           0x1
1102 #define PALMAS_SMPS_DVFS1_STATUS                                0x2
1103
1104 #define DVFS_BASE_VOLTAGE_UV                                    500000
1105 #define DVFS_MAX_VOLTAGE_UV                                     1650000
1106 #define DVFS_VOLTAGE_STEP_UV                                    10000
1107
1108 /* Registers for function PMU_CONTROL */
1109 #define PALMAS_DEV_CTRL                                         0x0
1110 #define PALMAS_POWER_CTRL                                       0x1
1111 #define PALMAS_VSYS_LO                                          0x2
1112 #define PALMAS_VSYS_MON                                         0x3
1113 #define PALMAS_VBAT_MON                                         0x4
1114 #define PALMAS_WATCHDOG                                         0x5
1115 #define PALMAS_BOOT_STATUS                                      0x6
1116 #define PALMAS_BATTERY_BOUNCE                                   0x7
1117 #define PALMAS_BACKUP_BATTERY_CTRL                              0x8
1118 #define PALMAS_LONG_PRESS_KEY                                   0x9
1119 #define PALMAS_OSC_THERM_CTRL                                   0xA
1120 #define PALMAS_BATDEBOUNCING                                    0xB
1121 #define PALMAS_SWOFF_HWRST                                      0xF
1122 #define PALMAS_SWOFF_COLDRST                                    0x10
1123 #define PALMAS_SWOFF_STATUS                                     0x11
1124 #define PALMAS_PMU_CONFIG                                       0x12
1125 #define PALMAS_SPARE                                            0x14
1126 #define PALMAS_PMU_SECONDARY_INT                                0x15
1127 #define PALMAS_SW_REVISION                                      0x17
1128 #define PALMAS_EXT_CHRG_CTRL                                    0x18
1129 #define PALMAS_PMU_SECONDARY_INT2                               0x19
1130
1131 /* Bit definitions for DEV_CTRL */
1132 #define PALMAS_DEV_CTRL_DEV_STATUS_MASK                         0x0c
1133 #define PALMAS_DEV_CTRL_DEV_STATUS_SHIFT                        2
1134 #define PALMAS_DEV_CTRL_SW_RST                                  0x02
1135 #define PALMAS_DEV_CTRL_SW_RST_SHIFT                            1
1136 #define PALMAS_DEV_CTRL_DEV_ON                                  0x01
1137 #define PALMAS_DEV_CTRL_DEV_ON_SHIFT                            0
1138
1139 /* Bit definitions for POWER_CTRL */
1140 #define PALMAS_POWER_CTRL_ENABLE2_MASK                          0x04
1141 #define PALMAS_POWER_CTRL_ENABLE2_MASK_SHIFT                    2
1142 #define PALMAS_POWER_CTRL_ENABLE1_MASK                          0x02
1143 #define PALMAS_POWER_CTRL_ENABLE1_MASK_SHIFT                    1
1144 #define PALMAS_POWER_CTRL_NSLEEP_MASK                           0x01
1145 #define PALMAS_POWER_CTRL_NSLEEP_MASK_SHIFT                     0
1146
1147 /* Bit definitions for VSYS_LO */
1148 #define PALMAS_VSYS_LO_THRESHOLD_MASK                           0x1f
1149 #define PALMAS_VSYS_LO_THRESHOLD_SHIFT                          0
1150
1151 /* Bit definitions for VSYS_MON */
1152 #define PALMAS_VSYS_MON_ENABLE                                  0x80
1153 #define PALMAS_VSYS_MON_ENABLE_SHIFT                            7
1154 #define PALMAS_VSYS_MON_THRESHOLD_MASK                          0x3f
1155 #define PALMAS_VSYS_MON_THRESHOLD_SHIFT                         0
1156
1157 /* Bit definitions for VBAT_MON */
1158 #define PALMAS_VBAT_MON_ENABLE                                  0x80
1159 #define PALMAS_VBAT_MON_ENABLE_SHIFT                            7
1160 #define PALMAS_VBAT_MON_THRESHOLD_MASK                          0x3f
1161 #define PALMAS_VBAT_MON_THRESHOLD_SHIFT                         0
1162
1163 /* Bit definitions for WATCHDOG */
1164 #define PALMAS_WATCHDOG_LOCK                                    0x20
1165 #define PALMAS_WATCHDOG_LOCK_SHIFT                              5
1166 #define PALMAS_WATCHDOG_ENABLE                                  0x10
1167 #define PALMAS_WATCHDOG_ENABLE_SHIFT                            4
1168 #define PALMAS_WATCHDOG_MODE                                    0x08
1169 #define PALMAS_WATCHDOG_MODE_SHIFT                              3
1170 #define PALMAS_WATCHDOG_TIMER_MASK                              0x07
1171 #define PALMAS_WATCHDOG_TIMER_SHIFT                             0
1172
1173 /* Bit definitions for BOOT_STATUS */
1174 #define PALMAS_BOOT_STATUS_BOOT1                                0x02
1175 #define PALMAS_BOOT_STATUS_BOOT1_SHIFT                          1
1176 #define PALMAS_BOOT_STATUS_BOOT0                                0x01
1177 #define PALMAS_BOOT_STATUS_BOOT0_SHIFT                          0
1178
1179 /* Bit definitions for BATTERY_BOUNCE */
1180 #define PALMAS_BATTERY_BOUNCE_BB_DELAY_MASK                     0x3f
1181 #define PALMAS_BATTERY_BOUNCE_BB_DELAY_SHIFT                    0
1182
1183 /* Bit definitions for BACKUP_BATTERY_CTRL */
1184 #define PALMAS_BACKUP_BATTERY_CTRL_VRTC_18_15                   0x80
1185 #define PALMAS_BACKUP_BATTERY_CTRL_VRTC_18_15_SHIFT             7
1186 #define PALMAS_BACKUP_BATTERY_CTRL_VRTC_EN_SLP                  0x40
1187 #define PALMAS_BACKUP_BATTERY_CTRL_VRTC_EN_SLP_SHIFT            6
1188 #define PALMAS_BACKUP_BATTERY_CTRL_VRTC_EN_OFF                  0x20
1189 #define PALMAS_BACKUP_BATTERY_CTRL_VRTC_EN_OFF_SHIFT            5
1190 #define PALMAS_BACKUP_BATTERY_CTRL_VRTC_PWEN                    0x10
1191 #define PALMAS_BACKUP_BATTERY_CTRL_VRTC_PWEN_SHIFT              4
1192 #define PALMAS_BACKUP_BATTERY_CTRL_BBS_BBC_LOW_ICHRG            0x08
1193 #define PALMAS_BACKUP_BATTERY_CTRL_BBS_BBC_LOW_ICHRG_SHIFT      3
1194 #define PALMAS_BACKUP_BATTERY_CTRL_BB_SEL_MASK                  0x06
1195 #define PALMAS_BACKUP_BATTERY_CTRL_BB_SEL_SHIFT                 1
1196 #define PALMAS_BACKUP_BATTERY_CTRL_BB_CHG_EN                    0x01
1197 #define PALMAS_BACKUP_BATTERY_CTRL_BB_CHG_EN_SHIFT              0
1198
1199 /* Bit definitions for LONG_PRESS_KEY */
1200 #define PALMAS_LONG_PRESS_KEY_LPK_LOCK                          0x80
1201 #define PALMAS_LONG_PRESS_KEY_LPK_LOCK_SHIFT                    7
1202 #define PALMAS_LONG_PRESS_KEY_LPK_INT_CLR                       0x10
1203 #define PALMAS_LONG_PRESS_KEY_LPK_INT_CLR_SHIFT                 4
1204 #define PALMAS_LONG_PRESS_KEY_LPK_TIME_MASK                     0x0c
1205 #define PALMAS_LONG_PRESS_KEY_LPK_TIME_SHIFT                    2
1206 #define PALMAS_LONG_PRESS_KEY_PWRON_DEBOUNCE_MASK               0x03
1207 #define PALMAS_LONG_PRESS_KEY_PWRON_DEBOUNCE_SHIFT              0
1208
1209 /* Bit definitions for OSC_THERM_CTRL */
1210 #define PALMAS_OSC_THERM_CTRL_VANA_ON_IN_SLEEP                  0x80
1211 #define PALMAS_OSC_THERM_CTRL_VANA_ON_IN_SLEEP_SHIFT            7
1212 #define PALMAS_OSC_THERM_CTRL_INT_MASK_IN_SLEEP                 0x40
1213 #define PALMAS_OSC_THERM_CTRL_INT_MASK_IN_SLEEP_SHIFT           6
1214 #define PALMAS_OSC_THERM_CTRL_RC15MHZ_ON_IN_SLEEP               0x20
1215 #define PALMAS_OSC_THERM_CTRL_RC15MHZ_ON_IN_SLEEP_SHIFT         5
1216 #define PALMAS_OSC_THERM_CTRL_THERM_OFF_IN_SLEEP                0x10
1217 #define PALMAS_OSC_THERM_CTRL_THERM_OFF_IN_SLEEP_SHIFT          4
1218 #define PALMAS_OSC_THERM_CTRL_THERM_HD_SEL_MASK                 0x0c
1219 #define PALMAS_OSC_THERM_CTRL_THERM_HD_SEL_SHIFT                2
1220 #define PALMAS_OSC_THERM_CTRL_OSC_BYPASS                        0x02
1221 #define PALMAS_OSC_THERM_CTRL_OSC_BYPASS_SHIFT                  1
1222 #define PALMAS_OSC_THERM_CTRL_OSC_HPMODE                        0x01
1223 #define PALMAS_OSC_THERM_CTRL_OSC_HPMODE_SHIFT                  0
1224
1225 /* Bit definitions for BATDEBOUNCING */
1226 #define PALMAS_BATDEBOUNCING_BAT_DEB_BYPASS                     0x80
1227 #define PALMAS_BATDEBOUNCING_BAT_DEB_BYPASS_SHIFT               7
1228 #define PALMAS_BATDEBOUNCING_BINS_DEB_MASK                      0x78
1229 #define PALMAS_BATDEBOUNCING_BINS_DEB_SHIFT                     3
1230 #define PALMAS_BATDEBOUNCING_BEXT_DEB_MASK                      0x07
1231 #define PALMAS_BATDEBOUNCING_BEXT_DEB_SHIFT                     0
1232
1233 /* Bit definitions for SWOFF_HWRST */
1234 #define PALMAS_SWOFF_HWRST_PWRON_LPK                            0x80
1235 #define PALMAS_SWOFF_HWRST_PWRON_LPK_SHIFT                      7
1236 #define PALMAS_SWOFF_HWRST_PWRDOWN                              0x40
1237 #define PALMAS_SWOFF_HWRST_PWRDOWN_SHIFT                        6
1238 #define PALMAS_SWOFF_HWRST_WTD                                  0x20
1239 #define PALMAS_SWOFF_HWRST_WTD_SHIFT                            5
1240 #define PALMAS_SWOFF_HWRST_TSHUT                                0x10
1241 #define PALMAS_SWOFF_HWRST_TSHUT_SHIFT                          4
1242 #define PALMAS_SWOFF_HWRST_RESET_IN                             0x08
1243 #define PALMAS_SWOFF_HWRST_RESET_IN_SHIFT                       3
1244 #define PALMAS_SWOFF_HWRST_SW_RST                               0x04
1245 #define PALMAS_SWOFF_HWRST_SW_RST_SHIFT                         2
1246 #define PALMAS_SWOFF_HWRST_VSYS_LO                              0x02
1247 #define PALMAS_SWOFF_HWRST_VSYS_LO_SHIFT                        1
1248 #define PALMAS_SWOFF_HWRST_GPADC_SHUTDOWN                       0x01
1249 #define PALMAS_SWOFF_HWRST_GPADC_SHUTDOWN_SHIFT                 0
1250
1251 /* Bit definitions for SWOFF_COLDRST */
1252 #define PALMAS_SWOFF_COLDRST_PWRON_LPK                          0x80
1253 #define PALMAS_SWOFF_COLDRST_PWRON_LPK_SHIFT                    7
1254 #define PALMAS_SWOFF_COLDRST_PWRDOWN                            0x40
1255 #define PALMAS_SWOFF_COLDRST_PWRDOWN_SHIFT                      6
1256 #define PALMAS_SWOFF_COLDRST_WTD                                0x20
1257 #define PALMAS_SWOFF_COLDRST_WTD_SHIFT                          5
1258 #define PALMAS_SWOFF_COLDRST_TSHUT                              0x10
1259 #define PALMAS_SWOFF_COLDRST_TSHUT_SHIFT                        4
1260 #define PALMAS_SWOFF_COLDRST_RESET_IN                           0x08
1261 #define PALMAS_SWOFF_COLDRST_RESET_IN_SHIFT                     3
1262 #define PALMAS_SWOFF_COLDRST_SW_RST                             0x04
1263 #define PALMAS_SWOFF_COLDRST_SW_RST_SHIFT                       2
1264 #define PALMAS_SWOFF_COLDRST_VSYS_LO                            0x02
1265 #define PALMAS_SWOFF_COLDRST_VSYS_LO_SHIFT                      1
1266 #define PALMAS_SWOFF_COLDRST_GPADC_SHUTDOWN                     0x01
1267 #define PALMAS_SWOFF_COLDRST_GPADC_SHUTDOWN_SHIFT               0
1268
1269 /* Bit definitions for SWOFF_STATUS */
1270 #define PALMAS_SWOFF_STATUS_PWRON_LPK                           0x80
1271 #define PALMAS_SWOFF_STATUS_PWRON_LPK_SHIFT                     7
1272 #define PALMAS_SWOFF_STATUS_PWRDOWN                             0x40
1273 #define PALMAS_SWOFF_STATUS_PWRDOWN_SHIFT                       6
1274 #define PALMAS_SWOFF_STATUS_WTD                                 0x20
1275 #define PALMAS_SWOFF_STATUS_WTD_SHIFT                           5
1276 #define PALMAS_SWOFF_STATUS_TSHUT                               0x10
1277 #define PALMAS_SWOFF_STATUS_TSHUT_SHIFT                         4
1278 #define PALMAS_SWOFF_STATUS_RESET_IN                            0x08
1279 #define PALMAS_SWOFF_STATUS_RESET_IN_SHIFT                      3
1280 #define PALMAS_SWOFF_STATUS_SW_RST                              0x04
1281 #define PALMAS_SWOFF_STATUS_SW_RST_SHIFT                        2
1282 #define PALMAS_SWOFF_STATUS_VSYS_LO                             0x02
1283 #define PALMAS_SWOFF_STATUS_VSYS_LO_SHIFT                       1
1284 #define PALMAS_SWOFF_STATUS_GPADC_SHUTDOWN                      0x01
1285 #define PALMAS_SWOFF_STATUS_GPADC_SHUTDOWN_SHIFT                0
1286
1287 /* Bit definitions for PMU_CONFIG */
1288 #define PALMAS_PMU_CONFIG_MULTI_CELL_EN                         0x40
1289 #define PALMAS_PMU_CONFIG_MULTI_CELL_EN_SHIFT                   6
1290 #define PALMAS_PMU_CONFIG_SPARE_MASK                            0x30
1291 #define PALMAS_PMU_CONFIG_SPARE_SHIFT                           4
1292 #define PALMAS_PMU_CONFIG_SWOFF_DLY_MASK                        0x0c
1293 #define PALMAS_PMU_CONFIG_SWOFF_DLY_SHIFT                       2
1294 #define PALMAS_PMU_CONFIG_GATE_RESET_OUT                        0x02
1295 #define PALMAS_PMU_CONFIG_GATE_RESET_OUT_SHIFT                  1
1296 #define PALMAS_PMU_CONFIG_AUTODEVON                             0x01
1297 #define PALMAS_PMU_CONFIG_AUTODEVON_SHIFT                       0
1298
1299 /* Bit definitions for SPARE */
1300 #define PALMAS_SPARE_SPARE_MASK                                 0xf8
1301 #define PALMAS_SPARE_SPARE_SHIFT                                3
1302 #define PALMAS_SPARE_REGEN3_OD                                  0x04
1303 #define PALMAS_SPARE_REGEN3_OD_SHIFT                            2
1304 #define PALMAS_SPARE_REGEN2_OD                                  0x02
1305 #define PALMAS_SPARE_REGEN2_OD_SHIFT                            1
1306 #define PALMAS_SPARE_REGEN1_OD                                  0x01
1307 #define PALMAS_SPARE_REGEN1_OD_SHIFT                            0
1308
1309 /* Bit definitions for PMU_SECONDARY_INT */
1310 #define PALMAS_PMU_SECONDARY_INT_VBUS_OVV_INT_SRC               0x80
1311 #define PALMAS_PMU_SECONDARY_INT_VBUS_OVV_INT_SRC_SHIFT         7
1312 #define PALMAS_PMU_SECONDARY_INT_CHARG_DET_N_INT_SRC            0x40
1313 #define PALMAS_PMU_SECONDARY_INT_CHARG_DET_N_INT_SRC_SHIFT      6
1314 #define PALMAS_PMU_SECONDARY_INT_BB_INT_SRC                     0x20
1315 #define PALMAS_PMU_SECONDARY_INT_BB_INT_SRC_SHIFT               5
1316 #define PALMAS_PMU_SECONDARY_INT_FBI_INT_SRC                    0x10
1317 #define PALMAS_PMU_SECONDARY_INT_FBI_INT_SRC_SHIFT              4
1318 #define PALMAS_PMU_SECONDARY_INT_VBUS_OVV_MASK                  0x08
1319 #define PALMAS_PMU_SECONDARY_INT_VBUS_OVV_MASK_SHIFT            3
1320 #define PALMAS_PMU_SECONDARY_INT_CHARG_DET_N_MASK               0x04
1321 #define PALMAS_PMU_SECONDARY_INT_CHARG_DET_N_MASK_SHIFT         2
1322 #define PALMAS_PMU_SECONDARY_INT_BB_MASK                        0x02
1323 #define PALMAS_PMU_SECONDARY_INT_BB_MASK_SHIFT                  1
1324 #define PALMAS_PMU_SECONDARY_INT_FBI_MASK                       0x01
1325 #define PALMAS_PMU_SECONDARY_INT_FBI_MASK_SHIFT                 0
1326
1327 /* Bit definitions for SW_REVISION */
1328 #define PALMAS_SW_REVISION_SW_REVISION_MASK                     0xff
1329 #define PALMAS_SW_REVISION_SW_REVISION_SHIFT                    0
1330
1331 /* Bit definitions for EXT_CHRG_CTRL */
1332 #define PALMAS_EXT_CHRG_CTRL_VBUS_OVV_STATUS                    0x80
1333 #define PALMAS_EXT_CHRG_CTRL_VBUS_OVV_STATUS_SHIFT              7
1334 #define PALMAS_EXT_CHRG_CTRL_CHARG_DET_N_STATUS                 0x40
1335 #define PALMAS_EXT_CHRG_CTRL_CHARG_DET_N_STATUS_SHIFT           6
1336 #define PALMAS_EXT_CHRG_CTRL_VSYS_DEBOUNCE_DELAY                0x08
1337 #define PALMAS_EXT_CHRG_CTRL_VSYS_DEBOUNCE_DELAY_SHIFT          3
1338 #define PALMAS_EXT_CHRG_CTRL_CHRG_DET_N                         0x04
1339 #define PALMAS_EXT_CHRG_CTRL_CHRG_DET_N_SHIFT                   2
1340 #define PALMAS_EXT_CHRG_CTRL_AUTO_ACA_EN                        0x02
1341 #define PALMAS_EXT_CHRG_CTRL_AUTO_ACA_EN_SHIFT                  1
1342 #define PALMAS_EXT_CHRG_CTRL_AUTO_LDOUSB_EN                     0x01
1343 #define PALMAS_EXT_CHRG_CTRL_AUTO_LDOUSB_EN_SHIFT               0
1344
1345 /* Bit definitions for PMU_SECONDARY_INT2 */
1346 #define PALMAS_PMU_SECONDARY_INT2_DVFS2_INT_SRC                 0x20
1347 #define PALMAS_PMU_SECONDARY_INT2_DVFS2_INT_SRC_SHIFT           5
1348 #define PALMAS_PMU_SECONDARY_INT2_DVFS1_INT_SRC                 0x10
1349 #define PALMAS_PMU_SECONDARY_INT2_DVFS1_INT_SRC_SHIFT           4
1350 #define PALMAS_PMU_SECONDARY_INT2_DVFS2_MASK                    0x02
1351 #define PALMAS_PMU_SECONDARY_INT2_DVFS2_MASK_SHIFT              1
1352 #define PALMAS_PMU_SECONDARY_INT2_DVFS1_MASK                    0x01
1353 #define PALMAS_PMU_SECONDARY_INT2_DVFS1_MASK_SHIFT              0
1354
1355 /* Registers for function RESOURCE */
1356 #define PALMAS_CLK32KG_CTRL                                     0x0
1357 #define PALMAS_CLK32KGAUDIO_CTRL                                0x1
1358 #define PALMAS_REGEN1_CTRL                                      0x2
1359 #define PALMAS_REGEN2_CTRL                                      0x3
1360 #define PALMAS_SYSEN1_CTRL                                      0x4
1361 #define PALMAS_SYSEN2_CTRL                                      0x5
1362 #define PALMAS_NSLEEP_RES_ASSIGN                                0x6
1363 #define PALMAS_NSLEEP_SMPS_ASSIGN                               0x7
1364 #define PALMAS_NSLEEP_LDO_ASSIGN1                               0x8
1365 #define PALMAS_NSLEEP_LDO_ASSIGN2                               0x9
1366 #define PALMAS_ENABLE1_RES_ASSIGN                               0xA
1367 #define PALMAS_ENABLE1_SMPS_ASSIGN                              0xB
1368 #define PALMAS_ENABLE1_LDO_ASSIGN1                              0xC
1369 #define PALMAS_ENABLE1_LDO_ASSIGN2                              0xD
1370 #define PALMAS_ENABLE2_RES_ASSIGN                               0xE
1371 #define PALMAS_ENABLE2_SMPS_ASSIGN                              0xF
1372 #define PALMAS_ENABLE2_LDO_ASSIGN1                              0x10
1373 #define PALMAS_ENABLE2_LDO_ASSIGN2                              0x11
1374 #define PALMAS_REGEN3_CTRL                                      0x12
1375
1376 /* Bit definitions for CLK32KG_CTRL */
1377 #define PALMAS_CLK32KG_CTRL_STATUS                              0x10
1378 #define PALMAS_CLK32KG_CTRL_STATUS_SHIFT                        4
1379 #define PALMAS_CLK32KG_CTRL_MODE_SLEEP                          0x04
1380 #define PALMAS_CLK32KG_CTRL_MODE_SLEEP_SHIFT                    2
1381 #define PALMAS_CLK32KG_CTRL_MODE_ACTIVE                         0x01
1382 #define PALMAS_CLK32KG_CTRL_MODE_ACTIVE_SHIFT                   0
1383
1384 /* Bit definitions for CLK32KGAUDIO_CTRL */
1385 #define PALMAS_CLK32KGAUDIO_CTRL_STATUS                         0x10
1386 #define PALMAS_CLK32KGAUDIO_CTRL_STATUS_SHIFT                   4
1387 #define PALMAS_CLK32KGAUDIO_CTRL_RESERVED3                      0x08
1388 #define PALMAS_CLK32KGAUDIO_CTRL_RESERVED3_SHIFT                3
1389 #define PALMAS_CLK32KGAUDIO_CTRL_MODE_SLEEP                     0x04
1390 #define PALMAS_CLK32KGAUDIO_CTRL_MODE_SLEEP_SHIFT               2
1391 #define PALMAS_CLK32KGAUDIO_CTRL_MODE_ACTIVE                    0x01
1392 #define PALMAS_CLK32KGAUDIO_CTRL_MODE_ACTIVE_SHIFT              0
1393
1394 /* Bit definitions for REGEN1_CTRL */
1395 #define PALMAS_REGEN1_CTRL_STATUS                               0x10
1396 #define PALMAS_REGEN1_CTRL_STATUS_SHIFT                         4
1397 #define PALMAS_REGEN1_CTRL_MODE_SLEEP                           0x04
1398 #define PALMAS_REGEN1_CTRL_MODE_SLEEP_SHIFT                     2
1399 #define PALMAS_REGEN1_CTRL_MODE_ACTIVE                          0x01
1400 #define PALMAS_REGEN1_CTRL_MODE_ACTIVE_SHIFT                    0
1401
1402 /* Bit definitions for REGEN2_CTRL */
1403 #define PALMAS_REGEN2_CTRL_STATUS                               0x10
1404 #define PALMAS_REGEN2_CTRL_STATUS_SHIFT                         4
1405 #define PALMAS_REGEN2_CTRL_MODE_SLEEP                           0x04
1406 #define PALMAS_REGEN2_CTRL_MODE_SLEEP_SHIFT                     2
1407 #define PALMAS_REGEN2_CTRL_MODE_ACTIVE                          0x01
1408 #define PALMAS_REGEN2_CTRL_MODE_ACTIVE_SHIFT                    0
1409
1410 /* Bit definitions for SYSEN1_CTRL */
1411 #define PALMAS_SYSEN1_CTRL_STATUS                               0x10
1412 #define PALMAS_SYSEN1_CTRL_STATUS_SHIFT                         4
1413 #define PALMAS_SYSEN1_CTRL_MODE_SLEEP                           0x04
1414 #define PALMAS_SYSEN1_CTRL_MODE_SLEEP_SHIFT                     2
1415 #define PALMAS_SYSEN1_CTRL_MODE_ACTIVE                          0x01
1416 #define PALMAS_SYSEN1_CTRL_MODE_ACTIVE_SHIFT                    0
1417
1418 /* Bit definitions for SYSEN2_CTRL */
1419 #define PALMAS_SYSEN2_CTRL_STATUS                               0x10
1420 #define PALMAS_SYSEN2_CTRL_STATUS_SHIFT                         4
1421 #define PALMAS_SYSEN2_CTRL_MODE_SLEEP                           0x04
1422 #define PALMAS_SYSEN2_CTRL_MODE_SLEEP_SHIFT                     2
1423 #define PALMAS_SYSEN2_CTRL_MODE_ACTIVE                          0x01
1424 #define PALMAS_SYSEN2_CTRL_MODE_ACTIVE_SHIFT                    0
1425
1426 /* Bit definitions for NSLEEP_RES_ASSIGN */
1427 #define PALMAS_NSLEEP_RES_ASSIGN_REGEN3                         0x40
1428 #define PALMAS_NSLEEP_RES_ASSIGN_REGEN3_SHIFT                   6
1429 #define PALMAS_NSLEEP_RES_ASSIGN_CLK32KGAUDIO                   0x20
1430 #define PALMAS_NSLEEP_RES_ASSIGN_CLK32KGAUDIO_SHIFT             5
1431 #define PALMAS_NSLEEP_RES_ASSIGN_CLK32KG                        0x10
1432 #define PALMAS_NSLEEP_RES_ASSIGN_CLK32KG_SHIFT                  4
1433 #define PALMAS_NSLEEP_RES_ASSIGN_SYSEN2                         0x08
1434 #define PALMAS_NSLEEP_RES_ASSIGN_SYSEN2_SHIFT                   3
1435 #define PALMAS_NSLEEP_RES_ASSIGN_SYSEN1                         0x04
1436 #define PALMAS_NSLEEP_RES_ASSIGN_SYSEN1_SHIFT                   2
1437 #define PALMAS_NSLEEP_RES_ASSIGN_REGEN2                         0x02
1438 #define PALMAS_NSLEEP_RES_ASSIGN_REGEN2_SHIFT                   1
1439 #define PALMAS_NSLEEP_RES_ASSIGN_REGEN1                         0x01
1440 #define PALMAS_NSLEEP_RES_ASSIGN_REGEN1_SHIFT                   0
1441
1442 /* Bit definitions for NSLEEP_SMPS_ASSIGN */
1443 #define PALMAS_NSLEEP_SMPS_ASSIGN_SMPS10                        0x80
1444 #define PALMAS_NSLEEP_SMPS_ASSIGN_SMPS10_SHIFT                  7
1445 #define PALMAS_NSLEEP_SMPS_ASSIGN_SMPS9                         0x40
1446 #define PALMAS_NSLEEP_SMPS_ASSIGN_SMPS9_SHIFT                   6
1447 #define PALMAS_NSLEEP_SMPS_ASSIGN_SMPS8                         0x20
1448 #define PALMAS_NSLEEP_SMPS_ASSIGN_SMPS8_SHIFT                   5
1449 #define PALMAS_NSLEEP_SMPS_ASSIGN_SMPS7                         0x10
1450 #define PALMAS_NSLEEP_SMPS_ASSIGN_SMPS7_SHIFT                   4
1451 #define PALMAS_NSLEEP_SMPS_ASSIGN_SMPS6                         0x08
1452 #define PALMAS_NSLEEP_SMPS_ASSIGN_SMPS6_SHIFT                   3
1453 #define PALMAS_NSLEEP_SMPS_ASSIGN_SMPS45                        0x04
1454 #define PALMAS_NSLEEP_SMPS_ASSIGN_SMPS45_SHIFT                  2
1455 #define PALMAS_NSLEEP_SMPS_ASSIGN_SMPS3                         0x02
1456 #define PALMAS_NSLEEP_SMPS_ASSIGN_SMPS3_SHIFT                   1
1457 #define PALMAS_NSLEEP_SMPS_ASSIGN_SMPS12                        0x01
1458 #define PALMAS_NSLEEP_SMPS_ASSIGN_SMPS12_SHIFT                  0
1459
1460 /* Bit definitions for NSLEEP_LDO_ASSIGN1 */
1461 #define PALMAS_NSLEEP_LDO_ASSIGN1_LDO8                          0x80
1462 #define PALMAS_NSLEEP_LDO_ASSIGN1_LDO8_SHIFT                    7
1463 #define PALMAS_NSLEEP_LDO_ASSIGN1_LDO7                          0x40
1464 #define PALMAS_NSLEEP_LDO_ASSIGN1_LDO7_SHIFT                    6
1465 #define PALMAS_NSLEEP_LDO_ASSIGN1_LDO6                          0x20
1466 #define PALMAS_NSLEEP_LDO_ASSIGN1_LDO6_SHIFT                    5
1467 #define PALMAS_NSLEEP_LDO_ASSIGN1_LDO5                          0x10
1468 #define PALMAS_NSLEEP_LDO_ASSIGN1_LDO5_SHIFT                    4
1469 #define PALMAS_NSLEEP_LDO_ASSIGN1_LDO4                          0x08
1470 #define PALMAS_NSLEEP_LDO_ASSIGN1_LDO4_SHIFT                    3
1471 #define PALMAS_NSLEEP_LDO_ASSIGN1_LDO3                          0x04
1472 #define PALMAS_NSLEEP_LDO_ASSIGN1_LDO3_SHIFT                    2
1473 #define PALMAS_NSLEEP_LDO_ASSIGN1_LDO2                          0x02
1474 #define PALMAS_NSLEEP_LDO_ASSIGN1_LDO2_SHIFT                    1
1475 #define PALMAS_NSLEEP_LDO_ASSIGN1_LDO1                          0x01
1476 #define PALMAS_NSLEEP_LDO_ASSIGN1_LDO1_SHIFT                    0
1477
1478 /* Bit definitions for NSLEEP_LDO_ASSIGN2 */
1479 #define PALMAS_NSLEEP_LDO_ASSIGN2_LDOUSB                        0x04
1480 #define PALMAS_NSLEEP_LDO_ASSIGN2_LDOUSB_SHIFT                  2
1481 #define PALMAS_NSLEEP_LDO_ASSIGN2_LDOLN                         0x02
1482 #define PALMAS_NSLEEP_LDO_ASSIGN2_LDOLN_SHIFT                   1
1483 #define PALMAS_NSLEEP_LDO_ASSIGN2_LDO9                          0x01
1484 #define PALMAS_NSLEEP_LDO_ASSIGN2_LDO9_SHIFT                    0
1485
1486 /* Bit definitions for ENABLE1_RES_ASSIGN */
1487 #define PALMAS_ENABLE1_RES_ASSIGN_REGEN3                        0x40
1488 #define PALMAS_ENABLE1_RES_ASSIGN_REGEN3_SHIFT                  6
1489 #define PALMAS_ENABLE1_RES_ASSIGN_CLK32KGAUDIO                  0x20
1490 #define PALMAS_ENABLE1_RES_ASSIGN_CLK32KGAUDIO_SHIFT            5
1491 #define PALMAS_ENABLE1_RES_ASSIGN_CLK32KG                       0x10
1492 #define PALMAS_ENABLE1_RES_ASSIGN_CLK32KG_SHIFT                 4
1493 #define PALMAS_ENABLE1_RES_ASSIGN_SYSEN2                        0x08
1494 #define PALMAS_ENABLE1_RES_ASSIGN_SYSEN2_SHIFT                  3
1495 #define PALMAS_ENABLE1_RES_ASSIGN_SYSEN1                        0x04
1496 #define PALMAS_ENABLE1_RES_ASSIGN_SYSEN1_SHIFT                  2
1497 #define PALMAS_ENABLE1_RES_ASSIGN_REGEN2                        0x02
1498 #define PALMAS_ENABLE1_RES_ASSIGN_REGEN2_SHIFT                  1
1499 #define PALMAS_ENABLE1_RES_ASSIGN_REGEN1                        0x01
1500 #define PALMAS_ENABLE1_RES_ASSIGN_REGEN1_SHIFT                  0
1501
1502 /* Bit definitions for ENABLE1_SMPS_ASSIGN */
1503 #define PALMAS_ENABLE1_SMPS_ASSIGN_SMPS10                       0x80
1504 #define PALMAS_ENABLE1_SMPS_ASSIGN_SMPS10_SHIFT                 7
1505 #define PALMAS_ENABLE1_SMPS_ASSIGN_SMPS9                        0x40
1506 #define PALMAS_ENABLE1_SMPS_ASSIGN_SMPS9_SHIFT                  6
1507 #define PALMAS_ENABLE1_SMPS_ASSIGN_SMPS8                        0x20
1508 #define PALMAS_ENABLE1_SMPS_ASSIGN_SMPS8_SHIFT                  5
1509 #define PALMAS_ENABLE1_SMPS_ASSIGN_SMPS7                        0x10
1510 #define PALMAS_ENABLE1_SMPS_ASSIGN_SMPS7_SHIFT                  4
1511 #define PALMAS_ENABLE1_SMPS_ASSIGN_SMPS6                        0x08
1512 #define PALMAS_ENABLE1_SMPS_ASSIGN_SMPS6_SHIFT                  3
1513 #define PALMAS_ENABLE1_SMPS_ASSIGN_SMPS45                       0x04
1514 #define PALMAS_ENABLE1_SMPS_ASSIGN_SMPS45_SHIFT                 2
1515 #define PALMAS_ENABLE1_SMPS_ASSIGN_SMPS3                        0x02
1516 #define PALMAS_ENABLE1_SMPS_ASSIGN_SMPS3_SHIFT                  1
1517 #define PALMAS_ENABLE1_SMPS_ASSIGN_SMPS12                       0x01
1518 #define PALMAS_ENABLE1_SMPS_ASSIGN_SMPS12_SHIFT                 0
1519
1520 /* Bit definitions for ENABLE1_LDO_ASSIGN1 */
1521 #define PALMAS_ENABLE1_LDO_ASSIGN1_LDO8                         0x80
1522 #define PALMAS_ENABLE1_LDO_ASSIGN1_LDO8_SHIFT                   7
1523 #define PALMAS_ENABLE1_LDO_ASSIGN1_LDO7                         0x40
1524 #define PALMAS_ENABLE1_LDO_ASSIGN1_LDO7_SHIFT                   6
1525 #define PALMAS_ENABLE1_LDO_ASSIGN1_LDO6                         0x20
1526 #define PALMAS_ENABLE1_LDO_ASSIGN1_LDO6_SHIFT                   5
1527 #define PALMAS_ENABLE1_LDO_ASSIGN1_LDO5                         0x10
1528 #define PALMAS_ENABLE1_LDO_ASSIGN1_LDO5_SHIFT                   4
1529 #define PALMAS_ENABLE1_LDO_ASSIGN1_LDO4                         0x08
1530 #define PALMAS_ENABLE1_LDO_ASSIGN1_LDO4_SHIFT                   3
1531 #define PALMAS_ENABLE1_LDO_ASSIGN1_LDO3                         0x04
1532 #define PALMAS_ENABLE1_LDO_ASSIGN1_LDO3_SHIFT                   2
1533 #define PALMAS_ENABLE1_LDO_ASSIGN1_LDO2                         0x02
1534 #define PALMAS_ENABLE1_LDO_ASSIGN1_LDO2_SHIFT                   1
1535 #define PALMAS_ENABLE1_LDO_ASSIGN1_LDO1                         0x01
1536 #define PALMAS_ENABLE1_LDO_ASSIGN1_LDO1_SHIFT                   0
1537
1538 /* Bit definitions for ENABLE1_LDO_ASSIGN2 */
1539 #define PALMAS_ENABLE1_LDO_ASSIGN2_LDOUSB                       0x04
1540 #define PALMAS_ENABLE1_LDO_ASSIGN2_LDOUSB_SHIFT                 2
1541 #define PALMAS_ENABLE1_LDO_ASSIGN2_LDOLN                        0x02
1542 #define PALMAS_ENABLE1_LDO_ASSIGN2_LDOLN_SHIFT                  1
1543 #define PALMAS_ENABLE1_LDO_ASSIGN2_LDO9                         0x01
1544 #define PALMAS_ENABLE1_LDO_ASSIGN2_LDO9_SHIFT                   0
1545
1546 /* Bit definitions for ENABLE2_RES_ASSIGN */
1547 #define PALMAS_ENABLE2_RES_ASSIGN_REGEN3                        0x40
1548 #define PALMAS_ENABLE2_RES_ASSIGN_REGEN3_SHIFT                  6
1549 #define PALMAS_ENABLE2_RES_ASSIGN_CLK32KGAUDIO                  0x20
1550 #define PALMAS_ENABLE2_RES_ASSIGN_CLK32KGAUDIO_SHIFT            5
1551 #define PALMAS_ENABLE2_RES_ASSIGN_CLK32KG                       0x10
1552 #define PALMAS_ENABLE2_RES_ASSIGN_CLK32KG_SHIFT                 4
1553 #define PALMAS_ENABLE2_RES_ASSIGN_SYSEN2                        0x08
1554 #define PALMAS_ENABLE2_RES_ASSIGN_SYSEN2_SHIFT                  3
1555 #define PALMAS_ENABLE2_RES_ASSIGN_SYSEN1                        0x04
1556 #define PALMAS_ENABLE2_RES_ASSIGN_SYSEN1_SHIFT                  2
1557 #define PALMAS_ENABLE2_RES_ASSIGN_REGEN2                        0x02
1558 #define PALMAS_ENABLE2_RES_ASSIGN_REGEN2_SHIFT                  1
1559 #define PALMAS_ENABLE2_RES_ASSIGN_REGEN1                        0x01
1560 #define PALMAS_ENABLE2_RES_ASSIGN_REGEN1_SHIFT                  0
1561
1562 /* Bit definitions for ENABLE2_SMPS_ASSIGN */
1563 #define PALMAS_ENABLE2_SMPS_ASSIGN_SMPS10                       0x80
1564 #define PALMAS_ENABLE2_SMPS_ASSIGN_SMPS10_SHIFT                 7
1565 #define PALMAS_ENABLE2_SMPS_ASSIGN_SMPS9                        0x40
1566 #define PALMAS_ENABLE2_SMPS_ASSIGN_SMPS9_SHIFT                  6
1567 #define PALMAS_ENABLE2_SMPS_ASSIGN_SMPS8                        0x20
1568 #define PALMAS_ENABLE2_SMPS_ASSIGN_SMPS8_SHIFT                  5
1569 #define PALMAS_ENABLE2_SMPS_ASSIGN_SMPS7                        0x10
1570 #define PALMAS_ENABLE2_SMPS_ASSIGN_SMPS7_SHIFT                  4
1571 #define PALMAS_ENABLE2_SMPS_ASSIGN_SMPS6                        0x08
1572 #define PALMAS_ENABLE2_SMPS_ASSIGN_SMPS6_SHIFT                  3
1573 #define PALMAS_ENABLE2_SMPS_ASSIGN_SMPS45                       0x04
1574 #define PALMAS_ENABLE2_SMPS_ASSIGN_SMPS45_SHIFT                 2
1575 #define PALMAS_ENABLE2_SMPS_ASSIGN_SMPS3                        0x02
1576 #define PALMAS_ENABLE2_SMPS_ASSIGN_SMPS3_SHIFT                  1
1577 #define PALMAS_ENABLE2_SMPS_ASSIGN_SMPS12                       0x01
1578 #define PALMAS_ENABLE2_SMPS_ASSIGN_SMPS12_SHIFT                 0
1579
1580 /* Bit definitions for ENABLE2_LDO_ASSIGN1 */
1581 #define PALMAS_ENABLE2_LDO_ASSIGN1_LDO8                         0x80
1582 #define PALMAS_ENABLE2_LDO_ASSIGN1_LDO8_SHIFT                   7
1583 #define PALMAS_ENABLE2_LDO_ASSIGN1_LDO7                         0x40
1584 #define PALMAS_ENABLE2_LDO_ASSIGN1_LDO7_SHIFT                   6
1585 #define PALMAS_ENABLE2_LDO_ASSIGN1_LDO6                         0x20
1586 #define PALMAS_ENABLE2_LDO_ASSIGN1_LDO6_SHIFT                   5
1587 #define PALMAS_ENABLE2_LDO_ASSIGN1_LDO5                         0x10
1588 #define PALMAS_ENABLE2_LDO_ASSIGN1_LDO5_SHIFT                   4
1589 #define PALMAS_ENABLE2_LDO_ASSIGN1_LDO4                         0x08
1590 #define PALMAS_ENABLE2_LDO_ASSIGN1_LDO4_SHIFT                   3
1591 #define PALMAS_ENABLE2_LDO_ASSIGN1_LDO3                         0x04
1592 #define PALMAS_ENABLE2_LDO_ASSIGN1_LDO3_SHIFT                   2
1593 #define PALMAS_ENABLE2_LDO_ASSIGN1_LDO2                         0x02
1594 #define PALMAS_ENABLE2_LDO_ASSIGN1_LDO2_SHIFT                   1
1595 #define PALMAS_ENABLE2_LDO_ASSIGN1_LDO1                         0x01
1596 #define PALMAS_ENABLE2_LDO_ASSIGN1_LDO1_SHIFT                   0
1597
1598 /* Bit definitions for ENABLE2_LDO_ASSIGN2 */
1599 #define PALMAS_ENABLE2_LDO_ASSIGN2_LDOUSB                       0x04
1600 #define PALMAS_ENABLE2_LDO_ASSIGN2_LDOUSB_SHIFT                 2
1601 #define PALMAS_ENABLE2_LDO_ASSIGN2_LDOLN                        0x02
1602 #define PALMAS_ENABLE2_LDO_ASSIGN2_LDOLN_SHIFT                  1
1603 #define PALMAS_ENABLE2_LDO_ASSIGN2_LDO9                         0x01
1604 #define PALMAS_ENABLE2_LDO_ASSIGN2_LDO9_SHIFT                   0
1605
1606 /* Bit definitions for REGEN3_CTRL */
1607 #define PALMAS_REGEN3_CTRL_STATUS                               0x10
1608 #define PALMAS_REGEN3_CTRL_STATUS_SHIFT                         4
1609 #define PALMAS_REGEN3_CTRL_MODE_SLEEP                           0x04
1610 #define PALMAS_REGEN3_CTRL_MODE_SLEEP_SHIFT                     2
1611 #define PALMAS_REGEN3_CTRL_MODE_ACTIVE                          0x01
1612 #define PALMAS_REGEN3_CTRL_MODE_ACTIVE_SHIFT                    0
1613
1614 /* Registers for function PAD_CONTROL */
1615 #define PALMAS_PU_PD_INPUT_CTRL1                                0x0
1616 #define PALMAS_PU_PD_INPUT_CTRL2                                0x1
1617 #define PALMAS_PU_PD_INPUT_CTRL3                                0x2
1618 #define PALMAS_OD_OUTPUT_CTRL                                   0x4
1619 #define PALMAS_POLARITY_CTRL                                    0x5
1620 #define PALMAS_PRIMARY_SECONDARY_PAD1                           0x6
1621 #define PALMAS_PRIMARY_SECONDARY_PAD2                           0x7
1622 #define PALMAS_I2C_SPI                                          0x8
1623 #define PALMAS_PU_PD_INPUT_CTRL4                                0x9
1624 #define PALMAS_PRIMARY_SECONDARY_PAD3                           0xA
1625
1626 /* Bit definitions for PU_PD_INPUT_CTRL1 */
1627 #define PALMAS_PU_PD_INPUT_CTRL1_RESET_IN_PD                    0x40
1628 #define PALMAS_PU_PD_INPUT_CTRL1_RESET_IN_PD_SHIFT              6
1629 #define PALMAS_PU_PD_INPUT_CTRL1_GPADC_START_PU                 0x20
1630 #define PALMAS_PU_PD_INPUT_CTRL1_GPADC_START_PU_SHIFT           5
1631 #define PALMAS_PU_PD_INPUT_CTRL1_GPADC_START_PD                 0x10
1632 #define PALMAS_PU_PD_INPUT_CTRL1_GPADC_START_PD_SHIFT           4
1633 #define PALMAS_PU_PD_INPUT_CTRL1_PWRDOWN_PD                     0x04
1634 #define PALMAS_PU_PD_INPUT_CTRL1_PWRDOWN_PD_SHIFT               2
1635 #define PALMAS_PU_PD_INPUT_CTRL1_NRESWARM_PU                    0x02
1636 #define PALMAS_PU_PD_INPUT_CTRL1_NRESWARM_PU_SHIFT              1
1637
1638 /* Bit definitions for PU_PD_INPUT_CTRL2 */
1639 #define PALMAS_PU_PD_INPUT_CTRL2_ENABLE2_PU                     0x20
1640 #define PALMAS_PU_PD_INPUT_CTRL2_ENABLE2_PU_SHIFT               5
1641 #define PALMAS_PU_PD_INPUT_CTRL2_ENABLE2_PD                     0x10
1642 #define PALMAS_PU_PD_INPUT_CTRL2_ENABLE2_PD_SHIFT               4
1643 #define PALMAS_PU_PD_INPUT_CTRL2_ENABLE1_PU                     0x08
1644 #define PALMAS_PU_PD_INPUT_CTRL2_ENABLE1_PU_SHIFT               3
1645 #define PALMAS_PU_PD_INPUT_CTRL2_ENABLE1_PD                     0x04
1646 #define PALMAS_PU_PD_INPUT_CTRL2_ENABLE1_PD_SHIFT               2
1647 #define PALMAS_PU_PD_INPUT_CTRL2_NSLEEP_PU                      0x02
1648 #define PALMAS_PU_PD_INPUT_CTRL2_NSLEEP_PU_SHIFT                1
1649 #define PALMAS_PU_PD_INPUT_CTRL2_NSLEEP_PD                      0x01
1650 #define PALMAS_PU_PD_INPUT_CTRL2_NSLEEP_PD_SHIFT                0
1651
1652 /* Bit definitions for PU_PD_INPUT_CTRL3 */
1653 #define PALMAS_PU_PD_INPUT_CTRL3_ACOK_PD                        0x40
1654 #define PALMAS_PU_PD_INPUT_CTRL3_ACOK_PD_SHIFT                  6
1655 #define PALMAS_PU_PD_INPUT_CTRL3_CHRG_DET_N_PD                  0x10
1656 #define PALMAS_PU_PD_INPUT_CTRL3_CHRG_DET_N_PD_SHIFT            4
1657 #define PALMAS_PU_PD_INPUT_CTRL3_POWERHOLD_PD                   0x04
1658 #define PALMAS_PU_PD_INPUT_CTRL3_POWERHOLD_PD_SHIFT             2
1659 #define PALMAS_PU_PD_INPUT_CTRL3_MSECURE_PD                     0x01
1660 #define PALMAS_PU_PD_INPUT_CTRL3_MSECURE_PD_SHIFT               0
1661
1662 /* Bit definitions for OD_OUTPUT_CTRL */
1663 #define PALMAS_OD_OUTPUT_CTRL_PWM_2_OD                          0x80
1664 #define PALMAS_OD_OUTPUT_CTRL_PWM_2_OD_SHIFT                    7
1665 #define PALMAS_OD_OUTPUT_CTRL_VBUSDET_OD                        0x40
1666 #define PALMAS_OD_OUTPUT_CTRL_VBUSDET_OD_SHIFT                  6
1667 #define PALMAS_OD_OUTPUT_CTRL_PWM_1_OD                          0x20
1668 #define PALMAS_OD_OUTPUT_CTRL_PWM_1_OD_SHIFT                    5
1669 #define PALMAS_OD_OUTPUT_CTRL_INT_OD                            0x08
1670 #define PALMAS_OD_OUTPUT_CTRL_INT_OD_SHIFT                      3
1671
1672 /* Bit definitions for POLARITY_CTRL */
1673 #define PALMAS_POLARITY_CTRL_INT_POLARITY                       0x80
1674 #define PALMAS_POLARITY_CTRL_INT_POLARITY_SHIFT                 7
1675 #define PALMAS_POLARITY_CTRL_ENABLE2_POLARITY                   0x40
1676 #define PALMAS_POLARITY_CTRL_ENABLE2_POLARITY_SHIFT             6
1677 #define PALMAS_POLARITY_CTRL_ENABLE1_POLARITY                   0x20
1678 #define PALMAS_POLARITY_CTRL_ENABLE1_POLARITY_SHIFT             5
1679 #define PALMAS_POLARITY_CTRL_NSLEEP_POLARITY                    0x10
1680 #define PALMAS_POLARITY_CTRL_NSLEEP_POLARITY_SHIFT              4
1681 #define PALMAS_POLARITY_CTRL_RESET_IN_POLARITY                  0x08
1682 #define PALMAS_POLARITY_CTRL_RESET_IN_POLARITY_SHIFT            3
1683 #define PALMAS_POLARITY_CTRL_GPIO_3_CHRG_DET_N_POLARITY         0x04
1684 #define PALMAS_POLARITY_CTRL_GPIO_3_CHRG_DET_N_POLARITY_SHIFT   2
1685 #define PALMAS_POLARITY_CTRL_POWERGOOD_USB_PSEL_POLARITY        0x02
1686 #define PALMAS_POLARITY_CTRL_POWERGOOD_USB_PSEL_POLARITY_SHIFT  1
1687 #define PALMAS_POLARITY_CTRL_PWRDOWN_POLARITY                   0x01
1688 #define PALMAS_POLARITY_CTRL_PWRDOWN_POLARITY_SHIFT             0
1689
1690 /* Bit definitions for PRIMARY_SECONDARY_PAD1 */
1691 #define PALMAS_PRIMARY_SECONDARY_PAD1_GPIO_3                    0x80
1692 #define PALMAS_PRIMARY_SECONDARY_PAD1_GPIO_3_SHIFT              7
1693 #define PALMAS_PRIMARY_SECONDARY_PAD1_GPIO_2_MASK               0x60
1694 #define PALMAS_PRIMARY_SECONDARY_PAD1_GPIO_2_SHIFT              5
1695 #define PALMAS_PRIMARY_SECONDARY_PAD1_GPIO_1_MASK               0x18
1696 #define PALMAS_PRIMARY_SECONDARY_PAD1_GPIO_1_SHIFT              3
1697 #define PALMAS_PRIMARY_SECONDARY_PAD1_GPIO_0                    0x04
1698 #define PALMAS_PRIMARY_SECONDARY_PAD1_GPIO_0_SHIFT              2
1699 #define PALMAS_PRIMARY_SECONDARY_PAD1_VAC                       0x02
1700 #define PALMAS_PRIMARY_SECONDARY_PAD1_VAC_SHIFT                 1
1701 #define PALMAS_PRIMARY_SECONDARY_PAD1_POWERGOOD                 0x01
1702 #define PALMAS_PRIMARY_SECONDARY_PAD1_POWERGOOD_SHIFT           0
1703
1704 /* Bit definitions for PRIMARY_SECONDARY_PAD2 */
1705 #define PALMAS_PRIMARY_SECONDARY_PAD2_GPIO_7_MASK               0x30
1706 #define PALMAS_PRIMARY_SECONDARY_PAD2_GPIO_7_SHIFT              4
1707 #define PALMAS_PRIMARY_SECONDARY_PAD2_GPIO_6                    0x08
1708 #define PALMAS_PRIMARY_SECONDARY_PAD2_GPIO_6_SHIFT              3
1709 #define PALMAS_PRIMARY_SECONDARY_PAD2_GPIO_5_MASK               0x06
1710 #define PALMAS_PRIMARY_SECONDARY_PAD2_GPIO_5_SHIFT              1
1711 #define PALMAS_PRIMARY_SECONDARY_PAD2_GPIO_4                    0x01
1712 #define PALMAS_PRIMARY_SECONDARY_PAD2_GPIO_4_SHIFT              0
1713
1714 /* Bit definitions for I2C_SPI */
1715 #define PALMAS_I2C_SPI_I2C2OTP_EN                               0x80
1716 #define PALMAS_I2C_SPI_I2C2OTP_EN_SHIFT                         7
1717 #define PALMAS_I2C_SPI_I2C2OTP_PAGESEL                          0x40
1718 #define PALMAS_I2C_SPI_I2C2OTP_PAGESEL_SHIFT                    6
1719 #define PALMAS_I2C_SPI_ID_I2C2                                  0x20
1720 #define PALMAS_I2C_SPI_ID_I2C2_SHIFT                            5
1721 #define PALMAS_I2C_SPI_I2C_SPI                                  0x10
1722 #define PALMAS_I2C_SPI_I2C_SPI_SHIFT                            4
1723 #define PALMAS_I2C_SPI_ID_I2C1_MASK                             0x0f
1724 #define PALMAS_I2C_SPI_ID_I2C1_SHIFT                            0
1725
1726 /* Bit definitions for PU_PD_INPUT_CTRL4 */
1727 #define PALMAS_PU_PD_INPUT_CTRL4_DVFS2_DAT_PD                   0x40
1728 #define PALMAS_PU_PD_INPUT_CTRL4_DVFS2_DAT_PD_SHIFT             6
1729 #define PALMAS_PU_PD_INPUT_CTRL4_DVFS2_CLK_PD                   0x10
1730 #define PALMAS_PU_PD_INPUT_CTRL4_DVFS2_CLK_PD_SHIFT             4
1731 #define PALMAS_PU_PD_INPUT_CTRL4_DVFS1_DAT_PD                   0x04
1732 #define PALMAS_PU_PD_INPUT_CTRL4_DVFS1_DAT_PD_SHIFT             2
1733 #define PALMAS_PU_PD_INPUT_CTRL4_DVFS1_CLK_PD                   0x01
1734 #define PALMAS_PU_PD_INPUT_CTRL4_DVFS1_CLK_PD_SHIFT             0
1735
1736 /* Bit definitions for PRIMARY_SECONDARY_PAD3 */
1737 #define PALMAS_PRIMARY_SECONDARY_PAD3_DVFS2                     0x02
1738 #define PALMAS_PRIMARY_SECONDARY_PAD3_DVFS2_SHIFT               1
1739 #define PALMAS_PRIMARY_SECONDARY_PAD3_DVFS1                     0x01
1740 #define PALMAS_PRIMARY_SECONDARY_PAD3_DVFS1_SHIFT               0
1741
1742 /* Registers for function LED_PWM */
1743 #define PALMAS_LED_PERIOD_CTRL                                  0x0
1744 #define PALMAS_LED_CTRL                                         0x1
1745 #define PALMAS_PWM_CTRL1                                        0x2
1746 #define PALMAS_PWM_CTRL2                                        0x3
1747
1748 /* Bit definitions for LED_PERIOD_CTRL */
1749 #define PALMAS_LED_PERIOD_CTRL_LED_2_PERIOD_MASK                0x38
1750 #define PALMAS_LED_PERIOD_CTRL_LED_2_PERIOD_SHIFT               3
1751 #define PALMAS_LED_PERIOD_CTRL_LED_1_PERIOD_MASK                0x07
1752 #define PALMAS_LED_PERIOD_CTRL_LED_1_PERIOD_SHIFT               0
1753
1754 /* Bit definitions for LED_CTRL */
1755 #define PALMAS_LED_CTRL_LED_2_SEQ                               0x20
1756 #define PALMAS_LED_CTRL_LED_2_SEQ_SHIFT                         5
1757 #define PALMAS_LED_CTRL_LED_1_SEQ                               0x10
1758 #define PALMAS_LED_CTRL_LED_1_SEQ_SHIFT                         4
1759 #define PALMAS_LED_CTRL_LED_2_ON_TIME_MASK                      0x0c
1760 #define PALMAS_LED_CTRL_LED_2_ON_TIME_SHIFT                     2
1761 #define PALMAS_LED_CTRL_LED_1_ON_TIME_MASK                      0x03
1762 #define PALMAS_LED_CTRL_LED_1_ON_TIME_SHIFT                     0
1763
1764 /* Bit definitions for PWM_CTRL1 */
1765 #define PALMAS_PWM_CTRL1_PWM_FREQ_EN                            0x02
1766 #define PALMAS_PWM_CTRL1_PWM_FREQ_EN_SHIFT                      1
1767 #define PALMAS_PWM_CTRL1_PWM_FREQ_SEL                           0x01
1768 #define PALMAS_PWM_CTRL1_PWM_FREQ_SEL_SHIFT                     0
1769
1770 /* Bit definitions for PWM_CTRL2 */
1771 #define PALMAS_PWM_CTRL2_PWM_DUTY_SEL_MASK                      0xff
1772 #define PALMAS_PWM_CTRL2_PWM_DUTY_SEL_SHIFT                     0
1773
1774 /* Registers for function INTERRUPT */
1775 #define PALMAS_INT1_STATUS                                      0x0
1776 #define PALMAS_INT1_MASK                                        0x1
1777 #define PALMAS_INT1_LINE_STATE                                  0x2
1778 #define PALMAS_INT1_EDGE_DETECT1_RESERVED                       0x3
1779 #define PALMAS_INT1_EDGE_DETECT2_RESERVED                       0x4
1780 #define PALMAS_INT2_STATUS                                      0x5
1781 #define PALMAS_INT2_MASK                                        0x6
1782 #define PALMAS_INT2_LINE_STATE                                  0x7
1783 #define PALMAS_INT2_EDGE_DETECT1_RESERVED                       0x8
1784 #define PALMAS_INT2_EDGE_DETECT2_RESERVED                       0x9
1785 #define PALMAS_INT3_STATUS                                      0xA
1786 #define PALMAS_INT3_MASK                                        0xB
1787 #define PALMAS_INT3_LINE_STATE                                  0xC
1788 #define PALMAS_INT3_EDGE_DETECT1_RESERVED                       0xD
1789 #define PALMAS_INT3_EDGE_DETECT2_RESERVED                       0xE
1790 #define PALMAS_INT4_STATUS                                      0xF
1791 #define PALMAS_INT4_MASK                                        0x10
1792 #define PALMAS_INT4_LINE_STATE                                  0x11
1793 #define PALMAS_INT4_EDGE_DETECT1                                0x12
1794 #define PALMAS_INT4_EDGE_DETECT2                                0x13
1795 #define PALMAS_INT_CTRL                                         0x14
1796
1797 /* Bit definitions for INT1_STATUS */
1798 #define PALMAS_INT1_STATUS_VBAT_MON                             0x80
1799 #define PALMAS_INT1_STATUS_VBAT_MON_SHIFT                       7
1800 #define PALMAS_INT1_STATUS_VSYS_MON                             0x40
1801 #define PALMAS_INT1_STATUS_VSYS_MON_SHIFT                       6
1802 #define PALMAS_INT1_STATUS_HOTDIE                               0x20
1803 #define PALMAS_INT1_STATUS_HOTDIE_SHIFT                         5
1804 #define PALMAS_INT1_STATUS_PWRDOWN                              0x10
1805 #define PALMAS_INT1_STATUS_PWRDOWN_SHIFT                        4
1806 #define PALMAS_INT1_STATUS_RPWRON                               0x08
1807 #define PALMAS_INT1_STATUS_RPWRON_SHIFT                         3
1808 #define PALMAS_INT1_STATUS_LONG_PRESS_KEY                       0x04
1809 #define PALMAS_INT1_STATUS_LONG_PRESS_KEY_SHIFT                 2
1810 #define PALMAS_INT1_STATUS_PWRON                                0x02
1811 #define PALMAS_INT1_STATUS_PWRON_SHIFT                          1
1812 #define PALMAS_INT1_STATUS_CHARG_DET_N_VBUS_OVV                 0x01
1813 #define PALMAS_INT1_STATUS_CHARG_DET_N_VBUS_OVV_SHIFT           0
1814
1815 /* Bit definitions for INT1_MASK */
1816 #define PALMAS_INT1_MASK_VBAT_MON                               0x80
1817 #define PALMAS_INT1_MASK_VBAT_MON_SHIFT                         7
1818 #define PALMAS_INT1_MASK_VSYS_MON                               0x40
1819 #define PALMAS_INT1_MASK_VSYS_MON_SHIFT                         6
1820 #define PALMAS_INT1_MASK_HOTDIE                                 0x20
1821 #define PALMAS_INT1_MASK_HOTDIE_SHIFT                           5
1822 #define PALMAS_INT1_MASK_PWRDOWN                                0x10
1823 #define PALMAS_INT1_MASK_PWRDOWN_SHIFT                          4
1824 #define PALMAS_INT1_MASK_RPWRON                                 0x08
1825 #define PALMAS_INT1_MASK_RPWRON_SHIFT                           3
1826 #define PALMAS_INT1_MASK_LONG_PRESS_KEY                         0x04
1827 #define PALMAS_INT1_MASK_LONG_PRESS_KEY_SHIFT                   2
1828 #define PALMAS_INT1_MASK_PWRON                                  0x02
1829 #define PALMAS_INT1_MASK_PWRON_SHIFT                            1
1830 #define PALMAS_INT1_MASK_CHARG_DET_N_VBUS_OVV                   0x01
1831 #define PALMAS_INT1_MASK_CHARG_DET_N_VBUS_OVV_SHIFT             0
1832
1833 /* Bit definitions for INT1_LINE_STATE */
1834 #define PALMAS_INT1_LINE_STATE_VBAT_MON                         0x80
1835 #define PALMAS_INT1_LINE_STATE_VBAT_MON_SHIFT                   7
1836 #define PALMAS_INT1_LINE_STATE_VSYS_MON                         0x40
1837 #define PALMAS_INT1_LINE_STATE_VSYS_MON_SHIFT                   6
1838 #define PALMAS_INT1_LINE_STATE_HOTDIE                           0x20
1839 #define PALMAS_INT1_LINE_STATE_HOTDIE_SHIFT                     5
1840 #define PALMAS_INT1_LINE_STATE_PWRDOWN                          0x10
1841 #define PALMAS_INT1_LINE_STATE_PWRDOWN_SHIFT                    4
1842 #define PALMAS_INT1_LINE_STATE_RPWRON                           0x08
1843 #define PALMAS_INT1_LINE_STATE_RPWRON_SHIFT                     3
1844 #define PALMAS_INT1_LINE_STATE_LONG_PRESS_KEY                   0x04
1845 #define PALMAS_INT1_LINE_STATE_LONG_PRESS_KEY_SHIFT             2
1846 #define PALMAS_INT1_LINE_STATE_PWRON                            0x02
1847 #define PALMAS_INT1_LINE_STATE_PWRON_SHIFT                      1
1848 #define PALMAS_INT1_LINE_STATE_CHARG_DET_N_VBUS_OVV             0x01
1849 #define PALMAS_INT1_LINE_STATE_CHARG_DET_N_VBUS_OVV_SHIFT       0
1850
1851 /* Bit definitions for INT2_STATUS */
1852 #define PALMAS_INT2_STATUS_VAC_ACOK                             0x80
1853 #define PALMAS_INT2_STATUS_VAC_ACOK_SHIFT                       7
1854 #define PALMAS_INT2_STATUS_SHORT                                0x40
1855 #define PALMAS_INT2_STATUS_SHORT_SHIFT                          6
1856 #define PALMAS_INT2_STATUS_FBI_BB                               0x20
1857 #define PALMAS_INT2_STATUS_FBI_BB_SHIFT                         5
1858 #define PALMAS_INT2_STATUS_RESET_IN                             0x10
1859 #define PALMAS_INT2_STATUS_RESET_IN_SHIFT                       4
1860 #define PALMAS_INT2_STATUS_BATREMOVAL                           0x08
1861 #define PALMAS_INT2_STATUS_BATREMOVAL_SHIFT                     3
1862 #define PALMAS_INT2_STATUS_WDT                                  0x04
1863 #define PALMAS_INT2_STATUS_WDT_SHIFT                            2
1864 #define PALMAS_INT2_STATUS_RTC_TIMER                            0x02
1865 #define PALMAS_INT2_STATUS_RTC_TIMER_SHIFT                      1
1866 #define PALMAS_INT2_STATUS_RTC_ALARM                            0x01
1867 #define PALMAS_INT2_STATUS_RTC_ALARM_SHIFT                      0
1868
1869 /* Bit definitions for INT2_MASK */
1870 #define PALMAS_INT2_MASK_VAC_ACOK                               0x80
1871 #define PALMAS_INT2_MASK_VAC_ACOK_SHIFT                         7
1872 #define PALMAS_INT2_MASK_SHORT                                  0x40
1873 #define PALMAS_INT2_MASK_SHORT_SHIFT                            6
1874 #define PALMAS_INT2_MASK_FBI_BB                                 0x20
1875 #define PALMAS_INT2_MASK_FBI_BB_SHIFT                           5
1876 #define PALMAS_INT2_MASK_RESET_IN                               0x10
1877 #define PALMAS_INT2_MASK_RESET_IN_SHIFT                         4
1878 #define PALMAS_INT2_MASK_BATREMOVAL                             0x08
1879 #define PALMAS_INT2_MASK_BATREMOVAL_SHIFT                       3
1880 #define PALMAS_INT2_MASK_WDT                                    0x04
1881 #define PALMAS_INT2_MASK_WDT_SHIFT                              2
1882 #define PALMAS_INT2_MASK_RTC_TIMER                              0x02
1883 #define PALMAS_INT2_MASK_RTC_TIMER_SHIFT                        1
1884 #define PALMAS_INT2_MASK_RTC_ALARM                              0x01
1885 #define PALMAS_INT2_MASK_RTC_ALARM_SHIFT                        0
1886
1887 /* Bit definitions for INT2_LINE_STATE */
1888 #define PALMAS_INT2_LINE_STATE_VAC_ACOK                         0x80
1889 #define PALMAS_INT2_LINE_STATE_VAC_ACOK_SHIFT                   7
1890 #define PALMAS_INT2_LINE_STATE_SHORT                            0x40
1891 #define PALMAS_INT2_LINE_STATE_SHORT_SHIFT                      6
1892 #define PALMAS_INT2_LINE_STATE_FBI_BB                           0x20
1893 #define PALMAS_INT2_LINE_STATE_FBI_BB_SHIFT                     5
1894 #define PALMAS_INT2_LINE_STATE_RESET_IN                         0x10
1895 #define PALMAS_INT2_LINE_STATE_RESET_IN_SHIFT                   4
1896 #define PALMAS_INT2_LINE_STATE_BATREMOVAL                       0x08
1897 #define PALMAS_INT2_LINE_STATE_BATREMOVAL_SHIFT                 3
1898 #define PALMAS_INT2_LINE_STATE_WDT                              0x04
1899 #define PALMAS_INT2_LINE_STATE_WDT_SHIFT                        2
1900 #define PALMAS_INT2_LINE_STATE_RTC_TIMER                        0x02
1901 #define PALMAS_INT2_LINE_STATE_RTC_TIMER_SHIFT                  1
1902 #define PALMAS_INT2_LINE_STATE_RTC_ALARM                        0x01
1903 #define PALMAS_INT2_LINE_STATE_RTC_ALARM_SHIFT                  0
1904
1905 /* Bit definitions for INT3_STATUS */
1906 #define PALMAS_INT3_STATUS_VBUS                                 0x80
1907 #define PALMAS_INT3_STATUS_VBUS_SHIFT                           7
1908 #define PALMAS_INT3_STATUS_VBUS_OTG                             0x40
1909 #define PALMAS_INT3_STATUS_VBUS_OTG_SHIFT                       6
1910 #define PALMAS_INT3_STATUS_ID                                   0x20
1911 #define PALMAS_INT3_STATUS_ID_SHIFT                             5
1912 #define PALMAS_INT3_STATUS_ID_OTG                               0x10
1913 #define PALMAS_INT3_STATUS_ID_OTG_SHIFT                         4
1914 #define PALMAS_INT3_STATUS_GPADC_EOC_RT                         0x08
1915 #define PALMAS_INT3_STATUS_GPADC_EOC_RT_SHIFT                   3
1916 #define PALMAS_INT3_STATUS_GPADC_EOC_SW                         0x04
1917 #define PALMAS_INT3_STATUS_GPADC_EOC_SW_SHIFT                   2
1918 #define PALMAS_INT3_STATUS_GPADC_AUTO_1                         0x02
1919 #define PALMAS_INT3_STATUS_GPADC_AUTO_1_SHIFT                   1
1920 #define PALMAS_INT3_STATUS_GPADC_AUTO_0                         0x01
1921 #define PALMAS_INT3_STATUS_GPADC_AUTO_0_SHIFT                   0
1922
1923 /* Bit definitions for INT3_MASK */
1924 #define PALMAS_INT3_MASK_VBUS                                   0x80
1925 #define PALMAS_INT3_MASK_VBUS_SHIFT                             7
1926 #define PALMAS_INT3_MASK_VBUS_OTG                               0x40
1927 #define PALMAS_INT3_MASK_VBUS_OTG_SHIFT                         6
1928 #define PALMAS_INT3_MASK_ID                                     0x20
1929 #define PALMAS_INT3_MASK_ID_SHIFT                               5
1930 #define PALMAS_INT3_MASK_ID_OTG                                 0x10
1931 #define PALMAS_INT3_MASK_ID_OTG_SHIFT                           4
1932 #define PALMAS_INT3_MASK_GPADC_EOC_RT                           0x08
1933 #define PALMAS_INT3_MASK_GPADC_EOC_RT_SHIFT                     3
1934 #define PALMAS_INT3_MASK_GPADC_EOC_SW                           0x04
1935 #define PALMAS_INT3_MASK_GPADC_EOC_SW_SHIFT                     2
1936 #define PALMAS_INT3_MASK_GPADC_AUTO_1                           0x02
1937 #define PALMAS_INT3_MASK_GPADC_AUTO_1_SHIFT                     1
1938 #define PALMAS_INT3_MASK_GPADC_AUTO_0                           0x01
1939 #define PALMAS_INT3_MASK_GPADC_AUTO_0_SHIFT                     0
1940
1941 /* Bit definitions for INT3_LINE_STATE */
1942 #define PALMAS_INT3_LINE_STATE_VBUS                             0x80
1943 #define PALMAS_INT3_LINE_STATE_VBUS_SHIFT                       7
1944 #define PALMAS_INT3_LINE_STATE_VBUS_OTG                         0x40
1945 #define PALMAS_INT3_LINE_STATE_VBUS_OTG_SHIFT                   6
1946 #define PALMAS_INT3_LINE_STATE_ID                               0x20
1947 #define PALMAS_INT3_LINE_STATE_ID_SHIFT                         5
1948 #define PALMAS_INT3_LINE_STATE_ID_OTG                           0x10
1949 #define PALMAS_INT3_LINE_STATE_ID_OTG_SHIFT                     4
1950 #define PALMAS_INT3_LINE_STATE_GPADC_EOC_RT                     0x08
1951 #define PALMAS_INT3_LINE_STATE_GPADC_EOC_RT_SHIFT               3
1952 #define PALMAS_INT3_LINE_STATE_GPADC_EOC_SW                     0x04
1953 #define PALMAS_INT3_LINE_STATE_GPADC_EOC_SW_SHIFT               2
1954 #define PALMAS_INT3_LINE_STATE_GPADC_AUTO_1                     0x02
1955 #define PALMAS_INT3_LINE_STATE_GPADC_AUTO_1_SHIFT               1
1956 #define PALMAS_INT3_LINE_STATE_GPADC_AUTO_0                     0x01
1957 #define PALMAS_INT3_LINE_STATE_GPADC_AUTO_0_SHIFT               0
1958
1959 /* Bit definitions for INT4_STATUS */
1960 #define PALMAS_INT4_STATUS_GPIO_7                               0x80
1961 #define PALMAS_INT4_STATUS_GPIO_7_SHIFT                         7
1962 #define PALMAS_INT4_STATUS_GPIO_6                               0x40
1963 #define PALMAS_INT4_STATUS_GPIO_6_SHIFT                         6
1964 #define PALMAS_INT4_STATUS_GPIO_5                               0x20
1965 #define PALMAS_INT4_STATUS_GPIO_5_SHIFT                         5
1966 #define PALMAS_INT4_STATUS_GPIO_4                               0x10
1967 #define PALMAS_INT4_STATUS_GPIO_4_SHIFT                         4
1968 #define PALMAS_INT4_STATUS_GPIO_3                               0x08
1969 #define PALMAS_INT4_STATUS_GPIO_3_SHIFT                         3
1970 #define PALMAS_INT4_STATUS_GPIO_2                               0x04
1971 #define PALMAS_INT4_STATUS_GPIO_2_SHIFT                         2
1972 #define PALMAS_INT4_STATUS_GPIO_1                               0x02
1973 #define PALMAS_INT4_STATUS_GPIO_1_SHIFT                         1
1974 #define PALMAS_INT4_STATUS_GPIO_0                               0x01
1975 #define PALMAS_INT4_STATUS_GPIO_0_SHIFT                         0
1976
1977 /* Bit definitions for INT4_MASK */
1978 #define PALMAS_INT4_MASK_GPIO_7                                 0x80
1979 #define PALMAS_INT4_MASK_GPIO_7_SHIFT                           7
1980 #define PALMAS_INT4_MASK_GPIO_6                                 0x40
1981 #define PALMAS_INT4_MASK_GPIO_6_SHIFT                           6
1982 #define PALMAS_INT4_MASK_GPIO_5                                 0x20
1983 #define PALMAS_INT4_MASK_GPIO_5_SHIFT                           5
1984 #define PALMAS_INT4_MASK_GPIO_4                                 0x10
1985 #define PALMAS_INT4_MASK_GPIO_4_SHIFT                           4
1986 #define PALMAS_INT4_MASK_GPIO_3                                 0x08
1987 #define PALMAS_INT4_MASK_GPIO_3_SHIFT                           3
1988 #define PALMAS_INT4_MASK_GPIO_2                                 0x04
1989 #define PALMAS_INT4_MASK_GPIO_2_SHIFT                           2
1990 #define PALMAS_INT4_MASK_GPIO_1                                 0x02
1991 #define PALMAS_INT4_MASK_GPIO_1_SHIFT                           1
1992 #define PALMAS_INT4_MASK_GPIO_0                                 0x01
1993 #define PALMAS_INT4_MASK_GPIO_0_SHIFT                           0
1994
1995 /* Bit definitions for INT4_LINE_STATE */
1996 #define PALMAS_INT4_LINE_STATE_GPIO_7                           0x80
1997 #define PALMAS_INT4_LINE_STATE_GPIO_7_SHIFT                     7
1998 #define PALMAS_INT4_LINE_STATE_GPIO_6                           0x40
1999 #define PALMAS_INT4_LINE_STATE_GPIO_6_SHIFT                     6
2000 #define PALMAS_INT4_LINE_STATE_GPIO_5                           0x20
2001 #define PALMAS_INT4_LINE_STATE_GPIO_5_SHIFT                     5
2002 #define PALMAS_INT4_LINE_STATE_GPIO_4                           0x10
2003 #define PALMAS_INT4_LINE_STATE_GPIO_4_SHIFT                     4
2004 #define PALMAS_INT4_LINE_STATE_GPIO_3                           0x08
2005 #define PALMAS_INT4_LINE_STATE_GPIO_3_SHIFT                     3
2006 #define PALMAS_INT4_LINE_STATE_GPIO_2                           0x04
2007 #define PALMAS_INT4_LINE_STATE_GPIO_2_SHIFT                     2
2008 #define PALMAS_INT4_LINE_STATE_GPIO_1                           0x02
2009 #define PALMAS_INT4_LINE_STATE_GPIO_1_SHIFT                     1
2010 #define PALMAS_INT4_LINE_STATE_GPIO_0                           0x01
2011 #define PALMAS_INT4_LINE_STATE_GPIO_0_SHIFT                     0
2012
2013 /* Bit definitions for INT4_EDGE_DETECT1 */
2014 #define PALMAS_INT4_EDGE_DETECT1_GPIO_3_RISING                  0x80
2015 #define PALMAS_INT4_EDGE_DETECT1_GPIO_3_RISING_SHIFT            7
2016 #define PALMAS_INT4_EDGE_DETECT1_GPIO_3_FALLING                 0x40
2017 #define PALMAS_INT4_EDGE_DETECT1_GPIO_3_FALLING_SHIFT           6
2018 #define PALMAS_INT4_EDGE_DETECT1_GPIO_2_RISING                  0x20
2019 #define PALMAS_INT4_EDGE_DETECT1_GPIO_2_RISING_SHIFT            5
2020 #define PALMAS_INT4_EDGE_DETECT1_GPIO_2_FALLING                 0x10
2021 #define PALMAS_INT4_EDGE_DETECT1_GPIO_2_FALLING_SHIFT           4
2022 #define PALMAS_INT4_EDGE_DETECT1_GPIO_1_RISING                  0x08
2023 #define PALMAS_INT4_EDGE_DETECT1_GPIO_1_RISING_SHIFT            3
2024 #define PALMAS_INT4_EDGE_DETECT1_GPIO_1_FALLING                 0x04
2025 #define PALMAS_INT4_EDGE_DETECT1_GPIO_1_FALLING_SHIFT           2
2026 #define PALMAS_INT4_EDGE_DETECT1_GPIO_0_RISING                  0x02
2027 #define PALMAS_INT4_EDGE_DETECT1_GPIO_0_RISING_SHIFT            1
2028 #define PALMAS_INT4_EDGE_DETECT1_GPIO_0_FALLING                 0x01
2029 #define PALMAS_INT4_EDGE_DETECT1_GPIO_0_FALLING_SHIFT           0
2030
2031 /* Bit definitions for INT4_EDGE_DETECT2 */
2032 #define PALMAS_INT4_EDGE_DETECT2_GPIO_7_RISING                  0x80
2033 #define PALMAS_INT4_EDGE_DETECT2_GPIO_7_RISING_SHIFT            7
2034 #define PALMAS_INT4_EDGE_DETECT2_GPIO_7_FALLING                 0x40
2035 #define PALMAS_INT4_EDGE_DETECT2_GPIO_7_FALLING_SHIFT           6
2036 #define PALMAS_INT4_EDGE_DETECT2_GPIO_6_RISING                  0x20
2037 #define PALMAS_INT4_EDGE_DETECT2_GPIO_6_RISING_SHIFT            5
2038 #define PALMAS_INT4_EDGE_DETECT2_GPIO_6_FALLING                 0x10
2039 #define PALMAS_INT4_EDGE_DETECT2_GPIO_6_FALLING_SHIFT           4
2040 #define PALMAS_INT4_EDGE_DETECT2_GPIO_5_RISING                  0x08
2041 #define PALMAS_INT4_EDGE_DETECT2_GPIO_5_RISING_SHIFT            3
2042 #define PALMAS_INT4_EDGE_DETECT2_GPIO_5_FALLING                 0x04
2043 #define PALMAS_INT4_EDGE_DETECT2_GPIO_5_FALLING_SHIFT           2
2044 #define PALMAS_INT4_EDGE_DETECT2_GPIO_4_RISING                  0x02
2045 #define PALMAS_INT4_EDGE_DETECT2_GPIO_4_RISING_SHIFT            1
2046 #define PALMAS_INT4_EDGE_DETECT2_GPIO_4_FALLING                 0x01
2047 #define PALMAS_INT4_EDGE_DETECT2_GPIO_4_FALLING_SHIFT           0
2048
2049 /* Bit definitions for INT_CTRL */
2050 #define PALMAS_INT_CTRL_INT_PENDING                             0x04
2051 #define PALMAS_INT_CTRL_INT_PENDING_SHIFT                       2
2052 #define PALMAS_INT_CTRL_INT_CLEAR                               0x01
2053 #define PALMAS_INT_CTRL_INT_CLEAR_SHIFT                         0
2054
2055 /* Registers for function USB_OTG */
2056 #define PALMAS_USB_WAKEUP                                       0x3
2057 #define PALMAS_USB_VBUS_CTRL_SET                                0x4
2058 #define PALMAS_USB_VBUS_CTRL_CLR                                0x5
2059 #define PALMAS_USB_ID_CTRL_SET                                  0x6
2060 #define PALMAS_USB_ID_CTRL_CLEAR                                0x7
2061 #define PALMAS_USB_VBUS_INT_SRC                                 0x8
2062 #define PALMAS_USB_VBUS_INT_LATCH_SET                           0x9
2063 #define PALMAS_USB_VBUS_INT_LATCH_CLR                           0xA
2064 #define PALMAS_USB_VBUS_INT_EN_LO_SET                           0xB
2065 #define PALMAS_USB_VBUS_INT_EN_LO_CLR                           0xC
2066 #define PALMAS_USB_VBUS_INT_EN_HI_SET                           0xD
2067 #define PALMAS_USB_VBUS_INT_EN_HI_CLR                           0xE
2068 #define PALMAS_USB_ID_INT_SRC                                   0xF
2069 #define PALMAS_USB_ID_INT_LATCH_SET                             0x10
2070 #define PALMAS_USB_ID_INT_LATCH_CLR                             0x11
2071 #define PALMAS_USB_ID_INT_EN_LO_SET                             0x12
2072 #define PALMAS_USB_ID_INT_EN_LO_CLR                             0x13
2073 #define PALMAS_USB_ID_INT_EN_HI_SET                             0x14
2074 #define PALMAS_USB_ID_INT_EN_HI_CLR                             0x15
2075 #define PALMAS_USB_OTG_ADP_CTRL                                 0x16
2076 #define PALMAS_USB_OTG_ADP_HIGH                                 0x17
2077 #define PALMAS_USB_OTG_ADP_LOW                                  0x18
2078 #define PALMAS_USB_OTG_ADP_RISE                                 0x19
2079 #define PALMAS_USB_OTG_REVISION                                 0x1A
2080
2081 /* Bit definitions for USB_WAKEUP */
2082 #define PALMAS_USB_WAKEUP_ID_WK_UP_COMP                         0x01
2083 #define PALMAS_USB_WAKEUP_ID_WK_UP_COMP_SHIFT                   0
2084
2085 /* Bit definitions for USB_VBUS_CTRL_SET */
2086 #define PALMAS_USB_VBUS_CTRL_SET_VBUS_CHRG_VSYS                 0x80
2087 #define PALMAS_USB_VBUS_CTRL_SET_VBUS_CHRG_VSYS_SHIFT           7
2088 #define PALMAS_USB_VBUS_CTRL_SET_VBUS_DISCHRG                   0x20
2089 #define PALMAS_USB_VBUS_CTRL_SET_VBUS_DISCHRG_SHIFT             5
2090 #define PALMAS_USB_VBUS_CTRL_SET_VBUS_IADP_SRC                  0x10
2091 #define PALMAS_USB_VBUS_CTRL_SET_VBUS_IADP_SRC_SHIFT            4
2092 #define PALMAS_USB_VBUS_CTRL_SET_VBUS_IADP_SINK                 0x08
2093 #define PALMAS_USB_VBUS_CTRL_SET_VBUS_IADP_SINK_SHIFT           3
2094 #define PALMAS_USB_VBUS_CTRL_SET_VBUS_ACT_COMP                  0x04
2095 #define PALMAS_USB_VBUS_CTRL_SET_VBUS_ACT_COMP_SHIFT            2
2096
2097 /* Bit definitions for USB_VBUS_CTRL_CLR */
2098 #define PALMAS_USB_VBUS_CTRL_CLR_VBUS_CHRG_VSYS                 0x80
2099 #define PALMAS_USB_VBUS_CTRL_CLR_VBUS_CHRG_VSYS_SHIFT           7
2100 #define PALMAS_USB_VBUS_CTRL_CLR_VBUS_DISCHRG                   0x20
2101 #define PALMAS_USB_VBUS_CTRL_CLR_VBUS_DISCHRG_SHIFT             5
2102 #define PALMAS_USB_VBUS_CTRL_CLR_VBUS_IADP_SRC                  0x10
2103 #define PALMAS_USB_VBUS_CTRL_CLR_VBUS_IADP_SRC_SHIFT            4
2104 #define PALMAS_USB_VBUS_CTRL_CLR_VBUS_IADP_SINK                 0x08
2105 #define PALMAS_USB_VBUS_CTRL_CLR_VBUS_IADP_SINK_SHIFT           3
2106 #define PALMAS_USB_VBUS_CTRL_CLR_VBUS_ACT_COMP                  0x04
2107 #define PALMAS_USB_VBUS_CTRL_CLR_VBUS_ACT_COMP_SHIFT            2
2108
2109 /* Bit definitions for USB_ID_CTRL_SET */
2110 #define PALMAS_USB_ID_CTRL_SET_ID_PU_220K                       0x80
2111 #define PALMAS_USB_ID_CTRL_SET_ID_PU_220K_SHIFT                 7
2112 #define PALMAS_USB_ID_CTRL_SET_ID_PU_100K                       0x40
2113 #define PALMAS_USB_ID_CTRL_SET_ID_PU_100K_SHIFT                 6
2114 #define PALMAS_USB_ID_CTRL_SET_ID_GND_DRV                       0x20
2115 #define PALMAS_USB_ID_CTRL_SET_ID_GND_DRV_SHIFT                 5
2116 #define PALMAS_USB_ID_CTRL_SET_ID_SRC_16U                       0x10
2117 #define PALMAS_USB_ID_CTRL_SET_ID_SRC_16U_SHIFT                 4
2118 #define PALMAS_USB_ID_CTRL_SET_ID_SRC_5U                        0x08
2119 #define PALMAS_USB_ID_CTRL_SET_ID_SRC_5U_SHIFT                  3
2120 #define PALMAS_USB_ID_CTRL_SET_ID_ACT_COMP                      0x04
2121 #define PALMAS_USB_ID_CTRL_SET_ID_ACT_COMP_SHIFT                2
2122
2123 /* Bit definitions for USB_ID_CTRL_CLEAR */
2124 #define PALMAS_USB_ID_CTRL_CLEAR_ID_PU_220K                     0x80
2125 #define PALMAS_USB_ID_CTRL_CLEAR_ID_PU_220K_SHIFT               7
2126 #define PALMAS_USB_ID_CTRL_CLEAR_ID_PU_100K                     0x40
2127 #define PALMAS_USB_ID_CTRL_CLEAR_ID_PU_100K_SHIFT               6
2128 #define PALMAS_USB_ID_CTRL_CLEAR_ID_GND_DRV                     0x20
2129 #define PALMAS_USB_ID_CTRL_CLEAR_ID_GND_DRV_SHIFT               5
2130 #define PALMAS_USB_ID_CTRL_CLEAR_ID_SRC_16U                     0x10
2131 #define PALMAS_USB_ID_CTRL_CLEAR_ID_SRC_16U_SHIFT               4
2132 #define PALMAS_USB_ID_CTRL_CLEAR_ID_SRC_5U                      0x08
2133 #define PALMAS_USB_ID_CTRL_CLEAR_ID_SRC_5U_SHIFT                3
2134 #define PALMAS_USB_ID_CTRL_CLEAR_ID_ACT_COMP                    0x04
2135 #define PALMAS_USB_ID_CTRL_CLEAR_ID_ACT_COMP_SHIFT              2
2136
2137 /* Bit definitions for USB_VBUS_INT_SRC */
2138 #define PALMAS_USB_VBUS_INT_SRC_VOTG_SESS_VLD                   0x80
2139 #define PALMAS_USB_VBUS_INT_SRC_VOTG_SESS_VLD_SHIFT             7
2140 #define PALMAS_USB_VBUS_INT_SRC_VADP_PRB                        0x40
2141 #define PALMAS_USB_VBUS_INT_SRC_VADP_PRB_SHIFT                  6
2142 #define PALMAS_USB_VBUS_INT_SRC_VADP_SNS                        0x20
2143 #define PALMAS_USB_VBUS_INT_SRC_VADP_SNS_SHIFT                  5
2144 #define PALMAS_USB_VBUS_INT_SRC_VA_VBUS_VLD                     0x08
2145 #define PALMAS_USB_VBUS_INT_SRC_VA_VBUS_VLD_SHIFT               3
2146 #define PALMAS_USB_VBUS_INT_SRC_VA_SESS_VLD                     0x04
2147 #define PALMAS_USB_VBUS_INT_SRC_VA_SESS_VLD_SHIFT               2
2148 #define PALMAS_USB_VBUS_INT_SRC_VB_SESS_VLD                     0x02
2149 #define PALMAS_USB_VBUS_INT_SRC_VB_SESS_VLD_SHIFT               1
2150 #define PALMAS_USB_VBUS_INT_SRC_VB_SESS_END                     0x01
2151 #define PALMAS_USB_VBUS_INT_SRC_VB_SESS_END_SHIFT               0
2152
2153 /* Bit definitions for USB_VBUS_INT_LATCH_SET */
2154 #define PALMAS_USB_VBUS_INT_LATCH_SET_VOTG_SESS_VLD             0x80
2155 #define PALMAS_USB_VBUS_INT_LATCH_SET_VOTG_SESS_VLD_SHIFT       7
2156 #define PALMAS_USB_VBUS_INT_LATCH_SET_VADP_PRB                  0x40
2157 #define PALMAS_USB_VBUS_INT_LATCH_SET_VADP_PRB_SHIFT            6
2158 #define PALMAS_USB_VBUS_INT_LATCH_SET_VADP_SNS                  0x20
2159 #define PALMAS_USB_VBUS_INT_LATCH_SET_VADP_SNS_SHIFT            5
2160 #define PALMAS_USB_VBUS_INT_LATCH_SET_ADP                       0x10
2161 #define PALMAS_USB_VBUS_INT_LATCH_SET_ADP_SHIFT                 4
2162 #define PALMAS_USB_VBUS_INT_LATCH_SET_VA_VBUS_VLD               0x08
2163 #define PALMAS_USB_VBUS_INT_LATCH_SET_VA_VBUS_VLD_SHIFT         3
2164 #define PALMAS_USB_VBUS_INT_LATCH_SET_VA_SESS_VLD               0x04
2165 #define PALMAS_USB_VBUS_INT_LATCH_SET_VA_SESS_VLD_SHIFT         2
2166 #define PALMAS_USB_VBUS_INT_LATCH_SET_VB_SESS_VLD               0x02
2167 #define PALMAS_USB_VBUS_INT_LATCH_SET_VB_SESS_VLD_SHIFT         1
2168 #define PALMAS_USB_VBUS_INT_LATCH_SET_VB_SESS_END               0x01
2169 #define PALMAS_USB_VBUS_INT_LATCH_SET_VB_SESS_END_SHIFT         0
2170
2171 /* Bit definitions for USB_VBUS_INT_LATCH_CLR */
2172 #define PALMAS_USB_VBUS_INT_LATCH_CLR_VOTG_SESS_VLD             0x80
2173 #define PALMAS_USB_VBUS_INT_LATCH_CLR_VOTG_SESS_VLD_SHIFT       7
2174 #define PALMAS_USB_VBUS_INT_LATCH_CLR_VADP_PRB                  0x40
2175 #define PALMAS_USB_VBUS_INT_LATCH_CLR_VADP_PRB_SHIFT            6
2176 #define PALMAS_USB_VBUS_INT_LATCH_CLR_VADP_SNS                  0x20
2177 #define PALMAS_USB_VBUS_INT_LATCH_CLR_VADP_SNS_SHIFT            5
2178 #define PALMAS_USB_VBUS_INT_LATCH_CLR_ADP                       0x10
2179 #define PALMAS_USB_VBUS_INT_LATCH_CLR_ADP_SHIFT                 4
2180 #define PALMAS_USB_VBUS_INT_LATCH_CLR_VA_VBUS_VLD               0x08
2181 #define PALMAS_USB_VBUS_INT_LATCH_CLR_VA_VBUS_VLD_SHIFT         3
2182 #define PALMAS_USB_VBUS_INT_LATCH_CLR_VA_SESS_VLD               0x04
2183 #define PALMAS_USB_VBUS_INT_LATCH_CLR_VA_SESS_VLD_SHIFT         2
2184 #define PALMAS_USB_VBUS_INT_LATCH_CLR_VB_SESS_VLD               0x02
2185 #define PALMAS_USB_VBUS_INT_LATCH_CLR_VB_SESS_VLD_SHIFT         1
2186 #define PALMAS_USB_VBUS_INT_LATCH_CLR_VB_SESS_END               0x01
2187 #define PALMAS_USB_VBUS_INT_LATCH_CLR_VB_SESS_END_SHIFT         0
2188
2189 /* Bit definitions for USB_VBUS_INT_EN_LO_SET */
2190 #define PALMAS_USB_VBUS_INT_EN_LO_SET_VOTG_SESS_VLD             0x80
2191 #define PALMAS_USB_VBUS_INT_EN_LO_SET_VOTG_SESS_VLD_SHIFT       7
2192 #define PALMAS_USB_VBUS_INT_EN_LO_SET_VADP_PRB                  0x40
2193 #define PALMAS_USB_VBUS_INT_EN_LO_SET_VADP_PRB_SHIFT            6
2194 #define PALMAS_USB_VBUS_INT_EN_LO_SET_VADP_SNS                  0x20
2195 #define PALMAS_USB_VBUS_INT_EN_LO_SET_VADP_SNS_SHIFT            5
2196 #define PALMAS_USB_VBUS_INT_EN_LO_SET_VA_VBUS_VLD               0x08
2197 #define PALMAS_USB_VBUS_INT_EN_LO_SET_VA_VBUS_VLD_SHIFT         3
2198 #define PALMAS_USB_VBUS_INT_EN_LO_SET_VA_SESS_VLD               0x04
2199 #define PALMAS_USB_VBUS_INT_EN_LO_SET_VA_SESS_VLD_SHIFT         2
2200 #define PALMAS_USB_VBUS_INT_EN_LO_SET_VB_SESS_VLD               0x02
2201 #define PALMAS_USB_VBUS_INT_EN_LO_SET_VB_SESS_VLD_SHIFT         1
2202 #define PALMAS_USB_VBUS_INT_EN_LO_SET_VB_SESS_END               0x01
2203 #define PALMAS_USB_VBUS_INT_EN_LO_SET_VB_SESS_END_SHIFT         0
2204
2205 /* Bit definitions for USB_VBUS_INT_EN_LO_CLR */
2206 #define PALMAS_USB_VBUS_INT_EN_LO_CLR_VOTG_SESS_VLD             0x80
2207 #define PALMAS_USB_VBUS_INT_EN_LO_CLR_VOTG_SESS_VLD_SHIFT       7
2208 #define PALMAS_USB_VBUS_INT_EN_LO_CLR_VADP_PRB                  0x40
2209 #define PALMAS_USB_VBUS_INT_EN_LO_CLR_VADP_PRB_SHIFT            6
2210 #define PALMAS_USB_VBUS_INT_EN_LO_CLR_VADP_SNS                  0x20
2211 #define PALMAS_USB_VBUS_INT_EN_LO_CLR_VADP_SNS_SHIFT            5
2212 #define PALMAS_USB_VBUS_INT_EN_LO_CLR_VA_VBUS_VLD               0x08
2213 #define PALMAS_USB_VBUS_INT_EN_LO_CLR_VA_VBUS_VLD_SHIFT         3
2214 #define PALMAS_USB_VBUS_INT_EN_LO_CLR_VA_SESS_VLD               0x04
2215 #define PALMAS_USB_VBUS_INT_EN_LO_CLR_VA_SESS_VLD_SHIFT         2
2216 #define PALMAS_USB_VBUS_INT_EN_LO_CLR_VB_SESS_VLD               0x02
2217 #define PALMAS_USB_VBUS_INT_EN_LO_CLR_VB_SESS_VLD_SHIFT         1
2218 #define PALMAS_USB_VBUS_INT_EN_LO_CLR_VB_SESS_END               0x01
2219 #define PALMAS_USB_VBUS_INT_EN_LO_CLR_VB_SESS_END_SHIFT         0
2220
2221 /* Bit definitions for USB_VBUS_INT_EN_HI_SET */
2222 #define PALMAS_USB_VBUS_INT_EN_HI_SET_VOTG_SESS_VLD             0x80
2223 #define PALMAS_USB_VBUS_INT_EN_HI_SET_VOTG_SESS_VLD_SHIFT       7
2224 #define PALMAS_USB_VBUS_INT_EN_HI_SET_VADP_PRB                  0x40
2225 #define PALMAS_USB_VBUS_INT_EN_HI_SET_VADP_PRB_SHIFT            6
2226 #define PALMAS_USB_VBUS_INT_EN_HI_SET_VADP_SNS                  0x20
2227 #define PALMAS_USB_VBUS_INT_EN_HI_SET_VADP_SNS_SHIFT            5
2228 #define PALMAS_USB_VBUS_INT_EN_HI_SET_ADP                       0x10
2229 #define PALMAS_USB_VBUS_INT_EN_HI_SET_ADP_SHIFT                 4
2230 #define PALMAS_USB_VBUS_INT_EN_HI_SET_VA_VBUS_VLD               0x08
2231 #define PALMAS_USB_VBUS_INT_EN_HI_SET_VA_VBUS_VLD_SHIFT         3
2232 #define PALMAS_USB_VBUS_INT_EN_HI_SET_VA_SESS_VLD               0x04
2233 #define PALMAS_USB_VBUS_INT_EN_HI_SET_VA_SESS_VLD_SHIFT         2
2234 #define PALMAS_USB_VBUS_INT_EN_HI_SET_VB_SESS_VLD               0x02
2235 #define PALMAS_USB_VBUS_INT_EN_HI_SET_VB_SESS_VLD_SHIFT         1
2236 #define PALMAS_USB_VBUS_INT_EN_HI_SET_VB_SESS_END               0x01
2237 #define PALMAS_USB_VBUS_INT_EN_HI_SET_VB_SESS_END_SHIFT         0
2238
2239 /* Bit definitions for USB_VBUS_INT_EN_HI_CLR */
2240 #define PALMAS_USB_VBUS_INT_EN_HI_CLR_VOTG_SESS_VLD             0x80
2241 #define PALMAS_USB_VBUS_INT_EN_HI_CLR_VOTG_SESS_VLD_SHIFT       7
2242 #define PALMAS_USB_VBUS_INT_EN_HI_CLR_VADP_PRB                  0x40
2243 #define PALMAS_USB_VBUS_INT_EN_HI_CLR_VADP_PRB_SHIFT            6
2244 #define PALMAS_USB_VBUS_INT_EN_HI_CLR_VADP_SNS                  0x20
2245 #define PALMAS_USB_VBUS_INT_EN_HI_CLR_VADP_SNS_SHIFT            5
2246 #define PALMAS_USB_VBUS_INT_EN_HI_CLR_ADP                       0x10
2247 #define PALMAS_USB_VBUS_INT_EN_HI_CLR_ADP_SHIFT                 4
2248 #define PALMAS_USB_VBUS_INT_EN_HI_CLR_VA_VBUS_VLD               0x08
2249 #define PALMAS_USB_VBUS_INT_EN_HI_CLR_VA_VBUS_VLD_SHIFT         3
2250 #define PALMAS_USB_VBUS_INT_EN_HI_CLR_VA_SESS_VLD               0x04
2251 #define PALMAS_USB_VBUS_INT_EN_HI_CLR_VA_SESS_VLD_SHIFT         2
2252 #define PALMAS_USB_VBUS_INT_EN_HI_CLR_VB_SESS_VLD               0x02
2253 #define PALMAS_USB_VBUS_INT_EN_HI_CLR_VB_SESS_VLD_SHIFT         1
2254 #define PALMAS_USB_VBUS_INT_EN_HI_CLR_VB_SESS_END               0x01
2255 #define PALMAS_USB_VBUS_INT_EN_HI_CLR_VB_SESS_END_SHIFT         0
2256
2257 /* Bit definitions for USB_ID_INT_SRC */
2258 #define PALMAS_USB_ID_INT_SRC_ID_FLOAT                          0x10
2259 #define PALMAS_USB_ID_INT_SRC_ID_FLOAT_SHIFT                    4
2260 #define PALMAS_USB_ID_INT_SRC_ID_A                              0x08
2261 #define PALMAS_USB_ID_INT_SRC_ID_A_SHIFT                        3
2262 #define PALMAS_USB_ID_INT_SRC_ID_B                              0x04
2263 #define PALMAS_USB_ID_INT_SRC_ID_B_SHIFT                        2
2264 #define PALMAS_USB_ID_INT_SRC_ID_C                              0x02
2265 #define PALMAS_USB_ID_INT_SRC_ID_C_SHIFT                        1
2266 #define PALMAS_USB_ID_INT_SRC_ID_GND                            0x01
2267 #define PALMAS_USB_ID_INT_SRC_ID_GND_SHIFT                      0
2268
2269 /* Bit definitions for USB_ID_INT_LATCH_SET */
2270 #define PALMAS_USB_ID_INT_LATCH_SET_ID_FLOAT                    0x10
2271 #define PALMAS_USB_ID_INT_LATCH_SET_ID_FLOAT_SHIFT              4
2272 #define PALMAS_USB_ID_INT_LATCH_SET_ID_A                        0x08
2273 #define PALMAS_USB_ID_INT_LATCH_SET_ID_A_SHIFT                  3
2274 #define PALMAS_USB_ID_INT_LATCH_SET_ID_B                        0x04
2275 #define PALMAS_USB_ID_INT_LATCH_SET_ID_B_SHIFT                  2
2276 #define PALMAS_USB_ID_INT_LATCH_SET_ID_C                        0x02
2277 #define PALMAS_USB_ID_INT_LATCH_SET_ID_C_SHIFT                  1
2278 #define PALMAS_USB_ID_INT_LATCH_SET_ID_GND                      0x01
2279 #define PALMAS_USB_ID_INT_LATCH_SET_ID_GND_SHIFT                0
2280
2281 /* Bit definitions for USB_ID_INT_LATCH_CLR */
2282 #define PALMAS_USB_ID_INT_LATCH_CLR_ID_FLOAT                    0x10
2283 #define PALMAS_USB_ID_INT_LATCH_CLR_ID_FLOAT_SHIFT              4
2284 #define PALMAS_USB_ID_INT_LATCH_CLR_ID_A                        0x08
2285 #define PALMAS_USB_ID_INT_LATCH_CLR_ID_A_SHIFT                  3
2286 #define PALMAS_USB_ID_INT_LATCH_CLR_ID_B                        0x04
2287 #define PALMAS_USB_ID_INT_LATCH_CLR_ID_B_SHIFT                  2
2288 #define PALMAS_USB_ID_INT_LATCH_CLR_ID_C                        0x02
2289 #define PALMAS_USB_ID_INT_LATCH_CLR_ID_C_SHIFT                  1
2290 #define PALMAS_USB_ID_INT_LATCH_CLR_ID_GND                      0x01
2291 #define PALMAS_USB_ID_INT_LATCH_CLR_ID_GND_SHIFT                0
2292
2293 /* Bit definitions for USB_ID_INT_EN_LO_SET */
2294 #define PALMAS_USB_ID_INT_EN_LO_SET_ID_FLOAT                    0x10
2295 #define PALMAS_USB_ID_INT_EN_LO_SET_ID_FLOAT_SHIFT              4
2296 #define PALMAS_USB_ID_INT_EN_LO_SET_ID_A                        0x08
2297 #define PALMAS_USB_ID_INT_EN_LO_SET_ID_A_SHIFT                  3
2298 #define PALMAS_USB_ID_INT_EN_LO_SET_ID_B                        0x04
2299 #define PALMAS_USB_ID_INT_EN_LO_SET_ID_B_SHIFT                  2
2300 #define PALMAS_USB_ID_INT_EN_LO_SET_ID_C                        0x02
2301 #define PALMAS_USB_ID_INT_EN_LO_SET_ID_C_SHIFT                  1
2302 #define PALMAS_USB_ID_INT_EN_LO_SET_ID_GND                      0x01
2303 #define PALMAS_USB_ID_INT_EN_LO_SET_ID_GND_SHIFT                0
2304
2305 /* Bit definitions for USB_ID_INT_EN_LO_CLR */
2306 #define PALMAS_USB_ID_INT_EN_LO_CLR_ID_FLOAT                    0x10
2307 #define PALMAS_USB_ID_INT_EN_LO_CLR_ID_FLOAT_SHIFT              4
2308 #define PALMAS_USB_ID_INT_EN_LO_CLR_ID_A                        0x08
2309 #define PALMAS_USB_ID_INT_EN_LO_CLR_ID_A_SHIFT                  3
2310 #define PALMAS_USB_ID_INT_EN_LO_CLR_ID_B                        0x04
2311 #define PALMAS_USB_ID_INT_EN_LO_CLR_ID_B_SHIFT                  2
2312 #define PALMAS_USB_ID_INT_EN_LO_CLR_ID_C                        0x02
2313 #define PALMAS_USB_ID_INT_EN_LO_CLR_ID_C_SHIFT                  1
2314 #define PALMAS_USB_ID_INT_EN_LO_CLR_ID_GND                      0x01
2315 #define PALMAS_USB_ID_INT_EN_LO_CLR_ID_GND_SHIFT                0
2316
2317 /* Bit definitions for USB_ID_INT_EN_HI_SET */
2318 #define PALMAS_USB_ID_INT_EN_HI_SET_ID_FLOAT                    0x10
2319 #define PALMAS_USB_ID_INT_EN_HI_SET_ID_FLOAT_SHIFT              4
2320 #define PALMAS_USB_ID_INT_EN_HI_SET_ID_A                        0x08
2321 #define PALMAS_USB_ID_INT_EN_HI_SET_ID_A_SHIFT                  3
2322 #define PALMAS_USB_ID_INT_EN_HI_SET_ID_B                        0x04
2323 #define PALMAS_USB_ID_INT_EN_HI_SET_ID_B_SHIFT                  2
2324 #define PALMAS_USB_ID_INT_EN_HI_SET_ID_C                        0x02
2325 #define PALMAS_USB_ID_INT_EN_HI_SET_ID_C_SHIFT                  1
2326 #define PALMAS_USB_ID_INT_EN_HI_SET_ID_GND                      0x01
2327 #define PALMAS_USB_ID_INT_EN_HI_SET_ID_GND_SHIFT                0
2328
2329 /* Bit definitions for USB_ID_INT_EN_HI_CLR */
2330 #define PALMAS_USB_ID_INT_EN_HI_CLR_ID_FLOAT                    0x10
2331 #define PALMAS_USB_ID_INT_EN_HI_CLR_ID_FLOAT_SHIFT              4
2332 #define PALMAS_USB_ID_INT_EN_HI_CLR_ID_A                        0x08
2333 #define PALMAS_USB_ID_INT_EN_HI_CLR_ID_A_SHIFT                  3
2334 #define PALMAS_USB_ID_INT_EN_HI_CLR_ID_B                        0x04
2335 #define PALMAS_USB_ID_INT_EN_HI_CLR_ID_B_SHIFT                  2
2336 #define PALMAS_USB_ID_INT_EN_HI_CLR_ID_C                        0x02
2337 #define PALMAS_USB_ID_INT_EN_HI_CLR_ID_C_SHIFT                  1
2338 #define PALMAS_USB_ID_INT_EN_HI_CLR_ID_GND                      0x01
2339 #define PALMAS_USB_ID_INT_EN_HI_CLR_ID_GND_SHIFT                0
2340
2341 /* Bit definitions for USB_OTG_ADP_CTRL */
2342 #define PALMAS_USB_OTG_ADP_CTRL_ADP_EN                          0x04
2343 #define PALMAS_USB_OTG_ADP_CTRL_ADP_EN_SHIFT                    2
2344 #define PALMAS_USB_OTG_ADP_CTRL_ADP_MODE_MASK                   0x03
2345 #define PALMAS_USB_OTG_ADP_CTRL_ADP_MODE_SHIFT                  0
2346
2347 /* Bit definitions for USB_OTG_ADP_HIGH */
2348 #define PALMAS_USB_OTG_ADP_HIGH_T_ADP_HIGH_MASK                 0xff
2349 #define PALMAS_USB_OTG_ADP_HIGH_T_ADP_HIGH_SHIFT                0
2350
2351 /* Bit definitions for USB_OTG_ADP_LOW */
2352 #define PALMAS_USB_OTG_ADP_LOW_T_ADP_LOW_MASK                   0xff
2353 #define PALMAS_USB_OTG_ADP_LOW_T_ADP_LOW_SHIFT                  0
2354
2355 /* Bit definitions for USB_OTG_ADP_RISE */
2356 #define PALMAS_USB_OTG_ADP_RISE_T_ADP_RISE_MASK                 0xff
2357 #define PALMAS_USB_OTG_ADP_RISE_T_ADP_RISE_SHIFT                0
2358
2359 /* Bit definitions for USB_OTG_REVISION */
2360 #define PALMAS_USB_OTG_REVISION_OTG_REV                         0x01
2361 #define PALMAS_USB_OTG_REVISION_OTG_REV_SHIFT                   0
2362
2363 /* Registers for function VIBRATOR */
2364 #define PALMAS_VIBRA_CTRL                                       0x0
2365
2366 /* Bit definitions for VIBRA_CTRL */
2367 #define PALMAS_VIBRA_CTRL_PWM_DUTY_SEL_MASK                     0x06
2368 #define PALMAS_VIBRA_CTRL_PWM_DUTY_SEL_SHIFT                    1
2369 #define PALMAS_VIBRA_CTRL_PWM_FREQ_SEL                          0x01
2370 #define PALMAS_VIBRA_CTRL_PWM_FREQ_SEL_SHIFT                    0
2371
2372 /* Registers for function GPIO */
2373 #define PALMAS_GPIO_DATA_IN                                     0x0
2374 #define PALMAS_GPIO_DATA_DIR                                    0x1
2375 #define PALMAS_GPIO_DATA_OUT                                    0x2
2376 #define PALMAS_GPIO_DEBOUNCE_EN                                 0x3
2377 #define PALMAS_GPIO_CLEAR_DATA_OUT                              0x4
2378 #define PALMAS_GPIO_SET_DATA_OUT                                0x5
2379 #define PALMAS_PU_PD_GPIO_CTRL1                                 0x6
2380 #define PALMAS_PU_PD_GPIO_CTRL2                                 0x7
2381 #define PALMAS_OD_OUTPUT_GPIO_CTRL                              0x8
2382
2383 /* Bit definitions for GPIO_DATA_IN */
2384 #define PALMAS_GPIO_DATA_IN_GPIO_7_IN                           0x80
2385 #define PALMAS_GPIO_DATA_IN_GPIO_7_IN_SHIFT                     7
2386 #define PALMAS_GPIO_DATA_IN_GPIO_6_IN                           0x40
2387 #define PALMAS_GPIO_DATA_IN_GPIO_6_IN_SHIFT                     6
2388 #define PALMAS_GPIO_DATA_IN_GPIO_5_IN                           0x20
2389 #define PALMAS_GPIO_DATA_IN_GPIO_5_IN_SHIFT                     5
2390 #define PALMAS_GPIO_DATA_IN_GPIO_4_IN                           0x10
2391 #define PALMAS_GPIO_DATA_IN_GPIO_4_IN_SHIFT                     4
2392 #define PALMAS_GPIO_DATA_IN_GPIO_3_IN                           0x08
2393 #define PALMAS_GPIO_DATA_IN_GPIO_3_IN_SHIFT                     3
2394 #define PALMAS_GPIO_DATA_IN_GPIO_2_IN                           0x04
2395 #define PALMAS_GPIO_DATA_IN_GPIO_2_IN_SHIFT                     2
2396 #define PALMAS_GPIO_DATA_IN_GPIO_1_IN                           0x02
2397 #define PALMAS_GPIO_DATA_IN_GPIO_1_IN_SHIFT                     1
2398 #define PALMAS_GPIO_DATA_IN_GPIO_0_IN                           0x01
2399 #define PALMAS_GPIO_DATA_IN_GPIO_0_IN_SHIFT                     0
2400
2401 /* Bit definitions for GPIO_DATA_DIR */
2402 #define PALMAS_GPIO_DATA_DIR_GPIO_7_DIR                         0x80
2403 #define PALMAS_GPIO_DATA_DIR_GPIO_7_DIR_SHIFT                   7
2404 #define PALMAS_GPIO_DATA_DIR_GPIO_6_DIR                         0x40
2405 #define PALMAS_GPIO_DATA_DIR_GPIO_6_DIR_SHIFT                   6
2406 #define PALMAS_GPIO_DATA_DIR_GPIO_5_DIR                         0x20
2407 #define PALMAS_GPIO_DATA_DIR_GPIO_5_DIR_SHIFT                   5
2408 #define PALMAS_GPIO_DATA_DIR_GPIO_4_DIR                         0x10
2409 #define PALMAS_GPIO_DATA_DIR_GPIO_4_DIR_SHIFT                   4
2410 #define PALMAS_GPIO_DATA_DIR_GPIO_3_DIR                         0x08
2411 #define PALMAS_GPIO_DATA_DIR_GPIO_3_DIR_SHIFT                   3
2412 #define PALMAS_GPIO_DATA_DIR_GPIO_2_DIR                         0x04
2413 #define PALMAS_GPIO_DATA_DIR_GPIO_2_DIR_SHIFT                   2
2414 #define PALMAS_GPIO_DATA_DIR_GPIO_1_DIR                         0x02
2415 #define PALMAS_GPIO_DATA_DIR_GPIO_1_DIR_SHIFT                   1
2416 #define PALMAS_GPIO_DATA_DIR_GPIO_0_DIR                         0x01
2417 #define PALMAS_GPIO_DATA_DIR_GPIO_0_DIR_SHIFT                   0
2418
2419 /* Bit definitions for GPIO_DATA_OUT */
2420 #define PALMAS_GPIO_DATA_OUT_GPIO_7_OUT                         0x80
2421 #define PALMAS_GPIO_DATA_OUT_GPIO_7_OUT_SHIFT                   7
2422 #define PALMAS_GPIO_DATA_OUT_GPIO_6_OUT                         0x40
2423 #define PALMAS_GPIO_DATA_OUT_GPIO_6_OUT_SHIFT                   6
2424 #define PALMAS_GPIO_DATA_OUT_GPIO_5_OUT                         0x20
2425 #define PALMAS_GPIO_DATA_OUT_GPIO_5_OUT_SHIFT                   5
2426 #define PALMAS_GPIO_DATA_OUT_GPIO_4_OUT                         0x10
2427 #define PALMAS_GPIO_DATA_OUT_GPIO_4_OUT_SHIFT                   4
2428 #define PALMAS_GPIO_DATA_OUT_GPIO_3_OUT                         0x08
2429 #define PALMAS_GPIO_DATA_OUT_GPIO_3_OUT_SHIFT                   3
2430 #define PALMAS_GPIO_DATA_OUT_GPIO_2_OUT                         0x04
2431 #define PALMAS_GPIO_DATA_OUT_GPIO_2_OUT_SHIFT                   2
2432 #define PALMAS_GPIO_DATA_OUT_GPIO_1_OUT                         0x02
2433 #define PALMAS_GPIO_DATA_OUT_GPIO_1_OUT_SHIFT                   1
2434 #define PALMAS_GPIO_DATA_OUT_GPIO_0_OUT                         0x01
2435 #define PALMAS_GPIO_DATA_OUT_GPIO_0_OUT_SHIFT                   0
2436
2437 /* Bit definitions for GPIO_DEBOUNCE_EN */
2438 #define PALMAS_GPIO_DEBOUNCE_EN_GPIO_7_DEBOUNCE_EN              0x80
2439 #define PALMAS_GPIO_DEBOUNCE_EN_GPIO_7_DEBOUNCE_EN_SHIFT        7
2440 #define PALMAS_GPIO_DEBOUNCE_EN_GPIO_6_DEBOUNCE_EN              0x40
2441 #define PALMAS_GPIO_DEBOUNCE_EN_GPIO_6_DEBOUNCE_EN_SHIFT        6
2442 #define PALMAS_GPIO_DEBOUNCE_EN_GPIO_5_DEBOUNCE_EN              0x20
2443 #define PALMAS_GPIO_DEBOUNCE_EN_GPIO_5_DEBOUNCE_EN_SHIFT        5
2444 #define PALMAS_GPIO_DEBOUNCE_EN_GPIO_4_DEBOUNCE_EN              0x10
2445 #define PALMAS_GPIO_DEBOUNCE_EN_GPIO_4_DEBOUNCE_EN_SHIFT        4
2446 #define PALMAS_GPIO_DEBOUNCE_EN_GPIO_3_DEBOUNCE_EN              0x08
2447 #define PALMAS_GPIO_DEBOUNCE_EN_GPIO_3_DEBOUNCE_EN_SHIFT        3
2448 #define PALMAS_GPIO_DEBOUNCE_EN_GPIO_2_DEBOUNCE_EN              0x04
2449 #define PALMAS_GPIO_DEBOUNCE_EN_GPIO_2_DEBOUNCE_EN_SHIFT        2
2450 #define PALMAS_GPIO_DEBOUNCE_EN_GPIO_1_DEBOUNCE_EN              0x02
2451 #define PALMAS_GPIO_DEBOUNCE_EN_GPIO_1_DEBOUNCE_EN_SHIFT        1
2452 #define PALMAS_GPIO_DEBOUNCE_EN_GPIO_0_DEBOUNCE_EN              0x01
2453 #define PALMAS_GPIO_DEBOUNCE_EN_GPIO_0_DEBOUNCE_EN_SHIFT        0
2454
2455 /* Bit definitions for GPIO_CLEAR_DATA_OUT */
2456 #define PALMAS_GPIO_CLEAR_DATA_OUT_GPIO_7_CLEAR_DATA_OUT        0x80
2457 #define PALMAS_GPIO_CLEAR_DATA_OUT_GPIO_7_CLEAR_DATA_OUT_SHIFT  7
2458 #define PALMAS_GPIO_CLEAR_DATA_OUT_GPIO_6_CLEAR_DATA_OUT        0x40
2459 #define PALMAS_GPIO_CLEAR_DATA_OUT_GPIO_6_CLEAR_DATA_OUT_SHIFT  6
2460 #define PALMAS_GPIO_CLEAR_DATA_OUT_GPIO_5_CLEAR_DATA_OUT        0x20
2461 #define PALMAS_GPIO_CLEAR_DATA_OUT_GPIO_5_CLEAR_DATA_OUT_SHIFT  5
2462 #define PALMAS_GPIO_CLEAR_DATA_OUT_GPIO_4_CLEAR_DATA_OUT        0x10
2463 #define PALMAS_GPIO_CLEAR_DATA_OUT_GPIO_4_CLEAR_DATA_OUT_SHIFT  4
2464 #define PALMAS_GPIO_CLEAR_DATA_OUT_GPIO_3_CLEAR_DATA_OUT        0x08
2465 #define PALMAS_GPIO_CLEAR_DATA_OUT_GPIO_3_CLEAR_DATA_OUT_SHIFT  3
2466 #define PALMAS_GPIO_CLEAR_DATA_OUT_GPIO_2_CLEAR_DATA_OUT        0x04
2467 #define PALMAS_GPIO_CLEAR_DATA_OUT_GPIO_2_CLEAR_DATA_OUT_SHIFT  2
2468 #define PALMAS_GPIO_CLEAR_DATA_OUT_GPIO_1_CLEAR_DATA_OUT        0x02
2469 #define PALMAS_GPIO_CLEAR_DATA_OUT_GPIO_1_CLEAR_DATA_OUT_SHIFT  1
2470 #define PALMAS_GPIO_CLEAR_DATA_OUT_GPIO_0_CLEAR_DATA_OUT        0x01
2471 #define PALMAS_GPIO_CLEAR_DATA_OUT_GPIO_0_CLEAR_DATA_OUT_SHIFT  0
2472
2473 /* Bit definitions for GPIO_SET_DATA_OUT */
2474 #define PALMAS_GPIO_SET_DATA_OUT_GPIO_7_SET_DATA_OUT            0x80
2475 #define PALMAS_GPIO_SET_DATA_OUT_GPIO_7_SET_DATA_OUT_SHIFT      7
2476 #define PALMAS_GPIO_SET_DATA_OUT_GPIO_6_SET_DATA_OUT            0x40
2477 #define PALMAS_GPIO_SET_DATA_OUT_GPIO_6_SET_DATA_OUT_SHIFT      6
2478 #define PALMAS_GPIO_SET_DATA_OUT_GPIO_5_SET_DATA_OUT            0x20
2479 #define PALMAS_GPIO_SET_DATA_OUT_GPIO_5_SET_DATA_OUT_SHIFT      5
2480 #define PALMAS_GPIO_SET_DATA_OUT_GPIO_4_SET_DATA_OUT            0x10
2481 #define PALMAS_GPIO_SET_DATA_OUT_GPIO_4_SET_DATA_OUT_SHIFT      4
2482 #define PALMAS_GPIO_SET_DATA_OUT_GPIO_3_SET_DATA_OUT            0x08
2483 #define PALMAS_GPIO_SET_DATA_OUT_GPIO_3_SET_DATA_OUT_SHIFT      3
2484 #define PALMAS_GPIO_SET_DATA_OUT_GPIO_2_SET_DATA_OUT            0x04
2485 #define PALMAS_GPIO_SET_DATA_OUT_GPIO_2_SET_DATA_OUT_SHIFT      2
2486 #define PALMAS_GPIO_SET_DATA_OUT_GPIO_1_SET_DATA_OUT            0x02
2487 #define PALMAS_GPIO_SET_DATA_OUT_GPIO_1_SET_DATA_OUT_SHIFT      1
2488 #define PALMAS_GPIO_SET_DATA_OUT_GPIO_0_SET_DATA_OUT            0x01
2489 #define PALMAS_GPIO_SET_DATA_OUT_GPIO_0_SET_DATA_OUT_SHIFT      0
2490
2491 /* Bit definitions for PU_PD_GPIO_CTRL1 */
2492 #define PALMAS_PU_PD_GPIO_CTRL1_GPIO_3_PD                       0x40
2493 #define PALMAS_PU_PD_GPIO_CTRL1_GPIO_3_PD_SHIFT                 6
2494 #define PALMAS_PU_PD_GPIO_CTRL1_GPIO_2_PU                       0x20
2495 #define PALMAS_PU_PD_GPIO_CTRL1_GPIO_2_PU_SHIFT                 5
2496 #define PALMAS_PU_PD_GPIO_CTRL1_GPIO_2_PD                       0x10
2497 #define PALMAS_PU_PD_GPIO_CTRL1_GPIO_2_PD_SHIFT                 4
2498 #define PALMAS_PU_PD_GPIO_CTRL1_GPIO_1_PU                       0x08
2499 #define PALMAS_PU_PD_GPIO_CTRL1_GPIO_1_PU_SHIFT                 3
2500 #define PALMAS_PU_PD_GPIO_CTRL1_GPIO_1_PD                       0x04
2501 #define PALMAS_PU_PD_GPIO_CTRL1_GPIO_1_PD_SHIFT                 2
2502 #define PALMAS_PU_PD_GPIO_CTRL1_GPIO_0_PD                       0x01
2503 #define PALMAS_PU_PD_GPIO_CTRL1_GPIO_0_PD_SHIFT                 0
2504
2505 /* Bit definitions for PU_PD_GPIO_CTRL2 */
2506 #define PALMAS_PU_PD_GPIO_CTRL2_GPIO_7_PD                       0x40
2507 #define PALMAS_PU_PD_GPIO_CTRL2_GPIO_7_PD_SHIFT                 6
2508 #define PALMAS_PU_PD_GPIO_CTRL2_GPIO_6_PU                       0x20
2509 #define PALMAS_PU_PD_GPIO_CTRL2_GPIO_6_PU_SHIFT                 5
2510 #define PALMAS_PU_PD_GPIO_CTRL2_GPIO_6_PD                       0x10
2511 #define PALMAS_PU_PD_GPIO_CTRL2_GPIO_6_PD_SHIFT                 4
2512 #define PALMAS_PU_PD_GPIO_CTRL2_GPIO_5_PU                       0x08
2513 #define PALMAS_PU_PD_GPIO_CTRL2_GPIO_5_PU_SHIFT                 3
2514 #define PALMAS_PU_PD_GPIO_CTRL2_GPIO_5_PD                       0x04
2515 #define PALMAS_PU_PD_GPIO_CTRL2_GPIO_5_PD_SHIFT                 2
2516 #define PALMAS_PU_PD_GPIO_CTRL2_GPIO_4_PU                       0x02
2517 #define PALMAS_PU_PD_GPIO_CTRL2_GPIO_4_PU_SHIFT                 1
2518 #define PALMAS_PU_PD_GPIO_CTRL2_GPIO_4_PD                       0x01
2519 #define PALMAS_PU_PD_GPIO_CTRL2_GPIO_4_PD_SHIFT                 0
2520
2521 /* Bit definitions for OD_OUTPUT_GPIO_CTRL */
2522 #define PALMAS_OD_OUTPUT_GPIO_CTRL_GPIO_5_OD                    0x20
2523 #define PALMAS_OD_OUTPUT_GPIO_CTRL_GPIO_5_OD_SHIFT              5
2524 #define PALMAS_OD_OUTPUT_GPIO_CTRL_GPIO_2_OD                    0x04
2525 #define PALMAS_OD_OUTPUT_GPIO_CTRL_GPIO_2_OD_SHIFT              2
2526 #define PALMAS_OD_OUTPUT_GPIO_CTRL_GPIO_1_OD                    0x02
2527 #define PALMAS_OD_OUTPUT_GPIO_CTRL_GPIO_1_OD_SHIFT              1
2528
2529 /* Registers for function GPADC */
2530 #define PALMAS_GPADC_CTRL1                                      0x0
2531 #define PALMAS_GPADC_CTRL2                                      0x1
2532 #define PALMAS_GPADC_RT_CTRL                                    0x2
2533 #define PALMAS_GPADC_AUTO_CTRL                                  0x3
2534 #define PALMAS_GPADC_STATUS                                     0x4
2535 #define PALMAS_GPADC_RT_SELECT                                  0x5
2536 #define PALMAS_GPADC_RT_CONV0_LSB                               0x6
2537 #define PALMAS_GPADC_RT_CONV0_MSB                               0x7
2538 #define PALMAS_GPADC_AUTO_SELECT                                0x8
2539 #define PALMAS_GPADC_AUTO_CONV0_LSB                             0x9
2540 #define PALMAS_GPADC_AUTO_CONV0_MSB                             0xA
2541 #define PALMAS_GPADC_AUTO_CONV1_LSB                             0xB
2542 #define PALMAS_GPADC_AUTO_CONV1_MSB                             0xC
2543 #define PALMAS_GPADC_SW_SELECT                                  0xD
2544 #define PALMAS_GPADC_SW_CONV0_LSB                               0xE
2545 #define PALMAS_GPADC_SW_CONV0_MSB                               0xF
2546 #define PALMAS_GPADC_THRES_CONV0_LSB                            0x10
2547 #define PALMAS_GPADC_THRES_CONV0_MSB                            0x11
2548 #define PALMAS_GPADC_THRES_CONV1_LSB                            0x12
2549 #define PALMAS_GPADC_THRES_CONV1_MSB                            0x13
2550 #define PALMAS_GPADC_SMPS_ILMONITOR_EN                          0x14
2551 #define PALMAS_GPADC_SMPS_VSEL_MONITORING                       0x15
2552
2553 /* Bit definitions for GPADC_CTRL1 */
2554 #define PALMAS_GPADC_CTRL1_RESERVED_MASK                        0xc0
2555 #define PALMAS_GPADC_CTRL1_RESERVED_SHIFT                       6
2556 #define PALMAS_GPADC_CTRL1_CURRENT_SRC_CH3_MASK                 0x30
2557 #define PALMAS_GPADC_CTRL1_CURRENT_SRC_CH3_SHIFT                4
2558 #define PALMAS_GPADC_CTRL1_CURRENT_SRC_CH0_MASK                 0x0c
2559 #define PALMAS_GPADC_CTRL1_CURRENT_SRC_CH0_SHIFT                2
2560 #define PALMAS_GPADC_CTRL1_BAT_REMOVAL_DET                      0x02
2561 #define PALMAS_GPADC_CTRL1_BAT_REMOVAL_DET_SHIFT                1
2562 #define PALMAS_GPADC_CTRL1_GPADC_FORCE                          0x01
2563 #define PALMAS_GPADC_CTRL1_GPADC_FORCE_SHIFT                    0
2564
2565 /* Bit definitions for GPADC_CTRL2 */
2566 #define PALMAS_GPADC_CTRL2_RESERVED_MASK                        0x06
2567 #define PALMAS_GPADC_CTRL2_RESERVED_SHIFT                       1
2568
2569 /* Bit definitions for GPADC_RT_CTRL */
2570 #define PALMAS_GPADC_RT_CTRL_EXTEND_DELAY                       0x02
2571 #define PALMAS_GPADC_RT_CTRL_EXTEND_DELAY_SHIFT                 1
2572 #define PALMAS_GPADC_RT_CTRL_START_POLARITY                     0x01
2573 #define PALMAS_GPADC_RT_CTRL_START_POLARITY_SHIFT               0
2574
2575 /* Bit definitions for GPADC_AUTO_CTRL */
2576 #define PALMAS_GPADC_AUTO_CTRL_SHUTDOWN_CONV1                   0x80
2577 #define PALMAS_GPADC_AUTO_CTRL_SHUTDOWN_CONV1_SHIFT             7
2578 #define PALMAS_GPADC_AUTO_CTRL_SHUTDOWN_CONV0                   0x40
2579 #define PALMAS_GPADC_AUTO_CTRL_SHUTDOWN_CONV0_SHIFT             6
2580 #define PALMAS_GPADC_AUTO_CTRL_AUTO_CONV1_EN                    0x20
2581 #define PALMAS_GPADC_AUTO_CTRL_AUTO_CONV1_EN_SHIFT              5
2582 #define PALMAS_GPADC_AUTO_CTRL_AUTO_CONV0_EN                    0x10
2583 #define PALMAS_GPADC_AUTO_CTRL_AUTO_CONV0_EN_SHIFT              4
2584 #define PALMAS_GPADC_AUTO_CTRL_COUNTER_CONV_MASK                0x0f
2585 #define PALMAS_GPADC_AUTO_CTRL_COUNTER_CONV_SHIFT               0
2586
2587 /* Bit definitions for GPADC_STATUS */
2588 #define PALMAS_GPADC_STATUS_GPADC_AVAILABLE                     0x10
2589 #define PALMAS_GPADC_STATUS_GPADC_AVAILABLE_SHIFT               4
2590
2591 /* Bit definitions for GPADC_RT_SELECT */
2592 #define PALMAS_GPADC_RT_SELECT_RT_CONV_EN                       0x80
2593 #define PALMAS_GPADC_RT_SELECT_RT_CONV_EN_SHIFT                 7
2594 #define PALMAS_GPADC_RT_SELECT_RT_CONV0_SEL_MASK                0x0f
2595 #define PALMAS_GPADC_RT_SELECT_RT_CONV0_SEL_SHIFT               0
2596
2597 /* Bit definitions for GPADC_RT_CONV0_LSB */
2598 #define PALMAS_GPADC_RT_CONV0_LSB_RT_CONV0_LSB_MASK             0xff
2599 #define PALMAS_GPADC_RT_CONV0_LSB_RT_CONV0_LSB_SHIFT            0
2600
2601 /* Bit definitions for GPADC_RT_CONV0_MSB */
2602 #define PALMAS_GPADC_RT_CONV0_MSB_RT_CONV0_MSB_MASK             0x0f
2603 #define PALMAS_GPADC_RT_CONV0_MSB_RT_CONV0_MSB_SHIFT            0
2604
2605 /* Bit definitions for GPADC_AUTO_SELECT */
2606 #define PALMAS_GPADC_AUTO_SELECT_AUTO_CONV1_SEL_MASK            0xf0
2607 #define PALMAS_GPADC_AUTO_SELECT_AUTO_CONV1_SEL_SHIFT           4
2608 #define PALMAS_GPADC_AUTO_SELECT_AUTO_CONV0_SEL_MASK            0x0f
2609 #define PALMAS_GPADC_AUTO_SELECT_AUTO_CONV0_SEL_SHIFT           0
2610
2611 /* Bit definitions for GPADC_AUTO_CONV0_LSB */
2612 #define PALMAS_GPADC_AUTO_CONV0_LSB_AUTO_CONV0_LSB_MASK         0xff
2613 #define PALMAS_GPADC_AUTO_CONV0_LSB_AUTO_CONV0_LSB_SHIFT        0
2614
2615 /* Bit definitions for GPADC_AUTO_CONV0_MSB */
2616 #define PALMAS_GPADC_AUTO_CONV0_MSB_AUTO_CONV0_MSB_MASK         0x0f
2617 #define PALMAS_GPADC_AUTO_CONV0_MSB_AUTO_CONV0_MSB_SHIFT        0
2618
2619 /* Bit definitions for GPADC_AUTO_CONV1_LSB */
2620 #define PALMAS_GPADC_AUTO_CONV1_LSB_AUTO_CONV1_LSB_MASK         0xff
2621 #define PALMAS_GPADC_AUTO_CONV1_LSB_AUTO_CONV1_LSB_SHIFT        0
2622
2623 /* Bit definitions for GPADC_AUTO_CONV1_MSB */
2624 #define PALMAS_GPADC_AUTO_CONV1_MSB_AUTO_CONV1_MSB_MASK         0x0f
2625 #define PALMAS_GPADC_AUTO_CONV1_MSB_AUTO_CONV1_MSB_SHIFT        0
2626
2627 /* Bit definitions for GPADC_SW_SELECT */
2628 #define PALMAS_GPADC_SW_SELECT_SW_CONV_EN                       0x80
2629 #define PALMAS_GPADC_SW_SELECT_SW_CONV_EN_SHIFT                 7
2630 #define PALMAS_GPADC_SW_SELECT_SW_START_CONV0                   0x10
2631 #define PALMAS_GPADC_SW_SELECT_SW_START_CONV0_SHIFT             4
2632 #define PALMAS_GPADC_SW_SELECT_SW_CONV0_SEL_MASK                0x0f
2633 #define PALMAS_GPADC_SW_SELECT_SW_CONV0_SEL_SHIFT               0
2634
2635 /* Bit definitions for GPADC_SW_CONV0_LSB */
2636 #define PALMAS_GPADC_SW_CONV0_LSB_SW_CONV0_LSB_MASK             0xff
2637 #define PALMAS_GPADC_SW_CONV0_LSB_SW_CONV0_LSB_SHIFT            0
2638
2639 /* Bit definitions for GPADC_SW_CONV0_MSB */
2640 #define PALMAS_GPADC_SW_CONV0_MSB_SW_CONV0_MSB_MASK             0x0f
2641 #define PALMAS_GPADC_SW_CONV0_MSB_SW_CONV0_MSB_SHIFT            0
2642
2643 /* Bit definitions for GPADC_THRES_CONV0_LSB */
2644 #define PALMAS_GPADC_THRES_CONV0_LSB_THRES_CONV0_LSB_MASK       0xff
2645 #define PALMAS_GPADC_THRES_CONV0_LSB_THRES_CONV0_LSB_SHIFT      0
2646
2647 /* Bit definitions for GPADC_THRES_CONV0_MSB */
2648 #define PALMAS_GPADC_THRES_CONV0_MSB_THRES_CONV0_POL            0x80
2649 #define PALMAS_GPADC_THRES_CONV0_MSB_THRES_CONV0_POL_SHIFT      7
2650 #define PALMAS_GPADC_THRES_CONV0_MSB_THRES_CONV0_MSB_MASK       0x0f
2651 #define PALMAS_GPADC_THRES_CONV0_MSB_THRES_CONV0_MSB_SHIFT      0
2652
2653 /* Bit definitions for GPADC_THRES_CONV1_LSB */
2654 #define PALMAS_GPADC_THRES_CONV1_LSB_THRES_CONV1_LSB_MASK       0xff
2655 #define PALMAS_GPADC_THRES_CONV1_LSB_THRES_CONV1_LSB_SHIFT      0
2656
2657 /* Bit definitions for GPADC_THRES_CONV1_MSB */
2658 #define PALMAS_GPADC_THRES_CONV1_MSB_THRES_CONV1_POL            0x80
2659 #define PALMAS_GPADC_THRES_CONV1_MSB_THRES_CONV1_POL_SHIFT      7
2660 #define PALMAS_GPADC_THRES_CONV1_MSB_THRES_CONV1_MSB_MASK       0x0f
2661 #define PALMAS_GPADC_THRES_CONV1_MSB_THRES_CONV1_MSB_SHIFT      0
2662
2663 /* Bit definitions for GPADC_SMPS_ILMONITOR_EN */
2664 #define PALMAS_GPADC_SMPS_ILMONITOR_EN_SMPS_ILMON_EN            0x20
2665 #define PALMAS_GPADC_SMPS_ILMONITOR_EN_SMPS_ILMON_EN_SHIFT      5
2666 #define PALMAS_GPADC_SMPS_ILMONITOR_EN_SMPS_ILMON_REXT          0x10
2667 #define PALMAS_GPADC_SMPS_ILMONITOR_EN_SMPS_ILMON_REXT_SHIFT    4
2668 #define PALMAS_GPADC_SMPS_ILMONITOR_EN_SMPS_ILMON_SEL_MASK      0x0f
2669 #define PALMAS_GPADC_SMPS_ILMONITOR_EN_SMPS_ILMON_SEL_SHIFT     0
2670
2671 /* Bit definitions for GPADC_SMPS_VSEL_MONITORING */
2672 #define PALMAS_GPADC_SMPS_VSEL_MONITORING_ACTIVE_PHASE          0x80
2673 #define PALMAS_GPADC_SMPS_VSEL_MONITORING_ACTIVE_PHASE_SHIFT    7
2674 #define PALMAS_GPADC_SMPS_VSEL_MONITORING_SMPS_VSEL_MONITORING_MASK     0x7f
2675 #define PALMAS_GPADC_SMPS_VSEL_MONITORING_SMPS_VSEL_MONITORING_SHIFT    0
2676
2677 #define PALMAS_INTERNAL_DESIGNREV                               0x57
2678 #define PALMAS_INTERNAL_DESIGNREV_DESIGNREV(val)                ((val) & 0xF)
2679
2680 /* Registers for function GPADC */
2681 #define PALMAS_GPADC_TRIM1                                      0x0
2682 #define PALMAS_GPADC_TRIM2                                      0x1
2683 #define PALMAS_GPADC_TRIM3                                      0x2
2684 #define PALMAS_GPADC_TRIM4                                      0x3
2685 #define PALMAS_GPADC_TRIM5                                      0x4
2686 #define PALMAS_GPADC_TRIM6                                      0x5
2687 #define PALMAS_GPADC_TRIM7                                      0x6
2688 #define PALMAS_GPADC_TRIM8                                      0x7
2689 #define PALMAS_GPADC_TRIM9                                      0x8
2690 #define PALMAS_GPADC_TRIM10                                     0x9
2691 #define PALMAS_GPADC_TRIM11                                     0xA
2692 #define PALMAS_GPADC_TRIM12                                     0xB
2693 #define PALMAS_GPADC_TRIM13                                     0xC
2694 #define PALMAS_GPADC_TRIM14                                     0xD
2695 #define PALMAS_GPADC_TRIM15                                     0xE
2696 #define PALMAS_GPADC_TRIM16                                     0xF
2697
2698 enum {
2699         PALMAS_EXT_CONTROL_ENABLE1      = 0x1,
2700         PALMAS_EXT_CONTROL_ENABLE2      = 0x2,
2701         PALMAS_EXT_CONTROL_NSLEEP       = 0x4,
2702 };
2703
2704 /*
2705  *PALMAS GPIOs
2706  */
2707 enum {
2708         PALMAS_GPIO0,
2709         PALMAS_GPIO1,
2710         PALMAS_GPIO2,
2711         PALMAS_GPIO3,
2712         PALMAS_GPIO4,
2713         PALMAS_GPIO5,
2714         PALMAS_GPIO6,
2715         PALMAS_GPIO7,
2716
2717         PALMAS_GPIO_NR,
2718 };
2719
2720 /* Palma Sleep requestor IDs IDs */
2721 enum {
2722         PALMAS_SLEEP_REQSTR_ID_REGEN1,
2723         PALMAS_SLEEP_REQSTR_ID_REGEN2,
2724         PALMAS_SLEEP_REQSTR_ID_SYSEN1,
2725         PALMAS_SLEEP_REQSTR_ID_SYSEN2,
2726         PALMAS_SLEEP_REQSTR_ID_CLK32KG,
2727         PALMAS_SLEEP_REQSTR_ID_CLK32KGAUDIO,
2728         PALMAS_SLEEP_REQSTR_ID_REGEN3,
2729         PALMAS_SLEEP_REQSTR_ID_SMPS12,
2730         PALMAS_SLEEP_REQSTR_ID_SMPS3,
2731         PALMAS_SLEEP_REQSTR_ID_SMPS45,
2732         PALMAS_SLEEP_REQSTR_ID_SMPS6,
2733         PALMAS_SLEEP_REQSTR_ID_SMPS7,
2734         PALMAS_SLEEP_REQSTR_ID_SMPS8,
2735         PALMAS_SLEEP_REQSTR_ID_SMPS9,
2736         PALMAS_SLEEP_REQSTR_ID_SMPS10,
2737         PALMAS_SLEEP_REQSTR_ID_LDO1,
2738         PALMAS_SLEEP_REQSTR_ID_LDO2,
2739         PALMAS_SLEEP_REQSTR_ID_LDO3,
2740         PALMAS_SLEEP_REQSTR_ID_LDO4,
2741         PALMAS_SLEEP_REQSTR_ID_LDO5,
2742         PALMAS_SLEEP_REQSTR_ID_LDO6,
2743         PALMAS_SLEEP_REQSTR_ID_LDO7,
2744         PALMAS_SLEEP_REQSTR_ID_LDO8,
2745         PALMAS_SLEEP_REQSTR_ID_LDO9,
2746         PALMAS_SLEEP_REQSTR_ID_LDOLN,
2747         PALMAS_SLEEP_REQSTR_ID_LDOUSB,
2748
2749         /* Last entry */
2750         PALMAS_SLEEP_REQSTR_ID_MAX,
2751 };
2752
2753 extern int palmas_ext_power_req_config(struct palmas *palmas,
2754                 int id,  int ext_pwr_ctrl, bool enable);
2755
2756 static inline int palmas_read(struct palmas *palmas, unsigned int base,
2757                 unsigned int reg, unsigned int *val)
2758 {
2759         unsigned int addr =  PALMAS_BASE_TO_REG(base, reg);
2760         int slave_id = PALMAS_BASE_TO_SLAVE(base);
2761
2762         return regmap_read(palmas->regmap[slave_id], addr, val);
2763 }
2764
2765 static inline int palmas_write(struct palmas *palmas, unsigned int base,
2766                 unsigned int reg, unsigned int value)
2767 {
2768         unsigned int addr = PALMAS_BASE_TO_REG(base, reg);
2769         int slave_id = PALMAS_BASE_TO_SLAVE(base);
2770
2771         return regmap_write(palmas->regmap[slave_id], addr, value);
2772 }
2773
2774 static inline int palmas_bulk_write(struct palmas *palmas, unsigned int base,
2775         unsigned int reg, const void *val, size_t val_count)
2776 {
2777         unsigned int addr = PALMAS_BASE_TO_REG(base, reg);
2778         int slave_id = PALMAS_BASE_TO_SLAVE(base);
2779
2780         return regmap_bulk_write(palmas->regmap[slave_id], addr,
2781                         val, val_count);
2782 }
2783
2784 static inline int palmas_bulk_read(struct palmas *palmas, unsigned int base,
2785                 unsigned int reg, void *val, size_t val_count)
2786 {
2787         unsigned int addr = PALMAS_BASE_TO_REG(base, reg);
2788         int slave_id = PALMAS_BASE_TO_SLAVE(base);
2789
2790         return regmap_bulk_read(palmas->regmap[slave_id], addr,
2791                 val, val_count);
2792 }
2793
2794 static inline int palmas_update_bits(struct palmas *palmas, unsigned int base,
2795         unsigned int reg, unsigned int mask, unsigned int val)
2796 {
2797         unsigned int addr = PALMAS_BASE_TO_REG(base, reg);
2798         int slave_id = PALMAS_BASE_TO_SLAVE(base);
2799
2800         return regmap_update_bits(palmas->regmap[slave_id], addr, mask, val);
2801 }
2802
2803 static inline int palmas_irq_get_virq(struct palmas *palmas, int irq)
2804 {
2805         return regmap_irq_get_virq(palmas->irq_data, irq);
2806 }
2807
2808 #endif /*  __LINUX_MFD_PALMAS_H */