regulator: palma: support for external regulator
[linux-2.6.git] / include / linux / mfd / palmas.h
1 /*
2  * TI Palmas
3  *
4  * Copyright 2011 Texas Instruments Inc.
5  *
6  * Author: Graeme Gregory <gg@slimlogic.co.uk>
7  *
8  *  This program is free software; you can redistribute it and/or modify it
9  *  under  the terms of the GNU General  Public License as published by the
10  *  Free Software Foundation;  either version 2 of the License, or (at your
11  *  option) any later version.
12  *
13  */
14
15 #ifndef __LINUX_MFD_PALMAS_H
16 #define __LINUX_MFD_PALMAS_H
17
18 #include <linux/usb/otg.h>
19 #include <linux/leds.h>
20 #include <linux/regmap.h>
21 #include <linux/regulator/driver.h>
22
23 #define PALMAS_NUM_CLIENTS              3
24
25 struct palmas_pmic;
26 struct palmas_rtc;
27
28 #define palmas_rails(_name) "palmas_"#_name
29
30 struct palmas {
31         struct device *dev;
32
33         struct i2c_client *i2c_clients[PALMAS_NUM_CLIENTS];
34         struct regmap *regmap[PALMAS_NUM_CLIENTS];
35
36         /* Stored chip id */
37         int id;
38
39         /* IRQ Data */
40         int irq;
41         u32 irq_mask;
42         struct mutex irq_lock;
43         struct regmap_irq_chip_data *irq_data;
44
45         /* Child Devices */
46         struct palmas_pmic *pmic;
47         struct palmas_rtc *rtc;
48
49         /* GPIO MUXing */
50         u8 gpio_muxed;
51         u8 led_muxed;
52         u8 pwm_muxed;
53 };
54
55 struct palmas_reg_init {
56         /* warm_rest controls the voltage levels after a warm reset
57          *
58          * 0: reload default values from OTP on warm reset
59          * 1: maintain voltage from VSEL on warm reset
60          */
61         int warm_reset;
62
63         /* roof_floor controls whether the regulator uses the i2c style
64          * of DVS or uses the method where a GPIO or other control method is
65          * attached to the NSLEEP/ENABLE1/ENABLE2 pins
66          *
67          * For SMPS
68          *
69          * 0: i2c selection of voltage
70          * 1: pin selection of voltage.
71          *
72          * For LDO unused
73          */
74         int roof_floor;
75
76         /* sleep_mode is the mode loaded to MODE_SLEEP bits as defined in
77          * the data sheet.
78          *
79          * For SMPS
80          *
81          * 0: Off
82          * 1: AUTO
83          * 2: ECO
84          * 3: Forced PWM
85          *
86          * For LDO
87          *
88          * 0: Off
89          * 1: On
90          */
91         int mode_sleep;
92
93         /* tstep is the timestep loaded to the TSTEP register
94          *
95          * For SMPS
96          *
97          * 0: Jump (no slope control)
98          * 1: 10mV/us
99          * 2: 5mV/us
100          * 3: 2.5mV/us
101          *
102          * For LDO unused
103          */
104         int tstep;
105
106         /* voltage_sel is the bitfield loaded onto the SMPSX_VOLTAGE
107          * register. Set this is the default voltage set in OTP needs
108          * to be overridden.
109          */
110         u8 vsel;
111
112 };
113
114 enum palmas_regulators {
115         /* SMPS regulators */
116         PALMAS_REG_SMPS12,
117         PALMAS_REG_SMPS123,
118         PALMAS_REG_SMPS3,
119         PALMAS_REG_SMPS45,
120         PALMAS_REG_SMPS457,
121         PALMAS_REG_SMPS6,
122         PALMAS_REG_SMPS7,
123         PALMAS_REG_SMPS8,
124         PALMAS_REG_SMPS9,
125         PALMAS_REG_SMPS10,
126         /* LDO regulators */
127         PALMAS_REG_LDO1,
128         PALMAS_REG_LDO2,
129         PALMAS_REG_LDO3,
130         PALMAS_REG_LDO4,
131         PALMAS_REG_LDO5,
132         PALMAS_REG_LDO6,
133         PALMAS_REG_LDO7,
134         PALMAS_REG_LDO8,
135         PALMAS_REG_LDO9,
136         PALMAS_REG_LDOLN,
137         PALMAS_REG_LDOUSB,
138         /* External regulators */
139         PALMAS_REG_REGEN1,
140         PALMAS_REG_REGEN2,
141         PALMAS_REG_REGEN3,
142         PALMAS_REG_SYSEN1,
143         PALMAS_REG_SYSEN2,
144         /* Total number of regulators */
145         PALMAS_NUM_REGS,
146 };
147
148 struct palmas_pmic_platform_data {
149         /* An array of pointers to regulator init data indexed by regulator
150          * ID
151          */
152         struct regulator_init_data **reg_data;
153
154         /* An array of pointers to structures containing sleep mode and DVS
155          * configuration for regulators indexed by ID
156          */
157         struct palmas_reg_init **reg_init;
158
159         /* use LDO6 for vibrator control */
160         int ldo6_vibrator;
161
162
163 };
164
165 struct palmas_platform_data {
166         int gpio_base;
167         int irq_base;
168
169         /* bit value to be loaded to the POWER_CTRL register */
170         u8 power_ctrl;
171
172         /*
173          * boolean to select if we want to configure muxing here
174          * then the two value to load into the registers if true
175          */
176         int mux_from_pdata;
177         u8 pad1, pad2;
178
179         struct palmas_pmic_platform_data *pmic_pdata;
180 };
181
182 /* Define the palmas IRQ numbers */
183 enum palmas_irqs {
184         /* INT1 registers */
185         PALMAS_CHARG_DET_N_VBUS_OVV_IRQ,
186         PALMAS_PWRON_IRQ,
187         PALMAS_LONG_PRESS_KEY_IRQ,
188         PALMAS_RPWRON_IRQ,
189         PALMAS_PWRDOWN_IRQ,
190         PALMAS_HOTDIE_IRQ,
191         PALMAS_VSYS_MON_IRQ,
192         PALMAS_VBAT_MON_IRQ,
193         /* INT2 registers */
194         PALMAS_RTC_ALARM_IRQ,
195         PALMAS_RTC_TIMER_IRQ,
196         PALMAS_WDT_IRQ,
197         PALMAS_BATREMOVAL_IRQ,
198         PALMAS_RESET_IN_IRQ,
199         PALMAS_FBI_BB_IRQ,
200         PALMAS_SHORT_IRQ,
201         PALMAS_VAC_ACOK_IRQ,
202         /* INT3 registers */
203         PALMAS_GPADC_AUTO_0_IRQ,
204         PALMAS_GPADC_AUTO_1_IRQ,
205         PALMAS_GPADC_EOC_SW_IRQ,
206         PALMAS_GPADC_EOC_RT_IRQ,
207         PALMAS_ID_OTG_IRQ,
208         PALMAS_ID_IRQ,
209         PALMAS_VBUS_OTG_IRQ,
210         PALMAS_VBUS_IRQ,
211         /* INT4 registers */
212         PALMAS_GPIO_0_IRQ,
213         PALMAS_GPIO_1_IRQ,
214         PALMAS_GPIO_2_IRQ,
215         PALMAS_GPIO_3_IRQ,
216         PALMAS_GPIO_4_IRQ,
217         PALMAS_GPIO_5_IRQ,
218         PALMAS_GPIO_6_IRQ,
219         PALMAS_GPIO_7_IRQ,
220         /* Total Number IRQs */
221         PALMAS_NUM_IRQ,
222 };
223
224 struct palmas_pmic {
225         struct palmas *palmas;
226         struct device *dev;
227         struct regulator_desc desc[PALMAS_NUM_REGS];
228         struct regulator_dev *rdev[PALMAS_NUM_REGS];
229         struct mutex mutex;
230
231         int smps123;
232         int smps457;
233
234         int range[PALMAS_REG_SMPS10];
235 };
236
237 /* defines so we can store the mux settings */
238 #define PALMAS_GPIO_0_MUXED                                     (1 << 0)
239 #define PALMAS_GPIO_1_MUXED                                     (1 << 1)
240 #define PALMAS_GPIO_2_MUXED                                     (1 << 2)
241 #define PALMAS_GPIO_3_MUXED                                     (1 << 3)
242 #define PALMAS_GPIO_4_MUXED                                     (1 << 4)
243 #define PALMAS_GPIO_5_MUXED                                     (1 << 5)
244 #define PALMAS_GPIO_6_MUXED                                     (1 << 6)
245 #define PALMAS_GPIO_7_MUXED                                     (1 << 7)
246
247 #define PALMAS_LED1_MUXED                                       (1 << 0)
248 #define PALMAS_LED2_MUXED                                       (1 << 1)
249
250 #define PALMAS_PWM1_MUXED                                       (1 << 0)
251 #define PALMAS_PWM2_MUXED                                       (1 << 1)
252
253 /* helper macro to get correct slave number */
254 #define PALMAS_BASE_TO_SLAVE(x)         ((x >> 8) - 1)
255 #define PALMAS_BASE_TO_REG(x, y)        ((x & 0xff) + y)
256 #define RTC_SLAVE                       0
257
258 /* Base addresses of IP blocks in Palmas */
259 #define PALMAS_SMPS_DVS_BASE                                    0x20
260 #define PALMAS_RTC_BASE                                         0x100
261 #define PALMAS_VALIDITY_BASE                                    0x118
262 #define PALMAS_SMPS_BASE                                        0x120
263 #define PALMAS_LDO_BASE                                         0x150
264 #define PALMAS_DVFS_BASE                                        0x180
265 #define PALMAS_PMU_CONTROL_BASE                                 0x1A0
266 #define PALMAS_RESOURCE_BASE                                    0x1D4
267 #define PALMAS_PU_PD_OD_BASE                                    0x1F4
268 #define PALMAS_LED_BASE                                         0x200
269 #define PALMAS_INTERRUPT_BASE                                   0x210
270 #define PALMAS_USB_OTG_BASE                                     0x250
271 #define PALMAS_VIBRATOR_BASE                                    0x270
272 #define PALMAS_GPIO_BASE                                        0x280
273 #define PALMAS_USB_BASE                                         0x290
274 #define PALMAS_GPADC_BASE                                       0x2C0
275 #define PALMAS_TRIM_GPADC_BASE                                  0x3CD
276
277 /* Registers for function RTC */
278 #define PALMAS_SECONDS_REG                                      0x0
279 #define PALMAS_MINUTES_REG                                      0x1
280 #define PALMAS_HOURS_REG                                        0x2
281 #define PALMAS_DAYS_REG                                         0x3
282 #define PALMAS_MONTHS_REG                                       0x4
283 #define PALMAS_YEARS_REG                                        0x5
284 #define PALMAS_WEEKS_REG                                        0x6
285 #define PALMAS_ALARM_SECONDS_REG                                0x8
286 #define PALMAS_ALARM_MINUTES_REG                                0x9
287 #define PALMAS_ALARM_HOURS_REG                                  0xA
288 #define PALMAS_ALARM_DAYS_REG                                   0xB
289 #define PALMAS_ALARM_MONTHS_REG                                 0xC
290 #define PALMAS_ALARM_YEARS_REG                                  0xD
291 #define PALMAS_RTC_CTRL_REG                                     0x10
292 #define PALMAS_RTC_STATUS_REG                                   0x11
293 #define PALMAS_RTC_INTERRUPTS_REG                               0x12
294 #define PALMAS_RTC_COMP_LSB_REG                                 0x13
295 #define PALMAS_RTC_COMP_MSB_REG                                 0x14
296 #define PALMAS_RTC_RES_PROG_REG                                 0x15
297 #define PALMAS_RTC_RESET_STATUS_REG                             0x16
298
299 /* Bit definitions for SECONDS_REG */
300 #define PALMAS_SECONDS_REG_SEC1_MASK                            0x70
301 #define PALMAS_SECONDS_REG_SEC1_SHIFT                           4
302 #define PALMAS_SECONDS_REG_SEC0_MASK                            0x0f
303 #define PALMAS_SECONDS_REG_SEC0_SHIFT                           0
304
305 /* Bit definitions for MINUTES_REG */
306 #define PALMAS_MINUTES_REG_MIN1_MASK                            0x70
307 #define PALMAS_MINUTES_REG_MIN1_SHIFT                           4
308 #define PALMAS_MINUTES_REG_MIN0_MASK                            0x0f
309 #define PALMAS_MINUTES_REG_MIN0_SHIFT                           0
310
311 /* Bit definitions for HOURS_REG */
312 #define PALMAS_HOURS_REG_PM_NAM                                 0x80
313 #define PALMAS_HOURS_REG_PM_NAM_SHIFT                           7
314 #define PALMAS_HOURS_REG_HOUR1_MASK                             0x30
315 #define PALMAS_HOURS_REG_HOUR1_SHIFT                            4
316 #define PALMAS_HOURS_REG_HOUR0_MASK                             0x0f
317 #define PALMAS_HOURS_REG_HOUR0_SHIFT                            0
318
319 /* Bit definitions for DAYS_REG */
320 #define PALMAS_DAYS_REG_DAY1_MASK                               0x30
321 #define PALMAS_DAYS_REG_DAY1_SHIFT                              4
322 #define PALMAS_DAYS_REG_DAY0_MASK                               0x0f
323 #define PALMAS_DAYS_REG_DAY0_SHIFT                              0
324
325 /* Bit definitions for MONTHS_REG */
326 #define PALMAS_MONTHS_REG_MONTH1                                0x10
327 #define PALMAS_MONTHS_REG_MONTH1_SHIFT                          4
328 #define PALMAS_MONTHS_REG_MONTH0_MASK                           0x0f
329 #define PALMAS_MONTHS_REG_MONTH0_SHIFT                          0
330
331 /* Bit definitions for YEARS_REG */
332 #define PALMAS_YEARS_REG_YEAR1_MASK                             0xf0
333 #define PALMAS_YEARS_REG_YEAR1_SHIFT                            4
334 #define PALMAS_YEARS_REG_YEAR0_MASK                             0x0f
335 #define PALMAS_YEARS_REG_YEAR0_SHIFT                            0
336
337 /* Bit definitions for WEEKS_REG */
338 #define PALMAS_WEEKS_REG_WEEK_MASK                              0x07
339 #define PALMAS_WEEKS_REG_WEEK_SHIFT                             0
340
341 /* Bit definitions for ALARM_SECONDS_REG */
342 #define PALMAS_ALARM_SECONDS_REG_ALARM_SEC1_MASK                0x70
343 #define PALMAS_ALARM_SECONDS_REG_ALARM_SEC1_SHIFT               4
344 #define PALMAS_ALARM_SECONDS_REG_ALARM_SEC0_MASK                0x0f
345 #define PALMAS_ALARM_SECONDS_REG_ALARM_SEC0_SHIFT               0
346
347 /* Bit definitions for ALARM_MINUTES_REG */
348 #define PALMAS_ALARM_MINUTES_REG_ALARM_MIN1_MASK                0x70
349 #define PALMAS_ALARM_MINUTES_REG_ALARM_MIN1_SHIFT               4
350 #define PALMAS_ALARM_MINUTES_REG_ALARM_MIN0_MASK                0x0f
351 #define PALMAS_ALARM_MINUTES_REG_ALARM_MIN0_SHIFT               0
352
353 /* Bit definitions for ALARM_HOURS_REG */
354 #define PALMAS_ALARM_HOURS_REG_ALARM_PM_NAM                     0x80
355 #define PALMAS_ALARM_HOURS_REG_ALARM_PM_NAM_SHIFT               7
356 #define PALMAS_ALARM_HOURS_REG_ALARM_HOUR1_MASK                 0x30
357 #define PALMAS_ALARM_HOURS_REG_ALARM_HOUR1_SHIFT                4
358 #define PALMAS_ALARM_HOURS_REG_ALARM_HOUR0_MASK                 0x0f
359 #define PALMAS_ALARM_HOURS_REG_ALARM_HOUR0_SHIFT                0
360
361 /* Bit definitions for ALARM_DAYS_REG */
362 #define PALMAS_ALARM_DAYS_REG_ALARM_DAY1_MASK                   0x30
363 #define PALMAS_ALARM_DAYS_REG_ALARM_DAY1_SHIFT                  4
364 #define PALMAS_ALARM_DAYS_REG_ALARM_DAY0_MASK                   0x0f
365 #define PALMAS_ALARM_DAYS_REG_ALARM_DAY0_SHIFT                  0
366
367 /* Bit definitions for ALARM_MONTHS_REG */
368 #define PALMAS_ALARM_MONTHS_REG_ALARM_MONTH1                    0x10
369 #define PALMAS_ALARM_MONTHS_REG_ALARM_MONTH1_SHIFT              4
370 #define PALMAS_ALARM_MONTHS_REG_ALARM_MONTH0_MASK               0x0f
371 #define PALMAS_ALARM_MONTHS_REG_ALARM_MONTH0_SHIFT              0
372
373 /* Bit definitions for ALARM_YEARS_REG */
374 #define PALMAS_ALARM_YEARS_REG_ALARM_YEAR1_MASK                 0xf0
375 #define PALMAS_ALARM_YEARS_REG_ALARM_YEAR1_SHIFT                4
376 #define PALMAS_ALARM_YEARS_REG_ALARM_YEAR0_MASK                 0x0f
377 #define PALMAS_ALARM_YEARS_REG_ALARM_YEAR0_SHIFT                0
378
379 /* Bit definitions for RTC_CTRL_REG */
380 #define PALMAS_RTC_CTRL_REG_RTC_V_OPT                           0x80
381 #define PALMAS_RTC_CTRL_REG_RTC_V_OPT_SHIFT                     7
382 #define PALMAS_RTC_CTRL_REG_GET_TIME                            0x40
383 #define PALMAS_RTC_CTRL_REG_GET_TIME_SHIFT                      6
384 #define PALMAS_RTC_CTRL_REG_SET_32_COUNTER                      0x20
385 #define PALMAS_RTC_CTRL_REG_SET_32_COUNTER_SHIFT                5
386 #define PALMAS_RTC_CTRL_REG_TEST_MODE                           0x10
387 #define PALMAS_RTC_CTRL_REG_TEST_MODE_SHIFT                     4
388 #define PALMAS_RTC_CTRL_REG_MODE_12_24                          0x08
389 #define PALMAS_RTC_CTRL_REG_MODE_12_24_SHIFT                    3
390 #define PALMAS_RTC_CTRL_REG_AUTO_COMP                           0x04
391 #define PALMAS_RTC_CTRL_REG_AUTO_COMP_SHIFT                     2
392 #define PALMAS_RTC_CTRL_REG_ROUND_30S                           0x02
393 #define PALMAS_RTC_CTRL_REG_ROUND_30S_SHIFT                     1
394 #define PALMAS_RTC_CTRL_REG_STOP_RTC                            0x01
395 #define PALMAS_RTC_CTRL_REG_STOP_RTC_SHIFT                      0
396
397 /* Bit definitions for RTC_STATUS_REG */
398 #define PALMAS_RTC_STATUS_REG_POWER_UP                          0x80
399 #define PALMAS_RTC_STATUS_REG_POWER_UP_SHIFT                    7
400 #define PALMAS_RTC_STATUS_REG_ALARM                             0x40
401 #define PALMAS_RTC_STATUS_REG_ALARM_SHIFT                       6
402 #define PALMAS_RTC_STATUS_REG_EVENT_1D                          0x20
403 #define PALMAS_RTC_STATUS_REG_EVENT_1D_SHIFT                    5
404 #define PALMAS_RTC_STATUS_REG_EVENT_1H                          0x10
405 #define PALMAS_RTC_STATUS_REG_EVENT_1H_SHIFT                    4
406 #define PALMAS_RTC_STATUS_REG_EVENT_1M                          0x08
407 #define PALMAS_RTC_STATUS_REG_EVENT_1M_SHIFT                    3
408 #define PALMAS_RTC_STATUS_REG_EVENT_1S                          0x04
409 #define PALMAS_RTC_STATUS_REG_EVENT_1S_SHIFT                    2
410 #define PALMAS_RTC_STATUS_REG_RUN                               0x02
411 #define PALMAS_RTC_STATUS_REG_RUN_SHIFT                         1
412
413 /* Bit definitions for RTC_INTERRUPTS_REG */
414 #define PALMAS_RTC_INTERRUPTS_REG_IT_SLEEP_MASK_EN              0x10
415 #define PALMAS_RTC_INTERRUPTS_REG_IT_SLEEP_MASK_EN_SHIFT        4
416 #define PALMAS_RTC_INTERRUPTS_REG_IT_ALARM                      0x08
417 #define PALMAS_RTC_INTERRUPTS_REG_IT_ALARM_SHIFT                3
418 #define PALMAS_RTC_INTERRUPTS_REG_IT_TIMER                      0x04
419 #define PALMAS_RTC_INTERRUPTS_REG_IT_TIMER_SHIFT                2
420 #define PALMAS_RTC_INTERRUPTS_REG_EVERY_MASK                    0x03
421 #define PALMAS_RTC_INTERRUPTS_REG_EVERY_SHIFT                   0
422
423 /* Bit definitions for RTC_COMP_LSB_REG */
424 #define PALMAS_RTC_COMP_LSB_REG_RTC_COMP_LSB_MASK               0xff
425 #define PALMAS_RTC_COMP_LSB_REG_RTC_COMP_LSB_SHIFT              0
426
427 /* Bit definitions for RTC_COMP_MSB_REG */
428 #define PALMAS_RTC_COMP_MSB_REG_RTC_COMP_MSB_MASK               0xff
429 #define PALMAS_RTC_COMP_MSB_REG_RTC_COMP_MSB_SHIFT              0
430
431 /* Bit definitions for RTC_RES_PROG_REG */
432 #define PALMAS_RTC_RES_PROG_REG_SW_RES_PROG_MASK                0x3f
433 #define PALMAS_RTC_RES_PROG_REG_SW_RES_PROG_SHIFT               0
434
435 /* Bit definitions for RTC_RESET_STATUS_REG */
436 #define PALMAS_RTC_RESET_STATUS_REG_RESET_STATUS                0x01
437 #define PALMAS_RTC_RESET_STATUS_REG_RESET_STATUS_SHIFT          0
438
439 /* Registers for function BACKUP */
440 #define PALMAS_BACKUP0                                          0x0
441 #define PALMAS_BACKUP1                                          0x1
442 #define PALMAS_BACKUP2                                          0x2
443 #define PALMAS_BACKUP3                                          0x3
444 #define PALMAS_BACKUP4                                          0x4
445 #define PALMAS_BACKUP5                                          0x5
446 #define PALMAS_BACKUP6                                          0x6
447 #define PALMAS_BACKUP7                                          0x7
448
449 /* Bit definitions for BACKUP0 */
450 #define PALMAS_BACKUP0_BACKUP_MASK                              0xff
451 #define PALMAS_BACKUP0_BACKUP_SHIFT                             0
452
453 /* Bit definitions for BACKUP1 */
454 #define PALMAS_BACKUP1_BACKUP_MASK                              0xff
455 #define PALMAS_BACKUP1_BACKUP_SHIFT                             0
456
457 /* Bit definitions for BACKUP2 */
458 #define PALMAS_BACKUP2_BACKUP_MASK                              0xff
459 #define PALMAS_BACKUP2_BACKUP_SHIFT                             0
460
461 /* Bit definitions for BACKUP3 */
462 #define PALMAS_BACKUP3_BACKUP_MASK                              0xff
463 #define PALMAS_BACKUP3_BACKUP_SHIFT                             0
464
465 /* Bit definitions for BACKUP4 */
466 #define PALMAS_BACKUP4_BACKUP_MASK                              0xff
467 #define PALMAS_BACKUP4_BACKUP_SHIFT                             0
468
469 /* Bit definitions for BACKUP5 */
470 #define PALMAS_BACKUP5_BACKUP_MASK                              0xff
471 #define PALMAS_BACKUP5_BACKUP_SHIFT                             0
472
473 /* Bit definitions for BACKUP6 */
474 #define PALMAS_BACKUP6_BACKUP_MASK                              0xff
475 #define PALMAS_BACKUP6_BACKUP_SHIFT                             0
476
477 /* Bit definitions for BACKUP7 */
478 #define PALMAS_BACKUP7_BACKUP_MASK                              0xff
479 #define PALMAS_BACKUP7_BACKUP_SHIFT                             0
480
481 /* Registers for function SMPS */
482 #define PALMAS_SMPS12_CTRL                                      0x0
483 #define PALMAS_SMPS12_TSTEP                                     0x1
484 #define PALMAS_SMPS12_FORCE                                     0x2
485 #define PALMAS_SMPS12_VOLTAGE                                   0x3
486 #define PALMAS_SMPS3_CTRL                                       0x4
487 #define PALMAS_SMPS3_VOLTAGE                                    0x7
488 #define PALMAS_SMPS45_CTRL                                      0x8
489 #define PALMAS_SMPS45_TSTEP                                     0x9
490 #define PALMAS_SMPS45_FORCE                                     0xA
491 #define PALMAS_SMPS45_VOLTAGE                                   0xB
492 #define PALMAS_SMPS6_CTRL                                       0xC
493 #define PALMAS_SMPS6_TSTEP                                      0xD
494 #define PALMAS_SMPS6_FORCE                                      0xE
495 #define PALMAS_SMPS6_VOLTAGE                                    0xF
496 #define PALMAS_SMPS7_CTRL                                       0x10
497 #define PALMAS_SMPS7_VOLTAGE                                    0x13
498 #define PALMAS_SMPS8_CTRL                                       0x14
499 #define PALMAS_SMPS8_TSTEP                                      0x15
500 #define PALMAS_SMPS8_FORCE                                      0x16
501 #define PALMAS_SMPS8_VOLTAGE                                    0x17
502 #define PALMAS_SMPS9_CTRL                                       0x18
503 #define PALMAS_SMPS9_VOLTAGE                                    0x1B
504 #define PALMAS_SMPS10_CTRL                                      0x1C
505 #define PALMAS_SMPS10_STATUS                                    0x1F
506 #define PALMAS_SMPS_CTRL                                        0x24
507 #define PALMAS_SMPS_PD_CTRL                                     0x25
508 #define PALMAS_SMPS_DITHER_EN                                   0x26
509 #define PALMAS_SMPS_THERMAL_EN                                  0x27
510 #define PALMAS_SMPS_THERMAL_STATUS                              0x28
511 #define PALMAS_SMPS_SHORT_STATUS                                0x29
512 #define PALMAS_SMPS_NEGATIVE_CURRENT_LIMIT_EN                   0x2A
513 #define PALMAS_SMPS_POWERGOOD_MASK1                             0x2B
514 #define PALMAS_SMPS_POWERGOOD_MASK2                             0x2C
515
516 /* Bit definitions for SMPS12_CTRL */
517 #define PALMAS_SMPS12_CTRL_WR_S                                 0x80
518 #define PALMAS_SMPS12_CTRL_WR_S_SHIFT                           7
519 #define PALMAS_SMPS12_CTRL_ROOF_FLOOR_EN                        0x40
520 #define PALMAS_SMPS12_CTRL_ROOF_FLOOR_EN_SHIFT                  6
521 #define PALMAS_SMPS12_CTRL_STATUS_MASK                          0x30
522 #define PALMAS_SMPS12_CTRL_STATUS_SHIFT                         4
523 #define PALMAS_SMPS12_CTRL_MODE_SLEEP_MASK                      0x0c
524 #define PALMAS_SMPS12_CTRL_MODE_SLEEP_SHIFT                     2
525 #define PALMAS_SMPS12_CTRL_MODE_ACTIVE_MASK                     0x03
526 #define PALMAS_SMPS12_CTRL_MODE_ACTIVE_SHIFT                    0
527
528 /* Bit definitions for SMPS12_TSTEP */
529 #define PALMAS_SMPS12_TSTEP_TSTEP_MASK                          0x03
530 #define PALMAS_SMPS12_TSTEP_TSTEP_SHIFT                         0
531
532 /* Bit definitions for SMPS12_FORCE */
533 #define PALMAS_SMPS12_FORCE_CMD                                 0x80
534 #define PALMAS_SMPS12_FORCE_CMD_SHIFT                           7
535 #define PALMAS_SMPS12_FORCE_VSEL_MASK                           0x7f
536 #define PALMAS_SMPS12_FORCE_VSEL_SHIFT                          0
537
538 /* Bit definitions for SMPS12_VOLTAGE */
539 #define PALMAS_SMPS12_VOLTAGE_RANGE                             0x80
540 #define PALMAS_SMPS12_VOLTAGE_RANGE_SHIFT                       7
541 #define PALMAS_SMPS12_VOLTAGE_VSEL_MASK                         0x7f
542 #define PALMAS_SMPS12_VOLTAGE_VSEL_SHIFT                        0
543
544 /* Bit definitions for SMPS3_CTRL */
545 #define PALMAS_SMPS3_CTRL_WR_S                                  0x80
546 #define PALMAS_SMPS3_CTRL_WR_S_SHIFT                            7
547 #define PALMAS_SMPS3_CTRL_STATUS_MASK                           0x30
548 #define PALMAS_SMPS3_CTRL_STATUS_SHIFT                          4
549 #define PALMAS_SMPS3_CTRL_MODE_SLEEP_MASK                       0x0c
550 #define PALMAS_SMPS3_CTRL_MODE_SLEEP_SHIFT                      2
551 #define PALMAS_SMPS3_CTRL_MODE_ACTIVE_MASK                      0x03
552 #define PALMAS_SMPS3_CTRL_MODE_ACTIVE_SHIFT                     0
553
554 /* Bit definitions for SMPS3_VOLTAGE */
555 #define PALMAS_SMPS3_VOLTAGE_RANGE                              0x80
556 #define PALMAS_SMPS3_VOLTAGE_RANGE_SHIFT                        7
557 #define PALMAS_SMPS3_VOLTAGE_VSEL_MASK                          0x7f
558 #define PALMAS_SMPS3_VOLTAGE_VSEL_SHIFT                         0
559
560 /* Bit definitions for SMPS45_CTRL */
561 #define PALMAS_SMPS45_CTRL_WR_S                                 0x80
562 #define PALMAS_SMPS45_CTRL_WR_S_SHIFT                           7
563 #define PALMAS_SMPS45_CTRL_ROOF_FLOOR_EN                        0x40
564 #define PALMAS_SMPS45_CTRL_ROOF_FLOOR_EN_SHIFT                  6
565 #define PALMAS_SMPS45_CTRL_STATUS_MASK                          0x30
566 #define PALMAS_SMPS45_CTRL_STATUS_SHIFT                         4
567 #define PALMAS_SMPS45_CTRL_MODE_SLEEP_MASK                      0x0c
568 #define PALMAS_SMPS45_CTRL_MODE_SLEEP_SHIFT                     2
569 #define PALMAS_SMPS45_CTRL_MODE_ACTIVE_MASK                     0x03
570 #define PALMAS_SMPS45_CTRL_MODE_ACTIVE_SHIFT                    0
571
572 /* Bit definitions for SMPS45_TSTEP */
573 #define PALMAS_SMPS45_TSTEP_TSTEP_MASK                          0x03
574 #define PALMAS_SMPS45_TSTEP_TSTEP_SHIFT                         0
575
576 /* Bit definitions for SMPS45_FORCE */
577 #define PALMAS_SMPS45_FORCE_CMD                                 0x80
578 #define PALMAS_SMPS45_FORCE_CMD_SHIFT                           7
579 #define PALMAS_SMPS45_FORCE_VSEL_MASK                           0x7f
580 #define PALMAS_SMPS45_FORCE_VSEL_SHIFT                          0
581
582 /* Bit definitions for SMPS45_VOLTAGE */
583 #define PALMAS_SMPS45_VOLTAGE_RANGE                             0x80
584 #define PALMAS_SMPS45_VOLTAGE_RANGE_SHIFT                       7
585 #define PALMAS_SMPS45_VOLTAGE_VSEL_MASK                         0x7f
586 #define PALMAS_SMPS45_VOLTAGE_VSEL_SHIFT                        0
587
588 /* Bit definitions for SMPS6_CTRL */
589 #define PALMAS_SMPS6_CTRL_WR_S                                  0x80
590 #define PALMAS_SMPS6_CTRL_WR_S_SHIFT                            7
591 #define PALMAS_SMPS6_CTRL_ROOF_FLOOR_EN                         0x40
592 #define PALMAS_SMPS6_CTRL_ROOF_FLOOR_EN_SHIFT                   6
593 #define PALMAS_SMPS6_CTRL_STATUS_MASK                           0x30
594 #define PALMAS_SMPS6_CTRL_STATUS_SHIFT                          4
595 #define PALMAS_SMPS6_CTRL_MODE_SLEEP_MASK                       0x0c
596 #define PALMAS_SMPS6_CTRL_MODE_SLEEP_SHIFT                      2
597 #define PALMAS_SMPS6_CTRL_MODE_ACTIVE_MASK                      0x03
598 #define PALMAS_SMPS6_CTRL_MODE_ACTIVE_SHIFT                     0
599
600 /* Bit definitions for SMPS6_TSTEP */
601 #define PALMAS_SMPS6_TSTEP_TSTEP_MASK                           0x03
602 #define PALMAS_SMPS6_TSTEP_TSTEP_SHIFT                          0
603
604 /* Bit definitions for SMPS6_FORCE */
605 #define PALMAS_SMPS6_FORCE_CMD                                  0x80
606 #define PALMAS_SMPS6_FORCE_CMD_SHIFT                            7
607 #define PALMAS_SMPS6_FORCE_VSEL_MASK                            0x7f
608 #define PALMAS_SMPS6_FORCE_VSEL_SHIFT                           0
609
610 /* Bit definitions for SMPS6_VOLTAGE */
611 #define PALMAS_SMPS6_VOLTAGE_RANGE                              0x80
612 #define PALMAS_SMPS6_VOLTAGE_RANGE_SHIFT                        7
613 #define PALMAS_SMPS6_VOLTAGE_VSEL_MASK                          0x7f
614 #define PALMAS_SMPS6_VOLTAGE_VSEL_SHIFT                         0
615
616 /* Bit definitions for SMPS7_CTRL */
617 #define PALMAS_SMPS7_CTRL_WR_S                                  0x80
618 #define PALMAS_SMPS7_CTRL_WR_S_SHIFT                            7
619 #define PALMAS_SMPS7_CTRL_STATUS_MASK                           0x30
620 #define PALMAS_SMPS7_CTRL_STATUS_SHIFT                          4
621 #define PALMAS_SMPS7_CTRL_MODE_SLEEP_MASK                       0x0c
622 #define PALMAS_SMPS7_CTRL_MODE_SLEEP_SHIFT                      2
623 #define PALMAS_SMPS7_CTRL_MODE_ACTIVE_MASK                      0x03
624 #define PALMAS_SMPS7_CTRL_MODE_ACTIVE_SHIFT                     0
625
626 /* Bit definitions for SMPS7_VOLTAGE */
627 #define PALMAS_SMPS7_VOLTAGE_RANGE                              0x80
628 #define PALMAS_SMPS7_VOLTAGE_RANGE_SHIFT                        7
629 #define PALMAS_SMPS7_VOLTAGE_VSEL_MASK                          0x7f
630 #define PALMAS_SMPS7_VOLTAGE_VSEL_SHIFT                         0
631
632 /* Bit definitions for SMPS8_CTRL */
633 #define PALMAS_SMPS8_CTRL_WR_S                                  0x80
634 #define PALMAS_SMPS8_CTRL_WR_S_SHIFT                            7
635 #define PALMAS_SMPS8_CTRL_ROOF_FLOOR_EN                         0x40
636 #define PALMAS_SMPS8_CTRL_ROOF_FLOOR_EN_SHIFT                   6
637 #define PALMAS_SMPS8_CTRL_STATUS_MASK                           0x30
638 #define PALMAS_SMPS8_CTRL_STATUS_SHIFT                          4
639 #define PALMAS_SMPS8_CTRL_MODE_SLEEP_MASK                       0x0c
640 #define PALMAS_SMPS8_CTRL_MODE_SLEEP_SHIFT                      2
641 #define PALMAS_SMPS8_CTRL_MODE_ACTIVE_MASK                      0x03
642 #define PALMAS_SMPS8_CTRL_MODE_ACTIVE_SHIFT                     0
643
644 /* Bit definitions for SMPS8_TSTEP */
645 #define PALMAS_SMPS8_TSTEP_TSTEP_MASK                           0x03
646 #define PALMAS_SMPS8_TSTEP_TSTEP_SHIFT                          0
647
648 /* Bit definitions for SMPS8_FORCE */
649 #define PALMAS_SMPS8_FORCE_CMD                                  0x80
650 #define PALMAS_SMPS8_FORCE_CMD_SHIFT                            7
651 #define PALMAS_SMPS8_FORCE_VSEL_MASK                            0x7f
652 #define PALMAS_SMPS8_FORCE_VSEL_SHIFT                           0
653
654 /* Bit definitions for SMPS8_VOLTAGE */
655 #define PALMAS_SMPS8_VOLTAGE_RANGE                              0x80
656 #define PALMAS_SMPS8_VOLTAGE_RANGE_SHIFT                        7
657 #define PALMAS_SMPS8_VOLTAGE_VSEL_MASK                          0x7f
658 #define PALMAS_SMPS8_VOLTAGE_VSEL_SHIFT                         0
659
660 /* Bit definitions for SMPS9_CTRL */
661 #define PALMAS_SMPS9_CTRL_WR_S                                  0x80
662 #define PALMAS_SMPS9_CTRL_WR_S_SHIFT                            7
663 #define PALMAS_SMPS9_CTRL_STATUS_MASK                           0x30
664 #define PALMAS_SMPS9_CTRL_STATUS_SHIFT                          4
665 #define PALMAS_SMPS9_CTRL_MODE_SLEEP_MASK                       0x0c
666 #define PALMAS_SMPS9_CTRL_MODE_SLEEP_SHIFT                      2
667 #define PALMAS_SMPS9_CTRL_MODE_ACTIVE_MASK                      0x03
668 #define PALMAS_SMPS9_CTRL_MODE_ACTIVE_SHIFT                     0
669
670 /* Bit definitions for SMPS9_VOLTAGE */
671 #define PALMAS_SMPS9_VOLTAGE_RANGE                              0x80
672 #define PALMAS_SMPS9_VOLTAGE_RANGE_SHIFT                        7
673 #define PALMAS_SMPS9_VOLTAGE_VSEL_MASK                          0x7f
674 #define PALMAS_SMPS9_VOLTAGE_VSEL_SHIFT                         0
675
676 /* Bit definitions for SMPS10_CTRL */
677 #define PALMAS_SMPS10_CTRL_MODE_SLEEP_MASK                      0xf0
678 #define PALMAS_SMPS10_CTRL_MODE_SLEEP_SHIFT                     4
679 #define PALMAS_SMPS10_CTRL_MODE_ACTIVE_MASK                     0x0f
680 #define PALMAS_SMPS10_CTRL_MODE_ACTIVE_SHIFT                    0
681
682 /* Bit definitions for SMPS10_STATUS */
683 #define PALMAS_SMPS10_STATUS_STATUS_MASK                        0x0f
684 #define PALMAS_SMPS10_STATUS_STATUS_SHIFT                       0
685
686 /* Bit definitions for SMPS_CTRL */
687 #define PALMAS_SMPS_CTRL_SMPS45_SMPS457_EN                      0x20
688 #define PALMAS_SMPS_CTRL_SMPS45_SMPS457_EN_SHIFT                5
689 #define PALMAS_SMPS_CTRL_SMPS12_SMPS123_EN                      0x10
690 #define PALMAS_SMPS_CTRL_SMPS12_SMPS123_EN_SHIFT                4
691 #define PALMAS_SMPS_CTRL_SMPS45_PHASE_CTRL_MASK                 0x0c
692 #define PALMAS_SMPS_CTRL_SMPS45_PHASE_CTRL_SHIFT                2
693 #define PALMAS_SMPS_CTRL_SMPS123_PHASE_CTRL_MASK                0x03
694 #define PALMAS_SMPS_CTRL_SMPS123_PHASE_CTRL_SHIFT               0
695
696 /* Bit definitions for SMPS_PD_CTRL */
697 #define PALMAS_SMPS_PD_CTRL_SMPS9                               0x40
698 #define PALMAS_SMPS_PD_CTRL_SMPS9_SHIFT                         6
699 #define PALMAS_SMPS_PD_CTRL_SMPS8                               0x20
700 #define PALMAS_SMPS_PD_CTRL_SMPS8_SHIFT                         5
701 #define PALMAS_SMPS_PD_CTRL_SMPS7                               0x10
702 #define PALMAS_SMPS_PD_CTRL_SMPS7_SHIFT                         4
703 #define PALMAS_SMPS_PD_CTRL_SMPS6                               0x08
704 #define PALMAS_SMPS_PD_CTRL_SMPS6_SHIFT                         3
705 #define PALMAS_SMPS_PD_CTRL_SMPS45                              0x04
706 #define PALMAS_SMPS_PD_CTRL_SMPS45_SHIFT                        2
707 #define PALMAS_SMPS_PD_CTRL_SMPS3                               0x02
708 #define PALMAS_SMPS_PD_CTRL_SMPS3_SHIFT                         1
709 #define PALMAS_SMPS_PD_CTRL_SMPS12                              0x01
710 #define PALMAS_SMPS_PD_CTRL_SMPS12_SHIFT                        0
711
712 /* Bit definitions for SMPS_THERMAL_EN */
713 #define PALMAS_SMPS_THERMAL_EN_SMPS9                            0x40
714 #define PALMAS_SMPS_THERMAL_EN_SMPS9_SHIFT                      6
715 #define PALMAS_SMPS_THERMAL_EN_SMPS8                            0x20
716 #define PALMAS_SMPS_THERMAL_EN_SMPS8_SHIFT                      5
717 #define PALMAS_SMPS_THERMAL_EN_SMPS6                            0x08
718 #define PALMAS_SMPS_THERMAL_EN_SMPS6_SHIFT                      3
719 #define PALMAS_SMPS_THERMAL_EN_SMPS457                          0x04
720 #define PALMAS_SMPS_THERMAL_EN_SMPS457_SHIFT                    2
721 #define PALMAS_SMPS_THERMAL_EN_SMPS123                          0x01
722 #define PALMAS_SMPS_THERMAL_EN_SMPS123_SHIFT                    0
723
724 /* Bit definitions for SMPS_THERMAL_STATUS */
725 #define PALMAS_SMPS_THERMAL_STATUS_SMPS9                        0x40
726 #define PALMAS_SMPS_THERMAL_STATUS_SMPS9_SHIFT                  6
727 #define PALMAS_SMPS_THERMAL_STATUS_SMPS8                        0x20
728 #define PALMAS_SMPS_THERMAL_STATUS_SMPS8_SHIFT                  5
729 #define PALMAS_SMPS_THERMAL_STATUS_SMPS6                        0x08
730 #define PALMAS_SMPS_THERMAL_STATUS_SMPS6_SHIFT                  3
731 #define PALMAS_SMPS_THERMAL_STATUS_SMPS457                      0x04
732 #define PALMAS_SMPS_THERMAL_STATUS_SMPS457_SHIFT                2
733 #define PALMAS_SMPS_THERMAL_STATUS_SMPS123                      0x01
734 #define PALMAS_SMPS_THERMAL_STATUS_SMPS123_SHIFT                0
735
736 /* Bit definitions for SMPS_SHORT_STATUS */
737 #define PALMAS_SMPS_SHORT_STATUS_SMPS10                         0x80
738 #define PALMAS_SMPS_SHORT_STATUS_SMPS10_SHIFT                   7
739 #define PALMAS_SMPS_SHORT_STATUS_SMPS9                          0x40
740 #define PALMAS_SMPS_SHORT_STATUS_SMPS9_SHIFT                    6
741 #define PALMAS_SMPS_SHORT_STATUS_SMPS8                          0x20
742 #define PALMAS_SMPS_SHORT_STATUS_SMPS8_SHIFT                    5
743 #define PALMAS_SMPS_SHORT_STATUS_SMPS7                          0x10
744 #define PALMAS_SMPS_SHORT_STATUS_SMPS7_SHIFT                    4
745 #define PALMAS_SMPS_SHORT_STATUS_SMPS6                          0x08
746 #define PALMAS_SMPS_SHORT_STATUS_SMPS6_SHIFT                    3
747 #define PALMAS_SMPS_SHORT_STATUS_SMPS45                         0x04
748 #define PALMAS_SMPS_SHORT_STATUS_SMPS45_SHIFT                   2
749 #define PALMAS_SMPS_SHORT_STATUS_SMPS3                          0x02
750 #define PALMAS_SMPS_SHORT_STATUS_SMPS3_SHIFT                    1
751 #define PALMAS_SMPS_SHORT_STATUS_SMPS12                         0x01
752 #define PALMAS_SMPS_SHORT_STATUS_SMPS12_SHIFT                   0
753
754 /* Bit definitions for SMPS_NEGATIVE_CURRENT_LIMIT_EN */
755 #define PALMAS_SMPS_NEGATIVE_CURRENT_LIMIT_EN_SMPS9             0x40
756 #define PALMAS_SMPS_NEGATIVE_CURRENT_LIMIT_EN_SMPS9_SHIFT       6
757 #define PALMAS_SMPS_NEGATIVE_CURRENT_LIMIT_EN_SMPS8             0x20
758 #define PALMAS_SMPS_NEGATIVE_CURRENT_LIMIT_EN_SMPS8_SHIFT       5
759 #define PALMAS_SMPS_NEGATIVE_CURRENT_LIMIT_EN_SMPS7             0x10
760 #define PALMAS_SMPS_NEGATIVE_CURRENT_LIMIT_EN_SMPS7_SHIFT       4
761 #define PALMAS_SMPS_NEGATIVE_CURRENT_LIMIT_EN_SMPS6             0x08
762 #define PALMAS_SMPS_NEGATIVE_CURRENT_LIMIT_EN_SMPS6_SHIFT       3
763 #define PALMAS_SMPS_NEGATIVE_CURRENT_LIMIT_EN_SMPS45            0x04
764 #define PALMAS_SMPS_NEGATIVE_CURRENT_LIMIT_EN_SMPS45_SHIFT      2
765 #define PALMAS_SMPS_NEGATIVE_CURRENT_LIMIT_EN_SMPS3             0x02
766 #define PALMAS_SMPS_NEGATIVE_CURRENT_LIMIT_EN_SMPS3_SHIFT       1
767 #define PALMAS_SMPS_NEGATIVE_CURRENT_LIMIT_EN_SMPS12            0x01
768 #define PALMAS_SMPS_NEGATIVE_CURRENT_LIMIT_EN_SMPS12_SHIFT      0
769
770 /* Bit definitions for SMPS_POWERGOOD_MASK1 */
771 #define PALMAS_SMPS_POWERGOOD_MASK1_SMPS10                      0x80
772 #define PALMAS_SMPS_POWERGOOD_MASK1_SMPS10_SHIFT                7
773 #define PALMAS_SMPS_POWERGOOD_MASK1_SMPS9                       0x40
774 #define PALMAS_SMPS_POWERGOOD_MASK1_SMPS9_SHIFT                 6
775 #define PALMAS_SMPS_POWERGOOD_MASK1_SMPS8                       0x20
776 #define PALMAS_SMPS_POWERGOOD_MASK1_SMPS8_SHIFT                 5
777 #define PALMAS_SMPS_POWERGOOD_MASK1_SMPS7                       0x10
778 #define PALMAS_SMPS_POWERGOOD_MASK1_SMPS7_SHIFT                 4
779 #define PALMAS_SMPS_POWERGOOD_MASK1_SMPS6                       0x08
780 #define PALMAS_SMPS_POWERGOOD_MASK1_SMPS6_SHIFT                 3
781 #define PALMAS_SMPS_POWERGOOD_MASK1_SMPS45                      0x04
782 #define PALMAS_SMPS_POWERGOOD_MASK1_SMPS45_SHIFT                2
783 #define PALMAS_SMPS_POWERGOOD_MASK1_SMPS3                       0x02
784 #define PALMAS_SMPS_POWERGOOD_MASK1_SMPS3_SHIFT                 1
785 #define PALMAS_SMPS_POWERGOOD_MASK1_SMPS12                      0x01
786 #define PALMAS_SMPS_POWERGOOD_MASK1_SMPS12_SHIFT                0
787
788 /* Bit definitions for SMPS_POWERGOOD_MASK2 */
789 #define PALMAS_SMPS_POWERGOOD_MASK2_POWERGOOD_TYPE_SELECT       0x80
790 #define PALMAS_SMPS_POWERGOOD_MASK2_POWERGOOD_TYPE_SELECT_SHIFT 7
791 #define PALMAS_SMPS_POWERGOOD_MASK2_GPIO_7                      0x04
792 #define PALMAS_SMPS_POWERGOOD_MASK2_GPIO_7_SHIFT                2
793 #define PALMAS_SMPS_POWERGOOD_MASK2_VBUS                        0x02
794 #define PALMAS_SMPS_POWERGOOD_MASK2_VBUS_SHIFT                  1
795 #define PALMAS_SMPS_POWERGOOD_MASK2_ACOK                        0x01
796 #define PALMAS_SMPS_POWERGOOD_MASK2_ACOK_SHIFT                  0
797
798 /* Registers for function LDO */
799 #define PALMAS_LDO1_CTRL                                        0x0
800 #define PALMAS_LDO1_VOLTAGE                                     0x1
801 #define PALMAS_LDO2_CTRL                                        0x2
802 #define PALMAS_LDO2_VOLTAGE                                     0x3
803 #define PALMAS_LDO3_CTRL                                        0x4
804 #define PALMAS_LDO3_VOLTAGE                                     0x5
805 #define PALMAS_LDO4_CTRL                                        0x6
806 #define PALMAS_LDO4_VOLTAGE                                     0x7
807 #define PALMAS_LDO5_CTRL                                        0x8
808 #define PALMAS_LDO5_VOLTAGE                                     0x9
809 #define PALMAS_LDO6_CTRL                                        0xA
810 #define PALMAS_LDO6_VOLTAGE                                     0xB
811 #define PALMAS_LDO7_CTRL                                        0xC
812 #define PALMAS_LDO7_VOLTAGE                                     0xD
813 #define PALMAS_LDO8_CTRL                                        0xE
814 #define PALMAS_LDO8_VOLTAGE                                     0xF
815 #define PALMAS_LDO9_CTRL                                        0x10
816 #define PALMAS_LDO9_VOLTAGE                                     0x11
817 #define PALMAS_LDOLN_CTRL                                       0x12
818 #define PALMAS_LDOLN_VOLTAGE                                    0x13
819 #define PALMAS_LDOUSB_CTRL                                      0x14
820 #define PALMAS_LDOUSB_VOLTAGE                                   0x15
821 #define PALMAS_LDO_CTRL                                         0x1A
822 #define PALMAS_LDO_PD_CTRL1                                     0x1B
823 #define PALMAS_LDO_PD_CTRL2                                     0x1C
824 #define PALMAS_LDO_SHORT_STATUS1                                0x1D
825 #define PALMAS_LDO_SHORT_STATUS2                                0x1E
826
827 /* Bit definitions for LDO1_CTRL */
828 #define PALMAS_LDO1_CTRL_WR_S                                   0x80
829 #define PALMAS_LDO1_CTRL_WR_S_SHIFT                             7
830 #define PALMAS_LDO1_CTRL_STATUS                                 0x10
831 #define PALMAS_LDO1_CTRL_STATUS_SHIFT                           4
832 #define PALMAS_LDO1_CTRL_MODE_SLEEP                             0x04
833 #define PALMAS_LDO1_CTRL_MODE_SLEEP_SHIFT                       2
834 #define PALMAS_LDO1_CTRL_MODE_ACTIVE                            0x01
835 #define PALMAS_LDO1_CTRL_MODE_ACTIVE_SHIFT                      0
836
837 /* Bit definitions for LDO1_VOLTAGE */
838 #define PALMAS_LDO1_VOLTAGE_VSEL_MASK                           0x3f
839 #define PALMAS_LDO1_VOLTAGE_VSEL_SHIFT                          0
840
841 /* Bit definitions for LDO2_CTRL */
842 #define PALMAS_LDO2_CTRL_WR_S                                   0x80
843 #define PALMAS_LDO2_CTRL_WR_S_SHIFT                             7
844 #define PALMAS_LDO2_CTRL_STATUS                                 0x10
845 #define PALMAS_LDO2_CTRL_STATUS_SHIFT                           4
846 #define PALMAS_LDO2_CTRL_MODE_SLEEP                             0x04
847 #define PALMAS_LDO2_CTRL_MODE_SLEEP_SHIFT                       2
848 #define PALMAS_LDO2_CTRL_MODE_ACTIVE                            0x01
849 #define PALMAS_LDO2_CTRL_MODE_ACTIVE_SHIFT                      0
850
851 /* Bit definitions for LDO2_VOLTAGE */
852 #define PALMAS_LDO2_VOLTAGE_VSEL_MASK                           0x3f
853 #define PALMAS_LDO2_VOLTAGE_VSEL_SHIFT                          0
854
855 /* Bit definitions for LDO3_CTRL */
856 #define PALMAS_LDO3_CTRL_WR_S                                   0x80
857 #define PALMAS_LDO3_CTRL_WR_S_SHIFT                             7
858 #define PALMAS_LDO3_CTRL_STATUS                                 0x10
859 #define PALMAS_LDO3_CTRL_STATUS_SHIFT                           4
860 #define PALMAS_LDO3_CTRL_MODE_SLEEP                             0x04
861 #define PALMAS_LDO3_CTRL_MODE_SLEEP_SHIFT                       2
862 #define PALMAS_LDO3_CTRL_MODE_ACTIVE                            0x01
863 #define PALMAS_LDO3_CTRL_MODE_ACTIVE_SHIFT                      0
864
865 /* Bit definitions for LDO3_VOLTAGE */
866 #define PALMAS_LDO3_VOLTAGE_VSEL_MASK                           0x3f
867 #define PALMAS_LDO3_VOLTAGE_VSEL_SHIFT                          0
868
869 /* Bit definitions for LDO4_CTRL */
870 #define PALMAS_LDO4_CTRL_WR_S                                   0x80
871 #define PALMAS_LDO4_CTRL_WR_S_SHIFT                             7
872 #define PALMAS_LDO4_CTRL_STATUS                                 0x10
873 #define PALMAS_LDO4_CTRL_STATUS_SHIFT                           4
874 #define PALMAS_LDO4_CTRL_MODE_SLEEP                             0x04
875 #define PALMAS_LDO4_CTRL_MODE_SLEEP_SHIFT                       2
876 #define PALMAS_LDO4_CTRL_MODE_ACTIVE                            0x01
877 #define PALMAS_LDO4_CTRL_MODE_ACTIVE_SHIFT                      0
878
879 /* Bit definitions for LDO4_VOLTAGE */
880 #define PALMAS_LDO4_VOLTAGE_VSEL_MASK                           0x3f
881 #define PALMAS_LDO4_VOLTAGE_VSEL_SHIFT                          0
882
883 /* Bit definitions for LDO5_CTRL */
884 #define PALMAS_LDO5_CTRL_WR_S                                   0x80
885 #define PALMAS_LDO5_CTRL_WR_S_SHIFT                             7
886 #define PALMAS_LDO5_CTRL_STATUS                                 0x10
887 #define PALMAS_LDO5_CTRL_STATUS_SHIFT                           4
888 #define PALMAS_LDO5_CTRL_MODE_SLEEP                             0x04
889 #define PALMAS_LDO5_CTRL_MODE_SLEEP_SHIFT                       2
890 #define PALMAS_LDO5_CTRL_MODE_ACTIVE                            0x01
891 #define PALMAS_LDO5_CTRL_MODE_ACTIVE_SHIFT                      0
892
893 /* Bit definitions for LDO5_VOLTAGE */
894 #define PALMAS_LDO5_VOLTAGE_VSEL_MASK                           0x3f
895 #define PALMAS_LDO5_VOLTAGE_VSEL_SHIFT                          0
896
897 /* Bit definitions for LDO6_CTRL */
898 #define PALMAS_LDO6_CTRL_WR_S                                   0x80
899 #define PALMAS_LDO6_CTRL_WR_S_SHIFT                             7
900 #define PALMAS_LDO6_CTRL_LDO_VIB_EN                             0x40
901 #define PALMAS_LDO6_CTRL_LDO_VIB_EN_SHIFT                       6
902 #define PALMAS_LDO6_CTRL_STATUS                                 0x10
903 #define PALMAS_LDO6_CTRL_STATUS_SHIFT                           4
904 #define PALMAS_LDO6_CTRL_MODE_SLEEP                             0x04
905 #define PALMAS_LDO6_CTRL_MODE_SLEEP_SHIFT                       2
906 #define PALMAS_LDO6_CTRL_MODE_ACTIVE                            0x01
907 #define PALMAS_LDO6_CTRL_MODE_ACTIVE_SHIFT                      0
908
909 /* Bit definitions for LDO6_VOLTAGE */
910 #define PALMAS_LDO6_VOLTAGE_VSEL_MASK                           0x3f
911 #define PALMAS_LDO6_VOLTAGE_VSEL_SHIFT                          0
912
913 /* Bit definitions for LDO7_CTRL */
914 #define PALMAS_LDO7_CTRL_WR_S                                   0x80
915 #define PALMAS_LDO7_CTRL_WR_S_SHIFT                             7
916 #define PALMAS_LDO7_CTRL_STATUS                                 0x10
917 #define PALMAS_LDO7_CTRL_STATUS_SHIFT                           4
918 #define PALMAS_LDO7_CTRL_MODE_SLEEP                             0x04
919 #define PALMAS_LDO7_CTRL_MODE_SLEEP_SHIFT                       2
920 #define PALMAS_LDO7_CTRL_MODE_ACTIVE                            0x01
921 #define PALMAS_LDO7_CTRL_MODE_ACTIVE_SHIFT                      0
922
923 /* Bit definitions for LDO7_VOLTAGE */
924 #define PALMAS_LDO7_VOLTAGE_VSEL_MASK                           0x3f
925 #define PALMAS_LDO7_VOLTAGE_VSEL_SHIFT                          0
926
927 /* Bit definitions for LDO8_CTRL */
928 #define PALMAS_LDO8_CTRL_WR_S                                   0x80
929 #define PALMAS_LDO8_CTRL_WR_S_SHIFT                             7
930 #define PALMAS_LDO8_CTRL_LDO_TRACKING_EN                        0x40
931 #define PALMAS_LDO8_CTRL_LDO_TRACKING_EN_SHIFT                  6
932 #define PALMAS_LDO8_CTRL_STATUS                                 0x10
933 #define PALMAS_LDO8_CTRL_STATUS_SHIFT                           4
934 #define PALMAS_LDO8_CTRL_MODE_SLEEP                             0x04
935 #define PALMAS_LDO8_CTRL_MODE_SLEEP_SHIFT                       2
936 #define PALMAS_LDO8_CTRL_MODE_ACTIVE                            0x01
937 #define PALMAS_LDO8_CTRL_MODE_ACTIVE_SHIFT                      0
938
939 /* Bit definitions for LDO8_VOLTAGE */
940 #define PALMAS_LDO8_VOLTAGE_VSEL_MASK                           0x3f
941 #define PALMAS_LDO8_VOLTAGE_VSEL_SHIFT                          0
942
943 /* Bit definitions for LDO9_CTRL */
944 #define PALMAS_LDO9_CTRL_WR_S                                   0x80
945 #define PALMAS_LDO9_CTRL_WR_S_SHIFT                             7
946 #define PALMAS_LDO9_CTRL_LDO_BYPASS_EN                          0x40
947 #define PALMAS_LDO9_CTRL_LDO_BYPASS_EN_SHIFT                    6
948 #define PALMAS_LDO9_CTRL_STATUS                                 0x10
949 #define PALMAS_LDO9_CTRL_STATUS_SHIFT                           4
950 #define PALMAS_LDO9_CTRL_MODE_SLEEP                             0x04
951 #define PALMAS_LDO9_CTRL_MODE_SLEEP_SHIFT                       2
952 #define PALMAS_LDO9_CTRL_MODE_ACTIVE                            0x01
953 #define PALMAS_LDO9_CTRL_MODE_ACTIVE_SHIFT                      0
954
955 /* Bit definitions for LDO9_VOLTAGE */
956 #define PALMAS_LDO9_VOLTAGE_VSEL_MASK                           0x3f
957 #define PALMAS_LDO9_VOLTAGE_VSEL_SHIFT                          0
958
959 /* Bit definitions for LDOLN_CTRL */
960 #define PALMAS_LDOLN_CTRL_WR_S                                  0x80
961 #define PALMAS_LDOLN_CTRL_WR_S_SHIFT                            7
962 #define PALMAS_LDOLN_CTRL_STATUS                                0x10
963 #define PALMAS_LDOLN_CTRL_STATUS_SHIFT                          4
964 #define PALMAS_LDOLN_CTRL_MODE_SLEEP                            0x04
965 #define PALMAS_LDOLN_CTRL_MODE_SLEEP_SHIFT                      2
966 #define PALMAS_LDOLN_CTRL_MODE_ACTIVE                           0x01
967 #define PALMAS_LDOLN_CTRL_MODE_ACTIVE_SHIFT                     0
968
969 /* Bit definitions for LDOLN_VOLTAGE */
970 #define PALMAS_LDOLN_VOLTAGE_VSEL_MASK                          0x3f
971 #define PALMAS_LDOLN_VOLTAGE_VSEL_SHIFT                         0
972
973 /* Bit definitions for LDOUSB_CTRL */
974 #define PALMAS_LDOUSB_CTRL_WR_S                                 0x80
975 #define PALMAS_LDOUSB_CTRL_WR_S_SHIFT                           7
976 #define PALMAS_LDOUSB_CTRL_STATUS                               0x10
977 #define PALMAS_LDOUSB_CTRL_STATUS_SHIFT                         4
978 #define PALMAS_LDOUSB_CTRL_MODE_SLEEP                           0x04
979 #define PALMAS_LDOUSB_CTRL_MODE_SLEEP_SHIFT                     2
980 #define PALMAS_LDOUSB_CTRL_MODE_ACTIVE                          0x01
981 #define PALMAS_LDOUSB_CTRL_MODE_ACTIVE_SHIFT                    0
982
983 /* Bit definitions for LDOUSB_VOLTAGE */
984 #define PALMAS_LDOUSB_VOLTAGE_VSEL_MASK                         0x3f
985 #define PALMAS_LDOUSB_VOLTAGE_VSEL_SHIFT                        0
986
987 /* Bit definitions for LDO_CTRL */
988 #define PALMAS_LDO_CTRL_LDOUSB_ON_VBUS_VSYS                     0x01
989 #define PALMAS_LDO_CTRL_LDOUSB_ON_VBUS_VSYS_SHIFT               0
990
991 /* Bit definitions for LDO_PD_CTRL1 */
992 #define PALMAS_LDO_PD_CTRL1_LDO8                                0x80
993 #define PALMAS_LDO_PD_CTRL1_LDO8_SHIFT                          7
994 #define PALMAS_LDO_PD_CTRL1_LDO7                                0x40
995 #define PALMAS_LDO_PD_CTRL1_LDO7_SHIFT                          6
996 #define PALMAS_LDO_PD_CTRL1_LDO6                                0x20
997 #define PALMAS_LDO_PD_CTRL1_LDO6_SHIFT                          5
998 #define PALMAS_LDO_PD_CTRL1_LDO5                                0x10
999 #define PALMAS_LDO_PD_CTRL1_LDO5_SHIFT                          4
1000 #define PALMAS_LDO_PD_CTRL1_LDO4                                0x08
1001 #define PALMAS_LDO_PD_CTRL1_LDO4_SHIFT                          3
1002 #define PALMAS_LDO_PD_CTRL1_LDO3                                0x04
1003 #define PALMAS_LDO_PD_CTRL1_LDO3_SHIFT                          2
1004 #define PALMAS_LDO_PD_CTRL1_LDO2                                0x02
1005 #define PALMAS_LDO_PD_CTRL1_LDO2_SHIFT                          1
1006 #define PALMAS_LDO_PD_CTRL1_LDO1                                0x01
1007 #define PALMAS_LDO_PD_CTRL1_LDO1_SHIFT                          0
1008
1009 /* Bit definitions for LDO_PD_CTRL2 */
1010 #define PALMAS_LDO_PD_CTRL2_LDOUSB                              0x04
1011 #define PALMAS_LDO_PD_CTRL2_LDOUSB_SHIFT                        2
1012 #define PALMAS_LDO_PD_CTRL2_LDOLN                               0x02
1013 #define PALMAS_LDO_PD_CTRL2_LDOLN_SHIFT                         1
1014 #define PALMAS_LDO_PD_CTRL2_LDO9                                0x01
1015 #define PALMAS_LDO_PD_CTRL2_LDO9_SHIFT                          0
1016
1017 /* Bit definitions for LDO_SHORT_STATUS1 */
1018 #define PALMAS_LDO_SHORT_STATUS1_LDO8                           0x80
1019 #define PALMAS_LDO_SHORT_STATUS1_LDO8_SHIFT                     7
1020 #define PALMAS_LDO_SHORT_STATUS1_LDO7                           0x40
1021 #define PALMAS_LDO_SHORT_STATUS1_LDO7_SHIFT                     6
1022 #define PALMAS_LDO_SHORT_STATUS1_LDO6                           0x20
1023 #define PALMAS_LDO_SHORT_STATUS1_LDO6_SHIFT                     5
1024 #define PALMAS_LDO_SHORT_STATUS1_LDO5                           0x10
1025 #define PALMAS_LDO_SHORT_STATUS1_LDO5_SHIFT                     4
1026 #define PALMAS_LDO_SHORT_STATUS1_LDO4                           0x08
1027 #define PALMAS_LDO_SHORT_STATUS1_LDO4_SHIFT                     3
1028 #define PALMAS_LDO_SHORT_STATUS1_LDO3                           0x04
1029 #define PALMAS_LDO_SHORT_STATUS1_LDO3_SHIFT                     2
1030 #define PALMAS_LDO_SHORT_STATUS1_LDO2                           0x02
1031 #define PALMAS_LDO_SHORT_STATUS1_LDO2_SHIFT                     1
1032 #define PALMAS_LDO_SHORT_STATUS1_LDO1                           0x01
1033 #define PALMAS_LDO_SHORT_STATUS1_LDO1_SHIFT                     0
1034
1035 /* Bit definitions for LDO_SHORT_STATUS2 */
1036 #define PALMAS_LDO_SHORT_STATUS2_LDOVANA                        0x08
1037 #define PALMAS_LDO_SHORT_STATUS2_LDOVANA_SHIFT                  3
1038 #define PALMAS_LDO_SHORT_STATUS2_LDOUSB                         0x04
1039 #define PALMAS_LDO_SHORT_STATUS2_LDOUSB_SHIFT                   2
1040 #define PALMAS_LDO_SHORT_STATUS2_LDOLN                          0x02
1041 #define PALMAS_LDO_SHORT_STATUS2_LDOLN_SHIFT                    1
1042 #define PALMAS_LDO_SHORT_STATUS2_LDO9                           0x01
1043 #define PALMAS_LDO_SHORT_STATUS2_LDO9_SHIFT                     0
1044
1045 /* Registers for function PMU_CONTROL */
1046 #define PALMAS_DEV_CTRL                                         0x0
1047 #define PALMAS_POWER_CTRL                                       0x1
1048 #define PALMAS_VSYS_LO                                          0x2
1049 #define PALMAS_VSYS_MON                                         0x3
1050 #define PALMAS_VBAT_MON                                         0x4
1051 #define PALMAS_WATCHDOG                                         0x5
1052 #define PALMAS_BOOT_STATUS                                      0x6
1053 #define PALMAS_BATTERY_BOUNCE                                   0x7
1054 #define PALMAS_BACKUP_BATTERY_CTRL                              0x8
1055 #define PALMAS_LONG_PRESS_KEY                                   0x9
1056 #define PALMAS_OSC_THERM_CTRL                                   0xA
1057 #define PALMAS_BATDEBOUNCING                                    0xB
1058 #define PALMAS_SWOFF_HWRST                                      0xF
1059 #define PALMAS_SWOFF_COLDRST                                    0x10
1060 #define PALMAS_SWOFF_STATUS                                     0x11
1061 #define PALMAS_PMU_CONFIG                                       0x12
1062 #define PALMAS_SPARE                                            0x14
1063 #define PALMAS_PMU_SECONDARY_INT                                0x15
1064 #define PALMAS_SW_REVISION                                      0x17
1065 #define PALMAS_EXT_CHRG_CTRL                                    0x18
1066 #define PALMAS_PMU_SECONDARY_INT2                               0x19
1067
1068 /* Bit definitions for DEV_CTRL */
1069 #define PALMAS_DEV_CTRL_DEV_STATUS_MASK                         0x0c
1070 #define PALMAS_DEV_CTRL_DEV_STATUS_SHIFT                        2
1071 #define PALMAS_DEV_CTRL_SW_RST                                  0x02
1072 #define PALMAS_DEV_CTRL_SW_RST_SHIFT                            1
1073 #define PALMAS_DEV_CTRL_DEV_ON                                  0x01
1074 #define PALMAS_DEV_CTRL_DEV_ON_SHIFT                            0
1075
1076 /* Bit definitions for POWER_CTRL */
1077 #define PALMAS_POWER_CTRL_ENABLE2_MASK                          0x04
1078 #define PALMAS_POWER_CTRL_ENABLE2_MASK_SHIFT                    2
1079 #define PALMAS_POWER_CTRL_ENABLE1_MASK                          0x02
1080 #define PALMAS_POWER_CTRL_ENABLE1_MASK_SHIFT                    1
1081 #define PALMAS_POWER_CTRL_NSLEEP_MASK                           0x01
1082 #define PALMAS_POWER_CTRL_NSLEEP_MASK_SHIFT                     0
1083
1084 /* Bit definitions for VSYS_LO */
1085 #define PALMAS_VSYS_LO_THRESHOLD_MASK                           0x1f
1086 #define PALMAS_VSYS_LO_THRESHOLD_SHIFT                          0
1087
1088 /* Bit definitions for VSYS_MON */
1089 #define PALMAS_VSYS_MON_ENABLE                                  0x80
1090 #define PALMAS_VSYS_MON_ENABLE_SHIFT                            7
1091 #define PALMAS_VSYS_MON_THRESHOLD_MASK                          0x3f
1092 #define PALMAS_VSYS_MON_THRESHOLD_SHIFT                         0
1093
1094 /* Bit definitions for VBAT_MON */
1095 #define PALMAS_VBAT_MON_ENABLE                                  0x80
1096 #define PALMAS_VBAT_MON_ENABLE_SHIFT                            7
1097 #define PALMAS_VBAT_MON_THRESHOLD_MASK                          0x3f
1098 #define PALMAS_VBAT_MON_THRESHOLD_SHIFT                         0
1099
1100 /* Bit definitions for WATCHDOG */
1101 #define PALMAS_WATCHDOG_LOCK                                    0x20
1102 #define PALMAS_WATCHDOG_LOCK_SHIFT                              5
1103 #define PALMAS_WATCHDOG_ENABLE                                  0x10
1104 #define PALMAS_WATCHDOG_ENABLE_SHIFT                            4
1105 #define PALMAS_WATCHDOG_MODE                                    0x08
1106 #define PALMAS_WATCHDOG_MODE_SHIFT                              3
1107 #define PALMAS_WATCHDOG_TIMER_MASK                              0x07
1108 #define PALMAS_WATCHDOG_TIMER_SHIFT                             0
1109
1110 /* Bit definitions for BOOT_STATUS */
1111 #define PALMAS_BOOT_STATUS_BOOT1                                0x02
1112 #define PALMAS_BOOT_STATUS_BOOT1_SHIFT                          1
1113 #define PALMAS_BOOT_STATUS_BOOT0                                0x01
1114 #define PALMAS_BOOT_STATUS_BOOT0_SHIFT                          0
1115
1116 /* Bit definitions for BATTERY_BOUNCE */
1117 #define PALMAS_BATTERY_BOUNCE_BB_DELAY_MASK                     0x3f
1118 #define PALMAS_BATTERY_BOUNCE_BB_DELAY_SHIFT                    0
1119
1120 /* Bit definitions for BACKUP_BATTERY_CTRL */
1121 #define PALMAS_BACKUP_BATTERY_CTRL_VRTC_18_15                   0x80
1122 #define PALMAS_BACKUP_BATTERY_CTRL_VRTC_18_15_SHIFT             7
1123 #define PALMAS_BACKUP_BATTERY_CTRL_VRTC_EN_SLP                  0x40
1124 #define PALMAS_BACKUP_BATTERY_CTRL_VRTC_EN_SLP_SHIFT            6
1125 #define PALMAS_BACKUP_BATTERY_CTRL_VRTC_EN_OFF                  0x20
1126 #define PALMAS_BACKUP_BATTERY_CTRL_VRTC_EN_OFF_SHIFT            5
1127 #define PALMAS_BACKUP_BATTERY_CTRL_VRTC_PWEN                    0x10
1128 #define PALMAS_BACKUP_BATTERY_CTRL_VRTC_PWEN_SHIFT              4
1129 #define PALMAS_BACKUP_BATTERY_CTRL_BBS_BBC_LOW_ICHRG            0x08
1130 #define PALMAS_BACKUP_BATTERY_CTRL_BBS_BBC_LOW_ICHRG_SHIFT      3
1131 #define PALMAS_BACKUP_BATTERY_CTRL_BB_SEL_MASK                  0x06
1132 #define PALMAS_BACKUP_BATTERY_CTRL_BB_SEL_SHIFT                 1
1133 #define PALMAS_BACKUP_BATTERY_CTRL_BB_CHG_EN                    0x01
1134 #define PALMAS_BACKUP_BATTERY_CTRL_BB_CHG_EN_SHIFT              0
1135
1136 /* Bit definitions for LONG_PRESS_KEY */
1137 #define PALMAS_LONG_PRESS_KEY_LPK_LOCK                          0x80
1138 #define PALMAS_LONG_PRESS_KEY_LPK_LOCK_SHIFT                    7
1139 #define PALMAS_LONG_PRESS_KEY_LPK_INT_CLR                       0x10
1140 #define PALMAS_LONG_PRESS_KEY_LPK_INT_CLR_SHIFT                 4
1141 #define PALMAS_LONG_PRESS_KEY_LPK_TIME_MASK                     0x0c
1142 #define PALMAS_LONG_PRESS_KEY_LPK_TIME_SHIFT                    2
1143 #define PALMAS_LONG_PRESS_KEY_PWRON_DEBOUNCE_MASK               0x03
1144 #define PALMAS_LONG_PRESS_KEY_PWRON_DEBOUNCE_SHIFT              0
1145
1146 /* Bit definitions for OSC_THERM_CTRL */
1147 #define PALMAS_OSC_THERM_CTRL_VANA_ON_IN_SLEEP                  0x80
1148 #define PALMAS_OSC_THERM_CTRL_VANA_ON_IN_SLEEP_SHIFT            7
1149 #define PALMAS_OSC_THERM_CTRL_INT_MASK_IN_SLEEP                 0x40
1150 #define PALMAS_OSC_THERM_CTRL_INT_MASK_IN_SLEEP_SHIFT           6
1151 #define PALMAS_OSC_THERM_CTRL_RC15MHZ_ON_IN_SLEEP               0x20
1152 #define PALMAS_OSC_THERM_CTRL_RC15MHZ_ON_IN_SLEEP_SHIFT         5
1153 #define PALMAS_OSC_THERM_CTRL_THERM_OFF_IN_SLEEP                0x10
1154 #define PALMAS_OSC_THERM_CTRL_THERM_OFF_IN_SLEEP_SHIFT          4
1155 #define PALMAS_OSC_THERM_CTRL_THERM_HD_SEL_MASK                 0x0c
1156 #define PALMAS_OSC_THERM_CTRL_THERM_HD_SEL_SHIFT                2
1157 #define PALMAS_OSC_THERM_CTRL_OSC_BYPASS                        0x02
1158 #define PALMAS_OSC_THERM_CTRL_OSC_BYPASS_SHIFT                  1
1159 #define PALMAS_OSC_THERM_CTRL_OSC_HPMODE                        0x01
1160 #define PALMAS_OSC_THERM_CTRL_OSC_HPMODE_SHIFT                  0
1161
1162 /* Bit definitions for BATDEBOUNCING */
1163 #define PALMAS_BATDEBOUNCING_BAT_DEB_BYPASS                     0x80
1164 #define PALMAS_BATDEBOUNCING_BAT_DEB_BYPASS_SHIFT               7
1165 #define PALMAS_BATDEBOUNCING_BINS_DEB_MASK                      0x78
1166 #define PALMAS_BATDEBOUNCING_BINS_DEB_SHIFT                     3
1167 #define PALMAS_BATDEBOUNCING_BEXT_DEB_MASK                      0x07
1168 #define PALMAS_BATDEBOUNCING_BEXT_DEB_SHIFT                     0
1169
1170 /* Bit definitions for SWOFF_HWRST */
1171 #define PALMAS_SWOFF_HWRST_PWRON_LPK                            0x80
1172 #define PALMAS_SWOFF_HWRST_PWRON_LPK_SHIFT                      7
1173 #define PALMAS_SWOFF_HWRST_PWRDOWN                              0x40
1174 #define PALMAS_SWOFF_HWRST_PWRDOWN_SHIFT                        6
1175 #define PALMAS_SWOFF_HWRST_WTD                                  0x20
1176 #define PALMAS_SWOFF_HWRST_WTD_SHIFT                            5
1177 #define PALMAS_SWOFF_HWRST_TSHUT                                0x10
1178 #define PALMAS_SWOFF_HWRST_TSHUT_SHIFT                          4
1179 #define PALMAS_SWOFF_HWRST_RESET_IN                             0x08
1180 #define PALMAS_SWOFF_HWRST_RESET_IN_SHIFT                       3
1181 #define PALMAS_SWOFF_HWRST_SW_RST                               0x04
1182 #define PALMAS_SWOFF_HWRST_SW_RST_SHIFT                         2
1183 #define PALMAS_SWOFF_HWRST_VSYS_LO                              0x02
1184 #define PALMAS_SWOFF_HWRST_VSYS_LO_SHIFT                        1
1185 #define PALMAS_SWOFF_HWRST_GPADC_SHUTDOWN                       0x01
1186 #define PALMAS_SWOFF_HWRST_GPADC_SHUTDOWN_SHIFT                 0
1187
1188 /* Bit definitions for SWOFF_COLDRST */
1189 #define PALMAS_SWOFF_COLDRST_PWRON_LPK                          0x80
1190 #define PALMAS_SWOFF_COLDRST_PWRON_LPK_SHIFT                    7
1191 #define PALMAS_SWOFF_COLDRST_PWRDOWN                            0x40
1192 #define PALMAS_SWOFF_COLDRST_PWRDOWN_SHIFT                      6
1193 #define PALMAS_SWOFF_COLDRST_WTD                                0x20
1194 #define PALMAS_SWOFF_COLDRST_WTD_SHIFT                          5
1195 #define PALMAS_SWOFF_COLDRST_TSHUT                              0x10
1196 #define PALMAS_SWOFF_COLDRST_TSHUT_SHIFT                        4
1197 #define PALMAS_SWOFF_COLDRST_RESET_IN                           0x08
1198 #define PALMAS_SWOFF_COLDRST_RESET_IN_SHIFT                     3
1199 #define PALMAS_SWOFF_COLDRST_SW_RST                             0x04
1200 #define PALMAS_SWOFF_COLDRST_SW_RST_SHIFT                       2
1201 #define PALMAS_SWOFF_COLDRST_VSYS_LO                            0x02
1202 #define PALMAS_SWOFF_COLDRST_VSYS_LO_SHIFT                      1
1203 #define PALMAS_SWOFF_COLDRST_GPADC_SHUTDOWN                     0x01
1204 #define PALMAS_SWOFF_COLDRST_GPADC_SHUTDOWN_SHIFT               0
1205
1206 /* Bit definitions for SWOFF_STATUS */
1207 #define PALMAS_SWOFF_STATUS_PWRON_LPK                           0x80
1208 #define PALMAS_SWOFF_STATUS_PWRON_LPK_SHIFT                     7
1209 #define PALMAS_SWOFF_STATUS_PWRDOWN                             0x40
1210 #define PALMAS_SWOFF_STATUS_PWRDOWN_SHIFT                       6
1211 #define PALMAS_SWOFF_STATUS_WTD                                 0x20
1212 #define PALMAS_SWOFF_STATUS_WTD_SHIFT                           5
1213 #define PALMAS_SWOFF_STATUS_TSHUT                               0x10
1214 #define PALMAS_SWOFF_STATUS_TSHUT_SHIFT                         4
1215 #define PALMAS_SWOFF_STATUS_RESET_IN                            0x08
1216 #define PALMAS_SWOFF_STATUS_RESET_IN_SHIFT                      3
1217 #define PALMAS_SWOFF_STATUS_SW_RST                              0x04
1218 #define PALMAS_SWOFF_STATUS_SW_RST_SHIFT                        2
1219 #define PALMAS_SWOFF_STATUS_VSYS_LO                             0x02
1220 #define PALMAS_SWOFF_STATUS_VSYS_LO_SHIFT                       1
1221 #define PALMAS_SWOFF_STATUS_GPADC_SHUTDOWN                      0x01
1222 #define PALMAS_SWOFF_STATUS_GPADC_SHUTDOWN_SHIFT                0
1223
1224 /* Bit definitions for PMU_CONFIG */
1225 #define PALMAS_PMU_CONFIG_MULTI_CELL_EN                         0x40
1226 #define PALMAS_PMU_CONFIG_MULTI_CELL_EN_SHIFT                   6
1227 #define PALMAS_PMU_CONFIG_SPARE_MASK                            0x30
1228 #define PALMAS_PMU_CONFIG_SPARE_SHIFT                           4
1229 #define PALMAS_PMU_CONFIG_SWOFF_DLY_MASK                        0x0c
1230 #define PALMAS_PMU_CONFIG_SWOFF_DLY_SHIFT                       2
1231 #define PALMAS_PMU_CONFIG_GATE_RESET_OUT                        0x02
1232 #define PALMAS_PMU_CONFIG_GATE_RESET_OUT_SHIFT                  1
1233 #define PALMAS_PMU_CONFIG_AUTODEVON                             0x01
1234 #define PALMAS_PMU_CONFIG_AUTODEVON_SHIFT                       0
1235
1236 /* Bit definitions for SPARE */
1237 #define PALMAS_SPARE_SPARE_MASK                                 0xf8
1238 #define PALMAS_SPARE_SPARE_SHIFT                                3
1239 #define PALMAS_SPARE_REGEN3_OD                                  0x04
1240 #define PALMAS_SPARE_REGEN3_OD_SHIFT                            2
1241 #define PALMAS_SPARE_REGEN2_OD                                  0x02
1242 #define PALMAS_SPARE_REGEN2_OD_SHIFT                            1
1243 #define PALMAS_SPARE_REGEN1_OD                                  0x01
1244 #define PALMAS_SPARE_REGEN1_OD_SHIFT                            0
1245
1246 /* Bit definitions for PMU_SECONDARY_INT */
1247 #define PALMAS_PMU_SECONDARY_INT_VBUS_OVV_INT_SRC               0x80
1248 #define PALMAS_PMU_SECONDARY_INT_VBUS_OVV_INT_SRC_SHIFT         7
1249 #define PALMAS_PMU_SECONDARY_INT_CHARG_DET_N_INT_SRC            0x40
1250 #define PALMAS_PMU_SECONDARY_INT_CHARG_DET_N_INT_SRC_SHIFT      6
1251 #define PALMAS_PMU_SECONDARY_INT_BB_INT_SRC                     0x20
1252 #define PALMAS_PMU_SECONDARY_INT_BB_INT_SRC_SHIFT               5
1253 #define PALMAS_PMU_SECONDARY_INT_FBI_INT_SRC                    0x10
1254 #define PALMAS_PMU_SECONDARY_INT_FBI_INT_SRC_SHIFT              4
1255 #define PALMAS_PMU_SECONDARY_INT_VBUS_OVV_MASK                  0x08
1256 #define PALMAS_PMU_SECONDARY_INT_VBUS_OVV_MASK_SHIFT            3
1257 #define PALMAS_PMU_SECONDARY_INT_CHARG_DET_N_MASK               0x04
1258 #define PALMAS_PMU_SECONDARY_INT_CHARG_DET_N_MASK_SHIFT         2
1259 #define PALMAS_PMU_SECONDARY_INT_BB_MASK                        0x02
1260 #define PALMAS_PMU_SECONDARY_INT_BB_MASK_SHIFT                  1
1261 #define PALMAS_PMU_SECONDARY_INT_FBI_MASK                       0x01
1262 #define PALMAS_PMU_SECONDARY_INT_FBI_MASK_SHIFT                 0
1263
1264 /* Bit definitions for SW_REVISION */
1265 #define PALMAS_SW_REVISION_SW_REVISION_MASK                     0xff
1266 #define PALMAS_SW_REVISION_SW_REVISION_SHIFT                    0
1267
1268 /* Bit definitions for EXT_CHRG_CTRL */
1269 #define PALMAS_EXT_CHRG_CTRL_VBUS_OVV_STATUS                    0x80
1270 #define PALMAS_EXT_CHRG_CTRL_VBUS_OVV_STATUS_SHIFT              7
1271 #define PALMAS_EXT_CHRG_CTRL_CHARG_DET_N_STATUS                 0x40
1272 #define PALMAS_EXT_CHRG_CTRL_CHARG_DET_N_STATUS_SHIFT           6
1273 #define PALMAS_EXT_CHRG_CTRL_VSYS_DEBOUNCE_DELAY                0x08
1274 #define PALMAS_EXT_CHRG_CTRL_VSYS_DEBOUNCE_DELAY_SHIFT          3
1275 #define PALMAS_EXT_CHRG_CTRL_CHRG_DET_N                         0x04
1276 #define PALMAS_EXT_CHRG_CTRL_CHRG_DET_N_SHIFT                   2
1277 #define PALMAS_EXT_CHRG_CTRL_AUTO_ACA_EN                        0x02
1278 #define PALMAS_EXT_CHRG_CTRL_AUTO_ACA_EN_SHIFT                  1
1279 #define PALMAS_EXT_CHRG_CTRL_AUTO_LDOUSB_EN                     0x01
1280 #define PALMAS_EXT_CHRG_CTRL_AUTO_LDOUSB_EN_SHIFT               0
1281
1282 /* Bit definitions for PMU_SECONDARY_INT2 */
1283 #define PALMAS_PMU_SECONDARY_INT2_DVFS2_INT_SRC                 0x20
1284 #define PALMAS_PMU_SECONDARY_INT2_DVFS2_INT_SRC_SHIFT           5
1285 #define PALMAS_PMU_SECONDARY_INT2_DVFS1_INT_SRC                 0x10
1286 #define PALMAS_PMU_SECONDARY_INT2_DVFS1_INT_SRC_SHIFT           4
1287 #define PALMAS_PMU_SECONDARY_INT2_DVFS2_MASK                    0x02
1288 #define PALMAS_PMU_SECONDARY_INT2_DVFS2_MASK_SHIFT              1
1289 #define PALMAS_PMU_SECONDARY_INT2_DVFS1_MASK                    0x01
1290 #define PALMAS_PMU_SECONDARY_INT2_DVFS1_MASK_SHIFT              0
1291
1292 /* Registers for function RESOURCE */
1293 #define PALMAS_CLK32KG_CTRL                                     0x0
1294 #define PALMAS_CLK32KGAUDIO_CTRL                                0x1
1295 #define PALMAS_REGEN1_CTRL                                      0x2
1296 #define PALMAS_REGEN2_CTRL                                      0x3
1297 #define PALMAS_SYSEN1_CTRL                                      0x4
1298 #define PALMAS_SYSEN2_CTRL                                      0x5
1299 #define PALMAS_NSLEEP_RES_ASSIGN                                0x6
1300 #define PALMAS_NSLEEP_SMPS_ASSIGN                               0x7
1301 #define PALMAS_NSLEEP_LDO_ASSIGN1                               0x8
1302 #define PALMAS_NSLEEP_LDO_ASSIGN2                               0x9
1303 #define PALMAS_ENABLE1_RES_ASSIGN                               0xA
1304 #define PALMAS_ENABLE1_SMPS_ASSIGN                              0xB
1305 #define PALMAS_ENABLE1_LDO_ASSIGN1                              0xC
1306 #define PALMAS_ENABLE1_LDO_ASSIGN2                              0xD
1307 #define PALMAS_ENABLE2_RES_ASSIGN                               0xE
1308 #define PALMAS_ENABLE2_SMPS_ASSIGN                              0xF
1309 #define PALMAS_ENABLE2_LDO_ASSIGN1                              0x10
1310 #define PALMAS_ENABLE2_LDO_ASSIGN2                              0x11
1311 #define PALMAS_REGEN3_CTRL                                      0x12
1312
1313 /* Bit definitions for CLK32KG_CTRL */
1314 #define PALMAS_CLK32KG_CTRL_STATUS                              0x10
1315 #define PALMAS_CLK32KG_CTRL_STATUS_SHIFT                        4
1316 #define PALMAS_CLK32KG_CTRL_MODE_SLEEP                          0x04
1317 #define PALMAS_CLK32KG_CTRL_MODE_SLEEP_SHIFT                    2
1318 #define PALMAS_CLK32KG_CTRL_MODE_ACTIVE                         0x01
1319 #define PALMAS_CLK32KG_CTRL_MODE_ACTIVE_SHIFT                   0
1320
1321 /* Bit definitions for CLK32KGAUDIO_CTRL */
1322 #define PALMAS_CLK32KGAUDIO_CTRL_STATUS                         0x10
1323 #define PALMAS_CLK32KGAUDIO_CTRL_STATUS_SHIFT                   4
1324 #define PALMAS_CLK32KGAUDIO_CTRL_RESERVED3                      0x08
1325 #define PALMAS_CLK32KGAUDIO_CTRL_RESERVED3_SHIFT                3
1326 #define PALMAS_CLK32KGAUDIO_CTRL_MODE_SLEEP                     0x04
1327 #define PALMAS_CLK32KGAUDIO_CTRL_MODE_SLEEP_SHIFT               2
1328 #define PALMAS_CLK32KGAUDIO_CTRL_MODE_ACTIVE                    0x01
1329 #define PALMAS_CLK32KGAUDIO_CTRL_MODE_ACTIVE_SHIFT              0
1330
1331 /* Bit definitions for REGEN1_CTRL */
1332 #define PALMAS_REGEN1_CTRL_STATUS                               0x10
1333 #define PALMAS_REGEN1_CTRL_STATUS_SHIFT                         4
1334 #define PALMAS_REGEN1_CTRL_MODE_SLEEP                           0x04
1335 #define PALMAS_REGEN1_CTRL_MODE_SLEEP_SHIFT                     2
1336 #define PALMAS_REGEN1_CTRL_MODE_ACTIVE                          0x01
1337 #define PALMAS_REGEN1_CTRL_MODE_ACTIVE_SHIFT                    0
1338
1339 /* Bit definitions for REGEN2_CTRL */
1340 #define PALMAS_REGEN2_CTRL_STATUS                               0x10
1341 #define PALMAS_REGEN2_CTRL_STATUS_SHIFT                         4
1342 #define PALMAS_REGEN2_CTRL_MODE_SLEEP                           0x04
1343 #define PALMAS_REGEN2_CTRL_MODE_SLEEP_SHIFT                     2
1344 #define PALMAS_REGEN2_CTRL_MODE_ACTIVE                          0x01
1345 #define PALMAS_REGEN2_CTRL_MODE_ACTIVE_SHIFT                    0
1346
1347 /* Bit definitions for SYSEN1_CTRL */
1348 #define PALMAS_SYSEN1_CTRL_STATUS                               0x10
1349 #define PALMAS_SYSEN1_CTRL_STATUS_SHIFT                         4
1350 #define PALMAS_SYSEN1_CTRL_MODE_SLEEP                           0x04
1351 #define PALMAS_SYSEN1_CTRL_MODE_SLEEP_SHIFT                     2
1352 #define PALMAS_SYSEN1_CTRL_MODE_ACTIVE                          0x01
1353 #define PALMAS_SYSEN1_CTRL_MODE_ACTIVE_SHIFT                    0
1354
1355 /* Bit definitions for SYSEN2_CTRL */
1356 #define PALMAS_SYSEN2_CTRL_STATUS                               0x10
1357 #define PALMAS_SYSEN2_CTRL_STATUS_SHIFT                         4
1358 #define PALMAS_SYSEN2_CTRL_MODE_SLEEP                           0x04
1359 #define PALMAS_SYSEN2_CTRL_MODE_SLEEP_SHIFT                     2
1360 #define PALMAS_SYSEN2_CTRL_MODE_ACTIVE                          0x01
1361 #define PALMAS_SYSEN2_CTRL_MODE_ACTIVE_SHIFT                    0
1362
1363 /* Bit definitions for NSLEEP_RES_ASSIGN */
1364 #define PALMAS_NSLEEP_RES_ASSIGN_REGEN3                         0x40
1365 #define PALMAS_NSLEEP_RES_ASSIGN_REGEN3_SHIFT                   6
1366 #define PALMAS_NSLEEP_RES_ASSIGN_CLK32KGAUDIO                   0x20
1367 #define PALMAS_NSLEEP_RES_ASSIGN_CLK32KGAUDIO_SHIFT             5
1368 #define PALMAS_NSLEEP_RES_ASSIGN_CLK32KG                        0x10
1369 #define PALMAS_NSLEEP_RES_ASSIGN_CLK32KG_SHIFT                  4
1370 #define PALMAS_NSLEEP_RES_ASSIGN_SYSEN2                         0x08
1371 #define PALMAS_NSLEEP_RES_ASSIGN_SYSEN2_SHIFT                   3
1372 #define PALMAS_NSLEEP_RES_ASSIGN_SYSEN1                         0x04
1373 #define PALMAS_NSLEEP_RES_ASSIGN_SYSEN1_SHIFT                   2
1374 #define PALMAS_NSLEEP_RES_ASSIGN_REGEN2                         0x02
1375 #define PALMAS_NSLEEP_RES_ASSIGN_REGEN2_SHIFT                   1
1376 #define PALMAS_NSLEEP_RES_ASSIGN_REGEN1                         0x01
1377 #define PALMAS_NSLEEP_RES_ASSIGN_REGEN1_SHIFT                   0
1378
1379 /* Bit definitions for NSLEEP_SMPS_ASSIGN */
1380 #define PALMAS_NSLEEP_SMPS_ASSIGN_SMPS10                        0x80
1381 #define PALMAS_NSLEEP_SMPS_ASSIGN_SMPS10_SHIFT                  7
1382 #define PALMAS_NSLEEP_SMPS_ASSIGN_SMPS9                         0x40
1383 #define PALMAS_NSLEEP_SMPS_ASSIGN_SMPS9_SHIFT                   6
1384 #define PALMAS_NSLEEP_SMPS_ASSIGN_SMPS8                         0x20
1385 #define PALMAS_NSLEEP_SMPS_ASSIGN_SMPS8_SHIFT                   5
1386 #define PALMAS_NSLEEP_SMPS_ASSIGN_SMPS7                         0x10
1387 #define PALMAS_NSLEEP_SMPS_ASSIGN_SMPS7_SHIFT                   4
1388 #define PALMAS_NSLEEP_SMPS_ASSIGN_SMPS6                         0x08
1389 #define PALMAS_NSLEEP_SMPS_ASSIGN_SMPS6_SHIFT                   3
1390 #define PALMAS_NSLEEP_SMPS_ASSIGN_SMPS45                        0x04
1391 #define PALMAS_NSLEEP_SMPS_ASSIGN_SMPS45_SHIFT                  2
1392 #define PALMAS_NSLEEP_SMPS_ASSIGN_SMPS3                         0x02
1393 #define PALMAS_NSLEEP_SMPS_ASSIGN_SMPS3_SHIFT                   1
1394 #define PALMAS_NSLEEP_SMPS_ASSIGN_SMPS12                        0x01
1395 #define PALMAS_NSLEEP_SMPS_ASSIGN_SMPS12_SHIFT                  0
1396
1397 /* Bit definitions for NSLEEP_LDO_ASSIGN1 */
1398 #define PALMAS_NSLEEP_LDO_ASSIGN1_LDO8                          0x80
1399 #define PALMAS_NSLEEP_LDO_ASSIGN1_LDO8_SHIFT                    7
1400 #define PALMAS_NSLEEP_LDO_ASSIGN1_LDO7                          0x40
1401 #define PALMAS_NSLEEP_LDO_ASSIGN1_LDO7_SHIFT                    6
1402 #define PALMAS_NSLEEP_LDO_ASSIGN1_LDO6                          0x20
1403 #define PALMAS_NSLEEP_LDO_ASSIGN1_LDO6_SHIFT                    5
1404 #define PALMAS_NSLEEP_LDO_ASSIGN1_LDO5                          0x10
1405 #define PALMAS_NSLEEP_LDO_ASSIGN1_LDO5_SHIFT                    4
1406 #define PALMAS_NSLEEP_LDO_ASSIGN1_LDO4                          0x08
1407 #define PALMAS_NSLEEP_LDO_ASSIGN1_LDO4_SHIFT                    3
1408 #define PALMAS_NSLEEP_LDO_ASSIGN1_LDO3                          0x04
1409 #define PALMAS_NSLEEP_LDO_ASSIGN1_LDO3_SHIFT                    2
1410 #define PALMAS_NSLEEP_LDO_ASSIGN1_LDO2                          0x02
1411 #define PALMAS_NSLEEP_LDO_ASSIGN1_LDO2_SHIFT                    1
1412 #define PALMAS_NSLEEP_LDO_ASSIGN1_LDO1                          0x01
1413 #define PALMAS_NSLEEP_LDO_ASSIGN1_LDO1_SHIFT                    0
1414
1415 /* Bit definitions for NSLEEP_LDO_ASSIGN2 */
1416 #define PALMAS_NSLEEP_LDO_ASSIGN2_LDOUSB                        0x04
1417 #define PALMAS_NSLEEP_LDO_ASSIGN2_LDOUSB_SHIFT                  2
1418 #define PALMAS_NSLEEP_LDO_ASSIGN2_LDOLN                         0x02
1419 #define PALMAS_NSLEEP_LDO_ASSIGN2_LDOLN_SHIFT                   1
1420 #define PALMAS_NSLEEP_LDO_ASSIGN2_LDO9                          0x01
1421 #define PALMAS_NSLEEP_LDO_ASSIGN2_LDO9_SHIFT                    0
1422
1423 /* Bit definitions for ENABLE1_RES_ASSIGN */
1424 #define PALMAS_ENABLE1_RES_ASSIGN_REGEN3                        0x40
1425 #define PALMAS_ENABLE1_RES_ASSIGN_REGEN3_SHIFT                  6
1426 #define PALMAS_ENABLE1_RES_ASSIGN_CLK32KGAUDIO                  0x20
1427 #define PALMAS_ENABLE1_RES_ASSIGN_CLK32KGAUDIO_SHIFT            5
1428 #define PALMAS_ENABLE1_RES_ASSIGN_CLK32KG                       0x10
1429 #define PALMAS_ENABLE1_RES_ASSIGN_CLK32KG_SHIFT                 4
1430 #define PALMAS_ENABLE1_RES_ASSIGN_SYSEN2                        0x08
1431 #define PALMAS_ENABLE1_RES_ASSIGN_SYSEN2_SHIFT                  3
1432 #define PALMAS_ENABLE1_RES_ASSIGN_SYSEN1                        0x04
1433 #define PALMAS_ENABLE1_RES_ASSIGN_SYSEN1_SHIFT                  2
1434 #define PALMAS_ENABLE1_RES_ASSIGN_REGEN2                        0x02
1435 #define PALMAS_ENABLE1_RES_ASSIGN_REGEN2_SHIFT                  1
1436 #define PALMAS_ENABLE1_RES_ASSIGN_REGEN1                        0x01
1437 #define PALMAS_ENABLE1_RES_ASSIGN_REGEN1_SHIFT                  0
1438
1439 /* Bit definitions for ENABLE1_SMPS_ASSIGN */
1440 #define PALMAS_ENABLE1_SMPS_ASSIGN_SMPS10                       0x80
1441 #define PALMAS_ENABLE1_SMPS_ASSIGN_SMPS10_SHIFT                 7
1442 #define PALMAS_ENABLE1_SMPS_ASSIGN_SMPS9                        0x40
1443 #define PALMAS_ENABLE1_SMPS_ASSIGN_SMPS9_SHIFT                  6
1444 #define PALMAS_ENABLE1_SMPS_ASSIGN_SMPS8                        0x20
1445 #define PALMAS_ENABLE1_SMPS_ASSIGN_SMPS8_SHIFT                  5
1446 #define PALMAS_ENABLE1_SMPS_ASSIGN_SMPS7                        0x10
1447 #define PALMAS_ENABLE1_SMPS_ASSIGN_SMPS7_SHIFT                  4
1448 #define PALMAS_ENABLE1_SMPS_ASSIGN_SMPS6                        0x08
1449 #define PALMAS_ENABLE1_SMPS_ASSIGN_SMPS6_SHIFT                  3
1450 #define PALMAS_ENABLE1_SMPS_ASSIGN_SMPS45                       0x04
1451 #define PALMAS_ENABLE1_SMPS_ASSIGN_SMPS45_SHIFT                 2
1452 #define PALMAS_ENABLE1_SMPS_ASSIGN_SMPS3                        0x02
1453 #define PALMAS_ENABLE1_SMPS_ASSIGN_SMPS3_SHIFT                  1
1454 #define PALMAS_ENABLE1_SMPS_ASSIGN_SMPS12                       0x01
1455 #define PALMAS_ENABLE1_SMPS_ASSIGN_SMPS12_SHIFT                 0
1456
1457 /* Bit definitions for ENABLE1_LDO_ASSIGN1 */
1458 #define PALMAS_ENABLE1_LDO_ASSIGN1_LDO8                         0x80
1459 #define PALMAS_ENABLE1_LDO_ASSIGN1_LDO8_SHIFT                   7
1460 #define PALMAS_ENABLE1_LDO_ASSIGN1_LDO7                         0x40
1461 #define PALMAS_ENABLE1_LDO_ASSIGN1_LDO7_SHIFT                   6
1462 #define PALMAS_ENABLE1_LDO_ASSIGN1_LDO6                         0x20
1463 #define PALMAS_ENABLE1_LDO_ASSIGN1_LDO6_SHIFT                   5
1464 #define PALMAS_ENABLE1_LDO_ASSIGN1_LDO5                         0x10
1465 #define PALMAS_ENABLE1_LDO_ASSIGN1_LDO5_SHIFT                   4
1466 #define PALMAS_ENABLE1_LDO_ASSIGN1_LDO4                         0x08
1467 #define PALMAS_ENABLE1_LDO_ASSIGN1_LDO4_SHIFT                   3
1468 #define PALMAS_ENABLE1_LDO_ASSIGN1_LDO3                         0x04
1469 #define PALMAS_ENABLE1_LDO_ASSIGN1_LDO3_SHIFT                   2
1470 #define PALMAS_ENABLE1_LDO_ASSIGN1_LDO2                         0x02
1471 #define PALMAS_ENABLE1_LDO_ASSIGN1_LDO2_SHIFT                   1
1472 #define PALMAS_ENABLE1_LDO_ASSIGN1_LDO1                         0x01
1473 #define PALMAS_ENABLE1_LDO_ASSIGN1_LDO1_SHIFT                   0
1474
1475 /* Bit definitions for ENABLE1_LDO_ASSIGN2 */
1476 #define PALMAS_ENABLE1_LDO_ASSIGN2_LDOUSB                       0x04
1477 #define PALMAS_ENABLE1_LDO_ASSIGN2_LDOUSB_SHIFT                 2
1478 #define PALMAS_ENABLE1_LDO_ASSIGN2_LDOLN                        0x02
1479 #define PALMAS_ENABLE1_LDO_ASSIGN2_LDOLN_SHIFT                  1
1480 #define PALMAS_ENABLE1_LDO_ASSIGN2_LDO9                         0x01
1481 #define PALMAS_ENABLE1_LDO_ASSIGN2_LDO9_SHIFT                   0
1482
1483 /* Bit definitions for ENABLE2_RES_ASSIGN */
1484 #define PALMAS_ENABLE2_RES_ASSIGN_REGEN3                        0x40
1485 #define PALMAS_ENABLE2_RES_ASSIGN_REGEN3_SHIFT                  6
1486 #define PALMAS_ENABLE2_RES_ASSIGN_CLK32KGAUDIO                  0x20
1487 #define PALMAS_ENABLE2_RES_ASSIGN_CLK32KGAUDIO_SHIFT            5
1488 #define PALMAS_ENABLE2_RES_ASSIGN_CLK32KG                       0x10
1489 #define PALMAS_ENABLE2_RES_ASSIGN_CLK32KG_SHIFT                 4
1490 #define PALMAS_ENABLE2_RES_ASSIGN_SYSEN2                        0x08
1491 #define PALMAS_ENABLE2_RES_ASSIGN_SYSEN2_SHIFT                  3
1492 #define PALMAS_ENABLE2_RES_ASSIGN_SYSEN1                        0x04
1493 #define PALMAS_ENABLE2_RES_ASSIGN_SYSEN1_SHIFT                  2
1494 #define PALMAS_ENABLE2_RES_ASSIGN_REGEN2                        0x02
1495 #define PALMAS_ENABLE2_RES_ASSIGN_REGEN2_SHIFT                  1
1496 #define PALMAS_ENABLE2_RES_ASSIGN_REGEN1                        0x01
1497 #define PALMAS_ENABLE2_RES_ASSIGN_REGEN1_SHIFT                  0
1498
1499 /* Bit definitions for ENABLE2_SMPS_ASSIGN */
1500 #define PALMAS_ENABLE2_SMPS_ASSIGN_SMPS10                       0x80
1501 #define PALMAS_ENABLE2_SMPS_ASSIGN_SMPS10_SHIFT                 7
1502 #define PALMAS_ENABLE2_SMPS_ASSIGN_SMPS9                        0x40
1503 #define PALMAS_ENABLE2_SMPS_ASSIGN_SMPS9_SHIFT                  6
1504 #define PALMAS_ENABLE2_SMPS_ASSIGN_SMPS8                        0x20
1505 #define PALMAS_ENABLE2_SMPS_ASSIGN_SMPS8_SHIFT                  5
1506 #define PALMAS_ENABLE2_SMPS_ASSIGN_SMPS7                        0x10
1507 #define PALMAS_ENABLE2_SMPS_ASSIGN_SMPS7_SHIFT                  4
1508 #define PALMAS_ENABLE2_SMPS_ASSIGN_SMPS6                        0x08
1509 #define PALMAS_ENABLE2_SMPS_ASSIGN_SMPS6_SHIFT                  3
1510 #define PALMAS_ENABLE2_SMPS_ASSIGN_SMPS45                       0x04
1511 #define PALMAS_ENABLE2_SMPS_ASSIGN_SMPS45_SHIFT                 2
1512 #define PALMAS_ENABLE2_SMPS_ASSIGN_SMPS3                        0x02
1513 #define PALMAS_ENABLE2_SMPS_ASSIGN_SMPS3_SHIFT                  1
1514 #define PALMAS_ENABLE2_SMPS_ASSIGN_SMPS12                       0x01
1515 #define PALMAS_ENABLE2_SMPS_ASSIGN_SMPS12_SHIFT                 0
1516
1517 /* Bit definitions for ENABLE2_LDO_ASSIGN1 */
1518 #define PALMAS_ENABLE2_LDO_ASSIGN1_LDO8                         0x80
1519 #define PALMAS_ENABLE2_LDO_ASSIGN1_LDO8_SHIFT                   7
1520 #define PALMAS_ENABLE2_LDO_ASSIGN1_LDO7                         0x40
1521 #define PALMAS_ENABLE2_LDO_ASSIGN1_LDO7_SHIFT                   6
1522 #define PALMAS_ENABLE2_LDO_ASSIGN1_LDO6                         0x20
1523 #define PALMAS_ENABLE2_LDO_ASSIGN1_LDO6_SHIFT                   5
1524 #define PALMAS_ENABLE2_LDO_ASSIGN1_LDO5                         0x10
1525 #define PALMAS_ENABLE2_LDO_ASSIGN1_LDO5_SHIFT                   4
1526 #define PALMAS_ENABLE2_LDO_ASSIGN1_LDO4                         0x08
1527 #define PALMAS_ENABLE2_LDO_ASSIGN1_LDO4_SHIFT                   3
1528 #define PALMAS_ENABLE2_LDO_ASSIGN1_LDO3                         0x04
1529 #define PALMAS_ENABLE2_LDO_ASSIGN1_LDO3_SHIFT                   2
1530 #define PALMAS_ENABLE2_LDO_ASSIGN1_LDO2                         0x02
1531 #define PALMAS_ENABLE2_LDO_ASSIGN1_LDO2_SHIFT                   1
1532 #define PALMAS_ENABLE2_LDO_ASSIGN1_LDO1                         0x01
1533 #define PALMAS_ENABLE2_LDO_ASSIGN1_LDO1_SHIFT                   0
1534
1535 /* Bit definitions for ENABLE2_LDO_ASSIGN2 */
1536 #define PALMAS_ENABLE2_LDO_ASSIGN2_LDOUSB                       0x04
1537 #define PALMAS_ENABLE2_LDO_ASSIGN2_LDOUSB_SHIFT                 2
1538 #define PALMAS_ENABLE2_LDO_ASSIGN2_LDOLN                        0x02
1539 #define PALMAS_ENABLE2_LDO_ASSIGN2_LDOLN_SHIFT                  1
1540 #define PALMAS_ENABLE2_LDO_ASSIGN2_LDO9                         0x01
1541 #define PALMAS_ENABLE2_LDO_ASSIGN2_LDO9_SHIFT                   0
1542
1543 /* Bit definitions for REGEN3_CTRL */
1544 #define PALMAS_REGEN3_CTRL_STATUS                               0x10
1545 #define PALMAS_REGEN3_CTRL_STATUS_SHIFT                         4
1546 #define PALMAS_REGEN3_CTRL_MODE_SLEEP                           0x04
1547 #define PALMAS_REGEN3_CTRL_MODE_SLEEP_SHIFT                     2
1548 #define PALMAS_REGEN3_CTRL_MODE_ACTIVE                          0x01
1549 #define PALMAS_REGEN3_CTRL_MODE_ACTIVE_SHIFT                    0
1550
1551 /* Registers for function PAD_CONTROL */
1552 #define PALMAS_PU_PD_INPUT_CTRL1                                0x0
1553 #define PALMAS_PU_PD_INPUT_CTRL2                                0x1
1554 #define PALMAS_PU_PD_INPUT_CTRL3                                0x2
1555 #define PALMAS_OD_OUTPUT_CTRL                                   0x4
1556 #define PALMAS_POLARITY_CTRL                                    0x5
1557 #define PALMAS_PRIMARY_SECONDARY_PAD1                           0x6
1558 #define PALMAS_PRIMARY_SECONDARY_PAD2                           0x7
1559 #define PALMAS_I2C_SPI                                          0x8
1560 #define PALMAS_PU_PD_INPUT_CTRL4                                0x9
1561 #define PALMAS_PRIMARY_SECONDARY_PAD3                           0xA
1562
1563 /* Bit definitions for PU_PD_INPUT_CTRL1 */
1564 #define PALMAS_PU_PD_INPUT_CTRL1_RESET_IN_PD                    0x40
1565 #define PALMAS_PU_PD_INPUT_CTRL1_RESET_IN_PD_SHIFT              6
1566 #define PALMAS_PU_PD_INPUT_CTRL1_GPADC_START_PU                 0x20
1567 #define PALMAS_PU_PD_INPUT_CTRL1_GPADC_START_PU_SHIFT           5
1568 #define PALMAS_PU_PD_INPUT_CTRL1_GPADC_START_PD                 0x10
1569 #define PALMAS_PU_PD_INPUT_CTRL1_GPADC_START_PD_SHIFT           4
1570 #define PALMAS_PU_PD_INPUT_CTRL1_PWRDOWN_PD                     0x04
1571 #define PALMAS_PU_PD_INPUT_CTRL1_PWRDOWN_PD_SHIFT               2
1572 #define PALMAS_PU_PD_INPUT_CTRL1_NRESWARM_PU                    0x02
1573 #define PALMAS_PU_PD_INPUT_CTRL1_NRESWARM_PU_SHIFT              1
1574
1575 /* Bit definitions for PU_PD_INPUT_CTRL2 */
1576 #define PALMAS_PU_PD_INPUT_CTRL2_ENABLE2_PU                     0x20
1577 #define PALMAS_PU_PD_INPUT_CTRL2_ENABLE2_PU_SHIFT               5
1578 #define PALMAS_PU_PD_INPUT_CTRL2_ENABLE2_PD                     0x10
1579 #define PALMAS_PU_PD_INPUT_CTRL2_ENABLE2_PD_SHIFT               4
1580 #define PALMAS_PU_PD_INPUT_CTRL2_ENABLE1_PU                     0x08
1581 #define PALMAS_PU_PD_INPUT_CTRL2_ENABLE1_PU_SHIFT               3
1582 #define PALMAS_PU_PD_INPUT_CTRL2_ENABLE1_PD                     0x04
1583 #define PALMAS_PU_PD_INPUT_CTRL2_ENABLE1_PD_SHIFT               2
1584 #define PALMAS_PU_PD_INPUT_CTRL2_NSLEEP_PU                      0x02
1585 #define PALMAS_PU_PD_INPUT_CTRL2_NSLEEP_PU_SHIFT                1
1586 #define PALMAS_PU_PD_INPUT_CTRL2_NSLEEP_PD                      0x01
1587 #define PALMAS_PU_PD_INPUT_CTRL2_NSLEEP_PD_SHIFT                0
1588
1589 /* Bit definitions for PU_PD_INPUT_CTRL3 */
1590 #define PALMAS_PU_PD_INPUT_CTRL3_ACOK_PD                        0x40
1591 #define PALMAS_PU_PD_INPUT_CTRL3_ACOK_PD_SHIFT                  6
1592 #define PALMAS_PU_PD_INPUT_CTRL3_CHRG_DET_N_PD                  0x10
1593 #define PALMAS_PU_PD_INPUT_CTRL3_CHRG_DET_N_PD_SHIFT            4
1594 #define PALMAS_PU_PD_INPUT_CTRL3_POWERHOLD_PD                   0x04
1595 #define PALMAS_PU_PD_INPUT_CTRL3_POWERHOLD_PD_SHIFT             2
1596 #define PALMAS_PU_PD_INPUT_CTRL3_MSECURE_PD                     0x01
1597 #define PALMAS_PU_PD_INPUT_CTRL3_MSECURE_PD_SHIFT               0
1598
1599 /* Bit definitions for OD_OUTPUT_CTRL */
1600 #define PALMAS_OD_OUTPUT_CTRL_PWM_2_OD                          0x80
1601 #define PALMAS_OD_OUTPUT_CTRL_PWM_2_OD_SHIFT                    7
1602 #define PALMAS_OD_OUTPUT_CTRL_VBUSDET_OD                        0x40
1603 #define PALMAS_OD_OUTPUT_CTRL_VBUSDET_OD_SHIFT                  6
1604 #define PALMAS_OD_OUTPUT_CTRL_PWM_1_OD                          0x20
1605 #define PALMAS_OD_OUTPUT_CTRL_PWM_1_OD_SHIFT                    5
1606 #define PALMAS_OD_OUTPUT_CTRL_INT_OD                            0x08
1607 #define PALMAS_OD_OUTPUT_CTRL_INT_OD_SHIFT                      3
1608
1609 /* Bit definitions for POLARITY_CTRL */
1610 #define PALMAS_POLARITY_CTRL_INT_POLARITY                       0x80
1611 #define PALMAS_POLARITY_CTRL_INT_POLARITY_SHIFT                 7
1612 #define PALMAS_POLARITY_CTRL_ENABLE2_POLARITY                   0x40
1613 #define PALMAS_POLARITY_CTRL_ENABLE2_POLARITY_SHIFT             6
1614 #define PALMAS_POLARITY_CTRL_ENABLE1_POLARITY                   0x20
1615 #define PALMAS_POLARITY_CTRL_ENABLE1_POLARITY_SHIFT             5
1616 #define PALMAS_POLARITY_CTRL_NSLEEP_POLARITY                    0x10
1617 #define PALMAS_POLARITY_CTRL_NSLEEP_POLARITY_SHIFT              4
1618 #define PALMAS_POLARITY_CTRL_RESET_IN_POLARITY                  0x08
1619 #define PALMAS_POLARITY_CTRL_RESET_IN_POLARITY_SHIFT            3
1620 #define PALMAS_POLARITY_CTRL_GPIO_3_CHRG_DET_N_POLARITY         0x04
1621 #define PALMAS_POLARITY_CTRL_GPIO_3_CHRG_DET_N_POLARITY_SHIFT   2
1622 #define PALMAS_POLARITY_CTRL_POWERGOOD_USB_PSEL_POLARITY        0x02
1623 #define PALMAS_POLARITY_CTRL_POWERGOOD_USB_PSEL_POLARITY_SHIFT  1
1624 #define PALMAS_POLARITY_CTRL_PWRDOWN_POLARITY                   0x01
1625 #define PALMAS_POLARITY_CTRL_PWRDOWN_POLARITY_SHIFT             0
1626
1627 /* Bit definitions for PRIMARY_SECONDARY_PAD1 */
1628 #define PALMAS_PRIMARY_SECONDARY_PAD1_GPIO_3                    0x80
1629 #define PALMAS_PRIMARY_SECONDARY_PAD1_GPIO_3_SHIFT              7
1630 #define PALMAS_PRIMARY_SECONDARY_PAD1_GPIO_2_MASK               0x60
1631 #define PALMAS_PRIMARY_SECONDARY_PAD1_GPIO_2_SHIFT              5
1632 #define PALMAS_PRIMARY_SECONDARY_PAD1_GPIO_1_MASK               0x18
1633 #define PALMAS_PRIMARY_SECONDARY_PAD1_GPIO_1_SHIFT              3
1634 #define PALMAS_PRIMARY_SECONDARY_PAD1_GPIO_0                    0x04
1635 #define PALMAS_PRIMARY_SECONDARY_PAD1_GPIO_0_SHIFT              2
1636 #define PALMAS_PRIMARY_SECONDARY_PAD1_VAC                       0x02
1637 #define PALMAS_PRIMARY_SECONDARY_PAD1_VAC_SHIFT                 1
1638 #define PALMAS_PRIMARY_SECONDARY_PAD1_POWERGOOD                 0x01
1639 #define PALMAS_PRIMARY_SECONDARY_PAD1_POWERGOOD_SHIFT           0
1640
1641 /* Bit definitions for PRIMARY_SECONDARY_PAD2 */
1642 #define PALMAS_PRIMARY_SECONDARY_PAD2_GPIO_7_MASK               0x30
1643 #define PALMAS_PRIMARY_SECONDARY_PAD2_GPIO_7_SHIFT              4
1644 #define PALMAS_PRIMARY_SECONDARY_PAD2_GPIO_6                    0x08
1645 #define PALMAS_PRIMARY_SECONDARY_PAD2_GPIO_6_SHIFT              3
1646 #define PALMAS_PRIMARY_SECONDARY_PAD2_GPIO_5_MASK               0x06
1647 #define PALMAS_PRIMARY_SECONDARY_PAD2_GPIO_5_SHIFT              1
1648 #define PALMAS_PRIMARY_SECONDARY_PAD2_GPIO_4                    0x01
1649 #define PALMAS_PRIMARY_SECONDARY_PAD2_GPIO_4_SHIFT              0
1650
1651 /* Bit definitions for I2C_SPI */
1652 #define PALMAS_I2C_SPI_I2C2OTP_EN                               0x80
1653 #define PALMAS_I2C_SPI_I2C2OTP_EN_SHIFT                         7
1654 #define PALMAS_I2C_SPI_I2C2OTP_PAGESEL                          0x40
1655 #define PALMAS_I2C_SPI_I2C2OTP_PAGESEL_SHIFT                    6
1656 #define PALMAS_I2C_SPI_ID_I2C2                                  0x20
1657 #define PALMAS_I2C_SPI_ID_I2C2_SHIFT                            5
1658 #define PALMAS_I2C_SPI_I2C_SPI                                  0x10
1659 #define PALMAS_I2C_SPI_I2C_SPI_SHIFT                            4
1660 #define PALMAS_I2C_SPI_ID_I2C1_MASK                             0x0f
1661 #define PALMAS_I2C_SPI_ID_I2C1_SHIFT                            0
1662
1663 /* Bit definitions for PU_PD_INPUT_CTRL4 */
1664 #define PALMAS_PU_PD_INPUT_CTRL4_DVFS2_DAT_PD                   0x40
1665 #define PALMAS_PU_PD_INPUT_CTRL4_DVFS2_DAT_PD_SHIFT             6
1666 #define PALMAS_PU_PD_INPUT_CTRL4_DVFS2_CLK_PD                   0x10
1667 #define PALMAS_PU_PD_INPUT_CTRL4_DVFS2_CLK_PD_SHIFT             4
1668 #define PALMAS_PU_PD_INPUT_CTRL4_DVFS1_DAT_PD                   0x04
1669 #define PALMAS_PU_PD_INPUT_CTRL4_DVFS1_DAT_PD_SHIFT             2
1670 #define PALMAS_PU_PD_INPUT_CTRL4_DVFS1_CLK_PD                   0x01
1671 #define PALMAS_PU_PD_INPUT_CTRL4_DVFS1_CLK_PD_SHIFT             0
1672
1673 /* Bit definitions for PRIMARY_SECONDARY_PAD3 */
1674 #define PALMAS_PRIMARY_SECONDARY_PAD3_DVFS2                     0x02
1675 #define PALMAS_PRIMARY_SECONDARY_PAD3_DVFS2_SHIFT               1
1676 #define PALMAS_PRIMARY_SECONDARY_PAD3_DVFS1                     0x01
1677 #define PALMAS_PRIMARY_SECONDARY_PAD3_DVFS1_SHIFT               0
1678
1679 /* Registers for function LED_PWM */
1680 #define PALMAS_LED_PERIOD_CTRL                                  0x0
1681 #define PALMAS_LED_CTRL                                         0x1
1682 #define PALMAS_PWM_CTRL1                                        0x2
1683 #define PALMAS_PWM_CTRL2                                        0x3
1684
1685 /* Bit definitions for LED_PERIOD_CTRL */
1686 #define PALMAS_LED_PERIOD_CTRL_LED_2_PERIOD_MASK                0x38
1687 #define PALMAS_LED_PERIOD_CTRL_LED_2_PERIOD_SHIFT               3
1688 #define PALMAS_LED_PERIOD_CTRL_LED_1_PERIOD_MASK                0x07
1689 #define PALMAS_LED_PERIOD_CTRL_LED_1_PERIOD_SHIFT               0
1690
1691 /* Bit definitions for LED_CTRL */
1692 #define PALMAS_LED_CTRL_LED_2_SEQ                               0x20
1693 #define PALMAS_LED_CTRL_LED_2_SEQ_SHIFT                         5
1694 #define PALMAS_LED_CTRL_LED_1_SEQ                               0x10
1695 #define PALMAS_LED_CTRL_LED_1_SEQ_SHIFT                         4
1696 #define PALMAS_LED_CTRL_LED_2_ON_TIME_MASK                      0x0c
1697 #define PALMAS_LED_CTRL_LED_2_ON_TIME_SHIFT                     2
1698 #define PALMAS_LED_CTRL_LED_1_ON_TIME_MASK                      0x03
1699 #define PALMAS_LED_CTRL_LED_1_ON_TIME_SHIFT                     0
1700
1701 /* Bit definitions for PWM_CTRL1 */
1702 #define PALMAS_PWM_CTRL1_PWM_FREQ_EN                            0x02
1703 #define PALMAS_PWM_CTRL1_PWM_FREQ_EN_SHIFT                      1
1704 #define PALMAS_PWM_CTRL1_PWM_FREQ_SEL                           0x01
1705 #define PALMAS_PWM_CTRL1_PWM_FREQ_SEL_SHIFT                     0
1706
1707 /* Bit definitions for PWM_CTRL2 */
1708 #define PALMAS_PWM_CTRL2_PWM_DUTY_SEL_MASK                      0xff
1709 #define PALMAS_PWM_CTRL2_PWM_DUTY_SEL_SHIFT                     0
1710
1711 /* Registers for function INTERRUPT */
1712 #define PALMAS_INT1_STATUS                                      0x0
1713 #define PALMAS_INT1_MASK                                        0x1
1714 #define PALMAS_INT1_LINE_STATE                                  0x2
1715 #define PALMAS_INT1_EDGE_DETECT1_RESERVED                       0x3
1716 #define PALMAS_INT1_EDGE_DETECT2_RESERVED                       0x4
1717 #define PALMAS_INT2_STATUS                                      0x5
1718 #define PALMAS_INT2_MASK                                        0x6
1719 #define PALMAS_INT2_LINE_STATE                                  0x7
1720 #define PALMAS_INT2_EDGE_DETECT1_RESERVED                       0x8
1721 #define PALMAS_INT2_EDGE_DETECT2_RESERVED                       0x9
1722 #define PALMAS_INT3_STATUS                                      0xA
1723 #define PALMAS_INT3_MASK                                        0xB
1724 #define PALMAS_INT3_LINE_STATE                                  0xC
1725 #define PALMAS_INT3_EDGE_DETECT1_RESERVED                       0xD
1726 #define PALMAS_INT3_EDGE_DETECT2_RESERVED                       0xE
1727 #define PALMAS_INT4_STATUS                                      0xF
1728 #define PALMAS_INT4_MASK                                        0x10
1729 #define PALMAS_INT4_LINE_STATE                                  0x11
1730 #define PALMAS_INT4_EDGE_DETECT1                                0x12
1731 #define PALMAS_INT4_EDGE_DETECT2                                0x13
1732 #define PALMAS_INT_CTRL                                         0x14
1733
1734 /* Bit definitions for INT1_STATUS */
1735 #define PALMAS_INT1_STATUS_VBAT_MON                             0x80
1736 #define PALMAS_INT1_STATUS_VBAT_MON_SHIFT                       7
1737 #define PALMAS_INT1_STATUS_VSYS_MON                             0x40
1738 #define PALMAS_INT1_STATUS_VSYS_MON_SHIFT                       6
1739 #define PALMAS_INT1_STATUS_HOTDIE                               0x20
1740 #define PALMAS_INT1_STATUS_HOTDIE_SHIFT                         5
1741 #define PALMAS_INT1_STATUS_PWRDOWN                              0x10
1742 #define PALMAS_INT1_STATUS_PWRDOWN_SHIFT                        4
1743 #define PALMAS_INT1_STATUS_RPWRON                               0x08
1744 #define PALMAS_INT1_STATUS_RPWRON_SHIFT                         3
1745 #define PALMAS_INT1_STATUS_LONG_PRESS_KEY                       0x04
1746 #define PALMAS_INT1_STATUS_LONG_PRESS_KEY_SHIFT                 2
1747 #define PALMAS_INT1_STATUS_PWRON                                0x02
1748 #define PALMAS_INT1_STATUS_PWRON_SHIFT                          1
1749 #define PALMAS_INT1_STATUS_CHARG_DET_N_VBUS_OVV                 0x01
1750 #define PALMAS_INT1_STATUS_CHARG_DET_N_VBUS_OVV_SHIFT           0
1751
1752 /* Bit definitions for INT1_MASK */
1753 #define PALMAS_INT1_MASK_VBAT_MON                               0x80
1754 #define PALMAS_INT1_MASK_VBAT_MON_SHIFT                         7
1755 #define PALMAS_INT1_MASK_VSYS_MON                               0x40
1756 #define PALMAS_INT1_MASK_VSYS_MON_SHIFT                         6
1757 #define PALMAS_INT1_MASK_HOTDIE                                 0x20
1758 #define PALMAS_INT1_MASK_HOTDIE_SHIFT                           5
1759 #define PALMAS_INT1_MASK_PWRDOWN                                0x10
1760 #define PALMAS_INT1_MASK_PWRDOWN_SHIFT                          4
1761 #define PALMAS_INT1_MASK_RPWRON                                 0x08
1762 #define PALMAS_INT1_MASK_RPWRON_SHIFT                           3
1763 #define PALMAS_INT1_MASK_LONG_PRESS_KEY                         0x04
1764 #define PALMAS_INT1_MASK_LONG_PRESS_KEY_SHIFT                   2
1765 #define PALMAS_INT1_MASK_PWRON                                  0x02
1766 #define PALMAS_INT1_MASK_PWRON_SHIFT                            1
1767 #define PALMAS_INT1_MASK_CHARG_DET_N_VBUS_OVV                   0x01
1768 #define PALMAS_INT1_MASK_CHARG_DET_N_VBUS_OVV_SHIFT             0
1769
1770 /* Bit definitions for INT1_LINE_STATE */
1771 #define PALMAS_INT1_LINE_STATE_VBAT_MON                         0x80
1772 #define PALMAS_INT1_LINE_STATE_VBAT_MON_SHIFT                   7
1773 #define PALMAS_INT1_LINE_STATE_VSYS_MON                         0x40
1774 #define PALMAS_INT1_LINE_STATE_VSYS_MON_SHIFT                   6
1775 #define PALMAS_INT1_LINE_STATE_HOTDIE                           0x20
1776 #define PALMAS_INT1_LINE_STATE_HOTDIE_SHIFT                     5
1777 #define PALMAS_INT1_LINE_STATE_PWRDOWN                          0x10
1778 #define PALMAS_INT1_LINE_STATE_PWRDOWN_SHIFT                    4
1779 #define PALMAS_INT1_LINE_STATE_RPWRON                           0x08
1780 #define PALMAS_INT1_LINE_STATE_RPWRON_SHIFT                     3
1781 #define PALMAS_INT1_LINE_STATE_LONG_PRESS_KEY                   0x04
1782 #define PALMAS_INT1_LINE_STATE_LONG_PRESS_KEY_SHIFT             2
1783 #define PALMAS_INT1_LINE_STATE_PWRON                            0x02
1784 #define PALMAS_INT1_LINE_STATE_PWRON_SHIFT                      1
1785 #define PALMAS_INT1_LINE_STATE_CHARG_DET_N_VBUS_OVV             0x01
1786 #define PALMAS_INT1_LINE_STATE_CHARG_DET_N_VBUS_OVV_SHIFT       0
1787
1788 /* Bit definitions for INT2_STATUS */
1789 #define PALMAS_INT2_STATUS_VAC_ACOK                             0x80
1790 #define PALMAS_INT2_STATUS_VAC_ACOK_SHIFT                       7
1791 #define PALMAS_INT2_STATUS_SHORT                                0x40
1792 #define PALMAS_INT2_STATUS_SHORT_SHIFT                          6
1793 #define PALMAS_INT2_STATUS_FBI_BB                               0x20
1794 #define PALMAS_INT2_STATUS_FBI_BB_SHIFT                         5
1795 #define PALMAS_INT2_STATUS_RESET_IN                             0x10
1796 #define PALMAS_INT2_STATUS_RESET_IN_SHIFT                       4
1797 #define PALMAS_INT2_STATUS_BATREMOVAL                           0x08
1798 #define PALMAS_INT2_STATUS_BATREMOVAL_SHIFT                     3
1799 #define PALMAS_INT2_STATUS_WDT                                  0x04
1800 #define PALMAS_INT2_STATUS_WDT_SHIFT                            2
1801 #define PALMAS_INT2_STATUS_RTC_TIMER                            0x02
1802 #define PALMAS_INT2_STATUS_RTC_TIMER_SHIFT                      1
1803 #define PALMAS_INT2_STATUS_RTC_ALARM                            0x01
1804 #define PALMAS_INT2_STATUS_RTC_ALARM_SHIFT                      0
1805
1806 /* Bit definitions for INT2_MASK */
1807 #define PALMAS_INT2_MASK_VAC_ACOK                               0x80
1808 #define PALMAS_INT2_MASK_VAC_ACOK_SHIFT                         7
1809 #define PALMAS_INT2_MASK_SHORT                                  0x40
1810 #define PALMAS_INT2_MASK_SHORT_SHIFT                            6
1811 #define PALMAS_INT2_MASK_FBI_BB                                 0x20
1812 #define PALMAS_INT2_MASK_FBI_BB_SHIFT                           5
1813 #define PALMAS_INT2_MASK_RESET_IN                               0x10
1814 #define PALMAS_INT2_MASK_RESET_IN_SHIFT                         4
1815 #define PALMAS_INT2_MASK_BATREMOVAL                             0x08
1816 #define PALMAS_INT2_MASK_BATREMOVAL_SHIFT                       3
1817 #define PALMAS_INT2_MASK_WDT                                    0x04
1818 #define PALMAS_INT2_MASK_WDT_SHIFT                              2
1819 #define PALMAS_INT2_MASK_RTC_TIMER                              0x02
1820 #define PALMAS_INT2_MASK_RTC_TIMER_SHIFT                        1
1821 #define PALMAS_INT2_MASK_RTC_ALARM                              0x01
1822 #define PALMAS_INT2_MASK_RTC_ALARM_SHIFT                        0
1823
1824 /* Bit definitions for INT2_LINE_STATE */
1825 #define PALMAS_INT2_LINE_STATE_VAC_ACOK                         0x80
1826 #define PALMAS_INT2_LINE_STATE_VAC_ACOK_SHIFT                   7
1827 #define PALMAS_INT2_LINE_STATE_SHORT                            0x40
1828 #define PALMAS_INT2_LINE_STATE_SHORT_SHIFT                      6
1829 #define PALMAS_INT2_LINE_STATE_FBI_BB                           0x20
1830 #define PALMAS_INT2_LINE_STATE_FBI_BB_SHIFT                     5
1831 #define PALMAS_INT2_LINE_STATE_RESET_IN                         0x10
1832 #define PALMAS_INT2_LINE_STATE_RESET_IN_SHIFT                   4
1833 #define PALMAS_INT2_LINE_STATE_BATREMOVAL                       0x08
1834 #define PALMAS_INT2_LINE_STATE_BATREMOVAL_SHIFT                 3
1835 #define PALMAS_INT2_LINE_STATE_WDT                              0x04
1836 #define PALMAS_INT2_LINE_STATE_WDT_SHIFT                        2
1837 #define PALMAS_INT2_LINE_STATE_RTC_TIMER                        0x02
1838 #define PALMAS_INT2_LINE_STATE_RTC_TIMER_SHIFT                  1
1839 #define PALMAS_INT2_LINE_STATE_RTC_ALARM                        0x01
1840 #define PALMAS_INT2_LINE_STATE_RTC_ALARM_SHIFT                  0
1841
1842 /* Bit definitions for INT3_STATUS */
1843 #define PALMAS_INT3_STATUS_VBUS                                 0x80
1844 #define PALMAS_INT3_STATUS_VBUS_SHIFT                           7
1845 #define PALMAS_INT3_STATUS_VBUS_OTG                             0x40
1846 #define PALMAS_INT3_STATUS_VBUS_OTG_SHIFT                       6
1847 #define PALMAS_INT3_STATUS_ID                                   0x20
1848 #define PALMAS_INT3_STATUS_ID_SHIFT                             5
1849 #define PALMAS_INT3_STATUS_ID_OTG                               0x10
1850 #define PALMAS_INT3_STATUS_ID_OTG_SHIFT                         4
1851 #define PALMAS_INT3_STATUS_GPADC_EOC_RT                         0x08
1852 #define PALMAS_INT3_STATUS_GPADC_EOC_RT_SHIFT                   3
1853 #define PALMAS_INT3_STATUS_GPADC_EOC_SW                         0x04
1854 #define PALMAS_INT3_STATUS_GPADC_EOC_SW_SHIFT                   2
1855 #define PALMAS_INT3_STATUS_GPADC_AUTO_1                         0x02
1856 #define PALMAS_INT3_STATUS_GPADC_AUTO_1_SHIFT                   1
1857 #define PALMAS_INT3_STATUS_GPADC_AUTO_0                         0x01
1858 #define PALMAS_INT3_STATUS_GPADC_AUTO_0_SHIFT                   0
1859
1860 /* Bit definitions for INT3_MASK */
1861 #define PALMAS_INT3_MASK_VBUS                                   0x80
1862 #define PALMAS_INT3_MASK_VBUS_SHIFT                             7
1863 #define PALMAS_INT3_MASK_VBUS_OTG                               0x40
1864 #define PALMAS_INT3_MASK_VBUS_OTG_SHIFT                         6
1865 #define PALMAS_INT3_MASK_ID                                     0x20
1866 #define PALMAS_INT3_MASK_ID_SHIFT                               5
1867 #define PALMAS_INT3_MASK_ID_OTG                                 0x10
1868 #define PALMAS_INT3_MASK_ID_OTG_SHIFT                           4
1869 #define PALMAS_INT3_MASK_GPADC_EOC_RT                           0x08
1870 #define PALMAS_INT3_MASK_GPADC_EOC_RT_SHIFT                     3
1871 #define PALMAS_INT3_MASK_GPADC_EOC_SW                           0x04
1872 #define PALMAS_INT3_MASK_GPADC_EOC_SW_SHIFT                     2
1873 #define PALMAS_INT3_MASK_GPADC_AUTO_1                           0x02
1874 #define PALMAS_INT3_MASK_GPADC_AUTO_1_SHIFT                     1
1875 #define PALMAS_INT3_MASK_GPADC_AUTO_0                           0x01
1876 #define PALMAS_INT3_MASK_GPADC_AUTO_0_SHIFT                     0
1877
1878 /* Bit definitions for INT3_LINE_STATE */
1879 #define PALMAS_INT3_LINE_STATE_VBUS                             0x80
1880 #define PALMAS_INT3_LINE_STATE_VBUS_SHIFT                       7
1881 #define PALMAS_INT3_LINE_STATE_VBUS_OTG                         0x40
1882 #define PALMAS_INT3_LINE_STATE_VBUS_OTG_SHIFT                   6
1883 #define PALMAS_INT3_LINE_STATE_ID                               0x20
1884 #define PALMAS_INT3_LINE_STATE_ID_SHIFT                         5
1885 #define PALMAS_INT3_LINE_STATE_ID_OTG                           0x10
1886 #define PALMAS_INT3_LINE_STATE_ID_OTG_SHIFT                     4
1887 #define PALMAS_INT3_LINE_STATE_GPADC_EOC_RT                     0x08
1888 #define PALMAS_INT3_LINE_STATE_GPADC_EOC_RT_SHIFT               3
1889 #define PALMAS_INT3_LINE_STATE_GPADC_EOC_SW                     0x04
1890 #define PALMAS_INT3_LINE_STATE_GPADC_EOC_SW_SHIFT               2
1891 #define PALMAS_INT3_LINE_STATE_GPADC_AUTO_1                     0x02
1892 #define PALMAS_INT3_LINE_STATE_GPADC_AUTO_1_SHIFT               1
1893 #define PALMAS_INT3_LINE_STATE_GPADC_AUTO_0                     0x01
1894 #define PALMAS_INT3_LINE_STATE_GPADC_AUTO_0_SHIFT               0
1895
1896 /* Bit definitions for INT4_STATUS */
1897 #define PALMAS_INT4_STATUS_GPIO_7                               0x80
1898 #define PALMAS_INT4_STATUS_GPIO_7_SHIFT                         7
1899 #define PALMAS_INT4_STATUS_GPIO_6                               0x40
1900 #define PALMAS_INT4_STATUS_GPIO_6_SHIFT                         6
1901 #define PALMAS_INT4_STATUS_GPIO_5                               0x20
1902 #define PALMAS_INT4_STATUS_GPIO_5_SHIFT                         5
1903 #define PALMAS_INT4_STATUS_GPIO_4                               0x10
1904 #define PALMAS_INT4_STATUS_GPIO_4_SHIFT                         4
1905 #define PALMAS_INT4_STATUS_GPIO_3                               0x08
1906 #define PALMAS_INT4_STATUS_GPIO_3_SHIFT                         3
1907 #define PALMAS_INT4_STATUS_GPIO_2                               0x04
1908 #define PALMAS_INT4_STATUS_GPIO_2_SHIFT                         2
1909 #define PALMAS_INT4_STATUS_GPIO_1                               0x02
1910 #define PALMAS_INT4_STATUS_GPIO_1_SHIFT                         1
1911 #define PALMAS_INT4_STATUS_GPIO_0                               0x01
1912 #define PALMAS_INT4_STATUS_GPIO_0_SHIFT                         0
1913
1914 /* Bit definitions for INT4_MASK */
1915 #define PALMAS_INT4_MASK_GPIO_7                                 0x80
1916 #define PALMAS_INT4_MASK_GPIO_7_SHIFT                           7
1917 #define PALMAS_INT4_MASK_GPIO_6                                 0x40
1918 #define PALMAS_INT4_MASK_GPIO_6_SHIFT                           6
1919 #define PALMAS_INT4_MASK_GPIO_5                                 0x20
1920 #define PALMAS_INT4_MASK_GPIO_5_SHIFT                           5
1921 #define PALMAS_INT4_MASK_GPIO_4                                 0x10
1922 #define PALMAS_INT4_MASK_GPIO_4_SHIFT                           4
1923 #define PALMAS_INT4_MASK_GPIO_3                                 0x08
1924 #define PALMAS_INT4_MASK_GPIO_3_SHIFT                           3
1925 #define PALMAS_INT4_MASK_GPIO_2                                 0x04
1926 #define PALMAS_INT4_MASK_GPIO_2_SHIFT                           2
1927 #define PALMAS_INT4_MASK_GPIO_1                                 0x02
1928 #define PALMAS_INT4_MASK_GPIO_1_SHIFT                           1
1929 #define PALMAS_INT4_MASK_GPIO_0                                 0x01
1930 #define PALMAS_INT4_MASK_GPIO_0_SHIFT                           0
1931
1932 /* Bit definitions for INT4_LINE_STATE */
1933 #define PALMAS_INT4_LINE_STATE_GPIO_7                           0x80
1934 #define PALMAS_INT4_LINE_STATE_GPIO_7_SHIFT                     7
1935 #define PALMAS_INT4_LINE_STATE_GPIO_6                           0x40
1936 #define PALMAS_INT4_LINE_STATE_GPIO_6_SHIFT                     6
1937 #define PALMAS_INT4_LINE_STATE_GPIO_5                           0x20
1938 #define PALMAS_INT4_LINE_STATE_GPIO_5_SHIFT                     5
1939 #define PALMAS_INT4_LINE_STATE_GPIO_4                           0x10
1940 #define PALMAS_INT4_LINE_STATE_GPIO_4_SHIFT                     4
1941 #define PALMAS_INT4_LINE_STATE_GPIO_3                           0x08
1942 #define PALMAS_INT4_LINE_STATE_GPIO_3_SHIFT                     3
1943 #define PALMAS_INT4_LINE_STATE_GPIO_2                           0x04
1944 #define PALMAS_INT4_LINE_STATE_GPIO_2_SHIFT                     2
1945 #define PALMAS_INT4_LINE_STATE_GPIO_1                           0x02
1946 #define PALMAS_INT4_LINE_STATE_GPIO_1_SHIFT                     1
1947 #define PALMAS_INT4_LINE_STATE_GPIO_0                           0x01
1948 #define PALMAS_INT4_LINE_STATE_GPIO_0_SHIFT                     0
1949
1950 /* Bit definitions for INT4_EDGE_DETECT1 */
1951 #define PALMAS_INT4_EDGE_DETECT1_GPIO_3_RISING                  0x80
1952 #define PALMAS_INT4_EDGE_DETECT1_GPIO_3_RISING_SHIFT            7
1953 #define PALMAS_INT4_EDGE_DETECT1_GPIO_3_FALLING                 0x40
1954 #define PALMAS_INT4_EDGE_DETECT1_GPIO_3_FALLING_SHIFT           6
1955 #define PALMAS_INT4_EDGE_DETECT1_GPIO_2_RISING                  0x20
1956 #define PALMAS_INT4_EDGE_DETECT1_GPIO_2_RISING_SHIFT            5
1957 #define PALMAS_INT4_EDGE_DETECT1_GPIO_2_FALLING                 0x10
1958 #define PALMAS_INT4_EDGE_DETECT1_GPIO_2_FALLING_SHIFT           4
1959 #define PALMAS_INT4_EDGE_DETECT1_GPIO_1_RISING                  0x08
1960 #define PALMAS_INT4_EDGE_DETECT1_GPIO_1_RISING_SHIFT            3
1961 #define PALMAS_INT4_EDGE_DETECT1_GPIO_1_FALLING                 0x04
1962 #define PALMAS_INT4_EDGE_DETECT1_GPIO_1_FALLING_SHIFT           2
1963 #define PALMAS_INT4_EDGE_DETECT1_GPIO_0_RISING                  0x02
1964 #define PALMAS_INT4_EDGE_DETECT1_GPIO_0_RISING_SHIFT            1
1965 #define PALMAS_INT4_EDGE_DETECT1_GPIO_0_FALLING                 0x01
1966 #define PALMAS_INT4_EDGE_DETECT1_GPIO_0_FALLING_SHIFT           0
1967
1968 /* Bit definitions for INT4_EDGE_DETECT2 */
1969 #define PALMAS_INT4_EDGE_DETECT2_GPIO_7_RISING                  0x80
1970 #define PALMAS_INT4_EDGE_DETECT2_GPIO_7_RISING_SHIFT            7
1971 #define PALMAS_INT4_EDGE_DETECT2_GPIO_7_FALLING                 0x40
1972 #define PALMAS_INT4_EDGE_DETECT2_GPIO_7_FALLING_SHIFT           6
1973 #define PALMAS_INT4_EDGE_DETECT2_GPIO_6_RISING                  0x20
1974 #define PALMAS_INT4_EDGE_DETECT2_GPIO_6_RISING_SHIFT            5
1975 #define PALMAS_INT4_EDGE_DETECT2_GPIO_6_FALLING                 0x10
1976 #define PALMAS_INT4_EDGE_DETECT2_GPIO_6_FALLING_SHIFT           4
1977 #define PALMAS_INT4_EDGE_DETECT2_GPIO_5_RISING                  0x08
1978 #define PALMAS_INT4_EDGE_DETECT2_GPIO_5_RISING_SHIFT            3
1979 #define PALMAS_INT4_EDGE_DETECT2_GPIO_5_FALLING                 0x04
1980 #define PALMAS_INT4_EDGE_DETECT2_GPIO_5_FALLING_SHIFT           2
1981 #define PALMAS_INT4_EDGE_DETECT2_GPIO_4_RISING                  0x02
1982 #define PALMAS_INT4_EDGE_DETECT2_GPIO_4_RISING_SHIFT            1
1983 #define PALMAS_INT4_EDGE_DETECT2_GPIO_4_FALLING                 0x01
1984 #define PALMAS_INT4_EDGE_DETECT2_GPIO_4_FALLING_SHIFT           0
1985
1986 /* Bit definitions for INT_CTRL */
1987 #define PALMAS_INT_CTRL_INT_PENDING                             0x04
1988 #define PALMAS_INT_CTRL_INT_PENDING_SHIFT                       2
1989 #define PALMAS_INT_CTRL_INT_CLEAR                               0x01
1990 #define PALMAS_INT_CTRL_INT_CLEAR_SHIFT                         0
1991
1992 /* Registers for function USB_OTG */
1993 #define PALMAS_USB_WAKEUP                                       0x3
1994 #define PALMAS_USB_VBUS_CTRL_SET                                0x4
1995 #define PALMAS_USB_VBUS_CTRL_CLR                                0x5
1996 #define PALMAS_USB_ID_CTRL_SET                                  0x6
1997 #define PALMAS_USB_ID_CTRL_CLEAR                                0x7
1998 #define PALMAS_USB_VBUS_INT_SRC                                 0x8
1999 #define PALMAS_USB_VBUS_INT_LATCH_SET                           0x9
2000 #define PALMAS_USB_VBUS_INT_LATCH_CLR                           0xA
2001 #define PALMAS_USB_VBUS_INT_EN_LO_SET                           0xB
2002 #define PALMAS_USB_VBUS_INT_EN_LO_CLR                           0xC
2003 #define PALMAS_USB_VBUS_INT_EN_HI_SET                           0xD
2004 #define PALMAS_USB_VBUS_INT_EN_HI_CLR                           0xE
2005 #define PALMAS_USB_ID_INT_SRC                                   0xF
2006 #define PALMAS_USB_ID_INT_LATCH_SET                             0x10
2007 #define PALMAS_USB_ID_INT_LATCH_CLR                             0x11
2008 #define PALMAS_USB_ID_INT_EN_LO_SET                             0x12
2009 #define PALMAS_USB_ID_INT_EN_LO_CLR                             0x13
2010 #define PALMAS_USB_ID_INT_EN_HI_SET                             0x14
2011 #define PALMAS_USB_ID_INT_EN_HI_CLR                             0x15
2012 #define PALMAS_USB_OTG_ADP_CTRL                                 0x16
2013 #define PALMAS_USB_OTG_ADP_HIGH                                 0x17
2014 #define PALMAS_USB_OTG_ADP_LOW                                  0x18
2015 #define PALMAS_USB_OTG_ADP_RISE                                 0x19
2016 #define PALMAS_USB_OTG_REVISION                                 0x1A
2017
2018 /* Bit definitions for USB_WAKEUP */
2019 #define PALMAS_USB_WAKEUP_ID_WK_UP_COMP                         0x01
2020 #define PALMAS_USB_WAKEUP_ID_WK_UP_COMP_SHIFT                   0
2021
2022 /* Bit definitions for USB_VBUS_CTRL_SET */
2023 #define PALMAS_USB_VBUS_CTRL_SET_VBUS_CHRG_VSYS                 0x80
2024 #define PALMAS_USB_VBUS_CTRL_SET_VBUS_CHRG_VSYS_SHIFT           7
2025 #define PALMAS_USB_VBUS_CTRL_SET_VBUS_DISCHRG                   0x20
2026 #define PALMAS_USB_VBUS_CTRL_SET_VBUS_DISCHRG_SHIFT             5
2027 #define PALMAS_USB_VBUS_CTRL_SET_VBUS_IADP_SRC                  0x10
2028 #define PALMAS_USB_VBUS_CTRL_SET_VBUS_IADP_SRC_SHIFT            4
2029 #define PALMAS_USB_VBUS_CTRL_SET_VBUS_IADP_SINK                 0x08
2030 #define PALMAS_USB_VBUS_CTRL_SET_VBUS_IADP_SINK_SHIFT           3
2031 #define PALMAS_USB_VBUS_CTRL_SET_VBUS_ACT_COMP                  0x04
2032 #define PALMAS_USB_VBUS_CTRL_SET_VBUS_ACT_COMP_SHIFT            2
2033
2034 /* Bit definitions for USB_VBUS_CTRL_CLR */
2035 #define PALMAS_USB_VBUS_CTRL_CLR_VBUS_CHRG_VSYS                 0x80
2036 #define PALMAS_USB_VBUS_CTRL_CLR_VBUS_CHRG_VSYS_SHIFT           7
2037 #define PALMAS_USB_VBUS_CTRL_CLR_VBUS_DISCHRG                   0x20
2038 #define PALMAS_USB_VBUS_CTRL_CLR_VBUS_DISCHRG_SHIFT             5
2039 #define PALMAS_USB_VBUS_CTRL_CLR_VBUS_IADP_SRC                  0x10
2040 #define PALMAS_USB_VBUS_CTRL_CLR_VBUS_IADP_SRC_SHIFT            4
2041 #define PALMAS_USB_VBUS_CTRL_CLR_VBUS_IADP_SINK                 0x08
2042 #define PALMAS_USB_VBUS_CTRL_CLR_VBUS_IADP_SINK_SHIFT           3
2043 #define PALMAS_USB_VBUS_CTRL_CLR_VBUS_ACT_COMP                  0x04
2044 #define PALMAS_USB_VBUS_CTRL_CLR_VBUS_ACT_COMP_SHIFT            2
2045
2046 /* Bit definitions for USB_ID_CTRL_SET */
2047 #define PALMAS_USB_ID_CTRL_SET_ID_PU_220K                       0x80
2048 #define PALMAS_USB_ID_CTRL_SET_ID_PU_220K_SHIFT                 7
2049 #define PALMAS_USB_ID_CTRL_SET_ID_PU_100K                       0x40
2050 #define PALMAS_USB_ID_CTRL_SET_ID_PU_100K_SHIFT                 6
2051 #define PALMAS_USB_ID_CTRL_SET_ID_GND_DRV                       0x20
2052 #define PALMAS_USB_ID_CTRL_SET_ID_GND_DRV_SHIFT                 5
2053 #define PALMAS_USB_ID_CTRL_SET_ID_SRC_16U                       0x10
2054 #define PALMAS_USB_ID_CTRL_SET_ID_SRC_16U_SHIFT                 4
2055 #define PALMAS_USB_ID_CTRL_SET_ID_SRC_5U                        0x08
2056 #define PALMAS_USB_ID_CTRL_SET_ID_SRC_5U_SHIFT                  3
2057 #define PALMAS_USB_ID_CTRL_SET_ID_ACT_COMP                      0x04
2058 #define PALMAS_USB_ID_CTRL_SET_ID_ACT_COMP_SHIFT                2
2059
2060 /* Bit definitions for USB_ID_CTRL_CLEAR */
2061 #define PALMAS_USB_ID_CTRL_CLEAR_ID_PU_220K                     0x80
2062 #define PALMAS_USB_ID_CTRL_CLEAR_ID_PU_220K_SHIFT               7
2063 #define PALMAS_USB_ID_CTRL_CLEAR_ID_PU_100K                     0x40
2064 #define PALMAS_USB_ID_CTRL_CLEAR_ID_PU_100K_SHIFT               6
2065 #define PALMAS_USB_ID_CTRL_CLEAR_ID_GND_DRV                     0x20
2066 #define PALMAS_USB_ID_CTRL_CLEAR_ID_GND_DRV_SHIFT               5
2067 #define PALMAS_USB_ID_CTRL_CLEAR_ID_SRC_16U                     0x10
2068 #define PALMAS_USB_ID_CTRL_CLEAR_ID_SRC_16U_SHIFT               4
2069 #define PALMAS_USB_ID_CTRL_CLEAR_ID_SRC_5U                      0x08
2070 #define PALMAS_USB_ID_CTRL_CLEAR_ID_SRC_5U_SHIFT                3
2071 #define PALMAS_USB_ID_CTRL_CLEAR_ID_ACT_COMP                    0x04
2072 #define PALMAS_USB_ID_CTRL_CLEAR_ID_ACT_COMP_SHIFT              2
2073
2074 /* Bit definitions for USB_VBUS_INT_SRC */
2075 #define PALMAS_USB_VBUS_INT_SRC_VOTG_SESS_VLD                   0x80
2076 #define PALMAS_USB_VBUS_INT_SRC_VOTG_SESS_VLD_SHIFT             7
2077 #define PALMAS_USB_VBUS_INT_SRC_VADP_PRB                        0x40
2078 #define PALMAS_USB_VBUS_INT_SRC_VADP_PRB_SHIFT                  6
2079 #define PALMAS_USB_VBUS_INT_SRC_VADP_SNS                        0x20
2080 #define PALMAS_USB_VBUS_INT_SRC_VADP_SNS_SHIFT                  5
2081 #define PALMAS_USB_VBUS_INT_SRC_VA_VBUS_VLD                     0x08
2082 #define PALMAS_USB_VBUS_INT_SRC_VA_VBUS_VLD_SHIFT               3
2083 #define PALMAS_USB_VBUS_INT_SRC_VA_SESS_VLD                     0x04
2084 #define PALMAS_USB_VBUS_INT_SRC_VA_SESS_VLD_SHIFT               2
2085 #define PALMAS_USB_VBUS_INT_SRC_VB_SESS_VLD                     0x02
2086 #define PALMAS_USB_VBUS_INT_SRC_VB_SESS_VLD_SHIFT               1
2087 #define PALMAS_USB_VBUS_INT_SRC_VB_SESS_END                     0x01
2088 #define PALMAS_USB_VBUS_INT_SRC_VB_SESS_END_SHIFT               0
2089
2090 /* Bit definitions for USB_VBUS_INT_LATCH_SET */
2091 #define PALMAS_USB_VBUS_INT_LATCH_SET_VOTG_SESS_VLD             0x80
2092 #define PALMAS_USB_VBUS_INT_LATCH_SET_VOTG_SESS_VLD_SHIFT       7
2093 #define PALMAS_USB_VBUS_INT_LATCH_SET_VADP_PRB                  0x40
2094 #define PALMAS_USB_VBUS_INT_LATCH_SET_VADP_PRB_SHIFT            6
2095 #define PALMAS_USB_VBUS_INT_LATCH_SET_VADP_SNS                  0x20
2096 #define PALMAS_USB_VBUS_INT_LATCH_SET_VADP_SNS_SHIFT            5
2097 #define PALMAS_USB_VBUS_INT_LATCH_SET_ADP                       0x10
2098 #define PALMAS_USB_VBUS_INT_LATCH_SET_ADP_SHIFT                 4
2099 #define PALMAS_USB_VBUS_INT_LATCH_SET_VA_VBUS_VLD               0x08
2100 #define PALMAS_USB_VBUS_INT_LATCH_SET_VA_VBUS_VLD_SHIFT         3
2101 #define PALMAS_USB_VBUS_INT_LATCH_SET_VA_SESS_VLD               0x04
2102 #define PALMAS_USB_VBUS_INT_LATCH_SET_VA_SESS_VLD_SHIFT         2
2103 #define PALMAS_USB_VBUS_INT_LATCH_SET_VB_SESS_VLD               0x02
2104 #define PALMAS_USB_VBUS_INT_LATCH_SET_VB_SESS_VLD_SHIFT         1
2105 #define PALMAS_USB_VBUS_INT_LATCH_SET_VB_SESS_END               0x01
2106 #define PALMAS_USB_VBUS_INT_LATCH_SET_VB_SESS_END_SHIFT         0
2107
2108 /* Bit definitions for USB_VBUS_INT_LATCH_CLR */
2109 #define PALMAS_USB_VBUS_INT_LATCH_CLR_VOTG_SESS_VLD             0x80
2110 #define PALMAS_USB_VBUS_INT_LATCH_CLR_VOTG_SESS_VLD_SHIFT       7
2111 #define PALMAS_USB_VBUS_INT_LATCH_CLR_VADP_PRB                  0x40
2112 #define PALMAS_USB_VBUS_INT_LATCH_CLR_VADP_PRB_SHIFT            6
2113 #define PALMAS_USB_VBUS_INT_LATCH_CLR_VADP_SNS                  0x20
2114 #define PALMAS_USB_VBUS_INT_LATCH_CLR_VADP_SNS_SHIFT            5
2115 #define PALMAS_USB_VBUS_INT_LATCH_CLR_ADP                       0x10
2116 #define PALMAS_USB_VBUS_INT_LATCH_CLR_ADP_SHIFT                 4
2117 #define PALMAS_USB_VBUS_INT_LATCH_CLR_VA_VBUS_VLD               0x08
2118 #define PALMAS_USB_VBUS_INT_LATCH_CLR_VA_VBUS_VLD_SHIFT         3
2119 #define PALMAS_USB_VBUS_INT_LATCH_CLR_VA_SESS_VLD               0x04
2120 #define PALMAS_USB_VBUS_INT_LATCH_CLR_VA_SESS_VLD_SHIFT         2
2121 #define PALMAS_USB_VBUS_INT_LATCH_CLR_VB_SESS_VLD               0x02
2122 #define PALMAS_USB_VBUS_INT_LATCH_CLR_VB_SESS_VLD_SHIFT         1
2123 #define PALMAS_USB_VBUS_INT_LATCH_CLR_VB_SESS_END               0x01
2124 #define PALMAS_USB_VBUS_INT_LATCH_CLR_VB_SESS_END_SHIFT         0
2125
2126 /* Bit definitions for USB_VBUS_INT_EN_LO_SET */
2127 #define PALMAS_USB_VBUS_INT_EN_LO_SET_VOTG_SESS_VLD             0x80
2128 #define PALMAS_USB_VBUS_INT_EN_LO_SET_VOTG_SESS_VLD_SHIFT       7
2129 #define PALMAS_USB_VBUS_INT_EN_LO_SET_VADP_PRB                  0x40
2130 #define PALMAS_USB_VBUS_INT_EN_LO_SET_VADP_PRB_SHIFT            6
2131 #define PALMAS_USB_VBUS_INT_EN_LO_SET_VADP_SNS                  0x20
2132 #define PALMAS_USB_VBUS_INT_EN_LO_SET_VADP_SNS_SHIFT            5
2133 #define PALMAS_USB_VBUS_INT_EN_LO_SET_VA_VBUS_VLD               0x08
2134 #define PALMAS_USB_VBUS_INT_EN_LO_SET_VA_VBUS_VLD_SHIFT         3
2135 #define PALMAS_USB_VBUS_INT_EN_LO_SET_VA_SESS_VLD               0x04
2136 #define PALMAS_USB_VBUS_INT_EN_LO_SET_VA_SESS_VLD_SHIFT         2
2137 #define PALMAS_USB_VBUS_INT_EN_LO_SET_VB_SESS_VLD               0x02
2138 #define PALMAS_USB_VBUS_INT_EN_LO_SET_VB_SESS_VLD_SHIFT         1
2139 #define PALMAS_USB_VBUS_INT_EN_LO_SET_VB_SESS_END               0x01
2140 #define PALMAS_USB_VBUS_INT_EN_LO_SET_VB_SESS_END_SHIFT         0
2141
2142 /* Bit definitions for USB_VBUS_INT_EN_LO_CLR */
2143 #define PALMAS_USB_VBUS_INT_EN_LO_CLR_VOTG_SESS_VLD             0x80
2144 #define PALMAS_USB_VBUS_INT_EN_LO_CLR_VOTG_SESS_VLD_SHIFT       7
2145 #define PALMAS_USB_VBUS_INT_EN_LO_CLR_VADP_PRB                  0x40
2146 #define PALMAS_USB_VBUS_INT_EN_LO_CLR_VADP_PRB_SHIFT            6
2147 #define PALMAS_USB_VBUS_INT_EN_LO_CLR_VADP_SNS                  0x20
2148 #define PALMAS_USB_VBUS_INT_EN_LO_CLR_VADP_SNS_SHIFT            5
2149 #define PALMAS_USB_VBUS_INT_EN_LO_CLR_VA_VBUS_VLD               0x08
2150 #define PALMAS_USB_VBUS_INT_EN_LO_CLR_VA_VBUS_VLD_SHIFT         3
2151 #define PALMAS_USB_VBUS_INT_EN_LO_CLR_VA_SESS_VLD               0x04
2152 #define PALMAS_USB_VBUS_INT_EN_LO_CLR_VA_SESS_VLD_SHIFT         2
2153 #define PALMAS_USB_VBUS_INT_EN_LO_CLR_VB_SESS_VLD               0x02
2154 #define PALMAS_USB_VBUS_INT_EN_LO_CLR_VB_SESS_VLD_SHIFT         1
2155 #define PALMAS_USB_VBUS_INT_EN_LO_CLR_VB_SESS_END               0x01
2156 #define PALMAS_USB_VBUS_INT_EN_LO_CLR_VB_SESS_END_SHIFT         0
2157
2158 /* Bit definitions for USB_VBUS_INT_EN_HI_SET */
2159 #define PALMAS_USB_VBUS_INT_EN_HI_SET_VOTG_SESS_VLD             0x80
2160 #define PALMAS_USB_VBUS_INT_EN_HI_SET_VOTG_SESS_VLD_SHIFT       7
2161 #define PALMAS_USB_VBUS_INT_EN_HI_SET_VADP_PRB                  0x40
2162 #define PALMAS_USB_VBUS_INT_EN_HI_SET_VADP_PRB_SHIFT            6
2163 #define PALMAS_USB_VBUS_INT_EN_HI_SET_VADP_SNS                  0x20
2164 #define PALMAS_USB_VBUS_INT_EN_HI_SET_VADP_SNS_SHIFT            5
2165 #define PALMAS_USB_VBUS_INT_EN_HI_SET_ADP                       0x10
2166 #define PALMAS_USB_VBUS_INT_EN_HI_SET_ADP_SHIFT                 4
2167 #define PALMAS_USB_VBUS_INT_EN_HI_SET_VA_VBUS_VLD               0x08
2168 #define PALMAS_USB_VBUS_INT_EN_HI_SET_VA_VBUS_VLD_SHIFT         3
2169 #define PALMAS_USB_VBUS_INT_EN_HI_SET_VA_SESS_VLD               0x04
2170 #define PALMAS_USB_VBUS_INT_EN_HI_SET_VA_SESS_VLD_SHIFT         2
2171 #define PALMAS_USB_VBUS_INT_EN_HI_SET_VB_SESS_VLD               0x02
2172 #define PALMAS_USB_VBUS_INT_EN_HI_SET_VB_SESS_VLD_SHIFT         1
2173 #define PALMAS_USB_VBUS_INT_EN_HI_SET_VB_SESS_END               0x01
2174 #define PALMAS_USB_VBUS_INT_EN_HI_SET_VB_SESS_END_SHIFT         0
2175
2176 /* Bit definitions for USB_VBUS_INT_EN_HI_CLR */
2177 #define PALMAS_USB_VBUS_INT_EN_HI_CLR_VOTG_SESS_VLD             0x80
2178 #define PALMAS_USB_VBUS_INT_EN_HI_CLR_VOTG_SESS_VLD_SHIFT       7
2179 #define PALMAS_USB_VBUS_INT_EN_HI_CLR_VADP_PRB                  0x40
2180 #define PALMAS_USB_VBUS_INT_EN_HI_CLR_VADP_PRB_SHIFT            6
2181 #define PALMAS_USB_VBUS_INT_EN_HI_CLR_VADP_SNS                  0x20
2182 #define PALMAS_USB_VBUS_INT_EN_HI_CLR_VADP_SNS_SHIFT            5
2183 #define PALMAS_USB_VBUS_INT_EN_HI_CLR_ADP                       0x10
2184 #define PALMAS_USB_VBUS_INT_EN_HI_CLR_ADP_SHIFT                 4
2185 #define PALMAS_USB_VBUS_INT_EN_HI_CLR_VA_VBUS_VLD               0x08
2186 #define PALMAS_USB_VBUS_INT_EN_HI_CLR_VA_VBUS_VLD_SHIFT         3
2187 #define PALMAS_USB_VBUS_INT_EN_HI_CLR_VA_SESS_VLD               0x04
2188 #define PALMAS_USB_VBUS_INT_EN_HI_CLR_VA_SESS_VLD_SHIFT         2
2189 #define PALMAS_USB_VBUS_INT_EN_HI_CLR_VB_SESS_VLD               0x02
2190 #define PALMAS_USB_VBUS_INT_EN_HI_CLR_VB_SESS_VLD_SHIFT         1
2191 #define PALMAS_USB_VBUS_INT_EN_HI_CLR_VB_SESS_END               0x01
2192 #define PALMAS_USB_VBUS_INT_EN_HI_CLR_VB_SESS_END_SHIFT         0
2193
2194 /* Bit definitions for USB_ID_INT_SRC */
2195 #define PALMAS_USB_ID_INT_SRC_ID_FLOAT                          0x10
2196 #define PALMAS_USB_ID_INT_SRC_ID_FLOAT_SHIFT                    4
2197 #define PALMAS_USB_ID_INT_SRC_ID_A                              0x08
2198 #define PALMAS_USB_ID_INT_SRC_ID_A_SHIFT                        3
2199 #define PALMAS_USB_ID_INT_SRC_ID_B                              0x04
2200 #define PALMAS_USB_ID_INT_SRC_ID_B_SHIFT                        2
2201 #define PALMAS_USB_ID_INT_SRC_ID_C                              0x02
2202 #define PALMAS_USB_ID_INT_SRC_ID_C_SHIFT                        1
2203 #define PALMAS_USB_ID_INT_SRC_ID_GND                            0x01
2204 #define PALMAS_USB_ID_INT_SRC_ID_GND_SHIFT                      0
2205
2206 /* Bit definitions for USB_ID_INT_LATCH_SET */
2207 #define PALMAS_USB_ID_INT_LATCH_SET_ID_FLOAT                    0x10
2208 #define PALMAS_USB_ID_INT_LATCH_SET_ID_FLOAT_SHIFT              4
2209 #define PALMAS_USB_ID_INT_LATCH_SET_ID_A                        0x08
2210 #define PALMAS_USB_ID_INT_LATCH_SET_ID_A_SHIFT                  3
2211 #define PALMAS_USB_ID_INT_LATCH_SET_ID_B                        0x04
2212 #define PALMAS_USB_ID_INT_LATCH_SET_ID_B_SHIFT                  2
2213 #define PALMAS_USB_ID_INT_LATCH_SET_ID_C                        0x02
2214 #define PALMAS_USB_ID_INT_LATCH_SET_ID_C_SHIFT                  1
2215 #define PALMAS_USB_ID_INT_LATCH_SET_ID_GND                      0x01
2216 #define PALMAS_USB_ID_INT_LATCH_SET_ID_GND_SHIFT                0
2217
2218 /* Bit definitions for USB_ID_INT_LATCH_CLR */
2219 #define PALMAS_USB_ID_INT_LATCH_CLR_ID_FLOAT                    0x10
2220 #define PALMAS_USB_ID_INT_LATCH_CLR_ID_FLOAT_SHIFT              4
2221 #define PALMAS_USB_ID_INT_LATCH_CLR_ID_A                        0x08
2222 #define PALMAS_USB_ID_INT_LATCH_CLR_ID_A_SHIFT                  3
2223 #define PALMAS_USB_ID_INT_LATCH_CLR_ID_B                        0x04
2224 #define PALMAS_USB_ID_INT_LATCH_CLR_ID_B_SHIFT                  2
2225 #define PALMAS_USB_ID_INT_LATCH_CLR_ID_C                        0x02
2226 #define PALMAS_USB_ID_INT_LATCH_CLR_ID_C_SHIFT                  1
2227 #define PALMAS_USB_ID_INT_LATCH_CLR_ID_GND                      0x01
2228 #define PALMAS_USB_ID_INT_LATCH_CLR_ID_GND_SHIFT                0
2229
2230 /* Bit definitions for USB_ID_INT_EN_LO_SET */
2231 #define PALMAS_USB_ID_INT_EN_LO_SET_ID_FLOAT                    0x10
2232 #define PALMAS_USB_ID_INT_EN_LO_SET_ID_FLOAT_SHIFT              4
2233 #define PALMAS_USB_ID_INT_EN_LO_SET_ID_A                        0x08
2234 #define PALMAS_USB_ID_INT_EN_LO_SET_ID_A_SHIFT                  3
2235 #define PALMAS_USB_ID_INT_EN_LO_SET_ID_B                        0x04
2236 #define PALMAS_USB_ID_INT_EN_LO_SET_ID_B_SHIFT                  2
2237 #define PALMAS_USB_ID_INT_EN_LO_SET_ID_C                        0x02
2238 #define PALMAS_USB_ID_INT_EN_LO_SET_ID_C_SHIFT                  1
2239 #define PALMAS_USB_ID_INT_EN_LO_SET_ID_GND                      0x01
2240 #define PALMAS_USB_ID_INT_EN_LO_SET_ID_GND_SHIFT                0
2241
2242 /* Bit definitions for USB_ID_INT_EN_LO_CLR */
2243 #define PALMAS_USB_ID_INT_EN_LO_CLR_ID_FLOAT                    0x10
2244 #define PALMAS_USB_ID_INT_EN_LO_CLR_ID_FLOAT_SHIFT              4
2245 #define PALMAS_USB_ID_INT_EN_LO_CLR_ID_A                        0x08
2246 #define PALMAS_USB_ID_INT_EN_LO_CLR_ID_A_SHIFT                  3
2247 #define PALMAS_USB_ID_INT_EN_LO_CLR_ID_B                        0x04
2248 #define PALMAS_USB_ID_INT_EN_LO_CLR_ID_B_SHIFT                  2
2249 #define PALMAS_USB_ID_INT_EN_LO_CLR_ID_C                        0x02
2250 #define PALMAS_USB_ID_INT_EN_LO_CLR_ID_C_SHIFT                  1
2251 #define PALMAS_USB_ID_INT_EN_LO_CLR_ID_GND                      0x01
2252 #define PALMAS_USB_ID_INT_EN_LO_CLR_ID_GND_SHIFT                0
2253
2254 /* Bit definitions for USB_ID_INT_EN_HI_SET */
2255 #define PALMAS_USB_ID_INT_EN_HI_SET_ID_FLOAT                    0x10
2256 #define PALMAS_USB_ID_INT_EN_HI_SET_ID_FLOAT_SHIFT              4
2257 #define PALMAS_USB_ID_INT_EN_HI_SET_ID_A                        0x08
2258 #define PALMAS_USB_ID_INT_EN_HI_SET_ID_A_SHIFT                  3
2259 #define PALMAS_USB_ID_INT_EN_HI_SET_ID_B                        0x04
2260 #define PALMAS_USB_ID_INT_EN_HI_SET_ID_B_SHIFT                  2
2261 #define PALMAS_USB_ID_INT_EN_HI_SET_ID_C                        0x02
2262 #define PALMAS_USB_ID_INT_EN_HI_SET_ID_C_SHIFT                  1
2263 #define PALMAS_USB_ID_INT_EN_HI_SET_ID_GND                      0x01
2264 #define PALMAS_USB_ID_INT_EN_HI_SET_ID_GND_SHIFT                0
2265
2266 /* Bit definitions for USB_ID_INT_EN_HI_CLR */
2267 #define PALMAS_USB_ID_INT_EN_HI_CLR_ID_FLOAT                    0x10
2268 #define PALMAS_USB_ID_INT_EN_HI_CLR_ID_FLOAT_SHIFT              4
2269 #define PALMAS_USB_ID_INT_EN_HI_CLR_ID_A                        0x08
2270 #define PALMAS_USB_ID_INT_EN_HI_CLR_ID_A_SHIFT                  3
2271 #define PALMAS_USB_ID_INT_EN_HI_CLR_ID_B                        0x04
2272 #define PALMAS_USB_ID_INT_EN_HI_CLR_ID_B_SHIFT                  2
2273 #define PALMAS_USB_ID_INT_EN_HI_CLR_ID_C                        0x02
2274 #define PALMAS_USB_ID_INT_EN_HI_CLR_ID_C_SHIFT                  1
2275 #define PALMAS_USB_ID_INT_EN_HI_CLR_ID_GND                      0x01
2276 #define PALMAS_USB_ID_INT_EN_HI_CLR_ID_GND_SHIFT                0
2277
2278 /* Bit definitions for USB_OTG_ADP_CTRL */
2279 #define PALMAS_USB_OTG_ADP_CTRL_ADP_EN                          0x04
2280 #define PALMAS_USB_OTG_ADP_CTRL_ADP_EN_SHIFT                    2
2281 #define PALMAS_USB_OTG_ADP_CTRL_ADP_MODE_MASK                   0x03
2282 #define PALMAS_USB_OTG_ADP_CTRL_ADP_MODE_SHIFT                  0
2283
2284 /* Bit definitions for USB_OTG_ADP_HIGH */
2285 #define PALMAS_USB_OTG_ADP_HIGH_T_ADP_HIGH_MASK                 0xff
2286 #define PALMAS_USB_OTG_ADP_HIGH_T_ADP_HIGH_SHIFT                0
2287
2288 /* Bit definitions for USB_OTG_ADP_LOW */
2289 #define PALMAS_USB_OTG_ADP_LOW_T_ADP_LOW_MASK                   0xff
2290 #define PALMAS_USB_OTG_ADP_LOW_T_ADP_LOW_SHIFT                  0
2291
2292 /* Bit definitions for USB_OTG_ADP_RISE */
2293 #define PALMAS_USB_OTG_ADP_RISE_T_ADP_RISE_MASK                 0xff
2294 #define PALMAS_USB_OTG_ADP_RISE_T_ADP_RISE_SHIFT                0
2295
2296 /* Bit definitions for USB_OTG_REVISION */
2297 #define PALMAS_USB_OTG_REVISION_OTG_REV                         0x01
2298 #define PALMAS_USB_OTG_REVISION_OTG_REV_SHIFT                   0
2299
2300 /* Registers for function VIBRATOR */
2301 #define PALMAS_VIBRA_CTRL                                       0x0
2302
2303 /* Bit definitions for VIBRA_CTRL */
2304 #define PALMAS_VIBRA_CTRL_PWM_DUTY_SEL_MASK                     0x06
2305 #define PALMAS_VIBRA_CTRL_PWM_DUTY_SEL_SHIFT                    1
2306 #define PALMAS_VIBRA_CTRL_PWM_FREQ_SEL                          0x01
2307 #define PALMAS_VIBRA_CTRL_PWM_FREQ_SEL_SHIFT                    0
2308
2309 /* Registers for function GPIO */
2310 #define PALMAS_GPIO_DATA_IN                                     0x0
2311 #define PALMAS_GPIO_DATA_DIR                                    0x1
2312 #define PALMAS_GPIO_DATA_OUT                                    0x2
2313 #define PALMAS_GPIO_DEBOUNCE_EN                                 0x3
2314 #define PALMAS_GPIO_CLEAR_DATA_OUT                              0x4
2315 #define PALMAS_GPIO_SET_DATA_OUT                                0x5
2316 #define PALMAS_PU_PD_GPIO_CTRL1                                 0x6
2317 #define PALMAS_PU_PD_GPIO_CTRL2                                 0x7
2318 #define PALMAS_OD_OUTPUT_GPIO_CTRL                              0x8
2319
2320 /* Bit definitions for GPIO_DATA_IN */
2321 #define PALMAS_GPIO_DATA_IN_GPIO_7_IN                           0x80
2322 #define PALMAS_GPIO_DATA_IN_GPIO_7_IN_SHIFT                     7
2323 #define PALMAS_GPIO_DATA_IN_GPIO_6_IN                           0x40
2324 #define PALMAS_GPIO_DATA_IN_GPIO_6_IN_SHIFT                     6
2325 #define PALMAS_GPIO_DATA_IN_GPIO_5_IN                           0x20
2326 #define PALMAS_GPIO_DATA_IN_GPIO_5_IN_SHIFT                     5
2327 #define PALMAS_GPIO_DATA_IN_GPIO_4_IN                           0x10
2328 #define PALMAS_GPIO_DATA_IN_GPIO_4_IN_SHIFT                     4
2329 #define PALMAS_GPIO_DATA_IN_GPIO_3_IN                           0x08
2330 #define PALMAS_GPIO_DATA_IN_GPIO_3_IN_SHIFT                     3
2331 #define PALMAS_GPIO_DATA_IN_GPIO_2_IN                           0x04
2332 #define PALMAS_GPIO_DATA_IN_GPIO_2_IN_SHIFT                     2
2333 #define PALMAS_GPIO_DATA_IN_GPIO_1_IN                           0x02
2334 #define PALMAS_GPIO_DATA_IN_GPIO_1_IN_SHIFT                     1
2335 #define PALMAS_GPIO_DATA_IN_GPIO_0_IN                           0x01
2336 #define PALMAS_GPIO_DATA_IN_GPIO_0_IN_SHIFT                     0
2337
2338 /* Bit definitions for GPIO_DATA_DIR */
2339 #define PALMAS_GPIO_DATA_DIR_GPIO_7_DIR                         0x80
2340 #define PALMAS_GPIO_DATA_DIR_GPIO_7_DIR_SHIFT                   7
2341 #define PALMAS_GPIO_DATA_DIR_GPIO_6_DIR                         0x40
2342 #define PALMAS_GPIO_DATA_DIR_GPIO_6_DIR_SHIFT                   6
2343 #define PALMAS_GPIO_DATA_DIR_GPIO_5_DIR                         0x20
2344 #define PALMAS_GPIO_DATA_DIR_GPIO_5_DIR_SHIFT                   5
2345 #define PALMAS_GPIO_DATA_DIR_GPIO_4_DIR                         0x10
2346 #define PALMAS_GPIO_DATA_DIR_GPIO_4_DIR_SHIFT                   4
2347 #define PALMAS_GPIO_DATA_DIR_GPIO_3_DIR                         0x08
2348 #define PALMAS_GPIO_DATA_DIR_GPIO_3_DIR_SHIFT                   3
2349 #define PALMAS_GPIO_DATA_DIR_GPIO_2_DIR                         0x04
2350 #define PALMAS_GPIO_DATA_DIR_GPIO_2_DIR_SHIFT                   2
2351 #define PALMAS_GPIO_DATA_DIR_GPIO_1_DIR                         0x02
2352 #define PALMAS_GPIO_DATA_DIR_GPIO_1_DIR_SHIFT                   1
2353 #define PALMAS_GPIO_DATA_DIR_GPIO_0_DIR                         0x01
2354 #define PALMAS_GPIO_DATA_DIR_GPIO_0_DIR_SHIFT                   0
2355
2356 /* Bit definitions for GPIO_DATA_OUT */
2357 #define PALMAS_GPIO_DATA_OUT_GPIO_7_OUT                         0x80
2358 #define PALMAS_GPIO_DATA_OUT_GPIO_7_OUT_SHIFT                   7
2359 #define PALMAS_GPIO_DATA_OUT_GPIO_6_OUT                         0x40
2360 #define PALMAS_GPIO_DATA_OUT_GPIO_6_OUT_SHIFT                   6
2361 #define PALMAS_GPIO_DATA_OUT_GPIO_5_OUT                         0x20
2362 #define PALMAS_GPIO_DATA_OUT_GPIO_5_OUT_SHIFT                   5
2363 #define PALMAS_GPIO_DATA_OUT_GPIO_4_OUT                         0x10
2364 #define PALMAS_GPIO_DATA_OUT_GPIO_4_OUT_SHIFT                   4
2365 #define PALMAS_GPIO_DATA_OUT_GPIO_3_OUT                         0x08
2366 #define PALMAS_GPIO_DATA_OUT_GPIO_3_OUT_SHIFT                   3
2367 #define PALMAS_GPIO_DATA_OUT_GPIO_2_OUT                         0x04
2368 #define PALMAS_GPIO_DATA_OUT_GPIO_2_OUT_SHIFT                   2
2369 #define PALMAS_GPIO_DATA_OUT_GPIO_1_OUT                         0x02
2370 #define PALMAS_GPIO_DATA_OUT_GPIO_1_OUT_SHIFT                   1
2371 #define PALMAS_GPIO_DATA_OUT_GPIO_0_OUT                         0x01
2372 #define PALMAS_GPIO_DATA_OUT_GPIO_0_OUT_SHIFT                   0
2373
2374 /* Bit definitions for GPIO_DEBOUNCE_EN */
2375 #define PALMAS_GPIO_DEBOUNCE_EN_GPIO_7_DEBOUNCE_EN              0x80
2376 #define PALMAS_GPIO_DEBOUNCE_EN_GPIO_7_DEBOUNCE_EN_SHIFT        7
2377 #define PALMAS_GPIO_DEBOUNCE_EN_GPIO_6_DEBOUNCE_EN              0x40
2378 #define PALMAS_GPIO_DEBOUNCE_EN_GPIO_6_DEBOUNCE_EN_SHIFT        6
2379 #define PALMAS_GPIO_DEBOUNCE_EN_GPIO_5_DEBOUNCE_EN              0x20
2380 #define PALMAS_GPIO_DEBOUNCE_EN_GPIO_5_DEBOUNCE_EN_SHIFT        5
2381 #define PALMAS_GPIO_DEBOUNCE_EN_GPIO_4_DEBOUNCE_EN              0x10
2382 #define PALMAS_GPIO_DEBOUNCE_EN_GPIO_4_DEBOUNCE_EN_SHIFT        4
2383 #define PALMAS_GPIO_DEBOUNCE_EN_GPIO_3_DEBOUNCE_EN              0x08
2384 #define PALMAS_GPIO_DEBOUNCE_EN_GPIO_3_DEBOUNCE_EN_SHIFT        3
2385 #define PALMAS_GPIO_DEBOUNCE_EN_GPIO_2_DEBOUNCE_EN              0x04
2386 #define PALMAS_GPIO_DEBOUNCE_EN_GPIO_2_DEBOUNCE_EN_SHIFT        2
2387 #define PALMAS_GPIO_DEBOUNCE_EN_GPIO_1_DEBOUNCE_EN              0x02
2388 #define PALMAS_GPIO_DEBOUNCE_EN_GPIO_1_DEBOUNCE_EN_SHIFT        1
2389 #define PALMAS_GPIO_DEBOUNCE_EN_GPIO_0_DEBOUNCE_EN              0x01
2390 #define PALMAS_GPIO_DEBOUNCE_EN_GPIO_0_DEBOUNCE_EN_SHIFT        0
2391
2392 /* Bit definitions for GPIO_CLEAR_DATA_OUT */
2393 #define PALMAS_GPIO_CLEAR_DATA_OUT_GPIO_7_CLEAR_DATA_OUT        0x80
2394 #define PALMAS_GPIO_CLEAR_DATA_OUT_GPIO_7_CLEAR_DATA_OUT_SHIFT  7
2395 #define PALMAS_GPIO_CLEAR_DATA_OUT_GPIO_6_CLEAR_DATA_OUT        0x40
2396 #define PALMAS_GPIO_CLEAR_DATA_OUT_GPIO_6_CLEAR_DATA_OUT_SHIFT  6
2397 #define PALMAS_GPIO_CLEAR_DATA_OUT_GPIO_5_CLEAR_DATA_OUT        0x20
2398 #define PALMAS_GPIO_CLEAR_DATA_OUT_GPIO_5_CLEAR_DATA_OUT_SHIFT  5
2399 #define PALMAS_GPIO_CLEAR_DATA_OUT_GPIO_4_CLEAR_DATA_OUT        0x10
2400 #define PALMAS_GPIO_CLEAR_DATA_OUT_GPIO_4_CLEAR_DATA_OUT_SHIFT  4
2401 #define PALMAS_GPIO_CLEAR_DATA_OUT_GPIO_3_CLEAR_DATA_OUT        0x08
2402 #define PALMAS_GPIO_CLEAR_DATA_OUT_GPIO_3_CLEAR_DATA_OUT_SHIFT  3
2403 #define PALMAS_GPIO_CLEAR_DATA_OUT_GPIO_2_CLEAR_DATA_OUT        0x04
2404 #define PALMAS_GPIO_CLEAR_DATA_OUT_GPIO_2_CLEAR_DATA_OUT_SHIFT  2
2405 #define PALMAS_GPIO_CLEAR_DATA_OUT_GPIO_1_CLEAR_DATA_OUT        0x02
2406 #define PALMAS_GPIO_CLEAR_DATA_OUT_GPIO_1_CLEAR_DATA_OUT_SHIFT  1
2407 #define PALMAS_GPIO_CLEAR_DATA_OUT_GPIO_0_CLEAR_DATA_OUT        0x01
2408 #define PALMAS_GPIO_CLEAR_DATA_OUT_GPIO_0_CLEAR_DATA_OUT_SHIFT  0
2409
2410 /* Bit definitions for GPIO_SET_DATA_OUT */
2411 #define PALMAS_GPIO_SET_DATA_OUT_GPIO_7_SET_DATA_OUT            0x80
2412 #define PALMAS_GPIO_SET_DATA_OUT_GPIO_7_SET_DATA_OUT_SHIFT      7
2413 #define PALMAS_GPIO_SET_DATA_OUT_GPIO_6_SET_DATA_OUT            0x40
2414 #define PALMAS_GPIO_SET_DATA_OUT_GPIO_6_SET_DATA_OUT_SHIFT      6
2415 #define PALMAS_GPIO_SET_DATA_OUT_GPIO_5_SET_DATA_OUT            0x20
2416 #define PALMAS_GPIO_SET_DATA_OUT_GPIO_5_SET_DATA_OUT_SHIFT      5
2417 #define PALMAS_GPIO_SET_DATA_OUT_GPIO_4_SET_DATA_OUT            0x10
2418 #define PALMAS_GPIO_SET_DATA_OUT_GPIO_4_SET_DATA_OUT_SHIFT      4
2419 #define PALMAS_GPIO_SET_DATA_OUT_GPIO_3_SET_DATA_OUT            0x08
2420 #define PALMAS_GPIO_SET_DATA_OUT_GPIO_3_SET_DATA_OUT_SHIFT      3
2421 #define PALMAS_GPIO_SET_DATA_OUT_GPIO_2_SET_DATA_OUT            0x04
2422 #define PALMAS_GPIO_SET_DATA_OUT_GPIO_2_SET_DATA_OUT_SHIFT      2
2423 #define PALMAS_GPIO_SET_DATA_OUT_GPIO_1_SET_DATA_OUT            0x02
2424 #define PALMAS_GPIO_SET_DATA_OUT_GPIO_1_SET_DATA_OUT_SHIFT      1
2425 #define PALMAS_GPIO_SET_DATA_OUT_GPIO_0_SET_DATA_OUT            0x01
2426 #define PALMAS_GPIO_SET_DATA_OUT_GPIO_0_SET_DATA_OUT_SHIFT      0
2427
2428 /* Bit definitions for PU_PD_GPIO_CTRL1 */
2429 #define PALMAS_PU_PD_GPIO_CTRL1_GPIO_3_PD                       0x40
2430 #define PALMAS_PU_PD_GPIO_CTRL1_GPIO_3_PD_SHIFT                 6
2431 #define PALMAS_PU_PD_GPIO_CTRL1_GPIO_2_PU                       0x20
2432 #define PALMAS_PU_PD_GPIO_CTRL1_GPIO_2_PU_SHIFT                 5
2433 #define PALMAS_PU_PD_GPIO_CTRL1_GPIO_2_PD                       0x10
2434 #define PALMAS_PU_PD_GPIO_CTRL1_GPIO_2_PD_SHIFT                 4
2435 #define PALMAS_PU_PD_GPIO_CTRL1_GPIO_1_PU                       0x08
2436 #define PALMAS_PU_PD_GPIO_CTRL1_GPIO_1_PU_SHIFT                 3
2437 #define PALMAS_PU_PD_GPIO_CTRL1_GPIO_1_PD                       0x04
2438 #define PALMAS_PU_PD_GPIO_CTRL1_GPIO_1_PD_SHIFT                 2
2439 #define PALMAS_PU_PD_GPIO_CTRL1_GPIO_0_PD                       0x01
2440 #define PALMAS_PU_PD_GPIO_CTRL1_GPIO_0_PD_SHIFT                 0
2441
2442 /* Bit definitions for PU_PD_GPIO_CTRL2 */
2443 #define PALMAS_PU_PD_GPIO_CTRL2_GPIO_7_PD                       0x40
2444 #define PALMAS_PU_PD_GPIO_CTRL2_GPIO_7_PD_SHIFT                 6
2445 #define PALMAS_PU_PD_GPIO_CTRL2_GPIO_6_PU                       0x20
2446 #define PALMAS_PU_PD_GPIO_CTRL2_GPIO_6_PU_SHIFT                 5
2447 #define PALMAS_PU_PD_GPIO_CTRL2_GPIO_6_PD                       0x10
2448 #define PALMAS_PU_PD_GPIO_CTRL2_GPIO_6_PD_SHIFT                 4
2449 #define PALMAS_PU_PD_GPIO_CTRL2_GPIO_5_PU                       0x08
2450 #define PALMAS_PU_PD_GPIO_CTRL2_GPIO_5_PU_SHIFT                 3
2451 #define PALMAS_PU_PD_GPIO_CTRL2_GPIO_5_PD                       0x04
2452 #define PALMAS_PU_PD_GPIO_CTRL2_GPIO_5_PD_SHIFT                 2
2453 #define PALMAS_PU_PD_GPIO_CTRL2_GPIO_4_PU                       0x02
2454 #define PALMAS_PU_PD_GPIO_CTRL2_GPIO_4_PU_SHIFT                 1
2455 #define PALMAS_PU_PD_GPIO_CTRL2_GPIO_4_PD                       0x01
2456 #define PALMAS_PU_PD_GPIO_CTRL2_GPIO_4_PD_SHIFT                 0
2457
2458 /* Bit definitions for OD_OUTPUT_GPIO_CTRL */
2459 #define PALMAS_OD_OUTPUT_GPIO_CTRL_GPIO_5_OD                    0x20
2460 #define PALMAS_OD_OUTPUT_GPIO_CTRL_GPIO_5_OD_SHIFT              5
2461 #define PALMAS_OD_OUTPUT_GPIO_CTRL_GPIO_2_OD                    0x04
2462 #define PALMAS_OD_OUTPUT_GPIO_CTRL_GPIO_2_OD_SHIFT              2
2463 #define PALMAS_OD_OUTPUT_GPIO_CTRL_GPIO_1_OD                    0x02
2464 #define PALMAS_OD_OUTPUT_GPIO_CTRL_GPIO_1_OD_SHIFT              1
2465
2466 /* Registers for function GPADC */
2467 #define PALMAS_GPADC_CTRL1                                      0x0
2468 #define PALMAS_GPADC_CTRL2                                      0x1
2469 #define PALMAS_GPADC_RT_CTRL                                    0x2
2470 #define PALMAS_GPADC_AUTO_CTRL                                  0x3
2471 #define PALMAS_GPADC_STATUS                                     0x4
2472 #define PALMAS_GPADC_RT_SELECT                                  0x5
2473 #define PALMAS_GPADC_RT_CONV0_LSB                               0x6
2474 #define PALMAS_GPADC_RT_CONV0_MSB                               0x7
2475 #define PALMAS_GPADC_AUTO_SELECT                                0x8
2476 #define PALMAS_GPADC_AUTO_CONV0_LSB                             0x9
2477 #define PALMAS_GPADC_AUTO_CONV0_MSB                             0xA
2478 #define PALMAS_GPADC_AUTO_CONV1_LSB                             0xB
2479 #define PALMAS_GPADC_AUTO_CONV1_MSB                             0xC
2480 #define PALMAS_GPADC_SW_SELECT                                  0xD
2481 #define PALMAS_GPADC_SW_CONV0_LSB                               0xE
2482 #define PALMAS_GPADC_SW_CONV0_MSB                               0xF
2483 #define PALMAS_GPADC_THRES_CONV0_LSB                            0x10
2484 #define PALMAS_GPADC_THRES_CONV0_MSB                            0x11
2485 #define PALMAS_GPADC_THRES_CONV1_LSB                            0x12
2486 #define PALMAS_GPADC_THRES_CONV1_MSB                            0x13
2487 #define PALMAS_GPADC_SMPS_ILMONITOR_EN                          0x14
2488 #define PALMAS_GPADC_SMPS_VSEL_MONITORING                       0x15
2489
2490 /* Bit definitions for GPADC_CTRL1 */
2491 #define PALMAS_GPADC_CTRL1_RESERVED_MASK                        0xc0
2492 #define PALMAS_GPADC_CTRL1_RESERVED_SHIFT                       6
2493 #define PALMAS_GPADC_CTRL1_CURRENT_SRC_CH3_MASK                 0x30
2494 #define PALMAS_GPADC_CTRL1_CURRENT_SRC_CH3_SHIFT                4
2495 #define PALMAS_GPADC_CTRL1_CURRENT_SRC_CH0_MASK                 0x0c
2496 #define PALMAS_GPADC_CTRL1_CURRENT_SRC_CH0_SHIFT                2
2497 #define PALMAS_GPADC_CTRL1_BAT_REMOVAL_DET                      0x02
2498 #define PALMAS_GPADC_CTRL1_BAT_REMOVAL_DET_SHIFT                1
2499 #define PALMAS_GPADC_CTRL1_GPADC_FORCE                          0x01
2500 #define PALMAS_GPADC_CTRL1_GPADC_FORCE_SHIFT                    0
2501
2502 /* Bit definitions for GPADC_CTRL2 */
2503 #define PALMAS_GPADC_CTRL2_RESERVED_MASK                        0x06
2504 #define PALMAS_GPADC_CTRL2_RESERVED_SHIFT                       1
2505
2506 /* Bit definitions for GPADC_RT_CTRL */
2507 #define PALMAS_GPADC_RT_CTRL_EXTEND_DELAY                       0x02
2508 #define PALMAS_GPADC_RT_CTRL_EXTEND_DELAY_SHIFT                 1
2509 #define PALMAS_GPADC_RT_CTRL_START_POLARITY                     0x01
2510 #define PALMAS_GPADC_RT_CTRL_START_POLARITY_SHIFT               0
2511
2512 /* Bit definitions for GPADC_AUTO_CTRL */
2513 #define PALMAS_GPADC_AUTO_CTRL_SHUTDOWN_CONV1                   0x80
2514 #define PALMAS_GPADC_AUTO_CTRL_SHUTDOWN_CONV1_SHIFT             7
2515 #define PALMAS_GPADC_AUTO_CTRL_SHUTDOWN_CONV0                   0x40
2516 #define PALMAS_GPADC_AUTO_CTRL_SHUTDOWN_CONV0_SHIFT             6
2517 #define PALMAS_GPADC_AUTO_CTRL_AUTO_CONV1_EN                    0x20
2518 #define PALMAS_GPADC_AUTO_CTRL_AUTO_CONV1_EN_SHIFT              5
2519 #define PALMAS_GPADC_AUTO_CTRL_AUTO_CONV0_EN                    0x10
2520 #define PALMAS_GPADC_AUTO_CTRL_AUTO_CONV0_EN_SHIFT              4
2521 #define PALMAS_GPADC_AUTO_CTRL_COUNTER_CONV_MASK                0x0f
2522 #define PALMAS_GPADC_AUTO_CTRL_COUNTER_CONV_SHIFT               0
2523
2524 /* Bit definitions for GPADC_STATUS */
2525 #define PALMAS_GPADC_STATUS_GPADC_AVAILABLE                     0x10
2526 #define PALMAS_GPADC_STATUS_GPADC_AVAILABLE_SHIFT               4
2527
2528 /* Bit definitions for GPADC_RT_SELECT */
2529 #define PALMAS_GPADC_RT_SELECT_RT_CONV_EN                       0x80
2530 #define PALMAS_GPADC_RT_SELECT_RT_CONV_EN_SHIFT                 7
2531 #define PALMAS_GPADC_RT_SELECT_RT_CONV0_SEL_MASK                0x0f
2532 #define PALMAS_GPADC_RT_SELECT_RT_CONV0_SEL_SHIFT               0
2533
2534 /* Bit definitions for GPADC_RT_CONV0_LSB */
2535 #define PALMAS_GPADC_RT_CONV0_LSB_RT_CONV0_LSB_MASK             0xff
2536 #define PALMAS_GPADC_RT_CONV0_LSB_RT_CONV0_LSB_SHIFT            0
2537
2538 /* Bit definitions for GPADC_RT_CONV0_MSB */
2539 #define PALMAS_GPADC_RT_CONV0_MSB_RT_CONV0_MSB_MASK             0x0f
2540 #define PALMAS_GPADC_RT_CONV0_MSB_RT_CONV0_MSB_SHIFT            0
2541
2542 /* Bit definitions for GPADC_AUTO_SELECT */
2543 #define PALMAS_GPADC_AUTO_SELECT_AUTO_CONV1_SEL_MASK            0xf0
2544 #define PALMAS_GPADC_AUTO_SELECT_AUTO_CONV1_SEL_SHIFT           4
2545 #define PALMAS_GPADC_AUTO_SELECT_AUTO_CONV0_SEL_MASK            0x0f
2546 #define PALMAS_GPADC_AUTO_SELECT_AUTO_CONV0_SEL_SHIFT           0
2547
2548 /* Bit definitions for GPADC_AUTO_CONV0_LSB */
2549 #define PALMAS_GPADC_AUTO_CONV0_LSB_AUTO_CONV0_LSB_MASK         0xff
2550 #define PALMAS_GPADC_AUTO_CONV0_LSB_AUTO_CONV0_LSB_SHIFT        0
2551
2552 /* Bit definitions for GPADC_AUTO_CONV0_MSB */
2553 #define PALMAS_GPADC_AUTO_CONV0_MSB_AUTO_CONV0_MSB_MASK         0x0f
2554 #define PALMAS_GPADC_AUTO_CONV0_MSB_AUTO_CONV0_MSB_SHIFT        0
2555
2556 /* Bit definitions for GPADC_AUTO_CONV1_LSB */
2557 #define PALMAS_GPADC_AUTO_CONV1_LSB_AUTO_CONV1_LSB_MASK         0xff
2558 #define PALMAS_GPADC_AUTO_CONV1_LSB_AUTO_CONV1_LSB_SHIFT        0
2559
2560 /* Bit definitions for GPADC_AUTO_CONV1_MSB */
2561 #define PALMAS_GPADC_AUTO_CONV1_MSB_AUTO_CONV1_MSB_MASK         0x0f
2562 #define PALMAS_GPADC_AUTO_CONV1_MSB_AUTO_CONV1_MSB_SHIFT        0
2563
2564 /* Bit definitions for GPADC_SW_SELECT */
2565 #define PALMAS_GPADC_SW_SELECT_SW_CONV_EN                       0x80
2566 #define PALMAS_GPADC_SW_SELECT_SW_CONV_EN_SHIFT                 7
2567 #define PALMAS_GPADC_SW_SELECT_SW_START_CONV0                   0x10
2568 #define PALMAS_GPADC_SW_SELECT_SW_START_CONV0_SHIFT             4
2569 #define PALMAS_GPADC_SW_SELECT_SW_CONV0_SEL_MASK                0x0f
2570 #define PALMAS_GPADC_SW_SELECT_SW_CONV0_SEL_SHIFT               0
2571
2572 /* Bit definitions for GPADC_SW_CONV0_LSB */
2573 #define PALMAS_GPADC_SW_CONV0_LSB_SW_CONV0_LSB_MASK             0xff
2574 #define PALMAS_GPADC_SW_CONV0_LSB_SW_CONV0_LSB_SHIFT            0
2575
2576 /* Bit definitions for GPADC_SW_CONV0_MSB */
2577 #define PALMAS_GPADC_SW_CONV0_MSB_SW_CONV0_MSB_MASK             0x0f
2578 #define PALMAS_GPADC_SW_CONV0_MSB_SW_CONV0_MSB_SHIFT            0
2579
2580 /* Bit definitions for GPADC_THRES_CONV0_LSB */
2581 #define PALMAS_GPADC_THRES_CONV0_LSB_THRES_CONV0_LSB_MASK       0xff
2582 #define PALMAS_GPADC_THRES_CONV0_LSB_THRES_CONV0_LSB_SHIFT      0
2583
2584 /* Bit definitions for GPADC_THRES_CONV0_MSB */
2585 #define PALMAS_GPADC_THRES_CONV0_MSB_THRES_CONV0_POL            0x80
2586 #define PALMAS_GPADC_THRES_CONV0_MSB_THRES_CONV0_POL_SHIFT      7
2587 #define PALMAS_GPADC_THRES_CONV0_MSB_THRES_CONV0_MSB_MASK       0x0f
2588 #define PALMAS_GPADC_THRES_CONV0_MSB_THRES_CONV0_MSB_SHIFT      0
2589
2590 /* Bit definitions for GPADC_THRES_CONV1_LSB */
2591 #define PALMAS_GPADC_THRES_CONV1_LSB_THRES_CONV1_LSB_MASK       0xff
2592 #define PALMAS_GPADC_THRES_CONV1_LSB_THRES_CONV1_LSB_SHIFT      0
2593
2594 /* Bit definitions for GPADC_THRES_CONV1_MSB */
2595 #define PALMAS_GPADC_THRES_CONV1_MSB_THRES_CONV1_POL            0x80
2596 #define PALMAS_GPADC_THRES_CONV1_MSB_THRES_CONV1_POL_SHIFT      7
2597 #define PALMAS_GPADC_THRES_CONV1_MSB_THRES_CONV1_MSB_MASK       0x0f
2598 #define PALMAS_GPADC_THRES_CONV1_MSB_THRES_CONV1_MSB_SHIFT      0
2599
2600 /* Bit definitions for GPADC_SMPS_ILMONITOR_EN */
2601 #define PALMAS_GPADC_SMPS_ILMONITOR_EN_SMPS_ILMON_EN            0x20
2602 #define PALMAS_GPADC_SMPS_ILMONITOR_EN_SMPS_ILMON_EN_SHIFT      5
2603 #define PALMAS_GPADC_SMPS_ILMONITOR_EN_SMPS_ILMON_REXT          0x10
2604 #define PALMAS_GPADC_SMPS_ILMONITOR_EN_SMPS_ILMON_REXT_SHIFT    4
2605 #define PALMAS_GPADC_SMPS_ILMONITOR_EN_SMPS_ILMON_SEL_MASK      0x0f
2606 #define PALMAS_GPADC_SMPS_ILMONITOR_EN_SMPS_ILMON_SEL_SHIFT     0
2607
2608 /* Bit definitions for GPADC_SMPS_VSEL_MONITORING */
2609 #define PALMAS_GPADC_SMPS_VSEL_MONITORING_ACTIVE_PHASE          0x80
2610 #define PALMAS_GPADC_SMPS_VSEL_MONITORING_ACTIVE_PHASE_SHIFT    7
2611 #define PALMAS_GPADC_SMPS_VSEL_MONITORING_SMPS_VSEL_MONITORING_MASK     0x7f
2612 #define PALMAS_GPADC_SMPS_VSEL_MONITORING_SMPS_VSEL_MONITORING_SHIFT    0
2613
2614 /* Registers for function GPADC */
2615 #define PALMAS_GPADC_TRIM1                                      0x0
2616 #define PALMAS_GPADC_TRIM2                                      0x1
2617 #define PALMAS_GPADC_TRIM3                                      0x2
2618 #define PALMAS_GPADC_TRIM4                                      0x3
2619 #define PALMAS_GPADC_TRIM5                                      0x4
2620 #define PALMAS_GPADC_TRIM6                                      0x5
2621 #define PALMAS_GPADC_TRIM7                                      0x6
2622 #define PALMAS_GPADC_TRIM8                                      0x7
2623 #define PALMAS_GPADC_TRIM9                                      0x8
2624 #define PALMAS_GPADC_TRIM10                                     0x9
2625 #define PALMAS_GPADC_TRIM11                                     0xA
2626 #define PALMAS_GPADC_TRIM12                                     0xB
2627 #define PALMAS_GPADC_TRIM13                                     0xC
2628 #define PALMAS_GPADC_TRIM14                                     0xD
2629 #define PALMAS_GPADC_TRIM15                                     0xE
2630 #define PALMAS_GPADC_TRIM16                                     0xF
2631
2632 /*
2633  *PALMAS GPIOs
2634  */
2635 enum {
2636         PALMAS_GPIO0,
2637         PALMAS_GPIO1,
2638         PALMAS_GPIO2,
2639         PALMAS_GPIO3,
2640         PALMAS_GPIO4,
2641         PALMAS_GPIO5,
2642         PALMAS_GPIO6,
2643         PALMAS_GPIO7,
2644
2645         PALMAS_GPIO_NR,
2646 };
2647 #endif /*  __LINUX_MFD_PALMAS_H */