mfd: palmas: add USB VBUS LP0 wakeup option
[linux-2.6.git] / include / linux / mfd / palmas.h
1 /*
2  * TI Palmas
3  *
4  * Copyright 2011 Texas Instruments Inc.
5  * Copyright (c) 2013, NVIDIA CORPORATION.  All rights reserved.
6  *
7  * Author: Graeme Gregory <gg@slimlogic.co.uk>
8  *
9  *  This program is free software; you can redistribute it and/or modify it
10  *  under  the terms of the GNU General  Public License as published by the
11  *  Free Software Foundation;  either version 2 of the License, or (at your
12  *  option) any later version.
13  *
14  */
15
16 #ifndef __LINUX_MFD_PALMAS_H
17 #define __LINUX_MFD_PALMAS_H
18
19 #include <linux/usb/otg.h>
20 #include <linux/leds.h>
21 #include <linux/regmap.h>
22 #include <linux/regulator/driver.h>
23
24 #define PALMAS_NUM_CLIENTS              3
25
26 struct palmas_pmic;
27 struct palmas_rtc;
28
29 #define palmas_rails(_name) "palmas_"#_name
30
31 struct palmas {
32         struct device *dev;
33
34         struct i2c_client *i2c_clients[PALMAS_NUM_CLIENTS];
35         struct regmap *regmap[PALMAS_NUM_CLIENTS];
36
37         /* Stored chip id */
38         int id;
39
40         /* IRQ Data */
41         int irq;
42         u32 irq_mask;
43         struct palmas_irq_chip_data *irq_chip_data;
44
45         /* Child Devices */
46         struct palmas_pmic *pmic;
47         struct palmas_rtc *rtc;
48
49         /* GPIO MUXing */
50         u8 gpio_muxed;
51         u8 led_muxed;
52         u8 pwm_muxed;
53
54         int design_revision;
55         int sw_otp_version;
56         int es_minor_version;
57         int es_major_version;
58 };
59
60 struct palmas_reg_init {
61         /* warm_rest controls the voltage levels after a warm reset
62          *
63          * 0: reload default values from OTP on warm reset
64          * 1: maintain voltage from VSEL on warm reset
65          */
66         int warm_reset;
67
68         /* roof_floor controls whether the regulator uses the i2c style
69          * of DVS or uses the method where a GPIO or other control method is
70          * attached to the NSLEEP/ENABLE1/ENABLE2 pins
71          *
72          * For SMPS
73          *
74          * 0: i2c selection of voltage
75          * 1: pin selection of voltage.
76          *
77          * For LDO unused
78          */
79         int roof_floor;
80
81         /* sleep_mode is the mode loaded to MODE_SLEEP bits as defined in
82          * the data sheet.
83          *
84          * For SMPS
85          *
86          * 0: Off
87          * 1: AUTO
88          * 2: ECO
89          * 3: Forced PWM
90          *
91          * For LDO
92          *
93          * 0: Off
94          * 1: On
95          */
96         int mode_sleep;
97
98         /* tstep is the timestep loaded to the TSTEP register
99          *
100          * For SMPS
101          *
102          * 0: Jump (no slope control)
103          * 1: 10mV/us
104          * 2: 5mV/us
105          * 3: 2.5mV/us
106          *
107          * For LDO unused
108          */
109         int tstep;
110
111         /* voltage_sel is the bitfield loaded onto the SMPSX_VOLTAGE
112          * register. Set this is the default voltage set in OTP needs
113          * to be overridden.
114          */
115         u8 vsel;
116
117 };
118
119 enum palmas_regulators {
120         /* SMPS regulators */
121         PALMAS_REG_SMPS12,
122         PALMAS_REG_SMPS123,
123         PALMAS_REG_SMPS3,
124         PALMAS_REG_SMPS45,
125         PALMAS_REG_SMPS457,
126         PALMAS_REG_SMPS6,
127         PALMAS_REG_SMPS7,
128         PALMAS_REG_SMPS8,
129         PALMAS_REG_SMPS9,
130         PALMAS_REG_SMPS10,
131         /* LDO regulators */
132         PALMAS_REG_LDO1,
133         PALMAS_REG_LDO2,
134         PALMAS_REG_LDO3,
135         PALMAS_REG_LDO4,
136         PALMAS_REG_LDO5,
137         PALMAS_REG_LDO6,
138         PALMAS_REG_LDO7,
139         PALMAS_REG_LDO8,
140         PALMAS_REG_LDO9,
141         PALMAS_REG_LDOLN,
142         PALMAS_REG_LDOUSB,
143         /* External regulators */
144         PALMAS_REG_REGEN1,
145         PALMAS_REG_REGEN2,
146         PALMAS_REG_REGEN3,
147         PALMAS_REG_SYSEN1,
148         PALMAS_REG_SYSEN2,
149         /* Total number of regulators */
150         PALMAS_NUM_REGS,
151 };
152
153 enum PALMAS_CLOCK32K {
154         PALMAS_CLOCK32KG,
155         PALMAS_CLOCK32KG_AUDIO,
156
157         /* Last entry */
158         PALMAS_CLOCK32K_NR,
159 };
160
161 struct palmas_clk32k_init_data {
162         int clk32k_id;
163         bool enable;
164         int sleep_control;
165 };
166
167 struct palmas_dvfs_init_data {
168         bool    en_pwm;
169         int     ext_ctrl;
170         int     reg_id;
171         bool    step_20mV;
172         int     base_voltage_uV;
173         int     max_voltage_uV;
174 };
175
176 struct palmas_pmic_platform_data {
177         /* An array of pointers to regulator init data indexed by regulator
178          * ID
179          */
180         struct regulator_init_data *reg_data[PALMAS_NUM_REGS];
181
182         /* An array of pointers to structures containing sleep mode and DVS
183          * configuration for regulators indexed by ID
184          */
185         struct palmas_reg_init *reg_init[PALMAS_NUM_REGS];
186
187         /* CL DVFS init data */
188         struct palmas_dvfs_init_data *dvfs_init_data;
189         int dvfs_init_data_size;
190
191         /* use LDO6 for vibrator control */
192         int ldo6_vibrator;
193
194         bool enable_ldo8_tracking;
195         bool disabe_ldo8_tracking_suspend;
196         bool disable_smps10_boost_suspend;
197
198
199 };
200
201 struct palmas_rtc_platform_data {
202         unsigned enable_charging:1;
203         unsigned charging_current_ua;
204 };
205
206 struct palmas_gpadc_platform_data {
207         int channel0_current_uA;
208         int channel3_current_uA;
209 };
210
211 struct palmas_pinctrl_config {
212         int pin_name;
213         int pin_mux_option;
214         int open_drain_state;
215         int pin_pull_up_dn;
216 };
217
218 struct palmas_pinctrl_platform_data {
219         struct palmas_pinctrl_config *pincfg;
220         int num_pinctrl;
221         bool dvfs1_enable;
222         bool dvfs2_enable;
223 };
224
225 struct palmas_extcon_platform_data {
226         const char *connection_name;
227         bool enable_vbus_detection;
228         bool enable_id_pin_detection;
229 };
230
231 struct palmas_platform_data {
232         int gpio_base;
233         int irq_base;
234         int irq_type;
235
236         /* bit value to be loaded to the POWER_CTRL register */
237         u8 power_ctrl;
238
239         struct palmas_pmic_platform_data *pmic_pdata;
240         struct palmas_rtc_platform_data *rtc_pdata;
241         struct palmas_gpadc_platform_data *adc_pdata;
242
243         struct palmas_clk32k_init_data  *clk32k_init_data;
244         int clk32k_init_data_size;
245         bool use_power_off;
246         /* LDOUSB is enabled or disabled on VBUS detection */
247         bool auto_ldousb_en;
248
249         struct palmas_pinctrl_platform_data *pinctrl_pdata;
250         struct palmas_extcon_platform_data *extcon_pdata;
251
252         int watchdog_timer_initial_period;
253 };
254
255 /* Define the palmas IRQ numbers */
256 enum palmas_irqs {
257         /* INT1 registers */
258         PALMAS_CHARG_DET_N_VBUS_OVV_IRQ,
259         PALMAS_PWRON_IRQ,
260         PALMAS_LONG_PRESS_KEY_IRQ,
261         PALMAS_RPWRON_IRQ,
262         PALMAS_PWRDOWN_IRQ,
263         PALMAS_HOTDIE_IRQ,
264         PALMAS_VSYS_MON_IRQ,
265         PALMAS_VBAT_MON_IRQ,
266         /* INT2 registers */
267         PALMAS_RTC_ALARM_IRQ,
268         PALMAS_RTC_TIMER_IRQ,
269         PALMAS_WDT_IRQ,
270         PALMAS_BATREMOVAL_IRQ,
271         PALMAS_RESET_IN_IRQ,
272         PALMAS_FBI_BB_IRQ,
273         PALMAS_SHORT_IRQ,
274         PALMAS_VAC_ACOK_IRQ,
275         /* INT3 registers */
276         PALMAS_GPADC_AUTO_0_IRQ,
277         PALMAS_GPADC_AUTO_1_IRQ,
278         PALMAS_GPADC_EOC_SW_IRQ,
279         PALMAS_GPADC_EOC_RT_IRQ,
280         PALMAS_ID_OTG_IRQ,
281         PALMAS_ID_IRQ,
282         PALMAS_VBUS_OTG_IRQ,
283         PALMAS_VBUS_IRQ,
284         /* INT4 registers */
285         PALMAS_GPIO_0_IRQ,
286         PALMAS_GPIO_1_IRQ,
287         PALMAS_GPIO_2_IRQ,
288         PALMAS_GPIO_3_IRQ,
289         PALMAS_GPIO_4_IRQ,
290         PALMAS_GPIO_5_IRQ,
291         PALMAS_GPIO_6_IRQ,
292         PALMAS_GPIO_7_IRQ,
293         /* Total Number IRQs */
294         PALMAS_NUM_IRQ,
295 };
296
297 struct palmas_pmic {
298         struct palmas *palmas;
299         struct device *dev;
300         struct regulator_desc desc[PALMAS_NUM_REGS];
301         struct regulator_dev *rdev[PALMAS_NUM_REGS];
302         struct mutex mutex;
303
304         int smps123;
305         int smps457;
306
307         unsigned int ramp_delay[PALMAS_NUM_REGS];
308         unsigned int current_mode_reg[PALMAS_NUM_REGS];
309
310         int range[PALMAS_REG_SMPS10];
311 };
312
313 /* defines so we can store the mux settings */
314 #define PALMAS_GPIO_0_MUXED                                     (1 << 0)
315 #define PALMAS_GPIO_1_MUXED                                     (1 << 1)
316 #define PALMAS_GPIO_2_MUXED                                     (1 << 2)
317 #define PALMAS_GPIO_3_MUXED                                     (1 << 3)
318 #define PALMAS_GPIO_4_MUXED                                     (1 << 4)
319 #define PALMAS_GPIO_5_MUXED                                     (1 << 5)
320 #define PALMAS_GPIO_6_MUXED                                     (1 << 6)
321 #define PALMAS_GPIO_7_MUXED                                     (1 << 7)
322
323 #define PALMAS_LED1_MUXED                                       (1 << 0)
324 #define PALMAS_LED2_MUXED                                       (1 << 1)
325
326 #define PALMAS_PWM1_MUXED                                       (1 << 0)
327 #define PALMAS_PWM2_MUXED                                       (1 << 1)
328
329 /* helper macro to get correct slave number */
330 #define PALMAS_BASE_TO_SLAVE(x)         ((x >> 8) - 1)
331 #define PALMAS_BASE_TO_REG(x, y)        ((x & 0xff) + y)
332 #define RTC_SLAVE                       0
333
334 /* Base addresses of IP blocks in Palmas */
335 #define PALMAS_SMPS_DVS_BASE                                    0x20
336 #define PALMAS_RTC_BASE                                         0x100
337 #define PALMAS_VALIDITY_BASE                                    0x118
338 #define PALMAS_SMPS_BASE                                        0x120
339 #define PALMAS_LDO_BASE                                         0x150
340 #define PALMAS_DVFS_BASE                                        0x180
341 #define PALMAS_PMU_CONTROL_BASE                                 0x1A0
342 #define PALMAS_RESOURCE_BASE                                    0x1D4
343 #define PALMAS_PU_PD_OD_BASE                                    0x1F4
344 #define PALMAS_LED_BASE                                         0x200
345 #define PALMAS_INTERRUPT_BASE                                   0x210
346 #define PALMAS_USB_OTG_BASE                                     0x250
347 #define PALMAS_VIBRATOR_BASE                                    0x270
348 #define PALMAS_GPIO_BASE                                        0x280
349 #define PALMAS_USB_BASE                                         0x290
350 #define PALMAS_GPADC_BASE                                       0x2C0
351 #define PALMAS_TRIM_GPADC_BASE                                  0x3CD
352 #define PALMAS_PAGE3_BASE                                       0x300
353
354 /* Registers for function RTC */
355 #define PALMAS_SECONDS_REG                                      0x0
356 #define PALMAS_MINUTES_REG                                      0x1
357 #define PALMAS_HOURS_REG                                        0x2
358 #define PALMAS_DAYS_REG                                         0x3
359 #define PALMAS_MONTHS_REG                                       0x4
360 #define PALMAS_YEARS_REG                                        0x5
361 #define PALMAS_WEEKS_REG                                        0x6
362 #define PALMAS_ALARM_SECONDS_REG                                0x8
363 #define PALMAS_ALARM_MINUTES_REG                                0x9
364 #define PALMAS_ALARM_HOURS_REG                                  0xA
365 #define PALMAS_ALARM_DAYS_REG                                   0xB
366 #define PALMAS_ALARM_MONTHS_REG                                 0xC
367 #define PALMAS_ALARM_YEARS_REG                                  0xD
368 #define PALMAS_RTC_CTRL_REG                                     0x10
369 #define PALMAS_RTC_STATUS_REG                                   0x11
370 #define PALMAS_RTC_INTERRUPTS_REG                               0x12
371 #define PALMAS_RTC_COMP_LSB_REG                                 0x13
372 #define PALMAS_RTC_COMP_MSB_REG                                 0x14
373 #define PALMAS_RTC_RES_PROG_REG                                 0x15
374 #define PALMAS_RTC_RESET_STATUS_REG                             0x16
375
376 /* Bit definitions for SECONDS_REG */
377 #define PALMAS_SECONDS_REG_SEC1_MASK                            0x70
378 #define PALMAS_SECONDS_REG_SEC1_SHIFT                           4
379 #define PALMAS_SECONDS_REG_SEC0_MASK                            0x0f
380 #define PALMAS_SECONDS_REG_SEC0_SHIFT                           0
381
382 /* Bit definitions for MINUTES_REG */
383 #define PALMAS_MINUTES_REG_MIN1_MASK                            0x70
384 #define PALMAS_MINUTES_REG_MIN1_SHIFT                           4
385 #define PALMAS_MINUTES_REG_MIN0_MASK                            0x0f
386 #define PALMAS_MINUTES_REG_MIN0_SHIFT                           0
387
388 /* Bit definitions for HOURS_REG */
389 #define PALMAS_HOURS_REG_PM_NAM                                 0x80
390 #define PALMAS_HOURS_REG_PM_NAM_SHIFT                           7
391 #define PALMAS_HOURS_REG_HOUR1_MASK                             0x30
392 #define PALMAS_HOURS_REG_HOUR1_SHIFT                            4
393 #define PALMAS_HOURS_REG_HOUR0_MASK                             0x0f
394 #define PALMAS_HOURS_REG_HOUR0_SHIFT                            0
395
396 /* Bit definitions for DAYS_REG */
397 #define PALMAS_DAYS_REG_DAY1_MASK                               0x30
398 #define PALMAS_DAYS_REG_DAY1_SHIFT                              4
399 #define PALMAS_DAYS_REG_DAY0_MASK                               0x0f
400 #define PALMAS_DAYS_REG_DAY0_SHIFT                              0
401
402 /* Bit definitions for MONTHS_REG */
403 #define PALMAS_MONTHS_REG_MONTH1                                0x10
404 #define PALMAS_MONTHS_REG_MONTH1_SHIFT                          4
405 #define PALMAS_MONTHS_REG_MONTH0_MASK                           0x0f
406 #define PALMAS_MONTHS_REG_MONTH0_SHIFT                          0
407
408 /* Bit definitions for YEARS_REG */
409 #define PALMAS_YEARS_REG_YEAR1_MASK                             0xf0
410 #define PALMAS_YEARS_REG_YEAR1_SHIFT                            4
411 #define PALMAS_YEARS_REG_YEAR0_MASK                             0x0f
412 #define PALMAS_YEARS_REG_YEAR0_SHIFT                            0
413
414 /* Bit definitions for WEEKS_REG */
415 #define PALMAS_WEEKS_REG_WEEK_MASK                              0x07
416 #define PALMAS_WEEKS_REG_WEEK_SHIFT                             0
417
418 /* Bit definitions for ALARM_SECONDS_REG */
419 #define PALMAS_ALARM_SECONDS_REG_ALARM_SEC1_MASK                0x70
420 #define PALMAS_ALARM_SECONDS_REG_ALARM_SEC1_SHIFT               4
421 #define PALMAS_ALARM_SECONDS_REG_ALARM_SEC0_MASK                0x0f
422 #define PALMAS_ALARM_SECONDS_REG_ALARM_SEC0_SHIFT               0
423
424 /* Bit definitions for ALARM_MINUTES_REG */
425 #define PALMAS_ALARM_MINUTES_REG_ALARM_MIN1_MASK                0x70
426 #define PALMAS_ALARM_MINUTES_REG_ALARM_MIN1_SHIFT               4
427 #define PALMAS_ALARM_MINUTES_REG_ALARM_MIN0_MASK                0x0f
428 #define PALMAS_ALARM_MINUTES_REG_ALARM_MIN0_SHIFT               0
429
430 /* Bit definitions for ALARM_HOURS_REG */
431 #define PALMAS_ALARM_HOURS_REG_ALARM_PM_NAM                     0x80
432 #define PALMAS_ALARM_HOURS_REG_ALARM_PM_NAM_SHIFT               7
433 #define PALMAS_ALARM_HOURS_REG_ALARM_HOUR1_MASK                 0x30
434 #define PALMAS_ALARM_HOURS_REG_ALARM_HOUR1_SHIFT                4
435 #define PALMAS_ALARM_HOURS_REG_ALARM_HOUR0_MASK                 0x0f
436 #define PALMAS_ALARM_HOURS_REG_ALARM_HOUR0_SHIFT                0
437
438 /* Bit definitions for ALARM_DAYS_REG */
439 #define PALMAS_ALARM_DAYS_REG_ALARM_DAY1_MASK                   0x30
440 #define PALMAS_ALARM_DAYS_REG_ALARM_DAY1_SHIFT                  4
441 #define PALMAS_ALARM_DAYS_REG_ALARM_DAY0_MASK                   0x0f
442 #define PALMAS_ALARM_DAYS_REG_ALARM_DAY0_SHIFT                  0
443
444 /* Bit definitions for ALARM_MONTHS_REG */
445 #define PALMAS_ALARM_MONTHS_REG_ALARM_MONTH1                    0x10
446 #define PALMAS_ALARM_MONTHS_REG_ALARM_MONTH1_SHIFT              4
447 #define PALMAS_ALARM_MONTHS_REG_ALARM_MONTH0_MASK               0x0f
448 #define PALMAS_ALARM_MONTHS_REG_ALARM_MONTH0_SHIFT              0
449
450 /* Bit definitions for ALARM_YEARS_REG */
451 #define PALMAS_ALARM_YEARS_REG_ALARM_YEAR1_MASK                 0xf0
452 #define PALMAS_ALARM_YEARS_REG_ALARM_YEAR1_SHIFT                4
453 #define PALMAS_ALARM_YEARS_REG_ALARM_YEAR0_MASK                 0x0f
454 #define PALMAS_ALARM_YEARS_REG_ALARM_YEAR0_SHIFT                0
455
456 /* Bit definitions for RTC_CTRL_REG */
457 #define PALMAS_RTC_CTRL_REG_RTC_V_OPT                           0x80
458 #define PALMAS_RTC_CTRL_REG_RTC_V_OPT_SHIFT                     7
459 #define PALMAS_RTC_CTRL_REG_GET_TIME                            0x40
460 #define PALMAS_RTC_CTRL_REG_GET_TIME_SHIFT                      6
461 #define PALMAS_RTC_CTRL_REG_SET_32_COUNTER                      0x20
462 #define PALMAS_RTC_CTRL_REG_SET_32_COUNTER_SHIFT                5
463 #define PALMAS_RTC_CTRL_REG_TEST_MODE                           0x10
464 #define PALMAS_RTC_CTRL_REG_TEST_MODE_SHIFT                     4
465 #define PALMAS_RTC_CTRL_REG_MODE_12_24                          0x08
466 #define PALMAS_RTC_CTRL_REG_MODE_12_24_SHIFT                    3
467 #define PALMAS_RTC_CTRL_REG_AUTO_COMP                           0x04
468 #define PALMAS_RTC_CTRL_REG_AUTO_COMP_SHIFT                     2
469 #define PALMAS_RTC_CTRL_REG_ROUND_30S                           0x02
470 #define PALMAS_RTC_CTRL_REG_ROUND_30S_SHIFT                     1
471 #define PALMAS_RTC_CTRL_REG_STOP_RTC                            0x01
472 #define PALMAS_RTC_CTRL_REG_STOP_RTC_SHIFT                      0
473
474 /* Bit definitions for RTC_STATUS_REG */
475 #define PALMAS_RTC_STATUS_REG_POWER_UP                          0x80
476 #define PALMAS_RTC_STATUS_REG_POWER_UP_SHIFT                    7
477 #define PALMAS_RTC_STATUS_REG_ALARM                             0x40
478 #define PALMAS_RTC_STATUS_REG_ALARM_SHIFT                       6
479 #define PALMAS_RTC_STATUS_REG_EVENT_1D                          0x20
480 #define PALMAS_RTC_STATUS_REG_EVENT_1D_SHIFT                    5
481 #define PALMAS_RTC_STATUS_REG_EVENT_1H                          0x10
482 #define PALMAS_RTC_STATUS_REG_EVENT_1H_SHIFT                    4
483 #define PALMAS_RTC_STATUS_REG_EVENT_1M                          0x08
484 #define PALMAS_RTC_STATUS_REG_EVENT_1M_SHIFT                    3
485 #define PALMAS_RTC_STATUS_REG_EVENT_1S                          0x04
486 #define PALMAS_RTC_STATUS_REG_EVENT_1S_SHIFT                    2
487 #define PALMAS_RTC_STATUS_REG_RUN                               0x02
488 #define PALMAS_RTC_STATUS_REG_RUN_SHIFT                         1
489
490 /* Bit definitions for RTC_INTERRUPTS_REG */
491 #define PALMAS_RTC_INTERRUPTS_REG_IT_SLEEP_MASK_EN              0x10
492 #define PALMAS_RTC_INTERRUPTS_REG_IT_SLEEP_MASK_EN_SHIFT        4
493 #define PALMAS_RTC_INTERRUPTS_REG_IT_ALARM                      0x08
494 #define PALMAS_RTC_INTERRUPTS_REG_IT_ALARM_SHIFT                3
495 #define PALMAS_RTC_INTERRUPTS_REG_IT_TIMER                      0x04
496 #define PALMAS_RTC_INTERRUPTS_REG_IT_TIMER_SHIFT                2
497 #define PALMAS_RTC_INTERRUPTS_REG_EVERY_MASK                    0x03
498 #define PALMAS_RTC_INTERRUPTS_REG_EVERY_SHIFT                   0
499
500 /* Bit definitions for RTC_COMP_LSB_REG */
501 #define PALMAS_RTC_COMP_LSB_REG_RTC_COMP_LSB_MASK               0xff
502 #define PALMAS_RTC_COMP_LSB_REG_RTC_COMP_LSB_SHIFT              0
503
504 /* Bit definitions for RTC_COMP_MSB_REG */
505 #define PALMAS_RTC_COMP_MSB_REG_RTC_COMP_MSB_MASK               0xff
506 #define PALMAS_RTC_COMP_MSB_REG_RTC_COMP_MSB_SHIFT              0
507
508 /* Bit definitions for RTC_RES_PROG_REG */
509 #define PALMAS_RTC_RES_PROG_REG_SW_RES_PROG_MASK                0x3f
510 #define PALMAS_RTC_RES_PROG_REG_SW_RES_PROG_SHIFT               0
511
512 /* Bit definitions for RTC_RESET_STATUS_REG */
513 #define PALMAS_RTC_RESET_STATUS_REG_RESET_STATUS                0x01
514 #define PALMAS_RTC_RESET_STATUS_REG_RESET_STATUS_SHIFT          0
515
516 /* Registers for function BACKUP */
517 #define PALMAS_BACKUP0                                          0x0
518 #define PALMAS_BACKUP1                                          0x1
519 #define PALMAS_BACKUP2                                          0x2
520 #define PALMAS_BACKUP3                                          0x3
521 #define PALMAS_BACKUP4                                          0x4
522 #define PALMAS_BACKUP5                                          0x5
523 #define PALMAS_BACKUP6                                          0x6
524 #define PALMAS_BACKUP7                                          0x7
525
526 /* Bit definitions for BACKUP0 */
527 #define PALMAS_BACKUP0_BACKUP_MASK                              0xff
528 #define PALMAS_BACKUP0_BACKUP_SHIFT                             0
529
530 /* Bit definitions for BACKUP1 */
531 #define PALMAS_BACKUP1_BACKUP_MASK                              0xff
532 #define PALMAS_BACKUP1_BACKUP_SHIFT                             0
533
534 /* Bit definitions for BACKUP2 */
535 #define PALMAS_BACKUP2_BACKUP_MASK                              0xff
536 #define PALMAS_BACKUP2_BACKUP_SHIFT                             0
537
538 /* Bit definitions for BACKUP3 */
539 #define PALMAS_BACKUP3_BACKUP_MASK                              0xff
540 #define PALMAS_BACKUP3_BACKUP_SHIFT                             0
541
542 /* Bit definitions for BACKUP4 */
543 #define PALMAS_BACKUP4_BACKUP_MASK                              0xff
544 #define PALMAS_BACKUP4_BACKUP_SHIFT                             0
545
546 /* Bit definitions for BACKUP5 */
547 #define PALMAS_BACKUP5_BACKUP_MASK                              0xff
548 #define PALMAS_BACKUP5_BACKUP_SHIFT                             0
549
550 /* Bit definitions for BACKUP6 */
551 #define PALMAS_BACKUP6_BACKUP_MASK                              0xff
552 #define PALMAS_BACKUP6_BACKUP_SHIFT                             0
553
554 /* Bit definitions for BACKUP7 */
555 #define PALMAS_BACKUP7_BACKUP_MASK                              0xff
556 #define PALMAS_BACKUP7_BACKUP_SHIFT                             0
557
558 /* Registers for function SMPS */
559 #define PALMAS_SMPS12_CTRL                                      0x0
560 #define PALMAS_SMPS12_TSTEP                                     0x1
561 #define PALMAS_SMPS12_FORCE                                     0x2
562 #define PALMAS_SMPS12_VOLTAGE                                   0x3
563 #define PALMAS_SMPS3_CTRL                                       0x4
564 #define PALMAS_SMPS3_VOLTAGE                                    0x7
565 #define PALMAS_SMPS45_CTRL                                      0x8
566 #define PALMAS_SMPS45_TSTEP                                     0x9
567 #define PALMAS_SMPS45_FORCE                                     0xA
568 #define PALMAS_SMPS45_VOLTAGE                                   0xB
569 #define PALMAS_SMPS6_CTRL                                       0xC
570 #define PALMAS_SMPS6_TSTEP                                      0xD
571 #define PALMAS_SMPS6_FORCE                                      0xE
572 #define PALMAS_SMPS6_VOLTAGE                                    0xF
573 #define PALMAS_SMPS7_CTRL                                       0x10
574 #define PALMAS_SMPS7_VOLTAGE                                    0x13
575 #define PALMAS_SMPS8_CTRL                                       0x14
576 #define PALMAS_SMPS8_TSTEP                                      0x15
577 #define PALMAS_SMPS8_FORCE                                      0x16
578 #define PALMAS_SMPS8_VOLTAGE                                    0x17
579 #define PALMAS_SMPS9_CTRL                                       0x18
580 #define PALMAS_SMPS9_VOLTAGE                                    0x1B
581 #define PALMAS_SMPS10_CTRL                                      0x1C
582 #define PALMAS_SMPS10_STATUS                                    0x1F
583 #define PALMAS_SMPS_CTRL                                        0x24
584 #define PALMAS_SMPS_PD_CTRL                                     0x25
585 #define PALMAS_SMPS_DITHER_EN                                   0x26
586 #define PALMAS_SMPS_THERMAL_EN                                  0x27
587 #define PALMAS_SMPS_THERMAL_STATUS                              0x28
588 #define PALMAS_SMPS_SHORT_STATUS                                0x29
589 #define PALMAS_SMPS_NEGATIVE_CURRENT_LIMIT_EN                   0x2A
590 #define PALMAS_SMPS_POWERGOOD_MASK1                             0x2B
591 #define PALMAS_SMPS_POWERGOOD_MASK2                             0x2C
592
593 /* Bit definitions for SMPS12_CTRL */
594 #define PALMAS_SMPS12_CTRL_WR_S                                 0x80
595 #define PALMAS_SMPS12_CTRL_WR_S_SHIFT                           7
596 #define PALMAS_SMPS12_CTRL_ROOF_FLOOR_EN                        0x40
597 #define PALMAS_SMPS12_CTRL_ROOF_FLOOR_EN_SHIFT                  6
598 #define PALMAS_SMPS12_CTRL_STATUS_MASK                          0x30
599 #define PALMAS_SMPS12_CTRL_STATUS_SHIFT                         4
600 #define PALMAS_SMPS12_CTRL_MODE_SLEEP_MASK                      0x0c
601 #define PALMAS_SMPS12_CTRL_MODE_SLEEP_SHIFT                     2
602 #define PALMAS_SMPS12_CTRL_MODE_ACTIVE_MASK                     0x03
603 #define PALMAS_SMPS12_CTRL_MODE_ACTIVE_SHIFT                    0
604
605 /* Bit definitions for SMPS12_TSTEP */
606 #define PALMAS_SMPS12_TSTEP_TSTEP_MASK                          0x03
607 #define PALMAS_SMPS12_TSTEP_TSTEP_SHIFT                         0
608
609 /* Bit definitions for SMPS12_FORCE */
610 #define PALMAS_SMPS12_FORCE_CMD                                 0x80
611 #define PALMAS_SMPS12_FORCE_CMD_SHIFT                           7
612 #define PALMAS_SMPS12_FORCE_VSEL_MASK                           0x7f
613 #define PALMAS_SMPS12_FORCE_VSEL_SHIFT                          0
614
615 /* Bit definitions for SMPS12_VOLTAGE */
616 #define PALMAS_SMPS12_VOLTAGE_RANGE                             0x80
617 #define PALMAS_SMPS12_VOLTAGE_RANGE_SHIFT                       7
618 #define PALMAS_SMPS12_VOLTAGE_VSEL_MASK                         0x7f
619 #define PALMAS_SMPS12_VOLTAGE_VSEL_SHIFT                        0
620
621 /* Bit definitions for SMPS3_CTRL */
622 #define PALMAS_SMPS3_CTRL_WR_S                                  0x80
623 #define PALMAS_SMPS3_CTRL_WR_S_SHIFT                            7
624 #define PALMAS_SMPS3_CTRL_STATUS_MASK                           0x30
625 #define PALMAS_SMPS3_CTRL_STATUS_SHIFT                          4
626 #define PALMAS_SMPS3_CTRL_MODE_SLEEP_MASK                       0x0c
627 #define PALMAS_SMPS3_CTRL_MODE_SLEEP_SHIFT                      2
628 #define PALMAS_SMPS3_CTRL_MODE_ACTIVE_MASK                      0x03
629 #define PALMAS_SMPS3_CTRL_MODE_ACTIVE_SHIFT                     0
630
631 /* Bit definitions for SMPS3_VOLTAGE */
632 #define PALMAS_SMPS3_VOLTAGE_RANGE                              0x80
633 #define PALMAS_SMPS3_VOLTAGE_RANGE_SHIFT                        7
634 #define PALMAS_SMPS3_VOLTAGE_VSEL_MASK                          0x7f
635 #define PALMAS_SMPS3_VOLTAGE_VSEL_SHIFT                         0
636
637 /* Bit definitions for SMPS45_CTRL */
638 #define PALMAS_SMPS45_CTRL_WR_S                                 0x80
639 #define PALMAS_SMPS45_CTRL_WR_S_SHIFT                           7
640 #define PALMAS_SMPS45_CTRL_ROOF_FLOOR_EN                        0x40
641 #define PALMAS_SMPS45_CTRL_ROOF_FLOOR_EN_SHIFT                  6
642 #define PALMAS_SMPS45_CTRL_STATUS_MASK                          0x30
643 #define PALMAS_SMPS45_CTRL_STATUS_SHIFT                         4
644 #define PALMAS_SMPS45_CTRL_MODE_SLEEP_MASK                      0x0c
645 #define PALMAS_SMPS45_CTRL_MODE_SLEEP_SHIFT                     2
646 #define PALMAS_SMPS45_CTRL_MODE_ACTIVE_MASK                     0x03
647 #define PALMAS_SMPS45_CTRL_MODE_ACTIVE_SHIFT                    0
648
649 /* Bit definitions for SMPS45_TSTEP */
650 #define PALMAS_SMPS45_TSTEP_TSTEP_MASK                          0x03
651 #define PALMAS_SMPS45_TSTEP_TSTEP_SHIFT                         0
652
653 /* Bit definitions for SMPS45_FORCE */
654 #define PALMAS_SMPS45_FORCE_CMD                                 0x80
655 #define PALMAS_SMPS45_FORCE_CMD_SHIFT                           7
656 #define PALMAS_SMPS45_FORCE_VSEL_MASK                           0x7f
657 #define PALMAS_SMPS45_FORCE_VSEL_SHIFT                          0
658
659 /* Bit definitions for SMPS45_VOLTAGE */
660 #define PALMAS_SMPS45_VOLTAGE_RANGE                             0x80
661 #define PALMAS_SMPS45_VOLTAGE_RANGE_SHIFT                       7
662 #define PALMAS_SMPS45_VOLTAGE_VSEL_MASK                         0x7f
663 #define PALMAS_SMPS45_VOLTAGE_VSEL_SHIFT                        0
664
665 /* Bit definitions for SMPS6_CTRL */
666 #define PALMAS_SMPS6_CTRL_WR_S                                  0x80
667 #define PALMAS_SMPS6_CTRL_WR_S_SHIFT                            7
668 #define PALMAS_SMPS6_CTRL_ROOF_FLOOR_EN                         0x40
669 #define PALMAS_SMPS6_CTRL_ROOF_FLOOR_EN_SHIFT                   6
670 #define PALMAS_SMPS6_CTRL_STATUS_MASK                           0x30
671 #define PALMAS_SMPS6_CTRL_STATUS_SHIFT                          4
672 #define PALMAS_SMPS6_CTRL_MODE_SLEEP_MASK                       0x0c
673 #define PALMAS_SMPS6_CTRL_MODE_SLEEP_SHIFT                      2
674 #define PALMAS_SMPS6_CTRL_MODE_ACTIVE_MASK                      0x03
675 #define PALMAS_SMPS6_CTRL_MODE_ACTIVE_SHIFT                     0
676
677 /* Bit definitions for SMPS6_TSTEP */
678 #define PALMAS_SMPS6_TSTEP_TSTEP_MASK                           0x03
679 #define PALMAS_SMPS6_TSTEP_TSTEP_SHIFT                          0
680
681 /* Bit definitions for SMPS6_FORCE */
682 #define PALMAS_SMPS6_FORCE_CMD                                  0x80
683 #define PALMAS_SMPS6_FORCE_CMD_SHIFT                            7
684 #define PALMAS_SMPS6_FORCE_VSEL_MASK                            0x7f
685 #define PALMAS_SMPS6_FORCE_VSEL_SHIFT                           0
686
687 /* Bit definitions for SMPS6_VOLTAGE */
688 #define PALMAS_SMPS6_VOLTAGE_RANGE                              0x80
689 #define PALMAS_SMPS6_VOLTAGE_RANGE_SHIFT                        7
690 #define PALMAS_SMPS6_VOLTAGE_VSEL_MASK                          0x7f
691 #define PALMAS_SMPS6_VOLTAGE_VSEL_SHIFT                         0
692
693 /* Bit definitions for SMPS7_CTRL */
694 #define PALMAS_SMPS7_CTRL_WR_S                                  0x80
695 #define PALMAS_SMPS7_CTRL_WR_S_SHIFT                            7
696 #define PALMAS_SMPS7_CTRL_STATUS_MASK                           0x30
697 #define PALMAS_SMPS7_CTRL_STATUS_SHIFT                          4
698 #define PALMAS_SMPS7_CTRL_MODE_SLEEP_MASK                       0x0c
699 #define PALMAS_SMPS7_CTRL_MODE_SLEEP_SHIFT                      2
700 #define PALMAS_SMPS7_CTRL_MODE_ACTIVE_MASK                      0x03
701 #define PALMAS_SMPS7_CTRL_MODE_ACTIVE_SHIFT                     0
702
703 /* Bit definitions for SMPS7_VOLTAGE */
704 #define PALMAS_SMPS7_VOLTAGE_RANGE                              0x80
705 #define PALMAS_SMPS7_VOLTAGE_RANGE_SHIFT                        7
706 #define PALMAS_SMPS7_VOLTAGE_VSEL_MASK                          0x7f
707 #define PALMAS_SMPS7_VOLTAGE_VSEL_SHIFT                         0
708
709 /* Bit definitions for SMPS8_CTRL */
710 #define PALMAS_SMPS8_CTRL_WR_S                                  0x80
711 #define PALMAS_SMPS8_CTRL_WR_S_SHIFT                            7
712 #define PALMAS_SMPS8_CTRL_ROOF_FLOOR_EN                         0x40
713 #define PALMAS_SMPS8_CTRL_ROOF_FLOOR_EN_SHIFT                   6
714 #define PALMAS_SMPS8_CTRL_STATUS_MASK                           0x30
715 #define PALMAS_SMPS8_CTRL_STATUS_SHIFT                          4
716 #define PALMAS_SMPS8_CTRL_MODE_SLEEP_MASK                       0x0c
717 #define PALMAS_SMPS8_CTRL_MODE_SLEEP_SHIFT                      2
718 #define PALMAS_SMPS8_CTRL_MODE_ACTIVE_MASK                      0x03
719 #define PALMAS_SMPS8_CTRL_MODE_ACTIVE_SHIFT                     0
720
721 /* Bit definitions for SMPS8_TSTEP */
722 #define PALMAS_SMPS8_TSTEP_TSTEP_MASK                           0x03
723 #define PALMAS_SMPS8_TSTEP_TSTEP_SHIFT                          0
724
725 /* Bit definitions for SMPS8_FORCE */
726 #define PALMAS_SMPS8_FORCE_CMD                                  0x80
727 #define PALMAS_SMPS8_FORCE_CMD_SHIFT                            7
728 #define PALMAS_SMPS8_FORCE_VSEL_MASK                            0x7f
729 #define PALMAS_SMPS8_FORCE_VSEL_SHIFT                           0
730
731 /* Bit definitions for SMPS8_VOLTAGE */
732 #define PALMAS_SMPS8_VOLTAGE_RANGE                              0x80
733 #define PALMAS_SMPS8_VOLTAGE_RANGE_SHIFT                        7
734 #define PALMAS_SMPS8_VOLTAGE_VSEL_MASK                          0x7f
735 #define PALMAS_SMPS8_VOLTAGE_VSEL_SHIFT                         0
736
737 /* Bit definitions for SMPS9_CTRL */
738 #define PALMAS_SMPS9_CTRL_WR_S                                  0x80
739 #define PALMAS_SMPS9_CTRL_WR_S_SHIFT                            7
740 #define PALMAS_SMPS9_CTRL_STATUS_MASK                           0x30
741 #define PALMAS_SMPS9_CTRL_STATUS_SHIFT                          4
742 #define PALMAS_SMPS9_CTRL_MODE_SLEEP_MASK                       0x0c
743 #define PALMAS_SMPS9_CTRL_MODE_SLEEP_SHIFT                      2
744 #define PALMAS_SMPS9_CTRL_MODE_ACTIVE_MASK                      0x03
745 #define PALMAS_SMPS9_CTRL_MODE_ACTIVE_SHIFT                     0
746
747 /* Bit definitions for SMPS9_VOLTAGE */
748 #define PALMAS_SMPS9_VOLTAGE_RANGE                              0x80
749 #define PALMAS_SMPS9_VOLTAGE_RANGE_SHIFT                        7
750 #define PALMAS_SMPS9_VOLTAGE_VSEL_MASK                          0x7f
751 #define PALMAS_SMPS9_VOLTAGE_VSEL_SHIFT                         0
752
753 /* Bit definitions for SMPS10_CTRL */
754 #define PALMAS_SMPS10_CTRL_MODE_SLEEP_MASK                      0xf0
755 #define PALMAS_SMPS10_CTRL_MODE_SLEEP_SHIFT                     4
756 #define PALMAS_SMPS10_CTRL_MODE_ACTIVE_MASK                     0x0f
757 #define PALMAS_SMPS10_CTRL_MODE_ACTIVE_SHIFT                    0
758
759 /* Bit definitions for SMPS10_STATUS */
760 #define PALMAS_SMPS10_STATUS_STATUS_MASK                        0x0f
761 #define PALMAS_SMPS10_STATUS_STATUS_SHIFT                       0
762
763 /* Bit definitions for SMPS_CTRL */
764 #define PALMAS_SMPS_CTRL_SMPS45_SMPS457_EN                      0x20
765 #define PALMAS_SMPS_CTRL_SMPS45_SMPS457_EN_SHIFT                5
766 #define PALMAS_SMPS_CTRL_SMPS12_SMPS123_EN                      0x10
767 #define PALMAS_SMPS_CTRL_SMPS12_SMPS123_EN_SHIFT                4
768 #define PALMAS_SMPS_CTRL_SMPS45_PHASE_CTRL_MASK                 0x0c
769 #define PALMAS_SMPS_CTRL_SMPS45_PHASE_CTRL_SHIFT                2
770 #define PALMAS_SMPS_CTRL_SMPS123_PHASE_CTRL_MASK                0x03
771 #define PALMAS_SMPS_CTRL_SMPS123_PHASE_CTRL_SHIFT               0
772
773 /* Bit definitions for SMPS_PD_CTRL */
774 #define PALMAS_SMPS_PD_CTRL_SMPS9                               0x40
775 #define PALMAS_SMPS_PD_CTRL_SMPS9_SHIFT                         6
776 #define PALMAS_SMPS_PD_CTRL_SMPS8                               0x20
777 #define PALMAS_SMPS_PD_CTRL_SMPS8_SHIFT                         5
778 #define PALMAS_SMPS_PD_CTRL_SMPS7                               0x10
779 #define PALMAS_SMPS_PD_CTRL_SMPS7_SHIFT                         4
780 #define PALMAS_SMPS_PD_CTRL_SMPS6                               0x08
781 #define PALMAS_SMPS_PD_CTRL_SMPS6_SHIFT                         3
782 #define PALMAS_SMPS_PD_CTRL_SMPS45                              0x04
783 #define PALMAS_SMPS_PD_CTRL_SMPS45_SHIFT                        2
784 #define PALMAS_SMPS_PD_CTRL_SMPS3                               0x02
785 #define PALMAS_SMPS_PD_CTRL_SMPS3_SHIFT                         1
786 #define PALMAS_SMPS_PD_CTRL_SMPS12                              0x01
787 #define PALMAS_SMPS_PD_CTRL_SMPS12_SHIFT                        0
788
789 /* Bit definitions for SMPS_THERMAL_EN */
790 #define PALMAS_SMPS_THERMAL_EN_SMPS9                            0x40
791 #define PALMAS_SMPS_THERMAL_EN_SMPS9_SHIFT                      6
792 #define PALMAS_SMPS_THERMAL_EN_SMPS8                            0x20
793 #define PALMAS_SMPS_THERMAL_EN_SMPS8_SHIFT                      5
794 #define PALMAS_SMPS_THERMAL_EN_SMPS6                            0x08
795 #define PALMAS_SMPS_THERMAL_EN_SMPS6_SHIFT                      3
796 #define PALMAS_SMPS_THERMAL_EN_SMPS457                          0x04
797 #define PALMAS_SMPS_THERMAL_EN_SMPS457_SHIFT                    2
798 #define PALMAS_SMPS_THERMAL_EN_SMPS123                          0x01
799 #define PALMAS_SMPS_THERMAL_EN_SMPS123_SHIFT                    0
800
801 /* Bit definitions for SMPS_THERMAL_STATUS */
802 #define PALMAS_SMPS_THERMAL_STATUS_SMPS9                        0x40
803 #define PALMAS_SMPS_THERMAL_STATUS_SMPS9_SHIFT                  6
804 #define PALMAS_SMPS_THERMAL_STATUS_SMPS8                        0x20
805 #define PALMAS_SMPS_THERMAL_STATUS_SMPS8_SHIFT                  5
806 #define PALMAS_SMPS_THERMAL_STATUS_SMPS6                        0x08
807 #define PALMAS_SMPS_THERMAL_STATUS_SMPS6_SHIFT                  3
808 #define PALMAS_SMPS_THERMAL_STATUS_SMPS457                      0x04
809 #define PALMAS_SMPS_THERMAL_STATUS_SMPS457_SHIFT                2
810 #define PALMAS_SMPS_THERMAL_STATUS_SMPS123                      0x01
811 #define PALMAS_SMPS_THERMAL_STATUS_SMPS123_SHIFT                0
812
813 /* Bit definitions for SMPS_SHORT_STATUS */
814 #define PALMAS_SMPS_SHORT_STATUS_SMPS10                         0x80
815 #define PALMAS_SMPS_SHORT_STATUS_SMPS10_SHIFT                   7
816 #define PALMAS_SMPS_SHORT_STATUS_SMPS9                          0x40
817 #define PALMAS_SMPS_SHORT_STATUS_SMPS9_SHIFT                    6
818 #define PALMAS_SMPS_SHORT_STATUS_SMPS8                          0x20
819 #define PALMAS_SMPS_SHORT_STATUS_SMPS8_SHIFT                    5
820 #define PALMAS_SMPS_SHORT_STATUS_SMPS7                          0x10
821 #define PALMAS_SMPS_SHORT_STATUS_SMPS7_SHIFT                    4
822 #define PALMAS_SMPS_SHORT_STATUS_SMPS6                          0x08
823 #define PALMAS_SMPS_SHORT_STATUS_SMPS6_SHIFT                    3
824 #define PALMAS_SMPS_SHORT_STATUS_SMPS45                         0x04
825 #define PALMAS_SMPS_SHORT_STATUS_SMPS45_SHIFT                   2
826 #define PALMAS_SMPS_SHORT_STATUS_SMPS3                          0x02
827 #define PALMAS_SMPS_SHORT_STATUS_SMPS3_SHIFT                    1
828 #define PALMAS_SMPS_SHORT_STATUS_SMPS12                         0x01
829 #define PALMAS_SMPS_SHORT_STATUS_SMPS12_SHIFT                   0
830
831 /* Bit definitions for SMPS_NEGATIVE_CURRENT_LIMIT_EN */
832 #define PALMAS_SMPS_NEGATIVE_CURRENT_LIMIT_EN_SMPS9             0x40
833 #define PALMAS_SMPS_NEGATIVE_CURRENT_LIMIT_EN_SMPS9_SHIFT       6
834 #define PALMAS_SMPS_NEGATIVE_CURRENT_LIMIT_EN_SMPS8             0x20
835 #define PALMAS_SMPS_NEGATIVE_CURRENT_LIMIT_EN_SMPS8_SHIFT       5
836 #define PALMAS_SMPS_NEGATIVE_CURRENT_LIMIT_EN_SMPS7             0x10
837 #define PALMAS_SMPS_NEGATIVE_CURRENT_LIMIT_EN_SMPS7_SHIFT       4
838 #define PALMAS_SMPS_NEGATIVE_CURRENT_LIMIT_EN_SMPS6             0x08
839 #define PALMAS_SMPS_NEGATIVE_CURRENT_LIMIT_EN_SMPS6_SHIFT       3
840 #define PALMAS_SMPS_NEGATIVE_CURRENT_LIMIT_EN_SMPS45            0x04
841 #define PALMAS_SMPS_NEGATIVE_CURRENT_LIMIT_EN_SMPS45_SHIFT      2
842 #define PALMAS_SMPS_NEGATIVE_CURRENT_LIMIT_EN_SMPS3             0x02
843 #define PALMAS_SMPS_NEGATIVE_CURRENT_LIMIT_EN_SMPS3_SHIFT       1
844 #define PALMAS_SMPS_NEGATIVE_CURRENT_LIMIT_EN_SMPS12            0x01
845 #define PALMAS_SMPS_NEGATIVE_CURRENT_LIMIT_EN_SMPS12_SHIFT      0
846
847 /* Bit definitions for SMPS_POWERGOOD_MASK1 */
848 #define PALMAS_SMPS_POWERGOOD_MASK1_SMPS10                      0x80
849 #define PALMAS_SMPS_POWERGOOD_MASK1_SMPS10_SHIFT                7
850 #define PALMAS_SMPS_POWERGOOD_MASK1_SMPS9                       0x40
851 #define PALMAS_SMPS_POWERGOOD_MASK1_SMPS9_SHIFT                 6
852 #define PALMAS_SMPS_POWERGOOD_MASK1_SMPS8                       0x20
853 #define PALMAS_SMPS_POWERGOOD_MASK1_SMPS8_SHIFT                 5
854 #define PALMAS_SMPS_POWERGOOD_MASK1_SMPS7                       0x10
855 #define PALMAS_SMPS_POWERGOOD_MASK1_SMPS7_SHIFT                 4
856 #define PALMAS_SMPS_POWERGOOD_MASK1_SMPS6                       0x08
857 #define PALMAS_SMPS_POWERGOOD_MASK1_SMPS6_SHIFT                 3
858 #define PALMAS_SMPS_POWERGOOD_MASK1_SMPS45                      0x04
859 #define PALMAS_SMPS_POWERGOOD_MASK1_SMPS45_SHIFT                2
860 #define PALMAS_SMPS_POWERGOOD_MASK1_SMPS3                       0x02
861 #define PALMAS_SMPS_POWERGOOD_MASK1_SMPS3_SHIFT                 1
862 #define PALMAS_SMPS_POWERGOOD_MASK1_SMPS12                      0x01
863 #define PALMAS_SMPS_POWERGOOD_MASK1_SMPS12_SHIFT                0
864
865 /* Bit definitions for SMPS_POWERGOOD_MASK2 */
866 #define PALMAS_SMPS_POWERGOOD_MASK2_POWERGOOD_TYPE_SELECT       0x80
867 #define PALMAS_SMPS_POWERGOOD_MASK2_POWERGOOD_TYPE_SELECT_SHIFT 7
868 #define PALMAS_SMPS_POWERGOOD_MASK2_GPIO_7                      0x04
869 #define PALMAS_SMPS_POWERGOOD_MASK2_GPIO_7_SHIFT                2
870 #define PALMAS_SMPS_POWERGOOD_MASK2_VBUS                        0x02
871 #define PALMAS_SMPS_POWERGOOD_MASK2_VBUS_SHIFT                  1
872 #define PALMAS_SMPS_POWERGOOD_MASK2_ACOK                        0x01
873 #define PALMAS_SMPS_POWERGOOD_MASK2_ACOK_SHIFT                  0
874
875 /* Registers for function LDO */
876 #define PALMAS_LDO1_CTRL                                        0x0
877 #define PALMAS_LDO1_VOLTAGE                                     0x1
878 #define PALMAS_LDO2_CTRL                                        0x2
879 #define PALMAS_LDO2_VOLTAGE                                     0x3
880 #define PALMAS_LDO3_CTRL                                        0x4
881 #define PALMAS_LDO3_VOLTAGE                                     0x5
882 #define PALMAS_LDO4_CTRL                                        0x6
883 #define PALMAS_LDO4_VOLTAGE                                     0x7
884 #define PALMAS_LDO5_CTRL                                        0x8
885 #define PALMAS_LDO5_VOLTAGE                                     0x9
886 #define PALMAS_LDO6_CTRL                                        0xA
887 #define PALMAS_LDO6_VOLTAGE                                     0xB
888 #define PALMAS_LDO7_CTRL                                        0xC
889 #define PALMAS_LDO7_VOLTAGE                                     0xD
890 #define PALMAS_LDO8_CTRL                                        0xE
891 #define PALMAS_LDO8_VOLTAGE                                     0xF
892 #define PALMAS_LDO9_CTRL                                        0x10
893 #define PALMAS_LDO9_VOLTAGE                                     0x11
894 #define PALMAS_LDOLN_CTRL                                       0x12
895 #define PALMAS_LDOLN_VOLTAGE                                    0x13
896 #define PALMAS_LDOUSB_CTRL                                      0x14
897 #define PALMAS_LDOUSB_VOLTAGE                                   0x15
898 #define PALMAS_LDO_CTRL                                         0x1A
899 #define PALMAS_LDO_PD_CTRL1                                     0x1B
900 #define PALMAS_LDO_PD_CTRL2                                     0x1C
901 #define PALMAS_LDO_SHORT_STATUS1                                0x1D
902 #define PALMAS_LDO_SHORT_STATUS2                                0x1E
903
904 /* Bit definitions for LDO1_CTRL */
905 #define PALMAS_LDO1_CTRL_WR_S                                   0x80
906 #define PALMAS_LDO1_CTRL_WR_S_SHIFT                             7
907 #define PALMAS_LDO1_CTRL_STATUS                                 0x10
908 #define PALMAS_LDO1_CTRL_STATUS_SHIFT                           4
909 #define PALMAS_LDO1_CTRL_MODE_SLEEP                             0x04
910 #define PALMAS_LDO1_CTRL_MODE_SLEEP_SHIFT                       2
911 #define PALMAS_LDO1_CTRL_MODE_ACTIVE                            0x01
912 #define PALMAS_LDO1_CTRL_MODE_ACTIVE_SHIFT                      0
913
914 /* Bit definitions for LDO1_VOLTAGE */
915 #define PALMAS_LDO1_VOLTAGE_VSEL_MASK                           0x3f
916 #define PALMAS_LDO1_VOLTAGE_VSEL_SHIFT                          0
917
918 /* Bit definitions for LDO2_CTRL */
919 #define PALMAS_LDO2_CTRL_WR_S                                   0x80
920 #define PALMAS_LDO2_CTRL_WR_S_SHIFT                             7
921 #define PALMAS_LDO2_CTRL_STATUS                                 0x10
922 #define PALMAS_LDO2_CTRL_STATUS_SHIFT                           4
923 #define PALMAS_LDO2_CTRL_MODE_SLEEP                             0x04
924 #define PALMAS_LDO2_CTRL_MODE_SLEEP_SHIFT                       2
925 #define PALMAS_LDO2_CTRL_MODE_ACTIVE                            0x01
926 #define PALMAS_LDO2_CTRL_MODE_ACTIVE_SHIFT                      0
927
928 /* Bit definitions for LDO2_VOLTAGE */
929 #define PALMAS_LDO2_VOLTAGE_VSEL_MASK                           0x3f
930 #define PALMAS_LDO2_VOLTAGE_VSEL_SHIFT                          0
931
932 /* Bit definitions for LDO3_CTRL */
933 #define PALMAS_LDO3_CTRL_WR_S                                   0x80
934 #define PALMAS_LDO3_CTRL_WR_S_SHIFT                             7
935 #define PALMAS_LDO3_CTRL_STATUS                                 0x10
936 #define PALMAS_LDO3_CTRL_STATUS_SHIFT                           4
937 #define PALMAS_LDO3_CTRL_MODE_SLEEP                             0x04
938 #define PALMAS_LDO3_CTRL_MODE_SLEEP_SHIFT                       2
939 #define PALMAS_LDO3_CTRL_MODE_ACTIVE                            0x01
940 #define PALMAS_LDO3_CTRL_MODE_ACTIVE_SHIFT                      0
941
942 /* Bit definitions for LDO3_VOLTAGE */
943 #define PALMAS_LDO3_VOLTAGE_VSEL_MASK                           0x3f
944 #define PALMAS_LDO3_VOLTAGE_VSEL_SHIFT                          0
945
946 /* Bit definitions for LDO4_CTRL */
947 #define PALMAS_LDO4_CTRL_WR_S                                   0x80
948 #define PALMAS_LDO4_CTRL_WR_S_SHIFT                             7
949 #define PALMAS_LDO4_CTRL_STATUS                                 0x10
950 #define PALMAS_LDO4_CTRL_STATUS_SHIFT                           4
951 #define PALMAS_LDO4_CTRL_MODE_SLEEP                             0x04
952 #define PALMAS_LDO4_CTRL_MODE_SLEEP_SHIFT                       2
953 #define PALMAS_LDO4_CTRL_MODE_ACTIVE                            0x01
954 #define PALMAS_LDO4_CTRL_MODE_ACTIVE_SHIFT                      0
955
956 /* Bit definitions for LDO4_VOLTAGE */
957 #define PALMAS_LDO4_VOLTAGE_VSEL_MASK                           0x3f
958 #define PALMAS_LDO4_VOLTAGE_VSEL_SHIFT                          0
959
960 /* Bit definitions for LDO5_CTRL */
961 #define PALMAS_LDO5_CTRL_WR_S                                   0x80
962 #define PALMAS_LDO5_CTRL_WR_S_SHIFT                             7
963 #define PALMAS_LDO5_CTRL_STATUS                                 0x10
964 #define PALMAS_LDO5_CTRL_STATUS_SHIFT                           4
965 #define PALMAS_LDO5_CTRL_MODE_SLEEP                             0x04
966 #define PALMAS_LDO5_CTRL_MODE_SLEEP_SHIFT                       2
967 #define PALMAS_LDO5_CTRL_MODE_ACTIVE                            0x01
968 #define PALMAS_LDO5_CTRL_MODE_ACTIVE_SHIFT                      0
969
970 /* Bit definitions for LDO5_VOLTAGE */
971 #define PALMAS_LDO5_VOLTAGE_VSEL_MASK                           0x3f
972 #define PALMAS_LDO5_VOLTAGE_VSEL_SHIFT                          0
973
974 /* Bit definitions for LDO6_CTRL */
975 #define PALMAS_LDO6_CTRL_WR_S                                   0x80
976 #define PALMAS_LDO6_CTRL_WR_S_SHIFT                             7
977 #define PALMAS_LDO6_CTRL_LDO_VIB_EN                             0x40
978 #define PALMAS_LDO6_CTRL_LDO_VIB_EN_SHIFT                       6
979 #define PALMAS_LDO6_CTRL_STATUS                                 0x10
980 #define PALMAS_LDO6_CTRL_STATUS_SHIFT                           4
981 #define PALMAS_LDO6_CTRL_MODE_SLEEP                             0x04
982 #define PALMAS_LDO6_CTRL_MODE_SLEEP_SHIFT                       2
983 #define PALMAS_LDO6_CTRL_MODE_ACTIVE                            0x01
984 #define PALMAS_LDO6_CTRL_MODE_ACTIVE_SHIFT                      0
985
986 /* Bit definitions for LDO6_VOLTAGE */
987 #define PALMAS_LDO6_VOLTAGE_VSEL_MASK                           0x3f
988 #define PALMAS_LDO6_VOLTAGE_VSEL_SHIFT                          0
989
990 /* Bit definitions for LDO7_CTRL */
991 #define PALMAS_LDO7_CTRL_WR_S                                   0x80
992 #define PALMAS_LDO7_CTRL_WR_S_SHIFT                             7
993 #define PALMAS_LDO7_CTRL_STATUS                                 0x10
994 #define PALMAS_LDO7_CTRL_STATUS_SHIFT                           4
995 #define PALMAS_LDO7_CTRL_MODE_SLEEP                             0x04
996 #define PALMAS_LDO7_CTRL_MODE_SLEEP_SHIFT                       2
997 #define PALMAS_LDO7_CTRL_MODE_ACTIVE                            0x01
998 #define PALMAS_LDO7_CTRL_MODE_ACTIVE_SHIFT                      0
999
1000 /* Bit definitions for LDO7_VOLTAGE */
1001 #define PALMAS_LDO7_VOLTAGE_VSEL_MASK                           0x3f
1002 #define PALMAS_LDO7_VOLTAGE_VSEL_SHIFT                          0
1003
1004 /* Bit definitions for LDO8_CTRL */
1005 #define PALMAS_LDO8_CTRL_WR_S                                   0x80
1006 #define PALMAS_LDO8_CTRL_WR_S_SHIFT                             7
1007 #define PALMAS_LDO8_CTRL_LDO_TRACKING_EN                        0x40
1008 #define PALMAS_LDO8_CTRL_LDO_TRACKING_EN_SHIFT                  6
1009 #define PALMAS_LDO8_CTRL_STATUS                                 0x10
1010 #define PALMAS_LDO8_CTRL_STATUS_SHIFT                           4
1011 #define PALMAS_LDO8_CTRL_MODE_SLEEP                             0x04
1012 #define PALMAS_LDO8_CTRL_MODE_SLEEP_SHIFT                       2
1013 #define PALMAS_LDO8_CTRL_MODE_ACTIVE                            0x01
1014 #define PALMAS_LDO8_CTRL_MODE_ACTIVE_SHIFT                      0
1015
1016 /* Bit definitions for LDO8_VOLTAGE */
1017 #define PALMAS_LDO8_VOLTAGE_VSEL_MASK                           0x3f
1018 #define PALMAS_LDO8_VOLTAGE_VSEL_SHIFT                          0
1019
1020 /* Bit definitions for LDO9_CTRL */
1021 #define PALMAS_LDO9_CTRL_WR_S                                   0x80
1022 #define PALMAS_LDO9_CTRL_WR_S_SHIFT                             7
1023 #define PALMAS_LDO9_CTRL_LDO_BYPASS_EN                          0x40
1024 #define PALMAS_LDO9_CTRL_LDO_BYPASS_EN_SHIFT                    6
1025 #define PALMAS_LDO9_CTRL_STATUS                                 0x10
1026 #define PALMAS_LDO9_CTRL_STATUS_SHIFT                           4
1027 #define PALMAS_LDO9_CTRL_MODE_SLEEP                             0x04
1028 #define PALMAS_LDO9_CTRL_MODE_SLEEP_SHIFT                       2
1029 #define PALMAS_LDO9_CTRL_MODE_ACTIVE                            0x01
1030 #define PALMAS_LDO9_CTRL_MODE_ACTIVE_SHIFT                      0
1031
1032 /* Bit definitions for LDO9_VOLTAGE */
1033 #define PALMAS_LDO9_VOLTAGE_VSEL_MASK                           0x3f
1034 #define PALMAS_LDO9_VOLTAGE_VSEL_SHIFT                          0
1035
1036 /* Bit definitions for LDOLN_CTRL */
1037 #define PALMAS_LDOLN_CTRL_WR_S                                  0x80
1038 #define PALMAS_LDOLN_CTRL_WR_S_SHIFT                            7
1039 #define PALMAS_LDOLN_CTRL_STATUS                                0x10
1040 #define PALMAS_LDOLN_CTRL_STATUS_SHIFT                          4
1041 #define PALMAS_LDOLN_CTRL_MODE_SLEEP                            0x04
1042 #define PALMAS_LDOLN_CTRL_MODE_SLEEP_SHIFT                      2
1043 #define PALMAS_LDOLN_CTRL_MODE_ACTIVE                           0x01
1044 #define PALMAS_LDOLN_CTRL_MODE_ACTIVE_SHIFT                     0
1045
1046 /* Bit definitions for LDOLN_VOLTAGE */
1047 #define PALMAS_LDOLN_VOLTAGE_VSEL_MASK                          0x3f
1048 #define PALMAS_LDOLN_VOLTAGE_VSEL_SHIFT                         0
1049
1050 /* Bit definitions for LDOUSB_CTRL */
1051 #define PALMAS_LDOUSB_CTRL_WR_S                                 0x80
1052 #define PALMAS_LDOUSB_CTRL_WR_S_SHIFT                           7
1053 #define PALMAS_LDOUSB_CTRL_STATUS                               0x10
1054 #define PALMAS_LDOUSB_CTRL_STATUS_SHIFT                         4
1055 #define PALMAS_LDOUSB_CTRL_MODE_SLEEP                           0x04
1056 #define PALMAS_LDOUSB_CTRL_MODE_SLEEP_SHIFT                     2
1057 #define PALMAS_LDOUSB_CTRL_MODE_ACTIVE                          0x01
1058 #define PALMAS_LDOUSB_CTRL_MODE_ACTIVE_SHIFT                    0
1059
1060 /* Bit definitions for LDOUSB_VOLTAGE */
1061 #define PALMAS_LDOUSB_VOLTAGE_VSEL_MASK                         0x3f
1062 #define PALMAS_LDOUSB_VOLTAGE_VSEL_SHIFT                        0
1063
1064 /* Bit definitions for LDO_CTRL */
1065 #define PALMAS_LDO_CTRL_LDOUSB_ON_VBUS_VSYS                     0x01
1066 #define PALMAS_LDO_CTRL_LDOUSB_ON_VBUS_VSYS_SHIFT               0
1067
1068 /* Bit definitions for LDO_PD_CTRL1 */
1069 #define PALMAS_LDO_PD_CTRL1_LDO8                                0x80
1070 #define PALMAS_LDO_PD_CTRL1_LDO8_SHIFT                          7
1071 #define PALMAS_LDO_PD_CTRL1_LDO7                                0x40
1072 #define PALMAS_LDO_PD_CTRL1_LDO7_SHIFT                          6
1073 #define PALMAS_LDO_PD_CTRL1_LDO6                                0x20
1074 #define PALMAS_LDO_PD_CTRL1_LDO6_SHIFT                          5
1075 #define PALMAS_LDO_PD_CTRL1_LDO5                                0x10
1076 #define PALMAS_LDO_PD_CTRL1_LDO5_SHIFT                          4
1077 #define PALMAS_LDO_PD_CTRL1_LDO4                                0x08
1078 #define PALMAS_LDO_PD_CTRL1_LDO4_SHIFT                          3
1079 #define PALMAS_LDO_PD_CTRL1_LDO3                                0x04
1080 #define PALMAS_LDO_PD_CTRL1_LDO3_SHIFT                          2
1081 #define PALMAS_LDO_PD_CTRL1_LDO2                                0x02
1082 #define PALMAS_LDO_PD_CTRL1_LDO2_SHIFT                          1
1083 #define PALMAS_LDO_PD_CTRL1_LDO1                                0x01
1084 #define PALMAS_LDO_PD_CTRL1_LDO1_SHIFT                          0
1085
1086 /* Bit definitions for LDO_PD_CTRL2 */
1087 #define PALMAS_LDO_PD_CTRL2_LDOUSB                              0x04
1088 #define PALMAS_LDO_PD_CTRL2_LDOUSB_SHIFT                        2
1089 #define PALMAS_LDO_PD_CTRL2_LDOLN                               0x02
1090 #define PALMAS_LDO_PD_CTRL2_LDOLN_SHIFT                         1
1091 #define PALMAS_LDO_PD_CTRL2_LDO9                                0x01
1092 #define PALMAS_LDO_PD_CTRL2_LDO9_SHIFT                          0
1093
1094 /* Bit definitions for LDO_SHORT_STATUS1 */
1095 #define PALMAS_LDO_SHORT_STATUS1_LDO8                           0x80
1096 #define PALMAS_LDO_SHORT_STATUS1_LDO8_SHIFT                     7
1097 #define PALMAS_LDO_SHORT_STATUS1_LDO7                           0x40
1098 #define PALMAS_LDO_SHORT_STATUS1_LDO7_SHIFT                     6
1099 #define PALMAS_LDO_SHORT_STATUS1_LDO6                           0x20
1100 #define PALMAS_LDO_SHORT_STATUS1_LDO6_SHIFT                     5
1101 #define PALMAS_LDO_SHORT_STATUS1_LDO5                           0x10
1102 #define PALMAS_LDO_SHORT_STATUS1_LDO5_SHIFT                     4
1103 #define PALMAS_LDO_SHORT_STATUS1_LDO4                           0x08
1104 #define PALMAS_LDO_SHORT_STATUS1_LDO4_SHIFT                     3
1105 #define PALMAS_LDO_SHORT_STATUS1_LDO3                           0x04
1106 #define PALMAS_LDO_SHORT_STATUS1_LDO3_SHIFT                     2
1107 #define PALMAS_LDO_SHORT_STATUS1_LDO2                           0x02
1108 #define PALMAS_LDO_SHORT_STATUS1_LDO2_SHIFT                     1
1109 #define PALMAS_LDO_SHORT_STATUS1_LDO1                           0x01
1110 #define PALMAS_LDO_SHORT_STATUS1_LDO1_SHIFT                     0
1111
1112 /* Bit definitions for LDO_SHORT_STATUS2 */
1113 #define PALMAS_LDO_SHORT_STATUS2_LDOVANA                        0x08
1114 #define PALMAS_LDO_SHORT_STATUS2_LDOVANA_SHIFT                  3
1115 #define PALMAS_LDO_SHORT_STATUS2_LDOUSB                         0x04
1116 #define PALMAS_LDO_SHORT_STATUS2_LDOUSB_SHIFT                   2
1117 #define PALMAS_LDO_SHORT_STATUS2_LDOLN                          0x02
1118 #define PALMAS_LDO_SHORT_STATUS2_LDOLN_SHIFT                    1
1119 #define PALMAS_LDO_SHORT_STATUS2_LDO9                           0x01
1120 #define PALMAS_LDO_SHORT_STATUS2_LDO9_SHIFT                     0
1121
1122 /* Registers for function DVFS Func */
1123 #define PALMAS_SMPS_DVFS1_CTRL                                  0x0
1124 #define PALMAS_SMPS_DVFS1_ENABLE_SHIFT                          0
1125 #define PALMAS_SMPS_DVFS1_OFFSET_STEP_SHIFT                     1
1126 #define PALMAS_SMPS_DVFS1_ENABLE_RST_SHIFT                      2
1127 #define PALMAS_SMPS_DVFS1_RESTORE_VALUE_SHIFT                   3
1128 #define PALMAS_SMPS_DVFS1_VOLTAGE_MAX                           0x1
1129 #define PALMAS_SMPS_DVFS1_STATUS                                0x2
1130
1131 #define DVFS_BASE_VOLTAGE_UV                                    500000
1132 #define DVFS_MAX_VOLTAGE_UV                                     1650000
1133 #define DVFS_VOLTAGE_STEP_UV                                    10000
1134
1135 /* Registers for function PMU_CONTROL */
1136 #define PALMAS_DEV_CTRL                                         0x0
1137 #define PALMAS_POWER_CTRL                                       0x1
1138 #define PALMAS_VSYS_LO                                          0x2
1139 #define PALMAS_VSYS_MON                                         0x3
1140 #define PALMAS_VBAT_MON                                         0x4
1141 #define PALMAS_WATCHDOG                                         0x5
1142 #define PALMAS_BOOT_STATUS                                      0x6
1143 #define PALMAS_BATTERY_BOUNCE                                   0x7
1144 #define PALMAS_BACKUP_BATTERY_CTRL                              0x8
1145 #define PALMAS_LONG_PRESS_KEY                                   0x9
1146 #define PALMAS_OSC_THERM_CTRL                                   0xA
1147 #define PALMAS_BATDEBOUNCING                                    0xB
1148 #define PALMAS_SWOFF_HWRST                                      0xF
1149 #define PALMAS_SWOFF_COLDRST                                    0x10
1150 #define PALMAS_SWOFF_STATUS                                     0x11
1151 #define PALMAS_PMU_CONFIG                                       0x12
1152 #define PALMAS_SPARE                                            0x14
1153 #define PALMAS_PMU_SECONDARY_INT                                0x15
1154 #define PALMAS_SW_REVISION                                      0x17
1155 #define PALMAS_EXT_CHRG_CTRL                                    0x18
1156 #define PALMAS_PMU_SECONDARY_INT2                               0x19
1157
1158 /* Bit definitions for DEV_CTRL */
1159 #define PALMAS_DEV_CTRL_DEV_STATUS_MASK                         0x0c
1160 #define PALMAS_DEV_CTRL_DEV_STATUS_SHIFT                        2
1161 #define PALMAS_DEV_CTRL_SW_RST                                  0x02
1162 #define PALMAS_DEV_CTRL_SW_RST_SHIFT                            1
1163 #define PALMAS_DEV_CTRL_DEV_ON                                  0x01
1164 #define PALMAS_DEV_CTRL_DEV_ON_SHIFT                            0
1165
1166 /* Bit definitions for POWER_CTRL */
1167 #define PALMAS_POWER_CTRL_ENABLE2_MASK                          0x04
1168 #define PALMAS_POWER_CTRL_ENABLE2_MASK_SHIFT                    2
1169 #define PALMAS_POWER_CTRL_ENABLE1_MASK                          0x02
1170 #define PALMAS_POWER_CTRL_ENABLE1_MASK_SHIFT                    1
1171 #define PALMAS_POWER_CTRL_NSLEEP_MASK                           0x01
1172 #define PALMAS_POWER_CTRL_NSLEEP_MASK_SHIFT                     0
1173
1174 /* Bit definitions for VSYS_LO */
1175 #define PALMAS_VSYS_LO_THRESHOLD_MASK                           0x1f
1176 #define PALMAS_VSYS_LO_THRESHOLD_SHIFT                          0
1177
1178 /* Bit definitions for VSYS_MON */
1179 #define PALMAS_VSYS_MON_ENABLE                                  0x80
1180 #define PALMAS_VSYS_MON_ENABLE_SHIFT                            7
1181 #define PALMAS_VSYS_MON_THRESHOLD_MASK                          0x3f
1182 #define PALMAS_VSYS_MON_THRESHOLD_SHIFT                         0
1183
1184 /* Bit definitions for VBAT_MON */
1185 #define PALMAS_VBAT_MON_ENABLE                                  0x80
1186 #define PALMAS_VBAT_MON_ENABLE_SHIFT                            7
1187 #define PALMAS_VBAT_MON_THRESHOLD_MASK                          0x3f
1188 #define PALMAS_VBAT_MON_THRESHOLD_SHIFT                         0
1189
1190 /* Bit definitions for WATCHDOG */
1191 #define PALMAS_WATCHDOG_LOCK                                    0x20
1192 #define PALMAS_WATCHDOG_LOCK_SHIFT                              5
1193 #define PALMAS_WATCHDOG_ENABLE                                  0x10
1194 #define PALMAS_WATCHDOG_ENABLE_SHIFT                            4
1195 #define PALMAS_WATCHDOG_MODE                                    0x08
1196 #define PALMAS_WATCHDOG_MODE_SHIFT                              3
1197 #define PALMAS_WATCHDOG_TIMER_MASK                              0x07
1198 #define PALMAS_WATCHDOG_TIMER_SHIFT                             0
1199
1200 /* Bit definitions for BOOT_STATUS */
1201 #define PALMAS_BOOT_STATUS_BOOT1                                0x02
1202 #define PALMAS_BOOT_STATUS_BOOT1_SHIFT                          1
1203 #define PALMAS_BOOT_STATUS_BOOT0                                0x01
1204 #define PALMAS_BOOT_STATUS_BOOT0_SHIFT                          0
1205
1206 /* Bit definitions for BATTERY_BOUNCE */
1207 #define PALMAS_BATTERY_BOUNCE_BB_DELAY_MASK                     0x3f
1208 #define PALMAS_BATTERY_BOUNCE_BB_DELAY_SHIFT                    0
1209
1210 /* Bit definitions for BACKUP_BATTERY_CTRL */
1211 #define PALMAS_BACKUP_BATTERY_CTRL_VRTC_18_15                   0x80
1212 #define PALMAS_BACKUP_BATTERY_CTRL_VRTC_18_15_SHIFT             7
1213 #define PALMAS_BACKUP_BATTERY_CTRL_VRTC_EN_SLP                  0x40
1214 #define PALMAS_BACKUP_BATTERY_CTRL_VRTC_EN_SLP_SHIFT            6
1215 #define PALMAS_BACKUP_BATTERY_CTRL_VRTC_EN_OFF                  0x20
1216 #define PALMAS_BACKUP_BATTERY_CTRL_VRTC_EN_OFF_SHIFT            5
1217 #define PALMAS_BACKUP_BATTERY_CTRL_VRTC_PWEN                    0x10
1218 #define PALMAS_BACKUP_BATTERY_CTRL_VRTC_PWEN_SHIFT              4
1219 #define PALMAS_BACKUP_BATTERY_CTRL_BBS_BBC_LOW_ICHRG            0x08
1220 #define PALMAS_BACKUP_BATTERY_CTRL_BBS_BBC_LOW_ICHRG_SHIFT      3
1221 #define PALMAS_BACKUP_BATTERY_CTRL_BB_SEL_MASK                  0x06
1222 #define PALMAS_BACKUP_BATTERY_CTRL_BB_SEL_SHIFT                 1
1223 #define PALMAS_BACKUP_BATTERY_CTRL_BB_CHG_EN                    0x01
1224 #define PALMAS_BACKUP_BATTERY_CTRL_BB_CHG_EN_SHIFT              0
1225
1226 /* Bit definitions for LONG_PRESS_KEY */
1227 #define PALMAS_LONG_PRESS_KEY_LPK_LOCK                          0x80
1228 #define PALMAS_LONG_PRESS_KEY_LPK_LOCK_SHIFT                    7
1229 #define PALMAS_LONG_PRESS_KEY_LPK_INT_CLR                       0x10
1230 #define PALMAS_LONG_PRESS_KEY_LPK_INT_CLR_SHIFT                 4
1231 #define PALMAS_LONG_PRESS_KEY_LPK_TIME_MASK                     0x0c
1232 #define PALMAS_LONG_PRESS_KEY_LPK_TIME_SHIFT                    2
1233 #define PALMAS_LONG_PRESS_KEY_PWRON_DEBOUNCE_MASK               0x03
1234 #define PALMAS_LONG_PRESS_KEY_PWRON_DEBOUNCE_SHIFT              0
1235
1236 /* Bit definitions for OSC_THERM_CTRL */
1237 #define PALMAS_OSC_THERM_CTRL_VANA_ON_IN_SLEEP                  0x80
1238 #define PALMAS_OSC_THERM_CTRL_VANA_ON_IN_SLEEP_SHIFT            7
1239 #define PALMAS_OSC_THERM_CTRL_INT_MASK_IN_SLEEP                 0x40
1240 #define PALMAS_OSC_THERM_CTRL_INT_MASK_IN_SLEEP_SHIFT           6
1241 #define PALMAS_OSC_THERM_CTRL_RC15MHZ_ON_IN_SLEEP               0x20
1242 #define PALMAS_OSC_THERM_CTRL_RC15MHZ_ON_IN_SLEEP_SHIFT         5
1243 #define PALMAS_OSC_THERM_CTRL_THERM_OFF_IN_SLEEP                0x10
1244 #define PALMAS_OSC_THERM_CTRL_THERM_OFF_IN_SLEEP_SHIFT          4
1245 #define PALMAS_OSC_THERM_CTRL_THERM_HD_SEL_MASK                 0x0c
1246 #define PALMAS_OSC_THERM_CTRL_THERM_HD_SEL_SHIFT                2
1247 #define PALMAS_OSC_THERM_CTRL_OSC_BYPASS                        0x02
1248 #define PALMAS_OSC_THERM_CTRL_OSC_BYPASS_SHIFT                  1
1249 #define PALMAS_OSC_THERM_CTRL_OSC_HPMODE                        0x01
1250 #define PALMAS_OSC_THERM_CTRL_OSC_HPMODE_SHIFT                  0
1251
1252 /* Bit definitions for BATDEBOUNCING */
1253 #define PALMAS_BATDEBOUNCING_BAT_DEB_BYPASS                     0x80
1254 #define PALMAS_BATDEBOUNCING_BAT_DEB_BYPASS_SHIFT               7
1255 #define PALMAS_BATDEBOUNCING_BINS_DEB_MASK                      0x78
1256 #define PALMAS_BATDEBOUNCING_BINS_DEB_SHIFT                     3
1257 #define PALMAS_BATDEBOUNCING_BEXT_DEB_MASK                      0x07
1258 #define PALMAS_BATDEBOUNCING_BEXT_DEB_SHIFT                     0
1259
1260 /* Bit definitions for SWOFF_HWRST */
1261 #define PALMAS_SWOFF_HWRST_PWRON_LPK                            0x80
1262 #define PALMAS_SWOFF_HWRST_PWRON_LPK_SHIFT                      7
1263 #define PALMAS_SWOFF_HWRST_PWRDOWN                              0x40
1264 #define PALMAS_SWOFF_HWRST_PWRDOWN_SHIFT                        6
1265 #define PALMAS_SWOFF_HWRST_WTD                                  0x20
1266 #define PALMAS_SWOFF_HWRST_WTD_SHIFT                            5
1267 #define PALMAS_SWOFF_HWRST_TSHUT                                0x10
1268 #define PALMAS_SWOFF_HWRST_TSHUT_SHIFT                          4
1269 #define PALMAS_SWOFF_HWRST_RESET_IN                             0x08
1270 #define PALMAS_SWOFF_HWRST_RESET_IN_SHIFT                       3
1271 #define PALMAS_SWOFF_HWRST_SW_RST                               0x04
1272 #define PALMAS_SWOFF_HWRST_SW_RST_SHIFT                         2
1273 #define PALMAS_SWOFF_HWRST_VSYS_LO                              0x02
1274 #define PALMAS_SWOFF_HWRST_VSYS_LO_SHIFT                        1
1275 #define PALMAS_SWOFF_HWRST_GPADC_SHUTDOWN                       0x01
1276 #define PALMAS_SWOFF_HWRST_GPADC_SHUTDOWN_SHIFT                 0
1277
1278 /* Bit definitions for SWOFF_COLDRST */
1279 #define PALMAS_SWOFF_COLDRST_PWRON_LPK                          0x80
1280 #define PALMAS_SWOFF_COLDRST_PWRON_LPK_SHIFT                    7
1281 #define PALMAS_SWOFF_COLDRST_PWRDOWN                            0x40
1282 #define PALMAS_SWOFF_COLDRST_PWRDOWN_SHIFT                      6
1283 #define PALMAS_SWOFF_COLDRST_WTD                                0x20
1284 #define PALMAS_SWOFF_COLDRST_WTD_SHIFT                          5
1285 #define PALMAS_SWOFF_COLDRST_TSHUT                              0x10
1286 #define PALMAS_SWOFF_COLDRST_TSHUT_SHIFT                        4
1287 #define PALMAS_SWOFF_COLDRST_RESET_IN                           0x08
1288 #define PALMAS_SWOFF_COLDRST_RESET_IN_SHIFT                     3
1289 #define PALMAS_SWOFF_COLDRST_SW_RST                             0x04
1290 #define PALMAS_SWOFF_COLDRST_SW_RST_SHIFT                       2
1291 #define PALMAS_SWOFF_COLDRST_VSYS_LO                            0x02
1292 #define PALMAS_SWOFF_COLDRST_VSYS_LO_SHIFT                      1
1293 #define PALMAS_SWOFF_COLDRST_GPADC_SHUTDOWN                     0x01
1294 #define PALMAS_SWOFF_COLDRST_GPADC_SHUTDOWN_SHIFT               0
1295
1296 /* Bit definitions for SWOFF_STATUS */
1297 #define PALMAS_SWOFF_STATUS_PWRON_LPK                           0x80
1298 #define PALMAS_SWOFF_STATUS_PWRON_LPK_SHIFT                     7
1299 #define PALMAS_SWOFF_STATUS_PWRDOWN                             0x40
1300 #define PALMAS_SWOFF_STATUS_PWRDOWN_SHIFT                       6
1301 #define PALMAS_SWOFF_STATUS_WTD                                 0x20
1302 #define PALMAS_SWOFF_STATUS_WTD_SHIFT                           5
1303 #define PALMAS_SWOFF_STATUS_TSHUT                               0x10
1304 #define PALMAS_SWOFF_STATUS_TSHUT_SHIFT                         4
1305 #define PALMAS_SWOFF_STATUS_RESET_IN                            0x08
1306 #define PALMAS_SWOFF_STATUS_RESET_IN_SHIFT                      3
1307 #define PALMAS_SWOFF_STATUS_SW_RST                              0x04
1308 #define PALMAS_SWOFF_STATUS_SW_RST_SHIFT                        2
1309 #define PALMAS_SWOFF_STATUS_VSYS_LO                             0x02
1310 #define PALMAS_SWOFF_STATUS_VSYS_LO_SHIFT                       1
1311 #define PALMAS_SWOFF_STATUS_GPADC_SHUTDOWN                      0x01
1312 #define PALMAS_SWOFF_STATUS_GPADC_SHUTDOWN_SHIFT                0
1313
1314 /* Bit definitions for PMU_CONFIG */
1315 #define PALMAS_PMU_CONFIG_MULTI_CELL_EN                         0x40
1316 #define PALMAS_PMU_CONFIG_MULTI_CELL_EN_SHIFT                   6
1317 #define PALMAS_PMU_CONFIG_SPARE_MASK                            0x30
1318 #define PALMAS_PMU_CONFIG_SPARE_SHIFT                           4
1319 #define PALMAS_PMU_CONFIG_SWOFF_DLY_MASK                        0x0c
1320 #define PALMAS_PMU_CONFIG_SWOFF_DLY_SHIFT                       2
1321 #define PALMAS_PMU_CONFIG_GATE_RESET_OUT                        0x02
1322 #define PALMAS_PMU_CONFIG_GATE_RESET_OUT_SHIFT                  1
1323 #define PALMAS_PMU_CONFIG_AUTODEVON                             0x01
1324 #define PALMAS_PMU_CONFIG_AUTODEVON_SHIFT                       0
1325
1326 /* Bit definitions for SPARE */
1327 #define PALMAS_SPARE_SPARE_MASK                                 0xf8
1328 #define PALMAS_SPARE_SPARE_SHIFT                                3
1329 #define PALMAS_SPARE_REGEN3_OD                                  0x04
1330 #define PALMAS_SPARE_REGEN3_OD_SHIFT                            2
1331 #define PALMAS_SPARE_REGEN2_OD                                  0x02
1332 #define PALMAS_SPARE_REGEN2_OD_SHIFT                            1
1333 #define PALMAS_SPARE_REGEN1_OD                                  0x01
1334 #define PALMAS_SPARE_REGEN1_OD_SHIFT                            0
1335
1336 /* Bit definitions for PMU_SECONDARY_INT */
1337 #define PALMAS_PMU_SECONDARY_INT_VBUS_OVV_INT_SRC               0x80
1338 #define PALMAS_PMU_SECONDARY_INT_VBUS_OVV_INT_SRC_SHIFT         7
1339 #define PALMAS_PMU_SECONDARY_INT_CHARG_DET_N_INT_SRC            0x40
1340 #define PALMAS_PMU_SECONDARY_INT_CHARG_DET_N_INT_SRC_SHIFT      6
1341 #define PALMAS_PMU_SECONDARY_INT_BB_INT_SRC                     0x20
1342 #define PALMAS_PMU_SECONDARY_INT_BB_INT_SRC_SHIFT               5
1343 #define PALMAS_PMU_SECONDARY_INT_FBI_INT_SRC                    0x10
1344 #define PALMAS_PMU_SECONDARY_INT_FBI_INT_SRC_SHIFT              4
1345 #define PALMAS_PMU_SECONDARY_INT_VBUS_OVV_MASK                  0x08
1346 #define PALMAS_PMU_SECONDARY_INT_VBUS_OVV_MASK_SHIFT            3
1347 #define PALMAS_PMU_SECONDARY_INT_CHARG_DET_N_MASK               0x04
1348 #define PALMAS_PMU_SECONDARY_INT_CHARG_DET_N_MASK_SHIFT         2
1349 #define PALMAS_PMU_SECONDARY_INT_BB_MASK                        0x02
1350 #define PALMAS_PMU_SECONDARY_INT_BB_MASK_SHIFT                  1
1351 #define PALMAS_PMU_SECONDARY_INT_FBI_MASK                       0x01
1352 #define PALMAS_PMU_SECONDARY_INT_FBI_MASK_SHIFT                 0
1353
1354 /* Bit definitions for SW_REVISION */
1355 #define PALMAS_SW_REVISION_SW_REVISION_MASK                     0xff
1356 #define PALMAS_SW_REVISION_SW_REVISION_SHIFT                    0
1357
1358 /* Bit definitions for EXT_CHRG_CTRL */
1359 #define PALMAS_EXT_CHRG_CTRL_VBUS_OVV_STATUS                    0x80
1360 #define PALMAS_EXT_CHRG_CTRL_VBUS_OVV_STATUS_SHIFT              7
1361 #define PALMAS_EXT_CHRG_CTRL_CHARG_DET_N_STATUS                 0x40
1362 #define PALMAS_EXT_CHRG_CTRL_CHARG_DET_N_STATUS_SHIFT           6
1363 #define PALMAS_EXT_CHRG_CTRL_VSYS_DEBOUNCE_DELAY                0x08
1364 #define PALMAS_EXT_CHRG_CTRL_VSYS_DEBOUNCE_DELAY_SHIFT          3
1365 #define PALMAS_EXT_CHRG_CTRL_CHRG_DET_N                         0x04
1366 #define PALMAS_EXT_CHRG_CTRL_CHRG_DET_N_SHIFT                   2
1367 #define PALMAS_EXT_CHRG_CTRL_AUTO_ACA_EN                        0x02
1368 #define PALMAS_EXT_CHRG_CTRL_AUTO_ACA_EN_SHIFT                  1
1369 #define PALMAS_EXT_CHRG_CTRL_AUTO_LDOUSB_EN                     0x01
1370 #define PALMAS_EXT_CHRG_CTRL_AUTO_LDOUSB_EN_SHIFT               0
1371
1372 /* Bit definitions for PMU_SECONDARY_INT2 */
1373 #define PALMAS_PMU_SECONDARY_INT2_DVFS2_INT_SRC                 0x20
1374 #define PALMAS_PMU_SECONDARY_INT2_DVFS2_INT_SRC_SHIFT           5
1375 #define PALMAS_PMU_SECONDARY_INT2_DVFS1_INT_SRC                 0x10
1376 #define PALMAS_PMU_SECONDARY_INT2_DVFS1_INT_SRC_SHIFT           4
1377 #define PALMAS_PMU_SECONDARY_INT2_DVFS2_MASK                    0x02
1378 #define PALMAS_PMU_SECONDARY_INT2_DVFS2_MASK_SHIFT              1
1379 #define PALMAS_PMU_SECONDARY_INT2_DVFS1_MASK                    0x01
1380 #define PALMAS_PMU_SECONDARY_INT2_DVFS1_MASK_SHIFT              0
1381
1382 /* Registers for function RESOURCE */
1383 #define PALMAS_CLK32KG_CTRL                                     0x0
1384 #define PALMAS_CLK32KGAUDIO_CTRL                                0x1
1385 #define PALMAS_REGEN1_CTRL                                      0x2
1386 #define PALMAS_REGEN2_CTRL                                      0x3
1387 #define PALMAS_SYSEN1_CTRL                                      0x4
1388 #define PALMAS_SYSEN2_CTRL                                      0x5
1389 #define PALMAS_NSLEEP_RES_ASSIGN                                0x6
1390 #define PALMAS_NSLEEP_SMPS_ASSIGN                               0x7
1391 #define PALMAS_NSLEEP_LDO_ASSIGN1                               0x8
1392 #define PALMAS_NSLEEP_LDO_ASSIGN2                               0x9
1393 #define PALMAS_ENABLE1_RES_ASSIGN                               0xA
1394 #define PALMAS_ENABLE1_SMPS_ASSIGN                              0xB
1395 #define PALMAS_ENABLE1_LDO_ASSIGN1                              0xC
1396 #define PALMAS_ENABLE1_LDO_ASSIGN2                              0xD
1397 #define PALMAS_ENABLE2_RES_ASSIGN                               0xE
1398 #define PALMAS_ENABLE2_SMPS_ASSIGN                              0xF
1399 #define PALMAS_ENABLE2_LDO_ASSIGN1                              0x10
1400 #define PALMAS_ENABLE2_LDO_ASSIGN2                              0x11
1401 #define PALMAS_REGEN3_CTRL                                      0x12
1402
1403 /* Bit definitions for CLK32KG_CTRL */
1404 #define PALMAS_CLK32KG_CTRL_STATUS                              0x10
1405 #define PALMAS_CLK32KG_CTRL_STATUS_SHIFT                        4
1406 #define PALMAS_CLK32KG_CTRL_MODE_SLEEP                          0x04
1407 #define PALMAS_CLK32KG_CTRL_MODE_SLEEP_SHIFT                    2
1408 #define PALMAS_CLK32KG_CTRL_MODE_ACTIVE                         0x01
1409 #define PALMAS_CLK32KG_CTRL_MODE_ACTIVE_SHIFT                   0
1410
1411 /* Bit definitions for CLK32KGAUDIO_CTRL */
1412 #define PALMAS_CLK32KGAUDIO_CTRL_STATUS                         0x10
1413 #define PALMAS_CLK32KGAUDIO_CTRL_STATUS_SHIFT                   4
1414 #define PALMAS_CLK32KGAUDIO_CTRL_RESERVED3                      0x08
1415 #define PALMAS_CLK32KGAUDIO_CTRL_RESERVED3_SHIFT                3
1416 #define PALMAS_CLK32KGAUDIO_CTRL_MODE_SLEEP                     0x04
1417 #define PALMAS_CLK32KGAUDIO_CTRL_MODE_SLEEP_SHIFT               2
1418 #define PALMAS_CLK32KGAUDIO_CTRL_MODE_ACTIVE                    0x01
1419 #define PALMAS_CLK32KGAUDIO_CTRL_MODE_ACTIVE_SHIFT              0
1420
1421 /* Bit definitions for REGEN1_CTRL */
1422 #define PALMAS_REGEN1_CTRL_STATUS                               0x10
1423 #define PALMAS_REGEN1_CTRL_STATUS_SHIFT                         4
1424 #define PALMAS_REGEN1_CTRL_MODE_SLEEP                           0x04
1425 #define PALMAS_REGEN1_CTRL_MODE_SLEEP_SHIFT                     2
1426 #define PALMAS_REGEN1_CTRL_MODE_ACTIVE                          0x01
1427 #define PALMAS_REGEN1_CTRL_MODE_ACTIVE_SHIFT                    0
1428
1429 /* Bit definitions for REGEN2_CTRL */
1430 #define PALMAS_REGEN2_CTRL_STATUS                               0x10
1431 #define PALMAS_REGEN2_CTRL_STATUS_SHIFT                         4
1432 #define PALMAS_REGEN2_CTRL_MODE_SLEEP                           0x04
1433 #define PALMAS_REGEN2_CTRL_MODE_SLEEP_SHIFT                     2
1434 #define PALMAS_REGEN2_CTRL_MODE_ACTIVE                          0x01
1435 #define PALMAS_REGEN2_CTRL_MODE_ACTIVE_SHIFT                    0
1436
1437 /* Bit definitions for SYSEN1_CTRL */
1438 #define PALMAS_SYSEN1_CTRL_STATUS                               0x10
1439 #define PALMAS_SYSEN1_CTRL_STATUS_SHIFT                         4
1440 #define PALMAS_SYSEN1_CTRL_MODE_SLEEP                           0x04
1441 #define PALMAS_SYSEN1_CTRL_MODE_SLEEP_SHIFT                     2
1442 #define PALMAS_SYSEN1_CTRL_MODE_ACTIVE                          0x01
1443 #define PALMAS_SYSEN1_CTRL_MODE_ACTIVE_SHIFT                    0
1444
1445 /* Bit definitions for SYSEN2_CTRL */
1446 #define PALMAS_SYSEN2_CTRL_STATUS                               0x10
1447 #define PALMAS_SYSEN2_CTRL_STATUS_SHIFT                         4
1448 #define PALMAS_SYSEN2_CTRL_MODE_SLEEP                           0x04
1449 #define PALMAS_SYSEN2_CTRL_MODE_SLEEP_SHIFT                     2
1450 #define PALMAS_SYSEN2_CTRL_MODE_ACTIVE                          0x01
1451 #define PALMAS_SYSEN2_CTRL_MODE_ACTIVE_SHIFT                    0
1452
1453 /* Bit definitions for NSLEEP_RES_ASSIGN */
1454 #define PALMAS_NSLEEP_RES_ASSIGN_REGEN3                         0x40
1455 #define PALMAS_NSLEEP_RES_ASSIGN_REGEN3_SHIFT                   6
1456 #define PALMAS_NSLEEP_RES_ASSIGN_CLK32KGAUDIO                   0x20
1457 #define PALMAS_NSLEEP_RES_ASSIGN_CLK32KGAUDIO_SHIFT             5
1458 #define PALMAS_NSLEEP_RES_ASSIGN_CLK32KG                        0x10
1459 #define PALMAS_NSLEEP_RES_ASSIGN_CLK32KG_SHIFT                  4
1460 #define PALMAS_NSLEEP_RES_ASSIGN_SYSEN2                         0x08
1461 #define PALMAS_NSLEEP_RES_ASSIGN_SYSEN2_SHIFT                   3
1462 #define PALMAS_NSLEEP_RES_ASSIGN_SYSEN1                         0x04
1463 #define PALMAS_NSLEEP_RES_ASSIGN_SYSEN1_SHIFT                   2
1464 #define PALMAS_NSLEEP_RES_ASSIGN_REGEN2                         0x02
1465 #define PALMAS_NSLEEP_RES_ASSIGN_REGEN2_SHIFT                   1
1466 #define PALMAS_NSLEEP_RES_ASSIGN_REGEN1                         0x01
1467 #define PALMAS_NSLEEP_RES_ASSIGN_REGEN1_SHIFT                   0
1468
1469 /* Bit definitions for NSLEEP_SMPS_ASSIGN */
1470 #define PALMAS_NSLEEP_SMPS_ASSIGN_SMPS10                        0x80
1471 #define PALMAS_NSLEEP_SMPS_ASSIGN_SMPS10_SHIFT                  7
1472 #define PALMAS_NSLEEP_SMPS_ASSIGN_SMPS9                         0x40
1473 #define PALMAS_NSLEEP_SMPS_ASSIGN_SMPS9_SHIFT                   6
1474 #define PALMAS_NSLEEP_SMPS_ASSIGN_SMPS8                         0x20
1475 #define PALMAS_NSLEEP_SMPS_ASSIGN_SMPS8_SHIFT                   5
1476 #define PALMAS_NSLEEP_SMPS_ASSIGN_SMPS7                         0x10
1477 #define PALMAS_NSLEEP_SMPS_ASSIGN_SMPS7_SHIFT                   4
1478 #define PALMAS_NSLEEP_SMPS_ASSIGN_SMPS6                         0x08
1479 #define PALMAS_NSLEEP_SMPS_ASSIGN_SMPS6_SHIFT                   3
1480 #define PALMAS_NSLEEP_SMPS_ASSIGN_SMPS45                        0x04
1481 #define PALMAS_NSLEEP_SMPS_ASSIGN_SMPS45_SHIFT                  2
1482 #define PALMAS_NSLEEP_SMPS_ASSIGN_SMPS3                         0x02
1483 #define PALMAS_NSLEEP_SMPS_ASSIGN_SMPS3_SHIFT                   1
1484 #define PALMAS_NSLEEP_SMPS_ASSIGN_SMPS12                        0x01
1485 #define PALMAS_NSLEEP_SMPS_ASSIGN_SMPS12_SHIFT                  0
1486
1487 /* Bit definitions for NSLEEP_LDO_ASSIGN1 */
1488 #define PALMAS_NSLEEP_LDO_ASSIGN1_LDO8                          0x80
1489 #define PALMAS_NSLEEP_LDO_ASSIGN1_LDO8_SHIFT                    7
1490 #define PALMAS_NSLEEP_LDO_ASSIGN1_LDO7                          0x40
1491 #define PALMAS_NSLEEP_LDO_ASSIGN1_LDO7_SHIFT                    6
1492 #define PALMAS_NSLEEP_LDO_ASSIGN1_LDO6                          0x20
1493 #define PALMAS_NSLEEP_LDO_ASSIGN1_LDO6_SHIFT                    5
1494 #define PALMAS_NSLEEP_LDO_ASSIGN1_LDO5                          0x10
1495 #define PALMAS_NSLEEP_LDO_ASSIGN1_LDO5_SHIFT                    4
1496 #define PALMAS_NSLEEP_LDO_ASSIGN1_LDO4                          0x08
1497 #define PALMAS_NSLEEP_LDO_ASSIGN1_LDO4_SHIFT                    3
1498 #define PALMAS_NSLEEP_LDO_ASSIGN1_LDO3                          0x04
1499 #define PALMAS_NSLEEP_LDO_ASSIGN1_LDO3_SHIFT                    2
1500 #define PALMAS_NSLEEP_LDO_ASSIGN1_LDO2                          0x02
1501 #define PALMAS_NSLEEP_LDO_ASSIGN1_LDO2_SHIFT                    1
1502 #define PALMAS_NSLEEP_LDO_ASSIGN1_LDO1                          0x01
1503 #define PALMAS_NSLEEP_LDO_ASSIGN1_LDO1_SHIFT                    0
1504
1505 /* Bit definitions for NSLEEP_LDO_ASSIGN2 */
1506 #define PALMAS_NSLEEP_LDO_ASSIGN2_LDOUSB                        0x04
1507 #define PALMAS_NSLEEP_LDO_ASSIGN2_LDOUSB_SHIFT                  2
1508 #define PALMAS_NSLEEP_LDO_ASSIGN2_LDOLN                         0x02
1509 #define PALMAS_NSLEEP_LDO_ASSIGN2_LDOLN_SHIFT                   1
1510 #define PALMAS_NSLEEP_LDO_ASSIGN2_LDO9                          0x01
1511 #define PALMAS_NSLEEP_LDO_ASSIGN2_LDO9_SHIFT                    0
1512
1513 /* Bit definitions for ENABLE1_RES_ASSIGN */
1514 #define PALMAS_ENABLE1_RES_ASSIGN_REGEN3                        0x40
1515 #define PALMAS_ENABLE1_RES_ASSIGN_REGEN3_SHIFT                  6
1516 #define PALMAS_ENABLE1_RES_ASSIGN_CLK32KGAUDIO                  0x20
1517 #define PALMAS_ENABLE1_RES_ASSIGN_CLK32KGAUDIO_SHIFT            5
1518 #define PALMAS_ENABLE1_RES_ASSIGN_CLK32KG                       0x10
1519 #define PALMAS_ENABLE1_RES_ASSIGN_CLK32KG_SHIFT                 4
1520 #define PALMAS_ENABLE1_RES_ASSIGN_SYSEN2                        0x08
1521 #define PALMAS_ENABLE1_RES_ASSIGN_SYSEN2_SHIFT                  3
1522 #define PALMAS_ENABLE1_RES_ASSIGN_SYSEN1                        0x04
1523 #define PALMAS_ENABLE1_RES_ASSIGN_SYSEN1_SHIFT                  2
1524 #define PALMAS_ENABLE1_RES_ASSIGN_REGEN2                        0x02
1525 #define PALMAS_ENABLE1_RES_ASSIGN_REGEN2_SHIFT                  1
1526 #define PALMAS_ENABLE1_RES_ASSIGN_REGEN1                        0x01
1527 #define PALMAS_ENABLE1_RES_ASSIGN_REGEN1_SHIFT                  0
1528
1529 /* Bit definitions for ENABLE1_SMPS_ASSIGN */
1530 #define PALMAS_ENABLE1_SMPS_ASSIGN_SMPS10                       0x80
1531 #define PALMAS_ENABLE1_SMPS_ASSIGN_SMPS10_SHIFT                 7
1532 #define PALMAS_ENABLE1_SMPS_ASSIGN_SMPS9                        0x40
1533 #define PALMAS_ENABLE1_SMPS_ASSIGN_SMPS9_SHIFT                  6
1534 #define PALMAS_ENABLE1_SMPS_ASSIGN_SMPS8                        0x20
1535 #define PALMAS_ENABLE1_SMPS_ASSIGN_SMPS8_SHIFT                  5
1536 #define PALMAS_ENABLE1_SMPS_ASSIGN_SMPS7                        0x10
1537 #define PALMAS_ENABLE1_SMPS_ASSIGN_SMPS7_SHIFT                  4
1538 #define PALMAS_ENABLE1_SMPS_ASSIGN_SMPS6                        0x08
1539 #define PALMAS_ENABLE1_SMPS_ASSIGN_SMPS6_SHIFT                  3
1540 #define PALMAS_ENABLE1_SMPS_ASSIGN_SMPS45                       0x04
1541 #define PALMAS_ENABLE1_SMPS_ASSIGN_SMPS45_SHIFT                 2
1542 #define PALMAS_ENABLE1_SMPS_ASSIGN_SMPS3                        0x02
1543 #define PALMAS_ENABLE1_SMPS_ASSIGN_SMPS3_SHIFT                  1
1544 #define PALMAS_ENABLE1_SMPS_ASSIGN_SMPS12                       0x01
1545 #define PALMAS_ENABLE1_SMPS_ASSIGN_SMPS12_SHIFT                 0
1546
1547 /* Bit definitions for ENABLE1_LDO_ASSIGN1 */
1548 #define PALMAS_ENABLE1_LDO_ASSIGN1_LDO8                         0x80
1549 #define PALMAS_ENABLE1_LDO_ASSIGN1_LDO8_SHIFT                   7
1550 #define PALMAS_ENABLE1_LDO_ASSIGN1_LDO7                         0x40
1551 #define PALMAS_ENABLE1_LDO_ASSIGN1_LDO7_SHIFT                   6
1552 #define PALMAS_ENABLE1_LDO_ASSIGN1_LDO6                         0x20
1553 #define PALMAS_ENABLE1_LDO_ASSIGN1_LDO6_SHIFT                   5
1554 #define PALMAS_ENABLE1_LDO_ASSIGN1_LDO5                         0x10
1555 #define PALMAS_ENABLE1_LDO_ASSIGN1_LDO5_SHIFT                   4
1556 #define PALMAS_ENABLE1_LDO_ASSIGN1_LDO4                         0x08
1557 #define PALMAS_ENABLE1_LDO_ASSIGN1_LDO4_SHIFT                   3
1558 #define PALMAS_ENABLE1_LDO_ASSIGN1_LDO3                         0x04
1559 #define PALMAS_ENABLE1_LDO_ASSIGN1_LDO3_SHIFT                   2
1560 #define PALMAS_ENABLE1_LDO_ASSIGN1_LDO2                         0x02
1561 #define PALMAS_ENABLE1_LDO_ASSIGN1_LDO2_SHIFT                   1
1562 #define PALMAS_ENABLE1_LDO_ASSIGN1_LDO1                         0x01
1563 #define PALMAS_ENABLE1_LDO_ASSIGN1_LDO1_SHIFT                   0
1564
1565 /* Bit definitions for ENABLE1_LDO_ASSIGN2 */
1566 #define PALMAS_ENABLE1_LDO_ASSIGN2_LDOUSB                       0x04
1567 #define PALMAS_ENABLE1_LDO_ASSIGN2_LDOUSB_SHIFT                 2
1568 #define PALMAS_ENABLE1_LDO_ASSIGN2_LDOLN                        0x02
1569 #define PALMAS_ENABLE1_LDO_ASSIGN2_LDOLN_SHIFT                  1
1570 #define PALMAS_ENABLE1_LDO_ASSIGN2_LDO9                         0x01
1571 #define PALMAS_ENABLE1_LDO_ASSIGN2_LDO9_SHIFT                   0
1572
1573 /* Bit definitions for ENABLE2_RES_ASSIGN */
1574 #define PALMAS_ENABLE2_RES_ASSIGN_REGEN3                        0x40
1575 #define PALMAS_ENABLE2_RES_ASSIGN_REGEN3_SHIFT                  6
1576 #define PALMAS_ENABLE2_RES_ASSIGN_CLK32KGAUDIO                  0x20
1577 #define PALMAS_ENABLE2_RES_ASSIGN_CLK32KGAUDIO_SHIFT            5
1578 #define PALMAS_ENABLE2_RES_ASSIGN_CLK32KG                       0x10
1579 #define PALMAS_ENABLE2_RES_ASSIGN_CLK32KG_SHIFT                 4
1580 #define PALMAS_ENABLE2_RES_ASSIGN_SYSEN2                        0x08
1581 #define PALMAS_ENABLE2_RES_ASSIGN_SYSEN2_SHIFT                  3
1582 #define PALMAS_ENABLE2_RES_ASSIGN_SYSEN1                        0x04
1583 #define PALMAS_ENABLE2_RES_ASSIGN_SYSEN1_SHIFT                  2
1584 #define PALMAS_ENABLE2_RES_ASSIGN_REGEN2                        0x02
1585 #define PALMAS_ENABLE2_RES_ASSIGN_REGEN2_SHIFT                  1
1586 #define PALMAS_ENABLE2_RES_ASSIGN_REGEN1                        0x01
1587 #define PALMAS_ENABLE2_RES_ASSIGN_REGEN1_SHIFT                  0
1588
1589 /* Bit definitions for ENABLE2_SMPS_ASSIGN */
1590 #define PALMAS_ENABLE2_SMPS_ASSIGN_SMPS10                       0x80
1591 #define PALMAS_ENABLE2_SMPS_ASSIGN_SMPS10_SHIFT                 7
1592 #define PALMAS_ENABLE2_SMPS_ASSIGN_SMPS9                        0x40
1593 #define PALMAS_ENABLE2_SMPS_ASSIGN_SMPS9_SHIFT                  6
1594 #define PALMAS_ENABLE2_SMPS_ASSIGN_SMPS8                        0x20
1595 #define PALMAS_ENABLE2_SMPS_ASSIGN_SMPS8_SHIFT                  5
1596 #define PALMAS_ENABLE2_SMPS_ASSIGN_SMPS7                        0x10
1597 #define PALMAS_ENABLE2_SMPS_ASSIGN_SMPS7_SHIFT                  4
1598 #define PALMAS_ENABLE2_SMPS_ASSIGN_SMPS6                        0x08
1599 #define PALMAS_ENABLE2_SMPS_ASSIGN_SMPS6_SHIFT                  3
1600 #define PALMAS_ENABLE2_SMPS_ASSIGN_SMPS45                       0x04
1601 #define PALMAS_ENABLE2_SMPS_ASSIGN_SMPS45_SHIFT                 2
1602 #define PALMAS_ENABLE2_SMPS_ASSIGN_SMPS3                        0x02
1603 #define PALMAS_ENABLE2_SMPS_ASSIGN_SMPS3_SHIFT                  1
1604 #define PALMAS_ENABLE2_SMPS_ASSIGN_SMPS12                       0x01
1605 #define PALMAS_ENABLE2_SMPS_ASSIGN_SMPS12_SHIFT                 0
1606
1607 /* Bit definitions for ENABLE2_LDO_ASSIGN1 */
1608 #define PALMAS_ENABLE2_LDO_ASSIGN1_LDO8                         0x80
1609 #define PALMAS_ENABLE2_LDO_ASSIGN1_LDO8_SHIFT                   7
1610 #define PALMAS_ENABLE2_LDO_ASSIGN1_LDO7                         0x40
1611 #define PALMAS_ENABLE2_LDO_ASSIGN1_LDO7_SHIFT                   6
1612 #define PALMAS_ENABLE2_LDO_ASSIGN1_LDO6                         0x20
1613 #define PALMAS_ENABLE2_LDO_ASSIGN1_LDO6_SHIFT                   5
1614 #define PALMAS_ENABLE2_LDO_ASSIGN1_LDO5                         0x10
1615 #define PALMAS_ENABLE2_LDO_ASSIGN1_LDO5_SHIFT                   4
1616 #define PALMAS_ENABLE2_LDO_ASSIGN1_LDO4                         0x08
1617 #define PALMAS_ENABLE2_LDO_ASSIGN1_LDO4_SHIFT                   3
1618 #define PALMAS_ENABLE2_LDO_ASSIGN1_LDO3                         0x04
1619 #define PALMAS_ENABLE2_LDO_ASSIGN1_LDO3_SHIFT                   2
1620 #define PALMAS_ENABLE2_LDO_ASSIGN1_LDO2                         0x02
1621 #define PALMAS_ENABLE2_LDO_ASSIGN1_LDO2_SHIFT                   1
1622 #define PALMAS_ENABLE2_LDO_ASSIGN1_LDO1                         0x01
1623 #define PALMAS_ENABLE2_LDO_ASSIGN1_LDO1_SHIFT                   0
1624
1625 /* Bit definitions for ENABLE2_LDO_ASSIGN2 */
1626 #define PALMAS_ENABLE2_LDO_ASSIGN2_LDOUSB                       0x04
1627 #define PALMAS_ENABLE2_LDO_ASSIGN2_LDOUSB_SHIFT                 2
1628 #define PALMAS_ENABLE2_LDO_ASSIGN2_LDOLN                        0x02
1629 #define PALMAS_ENABLE2_LDO_ASSIGN2_LDOLN_SHIFT                  1
1630 #define PALMAS_ENABLE2_LDO_ASSIGN2_LDO9                         0x01
1631 #define PALMAS_ENABLE2_LDO_ASSIGN2_LDO9_SHIFT                   0
1632
1633 /* Bit definitions for REGEN3_CTRL */
1634 #define PALMAS_REGEN3_CTRL_STATUS                               0x10
1635 #define PALMAS_REGEN3_CTRL_STATUS_SHIFT                         4
1636 #define PALMAS_REGEN3_CTRL_MODE_SLEEP                           0x04
1637 #define PALMAS_REGEN3_CTRL_MODE_SLEEP_SHIFT                     2
1638 #define PALMAS_REGEN3_CTRL_MODE_ACTIVE                          0x01
1639 #define PALMAS_REGEN3_CTRL_MODE_ACTIVE_SHIFT                    0
1640
1641 /* Registers for function PAD_CONTROL */
1642 #define PALMAS_PU_PD_INPUT_CTRL1                                0x0
1643 #define PALMAS_PU_PD_INPUT_CTRL2                                0x1
1644 #define PALMAS_PU_PD_INPUT_CTRL3                                0x2
1645 #define PALMAS_OD_OUTPUT_CTRL                                   0x4
1646 #define PALMAS_POLARITY_CTRL                                    0x5
1647 #define PALMAS_PRIMARY_SECONDARY_PAD1                           0x6
1648 #define PALMAS_PRIMARY_SECONDARY_PAD2                           0x7
1649 #define PALMAS_I2C_SPI                                          0x8
1650 #define PALMAS_PU_PD_INPUT_CTRL4                                0x9
1651 #define PALMAS_PRIMARY_SECONDARY_PAD3                           0xA
1652
1653 /* Bit definitions for PU_PD_INPUT_CTRL1 */
1654 #define PALMAS_PU_PD_INPUT_CTRL1_RESET_IN_PD                    0x40
1655 #define PALMAS_PU_PD_INPUT_CTRL1_RESET_IN_PD_SHIFT              6
1656 #define PALMAS_PU_PD_INPUT_CTRL1_GPADC_START_PU                 0x20
1657 #define PALMAS_PU_PD_INPUT_CTRL1_GPADC_START_PU_SHIFT           5
1658 #define PALMAS_PU_PD_INPUT_CTRL1_GPADC_START_PD                 0x10
1659 #define PALMAS_PU_PD_INPUT_CTRL1_GPADC_START_PD_SHIFT           4
1660 #define PALMAS_PU_PD_INPUT_CTRL1_PWRDOWN_PD                     0x04
1661 #define PALMAS_PU_PD_INPUT_CTRL1_PWRDOWN_PD_SHIFT               2
1662 #define PALMAS_PU_PD_INPUT_CTRL1_NRESWARM_PU                    0x02
1663 #define PALMAS_PU_PD_INPUT_CTRL1_NRESWARM_PU_SHIFT              1
1664
1665 /* Bit definitions for PU_PD_INPUT_CTRL2 */
1666 #define PALMAS_PU_PD_INPUT_CTRL2_ENABLE2_PU                     0x20
1667 #define PALMAS_PU_PD_INPUT_CTRL2_ENABLE2_PU_SHIFT               5
1668 #define PALMAS_PU_PD_INPUT_CTRL2_ENABLE2_PD                     0x10
1669 #define PALMAS_PU_PD_INPUT_CTRL2_ENABLE2_PD_SHIFT               4
1670 #define PALMAS_PU_PD_INPUT_CTRL2_ENABLE1_PU                     0x08
1671 #define PALMAS_PU_PD_INPUT_CTRL2_ENABLE1_PU_SHIFT               3
1672 #define PALMAS_PU_PD_INPUT_CTRL2_ENABLE1_PD                     0x04
1673 #define PALMAS_PU_PD_INPUT_CTRL2_ENABLE1_PD_SHIFT               2
1674 #define PALMAS_PU_PD_INPUT_CTRL2_NSLEEP_PU                      0x02
1675 #define PALMAS_PU_PD_INPUT_CTRL2_NSLEEP_PU_SHIFT                1
1676 #define PALMAS_PU_PD_INPUT_CTRL2_NSLEEP_PD                      0x01
1677 #define PALMAS_PU_PD_INPUT_CTRL2_NSLEEP_PD_SHIFT                0
1678
1679 /* Bit definitions for PU_PD_INPUT_CTRL3 */
1680 #define PALMAS_PU_PD_INPUT_CTRL3_ACOK_PD                        0x40
1681 #define PALMAS_PU_PD_INPUT_CTRL3_ACOK_PD_SHIFT                  6
1682 #define PALMAS_PU_PD_INPUT_CTRL3_CHRG_DET_N_PD                  0x10
1683 #define PALMAS_PU_PD_INPUT_CTRL3_CHRG_DET_N_PD_SHIFT            4
1684 #define PALMAS_PU_PD_INPUT_CTRL3_POWERHOLD_PD                   0x04
1685 #define PALMAS_PU_PD_INPUT_CTRL3_POWERHOLD_PD_SHIFT             2
1686 #define PALMAS_PU_PD_INPUT_CTRL3_MSECURE_PD                     0x01
1687 #define PALMAS_PU_PD_INPUT_CTRL3_MSECURE_PD_SHIFT               0
1688
1689 /* Bit definitions for OD_OUTPUT_CTRL */
1690 #define PALMAS_OD_OUTPUT_CTRL_PWM_2_OD                          0x80
1691 #define PALMAS_OD_OUTPUT_CTRL_PWM_2_OD_SHIFT                    7
1692 #define PALMAS_OD_OUTPUT_CTRL_VBUSDET_OD                        0x40
1693 #define PALMAS_OD_OUTPUT_CTRL_VBUSDET_OD_SHIFT                  6
1694 #define PALMAS_OD_OUTPUT_CTRL_PWM_1_OD                          0x20
1695 #define PALMAS_OD_OUTPUT_CTRL_PWM_1_OD_SHIFT                    5
1696 #define PALMAS_OD_OUTPUT_CTRL_INT_OD                            0x08
1697 #define PALMAS_OD_OUTPUT_CTRL_INT_OD_SHIFT                      3
1698
1699 /* Bit definitions for POLARITY_CTRL */
1700 #define PALMAS_POLARITY_CTRL_INT_POLARITY                       0x80
1701 #define PALMAS_POLARITY_CTRL_INT_POLARITY_SHIFT                 7
1702 #define PALMAS_POLARITY_CTRL_ENABLE2_POLARITY                   0x40
1703 #define PALMAS_POLARITY_CTRL_ENABLE2_POLARITY_SHIFT             6
1704 #define PALMAS_POLARITY_CTRL_ENABLE1_POLARITY                   0x20
1705 #define PALMAS_POLARITY_CTRL_ENABLE1_POLARITY_SHIFT             5
1706 #define PALMAS_POLARITY_CTRL_NSLEEP_POLARITY                    0x10
1707 #define PALMAS_POLARITY_CTRL_NSLEEP_POLARITY_SHIFT              4
1708 #define PALMAS_POLARITY_CTRL_RESET_IN_POLARITY                  0x08
1709 #define PALMAS_POLARITY_CTRL_RESET_IN_POLARITY_SHIFT            3
1710 #define PALMAS_POLARITY_CTRL_GPIO_3_CHRG_DET_N_POLARITY         0x04
1711 #define PALMAS_POLARITY_CTRL_GPIO_3_CHRG_DET_N_POLARITY_SHIFT   2
1712 #define PALMAS_POLARITY_CTRL_POWERGOOD_USB_PSEL_POLARITY        0x02
1713 #define PALMAS_POLARITY_CTRL_POWERGOOD_USB_PSEL_POLARITY_SHIFT  1
1714 #define PALMAS_POLARITY_CTRL_PWRDOWN_POLARITY                   0x01
1715 #define PALMAS_POLARITY_CTRL_PWRDOWN_POLARITY_SHIFT             0
1716
1717 /* Bit definitions for PRIMARY_SECONDARY_PAD1 */
1718 #define PALMAS_PRIMARY_SECONDARY_PAD1_GPIO_3                    0x80
1719 #define PALMAS_PRIMARY_SECONDARY_PAD1_GPIO_3_SHIFT              7
1720 #define PALMAS_PRIMARY_SECONDARY_PAD1_GPIO_2_MASK               0x60
1721 #define PALMAS_PRIMARY_SECONDARY_PAD1_GPIO_2_SHIFT              5
1722 #define PALMAS_PRIMARY_SECONDARY_PAD1_GPIO_1_MASK               0x18
1723 #define PALMAS_PRIMARY_SECONDARY_PAD1_GPIO_1_SHIFT              3
1724 #define PALMAS_PRIMARY_SECONDARY_PAD1_GPIO_0                    0x04
1725 #define PALMAS_PRIMARY_SECONDARY_PAD1_GPIO_0_SHIFT              2
1726 #define PALMAS_PRIMARY_SECONDARY_PAD1_VAC                       0x02
1727 #define PALMAS_PRIMARY_SECONDARY_PAD1_VAC_SHIFT                 1
1728 #define PALMAS_PRIMARY_SECONDARY_PAD1_POWERGOOD                 0x01
1729 #define PALMAS_PRIMARY_SECONDARY_PAD1_POWERGOOD_SHIFT           0
1730
1731 /* Bit definitions for PRIMARY_SECONDARY_PAD2 */
1732 #define PALMAS_PRIMARY_SECONDARY_PAD2_GPIO_7_MASK               0x30
1733 #define PALMAS_PRIMARY_SECONDARY_PAD2_GPIO_7_SHIFT              4
1734 #define PALMAS_PRIMARY_SECONDARY_PAD2_GPIO_6                    0x08
1735 #define PALMAS_PRIMARY_SECONDARY_PAD2_GPIO_6_SHIFT              3
1736 #define PALMAS_PRIMARY_SECONDARY_PAD2_GPIO_5_MASK               0x06
1737 #define PALMAS_PRIMARY_SECONDARY_PAD2_GPIO_5_SHIFT              1
1738 #define PALMAS_PRIMARY_SECONDARY_PAD2_GPIO_4                    0x01
1739 #define PALMAS_PRIMARY_SECONDARY_PAD2_GPIO_4_SHIFT              0
1740
1741 /* Bit definitions for I2C_SPI */
1742 #define PALMAS_I2C_SPI_I2C2OTP_EN                               0x80
1743 #define PALMAS_I2C_SPI_I2C2OTP_EN_SHIFT                         7
1744 #define PALMAS_I2C_SPI_I2C2OTP_PAGESEL                          0x40
1745 #define PALMAS_I2C_SPI_I2C2OTP_PAGESEL_SHIFT                    6
1746 #define PALMAS_I2C_SPI_ID_I2C2                                  0x20
1747 #define PALMAS_I2C_SPI_ID_I2C2_SHIFT                            5
1748 #define PALMAS_I2C_SPI_I2C_SPI                                  0x10
1749 #define PALMAS_I2C_SPI_I2C_SPI_SHIFT                            4
1750 #define PALMAS_I2C_SPI_ID_I2C1_MASK                             0x0f
1751 #define PALMAS_I2C_SPI_ID_I2C1_SHIFT                            0
1752
1753 /* Bit definitions for PU_PD_INPUT_CTRL4 */
1754 #define PALMAS_PU_PD_INPUT_CTRL4_DVFS2_DAT_PD                   0x40
1755 #define PALMAS_PU_PD_INPUT_CTRL4_DVFS2_DAT_PD_SHIFT             6
1756 #define PALMAS_PU_PD_INPUT_CTRL4_DVFS2_CLK_PD                   0x10
1757 #define PALMAS_PU_PD_INPUT_CTRL4_DVFS2_CLK_PD_SHIFT             4
1758 #define PALMAS_PU_PD_INPUT_CTRL4_DVFS1_DAT_PD                   0x04
1759 #define PALMAS_PU_PD_INPUT_CTRL4_DVFS1_DAT_PD_SHIFT             2
1760 #define PALMAS_PU_PD_INPUT_CTRL4_DVFS1_CLK_PD                   0x01
1761 #define PALMAS_PU_PD_INPUT_CTRL4_DVFS1_CLK_PD_SHIFT             0
1762
1763 /* Bit definitions for PRIMARY_SECONDARY_PAD3 */
1764 #define PALMAS_PRIMARY_SECONDARY_PAD3_DVFS2                     0x02
1765 #define PALMAS_PRIMARY_SECONDARY_PAD3_DVFS2_SHIFT               1
1766 #define PALMAS_PRIMARY_SECONDARY_PAD3_DVFS1                     0x01
1767 #define PALMAS_PRIMARY_SECONDARY_PAD3_DVFS1_SHIFT               0
1768
1769 /* Registers for function LED_PWM */
1770 #define PALMAS_LED_PERIOD_CTRL                                  0x0
1771 #define PALMAS_LED_CTRL                                         0x1
1772 #define PALMAS_PWM_CTRL1                                        0x2
1773 #define PALMAS_PWM_CTRL2                                        0x3
1774
1775 /* Bit definitions for LED_PERIOD_CTRL */
1776 #define PALMAS_LED_PERIOD_CTRL_LED_2_PERIOD_MASK                0x38
1777 #define PALMAS_LED_PERIOD_CTRL_LED_2_PERIOD_SHIFT               3
1778 #define PALMAS_LED_PERIOD_CTRL_LED_1_PERIOD_MASK                0x07
1779 #define PALMAS_LED_PERIOD_CTRL_LED_1_PERIOD_SHIFT               0
1780
1781 /* Bit definitions for LED_CTRL */
1782 #define PALMAS_LED_CTRL_LED_2_SEQ                               0x20
1783 #define PALMAS_LED_CTRL_LED_2_SEQ_SHIFT                         5
1784 #define PALMAS_LED_CTRL_LED_1_SEQ                               0x10
1785 #define PALMAS_LED_CTRL_LED_1_SEQ_SHIFT                         4
1786 #define PALMAS_LED_CTRL_LED_2_ON_TIME_MASK                      0x0c
1787 #define PALMAS_LED_CTRL_LED_2_ON_TIME_SHIFT                     2
1788 #define PALMAS_LED_CTRL_LED_1_ON_TIME_MASK                      0x03
1789 #define PALMAS_LED_CTRL_LED_1_ON_TIME_SHIFT                     0
1790
1791 /* Bit definitions for PWM_CTRL1 */
1792 #define PALMAS_PWM_CTRL1_PWM_FREQ_EN                            0x02
1793 #define PALMAS_PWM_CTRL1_PWM_FREQ_EN_SHIFT                      1
1794 #define PALMAS_PWM_CTRL1_PWM_FREQ_SEL                           0x01
1795 #define PALMAS_PWM_CTRL1_PWM_FREQ_SEL_SHIFT                     0
1796
1797 /* Bit definitions for PWM_CTRL2 */
1798 #define PALMAS_PWM_CTRL2_PWM_DUTY_SEL_MASK                      0xff
1799 #define PALMAS_PWM_CTRL2_PWM_DUTY_SEL_SHIFT                     0
1800
1801 /* Maximum INT mask/edge regsiter */
1802 #define PALMAS_MAX_INTERRUPT_MASK_REG                           4
1803 #define PALMAS_MAX_INTERRUPT_EDGE_REG                           8
1804
1805 /* Registers for function INTERRUPT */
1806 #define PALMAS_INT1_STATUS                                      0x0
1807 #define PALMAS_INT1_MASK                                        0x1
1808 #define PALMAS_INT1_LINE_STATE                                  0x2
1809 #define PALMAS_INT1_EDGE_DETECT1_RESERVED                       0x3
1810 #define PALMAS_INT1_EDGE_DETECT2_RESERVED                       0x4
1811 #define PALMAS_INT2_STATUS                                      0x5
1812 #define PALMAS_INT2_MASK                                        0x6
1813 #define PALMAS_INT2_LINE_STATE                                  0x7
1814 #define PALMAS_INT2_EDGE_DETECT1_RESERVED                       0x8
1815 #define PALMAS_INT2_EDGE_DETECT2_RESERVED                       0x9
1816 #define PALMAS_INT3_STATUS                                      0xA
1817 #define PALMAS_INT3_MASK                                        0xB
1818 #define PALMAS_INT3_LINE_STATE                                  0xC
1819 #define PALMAS_INT3_EDGE_DETECT1_RESERVED                       0xD
1820 #define PALMAS_INT3_EDGE_DETECT2_RESERVED                       0xE
1821 #define PALMAS_INT4_STATUS                                      0xF
1822 #define PALMAS_INT4_MASK                                        0x10
1823 #define PALMAS_INT4_LINE_STATE                                  0x11
1824 #define PALMAS_INT4_EDGE_DETECT1                                0x12
1825 #define PALMAS_INT4_EDGE_DETECT2                                0x13
1826 #define PALMAS_INT_CTRL                                         0x14
1827
1828 /* Bit definitions for INT1_STATUS */
1829 #define PALMAS_INT1_STATUS_VBAT_MON                             0x80
1830 #define PALMAS_INT1_STATUS_VBAT_MON_SHIFT                       7
1831 #define PALMAS_INT1_STATUS_VSYS_MON                             0x40
1832 #define PALMAS_INT1_STATUS_VSYS_MON_SHIFT                       6
1833 #define PALMAS_INT1_STATUS_HOTDIE                               0x20
1834 #define PALMAS_INT1_STATUS_HOTDIE_SHIFT                         5
1835 #define PALMAS_INT1_STATUS_PWRDOWN                              0x10
1836 #define PALMAS_INT1_STATUS_PWRDOWN_SHIFT                        4
1837 #define PALMAS_INT1_STATUS_RPWRON                               0x08
1838 #define PALMAS_INT1_STATUS_RPWRON_SHIFT                         3
1839 #define PALMAS_INT1_STATUS_LONG_PRESS_KEY                       0x04
1840 #define PALMAS_INT1_STATUS_LONG_PRESS_KEY_SHIFT                 2
1841 #define PALMAS_INT1_STATUS_PWRON                                0x02
1842 #define PALMAS_INT1_STATUS_PWRON_SHIFT                          1
1843 #define PALMAS_INT1_STATUS_CHARG_DET_N_VBUS_OVV                 0x01
1844 #define PALMAS_INT1_STATUS_CHARG_DET_N_VBUS_OVV_SHIFT           0
1845
1846 /* Bit definitions for INT1_MASK */
1847 #define PALMAS_INT1_MASK_VBAT_MON                               0x80
1848 #define PALMAS_INT1_MASK_VBAT_MON_SHIFT                         7
1849 #define PALMAS_INT1_MASK_VSYS_MON                               0x40
1850 #define PALMAS_INT1_MASK_VSYS_MON_SHIFT                         6
1851 #define PALMAS_INT1_MASK_HOTDIE                                 0x20
1852 #define PALMAS_INT1_MASK_HOTDIE_SHIFT                           5
1853 #define PALMAS_INT1_MASK_PWRDOWN                                0x10
1854 #define PALMAS_INT1_MASK_PWRDOWN_SHIFT                          4
1855 #define PALMAS_INT1_MASK_RPWRON                                 0x08
1856 #define PALMAS_INT1_MASK_RPWRON_SHIFT                           3
1857 #define PALMAS_INT1_MASK_LONG_PRESS_KEY                         0x04
1858 #define PALMAS_INT1_MASK_LONG_PRESS_KEY_SHIFT                   2
1859 #define PALMAS_INT1_MASK_PWRON                                  0x02
1860 #define PALMAS_INT1_MASK_PWRON_SHIFT                            1
1861 #define PALMAS_INT1_MASK_CHARG_DET_N_VBUS_OVV                   0x01
1862 #define PALMAS_INT1_MASK_CHARG_DET_N_VBUS_OVV_SHIFT             0
1863
1864 /* Bit definitions for INT1_LINE_STATE */
1865 #define PALMAS_INT1_LINE_STATE_VBAT_MON                         0x80
1866 #define PALMAS_INT1_LINE_STATE_VBAT_MON_SHIFT                   7
1867 #define PALMAS_INT1_LINE_STATE_VSYS_MON                         0x40
1868 #define PALMAS_INT1_LINE_STATE_VSYS_MON_SHIFT                   6
1869 #define PALMAS_INT1_LINE_STATE_HOTDIE                           0x20
1870 #define PALMAS_INT1_LINE_STATE_HOTDIE_SHIFT                     5
1871 #define PALMAS_INT1_LINE_STATE_PWRDOWN                          0x10
1872 #define PALMAS_INT1_LINE_STATE_PWRDOWN_SHIFT                    4
1873 #define PALMAS_INT1_LINE_STATE_RPWRON                           0x08
1874 #define PALMAS_INT1_LINE_STATE_RPWRON_SHIFT                     3
1875 #define PALMAS_INT1_LINE_STATE_LONG_PRESS_KEY                   0x04
1876 #define PALMAS_INT1_LINE_STATE_LONG_PRESS_KEY_SHIFT             2
1877 #define PALMAS_INT1_LINE_STATE_PWRON                            0x02
1878 #define PALMAS_INT1_LINE_STATE_PWRON_SHIFT                      1
1879 #define PALMAS_INT1_LINE_STATE_CHARG_DET_N_VBUS_OVV             0x01
1880 #define PALMAS_INT1_LINE_STATE_CHARG_DET_N_VBUS_OVV_SHIFT       0
1881
1882 /* Bit definitions for INT2_STATUS */
1883 #define PALMAS_INT2_STATUS_VAC_ACOK                             0x80
1884 #define PALMAS_INT2_STATUS_VAC_ACOK_SHIFT                       7
1885 #define PALMAS_INT2_STATUS_SHORT                                0x40
1886 #define PALMAS_INT2_STATUS_SHORT_SHIFT                          6
1887 #define PALMAS_INT2_STATUS_FBI_BB                               0x20
1888 #define PALMAS_INT2_STATUS_FBI_BB_SHIFT                         5
1889 #define PALMAS_INT2_STATUS_RESET_IN                             0x10
1890 #define PALMAS_INT2_STATUS_RESET_IN_SHIFT                       4
1891 #define PALMAS_INT2_STATUS_BATREMOVAL                           0x08
1892 #define PALMAS_INT2_STATUS_BATREMOVAL_SHIFT                     3
1893 #define PALMAS_INT2_STATUS_WDT                                  0x04
1894 #define PALMAS_INT2_STATUS_WDT_SHIFT                            2
1895 #define PALMAS_INT2_STATUS_RTC_TIMER                            0x02
1896 #define PALMAS_INT2_STATUS_RTC_TIMER_SHIFT                      1
1897 #define PALMAS_INT2_STATUS_RTC_ALARM                            0x01
1898 #define PALMAS_INT2_STATUS_RTC_ALARM_SHIFT                      0
1899
1900 /* Bit definitions for INT2_MASK */
1901 #define PALMAS_INT2_MASK_VAC_ACOK                               0x80
1902 #define PALMAS_INT2_MASK_VAC_ACOK_SHIFT                         7
1903 #define PALMAS_INT2_MASK_SHORT                                  0x40
1904 #define PALMAS_INT2_MASK_SHORT_SHIFT                            6
1905 #define PALMAS_INT2_MASK_FBI_BB                                 0x20
1906 #define PALMAS_INT2_MASK_FBI_BB_SHIFT                           5
1907 #define PALMAS_INT2_MASK_RESET_IN                               0x10
1908 #define PALMAS_INT2_MASK_RESET_IN_SHIFT                         4
1909 #define PALMAS_INT2_MASK_BATREMOVAL                             0x08
1910 #define PALMAS_INT2_MASK_BATREMOVAL_SHIFT                       3
1911 #define PALMAS_INT2_MASK_WDT                                    0x04
1912 #define PALMAS_INT2_MASK_WDT_SHIFT                              2
1913 #define PALMAS_INT2_MASK_RTC_TIMER                              0x02
1914 #define PALMAS_INT2_MASK_RTC_TIMER_SHIFT                        1
1915 #define PALMAS_INT2_MASK_RTC_ALARM                              0x01
1916 #define PALMAS_INT2_MASK_RTC_ALARM_SHIFT                        0
1917
1918 /* Bit definitions for INT2_LINE_STATE */
1919 #define PALMAS_INT2_LINE_STATE_VAC_ACOK                         0x80
1920 #define PALMAS_INT2_LINE_STATE_VAC_ACOK_SHIFT                   7
1921 #define PALMAS_INT2_LINE_STATE_SHORT                            0x40
1922 #define PALMAS_INT2_LINE_STATE_SHORT_SHIFT                      6
1923 #define PALMAS_INT2_LINE_STATE_FBI_BB                           0x20
1924 #define PALMAS_INT2_LINE_STATE_FBI_BB_SHIFT                     5
1925 #define PALMAS_INT2_LINE_STATE_RESET_IN                         0x10
1926 #define PALMAS_INT2_LINE_STATE_RESET_IN_SHIFT                   4
1927 #define PALMAS_INT2_LINE_STATE_BATREMOVAL                       0x08
1928 #define PALMAS_INT2_LINE_STATE_BATREMOVAL_SHIFT                 3
1929 #define PALMAS_INT2_LINE_STATE_WDT                              0x04
1930 #define PALMAS_INT2_LINE_STATE_WDT_SHIFT                        2
1931 #define PALMAS_INT2_LINE_STATE_RTC_TIMER                        0x02
1932 #define PALMAS_INT2_LINE_STATE_RTC_TIMER_SHIFT                  1
1933 #define PALMAS_INT2_LINE_STATE_RTC_ALARM                        0x01
1934 #define PALMAS_INT2_LINE_STATE_RTC_ALARM_SHIFT                  0
1935
1936 /* Bit definitions for INT3_STATUS */
1937 #define PALMAS_INT3_STATUS_VBUS                                 0x80
1938 #define PALMAS_INT3_STATUS_VBUS_SHIFT                           7
1939 #define PALMAS_INT3_STATUS_VBUS_OTG                             0x40
1940 #define PALMAS_INT3_STATUS_VBUS_OTG_SHIFT                       6
1941 #define PALMAS_INT3_STATUS_ID                                   0x20
1942 #define PALMAS_INT3_STATUS_ID_SHIFT                             5
1943 #define PALMAS_INT3_STATUS_ID_OTG                               0x10
1944 #define PALMAS_INT3_STATUS_ID_OTG_SHIFT                         4
1945 #define PALMAS_INT3_STATUS_GPADC_EOC_RT                         0x08
1946 #define PALMAS_INT3_STATUS_GPADC_EOC_RT_SHIFT                   3
1947 #define PALMAS_INT3_STATUS_GPADC_EOC_SW                         0x04
1948 #define PALMAS_INT3_STATUS_GPADC_EOC_SW_SHIFT                   2
1949 #define PALMAS_INT3_STATUS_GPADC_AUTO_1                         0x02
1950 #define PALMAS_INT3_STATUS_GPADC_AUTO_1_SHIFT                   1
1951 #define PALMAS_INT3_STATUS_GPADC_AUTO_0                         0x01
1952 #define PALMAS_INT3_STATUS_GPADC_AUTO_0_SHIFT                   0
1953
1954 /* Bit definitions for INT3_MASK */
1955 #define PALMAS_INT3_MASK_VBUS                                   0x80
1956 #define PALMAS_INT3_MASK_VBUS_SHIFT                             7
1957 #define PALMAS_INT3_MASK_VBUS_OTG                               0x40
1958 #define PALMAS_INT3_MASK_VBUS_OTG_SHIFT                         6
1959 #define PALMAS_INT3_MASK_ID                                     0x20
1960 #define PALMAS_INT3_MASK_ID_SHIFT                               5
1961 #define PALMAS_INT3_MASK_ID_OTG                                 0x10
1962 #define PALMAS_INT3_MASK_ID_OTG_SHIFT                           4
1963 #define PALMAS_INT3_MASK_GPADC_EOC_RT                           0x08
1964 #define PALMAS_INT3_MASK_GPADC_EOC_RT_SHIFT                     3
1965 #define PALMAS_INT3_MASK_GPADC_EOC_SW                           0x04
1966 #define PALMAS_INT3_MASK_GPADC_EOC_SW_SHIFT                     2
1967 #define PALMAS_INT3_MASK_GPADC_AUTO_1                           0x02
1968 #define PALMAS_INT3_MASK_GPADC_AUTO_1_SHIFT                     1
1969 #define PALMAS_INT3_MASK_GPADC_AUTO_0                           0x01
1970 #define PALMAS_INT3_MASK_GPADC_AUTO_0_SHIFT                     0
1971
1972 /* Bit definitions for INT3_LINE_STATE */
1973 #define PALMAS_INT3_LINE_STATE_VBUS                             0x80
1974 #define PALMAS_INT3_LINE_STATE_VBUS_SHIFT                       7
1975 #define PALMAS_INT3_LINE_STATE_VBUS_OTG                         0x40
1976 #define PALMAS_INT3_LINE_STATE_VBUS_OTG_SHIFT                   6
1977 #define PALMAS_INT3_LINE_STATE_ID                               0x20
1978 #define PALMAS_INT3_LINE_STATE_ID_SHIFT                         5
1979 #define PALMAS_INT3_LINE_STATE_ID_OTG                           0x10
1980 #define PALMAS_INT3_LINE_STATE_ID_OTG_SHIFT                     4
1981 #define PALMAS_INT3_LINE_STATE_GPADC_EOC_RT                     0x08
1982 #define PALMAS_INT3_LINE_STATE_GPADC_EOC_RT_SHIFT               3
1983 #define PALMAS_INT3_LINE_STATE_GPADC_EOC_SW                     0x04
1984 #define PALMAS_INT3_LINE_STATE_GPADC_EOC_SW_SHIFT               2
1985 #define PALMAS_INT3_LINE_STATE_GPADC_AUTO_1                     0x02
1986 #define PALMAS_INT3_LINE_STATE_GPADC_AUTO_1_SHIFT               1
1987 #define PALMAS_INT3_LINE_STATE_GPADC_AUTO_0                     0x01
1988 #define PALMAS_INT3_LINE_STATE_GPADC_AUTO_0_SHIFT               0
1989
1990 /* Bit definitions for INT4_STATUS */
1991 #define PALMAS_INT4_STATUS_GPIO_7                               0x80
1992 #define PALMAS_INT4_STATUS_GPIO_7_SHIFT                         7
1993 #define PALMAS_INT4_STATUS_GPIO_6                               0x40
1994 #define PALMAS_INT4_STATUS_GPIO_6_SHIFT                         6
1995 #define PALMAS_INT4_STATUS_GPIO_5                               0x20
1996 #define PALMAS_INT4_STATUS_GPIO_5_SHIFT                         5
1997 #define PALMAS_INT4_STATUS_GPIO_4                               0x10
1998 #define PALMAS_INT4_STATUS_GPIO_4_SHIFT                         4
1999 #define PALMAS_INT4_STATUS_GPIO_3                               0x08
2000 #define PALMAS_INT4_STATUS_GPIO_3_SHIFT                         3
2001 #define PALMAS_INT4_STATUS_GPIO_2                               0x04
2002 #define PALMAS_INT4_STATUS_GPIO_2_SHIFT                         2
2003 #define PALMAS_INT4_STATUS_GPIO_1                               0x02
2004 #define PALMAS_INT4_STATUS_GPIO_1_SHIFT                         1
2005 #define PALMAS_INT4_STATUS_GPIO_0                               0x01
2006 #define PALMAS_INT4_STATUS_GPIO_0_SHIFT                         0
2007
2008 /* Bit definitions for INT4_MASK */
2009 #define PALMAS_INT4_MASK_GPIO_7                                 0x80
2010 #define PALMAS_INT4_MASK_GPIO_7_SHIFT                           7
2011 #define PALMAS_INT4_MASK_GPIO_6                                 0x40
2012 #define PALMAS_INT4_MASK_GPIO_6_SHIFT                           6
2013 #define PALMAS_INT4_MASK_GPIO_5                                 0x20
2014 #define PALMAS_INT4_MASK_GPIO_5_SHIFT                           5
2015 #define PALMAS_INT4_MASK_GPIO_4                                 0x10
2016 #define PALMAS_INT4_MASK_GPIO_4_SHIFT                           4
2017 #define PALMAS_INT4_MASK_GPIO_3                                 0x08
2018 #define PALMAS_INT4_MASK_GPIO_3_SHIFT                           3
2019 #define PALMAS_INT4_MASK_GPIO_2                                 0x04
2020 #define PALMAS_INT4_MASK_GPIO_2_SHIFT                           2
2021 #define PALMAS_INT4_MASK_GPIO_1                                 0x02
2022 #define PALMAS_INT4_MASK_GPIO_1_SHIFT                           1
2023 #define PALMAS_INT4_MASK_GPIO_0                                 0x01
2024 #define PALMAS_INT4_MASK_GPIO_0_SHIFT                           0
2025
2026 /* Bit definitions for INT4_LINE_STATE */
2027 #define PALMAS_INT4_LINE_STATE_GPIO_7                           0x80
2028 #define PALMAS_INT4_LINE_STATE_GPIO_7_SHIFT                     7
2029 #define PALMAS_INT4_LINE_STATE_GPIO_6                           0x40
2030 #define PALMAS_INT4_LINE_STATE_GPIO_6_SHIFT                     6
2031 #define PALMAS_INT4_LINE_STATE_GPIO_5                           0x20
2032 #define PALMAS_INT4_LINE_STATE_GPIO_5_SHIFT                     5
2033 #define PALMAS_INT4_LINE_STATE_GPIO_4                           0x10
2034 #define PALMAS_INT4_LINE_STATE_GPIO_4_SHIFT                     4
2035 #define PALMAS_INT4_LINE_STATE_GPIO_3                           0x08
2036 #define PALMAS_INT4_LINE_STATE_GPIO_3_SHIFT                     3
2037 #define PALMAS_INT4_LINE_STATE_GPIO_2                           0x04
2038 #define PALMAS_INT4_LINE_STATE_GPIO_2_SHIFT                     2
2039 #define PALMAS_INT4_LINE_STATE_GPIO_1                           0x02
2040 #define PALMAS_INT4_LINE_STATE_GPIO_1_SHIFT                     1
2041 #define PALMAS_INT4_LINE_STATE_GPIO_0                           0x01
2042 #define PALMAS_INT4_LINE_STATE_GPIO_0_SHIFT                     0
2043
2044 /* Bit definitions for INT4_EDGE_DETECT1 */
2045 #define PALMAS_INT4_EDGE_DETECT1_GPIO_3_RISING                  0x80
2046 #define PALMAS_INT4_EDGE_DETECT1_GPIO_3_RISING_SHIFT            7
2047 #define PALMAS_INT4_EDGE_DETECT1_GPIO_3_FALLING                 0x40
2048 #define PALMAS_INT4_EDGE_DETECT1_GPIO_3_FALLING_SHIFT           6
2049 #define PALMAS_INT4_EDGE_DETECT1_GPIO_2_RISING                  0x20
2050 #define PALMAS_INT4_EDGE_DETECT1_GPIO_2_RISING_SHIFT            5
2051 #define PALMAS_INT4_EDGE_DETECT1_GPIO_2_FALLING                 0x10
2052 #define PALMAS_INT4_EDGE_DETECT1_GPIO_2_FALLING_SHIFT           4
2053 #define PALMAS_INT4_EDGE_DETECT1_GPIO_1_RISING                  0x08
2054 #define PALMAS_INT4_EDGE_DETECT1_GPIO_1_RISING_SHIFT            3
2055 #define PALMAS_INT4_EDGE_DETECT1_GPIO_1_FALLING                 0x04
2056 #define PALMAS_INT4_EDGE_DETECT1_GPIO_1_FALLING_SHIFT           2
2057 #define PALMAS_INT4_EDGE_DETECT1_GPIO_0_RISING                  0x02
2058 #define PALMAS_INT4_EDGE_DETECT1_GPIO_0_RISING_SHIFT            1
2059 #define PALMAS_INT4_EDGE_DETECT1_GPIO_0_FALLING                 0x01
2060 #define PALMAS_INT4_EDGE_DETECT1_GPIO_0_FALLING_SHIFT           0
2061
2062 /* Bit definitions for INT4_EDGE_DETECT2 */
2063 #define PALMAS_INT4_EDGE_DETECT2_GPIO_7_RISING                  0x80
2064 #define PALMAS_INT4_EDGE_DETECT2_GPIO_7_RISING_SHIFT            7
2065 #define PALMAS_INT4_EDGE_DETECT2_GPIO_7_FALLING                 0x40
2066 #define PALMAS_INT4_EDGE_DETECT2_GPIO_7_FALLING_SHIFT           6
2067 #define PALMAS_INT4_EDGE_DETECT2_GPIO_6_RISING                  0x20
2068 #define PALMAS_INT4_EDGE_DETECT2_GPIO_6_RISING_SHIFT            5
2069 #define PALMAS_INT4_EDGE_DETECT2_GPIO_6_FALLING                 0x10
2070 #define PALMAS_INT4_EDGE_DETECT2_GPIO_6_FALLING_SHIFT           4
2071 #define PALMAS_INT4_EDGE_DETECT2_GPIO_5_RISING                  0x08
2072 #define PALMAS_INT4_EDGE_DETECT2_GPIO_5_RISING_SHIFT            3
2073 #define PALMAS_INT4_EDGE_DETECT2_GPIO_5_FALLING                 0x04
2074 #define PALMAS_INT4_EDGE_DETECT2_GPIO_5_FALLING_SHIFT           2
2075 #define PALMAS_INT4_EDGE_DETECT2_GPIO_4_RISING                  0x02
2076 #define PALMAS_INT4_EDGE_DETECT2_GPIO_4_RISING_SHIFT            1
2077 #define PALMAS_INT4_EDGE_DETECT2_GPIO_4_FALLING                 0x01
2078 #define PALMAS_INT4_EDGE_DETECT2_GPIO_4_FALLING_SHIFT           0
2079
2080 /* Bit definitions for INT_CTRL */
2081 #define PALMAS_INT_CTRL_INT_PENDING                             0x04
2082 #define PALMAS_INT_CTRL_INT_PENDING_SHIFT                       2
2083 #define PALMAS_INT_CTRL_INT_CLEAR                               0x01
2084 #define PALMAS_INT_CTRL_INT_CLEAR_SHIFT                         0
2085
2086 /* Registers for function USB_OTG */
2087 #define PALMAS_USB_WAKEUP                                       0x3
2088 #define PALMAS_USB_VBUS_CTRL_SET                                0x4
2089 #define PALMAS_USB_VBUS_CTRL_CLR                                0x5
2090 #define PALMAS_USB_ID_CTRL_SET                                  0x6
2091 #define PALMAS_USB_ID_CTRL_CLEAR                                0x7
2092 #define PALMAS_USB_VBUS_INT_SRC                                 0x8
2093 #define PALMAS_USB_VBUS_INT_LATCH_SET                           0x9
2094 #define PALMAS_USB_VBUS_INT_LATCH_CLR                           0xA
2095 #define PALMAS_USB_VBUS_INT_EN_LO_SET                           0xB
2096 #define PALMAS_USB_VBUS_INT_EN_LO_CLR                           0xC
2097 #define PALMAS_USB_VBUS_INT_EN_HI_SET                           0xD
2098 #define PALMAS_USB_VBUS_INT_EN_HI_CLR                           0xE
2099 #define PALMAS_USB_ID_INT_SRC                                   0xF
2100 #define PALMAS_USB_ID_INT_LATCH_SET                             0x10
2101 #define PALMAS_USB_ID_INT_LATCH_CLR                             0x11
2102 #define PALMAS_USB_ID_INT_EN_LO_SET                             0x12
2103 #define PALMAS_USB_ID_INT_EN_LO_CLR                             0x13
2104 #define PALMAS_USB_ID_INT_EN_HI_SET                             0x14
2105 #define PALMAS_USB_ID_INT_EN_HI_CLR                             0x15
2106 #define PALMAS_USB_OTG_ADP_CTRL                                 0x16
2107 #define PALMAS_USB_OTG_ADP_HIGH                                 0x17
2108 #define PALMAS_USB_OTG_ADP_LOW                                  0x18
2109 #define PALMAS_USB_OTG_ADP_RISE                                 0x19
2110 #define PALMAS_USB_OTG_REVISION                                 0x1A
2111
2112 /* Bit definitions for USB_WAKEUP */
2113 #define PALMAS_USB_WAKEUP_ID_WK_UP_COMP                         0x01
2114 #define PALMAS_USB_WAKEUP_ID_WK_UP_COMP_SHIFT                   0
2115
2116 /* Bit definitions for USB_VBUS_CTRL_SET */
2117 #define PALMAS_USB_VBUS_CTRL_SET_VBUS_CHRG_VSYS                 0x80
2118 #define PALMAS_USB_VBUS_CTRL_SET_VBUS_CHRG_VSYS_SHIFT           7
2119 #define PALMAS_USB_VBUS_CTRL_SET_VBUS_DISCHRG                   0x20
2120 #define PALMAS_USB_VBUS_CTRL_SET_VBUS_DISCHRG_SHIFT             5
2121 #define PALMAS_USB_VBUS_CTRL_SET_VBUS_IADP_SRC                  0x10
2122 #define PALMAS_USB_VBUS_CTRL_SET_VBUS_IADP_SRC_SHIFT            4
2123 #define PALMAS_USB_VBUS_CTRL_SET_VBUS_IADP_SINK                 0x08
2124 #define PALMAS_USB_VBUS_CTRL_SET_VBUS_IADP_SINK_SHIFT           3
2125 #define PALMAS_USB_VBUS_CTRL_SET_VBUS_ACT_COMP                  0x04
2126 #define PALMAS_USB_VBUS_CTRL_SET_VBUS_ACT_COMP_SHIFT            2
2127
2128 /* Bit definitions for USB_VBUS_CTRL_CLR */
2129 #define PALMAS_USB_VBUS_CTRL_CLR_VBUS_CHRG_VSYS                 0x80
2130 #define PALMAS_USB_VBUS_CTRL_CLR_VBUS_CHRG_VSYS_SHIFT           7
2131 #define PALMAS_USB_VBUS_CTRL_CLR_VBUS_DISCHRG                   0x20
2132 #define PALMAS_USB_VBUS_CTRL_CLR_VBUS_DISCHRG_SHIFT             5
2133 #define PALMAS_USB_VBUS_CTRL_CLR_VBUS_IADP_SRC                  0x10
2134 #define PALMAS_USB_VBUS_CTRL_CLR_VBUS_IADP_SRC_SHIFT            4
2135 #define PALMAS_USB_VBUS_CTRL_CLR_VBUS_IADP_SINK                 0x08
2136 #define PALMAS_USB_VBUS_CTRL_CLR_VBUS_IADP_SINK_SHIFT           3
2137 #define PALMAS_USB_VBUS_CTRL_CLR_VBUS_ACT_COMP                  0x04
2138 #define PALMAS_USB_VBUS_CTRL_CLR_VBUS_ACT_COMP_SHIFT            2
2139
2140 /* Bit definitions for USB_ID_CTRL_SET */
2141 #define PALMAS_USB_ID_CTRL_SET_ID_PU_220K                       0x80
2142 #define PALMAS_USB_ID_CTRL_SET_ID_PU_220K_SHIFT                 7
2143 #define PALMAS_USB_ID_CTRL_SET_ID_PU_100K                       0x40
2144 #define PALMAS_USB_ID_CTRL_SET_ID_PU_100K_SHIFT                 6
2145 #define PALMAS_USB_ID_CTRL_SET_ID_GND_DRV                       0x20
2146 #define PALMAS_USB_ID_CTRL_SET_ID_GND_DRV_SHIFT                 5
2147 #define PALMAS_USB_ID_CTRL_SET_ID_SRC_16U                       0x10
2148 #define PALMAS_USB_ID_CTRL_SET_ID_SRC_16U_SHIFT                 4
2149 #define PALMAS_USB_ID_CTRL_SET_ID_SRC_5U                        0x08
2150 #define PALMAS_USB_ID_CTRL_SET_ID_SRC_5U_SHIFT                  3
2151 #define PALMAS_USB_ID_CTRL_SET_ID_ACT_COMP                      0x04
2152 #define PALMAS_USB_ID_CTRL_SET_ID_ACT_COMP_SHIFT                2
2153
2154 /* Bit definitions for USB_ID_CTRL_CLEAR */
2155 #define PALMAS_USB_ID_CTRL_CLEAR_ID_PU_220K                     0x80
2156 #define PALMAS_USB_ID_CTRL_CLEAR_ID_PU_220K_SHIFT               7
2157 #define PALMAS_USB_ID_CTRL_CLEAR_ID_PU_100K                     0x40
2158 #define PALMAS_USB_ID_CTRL_CLEAR_ID_PU_100K_SHIFT               6
2159 #define PALMAS_USB_ID_CTRL_CLEAR_ID_GND_DRV                     0x20
2160 #define PALMAS_USB_ID_CTRL_CLEAR_ID_GND_DRV_SHIFT               5
2161 #define PALMAS_USB_ID_CTRL_CLEAR_ID_SRC_16U                     0x10
2162 #define PALMAS_USB_ID_CTRL_CLEAR_ID_SRC_16U_SHIFT               4
2163 #define PALMAS_USB_ID_CTRL_CLEAR_ID_SRC_5U                      0x08
2164 #define PALMAS_USB_ID_CTRL_CLEAR_ID_SRC_5U_SHIFT                3
2165 #define PALMAS_USB_ID_CTRL_CLEAR_ID_ACT_COMP                    0x04
2166 #define PALMAS_USB_ID_CTRL_CLEAR_ID_ACT_COMP_SHIFT              2
2167
2168 /* Bit definitions for USB_VBUS_INT_SRC */
2169 #define PALMAS_USB_VBUS_INT_SRC_VOTG_SESS_VLD                   0x80
2170 #define PALMAS_USB_VBUS_INT_SRC_VOTG_SESS_VLD_SHIFT             7
2171 #define PALMAS_USB_VBUS_INT_SRC_VADP_PRB                        0x40
2172 #define PALMAS_USB_VBUS_INT_SRC_VADP_PRB_SHIFT                  6
2173 #define PALMAS_USB_VBUS_INT_SRC_VADP_SNS                        0x20
2174 #define PALMAS_USB_VBUS_INT_SRC_VADP_SNS_SHIFT                  5
2175 #define PALMAS_USB_VBUS_INT_SRC_VA_VBUS_VLD                     0x08
2176 #define PALMAS_USB_VBUS_INT_SRC_VA_VBUS_VLD_SHIFT               3
2177 #define PALMAS_USB_VBUS_INT_SRC_VA_SESS_VLD                     0x04
2178 #define PALMAS_USB_VBUS_INT_SRC_VA_SESS_VLD_SHIFT               2
2179 #define PALMAS_USB_VBUS_INT_SRC_VB_SESS_VLD                     0x02
2180 #define PALMAS_USB_VBUS_INT_SRC_VB_SESS_VLD_SHIFT               1
2181 #define PALMAS_USB_VBUS_INT_SRC_VB_SESS_END                     0x01
2182 #define PALMAS_USB_VBUS_INT_SRC_VB_SESS_END_SHIFT               0
2183
2184 /* Bit definitions for USB_VBUS_INT_LATCH_SET */
2185 #define PALMAS_USB_VBUS_INT_LATCH_SET_VOTG_SESS_VLD             0x80
2186 #define PALMAS_USB_VBUS_INT_LATCH_SET_VOTG_SESS_VLD_SHIFT       7
2187 #define PALMAS_USB_VBUS_INT_LATCH_SET_VADP_PRB                  0x40
2188 #define PALMAS_USB_VBUS_INT_LATCH_SET_VADP_PRB_SHIFT            6
2189 #define PALMAS_USB_VBUS_INT_LATCH_SET_VADP_SNS                  0x20
2190 #define PALMAS_USB_VBUS_INT_LATCH_SET_VADP_SNS_SHIFT            5
2191 #define PALMAS_USB_VBUS_INT_LATCH_SET_ADP                       0x10
2192 #define PALMAS_USB_VBUS_INT_LATCH_SET_ADP_SHIFT                 4
2193 #define PALMAS_USB_VBUS_INT_LATCH_SET_VA_VBUS_VLD               0x08
2194 #define PALMAS_USB_VBUS_INT_LATCH_SET_VA_VBUS_VLD_SHIFT         3
2195 #define PALMAS_USB_VBUS_INT_LATCH_SET_VA_SESS_VLD               0x04
2196 #define PALMAS_USB_VBUS_INT_LATCH_SET_VA_SESS_VLD_SHIFT         2
2197 #define PALMAS_USB_VBUS_INT_LATCH_SET_VB_SESS_VLD               0x02
2198 #define PALMAS_USB_VBUS_INT_LATCH_SET_VB_SESS_VLD_SHIFT         1
2199 #define PALMAS_USB_VBUS_INT_LATCH_SET_VB_SESS_END               0x01
2200 #define PALMAS_USB_VBUS_INT_LATCH_SET_VB_SESS_END_SHIFT         0
2201
2202 /* Bit definitions for USB_VBUS_INT_LATCH_CLR */
2203 #define PALMAS_USB_VBUS_INT_LATCH_CLR_VOTG_SESS_VLD             0x80
2204 #define PALMAS_USB_VBUS_INT_LATCH_CLR_VOTG_SESS_VLD_SHIFT       7
2205 #define PALMAS_USB_VBUS_INT_LATCH_CLR_VADP_PRB                  0x40
2206 #define PALMAS_USB_VBUS_INT_LATCH_CLR_VADP_PRB_SHIFT            6
2207 #define PALMAS_USB_VBUS_INT_LATCH_CLR_VADP_SNS                  0x20
2208 #define PALMAS_USB_VBUS_INT_LATCH_CLR_VADP_SNS_SHIFT            5
2209 #define PALMAS_USB_VBUS_INT_LATCH_CLR_ADP                       0x10
2210 #define PALMAS_USB_VBUS_INT_LATCH_CLR_ADP_SHIFT                 4
2211 #define PALMAS_USB_VBUS_INT_LATCH_CLR_VA_VBUS_VLD               0x08
2212 #define PALMAS_USB_VBUS_INT_LATCH_CLR_VA_VBUS_VLD_SHIFT         3
2213 #define PALMAS_USB_VBUS_INT_LATCH_CLR_VA_SESS_VLD               0x04
2214 #define PALMAS_USB_VBUS_INT_LATCH_CLR_VA_SESS_VLD_SHIFT         2
2215 #define PALMAS_USB_VBUS_INT_LATCH_CLR_VB_SESS_VLD               0x02
2216 #define PALMAS_USB_VBUS_INT_LATCH_CLR_VB_SESS_VLD_SHIFT         1
2217 #define PALMAS_USB_VBUS_INT_LATCH_CLR_VB_SESS_END               0x01
2218 #define PALMAS_USB_VBUS_INT_LATCH_CLR_VB_SESS_END_SHIFT         0
2219
2220 /* Bit definitions for USB_VBUS_INT_EN_LO_SET */
2221 #define PALMAS_USB_VBUS_INT_EN_LO_SET_VOTG_SESS_VLD             0x80
2222 #define PALMAS_USB_VBUS_INT_EN_LO_SET_VOTG_SESS_VLD_SHIFT       7
2223 #define PALMAS_USB_VBUS_INT_EN_LO_SET_VADP_PRB                  0x40
2224 #define PALMAS_USB_VBUS_INT_EN_LO_SET_VADP_PRB_SHIFT            6
2225 #define PALMAS_USB_VBUS_INT_EN_LO_SET_VADP_SNS                  0x20
2226 #define PALMAS_USB_VBUS_INT_EN_LO_SET_VADP_SNS_SHIFT            5
2227 #define PALMAS_USB_VBUS_INT_EN_LO_SET_VA_VBUS_VLD               0x08
2228 #define PALMAS_USB_VBUS_INT_EN_LO_SET_VA_VBUS_VLD_SHIFT         3
2229 #define PALMAS_USB_VBUS_INT_EN_LO_SET_VA_SESS_VLD               0x04
2230 #define PALMAS_USB_VBUS_INT_EN_LO_SET_VA_SESS_VLD_SHIFT         2
2231 #define PALMAS_USB_VBUS_INT_EN_LO_SET_VB_SESS_VLD               0x02
2232 #define PALMAS_USB_VBUS_INT_EN_LO_SET_VB_SESS_VLD_SHIFT         1
2233 #define PALMAS_USB_VBUS_INT_EN_LO_SET_VB_SESS_END               0x01
2234 #define PALMAS_USB_VBUS_INT_EN_LO_SET_VB_SESS_END_SHIFT         0
2235
2236 /* Bit definitions for USB_VBUS_INT_EN_LO_CLR */
2237 #define PALMAS_USB_VBUS_INT_EN_LO_CLR_VOTG_SESS_VLD             0x80
2238 #define PALMAS_USB_VBUS_INT_EN_LO_CLR_VOTG_SESS_VLD_SHIFT       7
2239 #define PALMAS_USB_VBUS_INT_EN_LO_CLR_VADP_PRB                  0x40
2240 #define PALMAS_USB_VBUS_INT_EN_LO_CLR_VADP_PRB_SHIFT            6
2241 #define PALMAS_USB_VBUS_INT_EN_LO_CLR_VADP_SNS                  0x20
2242 #define PALMAS_USB_VBUS_INT_EN_LO_CLR_VADP_SNS_SHIFT            5
2243 #define PALMAS_USB_VBUS_INT_EN_LO_CLR_VA_VBUS_VLD               0x08
2244 #define PALMAS_USB_VBUS_INT_EN_LO_CLR_VA_VBUS_VLD_SHIFT         3
2245 #define PALMAS_USB_VBUS_INT_EN_LO_CLR_VA_SESS_VLD               0x04
2246 #define PALMAS_USB_VBUS_INT_EN_LO_CLR_VA_SESS_VLD_SHIFT         2
2247 #define PALMAS_USB_VBUS_INT_EN_LO_CLR_VB_SESS_VLD               0x02
2248 #define PALMAS_USB_VBUS_INT_EN_LO_CLR_VB_SESS_VLD_SHIFT         1
2249 #define PALMAS_USB_VBUS_INT_EN_LO_CLR_VB_SESS_END               0x01
2250 #define PALMAS_USB_VBUS_INT_EN_LO_CLR_VB_SESS_END_SHIFT         0
2251
2252 /* Bit definitions for USB_VBUS_INT_EN_HI_SET */
2253 #define PALMAS_USB_VBUS_INT_EN_HI_SET_VOTG_SESS_VLD             0x80
2254 #define PALMAS_USB_VBUS_INT_EN_HI_SET_VOTG_SESS_VLD_SHIFT       7
2255 #define PALMAS_USB_VBUS_INT_EN_HI_SET_VADP_PRB                  0x40
2256 #define PALMAS_USB_VBUS_INT_EN_HI_SET_VADP_PRB_SHIFT            6
2257 #define PALMAS_USB_VBUS_INT_EN_HI_SET_VADP_SNS                  0x20
2258 #define PALMAS_USB_VBUS_INT_EN_HI_SET_VADP_SNS_SHIFT            5
2259 #define PALMAS_USB_VBUS_INT_EN_HI_SET_ADP                       0x10
2260 #define PALMAS_USB_VBUS_INT_EN_HI_SET_ADP_SHIFT                 4
2261 #define PALMAS_USB_VBUS_INT_EN_HI_SET_VA_VBUS_VLD               0x08
2262 #define PALMAS_USB_VBUS_INT_EN_HI_SET_VA_VBUS_VLD_SHIFT         3
2263 #define PALMAS_USB_VBUS_INT_EN_HI_SET_VA_SESS_VLD               0x04
2264 #define PALMAS_USB_VBUS_INT_EN_HI_SET_VA_SESS_VLD_SHIFT         2
2265 #define PALMAS_USB_VBUS_INT_EN_HI_SET_VB_SESS_VLD               0x02
2266 #define PALMAS_USB_VBUS_INT_EN_HI_SET_VB_SESS_VLD_SHIFT         1
2267 #define PALMAS_USB_VBUS_INT_EN_HI_SET_VB_SESS_END               0x01
2268 #define PALMAS_USB_VBUS_INT_EN_HI_SET_VB_SESS_END_SHIFT         0
2269
2270 /* Bit definitions for USB_VBUS_INT_EN_HI_CLR */
2271 #define PALMAS_USB_VBUS_INT_EN_HI_CLR_VOTG_SESS_VLD             0x80
2272 #define PALMAS_USB_VBUS_INT_EN_HI_CLR_VOTG_SESS_VLD_SHIFT       7
2273 #define PALMAS_USB_VBUS_INT_EN_HI_CLR_VADP_PRB                  0x40
2274 #define PALMAS_USB_VBUS_INT_EN_HI_CLR_VADP_PRB_SHIFT            6
2275 #define PALMAS_USB_VBUS_INT_EN_HI_CLR_VADP_SNS                  0x20
2276 #define PALMAS_USB_VBUS_INT_EN_HI_CLR_VADP_SNS_SHIFT            5
2277 #define PALMAS_USB_VBUS_INT_EN_HI_CLR_ADP                       0x10
2278 #define PALMAS_USB_VBUS_INT_EN_HI_CLR_ADP_SHIFT                 4
2279 #define PALMAS_USB_VBUS_INT_EN_HI_CLR_VA_VBUS_VLD               0x08
2280 #define PALMAS_USB_VBUS_INT_EN_HI_CLR_VA_VBUS_VLD_SHIFT         3
2281 #define PALMAS_USB_VBUS_INT_EN_HI_CLR_VA_SESS_VLD               0x04
2282 #define PALMAS_USB_VBUS_INT_EN_HI_CLR_VA_SESS_VLD_SHIFT         2
2283 #define PALMAS_USB_VBUS_INT_EN_HI_CLR_VB_SESS_VLD               0x02
2284 #define PALMAS_USB_VBUS_INT_EN_HI_CLR_VB_SESS_VLD_SHIFT         1
2285 #define PALMAS_USB_VBUS_INT_EN_HI_CLR_VB_SESS_END               0x01
2286 #define PALMAS_USB_VBUS_INT_EN_HI_CLR_VB_SESS_END_SHIFT         0
2287
2288 /* Bit definitions for USB_ID_INT_SRC */
2289 #define PALMAS_USB_ID_INT_SRC_ID_FLOAT                          0x10
2290 #define PALMAS_USB_ID_INT_SRC_ID_FLOAT_SHIFT                    4
2291 #define PALMAS_USB_ID_INT_SRC_ID_A                              0x08
2292 #define PALMAS_USB_ID_INT_SRC_ID_A_SHIFT                        3
2293 #define PALMAS_USB_ID_INT_SRC_ID_B                              0x04
2294 #define PALMAS_USB_ID_INT_SRC_ID_B_SHIFT                        2
2295 #define PALMAS_USB_ID_INT_SRC_ID_C                              0x02
2296 #define PALMAS_USB_ID_INT_SRC_ID_C_SHIFT                        1
2297 #define PALMAS_USB_ID_INT_SRC_ID_GND                            0x01
2298 #define PALMAS_USB_ID_INT_SRC_ID_GND_SHIFT                      0
2299
2300 /* Bit definitions for USB_ID_INT_LATCH_SET */
2301 #define PALMAS_USB_ID_INT_LATCH_SET_ID_FLOAT                    0x10
2302 #define PALMAS_USB_ID_INT_LATCH_SET_ID_FLOAT_SHIFT              4
2303 #define PALMAS_USB_ID_INT_LATCH_SET_ID_A                        0x08
2304 #define PALMAS_USB_ID_INT_LATCH_SET_ID_A_SHIFT                  3
2305 #define PALMAS_USB_ID_INT_LATCH_SET_ID_B                        0x04
2306 #define PALMAS_USB_ID_INT_LATCH_SET_ID_B_SHIFT                  2
2307 #define PALMAS_USB_ID_INT_LATCH_SET_ID_C                        0x02
2308 #define PALMAS_USB_ID_INT_LATCH_SET_ID_C_SHIFT                  1
2309 #define PALMAS_USB_ID_INT_LATCH_SET_ID_GND                      0x01
2310 #define PALMAS_USB_ID_INT_LATCH_SET_ID_GND_SHIFT                0
2311
2312 /* Bit definitions for USB_ID_INT_LATCH_CLR */
2313 #define PALMAS_USB_ID_INT_LATCH_CLR_ID_FLOAT                    0x10
2314 #define PALMAS_USB_ID_INT_LATCH_CLR_ID_FLOAT_SHIFT              4
2315 #define PALMAS_USB_ID_INT_LATCH_CLR_ID_A                        0x08
2316 #define PALMAS_USB_ID_INT_LATCH_CLR_ID_A_SHIFT                  3
2317 #define PALMAS_USB_ID_INT_LATCH_CLR_ID_B                        0x04
2318 #define PALMAS_USB_ID_INT_LATCH_CLR_ID_B_SHIFT                  2
2319 #define PALMAS_USB_ID_INT_LATCH_CLR_ID_C                        0x02
2320 #define PALMAS_USB_ID_INT_LATCH_CLR_ID_C_SHIFT                  1
2321 #define PALMAS_USB_ID_INT_LATCH_CLR_ID_GND                      0x01
2322 #define PALMAS_USB_ID_INT_LATCH_CLR_ID_GND_SHIFT                0
2323
2324 /* Bit definitions for USB_ID_INT_EN_LO_SET */
2325 #define PALMAS_USB_ID_INT_EN_LO_SET_ID_FLOAT                    0x10
2326 #define PALMAS_USB_ID_INT_EN_LO_SET_ID_FLOAT_SHIFT              4
2327 #define PALMAS_USB_ID_INT_EN_LO_SET_ID_A                        0x08
2328 #define PALMAS_USB_ID_INT_EN_LO_SET_ID_A_SHIFT                  3
2329 #define PALMAS_USB_ID_INT_EN_LO_SET_ID_B                        0x04
2330 #define PALMAS_USB_ID_INT_EN_LO_SET_ID_B_SHIFT                  2
2331 #define PALMAS_USB_ID_INT_EN_LO_SET_ID_C                        0x02
2332 #define PALMAS_USB_ID_INT_EN_LO_SET_ID_C_SHIFT                  1
2333 #define PALMAS_USB_ID_INT_EN_LO_SET_ID_GND                      0x01
2334 #define PALMAS_USB_ID_INT_EN_LO_SET_ID_GND_SHIFT                0
2335
2336 /* Bit definitions for USB_ID_INT_EN_LO_CLR */
2337 #define PALMAS_USB_ID_INT_EN_LO_CLR_ID_FLOAT                    0x10
2338 #define PALMAS_USB_ID_INT_EN_LO_CLR_ID_FLOAT_SHIFT              4
2339 #define PALMAS_USB_ID_INT_EN_LO_CLR_ID_A                        0x08
2340 #define PALMAS_USB_ID_INT_EN_LO_CLR_ID_A_SHIFT                  3
2341 #define PALMAS_USB_ID_INT_EN_LO_CLR_ID_B                        0x04
2342 #define PALMAS_USB_ID_INT_EN_LO_CLR_ID_B_SHIFT                  2
2343 #define PALMAS_USB_ID_INT_EN_LO_CLR_ID_C                        0x02
2344 #define PALMAS_USB_ID_INT_EN_LO_CLR_ID_C_SHIFT                  1
2345 #define PALMAS_USB_ID_INT_EN_LO_CLR_ID_GND                      0x01
2346 #define PALMAS_USB_ID_INT_EN_LO_CLR_ID_GND_SHIFT                0
2347
2348 /* Bit definitions for USB_ID_INT_EN_HI_SET */
2349 #define PALMAS_USB_ID_INT_EN_HI_SET_ID_FLOAT                    0x10
2350 #define PALMAS_USB_ID_INT_EN_HI_SET_ID_FLOAT_SHIFT              4
2351 #define PALMAS_USB_ID_INT_EN_HI_SET_ID_A                        0x08
2352 #define PALMAS_USB_ID_INT_EN_HI_SET_ID_A_SHIFT                  3
2353 #define PALMAS_USB_ID_INT_EN_HI_SET_ID_B                        0x04
2354 #define PALMAS_USB_ID_INT_EN_HI_SET_ID_B_SHIFT                  2
2355 #define PALMAS_USB_ID_INT_EN_HI_SET_ID_C                        0x02
2356 #define PALMAS_USB_ID_INT_EN_HI_SET_ID_C_SHIFT                  1
2357 #define PALMAS_USB_ID_INT_EN_HI_SET_ID_GND                      0x01
2358 #define PALMAS_USB_ID_INT_EN_HI_SET_ID_GND_SHIFT                0
2359
2360 /* Bit definitions for USB_ID_INT_EN_HI_CLR */
2361 #define PALMAS_USB_ID_INT_EN_HI_CLR_ID_FLOAT                    0x10
2362 #define PALMAS_USB_ID_INT_EN_HI_CLR_ID_FLOAT_SHIFT              4
2363 #define PALMAS_USB_ID_INT_EN_HI_CLR_ID_A                        0x08
2364 #define PALMAS_USB_ID_INT_EN_HI_CLR_ID_A_SHIFT                  3
2365 #define PALMAS_USB_ID_INT_EN_HI_CLR_ID_B                        0x04
2366 #define PALMAS_USB_ID_INT_EN_HI_CLR_ID_B_SHIFT                  2
2367 #define PALMAS_USB_ID_INT_EN_HI_CLR_ID_C                        0x02
2368 #define PALMAS_USB_ID_INT_EN_HI_CLR_ID_C_SHIFT                  1
2369 #define PALMAS_USB_ID_INT_EN_HI_CLR_ID_GND                      0x01
2370 #define PALMAS_USB_ID_INT_EN_HI_CLR_ID_GND_SHIFT                0
2371
2372 /* Bit definitions for USB_OTG_ADP_CTRL */
2373 #define PALMAS_USB_OTG_ADP_CTRL_ADP_EN                          0x04
2374 #define PALMAS_USB_OTG_ADP_CTRL_ADP_EN_SHIFT                    2
2375 #define PALMAS_USB_OTG_ADP_CTRL_ADP_MODE_MASK                   0x03
2376 #define PALMAS_USB_OTG_ADP_CTRL_ADP_MODE_SHIFT                  0
2377
2378 /* Bit definitions for USB_OTG_ADP_HIGH */
2379 #define PALMAS_USB_OTG_ADP_HIGH_T_ADP_HIGH_MASK                 0xff
2380 #define PALMAS_USB_OTG_ADP_HIGH_T_ADP_HIGH_SHIFT                0
2381
2382 /* Bit definitions for USB_OTG_ADP_LOW */
2383 #define PALMAS_USB_OTG_ADP_LOW_T_ADP_LOW_MASK                   0xff
2384 #define PALMAS_USB_OTG_ADP_LOW_T_ADP_LOW_SHIFT                  0
2385
2386 /* Bit definitions for USB_OTG_ADP_RISE */
2387 #define PALMAS_USB_OTG_ADP_RISE_T_ADP_RISE_MASK                 0xff
2388 #define PALMAS_USB_OTG_ADP_RISE_T_ADP_RISE_SHIFT                0
2389
2390 /* Bit definitions for USB_OTG_REVISION */
2391 #define PALMAS_USB_OTG_REVISION_OTG_REV                         0x01
2392 #define PALMAS_USB_OTG_REVISION_OTG_REV_SHIFT                   0
2393
2394 /* Registers for function VIBRATOR */
2395 #define PALMAS_VIBRA_CTRL                                       0x0
2396
2397 /* Bit definitions for VIBRA_CTRL */
2398 #define PALMAS_VIBRA_CTRL_PWM_DUTY_SEL_MASK                     0x06
2399 #define PALMAS_VIBRA_CTRL_PWM_DUTY_SEL_SHIFT                    1
2400 #define PALMAS_VIBRA_CTRL_PWM_FREQ_SEL                          0x01
2401 #define PALMAS_VIBRA_CTRL_PWM_FREQ_SEL_SHIFT                    0
2402
2403 /* Registers for function GPIO */
2404 #define PALMAS_GPIO_DATA_IN                                     0x0
2405 #define PALMAS_GPIO_DATA_DIR                                    0x1
2406 #define PALMAS_GPIO_DATA_OUT                                    0x2
2407 #define PALMAS_GPIO_DEBOUNCE_EN                                 0x3
2408 #define PALMAS_GPIO_CLEAR_DATA_OUT                              0x4
2409 #define PALMAS_GPIO_SET_DATA_OUT                                0x5
2410 #define PALMAS_PU_PD_GPIO_CTRL1                                 0x6
2411 #define PALMAS_PU_PD_GPIO_CTRL2                                 0x7
2412 #define PALMAS_OD_OUTPUT_GPIO_CTRL                              0x8
2413
2414 /* Bit definitions for GPIO_DATA_IN */
2415 #define PALMAS_GPIO_DATA_IN_GPIO_7_IN                           0x80
2416 #define PALMAS_GPIO_DATA_IN_GPIO_7_IN_SHIFT                     7
2417 #define PALMAS_GPIO_DATA_IN_GPIO_6_IN                           0x40
2418 #define PALMAS_GPIO_DATA_IN_GPIO_6_IN_SHIFT                     6
2419 #define PALMAS_GPIO_DATA_IN_GPIO_5_IN                           0x20
2420 #define PALMAS_GPIO_DATA_IN_GPIO_5_IN_SHIFT                     5
2421 #define PALMAS_GPIO_DATA_IN_GPIO_4_IN                           0x10
2422 #define PALMAS_GPIO_DATA_IN_GPIO_4_IN_SHIFT                     4
2423 #define PALMAS_GPIO_DATA_IN_GPIO_3_IN                           0x08
2424 #define PALMAS_GPIO_DATA_IN_GPIO_3_IN_SHIFT                     3
2425 #define PALMAS_GPIO_DATA_IN_GPIO_2_IN                           0x04
2426 #define PALMAS_GPIO_DATA_IN_GPIO_2_IN_SHIFT                     2
2427 #define PALMAS_GPIO_DATA_IN_GPIO_1_IN                           0x02
2428 #define PALMAS_GPIO_DATA_IN_GPIO_1_IN_SHIFT                     1
2429 #define PALMAS_GPIO_DATA_IN_GPIO_0_IN                           0x01
2430 #define PALMAS_GPIO_DATA_IN_GPIO_0_IN_SHIFT                     0
2431
2432 /* Bit definitions for GPIO_DATA_DIR */
2433 #define PALMAS_GPIO_DATA_DIR_GPIO_7_DIR                         0x80
2434 #define PALMAS_GPIO_DATA_DIR_GPIO_7_DIR_SHIFT                   7
2435 #define PALMAS_GPIO_DATA_DIR_GPIO_6_DIR                         0x40
2436 #define PALMAS_GPIO_DATA_DIR_GPIO_6_DIR_SHIFT                   6
2437 #define PALMAS_GPIO_DATA_DIR_GPIO_5_DIR                         0x20
2438 #define PALMAS_GPIO_DATA_DIR_GPIO_5_DIR_SHIFT                   5
2439 #define PALMAS_GPIO_DATA_DIR_GPIO_4_DIR                         0x10
2440 #define PALMAS_GPIO_DATA_DIR_GPIO_4_DIR_SHIFT                   4
2441 #define PALMAS_GPIO_DATA_DIR_GPIO_3_DIR                         0x08
2442 #define PALMAS_GPIO_DATA_DIR_GPIO_3_DIR_SHIFT                   3
2443 #define PALMAS_GPIO_DATA_DIR_GPIO_2_DIR                         0x04
2444 #define PALMAS_GPIO_DATA_DIR_GPIO_2_DIR_SHIFT                   2
2445 #define PALMAS_GPIO_DATA_DIR_GPIO_1_DIR                         0x02
2446 #define PALMAS_GPIO_DATA_DIR_GPIO_1_DIR_SHIFT                   1
2447 #define PALMAS_GPIO_DATA_DIR_GPIO_0_DIR                         0x01
2448 #define PALMAS_GPIO_DATA_DIR_GPIO_0_DIR_SHIFT                   0
2449
2450 /* Bit definitions for GPIO_DATA_OUT */
2451 #define PALMAS_GPIO_DATA_OUT_GPIO_7_OUT                         0x80
2452 #define PALMAS_GPIO_DATA_OUT_GPIO_7_OUT_SHIFT                   7
2453 #define PALMAS_GPIO_DATA_OUT_GPIO_6_OUT                         0x40
2454 #define PALMAS_GPIO_DATA_OUT_GPIO_6_OUT_SHIFT                   6
2455 #define PALMAS_GPIO_DATA_OUT_GPIO_5_OUT                         0x20
2456 #define PALMAS_GPIO_DATA_OUT_GPIO_5_OUT_SHIFT                   5
2457 #define PALMAS_GPIO_DATA_OUT_GPIO_4_OUT                         0x10
2458 #define PALMAS_GPIO_DATA_OUT_GPIO_4_OUT_SHIFT                   4
2459 #define PALMAS_GPIO_DATA_OUT_GPIO_3_OUT                         0x08
2460 #define PALMAS_GPIO_DATA_OUT_GPIO_3_OUT_SHIFT                   3
2461 #define PALMAS_GPIO_DATA_OUT_GPIO_2_OUT                         0x04
2462 #define PALMAS_GPIO_DATA_OUT_GPIO_2_OUT_SHIFT                   2
2463 #define PALMAS_GPIO_DATA_OUT_GPIO_1_OUT                         0x02
2464 #define PALMAS_GPIO_DATA_OUT_GPIO_1_OUT_SHIFT                   1
2465 #define PALMAS_GPIO_DATA_OUT_GPIO_0_OUT                         0x01
2466 #define PALMAS_GPIO_DATA_OUT_GPIO_0_OUT_SHIFT                   0
2467
2468 /* Bit definitions for GPIO_DEBOUNCE_EN */
2469 #define PALMAS_GPIO_DEBOUNCE_EN_GPIO_7_DEBOUNCE_EN              0x80
2470 #define PALMAS_GPIO_DEBOUNCE_EN_GPIO_7_DEBOUNCE_EN_SHIFT        7
2471 #define PALMAS_GPIO_DEBOUNCE_EN_GPIO_6_DEBOUNCE_EN              0x40
2472 #define PALMAS_GPIO_DEBOUNCE_EN_GPIO_6_DEBOUNCE_EN_SHIFT        6
2473 #define PALMAS_GPIO_DEBOUNCE_EN_GPIO_5_DEBOUNCE_EN              0x20
2474 #define PALMAS_GPIO_DEBOUNCE_EN_GPIO_5_DEBOUNCE_EN_SHIFT        5
2475 #define PALMAS_GPIO_DEBOUNCE_EN_GPIO_4_DEBOUNCE_EN              0x10
2476 #define PALMAS_GPIO_DEBOUNCE_EN_GPIO_4_DEBOUNCE_EN_SHIFT        4
2477 #define PALMAS_GPIO_DEBOUNCE_EN_GPIO_3_DEBOUNCE_EN              0x08
2478 #define PALMAS_GPIO_DEBOUNCE_EN_GPIO_3_DEBOUNCE_EN_SHIFT        3
2479 #define PALMAS_GPIO_DEBOUNCE_EN_GPIO_2_DEBOUNCE_EN              0x04
2480 #define PALMAS_GPIO_DEBOUNCE_EN_GPIO_2_DEBOUNCE_EN_SHIFT        2
2481 #define PALMAS_GPIO_DEBOUNCE_EN_GPIO_1_DEBOUNCE_EN              0x02
2482 #define PALMAS_GPIO_DEBOUNCE_EN_GPIO_1_DEBOUNCE_EN_SHIFT        1
2483 #define PALMAS_GPIO_DEBOUNCE_EN_GPIO_0_DEBOUNCE_EN              0x01
2484 #define PALMAS_GPIO_DEBOUNCE_EN_GPIO_0_DEBOUNCE_EN_SHIFT        0
2485
2486 /* Bit definitions for GPIO_CLEAR_DATA_OUT */
2487 #define PALMAS_GPIO_CLEAR_DATA_OUT_GPIO_7_CLEAR_DATA_OUT        0x80
2488 #define PALMAS_GPIO_CLEAR_DATA_OUT_GPIO_7_CLEAR_DATA_OUT_SHIFT  7
2489 #define PALMAS_GPIO_CLEAR_DATA_OUT_GPIO_6_CLEAR_DATA_OUT        0x40
2490 #define PALMAS_GPIO_CLEAR_DATA_OUT_GPIO_6_CLEAR_DATA_OUT_SHIFT  6
2491 #define PALMAS_GPIO_CLEAR_DATA_OUT_GPIO_5_CLEAR_DATA_OUT        0x20
2492 #define PALMAS_GPIO_CLEAR_DATA_OUT_GPIO_5_CLEAR_DATA_OUT_SHIFT  5
2493 #define PALMAS_GPIO_CLEAR_DATA_OUT_GPIO_4_CLEAR_DATA_OUT        0x10
2494 #define PALMAS_GPIO_CLEAR_DATA_OUT_GPIO_4_CLEAR_DATA_OUT_SHIFT  4
2495 #define PALMAS_GPIO_CLEAR_DATA_OUT_GPIO_3_CLEAR_DATA_OUT        0x08
2496 #define PALMAS_GPIO_CLEAR_DATA_OUT_GPIO_3_CLEAR_DATA_OUT_SHIFT  3
2497 #define PALMAS_GPIO_CLEAR_DATA_OUT_GPIO_2_CLEAR_DATA_OUT        0x04
2498 #define PALMAS_GPIO_CLEAR_DATA_OUT_GPIO_2_CLEAR_DATA_OUT_SHIFT  2
2499 #define PALMAS_GPIO_CLEAR_DATA_OUT_GPIO_1_CLEAR_DATA_OUT        0x02
2500 #define PALMAS_GPIO_CLEAR_DATA_OUT_GPIO_1_CLEAR_DATA_OUT_SHIFT  1
2501 #define PALMAS_GPIO_CLEAR_DATA_OUT_GPIO_0_CLEAR_DATA_OUT        0x01
2502 #define PALMAS_GPIO_CLEAR_DATA_OUT_GPIO_0_CLEAR_DATA_OUT_SHIFT  0
2503
2504 /* Bit definitions for GPIO_SET_DATA_OUT */
2505 #define PALMAS_GPIO_SET_DATA_OUT_GPIO_7_SET_DATA_OUT            0x80
2506 #define PALMAS_GPIO_SET_DATA_OUT_GPIO_7_SET_DATA_OUT_SHIFT      7
2507 #define PALMAS_GPIO_SET_DATA_OUT_GPIO_6_SET_DATA_OUT            0x40
2508 #define PALMAS_GPIO_SET_DATA_OUT_GPIO_6_SET_DATA_OUT_SHIFT      6
2509 #define PALMAS_GPIO_SET_DATA_OUT_GPIO_5_SET_DATA_OUT            0x20
2510 #define PALMAS_GPIO_SET_DATA_OUT_GPIO_5_SET_DATA_OUT_SHIFT      5
2511 #define PALMAS_GPIO_SET_DATA_OUT_GPIO_4_SET_DATA_OUT            0x10
2512 #define PALMAS_GPIO_SET_DATA_OUT_GPIO_4_SET_DATA_OUT_SHIFT      4
2513 #define PALMAS_GPIO_SET_DATA_OUT_GPIO_3_SET_DATA_OUT            0x08
2514 #define PALMAS_GPIO_SET_DATA_OUT_GPIO_3_SET_DATA_OUT_SHIFT      3
2515 #define PALMAS_GPIO_SET_DATA_OUT_GPIO_2_SET_DATA_OUT            0x04
2516 #define PALMAS_GPIO_SET_DATA_OUT_GPIO_2_SET_DATA_OUT_SHIFT      2
2517 #define PALMAS_GPIO_SET_DATA_OUT_GPIO_1_SET_DATA_OUT            0x02
2518 #define PALMAS_GPIO_SET_DATA_OUT_GPIO_1_SET_DATA_OUT_SHIFT      1
2519 #define PALMAS_GPIO_SET_DATA_OUT_GPIO_0_SET_DATA_OUT            0x01
2520 #define PALMAS_GPIO_SET_DATA_OUT_GPIO_0_SET_DATA_OUT_SHIFT      0
2521
2522 /* Bit definitions for PU_PD_GPIO_CTRL1 */
2523 #define PALMAS_PU_PD_GPIO_CTRL1_GPIO_3_PD                       0x40
2524 #define PALMAS_PU_PD_GPIO_CTRL1_GPIO_3_PD_SHIFT                 6
2525 #define PALMAS_PU_PD_GPIO_CTRL1_GPIO_2_PU                       0x20
2526 #define PALMAS_PU_PD_GPIO_CTRL1_GPIO_2_PU_SHIFT                 5
2527 #define PALMAS_PU_PD_GPIO_CTRL1_GPIO_2_PD                       0x10
2528 #define PALMAS_PU_PD_GPIO_CTRL1_GPIO_2_PD_SHIFT                 4
2529 #define PALMAS_PU_PD_GPIO_CTRL1_GPIO_1_PU                       0x08
2530 #define PALMAS_PU_PD_GPIO_CTRL1_GPIO_1_PU_SHIFT                 3
2531 #define PALMAS_PU_PD_GPIO_CTRL1_GPIO_1_PD                       0x04
2532 #define PALMAS_PU_PD_GPIO_CTRL1_GPIO_1_PD_SHIFT                 2
2533 #define PALMAS_PU_PD_GPIO_CTRL1_GPIO_0_PD                       0x01
2534 #define PALMAS_PU_PD_GPIO_CTRL1_GPIO_0_PD_SHIFT                 0
2535
2536 /* Bit definitions for PU_PD_GPIO_CTRL2 */
2537 #define PALMAS_PU_PD_GPIO_CTRL2_GPIO_7_PD                       0x40
2538 #define PALMAS_PU_PD_GPIO_CTRL2_GPIO_7_PD_SHIFT                 6
2539 #define PALMAS_PU_PD_GPIO_CTRL2_GPIO_6_PU                       0x20
2540 #define PALMAS_PU_PD_GPIO_CTRL2_GPIO_6_PU_SHIFT                 5
2541 #define PALMAS_PU_PD_GPIO_CTRL2_GPIO_6_PD                       0x10
2542 #define PALMAS_PU_PD_GPIO_CTRL2_GPIO_6_PD_SHIFT                 4
2543 #define PALMAS_PU_PD_GPIO_CTRL2_GPIO_5_PU                       0x08
2544 #define PALMAS_PU_PD_GPIO_CTRL2_GPIO_5_PU_SHIFT                 3
2545 #define PALMAS_PU_PD_GPIO_CTRL2_GPIO_5_PD                       0x04
2546 #define PALMAS_PU_PD_GPIO_CTRL2_GPIO_5_PD_SHIFT                 2
2547 #define PALMAS_PU_PD_GPIO_CTRL2_GPIO_4_PU                       0x02
2548 #define PALMAS_PU_PD_GPIO_CTRL2_GPIO_4_PU_SHIFT                 1
2549 #define PALMAS_PU_PD_GPIO_CTRL2_GPIO_4_PD                       0x01
2550 #define PALMAS_PU_PD_GPIO_CTRL2_GPIO_4_PD_SHIFT                 0
2551
2552 /* Bit definitions for OD_OUTPUT_GPIO_CTRL */
2553 #define PALMAS_OD_OUTPUT_GPIO_CTRL_GPIO_5_OD                    0x20
2554 #define PALMAS_OD_OUTPUT_GPIO_CTRL_GPIO_5_OD_SHIFT              5
2555 #define PALMAS_OD_OUTPUT_GPIO_CTRL_GPIO_2_OD                    0x04
2556 #define PALMAS_OD_OUTPUT_GPIO_CTRL_GPIO_2_OD_SHIFT              2
2557 #define PALMAS_OD_OUTPUT_GPIO_CTRL_GPIO_1_OD                    0x02
2558 #define PALMAS_OD_OUTPUT_GPIO_CTRL_GPIO_1_OD_SHIFT              1
2559
2560 /* Registers for function GPADC */
2561 #define PALMAS_GPADC_CTRL1                                      0x0
2562 #define PALMAS_GPADC_CTRL2                                      0x1
2563 #define PALMAS_GPADC_RT_CTRL                                    0x2
2564 #define PALMAS_GPADC_AUTO_CTRL                                  0x3
2565 #define PALMAS_GPADC_STATUS                                     0x4
2566 #define PALMAS_GPADC_RT_SELECT                                  0x5
2567 #define PALMAS_GPADC_RT_CONV0_LSB                               0x6
2568 #define PALMAS_GPADC_RT_CONV0_MSB                               0x7
2569 #define PALMAS_GPADC_AUTO_SELECT                                0x8
2570 #define PALMAS_GPADC_AUTO_CONV0_LSB                             0x9
2571 #define PALMAS_GPADC_AUTO_CONV0_MSB                             0xA
2572 #define PALMAS_GPADC_AUTO_CONV1_LSB                             0xB
2573 #define PALMAS_GPADC_AUTO_CONV1_MSB                             0xC
2574 #define PALMAS_GPADC_SW_SELECT                                  0xD
2575 #define PALMAS_GPADC_SW_CONV0_LSB                               0xE
2576 #define PALMAS_GPADC_SW_CONV0_MSB                               0xF
2577 #define PALMAS_GPADC_THRES_CONV0_LSB                            0x10
2578 #define PALMAS_GPADC_THRES_CONV0_MSB                            0x11
2579 #define PALMAS_GPADC_THRES_CONV1_LSB                            0x12
2580 #define PALMAS_GPADC_THRES_CONV1_MSB                            0x13
2581 #define PALMAS_GPADC_SMPS_ILMONITOR_EN                          0x14
2582 #define PALMAS_GPADC_SMPS_VSEL_MONITORING                       0x15
2583
2584 /* Bit definitions for GPADC_CTRL1 */
2585 #define PALMAS_GPADC_CTRL1_RESERVED_MASK                        0xc0
2586 #define PALMAS_GPADC_CTRL1_RESERVED_SHIFT                       6
2587 #define PALMAS_GPADC_CTRL1_CURRENT_SRC_CH3_MASK                 0x30
2588 #define PALMAS_GPADC_CTRL1_CURRENT_SRC_CH3_SHIFT                4
2589 #define PALMAS_GPADC_CTRL1_CURRENT_SRC_CH0_MASK                 0x0c
2590 #define PALMAS_GPADC_CTRL1_CURRENT_SRC_CH0_SHIFT                2
2591 #define PALMAS_GPADC_CTRL1_BAT_REMOVAL_DET                      0x02
2592 #define PALMAS_GPADC_CTRL1_BAT_REMOVAL_DET_SHIFT                1
2593 #define PALMAS_GPADC_CTRL1_GPADC_FORCE                          0x01
2594 #define PALMAS_GPADC_CTRL1_GPADC_FORCE_SHIFT                    0
2595
2596 /* Bit definitions for GPADC_CTRL2 */
2597 #define PALMAS_GPADC_CTRL2_RESERVED_MASK                        0x06
2598 #define PALMAS_GPADC_CTRL2_RESERVED_SHIFT                       1
2599
2600 /* Bit definitions for GPADC_RT_CTRL */
2601 #define PALMAS_GPADC_RT_CTRL_EXTEND_DELAY                       0x02
2602 #define PALMAS_GPADC_RT_CTRL_EXTEND_DELAY_SHIFT                 1
2603 #define PALMAS_GPADC_RT_CTRL_START_POLARITY                     0x01
2604 #define PALMAS_GPADC_RT_CTRL_START_POLARITY_SHIFT               0
2605
2606 /* Bit definitions for GPADC_AUTO_CTRL */
2607 #define PALMAS_GPADC_AUTO_CTRL_SHUTDOWN_CONV1                   0x80
2608 #define PALMAS_GPADC_AUTO_CTRL_SHUTDOWN_CONV1_SHIFT             7
2609 #define PALMAS_GPADC_AUTO_CTRL_SHUTDOWN_CONV0                   0x40
2610 #define PALMAS_GPADC_AUTO_CTRL_SHUTDOWN_CONV0_SHIFT             6
2611 #define PALMAS_GPADC_AUTO_CTRL_AUTO_CONV1_EN                    0x20
2612 #define PALMAS_GPADC_AUTO_CTRL_AUTO_CONV1_EN_SHIFT              5
2613 #define PALMAS_GPADC_AUTO_CTRL_AUTO_CONV0_EN                    0x10
2614 #define PALMAS_GPADC_AUTO_CTRL_AUTO_CONV0_EN_SHIFT              4
2615 #define PALMAS_GPADC_AUTO_CTRL_COUNTER_CONV_MASK                0x0f
2616 #define PALMAS_GPADC_AUTO_CTRL_COUNTER_CONV_SHIFT               0
2617
2618 /* Bit definitions for GPADC_STATUS */
2619 #define PALMAS_GPADC_STATUS_GPADC_AVAILABLE                     0x10
2620 #define PALMAS_GPADC_STATUS_GPADC_AVAILABLE_SHIFT               4
2621
2622 /* Bit definitions for GPADC_RT_SELECT */
2623 #define PALMAS_GPADC_RT_SELECT_RT_CONV_EN                       0x80
2624 #define PALMAS_GPADC_RT_SELECT_RT_CONV_EN_SHIFT                 7
2625 #define PALMAS_GPADC_RT_SELECT_RT_CONV0_SEL_MASK                0x0f
2626 #define PALMAS_GPADC_RT_SELECT_RT_CONV0_SEL_SHIFT               0
2627
2628 /* Bit definitions for GPADC_RT_CONV0_LSB */
2629 #define PALMAS_GPADC_RT_CONV0_LSB_RT_CONV0_LSB_MASK             0xff
2630 #define PALMAS_GPADC_RT_CONV0_LSB_RT_CONV0_LSB_SHIFT            0
2631
2632 /* Bit definitions for GPADC_RT_CONV0_MSB */
2633 #define PALMAS_GPADC_RT_CONV0_MSB_RT_CONV0_MSB_MASK             0x0f
2634 #define PALMAS_GPADC_RT_CONV0_MSB_RT_CONV0_MSB_SHIFT            0
2635
2636 /* Bit definitions for GPADC_AUTO_SELECT */
2637 #define PALMAS_GPADC_AUTO_SELECT_AUTO_CONV1_SEL_MASK            0xf0
2638 #define PALMAS_GPADC_AUTO_SELECT_AUTO_CONV1_SEL_SHIFT           4
2639 #define PALMAS_GPADC_AUTO_SELECT_AUTO_CONV0_SEL_MASK            0x0f
2640 #define PALMAS_GPADC_AUTO_SELECT_AUTO_CONV0_SEL_SHIFT           0
2641
2642 /* Bit definitions for GPADC_AUTO_CONV0_LSB */
2643 #define PALMAS_GPADC_AUTO_CONV0_LSB_AUTO_CONV0_LSB_MASK         0xff
2644 #define PALMAS_GPADC_AUTO_CONV0_LSB_AUTO_CONV0_LSB_SHIFT        0
2645
2646 /* Bit definitions for GPADC_AUTO_CONV0_MSB */
2647 #define PALMAS_GPADC_AUTO_CONV0_MSB_AUTO_CONV0_MSB_MASK         0x0f
2648 #define PALMAS_GPADC_AUTO_CONV0_MSB_AUTO_CONV0_MSB_SHIFT        0
2649
2650 /* Bit definitions for GPADC_AUTO_CONV1_LSB */
2651 #define PALMAS_GPADC_AUTO_CONV1_LSB_AUTO_CONV1_LSB_MASK         0xff
2652 #define PALMAS_GPADC_AUTO_CONV1_LSB_AUTO_CONV1_LSB_SHIFT        0
2653
2654 /* Bit definitions for GPADC_AUTO_CONV1_MSB */
2655 #define PALMAS_GPADC_AUTO_CONV1_MSB_AUTO_CONV1_MSB_MASK         0x0f
2656 #define PALMAS_GPADC_AUTO_CONV1_MSB_AUTO_CONV1_MSB_SHIFT        0
2657
2658 /* Bit definitions for GPADC_SW_SELECT */
2659 #define PALMAS_GPADC_SW_SELECT_SW_CONV_EN                       0x80
2660 #define PALMAS_GPADC_SW_SELECT_SW_CONV_EN_SHIFT                 7
2661 #define PALMAS_GPADC_SW_SELECT_SW_START_CONV0                   0x10
2662 #define PALMAS_GPADC_SW_SELECT_SW_START_CONV0_SHIFT             4
2663 #define PALMAS_GPADC_SW_SELECT_SW_CONV0_SEL_MASK                0x0f
2664 #define PALMAS_GPADC_SW_SELECT_SW_CONV0_SEL_SHIFT               0
2665
2666 /* Bit definitions for GPADC_SW_CONV0_LSB */
2667 #define PALMAS_GPADC_SW_CONV0_LSB_SW_CONV0_LSB_MASK             0xff
2668 #define PALMAS_GPADC_SW_CONV0_LSB_SW_CONV0_LSB_SHIFT            0
2669
2670 /* Bit definitions for GPADC_SW_CONV0_MSB */
2671 #define PALMAS_GPADC_SW_CONV0_MSB_SW_CONV0_MSB_MASK             0x0f
2672 #define PALMAS_GPADC_SW_CONV0_MSB_SW_CONV0_MSB_SHIFT            0
2673
2674 /* Bit definitions for GPADC_THRES_CONV0_LSB */
2675 #define PALMAS_GPADC_THRES_CONV0_LSB_THRES_CONV0_LSB_MASK       0xff
2676 #define PALMAS_GPADC_THRES_CONV0_LSB_THRES_CONV0_LSB_SHIFT      0
2677
2678 /* Bit definitions for GPADC_THRES_CONV0_MSB */
2679 #define PALMAS_GPADC_THRES_CONV0_MSB_THRES_CONV0_POL            0x80
2680 #define PALMAS_GPADC_THRES_CONV0_MSB_THRES_CONV0_POL_SHIFT      7
2681 #define PALMAS_GPADC_THRES_CONV0_MSB_THRES_CONV0_MSB_MASK       0x0f
2682 #define PALMAS_GPADC_THRES_CONV0_MSB_THRES_CONV0_MSB_SHIFT      0
2683
2684 /* Bit definitions for GPADC_THRES_CONV1_LSB */
2685 #define PALMAS_GPADC_THRES_CONV1_LSB_THRES_CONV1_LSB_MASK       0xff
2686 #define PALMAS_GPADC_THRES_CONV1_LSB_THRES_CONV1_LSB_SHIFT      0
2687
2688 /* Bit definitions for GPADC_THRES_CONV1_MSB */
2689 #define PALMAS_GPADC_THRES_CONV1_MSB_THRES_CONV1_POL            0x80
2690 #define PALMAS_GPADC_THRES_CONV1_MSB_THRES_CONV1_POL_SHIFT      7
2691 #define PALMAS_GPADC_THRES_CONV1_MSB_THRES_CONV1_MSB_MASK       0x0f
2692 #define PALMAS_GPADC_THRES_CONV1_MSB_THRES_CONV1_MSB_SHIFT      0
2693
2694 /* Bit definitions for GPADC_SMPS_ILMONITOR_EN */
2695 #define PALMAS_GPADC_SMPS_ILMONITOR_EN_SMPS_ILMON_EN            0x20
2696 #define PALMAS_GPADC_SMPS_ILMONITOR_EN_SMPS_ILMON_EN_SHIFT      5
2697 #define PALMAS_GPADC_SMPS_ILMONITOR_EN_SMPS_ILMON_REXT          0x10
2698 #define PALMAS_GPADC_SMPS_ILMONITOR_EN_SMPS_ILMON_REXT_SHIFT    4
2699 #define PALMAS_GPADC_SMPS_ILMONITOR_EN_SMPS_ILMON_SEL_MASK      0x0f
2700 #define PALMAS_GPADC_SMPS_ILMONITOR_EN_SMPS_ILMON_SEL_SHIFT     0
2701
2702 /* Bit definitions for GPADC_SMPS_VSEL_MONITORING */
2703 #define PALMAS_GPADC_SMPS_VSEL_MONITORING_ACTIVE_PHASE          0x80
2704 #define PALMAS_GPADC_SMPS_VSEL_MONITORING_ACTIVE_PHASE_SHIFT    7
2705 #define PALMAS_GPADC_SMPS_VSEL_MONITORING_SMPS_VSEL_MONITORING_MASK     0x7f
2706 #define PALMAS_GPADC_SMPS_VSEL_MONITORING_SMPS_VSEL_MONITORING_SHIFT    0
2707
2708 #define PALMAS_INTERNAL_DESIGNREV                               0x57
2709 #define PALMAS_INTERNAL_DESIGNREV_DESIGNREV(val)                ((val) & 0xF)
2710
2711 /* Registers for function GPADC */
2712 #define PALMAS_GPADC_TRIM1                                      0x0
2713 #define PALMAS_GPADC_TRIM2                                      0x1
2714 #define PALMAS_GPADC_TRIM3                                      0x2
2715 #define PALMAS_GPADC_TRIM4                                      0x3
2716 #define PALMAS_GPADC_TRIM5                                      0x4
2717 #define PALMAS_GPADC_TRIM6                                      0x5
2718 #define PALMAS_GPADC_TRIM7                                      0x6
2719 #define PALMAS_GPADC_TRIM8                                      0x7
2720 #define PALMAS_GPADC_TRIM9                                      0x8
2721 #define PALMAS_GPADC_TRIM10                                     0x9
2722 #define PALMAS_GPADC_TRIM11                                     0xA
2723 #define PALMAS_GPADC_TRIM12                                     0xB
2724 #define PALMAS_GPADC_TRIM13                                     0xC
2725 #define PALMAS_GPADC_TRIM14                                     0xD
2726 #define PALMAS_GPADC_TRIM15                                     0xE
2727 #define PALMAS_GPADC_TRIM16                                     0xF
2728 #define PALMAS_GPADC_TRIMINVALID                                -1
2729
2730 enum {
2731         PALMAS_EXT_CONTROL_ENABLE1      = 0x1,
2732         PALMAS_EXT_CONTROL_ENABLE2      = 0x2,
2733         PALMAS_EXT_CONTROL_NSLEEP       = 0x4,
2734 };
2735
2736 /*
2737  *PALMAS GPIOs
2738  */
2739 enum {
2740         PALMAS_GPIO0,
2741         PALMAS_GPIO1,
2742         PALMAS_GPIO2,
2743         PALMAS_GPIO3,
2744         PALMAS_GPIO4,
2745         PALMAS_GPIO5,
2746         PALMAS_GPIO6,
2747         PALMAS_GPIO7,
2748
2749         PALMAS_GPIO_NR,
2750 };
2751
2752 /* Palma GPADC Channels */
2753 enum {
2754         PALMAS_ADC_CH_IN0,
2755         PALMAS_ADC_CH_IN1,
2756         PALMAS_ADC_CH_IN2,
2757         PALMAS_ADC_CH_IN3,
2758         PALMAS_ADC_CH_IN4,
2759         PALMAS_ADC_CH_IN5,
2760         PALMAS_ADC_CH_IN6,
2761         PALMAS_ADC_CH_IN7,
2762         PALMAS_ADC_CH_IN8,
2763         PALMAS_ADC_CH_IN9,
2764         PALMAS_ADC_CH_IN10,
2765         PALMAS_ADC_CH_IN11,
2766         PALMAS_ADC_CH_IN12,
2767         PALMAS_ADC_CH_IN13,
2768         PALMAS_ADC_CH_IN14,
2769         PALMAS_ADC_CH_IN15,
2770
2771         PALMAS_ADC_CH_MAX,
2772 };
2773
2774 /* Palma Sleep requestor IDs IDs */
2775 enum {
2776         PALMAS_SLEEP_REQSTR_ID_REGEN1,
2777         PALMAS_SLEEP_REQSTR_ID_REGEN2,
2778         PALMAS_SLEEP_REQSTR_ID_SYSEN1,
2779         PALMAS_SLEEP_REQSTR_ID_SYSEN2,
2780         PALMAS_SLEEP_REQSTR_ID_CLK32KG,
2781         PALMAS_SLEEP_REQSTR_ID_CLK32KGAUDIO,
2782         PALMAS_SLEEP_REQSTR_ID_REGEN3,
2783         PALMAS_SLEEP_REQSTR_ID_SMPS12,
2784         PALMAS_SLEEP_REQSTR_ID_SMPS3,
2785         PALMAS_SLEEP_REQSTR_ID_SMPS45,
2786         PALMAS_SLEEP_REQSTR_ID_SMPS6,
2787         PALMAS_SLEEP_REQSTR_ID_SMPS7,
2788         PALMAS_SLEEP_REQSTR_ID_SMPS8,
2789         PALMAS_SLEEP_REQSTR_ID_SMPS9,
2790         PALMAS_SLEEP_REQSTR_ID_SMPS10,
2791         PALMAS_SLEEP_REQSTR_ID_LDO1,
2792         PALMAS_SLEEP_REQSTR_ID_LDO2,
2793         PALMAS_SLEEP_REQSTR_ID_LDO3,
2794         PALMAS_SLEEP_REQSTR_ID_LDO4,
2795         PALMAS_SLEEP_REQSTR_ID_LDO5,
2796         PALMAS_SLEEP_REQSTR_ID_LDO6,
2797         PALMAS_SLEEP_REQSTR_ID_LDO7,
2798         PALMAS_SLEEP_REQSTR_ID_LDO8,
2799         PALMAS_SLEEP_REQSTR_ID_LDO9,
2800         PALMAS_SLEEP_REQSTR_ID_LDOLN,
2801         PALMAS_SLEEP_REQSTR_ID_LDOUSB,
2802
2803         /* Last entry */
2804         PALMAS_SLEEP_REQSTR_ID_MAX,
2805 };
2806
2807 /* Palmas Pinmux option */
2808 enum {
2809         PALMAS_PINMUX_GPIO = 0,
2810         PALMAS_PINMUX_LED,
2811         PALMAS_PINMUX_PWM,
2812         PALMAS_PINMUX_REGEN,
2813         PALMAS_PINMUX_SYSEN,
2814         PALMAS_PINMUX_CLK32KGAUDIO,
2815         PALMAS_PINMUX_ID,
2816         PALMAS_PINMUX_VBUS_DET,
2817         PALMAS_PINMUX_CHRG_DET,
2818         PALMAS_PINMUX_VAC,
2819         PALMAS_PINMUX_VACOK,
2820         PALMAS_PINMUX_POWERGOOD,
2821         PALMAS_PINMUX_USB_PSEL,
2822         PALMAS_PINMUX_MSECURE,
2823         PALMAS_PINMUX_PWRHOLD,
2824         PALMAS_PINMUX_INT,
2825         PALMAS_PINMUX_DVFS2,
2826         PALMAS_PINMUX_DVFS1,
2827         PALMAS_PINMUX_NRESWARM,
2828         PALMAS_PINMUX_PWRDOWN,
2829         PALMAS_PINMUX_GPADC_START,
2830         PALMAS_PINMUX_RESET_IN,
2831         PALMAS_PINMUX_NSLEEP,
2832         PALMAS_PINMUX_ENABLE1,
2833         PALMAS_PINMUX_ENABLE2,
2834         PALMAS_PINMUX_RESVD = 0x2000,
2835         PALMAS_PINMUX_DEFAULT = 0x4000,
2836         PALMAS_PINMUX_INVALID = 0x8000,
2837 };
2838
2839 /* Palmas Pinmux Pullup/pulldown/opendrain configuration. */
2840 enum {
2841         PALMAS_PIN_CONFIG_DEFAULT,
2842         PALMAS_PIN_CONFIG_NORMAL,
2843         PALMAS_PIN_CONFIG_PULL_UP,
2844         PALMAS_PIN_CONFIG_PULL_DOWN,
2845
2846         PALMAS_PIN_CONFIG_OD_DEFAULT,
2847         PALMAS_PIN_CONFIG_OD_ENABLE,
2848         PALMAS_PIN_CONFIG_OD_DISABLE,
2849 };
2850
2851 /* Palmas Pins name */
2852 enum {
2853         PALMAS_PIN_NAME_GPIO0,
2854         PALMAS_PIN_NAME_GPIO1,
2855         PALMAS_PIN_NAME_GPIO2,
2856         PALMAS_PIN_NAME_GPIO3,
2857         PALMAS_PIN_NAME_GPIO4,
2858         PALMAS_PIN_NAME_GPIO5,
2859         PALMAS_PIN_NAME_GPIO6,
2860         PALMAS_PIN_NAME_GPIO7,
2861         PALMAS_PIN_NAME_VAC,
2862         PALMAS_PIN_NAME_POWERGOOD,
2863         PALMAS_PIN_NAME_NRESWARM,
2864         PALMAS_PIN_NAME_PWRDOWN,
2865         PALMAS_PIN_NAME_GPADC_START,
2866         PALMAS_PIN_NAME_RESET_IN,
2867         PALMAS_PIN_NAME_NSLEEP,
2868         PALMAS_PIN_NAME_ENABLE1,
2869         PALMAS_PIN_NAME_ENABLE2,
2870         PALMAS_PIN_NAME_INT,
2871         PALMAS_PIN_NAME_MAX,
2872 };
2873
2874 extern int palmas_ext_power_req_config(struct palmas *palmas,
2875                 int id,  int ext_pwr_ctrl, bool enable);
2876
2877 static inline int palmas_read(struct palmas *palmas, unsigned int base,
2878                 unsigned int reg, unsigned int *val)
2879 {
2880         unsigned int addr =  PALMAS_BASE_TO_REG(base, reg);
2881         int slave_id = PALMAS_BASE_TO_SLAVE(base);
2882
2883         return regmap_read(palmas->regmap[slave_id], addr, val);
2884 }
2885
2886 static inline int palmas_write(struct palmas *palmas, unsigned int base,
2887                 unsigned int reg, unsigned int value)
2888 {
2889         unsigned int addr = PALMAS_BASE_TO_REG(base, reg);
2890         int slave_id = PALMAS_BASE_TO_SLAVE(base);
2891
2892         return regmap_write(palmas->regmap[slave_id], addr, value);
2893 }
2894
2895 static inline int palmas_bulk_write(struct palmas *palmas, unsigned int base,
2896         unsigned int reg, const void *val, size_t val_count)
2897 {
2898         unsigned int addr = PALMAS_BASE_TO_REG(base, reg);
2899         int slave_id = PALMAS_BASE_TO_SLAVE(base);
2900
2901         return regmap_bulk_write(palmas->regmap[slave_id], addr,
2902                         val, val_count);
2903 }
2904
2905 static inline int palmas_bulk_read(struct palmas *palmas, unsigned int base,
2906                 unsigned int reg, void *val, size_t val_count)
2907 {
2908         unsigned int addr = PALMAS_BASE_TO_REG(base, reg);
2909         int slave_id = PALMAS_BASE_TO_SLAVE(base);
2910
2911         return regmap_bulk_read(palmas->regmap[slave_id], addr,
2912                 val, val_count);
2913 }
2914
2915 static inline int palmas_update_bits(struct palmas *palmas, unsigned int base,
2916         unsigned int reg, unsigned int mask, unsigned int val)
2917 {
2918         unsigned int addr = PALMAS_BASE_TO_REG(base, reg);
2919         int slave_id = PALMAS_BASE_TO_SLAVE(base);
2920
2921         return regmap_update_bits(palmas->regmap[slave_id], addr, mask, val);
2922 }
2923
2924 extern int palmas_irq_get_virq(struct palmas *palmas, int irq);
2925
2926 static inline int palmas_is_es_version_or_less(struct palmas *palmas,
2927         int major, int minor)
2928 {
2929         if (palmas->es_major_version < major)
2930                 return true;
2931
2932         if ((palmas->es_major_version == major) &&
2933                 (palmas->es_minor_version <= minor))
2934                 return true;
2935
2936         return false;
2937 }
2938 #endif /*  __LINUX_MFD_PALMAS_H */