Don't include linux/config.h from anywhere else in include/
[linux-2.6.git] / include / linux / cobalt-nvram.h
1 /*
2  * $Id: cobalt-nvram.h,v 1.20 2001/10/17 23:16:55 thockin Exp $
3  * cobalt-nvram.h : defines for the various fields in the cobalt NVRAM
4  *
5  * Copyright 2001,2002 Sun Microsystems, Inc.
6  */
7
8 #ifndef COBALT_NVRAM_H
9 #define COBALT_NVRAM_H
10
11 #include <linux/nvram.h>
12
13 #define COBT_CMOS_INFO_MAX              0x7f    /* top address allowed */
14 #define COBT_CMOS_BIOS_DRIVE_INFO       0x12    /* drive info would go here */
15
16 #define COBT_CMOS_CKS_START             NVRAM_OFFSET(0x0e)
17 #define COBT_CMOS_CKS_END               NVRAM_OFFSET(0x7f)
18
19 /* flag bytes - 16 flags for now, leave room for more */
20 #define COBT_CMOS_FLAG_BYTE_0           NVRAM_OFFSET(0x10)
21 #define COBT_CMOS_FLAG_BYTE_1           NVRAM_OFFSET(0x11)
22
23 /* flags in flag bytes - up to 16 */
24 #define COBT_CMOS_FLAG_MIN              0x0001
25 #define COBT_CMOS_CONSOLE_FLAG          0x0001 /* console on/off */
26 #define COBT_CMOS_DEBUG_FLAG            0x0002 /* ROM debug messages */
27 #define COBT_CMOS_AUTO_PROMPT_FLAG      0x0004 /* boot to ROM prompt? */
28 #define COBT_CMOS_CLEAN_BOOT_FLAG       0x0008 /* set by a clean shutdown */
29 #define COBT_CMOS_HW_NOPROBE_FLAG       0x0010 /* go easy on the probing */
30 #define COBT_CMOS_SYSFAULT_FLAG         0x0020 /* system fault detected */
31 #define COBT_CMOS_OOPSPANIC_FLAG        0x0040 /* panic on oops */
32 #define COBT_CMOS_DELAY_CACHE_FLAG      0x0080 /* delay cache initialization */
33 #define COBT_CMOS_NOLOGO_FLAG           0x0100 /* hide "C" logo @ boot */
34 #define COBT_CMOS_VERSION_FLAG          0x0200 /* the version field is valid */
35 #define COBT_CMOS_FLAG_MAX              0x0200
36
37 /* leave byte 0x12 blank - Linux looks for drive info here */
38
39 /* CMOS structure version, valid if COBT_CMOS_VERSION_FLAG is true */
40 #define COBT_CMOS_VERSION               NVRAM_OFFSET(0x13)
41 #define COBT_CMOS_VER_BTOCODE           1 /* min. version needed for btocode */
42
43 /* index of default boot method */
44 #define COBT_CMOS_BOOT_METHOD           NVRAM_OFFSET(0x20)
45 #define COBT_CMOS_BOOT_METHOD_DISK      0
46 #define COBT_CMOS_BOOT_METHOD_ROM       1
47 #define COBT_CMOS_BOOT_METHOD_NET       2
48
49 #define COBT_CMOS_BOOT_DEV_MIN          NVRAM_OFFSET(0x21)
50 /* major #, minor # of first through fourth boot device */
51 #define COBT_CMOS_BOOT_DEV0_MAJ         NVRAM_OFFSET(0x21)
52 #define COBT_CMOS_BOOT_DEV0_MIN         NVRAM_OFFSET(0x22)
53 #define COBT_CMOS_BOOT_DEV1_MAJ         NVRAM_OFFSET(0x23)
54 #define COBT_CMOS_BOOT_DEV1_MIN         NVRAM_OFFSET(0x24)
55 #define COBT_CMOS_BOOT_DEV2_MAJ         NVRAM_OFFSET(0x25)
56 #define COBT_CMOS_BOOT_DEV2_MIN         NVRAM_OFFSET(0x26)
57 #define COBT_CMOS_BOOT_DEV3_MAJ         NVRAM_OFFSET(0x27)
58 #define COBT_CMOS_BOOT_DEV3_MIN         NVRAM_OFFSET(0x28)
59 #define COBT_CMOS_BOOT_DEV_MAX          NVRAM_OFFSET(0x28)
60
61 /* checksum of bytes 0xe-0x7f */
62 #define COBT_CMOS_CHECKSUM              NVRAM_OFFSET(0x2e)
63
64 /* running uptime counter, units of 5 minutes (32 bits =~ 41000 years) */
65 #define COBT_CMOS_UPTIME_0              NVRAM_OFFSET(0x30)
66 #define COBT_CMOS_UPTIME_1              NVRAM_OFFSET(0x31)
67 #define COBT_CMOS_UPTIME_2              NVRAM_OFFSET(0x32)
68 #define COBT_CMOS_UPTIME_3              NVRAM_OFFSET(0x33)
69
70 /* count of successful boots (32 bits) */
71 #define COBT_CMOS_BOOTCOUNT_0           NVRAM_OFFSET(0x38)
72 #define COBT_CMOS_BOOTCOUNT_1           NVRAM_OFFSET(0x39)
73 #define COBT_CMOS_BOOTCOUNT_2           NVRAM_OFFSET(0x3a)
74 #define COBT_CMOS_BOOTCOUNT_3           NVRAM_OFFSET(0x3b)
75
76 /* 13 bytes: system serial number, same as on the back of the system */
77 #define COBT_CMOS_SYS_SERNUM_LEN        13
78 #define COBT_CMOS_SYS_SERNUM_0          NVRAM_OFFSET(0x40)
79 #define COBT_CMOS_SYS_SERNUM_1          NVRAM_OFFSET(0x41)
80 #define COBT_CMOS_SYS_SERNUM_2          NVRAM_OFFSET(0x42)
81 #define COBT_CMOS_SYS_SERNUM_3          NVRAM_OFFSET(0x43)
82 #define COBT_CMOS_SYS_SERNUM_4          NVRAM_OFFSET(0x44)
83 #define COBT_CMOS_SYS_SERNUM_5          NVRAM_OFFSET(0x45)
84 #define COBT_CMOS_SYS_SERNUM_6          NVRAM_OFFSET(0x46)
85 #define COBT_CMOS_SYS_SERNUM_7          NVRAM_OFFSET(0x47)
86 #define COBT_CMOS_SYS_SERNUM_8          NVRAM_OFFSET(0x48)
87 #define COBT_CMOS_SYS_SERNUM_9          NVRAM_OFFSET(0x49)
88 #define COBT_CMOS_SYS_SERNUM_10         NVRAM_OFFSET(0x4a)
89 #define COBT_CMOS_SYS_SERNUM_11         NVRAM_OFFSET(0x4b)
90 #define COBT_CMOS_SYS_SERNUM_12         NVRAM_OFFSET(0x4c)
91 /* checksum for serial num - 1 byte */
92 #define COBT_CMOS_SYS_SERNUM_CSUM       NVRAM_OFFSET(0x4f)
93
94 #define COBT_CMOS_ROM_REV_MAJ           NVRAM_OFFSET(0x50)
95 #define COBT_CMOS_ROM_REV_MIN           NVRAM_OFFSET(0x51)
96 #define COBT_CMOS_ROM_REV_REV           NVRAM_OFFSET(0x52)
97
98 #define COBT_CMOS_BTO_CODE_0            NVRAM_OFFSET(0x53)
99 #define COBT_CMOS_BTO_CODE_1            NVRAM_OFFSET(0x54)
100 #define COBT_CMOS_BTO_CODE_2            NVRAM_OFFSET(0x55)
101 #define COBT_CMOS_BTO_CODE_3            NVRAM_OFFSET(0x56)
102
103 #define COBT_CMOS_BTO_IP_CSUM           NVRAM_OFFSET(0x57)
104 #define COBT_CMOS_BTO_IP_0              NVRAM_OFFSET(0x58)
105 #define COBT_CMOS_BTO_IP_1              NVRAM_OFFSET(0x59)
106 #define COBT_CMOS_BTO_IP_2              NVRAM_OFFSET(0x5a)
107 #define COBT_CMOS_BTO_IP_3              NVRAM_OFFSET(0x5b)
108
109 #endif /* COBALT_NVRAM_H */