Don't include linux/config.h from anywhere else in include/
[linux-2.6.git] / include / asm-ppc / gt64260_defs.h
1 /*
2  * include/asm-ppc/gt64260_defs.h
3  *
4  * Register definitions for the Marvell/Galileo GT64260 host bridge.
5  *
6  * Author: Mark A. Greer <mgreer@mvista.com>
7  *
8  * 2001 (c) MontaVista, Software, Inc.  This file is licensed under
9  * the terms of the GNU General Public License version 2.  This program
10  * is licensed "as is" without any warranty of any kind, whether express
11  * or implied.
12  */
13 #ifndef __ASMPPC_GT64260_DEFS_H
14 #define __ASMPPC_GT64260_DEFS_H
15
16 /*
17  * Define a macro to represent the supported version of the 64260.
18  */
19 #define GT64260                 0x01
20 #define GT64260A                0x10
21
22 /*
23  *****************************************************************************
24  *
25  *      CPU Interface Registers
26  *
27  *****************************************************************************
28  */
29
30 /* CPU physical address of 64260's registers */
31 #define GT64260_INTERNAL_SPACE_DECODE                   0x0068
32 #define GT64260_INTERNAL_SPACE_SIZE                     0x10000
33 #define GT64260_INTERNAL_SPACE_DEFAULT_ADDR             0x14000000
34
35 /* CPU Memory Controller Window Registers (4 windows) */
36 #define GT64260_CPU_SCS_DECODE_WINDOWS                  4
37
38 #define GT64260_CPU_SCS_DECODE_0_BOT                    0x0008
39 #define GT64260_CPU_SCS_DECODE_0_TOP                    0x0010
40 #define GT64260_CPU_SCS_DECODE_1_BOT                    0x0208
41 #define GT64260_CPU_SCS_DECODE_1_TOP                    0x0210
42 #define GT64260_CPU_SCS_DECODE_2_BOT                    0x0018
43 #define GT64260_CPU_SCS_DECODE_2_TOP                    0x0020
44 #define GT64260_CPU_SCS_DECODE_3_BOT                    0x0218
45 #define GT64260_CPU_SCS_DECODE_3_TOP                    0x0220
46
47 /* CPU Device Controller Window Registers (4 windows) */
48 #define GT64260_CPU_CS_DECODE_WINDOWS                   4
49
50 #define GT64260_CPU_CS_DECODE_0_BOT                     0x0028
51 #define GT64260_CPU_CS_DECODE_0_TOP                     0x0030
52 #define GT64260_CPU_CS_DECODE_1_BOT                     0x0228
53 #define GT64260_CPU_CS_DECODE_1_TOP                     0x0230
54 #define GT64260_CPU_CS_DECODE_2_BOT                     0x0248
55 #define GT64260_CPU_CS_DECODE_2_TOP                     0x0250
56 #define GT64260_CPU_CS_DECODE_3_BOT                     0x0038
57 #define GT64260_CPU_CS_DECODE_3_TOP                     0x0040
58
59 #define GT64260_CPU_BOOT_CS_DECODE_0_BOT                0x0238
60 #define GT64260_CPU_BOOT_CS_DECODE_0_TOP                0x0240
61
62 /* CPU Windows to PCI space (2 PCI buses each w/ 1 I/O & 4 MEM windows) */
63 #define GT64260_PCI_BUSES                               2
64 #define GT64260_PCI_IO_WINDOWS_PER_BUS                  1
65 #define GT64260_PCI_MEM_WINDOWS_PER_BUS                 4
66
67 #define GT64260_CPU_PCI_SWAP_BYTE                       0x00000000
68 #define GT64260_CPU_PCI_SWAP_NONE                       0x01000000
69 #define GT64260_CPU_PCI_SWAP_BYTE_WORD                  0x02000000
70 #define GT64260_CPU_PCI_SWAP_WORD                       0x03000000
71 #define GT64260_CPU_PCI_SWAP_MASK                       0x07000000
72
73 #define GT64260_CPU_PCI_MEM_REQ64                       (1<<27)
74
75 #define GT64260_CPU_PCI_0_IO_DECODE_BOT                 0x0048
76 #define GT64260_CPU_PCI_0_IO_DECODE_TOP                 0x0050
77 #define GT64260_CPU_PCI_0_MEM_0_DECODE_BOT              0x0058
78 #define GT64260_CPU_PCI_0_MEM_0_DECODE_TOP              0x0060
79 #define GT64260_CPU_PCI_0_MEM_1_DECODE_BOT              0x0080
80 #define GT64260_CPU_PCI_0_MEM_1_DECODE_TOP              0x0088
81 #define GT64260_CPU_PCI_0_MEM_2_DECODE_BOT              0x0258
82 #define GT64260_CPU_PCI_0_MEM_2_DECODE_TOP              0x0260
83 #define GT64260_CPU_PCI_0_MEM_3_DECODE_BOT              0x0280
84 #define GT64260_CPU_PCI_0_MEM_3_DECODE_TOP              0x0288
85
86 #define GT64260_CPU_PCI_0_IO_REMAP                      0x00f0
87 #define GT64260_CPU_PCI_0_MEM_0_REMAP_LO                0x00f8
88 #define GT64260_CPU_PCI_0_MEM_0_REMAP_HI                0x0320
89 #define GT64260_CPU_PCI_0_MEM_1_REMAP_LO                0x0100
90 #define GT64260_CPU_PCI_0_MEM_1_REMAP_HI                0x0328
91 #define GT64260_CPU_PCI_0_MEM_2_REMAP_LO                0x02f8
92 #define GT64260_CPU_PCI_0_MEM_2_REMAP_HI                0x0330
93 #define GT64260_CPU_PCI_0_MEM_3_REMAP_LO                0x0300
94 #define GT64260_CPU_PCI_0_MEM_3_REMAP_HI                0x0338
95
96 #define GT64260_CPU_PCI_1_IO_DECODE_BOT                 0x0090
97 #define GT64260_CPU_PCI_1_IO_DECODE_TOP                 0x0098
98 #define GT64260_CPU_PCI_1_MEM_0_DECODE_BOT              0x00a0
99 #define GT64260_CPU_PCI_1_MEM_0_DECODE_TOP              0x00a8
100 #define GT64260_CPU_PCI_1_MEM_1_DECODE_BOT              0x00b0
101 #define GT64260_CPU_PCI_1_MEM_1_DECODE_TOP              0x00b8
102 #define GT64260_CPU_PCI_1_MEM_2_DECODE_BOT              0x02a0
103 #define GT64260_CPU_PCI_1_MEM_2_DECODE_TOP              0x02a8
104 #define GT64260_CPU_PCI_1_MEM_3_DECODE_BOT              0x02b0
105 #define GT64260_CPU_PCI_1_MEM_3_DECODE_TOP              0x02b8
106
107 #define GT64260_CPU_PCI_1_IO_REMAP                      0x0108
108 #define GT64260_CPU_PCI_1_MEM_0_REMAP_LO                0x0110
109 #define GT64260_CPU_PCI_1_MEM_0_REMAP_HI                0x0340
110 #define GT64260_CPU_PCI_1_MEM_1_REMAP_LO                0x0118
111 #define GT64260_CPU_PCI_1_MEM_1_REMAP_HI                0x0348
112 #define GT64260_CPU_PCI_1_MEM_2_REMAP_LO                0x0310
113 #define GT64260_CPU_PCI_1_MEM_2_REMAP_HI                0x0350
114 #define GT64260_CPU_PCI_1_MEM_3_REMAP_LO                0x0318
115 #define GT64260_CPU_PCI_1_MEM_3_REMAP_HI                0x0358
116
117 /* CPU Control Registers */
118 #define GT64260_CPU_CONFIG                              0x0000
119 #define GT64260_CPU_MODE                                0x0120
120 #define GT64260_CPU_MASTER_CNTL                         0x0160
121 #define GT64260_CPU_XBAR_CNTL_LO                        0x0150
122 #define GT64260_CPU_XBAR_CNTL_HI                        0x0158
123 #define GT64260_CPU_XBAR_TO                             0x0168
124 #define GT64260_CPU_RR_XBAR_CNTL_LO                     0x0170
125 #define GT64260_CPU_RR_XBAR_CNTL_HI                     0x0178
126
127 /* CPU Sync Barrier Registers */
128 #define GT64260_CPU_SYNC_BARRIER_PCI_0                  0x00c0
129 #define GT64260_CPU_SYNC_BARRIER_PCI_1                  0x00c8
130
131 /* CPU Access Protection Registers */
132 #define GT64260_CPU_PROT_WINDOWS                        8
133
134 #define GT64260_CPU_PROT_ACCPROTECT                     (1<<16)
135 #define GT64260_CPU_PROT_WRPROTECT                      (1<<17)
136 #define GT64260_CPU_PROT_CACHEPROTECT                   (1<<18)
137
138 #define GT64260_CPU_PROT_BASE_0                         0x0180
139 #define GT64260_CPU_PROT_TOP_0                          0x0188
140 #define GT64260_CPU_PROT_BASE_1                         0x0190
141 #define GT64260_CPU_PROT_TOP_1                          0x0198
142 #define GT64260_CPU_PROT_BASE_2                         0x01a0
143 #define GT64260_CPU_PROT_TOP_2                          0x01a8
144 #define GT64260_CPU_PROT_BASE_3                         0x01b0
145 #define GT64260_CPU_PROT_TOP_3                          0x01b8
146 #define GT64260_CPU_PROT_BASE_4                         0x01c0
147 #define GT64260_CPU_PROT_TOP_4                          0x01c8
148 #define GT64260_CPU_PROT_BASE_5                         0x01d0
149 #define GT64260_CPU_PROT_TOP_5                          0x01d8
150 #define GT64260_CPU_PROT_BASE_6                         0x01e0
151 #define GT64260_CPU_PROT_TOP_6                          0x01e8
152 #define GT64260_CPU_PROT_BASE_7                         0x01f0
153 #define GT64260_CPU_PROT_TOP_7                          0x01f8
154
155 /* CPU Snoop Control Registers */
156 #define GT64260_CPU_SNOOP_WINDOWS                       4
157
158 #define GT64260_CPU_SNOOP_NONE                          0x00000000
159 #define GT64260_CPU_SNOOP_WT                            0x00010000
160 #define GT64260_CPU_SNOOP_WB                            0x00020000
161 #define GT64260_CPU_SNOOP_MASK                          0x00030000
162 #define GT64260_CPU_SNOOP_ALL_BITS                      GT64260_CPU_SNOOP_MASK
163
164 #define GT64260_CPU_SNOOP_BASE_0                        0x0380
165 #define GT64260_CPU_SNOOP_TOP_0                         0x0388
166 #define GT64260_CPU_SNOOP_BASE_1                        0x0390
167 #define GT64260_CPU_SNOOP_TOP_1                         0x0398
168 #define GT64260_CPU_SNOOP_BASE_2                        0x03a0
169 #define GT64260_CPU_SNOOP_TOP_2                         0x03a8
170 #define GT64260_CPU_SNOOP_BASE_3                        0x03b0
171 #define GT64260_CPU_SNOOP_TOP_3                         0x03b8
172
173 /* CPU Error Report Registers */
174 #define GT64260_CPU_ERR_ADDR_LO                         0x0070
175 #define GT64260_CPU_ERR_ADDR_HI                         0x0078
176 #define GT64260_CPU_ERR_DATA_LO                         0x0128
177 #define GT64260_CPU_ERR_DATA_HI                         0x0130
178 #define GT64260_CPU_ERR_PARITY                          0x0138
179 #define GT64260_CPU_ERR_CAUSE                           0x0140
180 #define GT64260_CPU_ERR_MASK                            0x0148
181
182
183 /*
184  *****************************************************************************
185  *
186  *      SDRAM Cotnroller Registers
187  *
188  *****************************************************************************
189  */
190
191 /* SDRAM Config Registers */
192 #define GT64260_SDRAM_CONFIG                            0x0448
193 #define GT64260_SDRAM_OPERATION_MODE                    0x0474
194 #define GT64260_SDRAM_ADDR_CNTL                         0x047c
195 #define GT64260_SDRAM_TIMING_PARAMS                     0x04b4
196 #define GT64260_SDRAM_UMA_CNTL                          0x04a4
197 #define GT64260_SDRAM_XBAR_CNTL_LO                      0x04a8
198 #define GT64260_SDRAM_XBAR_CNTL_HI                      0x04ac
199 #define GT64260_SDRAM_XBAR_CNTL_TO                      0x04b0
200
201 /* SDRAM Banks Parameters Registers */
202 #define GT64260_SDRAM_BANK_PARAMS_0                     0x044c
203 #define GT64260_SDRAM_BANK_PARAMS_1                     0x0450
204 #define GT64260_SDRAM_BANK_PARAMS_2                     0x0454
205 #define GT64260_SDRAM_BANK_PARAMS_3                     0x0458
206
207 /* SDRAM Error Report Registers */
208 #define GT64260_SDRAM_ERR_DATA_LO                       0x0484
209 #define GT64260_SDRAM_ERR_DATA_HI                       0x0480
210 #define GT64260_SDRAM_ERR_ADDR                          0x0490
211 #define GT64260_SDRAM_ERR_ECC_RCVD                      0x0488
212 #define GT64260_SDRAM_ERR_ECC_CALC                      0x048c
213 #define GT64260_SDRAM_ERR_ECC_CNTL                      0x0494
214 #define GT64260_SDRAM_ERR_ECC_ERR_CNT                   0x0498
215
216
217 /*
218  *****************************************************************************
219  *
220  *      Device/BOOT Cotnroller Registers
221  *
222  *****************************************************************************
223  */
224
225 /* Device Control Registers */
226 #define GT64260_DEV_BANK_PARAMS_0                       0x045c
227 #define GT64260_DEV_BANK_PARAMS_1                       0x0460
228 #define GT64260_DEV_BANK_PARAMS_2                       0x0464
229 #define GT64260_DEV_BANK_PARAMS_3                       0x0468
230 #define GT64260_DEV_BOOT_PARAMS                         0x046c
231 #define GT64260_DEV_IF_CNTL                             0x04c0
232 #define GT64260_DEV_IF_XBAR_CNTL_LO                     0x04c8
233 #define GT64260_DEV_IF_XBAR_CNTL_HI                     0x04cc
234 #define GT64260_DEV_IF_XBAR_CNTL_TO                     0x04c4
235
236 /* Device Interrupt Registers */
237 #define GT64260_DEV_INTR_CAUSE                          0x04d0
238 #define GT64260_DEV_INTR_MASK                           0x04d4
239 #define GT64260_DEV_INTR_ERR_ADDR                       0x04d8
240
241
242 /*
243  *****************************************************************************
244  *
245  *      PCI Bridge Interface Registers
246  *
247  *****************************************************************************
248  */
249
250 /* PCI Configuration Access Registers */
251 #define GT64260_PCI_0_CONFIG_ADDR                       0x0cf8
252 #define GT64260_PCI_0_CONFIG_DATA                       0x0cfc
253 #define GT64260_PCI_0_IACK                              0x0c34
254
255 #define GT64260_PCI_1_CONFIG_ADDR                       0x0c78
256 #define GT64260_PCI_1_CONFIG_DATA                       0x0c7c
257 #define GT64260_PCI_1_IACK                              0x0cb4
258
259 /* PCI Control Registers */
260 #define GT64260_PCI_0_CMD                               0x0c00
261 #define GT64260_PCI_0_MODE                              0x0d00
262 #define GT64260_PCI_0_TO_RETRY                          0x0c04
263 #define GT64260_PCI_0_RD_BUF_DISCARD_TIMER              0x0d04
264 #define GT64260_PCI_0_MSI_TRIGGER_TIMER                 0x0c38
265 #define GT64260_PCI_0_ARBITER_CNTL                      0x1d00
266 #define GT64260_PCI_0_XBAR_CNTL_LO                      0x1d08
267 #define GT64260_PCI_0_XBAR_CNTL_HI                      0x1d0c
268 #define GT64260_PCI_0_XBAR_CNTL_TO                      0x1d04
269 #define GT64260_PCI_0_RD_RESP_XBAR_CNTL_LO              0x1d18
270 #define GT64260_PCI_0_RD_RESP_XBAR_CNTL_HI              0x1d1c
271 #define GT64260_PCI_0_SYNC_BARRIER                      0x1d10
272 #define GT64260_PCI_0_P2P_CONFIG                        0x1d14
273 #define GT64260_PCI_0_P2P_SWAP_CNTL                     0x1d54
274
275 #define GT64260_PCI_1_CMD                               0x0c80
276 #define GT64260_PCI_1_MODE                              0x0d80
277 #define GT64260_PCI_1_TO_RETRY                          0x0c84
278 #define GT64260_PCI_1_RD_BUF_DISCARD_TIMER              0x0d84
279 #define GT64260_PCI_1_MSI_TRIGGER_TIMER                 0x0cb8
280 #define GT64260_PCI_1_ARBITER_CNTL                      0x1d80
281 #define GT64260_PCI_1_XBAR_CNTL_LO                      0x1d88
282 #define GT64260_PCI_1_XBAR_CNTL_HI                      0x1d8c
283 #define GT64260_PCI_1_XBAR_CNTL_TO                      0x1d84
284 #define GT64260_PCI_1_RD_RESP_XBAR_CNTL_LO              0x1d98
285 #define GT64260_PCI_1_RD_RESP_XBAR_CNTL_HI              0x1d9c
286 #define GT64260_PCI_1_SYNC_BARRIER                      0x1d90
287 #define GT64260_PCI_1_P2P_CONFIG                        0x1d94
288 #define GT64260_PCI_1_P2P_SWAP_CNTL                     0x1dd4
289
290 /* PCI Access Control Regions Registers */
291 #define GT64260_PCI_ACC_CNTL_WINDOWS                    8
292
293 #define GT64260_PCI_ACC_CNTL_PREFETCHEN                 (1<<12)
294 #define GT64260_PCI_ACC_CNTL_DREADEN                    (1<<13)
295 #define GT64260_PCI_ACC_CNTL_RDPREFETCH                 (1<<16)
296 #define GT64260_PCI_ACC_CNTL_RDLINEPREFETCH             (1<<17)
297 #define GT64260_PCI_ACC_CNTL_RDMULPREFETCH              (1<<18)
298 #define GT64260_PCI_ACC_CNTL_MBURST_4_WORDS             0x00000000
299 #define GT64260_PCI_ACC_CNTL_MBURST_8_WORDS             0x00100000
300 #define GT64260_PCI_ACC_CNTL_MBURST_16_WORDS            0x00200000
301 #define GT64260_PCI_ACC_CNTL_MBURST_MASK                0x00300000
302 #define GT64260_PCI_ACC_CNTL_SWAP_BYTE                  0x00000000
303 #define GT64260_PCI_ACC_CNTL_SWAP_NONE                  0x01000000
304 #define GT64260_PCI_ACC_CNTL_SWAP_BYTE_WORD             0x02000000
305 #define GT64260_PCI_ACC_CNTL_SWAP_WORD                  0x03000000
306 #define GT64260_PCI_ACC_CNTL_SWAP_MASK                  0x03000000
307 #define GT64260_PCI_ACC_CNTL_ACCPROT                    (1<<28)
308 #define GT64260_PCI_ACC_CNTL_WRPROT                     (1<<29)
309
310 #define GT64260_PCI_ACC_CNTL_ALL_BITS   (GT64260_PCI_ACC_CNTL_PREFETCHEN |    \
311                                          GT64260_PCI_ACC_CNTL_DREADEN |       \
312                                          GT64260_PCI_ACC_CNTL_RDPREFETCH |    \
313                                          GT64260_PCI_ACC_CNTL_RDLINEPREFETCH |\
314                                          GT64260_PCI_ACC_CNTL_RDMULPREFETCH | \
315                                          GT64260_PCI_ACC_CNTL_MBURST_MASK |   \
316                                          GT64260_PCI_ACC_CNTL_SWAP_MASK |     \
317                                          GT64260_PCI_ACC_CNTL_ACCPROT|        \
318                                          GT64260_PCI_ACC_CNTL_WRPROT)
319
320 #define GT64260_PCI_0_ACC_CNTL_0_BASE_LO                0x1e00
321 #define GT64260_PCI_0_ACC_CNTL_0_BASE_HI                0x1e04
322 #define GT64260_PCI_0_ACC_CNTL_0_TOP                    0x1e08
323 #define GT64260_PCI_0_ACC_CNTL_1_BASE_LO                0x1e10
324 #define GT64260_PCI_0_ACC_CNTL_1_BASE_HI                0x1e14
325 #define GT64260_PCI_0_ACC_CNTL_1_TOP                    0x1e18
326 #define GT64260_PCI_0_ACC_CNTL_2_BASE_LO                0x1e20
327 #define GT64260_PCI_0_ACC_CNTL_2_BASE_HI                0x1e24
328 #define GT64260_PCI_0_ACC_CNTL_2_TOP                    0x1e28
329 #define GT64260_PCI_0_ACC_CNTL_3_BASE_LO                0x1e30
330 #define GT64260_PCI_0_ACC_CNTL_3_BASE_HI                0x1e34
331 #define GT64260_PCI_0_ACC_CNTL_3_TOP                    0x1e38
332 #define GT64260_PCI_0_ACC_CNTL_4_BASE_LO                0x1e40
333 #define GT64260_PCI_0_ACC_CNTL_4_BASE_HI                0x1e44
334 #define GT64260_PCI_0_ACC_CNTL_4_TOP                    0x1e48
335 #define GT64260_PCI_0_ACC_CNTL_5_BASE_LO                0x1e50
336 #define GT64260_PCI_0_ACC_CNTL_5_BASE_HI                0x1e54
337 #define GT64260_PCI_0_ACC_CNTL_5_TOP                    0x1e58
338 #define GT64260_PCI_0_ACC_CNTL_6_BASE_LO                0x1e60
339 #define GT64260_PCI_0_ACC_CNTL_6_BASE_HI                0x1e64
340 #define GT64260_PCI_0_ACC_CNTL_6_TOP                    0x1e68
341 #define GT64260_PCI_0_ACC_CNTL_7_BASE_LO                0x1e70
342 #define GT64260_PCI_0_ACC_CNTL_7_BASE_HI                0x1e74
343 #define GT64260_PCI_0_ACC_CNTL_7_TOP                    0x1e78
344
345 #define GT64260_PCI_1_ACC_CNTL_0_BASE_LO                0x1e80
346 #define GT64260_PCI_1_ACC_CNTL_0_BASE_HI                0x1e84
347 #define GT64260_PCI_1_ACC_CNTL_0_TOP                    0x1e88
348 #define GT64260_PCI_1_ACC_CNTL_1_BASE_LO                0x1e90
349 #define GT64260_PCI_1_ACC_CNTL_1_BASE_HI                0x1e94
350 #define GT64260_PCI_1_ACC_CNTL_1_TOP                    0x1e98
351 #define GT64260_PCI_1_ACC_CNTL_2_BASE_LO                0x1ea0
352 #define GT64260_PCI_1_ACC_CNTL_2_BASE_HI                0x1ea4
353 #define GT64260_PCI_1_ACC_CNTL_2_TOP                    0x1ea8
354 #define GT64260_PCI_1_ACC_CNTL_3_BASE_LO                0x1eb0
355 #define GT64260_PCI_1_ACC_CNTL_3_BASE_HI                0x1eb4
356 #define GT64260_PCI_1_ACC_CNTL_3_TOP                    0x1eb8
357 #define GT64260_PCI_1_ACC_CNTL_4_BASE_LO                0x1ec0
358 #define GT64260_PCI_1_ACC_CNTL_4_BASE_HI                0x1ec4
359 #define GT64260_PCI_1_ACC_CNTL_4_TOP                    0x1ec8
360 #define GT64260_PCI_1_ACC_CNTL_5_BASE_LO                0x1ed0
361 #define GT64260_PCI_1_ACC_CNTL_5_BASE_HI                0x1ed4
362 #define GT64260_PCI_1_ACC_CNTL_5_TOP                    0x1ed8
363 #define GT64260_PCI_1_ACC_CNTL_6_BASE_LO                0x1ee0
364 #define GT64260_PCI_1_ACC_CNTL_6_BASE_HI                0x1ee4
365 #define GT64260_PCI_1_ACC_CNTL_6_TOP                    0x1ee8
366 #define GT64260_PCI_1_ACC_CNTL_7_BASE_LO                0x1ef0
367 #define GT64260_PCI_1_ACC_CNTL_7_BASE_HI                0x1ef4
368 #define GT64260_PCI_1_ACC_CNTL_7_TOP                    0x1ef8
369
370 /* PCI Snoop Control Registers */
371 #define GT64260_PCI_SNOOP_WINDOWS                       4
372
373 #define GT64260_PCI_SNOOP_NONE                          0x00000000
374 #define GT64260_PCI_SNOOP_WT                            0x00001000
375 #define GT64260_PCI_SNOOP_WB                            0x00002000
376
377 #define GT64260_PCI_0_SNOOP_0_BASE_LO                   0x1f00
378 #define GT64260_PCI_0_SNOOP_0_BASE_HI                   0x1f04
379 #define GT64260_PCI_0_SNOOP_0_TOP                       0x1f08
380 #define GT64260_PCI_0_SNOOP_1_BASE_LO                   0x1f10
381 #define GT64260_PCI_0_SNOOP_1_BASE_HI                   0x1f14
382 #define GT64260_PCI_0_SNOOP_1_TOP                       0x1f18
383 #define GT64260_PCI_0_SNOOP_2_BASE_LO                   0x1f20
384 #define GT64260_PCI_0_SNOOP_2_BASE_HI                   0x1f24
385 #define GT64260_PCI_0_SNOOP_2_TOP                       0x1f28
386 #define GT64260_PCI_0_SNOOP_3_BASE_LO                   0x1f30
387 #define GT64260_PCI_0_SNOOP_3_BASE_HI                   0x1f34
388 #define GT64260_PCI_0_SNOOP_3_TOP                       0x1f38
389
390 #define GT64260_PCI_1_SNOOP_0_BASE_LO                   0x1f80
391 #define GT64260_PCI_1_SNOOP_0_BASE_HI                   0x1f84
392 #define GT64260_PCI_1_SNOOP_0_TOP                       0x1f88
393 #define GT64260_PCI_1_SNOOP_1_BASE_LO                   0x1f90
394 #define GT64260_PCI_1_SNOOP_1_BASE_HI                   0x1f94
395 #define GT64260_PCI_1_SNOOP_1_TOP                       0x1f98
396 #define GT64260_PCI_1_SNOOP_2_BASE_LO                   0x1fa0
397 #define GT64260_PCI_1_SNOOP_2_BASE_HI                   0x1fa4
398 #define GT64260_PCI_1_SNOOP_2_TOP                       0x1fa8
399 #define GT64260_PCI_1_SNOOP_3_BASE_LO                   0x1fb0
400 #define GT64260_PCI_1_SNOOP_3_BASE_HI                   0x1fb4
401 #define GT64260_PCI_1_SNOOP_3_TOP                       0x1fb8
402
403 /* PCI Error Report Registers */
404 #define GT64260_PCI_0_ERR_SERR_MASK                     0x0c28
405 #define GT64260_PCI_0_ERR_ADDR_LO                       0x1d40
406 #define GT64260_PCI_0_ERR_ADDR_HI                       0x1d44
407 #define GT64260_PCI_0_ERR_DATA_LO                       0x1d48
408 #define GT64260_PCI_0_ERR_DATA_HI                       0x1d4c
409 #define GT64260_PCI_0_ERR_CMD                           0x1d50
410 #define GT64260_PCI_0_ERR_CAUSE                         0x1d58
411 #define GT64260_PCI_0_ERR_MASK                          0x1d5c
412
413 #define GT64260_PCI_1_ERR_SERR_MASK                     0x0ca8
414 #define GT64260_PCI_1_ERR_ADDR_LO                       0x1dc0
415 #define GT64260_PCI_1_ERR_ADDR_HI                       0x1dc4
416 #define GT64260_PCI_1_ERR_DATA_LO                       0x1dc8
417 #define GT64260_PCI_1_ERR_DATA_HI                       0x1dcc
418 #define GT64260_PCI_1_ERR_CMD                           0x1dd0
419 #define GT64260_PCI_1_ERR_CAUSE                         0x1dd8
420 #define GT64260_PCI_1_ERR_MASK                          0x1ddc
421
422 /* PCI Slave Address Decoding Registers */
423 #define GT64260_PCI_SCS_WINDOWS                         4
424 #define GT64260_PCI_CS_WINDOWS                          4
425 #define GT64260_PCI_BOOT_WINDOWS                        1
426 #define GT64260_PCI_P2P_MEM_WINDOWS                     2
427 #define GT64260_PCI_P2P_IO_WINDOWS                      1
428 #define GT64260_PCI_DAC_SCS_WINDOWS                     4
429 #define GT64260_PCI_DAC_CS_WINDOWS                      4
430 #define GT64260_PCI_DAC_BOOT_WINDOWS                    1
431 #define GT64260_PCI_DAC_P2P_MEM_WINDOWS                 2
432
433 #define GT64260_PCI_0_SLAVE_SCS_0_SIZE                  0x0c08
434 #define GT64260_PCI_0_SLAVE_SCS_1_SIZE                  0x0d08
435 #define GT64260_PCI_0_SLAVE_SCS_2_SIZE                  0x0c0c
436 #define GT64260_PCI_0_SLAVE_SCS_3_SIZE                  0x0d0c
437 #define GT64260_PCI_0_SLAVE_CS_0_SIZE                   0x0c10
438 #define GT64260_PCI_0_SLAVE_CS_1_SIZE                   0x0d10
439 #define GT64260_PCI_0_SLAVE_CS_2_SIZE                   0x0d18
440 #define GT64260_PCI_0_SLAVE_CS_3_SIZE                   0x0c14
441 #define GT64260_PCI_0_SLAVE_BOOT_SIZE                   0x0d14
442 #define GT64260_PCI_0_SLAVE_P2P_MEM_0_SIZE              0x0d1c
443 #define GT64260_PCI_0_SLAVE_P2P_MEM_1_SIZE              0x0d20
444 #define GT64260_PCI_0_SLAVE_P2P_IO_SIZE                 0x0d24
445 #define GT64260_PCI_0_SLAVE_CPU_SIZE                    0x0d28
446
447 #define GT64260_PCI_0_SLAVE_DAC_SCS_0_SIZE              0x0e00
448 #define GT64260_PCI_0_SLAVE_DAC_SCS_1_SIZE              0x0e04
449 #define GT64260_PCI_0_SLAVE_DAC_SCS_2_SIZE              0x0e08
450 #define GT64260_PCI_0_SLAVE_DAC_SCS_3_SIZE              0x0e0c
451 #define GT64260_PCI_0_SLAVE_DAC_CS_0_SIZE               0x0e10
452 #define GT64260_PCI_0_SLAVE_DAC_CS_1_SIZE               0x0e14
453 #define GT64260_PCI_0_SLAVE_DAC_CS_2_SIZE               0x0e18
454 #define GT64260_PCI_0_SLAVE_DAC_CS_3_SIZE               0x0e1c
455 #define GT64260_PCI_0_SLAVE_DAC_BOOT_SIZE               0x0e20
456 #define GT64260_PCI_0_SLAVE_DAC_P2P_MEM_0_SIZE          0x0e24
457 #define GT64260_PCI_0_SLAVE_DAC_P2P_MEM_1_SIZE          0x0e28
458 #define GT64260_PCI_0_SLAVE_DAC_CPU_SIZE                0x0e2c
459
460 #define GT64260_PCI_0_SLAVE_EXP_ROM_SIZE                0x0d2c
461
462 #define GT64260_PCI_SLAVE_BAR_REG_ENABLES_SCS_0         (1<<0)
463 #define GT64260_PCI_SLAVE_BAR_REG_ENABLES_SCS_1         (1<<1)
464 #define GT64260_PCI_SLAVE_BAR_REG_ENABLES_SCS_2         (1<<2)
465 #define GT64260_PCI_SLAVE_BAR_REG_ENABLES_SCS_3         (1<<3)
466 #define GT64260_PCI_SLAVE_BAR_REG_ENABLES_CS_0          (1<<4)
467 #define GT64260_PCI_SLAVE_BAR_REG_ENABLES_CS_1          (1<<5)
468 #define GT64260_PCI_SLAVE_BAR_REG_ENABLES_CS_2          (1<<6)
469 #define GT64260_PCI_SLAVE_BAR_REG_ENABLES_CS_3          (1<<7)
470 #define GT64260_PCI_SLAVE_BAR_REG_ENABLES_BOOT          (1<<8)
471 #define GT64260_PCI_SLAVE_BAR_REG_ENABLES_REG_MEM       (1<<9)
472 #define GT64260_PCI_SLAVE_BAR_REG_ENABLES_REG_IO        (1<<10)
473 #define GT64260_PCI_SLAVE_BAR_REG_ENABLES_P2P_MEM_0     (1<<11)
474 #define GT64260_PCI_SLAVE_BAR_REG_ENABLES_P2P_MEM_1     (1<<12)
475 #define GT64260_PCI_SLAVE_BAR_REG_ENABLES_P2P_IO        (1<<13)
476 #define GT64260_PCI_SLAVE_BAR_REG_ENABLES_CPU           (1<<14)
477 #define GT64260_PCI_SLAVE_BAR_REG_ENABLES_DAC_SCS_0     (1<<15)
478 #define GT64260_PCI_SLAVE_BAR_REG_ENABLES_DAC_SCS_1     (1<<16)
479 #define GT64260_PCI_SLAVE_BAR_REG_ENABLES_DAC_SCS_2     (1<<17)
480 #define GT64260_PCI_SLAVE_BAR_REG_ENABLES_DAC_SCS_3     (1<<18)
481 #define GT64260_PCI_SLAVE_BAR_REG_ENABLES_DAC_CS_0      (1<<19)
482 #define GT64260_PCI_SLAVE_BAR_REG_ENABLES_DAC_CS_1      (1<<20)
483 #define GT64260_PCI_SLAVE_BAR_REG_ENABLES_DAC_CS_2      (1<<21)
484 #define GT64260_PCI_SLAVE_BAR_REG_ENABLES_DAC_CS_3      (1<<22)
485 #define GT64260_PCI_SLAVE_BAR_REG_ENABLES_DAC_BOOT      (1<<23)
486 #define GT64260_PCI_SLAVE_BAR_REG_ENABLES_DAC_P2P_MEM_0 (1<<24)
487 #define GT64260_PCI_SLAVE_BAR_REG_ENABLES_DAC_P2P_MEM_1 (1<<25)
488 #define GT64260_PCI_SLAVE_BAR_REG_ENABLES_DAC_CPU       (1<<26)
489
490 #define GT64260_PCI_0_SLAVE_BAR_REG_ENABLES             0x0c3c
491 #define GT64260_PCI_0_SLAVE_SCS_0_REMAP                 0x0c48
492 #define GT64260_PCI_0_SLAVE_SCS_1_REMAP                 0x0d48
493 #define GT64260_PCI_0_SLAVE_SCS_2_REMAP                 0x0c4c
494 #define GT64260_PCI_0_SLAVE_SCS_3_REMAP                 0x0d4c
495 #define GT64260_PCI_0_SLAVE_CS_0_REMAP                  0x0c50
496 #define GT64260_PCI_0_SLAVE_CS_1_REMAP                  0x0d50
497 #define GT64260_PCI_0_SLAVE_CS_2_REMAP                  0x0d58
498 #define GT64260_PCI_0_SLAVE_CS_3_REMAP                  0x0c54
499 #define GT64260_PCI_0_SLAVE_BOOT_REMAP                  0x0d54
500 #define GT64260_PCI_0_SLAVE_P2P_MEM_0_REMAP_LO          0x0d5c
501 #define GT64260_PCI_0_SLAVE_P2P_MEM_0_REMAP_HI          0x0d60
502 #define GT64260_PCI_0_SLAVE_P2P_MEM_1_REMAP_LO          0x0d64
503 #define GT64260_PCI_0_SLAVE_P2P_MEM_1_REMAP_HI          0x0d68
504 #define GT64260_PCI_0_SLAVE_P2P_IO_REMAP                0x0d6c
505 #define GT64260_PCI_0_SLAVE_CPU_REMAP                   0x0d70
506
507 #define GT64260_PCI_0_SLAVE_DAC_SCS_0_REMAP             0x0f00
508 #define GT64260_PCI_0_SLAVE_DAC_SCS_1_REMAP             0x0f04
509 #define GT64260_PCI_0_SLAVE_DAC_SCS_2_REMAP             0x0f08
510 #define GT64260_PCI_0_SLAVE_DAC_SCS_3_REMAP             0x0f0c
511 #define GT64260_PCI_0_SLAVE_DAC_CS_0_REMAP              0x0f10
512 #define GT64260_PCI_0_SLAVE_DAC_CS_1_REMAP              0x0f14
513 #define GT64260_PCI_0_SLAVE_DAC_CS_2_REMAP              0x0f18
514 #define GT64260_PCI_0_SLAVE_DAC_CS_3_REMAP              0x0f1c
515 #define GT64260_PCI_0_SLAVE_DAC_BOOT_REMAP              0x0f20
516 #define GT64260_PCI_0_SLAVE_DAC_P2P_MEM_0_REMAP_LO      0x0f24
517 #define GT64260_PCI_0_SLAVE_DAC_P2P_MEM_0_REMAP_HI      0x0f28
518 #define GT64260_PCI_0_SLAVE_DAC_P2P_MEM_1_REMAP_LO      0x0f2c
519 #define GT64260_PCI_0_SLAVE_DAC_P2P_MEM_1_REMAP_HI      0x0f30
520 #define GT64260_PCI_0_SLAVE_DAC_CPU_REMAP               0x0f34
521
522 #define GT64260_PCI_0_SLAVE_EXP_ROM_REMAP               0x0f38
523 #define GT64260_PCI_0_SLAVE_PCI_DECODE_CNTL             0x0d3c
524
525 #define GT64260_PCI_1_SLAVE_SCS_0_SIZE                  0x0c88
526 #define GT64260_PCI_1_SLAVE_SCS_1_SIZE                  0x0d88
527 #define GT64260_PCI_1_SLAVE_SCS_2_SIZE                  0x0c8c
528 #define GT64260_PCI_1_SLAVE_SCS_3_SIZE                  0x0d8c
529 #define GT64260_PCI_1_SLAVE_CS_0_SIZE                   0x0c90
530 #define GT64260_PCI_1_SLAVE_CS_1_SIZE                   0x0d90
531 #define GT64260_PCI_1_SLAVE_CS_2_SIZE                   0x0d98
532 #define GT64260_PCI_1_SLAVE_CS_3_SIZE                   0x0c94
533 #define GT64260_PCI_1_SLAVE_BOOT_SIZE                   0x0d94
534 #define GT64260_PCI_1_SLAVE_P2P_MEM_0_SIZE              0x0d9c
535 #define GT64260_PCI_1_SLAVE_P2P_MEM_1_SIZE              0x0da0
536 #define GT64260_PCI_1_SLAVE_P2P_IO_SIZE                 0x0da4
537 #define GT64260_PCI_1_SLAVE_CPU_SIZE                    0x0da8
538
539 #define GT64260_PCI_1_SLAVE_DAC_SCS_0_SIZE              0x0e80
540 #define GT64260_PCI_1_SLAVE_DAC_SCS_1_SIZE              0x0e84
541 #define GT64260_PCI_1_SLAVE_DAC_SCS_2_SIZE              0x0e88
542 #define GT64260_PCI_1_SLAVE_DAC_SCS_3_SIZE              0x0e8c
543 #define GT64260_PCI_1_SLAVE_DAC_CS_0_SIZE               0x0e90
544 #define GT64260_PCI_1_SLAVE_DAC_CS_1_SIZE               0x0e94
545 #define GT64260_PCI_1_SLAVE_DAC_CS_2_SIZE               0x0e98
546 #define GT64260_PCI_1_SLAVE_DAC_CS_3_SIZE               0x0e9c
547 #define GT64260_PCI_1_SLAVE_DAC_BOOT_SIZE               0x0ea0
548 #define GT64260_PCI_1_SLAVE_DAC_P2P_MEM_0_SIZE          0x0ea4
549 #define GT64260_PCI_1_SLAVE_DAC_P2P_MEM_1_SIZE          0x0ea8
550 #define GT64260_PCI_1_SLAVE_DAC_CPU_SIZE                0x0eac
551
552 #define GT64260_PCI_1_SLAVE_EXP_ROM_SIZE                0x0dac
553
554 #define GT64260_PCI_1_SLAVE_BAR_REG_ENABLES             0x0cbc
555 #define GT64260_PCI_1_SLAVE_SCS_0_REMAP                 0x0cc8
556 #define GT64260_PCI_1_SLAVE_SCS_1_REMAP                 0x0dc8
557 #define GT64260_PCI_1_SLAVE_SCS_2_REMAP                 0x0ccc
558 #define GT64260_PCI_1_SLAVE_SCS_3_REMAP                 0x0dcc
559 #define GT64260_PCI_1_SLAVE_CS_0_REMAP                  0x0cd0
560 #define GT64260_PCI_1_SLAVE_CS_1_REMAP                  0x0dd0
561 #define GT64260_PCI_1_SLAVE_CS_2_REMAP                  0x0dd8
562 #define GT64260_PCI_1_SLAVE_CS_3_REMAP                  0x0cd4
563 #define GT64260_PCI_1_SLAVE_BOOT_REMAP                  0x0dd4
564 #define GT64260_PCI_1_SLAVE_P2P_MEM_0_REMAP_LO          0x0ddc
565 #define GT64260_PCI_1_SLAVE_P2P_MEM_0_REMAP_HI          0x0de0
566 #define GT64260_PCI_1_SLAVE_P2P_MEM_1_REMAP_LO          0x0de4
567 #define GT64260_PCI_1_SLAVE_P2P_MEM_1_REMAP_HI          0x0de8
568 #define GT64260_PCI_1_SLAVE_P2P_IO_REMAP                0x0dec
569 #define GT64260_PCI_1_SLAVE_CPU_REMAP                   0x0df0
570
571 #define GT64260_PCI_1_SLAVE_DAC_SCS_0_REMAP             0x0f80
572 #define GT64260_PCI_1_SLAVE_DAC_SCS_1_REMAP             0x0f84
573 #define GT64260_PCI_1_SLAVE_DAC_SCS_2_REMAP             0x0f88
574 #define GT64260_PCI_1_SLAVE_DAC_SCS_3_REMAP             0x0f8c
575 #define GT64260_PCI_1_SLAVE_DAC_CS_0_REMAP              0x0f90
576 #define GT64260_PCI_1_SLAVE_DAC_CS_1_REMAP              0x0f94
577 #define GT64260_PCI_1_SLAVE_DAC_CS_2_REMAP              0x0f98
578 #define GT64260_PCI_1_SLAVE_DAC_CS_3_REMAP              0x0f9c
579 #define GT64260_PCI_1_SLAVE_DAC_BOOT_REMAP              0x0fa0
580 #define GT64260_PCI_1_SLAVE_DAC_P2P_MEM_0_REMAP_LO      0x0fa4
581 #define GT64260_PCI_1_SLAVE_DAC_P2P_MEM_0_REMAP_HI      0x0fa8
582 #define GT64260_PCI_1_SLAVE_DAC_P2P_MEM_1_REMAP_LO      0x0fac
583 #define GT64260_PCI_1_SLAVE_DAC_P2P_MEM_1_REMAP_HI      0x0fb0
584 #define GT64260_PCI_1_SLAVE_DAC_CPU_REMAP               0x0fb4
585
586 #define GT64260_PCI_1_SLAVE_EXP_ROM_REMAP               0x0fb8
587 #define GT64260_PCI_1_SLAVE_PCI_DECODE_CNTL             0x0dbc
588
589
590 /*
591  *****************************************************************************
592  *
593  *      I2O Controller Interface Registers
594  *
595  *****************************************************************************
596  */
597
598 /* FIXME: fill in */
599
600
601
602 /*
603  *****************************************************************************
604  *
605  *      DMA Controller Interface Registers
606  *
607  *****************************************************************************
608  */
609
610 /* FIXME: fill in */
611
612
613 /*
614  *****************************************************************************
615  *
616  *      Timer/Counter Interface Registers
617  *
618  *****************************************************************************
619  */
620
621 /* FIXME: fill in */
622
623
624 /*
625  *****************************************************************************
626  *
627  *      Communications Controller (Enet, Serial, etc.) Interface Registers
628  *
629  *****************************************************************************
630  */
631
632 #define GT64260_ENET_0_CNTL_LO                          0xf200
633 #define GT64260_ENET_0_CNTL_HI                          0xf204
634 #define GT64260_ENET_0_RX_BUF_PCI_ADDR_HI               0xf208
635 #define GT64260_ENET_0_TX_BUF_PCI_ADDR_HI               0xf20c
636 #define GT64260_ENET_0_RX_DESC_ADDR_HI                  0xf210
637 #define GT64260_ENET_0_TX_DESC_ADDR_HI                  0xf214
638 #define GT64260_ENET_0_HASH_TAB_PCI_ADDR_HI             0xf218
639 #define GT64260_ENET_1_CNTL_LO                          0xf220
640 #define GT64260_ENET_1_CNTL_HI                          0xf224
641 #define GT64260_ENET_1_RX_BUF_PCI_ADDR_HI               0xf228
642 #define GT64260_ENET_1_TX_BUF_PCI_ADDR_HI               0xf22c
643 #define GT64260_ENET_1_RX_DESC_ADDR_HI                  0xf230
644 #define GT64260_ENET_1_TX_DESC_ADDR_HI                  0xf234
645 #define GT64260_ENET_1_HASH_TAB_PCI_ADDR_HI             0xf238
646 #define GT64260_ENET_2_CNTL_LO                          0xf240
647 #define GT64260_ENET_2_CNTL_HI                          0xf244
648 #define GT64260_ENET_2_RX_BUF_PCI_ADDR_HI               0xf248
649 #define GT64260_ENET_2_TX_BUF_PCI_ADDR_HI               0xf24c
650 #define GT64260_ENET_2_RX_DESC_ADDR_HI                  0xf250
651 #define GT64260_ENET_2_TX_DESC_ADDR_HI                  0xf254
652 #define GT64260_ENET_2_HASH_TAB_PCI_ADDR_HI             0xf258
653
654 #define GT64260_MPSC_0_CNTL_LO                          0xf280
655 #define GT64260_MPSC_0_CNTL_HI                          0xf284
656 #define GT64260_MPSC_0_RX_BUF_PCI_ADDR_HI               0xf288
657 #define GT64260_MPSC_0_TX_BUF_PCI_ADDR_HI               0xf28c
658 #define GT64260_MPSC_0_RX_DESC_ADDR_HI                  0xf290
659 #define GT64260_MPSC_0_TX_DESC_ADDR_HI                  0xf294
660 #define GT64260_MPSC_1_CNTL_LO                          0xf2c0
661 #define GT64260_MPSC_1_CNTL_HI                          0xf2c4
662 #define GT64260_MPSC_1_RX_BUF_PCI_ADDR_HI               0xf2c8
663 #define GT64260_MPSC_1_TX_BUF_PCI_ADDR_HI               0xf2cc
664 #define GT64260_MPSC_1_RX_DESC_ADDR_HI                  0xf2d0
665 #define GT64260_MPSC_1_TX_DESC_ADDR_HI                  0xf2d4
666
667 #define GT64260_SER_INIT_PCI_ADDR_HI                    0xf320
668 #define GT64260_SER_INIT_LAST_DATA                      0xf324
669 #define GT64260_SER_INIT_CONTROL                        0xf328
670 #define GT64260_SER_INIT_STATUS                         0xf32c
671
672 #define GT64260_COMM_ARBITER_CNTL                       0xf300
673 #define GT64260_COMM_CONFIG                             0xb40c
674 #define GT64260_COMM_XBAR_TO                            0xf304
675 #define GT64260_COMM_INTR_CAUSE                         0xf310
676 #define GT64260_COMM_INTR_MASK                          0xf314
677 #define GT64260_COMM_ERR_ADDR                           0xf318
678
679
680 /*
681  *****************************************************************************
682  *
683  *      Fast Ethernet Controller Interface Registers
684  *
685  *****************************************************************************
686  */
687
688 #define GT64260_ENET_PHY_ADDR                           0x2000
689 #define GT64260_ENET_ESMIR                              0x2010
690
691 #define GT64260_ENET_E0PCR                              0x2400
692 #define GT64260_ENET_E0PCXR                             0x2408
693 #define GT64260_ENET_E0PCMR                             0x2410
694 #define GT64260_ENET_E0PSR                              0x2418
695 #define GT64260_ENET_E0SPR                              0x2420
696 #define GT64260_ENET_E0HTPR                             0x2428
697 #define GT64260_ENET_E0FCSAL                            0x2430
698 #define GT64260_ENET_E0FCSAH                            0x2438
699 #define GT64260_ENET_E0SDCR                             0x2440
700 #define GT64260_ENET_E0SDCMR                            0x2448
701 #define GT64260_ENET_E0ICR                              0x2450
702 #define GT64260_ENET_E0IMR                              0x2458
703 #define GT64260_ENET_E0FRDP0                            0x2480
704 #define GT64260_ENET_E0FRDP1                            0x2484
705 #define GT64260_ENET_E0FRDP2                            0x2488
706 #define GT64260_ENET_E0FRDP3                            0x248c
707 #define GT64260_ENET_E0CRDP0                            0x24a0
708 #define GT64260_ENET_E0CRDP1                            0x24a4
709 #define GT64260_ENET_E0CRDP2                            0x24a8
710 #define GT64260_ENET_E0CRDP3                            0x24ac
711 #define GT64260_ENET_E0CTDP0                            0x24e0
712 #define GT64260_ENET_E0CTDP1                            0x24e4
713 #define GT64260_ENET_0_DSCP2P0L                         0x2460
714 #define GT64260_ENET_0_DSCP2P0H                         0x2464
715 #define GT64260_ENET_0_DSCP2P1L                         0x2468
716 #define GT64260_ENET_0_DSCP2P1H                         0x246c
717 #define GT64260_ENET_0_VPT2P                            0x2470
718 #define GT64260_ENET_0_MIB_CTRS                         0x2500
719
720 #define GT64260_ENET_E1PCR                              0x2800
721 #define GT64260_ENET_E1PCXR                             0x2808
722 #define GT64260_ENET_E1PCMR                             0x2810
723 #define GT64260_ENET_E1PSR                              0x2818
724 #define GT64260_ENET_E1SPR                              0x2820
725 #define GT64260_ENET_E1HTPR                             0x2828
726 #define GT64260_ENET_E1FCSAL                            0x2830
727 #define GT64260_ENET_E1FCSAH                            0x2838
728 #define GT64260_ENET_E1SDCR                             0x2840
729 #define GT64260_ENET_E1SDCMR                            0x2848
730 #define GT64260_ENET_E1ICR                              0x2850
731 #define GT64260_ENET_E1IMR                              0x2858
732 #define GT64260_ENET_E1FRDP0                            0x2880
733 #define GT64260_ENET_E1FRDP1                            0x2884
734 #define GT64260_ENET_E1FRDP2                            0x2888
735 #define GT64260_ENET_E1FRDP3                            0x288c
736 #define GT64260_ENET_E1CRDP0                            0x28a0
737 #define GT64260_ENET_E1CRDP1                            0x28a4
738 #define GT64260_ENET_E1CRDP2                            0x28a8
739 #define GT64260_ENET_E1CRDP3                            0x28ac
740 #define GT64260_ENET_E1CTDP0                            0x28e0
741 #define GT64260_ENET_E1CTDP1                            0x28e4
742 #define GT64260_ENET_1_DSCP2P0L                         0x2860
743 #define GT64260_ENET_1_DSCP2P0H                         0x2864
744 #define GT64260_ENET_1_DSCP2P1L                         0x2868
745 #define GT64260_ENET_1_DSCP2P1H                         0x286c
746 #define GT64260_ENET_1_VPT2P                            0x2870
747 #define GT64260_ENET_1_MIB_CTRS                         0x2900
748
749 #define GT64260_ENET_E2PCR                              0x2c00
750 #define GT64260_ENET_E2PCXR                             0x2c08
751 #define GT64260_ENET_E2PCMR                             0x2c10
752 #define GT64260_ENET_E2PSR                              0x2c18
753 #define GT64260_ENET_E2SPR                              0x2c20
754 #define GT64260_ENET_E2HTPR                             0x2c28
755 #define GT64260_ENET_E2FCSAL                            0x2c30
756 #define GT64260_ENET_E2FCSAH                            0x2c38
757 #define GT64260_ENET_E2SDCR                             0x2c40
758 #define GT64260_ENET_E2SDCMR                            0x2c48
759 #define GT64260_ENET_E2ICR                              0x2c50
760 #define GT64260_ENET_E2IMR                              0x2c58
761 #define GT64260_ENET_E2FRDP0                            0x2c80
762 #define GT64260_ENET_E2FRDP1                            0x2c84
763 #define GT64260_ENET_E2FRDP2                            0x2c88
764 #define GT64260_ENET_E2FRDP3                            0x2c8c
765 #define GT64260_ENET_E2CRDP0                            0x2ca0
766 #define GT64260_ENET_E2CRDP1                            0x2ca4
767 #define GT64260_ENET_E2CRDP2                            0x2ca8
768 #define GT64260_ENET_E2CRDP3                            0x2cac
769 #define GT64260_ENET_E2CTDP0                            0x2ce0
770 #define GT64260_ENET_E2CTDP1                            0x2ce4
771 #define GT64260_ENET_2_DSCP2P0L                         0x2c60
772 #define GT64260_ENET_2_DSCP2P0H                         0x2c64
773 #define GT64260_ENET_2_DSCP2P1L                         0x2c68
774 #define GT64260_ENET_2_DSCP2P1H                         0x2c6c
775 #define GT64260_ENET_2_VPT2P                            0x2c70
776 #define GT64260_ENET_2_MIB_CTRS                         0x2d00
777
778
779 /*
780  *****************************************************************************
781  *
782  *      Multi-Protocol Serial Controller Interface Registers
783  *
784  *****************************************************************************
785  */
786
787 /* Signal Routing */
788 #define GT64260_MPSC_MRR                                0xb400
789 #define GT64260_MPSC_RCRR                               0xb404
790 #define GT64260_MPSC_TCRR                               0xb408
791
792 /* Main Configuratino Registers */
793 #define GT64260_MPSC_0_MMCRL                            0x8000
794 #define GT64260_MPSC_0_MMCRH                            0x8004
795 #define GT64260_MPSC_0_MPCR                             0x8008
796 #define GT64260_MPSC_0_CHR_1                            0x800c
797 #define GT64260_MPSC_0_CHR_2                            0x8010
798 #define GT64260_MPSC_0_CHR_3                            0x8014
799 #define GT64260_MPSC_0_CHR_4                            0x8018
800 #define GT64260_MPSC_0_CHR_5                            0x801c
801 #define GT64260_MPSC_0_CHR_6                            0x8020
802 #define GT64260_MPSC_0_CHR_7                            0x8024
803 #define GT64260_MPSC_0_CHR_8                            0x8028
804 #define GT64260_MPSC_0_CHR_9                            0x802c
805 #define GT64260_MPSC_0_CHR_10                           0x8030
806 #define GT64260_MPSC_0_CHR_11                           0x8034
807
808 #define GT64260_MPSC_1_MMCRL                            0x9000
809 #define GT64260_MPSC_1_MMCRH                            0x9004
810 #define GT64260_MPSC_1_MPCR                             0x9008
811 #define GT64260_MPSC_1_CHR_1                            0x900c
812 #define GT64260_MPSC_1_CHR_2                            0x9010
813 #define GT64260_MPSC_1_CHR_3                            0x9014
814 #define GT64260_MPSC_1_CHR_4                            0x9018
815 #define GT64260_MPSC_1_CHR_5                            0x901c
816 #define GT64260_MPSC_1_CHR_6                            0x9020
817 #define GT64260_MPSC_1_CHR_7                            0x9024
818 #define GT64260_MPSC_1_CHR_8                            0x9028
819 #define GT64260_MPSC_1_CHR_9                            0x902c
820 #define GT64260_MPSC_1_CHR_10                           0x9030
821 #define GT64260_MPSC_1_CHR_11                           0x9034
822
823 #define GT64260_MPSC_0_INTR_CAUSE                       0xb804
824 #define GT64260_MPSC_0_INTR_MASK                        0xb884
825 #define GT64260_MPSC_1_INTR_CAUSE                       0xb80c
826 #define GT64260_MPSC_1_INTR_MASK                        0xb88c
827
828 #define GT64260_MPSC_UART_CR_TEV                        (1<<1)
829 #define GT64260_MPSC_UART_CR_TA                         (1<<7)
830 #define GT64260_MPSC_UART_CR_TTCS                       (1<<9)
831 #define GT64260_MPSC_UART_CR_REV                        (1<<17)
832 #define GT64260_MPSC_UART_CR_RA                         (1<<23)
833 #define GT64260_MPSC_UART_CR_CRD                        (1<<25)
834 #define GT64260_MPSC_UART_CR_EH                         (1<<31)
835
836 #define GT64260_MPSC_UART_ESR_CTS                       (1<<0)
837 #define GT64260_MPSC_UART_ESR_CD                        (1<<1)
838 #define GT64260_MPSC_UART_ESR_TIDLE                     (1<<3)
839 #define GT64260_MPSC_UART_ESR_RHS                       (1<<5)
840 #define GT64260_MPSC_UART_ESR_RLS                       (1<<7)
841 #define GT64260_MPSC_UART_ESR_RLIDL                     (1<<11)
842
843
844 /*
845  *****************************************************************************
846  *
847  *      Serial DMA Controller Interface Registers
848  *
849  *****************************************************************************
850  */
851
852 #define GT64260_SDMA_0_SDC                              0x4000
853 #define GT64260_SDMA_0_SDCM                             0x4008
854 #define GT64260_SDMA_0_RX_DESC                          0x4800
855 #define GT64260_SDMA_0_RX_BUF_PTR                       0x4808
856 #define GT64260_SDMA_0_SCRDP                            0x4810
857 #define GT64260_SDMA_0_TX_DESC                          0x4c00
858 #define GT64260_SDMA_0_SCTDP                            0x4c10
859 #define GT64260_SDMA_0_SFTDP                            0x4c14
860
861 #define GT64260_SDMA_1_SDC                              0x6000
862 #define GT64260_SDMA_1_SDCM                             0x6008
863 #define GT64260_SDMA_1_RX_DESC                          0x6800
864 #define GT64260_SDMA_1_RX_BUF_PTR                       0x6808
865 #define GT64260_SDMA_1_SCRDP                            0x6810
866 #define GT64260_SDMA_1_TX_DESC                          0x6c00
867 #define GT64260_SDMA_1_SCTDP                            0x6c10
868 #define GT64260_SDMA_1_SFTDP                            0x6c14
869
870 #define GT64260_SDMA_INTR_CAUSE                         0xb800
871 #define GT64260_SDMA_INTR_MASK                          0xb880
872
873 #define GT64260_SDMA_DESC_CMDSTAT_PE                    (1<<0)
874 #define GT64260_SDMA_DESC_CMDSTAT_CDL                   (1<<1)
875 #define GT64260_SDMA_DESC_CMDSTAT_FR                    (1<<3)
876 #define GT64260_SDMA_DESC_CMDSTAT_OR                    (1<<6)
877 #define GT64260_SDMA_DESC_CMDSTAT_BR                    (1<<9)
878 #define GT64260_SDMA_DESC_CMDSTAT_MI                    (1<<10)
879 #define GT64260_SDMA_DESC_CMDSTAT_A                     (1<<11)
880 #define GT64260_SDMA_DESC_CMDSTAT_AM                    (1<<12)
881 #define GT64260_SDMA_DESC_CMDSTAT_CT                    (1<<13)
882 #define GT64260_SDMA_DESC_CMDSTAT_C                     (1<<14)
883 #define GT64260_SDMA_DESC_CMDSTAT_ES                    (1<<15)
884 #define GT64260_SDMA_DESC_CMDSTAT_L                     (1<<16)
885 #define GT64260_SDMA_DESC_CMDSTAT_F                     (1<<17)
886 #define GT64260_SDMA_DESC_CMDSTAT_P                     (1<<18)
887 #define GT64260_SDMA_DESC_CMDSTAT_EI                    (1<<23)
888 #define GT64260_SDMA_DESC_CMDSTAT_O                     (1<<31)
889
890 #define GT64260_SDMA_SDC_RFT                            (1<<0)
891 #define GT64260_SDMA_SDC_SFM                            (1<<1)
892 #define GT64260_SDMA_SDC_BLMR                           (1<<6)
893 #define GT64260_SDMA_SDC_BLMT                           (1<<7)
894 #define GT64260_SDMA_SDC_POVR                           (1<<8)
895 #define GT64260_SDMA_SDC_RIFB                           (1<<9)
896
897 #define GT64260_SDMA_SDCM_ERD                           (1<<7)
898 #define GT64260_SDMA_SDCM_AR                            (1<<15)
899 #define GT64260_SDMA_SDCM_STD                           (1<<16)
900 #define GT64260_SDMA_SDCM_TXD                           (1<<23)
901 #define GT64260_SDMA_SDCM_AT                            (1<<31)
902
903 #define GT64260_SDMA_0_CAUSE_RXBUF                      (1<<0)
904 #define GT64260_SDMA_0_CAUSE_RXERR                      (1<<1)
905 #define GT64260_SDMA_0_CAUSE_TXBUF                      (1<<2)
906 #define GT64260_SDMA_0_CAUSE_TXEND                      (1<<3)
907 #define GT64260_SDMA_1_CAUSE_RXBUF                      (1<<8)
908 #define GT64260_SDMA_1_CAUSE_RXERR                      (1<<9)
909 #define GT64260_SDMA_1_CAUSE_TXBUF                      (1<<10)
910 #define GT64260_SDMA_1_CAUSE_TXEND                      (1<<11)
911
912
913 /*
914  *****************************************************************************
915  *
916  *      Baud Rate Generator Interface Registers
917  *
918  *****************************************************************************
919  */
920
921 #define GT64260_BRG_0_BCR                               0xb200
922 #define GT64260_BRG_0_BTR                               0xb204
923 #define GT64260_BRG_1_BCR                               0xb208
924 #define GT64260_BRG_1_BTR                               0xb20c
925 #define GT64260_BRG_2_BCR                               0xb210
926 #define GT64260_BRG_2_BTR                               0xb214
927
928 #define GT64260_BRG_INTR_CAUSE                          0xb834
929 #define GT64260_BRG_INTR_MASK                           0xb8b4
930
931
932 /*
933  *****************************************************************************
934  *
935  *      Watchdog Timer Interface Registers
936  *
937  *****************************************************************************
938  */
939
940 #define GT64260_WDT_WDC                                 0xb410
941 #define GT64260_WDT_WDV                                 0xb414
942
943
944 /*
945  *****************************************************************************
946  *
947  *       General Purpose Pins Controller Interface Registers
948  *
949  *****************************************************************************
950  */
951
952 #define GT64260_GPP_IO_CNTL                             0xf100
953 #define GT64260_GPP_LEVEL_CNTL                          0xf110
954 #define GT64260_GPP_VALUE                               0xf104
955 #define GT64260_GPP_INTR_CAUSE                          0xf108
956 #define GT64260_GPP_INTR_MASK                           0xf10c
957
958
959 /*
960  *****************************************************************************
961  *
962  *      Multi-Purpose Pins Controller Interface Registers
963  *
964  *****************************************************************************
965  */
966
967 #define GT64260_MPP_CNTL_0                              0xf000
968 #define GT64260_MPP_CNTL_1                              0xf004
969 #define GT64260_MPP_CNTL_2                              0xf008
970 #define GT64260_MPP_CNTL_3                              0xf00c
971 #define GT64260_MPP_SERIAL_PORTS_MULTIPLEX              0xf010
972
973
974 /*
975  *****************************************************************************
976  *
977  *      I2C Controller Interface Registers
978  *
979  *****************************************************************************
980  */
981
982 /* FIXME: fill in */
983
984
985 /*
986  *****************************************************************************
987  *
988  *      Interrupt Controller Interface Registers
989  *
990  *****************************************************************************
991  */
992
993 #define GT64260_IC_MAIN_CAUSE_LO                        0x0c18
994 #define GT64260_IC_MAIN_CAUSE_HI                        0x0c68
995 #define GT64260_IC_CPU_INTR_MASK_LO                     0x0c1c
996 #define GT64260_IC_CPU_INTR_MASK_HI                     0x0c6c
997 #define GT64260_IC_CPU_SELECT_CAUSE                     0x0c70
998 #define GT64260_IC_PCI_0_INTR_MASK_LO                   0x0c24
999 #define GT64260_IC_PCI_0_INTR_MASK_HI                   0x0c64
1000 #define GT64260_IC_PCI_0_SELECT_CAUSE                   0x0c74
1001 #define GT64260_IC_PCI_1_INTR_MASK_LO                   0x0ca4
1002 #define GT64260_IC_PCI_1_INTR_MASK_HI                   0x0ce4
1003 #define GT64260_IC_PCI_1_SELECT_CAUSE                   0x0cf4
1004 #define GT64260_IC_CPU_INT_0_MASK                       0x0e60
1005 #define GT64260_IC_CPU_INT_1_MASK                       0x0e64
1006 #define GT64260_IC_CPU_INT_2_MASK                       0x0e68
1007 #define GT64260_IC_CPU_INT_3_MASK                       0x0e6c
1008
1009
1010 #endif /* __ASMPPC_GT64260_DEFS_H */