Don't include linux/config.h from anywhere else in include/
[linux-2.6.git] / include / asm-ppc / gt64260.h
1 /*
2  * include/asm-ppc/gt64260.h
3  *
4  * Prototypes, etc. for the Marvell/Galileo GT64260 host bridge routines.
5  *
6  * Author: Mark A. Greer <mgreer@mvista.com>
7  *
8  * 2001 (c) MontaVista, Software, Inc.  This file is licensed under
9  * the terms of the GNU General Public License version 2.  This program
10  * is licensed "as is" without any warranty of any kind, whether express
11  * or implied.
12  */
13 #ifndef __ASMPPC_GT64260_H
14 #define __ASMPPC_GT64260_H
15
16 #include <linux/kernel.h>
17 #include <linux/init.h>
18 #include <linux/pci.h>
19 #include <linux/slab.h>
20
21 #include <asm/byteorder.h>
22 #include <asm/io.h>
23 #include <asm/irq.h>
24 #include <asm/uaccess.h>
25 #include <asm/machdep.h>
26 #include <asm/pci-bridge.h>
27 #include <asm/gt64260_defs.h>
28
29
30 extern u32     gt64260_base;
31 extern u32     gt64260_irq_base;     /* We handle the next 96 IRQs from here */
32 extern u32     gt64260_revision;
33 extern u8      gt64260_pci_exclude_bridge;
34
35 #ifndef TRUE
36 #define TRUE    1
37 #endif
38
39 #ifndef FALSE
40 #define FALSE   0
41 #endif
42
43 /* IRQs defined by the 64260 */
44 #define GT64260_IRQ_MPSC0               40
45 #define GT64260_IRQ_MPSC1               42
46 #define GT64260_IRQ_SDMA                36
47
48 /*
49  * Define a default physical memory map to be set up on the bridge.
50  * Also define a struct to pass that info from board-specific routines to
51  * GT64260 generic set up routines.  By passing this info in, the board
52  * support developer can modify it at will.
53  */
54
55 /*
56  * This is the default memory map:
57  *                      CPU                     PCI
58  *                      ---                     ---
59  * PCI 0 I/O:   0xfa000000-0xfaffffff   0x00000000-0x00ffffff
60  * PCI 1 I/O:   0xfb000000-0xfbffffff   0x01000000-0x01ffffff
61  * PCI 0 MEM:   0x80000000-0x8fffffff   0x80000000-0x8fffffff
62  * PCI 1 MEM:   0x90000000-0x9fffffff   0x90000000-0x9fffffff
63  */
64
65 /* Default physical memory map for the GT64260 bridge */
66
67 /*
68  * PCI Bus 0 Definitions
69  */
70 #define GT64260_PCI_0_IO_SIZE           0x01000000U
71 #define GT64260_PCI_0_MEM_SIZE          0x10000000U
72
73 /* Processor Physical addresses */
74 #define GT64260_PCI_0_IO_START_PROC     0xfa000000U
75 #define GT64260_PCI_0_IO_END_PROC       (GT64260_PCI_0_IO_START_PROC + \
76                                          GT64260_PCI_0_IO_SIZE - 1)
77
78 /* PCI 0 addresses */
79 #define GT64260_PCI_0_IO_START          0x00000000U
80 #define GT64260_PCI_0_IO_END            (GT64260_PCI_0_IO_START + \
81                                          GT64260_PCI_0_IO_SIZE - 1)
82
83 /* Processor Physical addresses */
84 #define GT64260_PCI_0_MEM_START_PROC    0x80000000U
85 #define GT64260_PCI_0_MEM_END_PROC      (GT64260_PCI_0_MEM_START_PROC + \
86                                          GT64260_PCI_0_MEM_SIZE - 1)
87
88 /* PCI 0 addresses */
89 #define GT64260_PCI_0_MEM_START         0x80000000U
90 #define GT64260_PCI_0_MEM_END           (GT64260_PCI_0_MEM_START + \
91                                          GT64260_PCI_0_MEM_SIZE - 1)
92
93 /*
94  * PCI Bus 1 Definitions
95  */
96 #define GT64260_PCI_1_IO_SIZE           0x01000000U
97 #define GT64260_PCI_1_MEM_SIZE          0x10000000U
98
99 /* PCI 1 addresses */
100 #define GT64260_PCI_1_IO_START          0x01000000U
101 #define GT64260_PCI_1_IO_END            (GT64260_PCI_1_IO_START + \
102                                          GT64260_PCI_1_IO_SIZE - 1)
103
104 /* Processor Physical addresses */
105 #define GT64260_PCI_1_IO_START_PROC     0xfb000000U
106 #define GT64260_PCI_1_IO_END_PROC       (GT64260_PCI_1_IO_START_PROC + \
107                                          GT64260_PCI_1_IO_SIZE - 1)
108
109 /* PCI 1 addresses */
110 #define GT64260_PCI_1_MEM_START         0x90000000U
111 #define GT64260_PCI_1_MEM_END           (GT64260_PCI_1_MEM_START + \
112                                          GT64260_PCI_1_MEM_SIZE - 1)
113
114 /* Processor Physical addresses */
115 #define GT64260_PCI_1_MEM_START_PROC    0x90000000U
116 #define GT64260_PCI_1_MEM_END_PROC      (GT64260_PCI_1_MEM_START_PROC + \
117                                          GT64260_PCI_1_MEM_SIZE - 1)
118
119 /* Define struct to pass mem-map info into gt64260_common.c code */
120 typedef struct {
121         struct pci_controller   *hose_a;
122         struct pci_controller   *hose_b;
123
124         u32     mem_size;
125
126         u32     pci_0_io_start_proc;
127         u32     pci_0_io_start_pci;
128         u32     pci_0_io_size;
129         u32     pci_0_io_swap;
130
131         u32     pci_0_mem_start_proc;
132         u32     pci_0_mem_start_pci_hi;
133         u32     pci_0_mem_start_pci_lo;
134         u32     pci_0_mem_size;
135         u32     pci_0_mem_swap;
136
137         u32     pci_1_io_start_proc;
138         u32     pci_1_io_start_pci;
139         u32     pci_1_io_size;
140         u32     pci_1_io_swap;
141
142         u32     pci_1_mem_start_proc;
143         u32     pci_1_mem_start_pci_hi;
144         u32     pci_1_mem_start_pci_lo;
145         u32     pci_1_mem_size;
146         u32     pci_1_mem_swap;
147 } gt64260_bridge_info_t;
148
149 #define GT64260_BRIDGE_INFO_DEFAULT(ip, ms) {                           \
150         (ip)->mem_size = (ms);                                          \
151                                                                         \
152         (ip)->pci_0_io_start_proc = GT64260_PCI_0_IO_START_PROC;        \
153         (ip)->pci_0_io_start_pci  = GT64260_PCI_0_IO_START;             \
154         (ip)->pci_0_io_size       = GT64260_PCI_0_IO_SIZE;              \
155         (ip)->pci_0_io_swap       = GT64260_CPU_PCI_SWAP_NONE;          \
156                                                                         \
157         (ip)->pci_0_mem_start_proc   = GT64260_PCI_0_MEM_START_PROC;    \
158         (ip)->pci_0_mem_start_pci_hi = 0x00000000;                      \
159         (ip)->pci_0_mem_start_pci_lo = GT64260_PCI_0_MEM_START;         \
160         (ip)->pci_0_mem_size         = GT64260_PCI_0_MEM_SIZE;          \
161         (ip)->pci_0_mem_swap         = GT64260_CPU_PCI_SWAP_NONE;       \
162                                                                         \
163         (ip)->pci_1_io_start_proc = GT64260_PCI_1_IO_START_PROC;        \
164         (ip)->pci_1_io_start_pci  = GT64260_PCI_1_IO_START;             \
165         (ip)->pci_1_io_size       = GT64260_PCI_1_IO_SIZE;              \
166         (ip)->pci_1_io_swap       = GT64260_CPU_PCI_SWAP_NONE;          \
167                                                                         \
168         (ip)->pci_1_mem_start_proc   = GT64260_PCI_1_MEM_START_PROC;    \
169         (ip)->pci_1_mem_start_pci_hi = 0x00000000;                      \
170         (ip)->pci_1_mem_start_pci_lo = GT64260_PCI_1_MEM_START;         \
171         (ip)->pci_1_mem_size         = GT64260_PCI_1_MEM_SIZE;          \
172         (ip)->pci_1_mem_swap         = GT64260_CPU_PCI_SWAP_NONE;       \
173 }
174
175 /*
176  *****************************************************************************
177  *
178  *      I/O macros to access the 64260's registers
179  *
180  *****************************************************************************
181  */
182
183 extern inline uint32_t gt_read(uint32_t offs){
184         return (in_le32((volatile uint *)(gt64260_base + offs)));
185 }
186 extern inline void gt_write(uint32_t offs, uint32_t d){
187         out_le32((volatile uint *)(gt64260_base + offs), d);
188 }
189
190 #if 0 /* paranoid SMP version */
191 extern inline void gt_modify(u32 offs, u32 data, u32 mask) \
192 {
193         uint32_t reg;
194         spin_lock(&gt64260_lock);
195         reg = gt_read(offs) & (~mask); /* zero any bits we care about*/
196         reg |= data & mask; /* set bits from the data */
197         gt_write(offs, reg);
198         spin_unlock(&gt64260_lock);
199 }
200 #else
201 extern inline void gt_modify(uint32_t offs, uint32_t data, uint32_t mask)
202 {
203         uint32_t reg;
204         reg = gt_read(offs) & (~(mask)); /* zero any bits we care about*/
205         reg |= (data) & (mask); /* set bits from the data */
206         gt_write(offs, reg);
207 }
208 #endif
209 #define gt_set_bits(offs, bits) gt_modify(offs, ~0, bits)
210
211 #define gt_clr_bits(offs, bits) gt_modify(offs, 0, bits)
212
213
214 /*
215  *****************************************************************************
216  *
217  *      Function Prototypes
218  *
219  *****************************************************************************
220  */
221
222 int gt64260_find_bridges(u32 phys_base_addr, gt64260_bridge_info_t *info,
223         int ((*map_irq)(struct pci_dev *, unsigned char, unsigned char)));
224 int gt64260_bridge_init(gt64260_bridge_info_t *info);
225 int gt64260_cpu_scs_set_window(u32 window,
226                                u32 base_addr,
227                                u32 size);
228 int gt64260_cpu_cs_set_window(u32 window,
229                               u32 base_addr,
230                               u32 size);
231 int gt64260_cpu_boot_set_window(u32 base_addr,
232                                 u32 size);
233 int gt64260_cpu_set_pci_io_window(u32 pci_bus,
234                                   u32 cpu_base_addr,
235                                   u32 pci_base_addr,
236                                   u32 size,
237                                   u32 swap);
238 int gt64260_cpu_set_pci_mem_window(u32 pci_bus,
239                                    u32 window,
240                                    u32 cpu_base_addr,
241                                    u32 pci_base_addr_hi,
242                                    u32 pci_base_addr_lo,
243                                    u32 size,
244                                    u32 swap_64bit);
245 int gt64260_cpu_prot_set_window(u32 window,
246                                 u32 base_addr,
247                                 u32 size,
248                                 u32 access_bits);
249 int gt64260_cpu_snoop_set_window(u32 window,
250                                  u32 base_addr,
251                                  u32 size,
252                                  u32  snoop_type);
253 void gt64260_cpu_disable_all_windows(void);
254 int gt64260_pci_bar_enable(u32 pci_bus, u32 enable_bits);
255 int gt64260_pci_slave_scs_set_window(struct pci_controller *hose,
256                                      u32 window,
257                                      u32 pci_base_addr,
258                                      u32 cpu_base_addr,
259                                      u32 size);
260 int gt64260_pci_slave_cs_set_window(struct pci_controller *hose,
261                                     u32 window,
262                                     u32 pci_base_addr,
263                                     u32 cpu_base_addr,
264                                     u32 size);
265 int gt64260_pci_slave_boot_set_window(struct pci_controller *hose,
266                                       u32 pci_base_addr,
267                                       u32 cpu_base_addr,
268                                       u32 size);
269 int gt64260_pci_slave_p2p_mem_set_window(struct pci_controller *hose,
270                                          u32 window,
271                                          u32 pci_base_addr,
272                                          u32 other_bus_base_addr,
273                                          u32 size);
274 int gt64260_pci_slave_p2p_io_set_window(struct pci_controller *hose,
275                                         u32 pci_base_addr,
276                                         u32 other_bus_base_addr,
277                                         u32 size);
278 int gt64260_pci_slave_dac_scs_set_window(struct pci_controller *hose,
279                                          u32 window,
280                                          u32 pci_base_addr_hi,
281                                          u32 pci_base_addr_lo,
282                                          u32 cpu_base_addr,
283                                          u32 size);
284 int gt64260_pci_slave_dac_cs_set_window(struct pci_controller *hose,
285                                         u32 window,
286                                         u32 pci_base_addr_hi,
287                                         u32 pci_base_addr_lo,
288                                         u32 cpu_base_addr,
289                                         u32 size);
290 int gt64260_pci_slave_dac_boot_set_window(struct pci_controller *hose,
291                                           u32 pci_base_addr_hi,
292                                           u32 pci_base_addr_lo,
293                                           u32 cpu_base_addr,
294                                           u32 size);
295 int gt64260_pci_slave_dac_p2p_mem_set_window(struct pci_controller *hose,
296                                              u32 window,
297                                              u32 pci_base_addr_hi,
298                                              u32 pci_base_addr_lo,
299                                              u32 other_bus_base_addr,
300                                              u32 size);
301 int gt64260_pci_acc_cntl_set_window(u32 pci_bus,
302                                     u32 window,
303                                     u32 base_addr_hi,
304                                     u32 base_addr_lo,
305                                     u32 size,
306                                     u32 features);
307 int gt64260_pci_snoop_set_window(u32 pci_bus,
308                                  u32 window,
309                                  u32 base_addr_hi,
310                                  u32 base_addr_lo,
311                                  u32 size,
312                                  u32 snoop_type);
313 int gt64260_set_base(u32 new_base);
314 int gt64260_get_base(u32 *base);
315 int gt64260_pci_exclude_device(u8 bus, u8 devfn);
316
317 void gt64260_init_irq(void);
318 int gt64260_get_irq(struct pt_regs *regs);
319
320 void gt64260_mpsc_progress(char *s, unsigned short hex);
321
322 #endif /* __ASMPPC_GT64260_H */