[POWERPC] cell: handle SPE kernel mappings that cross segment boundaries
[linux-2.6.git] / include / asm-powerpc / spu.h
1 /*
2  * SPU core / file system interface and HW structures
3  *
4  * (C) Copyright IBM Deutschland Entwicklung GmbH 2005
5  *
6  * Author: Arnd Bergmann <arndb@de.ibm.com>
7  *
8  * This program is free software; you can redistribute it and/or modify
9  * it under the terms of the GNU General Public License as published by
10  * the Free Software Foundation; either version 2, or (at your option)
11  * any later version.
12  *
13  * This program is distributed in the hope that it will be useful,
14  * but WITHOUT ANY WARRANTY; without even the implied warranty of
15  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16  * GNU General Public License for more details.
17  *
18  * You should have received a copy of the GNU General Public License
19  * along with this program; if not, write to the Free Software
20  * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
21  */
22
23 #ifndef _SPU_H
24 #define _SPU_H
25 #ifdef __KERNEL__
26
27 #include <linux/workqueue.h>
28 #include <linux/sysdev.h>
29
30 #define LS_SIZE (256 * 1024)
31 #define LS_ADDR_MASK (LS_SIZE - 1)
32
33 #define MFC_PUT_CMD             0x20
34 #define MFC_PUTS_CMD            0x28
35 #define MFC_PUTR_CMD            0x30
36 #define MFC_PUTF_CMD            0x22
37 #define MFC_PUTB_CMD            0x21
38 #define MFC_PUTFS_CMD           0x2A
39 #define MFC_PUTBS_CMD           0x29
40 #define MFC_PUTRF_CMD           0x32
41 #define MFC_PUTRB_CMD           0x31
42 #define MFC_PUTL_CMD            0x24
43 #define MFC_PUTRL_CMD           0x34
44 #define MFC_PUTLF_CMD           0x26
45 #define MFC_PUTLB_CMD           0x25
46 #define MFC_PUTRLF_CMD          0x36
47 #define MFC_PUTRLB_CMD          0x35
48
49 #define MFC_GET_CMD             0x40
50 #define MFC_GETS_CMD            0x48
51 #define MFC_GETF_CMD            0x42
52 #define MFC_GETB_CMD            0x41
53 #define MFC_GETFS_CMD           0x4A
54 #define MFC_GETBS_CMD           0x49
55 #define MFC_GETL_CMD            0x44
56 #define MFC_GETLF_CMD           0x46
57 #define MFC_GETLB_CMD           0x45
58
59 #define MFC_SDCRT_CMD           0x80
60 #define MFC_SDCRTST_CMD         0x81
61 #define MFC_SDCRZ_CMD           0x89
62 #define MFC_SDCRS_CMD           0x8D
63 #define MFC_SDCRF_CMD           0x8F
64
65 #define MFC_GETLLAR_CMD         0xD0
66 #define MFC_PUTLLC_CMD          0xB4
67 #define MFC_PUTLLUC_CMD         0xB0
68 #define MFC_PUTQLLUC_CMD        0xB8
69 #define MFC_SNDSIG_CMD          0xA0
70 #define MFC_SNDSIGB_CMD         0xA1
71 #define MFC_SNDSIGF_CMD         0xA2
72 #define MFC_BARRIER_CMD         0xC0
73 #define MFC_EIEIO_CMD           0xC8
74 #define MFC_SYNC_CMD            0xCC
75
76 #define MFC_MIN_DMA_SIZE_SHIFT  4       /* 16 bytes */
77 #define MFC_MAX_DMA_SIZE_SHIFT  14      /* 16384 bytes */
78 #define MFC_MIN_DMA_SIZE        (1 << MFC_MIN_DMA_SIZE_SHIFT)
79 #define MFC_MAX_DMA_SIZE        (1 << MFC_MAX_DMA_SIZE_SHIFT)
80 #define MFC_MIN_DMA_SIZE_MASK   (MFC_MIN_DMA_SIZE - 1)
81 #define MFC_MAX_DMA_SIZE_MASK   (MFC_MAX_DMA_SIZE - 1)
82 #define MFC_MIN_DMA_LIST_SIZE   0x0008  /*   8 bytes */
83 #define MFC_MAX_DMA_LIST_SIZE   0x4000  /* 16K bytes */
84
85 #define MFC_TAGID_TO_TAGMASK(tag_id)  (1 << (tag_id & 0x1F))
86
87 /* Events for Channels 0-2 */
88 #define MFC_DMA_TAG_STATUS_UPDATE_EVENT     0x00000001
89 #define MFC_DMA_TAG_CMD_STALL_NOTIFY_EVENT  0x00000002
90 #define MFC_DMA_QUEUE_AVAILABLE_EVENT       0x00000008
91 #define MFC_SPU_MAILBOX_WRITTEN_EVENT       0x00000010
92 #define MFC_DECREMENTER_EVENT               0x00000020
93 #define MFC_PU_INT_MAILBOX_AVAILABLE_EVENT  0x00000040
94 #define MFC_PU_MAILBOX_AVAILABLE_EVENT      0x00000080
95 #define MFC_SIGNAL_2_EVENT                  0x00000100
96 #define MFC_SIGNAL_1_EVENT                  0x00000200
97 #define MFC_LLR_LOST_EVENT                  0x00000400
98 #define MFC_PRIV_ATTN_EVENT                 0x00000800
99 #define MFC_MULTI_SRC_EVENT                 0x00001000
100
101 /* Flags indicating progress during context switch. */
102 #define SPU_CONTEXT_SWITCH_PENDING      0UL
103 #define SPU_CONTEXT_SWITCH_ACTIVE       1UL
104
105 struct spu_context;
106 struct spu_runqueue;
107 struct spu_lscsa;
108 struct device_node;
109
110 enum spu_utilization_state {
111         SPU_UTIL_USER,
112         SPU_UTIL_SYSTEM,
113         SPU_UTIL_IOWAIT,
114         SPU_UTIL_IDLE_LOADED,
115         SPU_UTIL_MAX
116 };
117
118 struct spu {
119         const char *name;
120         unsigned long local_store_phys;
121         u8 *local_store;
122         unsigned long problem_phys;
123         struct spu_problem __iomem *problem;
124         struct spu_priv2 __iomem *priv2;
125         struct list_head cbe_list;
126         struct list_head full_list;
127         enum { SPU_FREE, SPU_USED } alloc_state;
128         int number;
129         unsigned int irqs[3];
130         u32 node;
131         u64 flags;
132         u64 dar;
133         u64 dsisr;
134         u64 class_0_pending;
135         size_t ls_size;
136         unsigned int slb_replace;
137         struct mm_struct *mm;
138         struct spu_context *ctx;
139         struct spu_runqueue *rq;
140         unsigned long long timestamp;
141         pid_t pid;
142         pid_t tgid;
143         spinlock_t register_lock;
144
145         void (* wbox_callback)(struct spu *spu);
146         void (* ibox_callback)(struct spu *spu);
147         void (* stop_callback)(struct spu *spu);
148         void (* mfc_callback)(struct spu *spu);
149         void (* dma_callback)(struct spu *spu, int type);
150
151         char irq_c0[8];
152         char irq_c1[8];
153         char irq_c2[8];
154
155         u64 spe_id;
156
157         void* pdata; /* platform private data */
158
159         /* of based platforms only */
160         struct device_node *devnode;
161
162         /* native only */
163         struct spu_priv1 __iomem *priv1;
164
165         /* beat only */
166         u64 shadow_int_mask_RW[3];
167
168         struct sys_device sysdev;
169
170         int has_mem_affinity;
171         struct list_head aff_list;
172
173         struct {
174                 /* protected by interrupt reentrancy */
175                 enum spu_utilization_state util_state;
176                 unsigned long long tstamp;
177                 unsigned long long times[SPU_UTIL_MAX];
178                 unsigned long long vol_ctx_switch;
179                 unsigned long long invol_ctx_switch;
180                 unsigned long long min_flt;
181                 unsigned long long maj_flt;
182                 unsigned long long hash_flt;
183                 unsigned long long slb_flt;
184                 unsigned long long class2_intr;
185                 unsigned long long libassist;
186         } stats;
187 };
188
189 struct cbe_spu_info {
190         struct mutex list_mutex;
191         struct list_head spus;
192         int n_spus;
193         int nr_active;
194         atomic_t reserved_spus;
195 };
196
197 extern struct cbe_spu_info cbe_spu_info[];
198
199 void spu_init_channels(struct spu *spu);
200 int spu_irq_class_0_bottom(struct spu *spu);
201 int spu_irq_class_1_bottom(struct spu *spu);
202 void spu_irq_setaffinity(struct spu *spu, int cpu);
203
204 void spu_setup_kernel_slbs(struct spu *spu, struct spu_lscsa *lscsa,
205                 void *code, int code_size);
206
207 #ifdef CONFIG_KEXEC
208 void crash_register_spus(struct list_head *list);
209 #else
210 static inline void crash_register_spus(struct list_head *list)
211 {
212 }
213 #endif
214
215 extern void spu_invalidate_slbs(struct spu *spu);
216 extern void spu_associate_mm(struct spu *spu, struct mm_struct *mm);
217 int spu_64k_pages_available(void);
218
219 /* Calls from the memory management to the SPU */
220 struct mm_struct;
221 extern void spu_flush_all_slbs(struct mm_struct *mm);
222
223 /* This interface allows a profiler (e.g., OProfile) to store a ref
224  * to spu context information that it creates.  This caching technique
225  * avoids the need to recreate this information after a save/restore operation.
226  *
227  * Assumes the caller has already incremented the ref count to
228  * profile_info; then spu_context_destroy must call kref_put
229  * on prof_info_kref.
230  */
231 void spu_set_profile_private_kref(struct spu_context *ctx,
232                                   struct kref *prof_info_kref,
233                                   void ( * prof_info_release) (struct kref *kref));
234
235 void *spu_get_profile_private_kref(struct spu_context *ctx);
236
237 /* system callbacks from the SPU */
238 struct spu_syscall_block {
239         u64 nr_ret;
240         u64 parm[6];
241 };
242 extern long spu_sys_callback(struct spu_syscall_block *s);
243
244 /* syscalls implemented in spufs */
245 struct file;
246 struct spufs_calls {
247         long (*create_thread)(const char __user *name,
248                                         unsigned int flags, mode_t mode,
249                                         struct file *neighbor);
250         long (*spu_run)(struct file *filp, __u32 __user *unpc,
251                                                 __u32 __user *ustatus);
252         int (*coredump_extra_notes_size)(void);
253         int (*coredump_extra_notes_write)(struct file *file, loff_t *foffset);
254         struct module *owner;
255 };
256
257 /* return status from spu_run, same as in libspe */
258 #define SPE_EVENT_DMA_ALIGNMENT         0x0008  /*A DMA alignment error */
259 #define SPE_EVENT_SPE_ERROR             0x0010  /*An illegal instruction error*/
260 #define SPE_EVENT_SPE_DATA_SEGMENT      0x0020  /*A DMA segmentation error    */
261 #define SPE_EVENT_SPE_DATA_STORAGE      0x0040  /*A DMA storage error */
262 #define SPE_EVENT_INVALID_DMA           0x0800  /* Invalid MFC DMA */
263
264 /*
265  * Flags for sys_spu_create.
266  */
267 #define SPU_CREATE_EVENTS_ENABLED       0x0001
268 #define SPU_CREATE_GANG                 0x0002
269 #define SPU_CREATE_NOSCHED              0x0004
270 #define SPU_CREATE_ISOLATE              0x0008
271 #define SPU_CREATE_AFFINITY_SPU         0x0010
272 #define SPU_CREATE_AFFINITY_MEM         0x0020
273
274 #define SPU_CREATE_FLAG_ALL             0x003f /* mask of all valid flags */
275
276
277 int register_spu_syscalls(struct spufs_calls *calls);
278 void unregister_spu_syscalls(struct spufs_calls *calls);
279
280 int spu_add_sysdev_attr(struct sysdev_attribute *attr);
281 void spu_remove_sysdev_attr(struct sysdev_attribute *attr);
282
283 int spu_add_sysdev_attr_group(struct attribute_group *attrs);
284 void spu_remove_sysdev_attr_group(struct attribute_group *attrs);
285
286
287 /*
288  * Notifier blocks:
289  *
290  * oprofile can get notified when a context switch is performed
291  * on an spe. The notifer function that gets called is passed
292  * a pointer to the SPU structure as well as the object-id that
293  * identifies the binary running on that SPU now.
294  *
295  * For a context save, the object-id that is passed is zero,
296  * identifying that the kernel will run from that moment on.
297  *
298  * For a context restore, the object-id is the value written
299  * to object-id spufs file from user space and the notifer
300  * function can assume that spu->ctx is valid.
301  */
302 struct notifier_block;
303 int spu_switch_event_register(struct notifier_block * n);
304 int spu_switch_event_unregister(struct notifier_block * n);
305
306 /*
307  * This defines the Local Store, Problem Area and Privlege Area of an SPU.
308  */
309
310 union mfc_tag_size_class_cmd {
311         struct {
312                 u16 mfc_size;
313                 u16 mfc_tag;
314                 u8  pad;
315                 u8  mfc_rclassid;
316                 u16 mfc_cmd;
317         } u;
318         struct {
319                 u32 mfc_size_tag32;
320                 u32 mfc_class_cmd32;
321         } by32;
322         u64 all64;
323 };
324
325 struct mfc_cq_sr {
326         u64 mfc_cq_data0_RW;
327         u64 mfc_cq_data1_RW;
328         u64 mfc_cq_data2_RW;
329         u64 mfc_cq_data3_RW;
330 };
331
332 struct spu_problem {
333 #define MS_SYNC_PENDING         1L
334         u64 spc_mssync_RW;                                      /* 0x0000 */
335         u8  pad_0x0008_0x3000[0x3000 - 0x0008];
336
337         /* DMA Area */
338         u8  pad_0x3000_0x3004[0x4];                             /* 0x3000 */
339         u32 mfc_lsa_W;                                          /* 0x3004 */
340         u64 mfc_ea_W;                                           /* 0x3008 */
341         union mfc_tag_size_class_cmd mfc_union_W;                       /* 0x3010 */
342         u8  pad_0x3018_0x3104[0xec];                            /* 0x3018 */
343         u32 dma_qstatus_R;                                      /* 0x3104 */
344         u8  pad_0x3108_0x3204[0xfc];                            /* 0x3108 */
345         u32 dma_querytype_RW;                                   /* 0x3204 */
346         u8  pad_0x3208_0x321c[0x14];                            /* 0x3208 */
347         u32 dma_querymask_RW;                                   /* 0x321c */
348         u8  pad_0x3220_0x322c[0xc];                             /* 0x3220 */
349         u32 dma_tagstatus_R;                                    /* 0x322c */
350 #define DMA_TAGSTATUS_INTR_ANY  1u
351 #define DMA_TAGSTATUS_INTR_ALL  2u
352         u8  pad_0x3230_0x4000[0x4000 - 0x3230];                 /* 0x3230 */
353
354         /* SPU Control Area */
355         u8  pad_0x4000_0x4004[0x4];                             /* 0x4000 */
356         u32 pu_mb_R;                                            /* 0x4004 */
357         u8  pad_0x4008_0x400c[0x4];                             /* 0x4008 */
358         u32 spu_mb_W;                                           /* 0x400c */
359         u8  pad_0x4010_0x4014[0x4];                             /* 0x4010 */
360         u32 mb_stat_R;                                          /* 0x4014 */
361         u8  pad_0x4018_0x401c[0x4];                             /* 0x4018 */
362         u32 spu_runcntl_RW;                                     /* 0x401c */
363 #define SPU_RUNCNTL_STOP        0L
364 #define SPU_RUNCNTL_RUNNABLE    1L
365 #define SPU_RUNCNTL_ISOLATE     2L
366         u8  pad_0x4020_0x4024[0x4];                             /* 0x4020 */
367         u32 spu_status_R;                                       /* 0x4024 */
368 #define SPU_STOP_STATUS_SHIFT           16
369 #define SPU_STATUS_STOPPED              0x0
370 #define SPU_STATUS_RUNNING              0x1
371 #define SPU_STATUS_STOPPED_BY_STOP      0x2
372 #define SPU_STATUS_STOPPED_BY_HALT      0x4
373 #define SPU_STATUS_WAITING_FOR_CHANNEL  0x8
374 #define SPU_STATUS_SINGLE_STEP          0x10
375 #define SPU_STATUS_INVALID_INSTR        0x20
376 #define SPU_STATUS_INVALID_CH           0x40
377 #define SPU_STATUS_ISOLATED_STATE       0x80
378 #define SPU_STATUS_ISOLATED_LOAD_STATUS 0x200
379 #define SPU_STATUS_ISOLATED_EXIT_STATUS 0x400
380         u8  pad_0x4028_0x402c[0x4];                             /* 0x4028 */
381         u32 spu_spe_R;                                          /* 0x402c */
382         u8  pad_0x4030_0x4034[0x4];                             /* 0x4030 */
383         u32 spu_npc_RW;                                         /* 0x4034 */
384         u8  pad_0x4038_0x14000[0x14000 - 0x4038];               /* 0x4038 */
385
386         /* Signal Notification Area */
387         u8  pad_0x14000_0x1400c[0xc];                           /* 0x14000 */
388         u32 signal_notify1;                                     /* 0x1400c */
389         u8  pad_0x14010_0x1c00c[0x7ffc];                        /* 0x14010 */
390         u32 signal_notify2;                                     /* 0x1c00c */
391 } __attribute__ ((aligned(0x20000)));
392
393 /* SPU Privilege 2 State Area */
394 struct spu_priv2 {
395         /* MFC Registers */
396         u8  pad_0x0000_0x1100[0x1100 - 0x0000];                 /* 0x0000 */
397
398         /* SLB Management Registers */
399         u8  pad_0x1100_0x1108[0x8];                             /* 0x1100 */
400         u64 slb_index_W;                                        /* 0x1108 */
401 #define SLB_INDEX_MASK                          0x7L
402         u64 slb_esid_RW;                                        /* 0x1110 */
403         u64 slb_vsid_RW;                                        /* 0x1118 */
404 #define SLB_VSID_SUPERVISOR_STATE       (0x1ull << 11)
405 #define SLB_VSID_SUPERVISOR_STATE_MASK  (0x1ull << 11)
406 #define SLB_VSID_PROBLEM_STATE          (0x1ull << 10)
407 #define SLB_VSID_PROBLEM_STATE_MASK     (0x1ull << 10)
408 #define SLB_VSID_EXECUTE_SEGMENT        (0x1ull << 9)
409 #define SLB_VSID_NO_EXECUTE_SEGMENT     (0x1ull << 9)
410 #define SLB_VSID_EXECUTE_SEGMENT_MASK   (0x1ull << 9)
411 #define SLB_VSID_4K_PAGE                (0x0 << 8)
412 #define SLB_VSID_LARGE_PAGE             (0x1ull << 8)
413 #define SLB_VSID_PAGE_SIZE_MASK         (0x1ull << 8)
414 #define SLB_VSID_CLASS_MASK             (0x1ull << 7)
415 #define SLB_VSID_VIRTUAL_PAGE_SIZE_MASK (0x1ull << 6)
416         u64 slb_invalidate_entry_W;                             /* 0x1120 */
417         u64 slb_invalidate_all_W;                               /* 0x1128 */
418         u8  pad_0x1130_0x2000[0x2000 - 0x1130];                 /* 0x1130 */
419
420         /* Context Save / Restore Area */
421         struct mfc_cq_sr spuq[16];                              /* 0x2000 */
422         struct mfc_cq_sr puq[8];                                /* 0x2200 */
423         u8  pad_0x2300_0x3000[0x3000 - 0x2300];                 /* 0x2300 */
424
425         /* MFC Control */
426         u64 mfc_control_RW;                                     /* 0x3000 */
427 #define MFC_CNTL_RESUME_DMA_QUEUE               (0ull << 0)
428 #define MFC_CNTL_SUSPEND_DMA_QUEUE              (1ull << 0)
429 #define MFC_CNTL_SUSPEND_DMA_QUEUE_MASK         (1ull << 0)
430 #define MFC_CNTL_SUSPEND_MASK                   (1ull << 4)
431 #define MFC_CNTL_NORMAL_DMA_QUEUE_OPERATION     (0ull << 8)
432 #define MFC_CNTL_SUSPEND_IN_PROGRESS            (1ull << 8)
433 #define MFC_CNTL_SUSPEND_COMPLETE               (3ull << 8)
434 #define MFC_CNTL_SUSPEND_DMA_STATUS_MASK        (3ull << 8)
435 #define MFC_CNTL_DMA_QUEUES_EMPTY               (1ull << 14)
436 #define MFC_CNTL_DMA_QUEUES_EMPTY_MASK          (1ull << 14)
437 #define MFC_CNTL_PURGE_DMA_REQUEST              (1ull << 15)
438 #define MFC_CNTL_PURGE_DMA_IN_PROGRESS          (1ull << 24)
439 #define MFC_CNTL_PURGE_DMA_COMPLETE             (3ull << 24)
440 #define MFC_CNTL_PURGE_DMA_STATUS_MASK          (3ull << 24)
441 #define MFC_CNTL_RESTART_DMA_COMMAND            (1ull << 32)
442 #define MFC_CNTL_DMA_COMMAND_REISSUE_PENDING    (1ull << 32)
443 #define MFC_CNTL_DMA_COMMAND_REISSUE_STATUS_MASK (1ull << 32)
444 #define MFC_CNTL_MFC_PRIVILEGE_STATE            (2ull << 33)
445 #define MFC_CNTL_MFC_PROBLEM_STATE              (3ull << 33)
446 #define MFC_CNTL_MFC_KEY_PROTECTION_STATE_MASK  (3ull << 33)
447 #define MFC_CNTL_DECREMENTER_HALTED             (1ull << 35)
448 #define MFC_CNTL_DECREMENTER_RUNNING            (1ull << 40)
449 #define MFC_CNTL_DECREMENTER_STATUS_MASK        (1ull << 40)
450         u8  pad_0x3008_0x4000[0x4000 - 0x3008];                 /* 0x3008 */
451
452         /* Interrupt Mailbox */
453         u64 puint_mb_R;                                         /* 0x4000 */
454         u8  pad_0x4008_0x4040[0x4040 - 0x4008];                 /* 0x4008 */
455
456         /* SPU Control */
457         u64 spu_privcntl_RW;                                    /* 0x4040 */
458 #define SPU_PRIVCNTL_MODE_NORMAL                (0x0ull << 0)
459 #define SPU_PRIVCNTL_MODE_SINGLE_STEP           (0x1ull << 0)
460 #define SPU_PRIVCNTL_MODE_MASK                  (0x1ull << 0)
461 #define SPU_PRIVCNTL_NO_ATTENTION_EVENT         (0x0ull << 1)
462 #define SPU_PRIVCNTL_ATTENTION_EVENT            (0x1ull << 1)
463 #define SPU_PRIVCNTL_ATTENTION_EVENT_MASK       (0x1ull << 1)
464 #define SPU_PRIVCNT_LOAD_REQUEST_NORMAL         (0x0ull << 2)
465 #define SPU_PRIVCNT_LOAD_REQUEST_ENABLE_MASK    (0x1ull << 2)
466         u8  pad_0x4048_0x4058[0x10];                            /* 0x4048 */
467         u64 spu_lslr_RW;                                        /* 0x4058 */
468         u64 spu_chnlcntptr_RW;                                  /* 0x4060 */
469         u64 spu_chnlcnt_RW;                                     /* 0x4068 */
470         u64 spu_chnldata_RW;                                    /* 0x4070 */
471         u64 spu_cfg_RW;                                         /* 0x4078 */
472         u8  pad_0x4080_0x5000[0x5000 - 0x4080];                 /* 0x4080 */
473
474         /* PV2_ImplRegs: Implementation-specific privileged-state 2 regs */
475         u64 spu_pm_trace_tag_status_RW;                         /* 0x5000 */
476         u64 spu_tag_status_query_RW;                            /* 0x5008 */
477 #define TAG_STATUS_QUERY_CONDITION_BITS (0x3ull << 32)
478 #define TAG_STATUS_QUERY_MASK_BITS (0xffffffffull)
479         u64 spu_cmd_buf1_RW;                                    /* 0x5010 */
480 #define SPU_COMMAND_BUFFER_1_LSA_BITS (0x7ffffull << 32)
481 #define SPU_COMMAND_BUFFER_1_EAH_BITS (0xffffffffull)
482         u64 spu_cmd_buf2_RW;                                    /* 0x5018 */
483 #define SPU_COMMAND_BUFFER_2_EAL_BITS ((0xffffffffull) << 32)
484 #define SPU_COMMAND_BUFFER_2_TS_BITS (0xffffull << 16)
485 #define SPU_COMMAND_BUFFER_2_TAG_BITS (0x3full)
486         u64 spu_atomic_status_RW;                               /* 0x5020 */
487 } __attribute__ ((aligned(0x20000)));
488
489 /* SPU Privilege 1 State Area */
490 struct spu_priv1 {
491         /* Control and Configuration Area */
492         u64 mfc_sr1_RW;                                         /* 0x000 */
493 #define MFC_STATE1_LOCAL_STORAGE_DECODE_MASK    0x01ull
494 #define MFC_STATE1_BUS_TLBIE_MASK               0x02ull
495 #define MFC_STATE1_REAL_MODE_OFFSET_ENABLE_MASK 0x04ull
496 #define MFC_STATE1_PROBLEM_STATE_MASK           0x08ull
497 #define MFC_STATE1_RELOCATE_MASK                0x10ull
498 #define MFC_STATE1_MASTER_RUN_CONTROL_MASK      0x20ull
499 #define MFC_STATE1_TABLE_SEARCH_MASK            0x40ull
500         u64 mfc_lpid_RW;                                        /* 0x008 */
501         u64 spu_idr_RW;                                         /* 0x010 */
502         u64 mfc_vr_RO;                                          /* 0x018 */
503 #define MFC_VERSION_BITS                (0xffff << 16)
504 #define MFC_REVISION_BITS               (0xffff)
505 #define MFC_GET_VERSION_BITS(vr)        (((vr) & MFC_VERSION_BITS) >> 16)
506 #define MFC_GET_REVISION_BITS(vr)       ((vr) & MFC_REVISION_BITS)
507         u64 spu_vr_RO;                                          /* 0x020 */
508 #define SPU_VERSION_BITS                (0xffff << 16)
509 #define SPU_REVISION_BITS               (0xffff)
510 #define SPU_GET_VERSION_BITS(vr)        (vr & SPU_VERSION_BITS) >> 16
511 #define SPU_GET_REVISION_BITS(vr)       (vr & SPU_REVISION_BITS)
512         u8  pad_0x28_0x100[0x100 - 0x28];                       /* 0x28 */
513
514         /* Interrupt Area */
515         u64 int_mask_RW[3];                                     /* 0x100 */
516 #define CLASS0_ENABLE_DMA_ALIGNMENT_INTR                0x1L
517 #define CLASS0_ENABLE_INVALID_DMA_COMMAND_INTR          0x2L
518 #define CLASS0_ENABLE_SPU_ERROR_INTR                    0x4L
519 #define CLASS0_ENABLE_MFC_FIR_INTR                      0x8L
520 #define CLASS1_ENABLE_SEGMENT_FAULT_INTR                0x1L
521 #define CLASS1_ENABLE_STORAGE_FAULT_INTR                0x2L
522 #define CLASS1_ENABLE_LS_COMPARE_SUSPEND_ON_GET_INTR    0x4L
523 #define CLASS1_ENABLE_LS_COMPARE_SUSPEND_ON_PUT_INTR    0x8L
524 #define CLASS2_ENABLE_MAILBOX_INTR                      0x1L
525 #define CLASS2_ENABLE_SPU_STOP_INTR                     0x2L
526 #define CLASS2_ENABLE_SPU_HALT_INTR                     0x4L
527 #define CLASS2_ENABLE_SPU_DMA_TAG_GROUP_COMPLETE_INTR   0x8L
528         u8  pad_0x118_0x140[0x28];                              /* 0x118 */
529         u64 int_stat_RW[3];                                     /* 0x140 */
530         u8  pad_0x158_0x180[0x28];                              /* 0x158 */
531         u64 int_route_RW;                                       /* 0x180 */
532
533         /* Interrupt Routing */
534         u8  pad_0x188_0x200[0x200 - 0x188];                     /* 0x188 */
535
536         /* Atomic Unit Control Area */
537         u64 mfc_atomic_flush_RW;                                /* 0x200 */
538 #define mfc_atomic_flush_enable                 0x1L
539         u8  pad_0x208_0x280[0x78];                              /* 0x208 */
540         u64 resource_allocation_groupID_RW;                     /* 0x280 */
541         u64 resource_allocation_enable_RW;                      /* 0x288 */
542         u8  pad_0x290_0x3c8[0x3c8 - 0x290];                     /* 0x290 */
543
544         /* SPU_Cache_ImplRegs: Implementation-dependent cache registers */
545
546         u64 smf_sbi_signal_sel;                                 /* 0x3c8 */
547 #define smf_sbi_mask_lsb        56
548 #define smf_sbi_shift           (63 - smf_sbi_mask_lsb)
549 #define smf_sbi_mask            (0x301LL << smf_sbi_shift)
550 #define smf_sbi_bus0_bits       (0x001LL << smf_sbi_shift)
551 #define smf_sbi_bus2_bits       (0x100LL << smf_sbi_shift)
552 #define smf_sbi2_bus0_bits      (0x201LL << smf_sbi_shift)
553 #define smf_sbi2_bus2_bits      (0x300LL << smf_sbi_shift)
554         u64 smf_ato_signal_sel;                                 /* 0x3d0 */
555 #define smf_ato_mask_lsb        35
556 #define smf_ato_shift           (63 - smf_ato_mask_lsb)
557 #define smf_ato_mask            (0x3LL << smf_ato_shift)
558 #define smf_ato_bus0_bits       (0x2LL << smf_ato_shift)
559 #define smf_ato_bus2_bits       (0x1LL << smf_ato_shift)
560         u8  pad_0x3d8_0x400[0x400 - 0x3d8];                     /* 0x3d8 */
561
562         /* TLB Management Registers */
563         u64 mfc_sdr_RW;                                         /* 0x400 */
564         u8  pad_0x408_0x500[0xf8];                              /* 0x408 */
565         u64 tlb_index_hint_RO;                                  /* 0x500 */
566         u64 tlb_index_W;                                        /* 0x508 */
567         u64 tlb_vpn_RW;                                         /* 0x510 */
568         u64 tlb_rpn_RW;                                         /* 0x518 */
569         u8  pad_0x520_0x540[0x20];                              /* 0x520 */
570         u64 tlb_invalidate_entry_W;                             /* 0x540 */
571         u64 tlb_invalidate_all_W;                               /* 0x548 */
572         u8  pad_0x550_0x580[0x580 - 0x550];                     /* 0x550 */
573
574         /* SPU_MMU_ImplRegs: Implementation-dependent MMU registers */
575         u64 smm_hid;                                            /* 0x580 */
576 #define PAGE_SIZE_MASK          0xf000000000000000ull
577 #define PAGE_SIZE_16MB_64KB     0x2000000000000000ull
578         u8  pad_0x588_0x600[0x600 - 0x588];                     /* 0x588 */
579
580         /* MFC Status/Control Area */
581         u64 mfc_accr_RW;                                        /* 0x600 */
582 #define MFC_ACCR_EA_ACCESS_GET          (1 << 0)
583 #define MFC_ACCR_EA_ACCESS_PUT          (1 << 1)
584 #define MFC_ACCR_LS_ACCESS_GET          (1 << 3)
585 #define MFC_ACCR_LS_ACCESS_PUT          (1 << 4)
586         u8  pad_0x608_0x610[0x8];                               /* 0x608 */
587         u64 mfc_dsisr_RW;                                       /* 0x610 */
588 #define MFC_DSISR_PTE_NOT_FOUND         (1 << 30)
589 #define MFC_DSISR_ACCESS_DENIED         (1 << 27)
590 #define MFC_DSISR_ATOMIC                (1 << 26)
591 #define MFC_DSISR_ACCESS_PUT            (1 << 25)
592 #define MFC_DSISR_ADDR_MATCH            (1 << 22)
593 #define MFC_DSISR_LS                    (1 << 17)
594 #define MFC_DSISR_L                     (1 << 16)
595 #define MFC_DSISR_ADDRESS_OVERFLOW      (1 << 0)
596         u8  pad_0x618_0x620[0x8];                               /* 0x618 */
597         u64 mfc_dar_RW;                                         /* 0x620 */
598         u8  pad_0x628_0x700[0x700 - 0x628];                     /* 0x628 */
599
600         /* Replacement Management Table (RMT) Area */
601         u64 rmt_index_RW;                                       /* 0x700 */
602         u8  pad_0x708_0x710[0x8];                               /* 0x708 */
603         u64 rmt_data1_RW;                                       /* 0x710 */
604         u8  pad_0x718_0x800[0x800 - 0x718];                     /* 0x718 */
605
606         /* Control/Configuration Registers */
607         u64 mfc_dsir_R;                                         /* 0x800 */
608 #define MFC_DSIR_Q                      (1 << 31)
609 #define MFC_DSIR_SPU_QUEUE              MFC_DSIR_Q
610         u64 mfc_lsacr_RW;                                       /* 0x808 */
611 #define MFC_LSACR_COMPARE_MASK          ((~0ull) << 32)
612 #define MFC_LSACR_COMPARE_ADDR          ((~0ull) >> 32)
613         u64 mfc_lscrr_R;                                        /* 0x810 */
614 #define MFC_LSCRR_Q                     (1 << 31)
615 #define MFC_LSCRR_SPU_QUEUE             MFC_LSCRR_Q
616 #define MFC_LSCRR_QI_SHIFT              32
617 #define MFC_LSCRR_QI_MASK               ((~0ull) << MFC_LSCRR_QI_SHIFT)
618         u8  pad_0x818_0x820[0x8];                               /* 0x818 */
619         u64 mfc_tclass_id_RW;                                   /* 0x820 */
620 #define MFC_TCLASS_ID_ENABLE            (1L << 0L)
621 #define MFC_TCLASS_SLOT2_ENABLE         (1L << 5L)
622 #define MFC_TCLASS_SLOT1_ENABLE         (1L << 6L)
623 #define MFC_TCLASS_SLOT0_ENABLE         (1L << 7L)
624 #define MFC_TCLASS_QUOTA_2_SHIFT        8L
625 #define MFC_TCLASS_QUOTA_1_SHIFT        16L
626 #define MFC_TCLASS_QUOTA_0_SHIFT        24L
627 #define MFC_TCLASS_QUOTA_2_MASK         (0x1FL << MFC_TCLASS_QUOTA_2_SHIFT)
628 #define MFC_TCLASS_QUOTA_1_MASK         (0x1FL << MFC_TCLASS_QUOTA_1_SHIFT)
629 #define MFC_TCLASS_QUOTA_0_MASK         (0x1FL << MFC_TCLASS_QUOTA_0_SHIFT)
630         u8  pad_0x828_0x900[0x900 - 0x828];                     /* 0x828 */
631
632         /* Real Mode Support Registers */
633         u64 mfc_rm_boundary;                                    /* 0x900 */
634         u8  pad_0x908_0x938[0x30];                              /* 0x908 */
635         u64 smf_dma_signal_sel;                                 /* 0x938 */
636 #define mfc_dma1_mask_lsb       41
637 #define mfc_dma1_shift          (63 - mfc_dma1_mask_lsb)
638 #define mfc_dma1_mask           (0x3LL << mfc_dma1_shift)
639 #define mfc_dma1_bits           (0x1LL << mfc_dma1_shift)
640 #define mfc_dma2_mask_lsb       43
641 #define mfc_dma2_shift          (63 - mfc_dma2_mask_lsb)
642 #define mfc_dma2_mask           (0x3LL << mfc_dma2_shift)
643 #define mfc_dma2_bits           (0x1LL << mfc_dma2_shift)
644         u8  pad_0x940_0xa38[0xf8];                              /* 0x940 */
645         u64 smm_signal_sel;                                     /* 0xa38 */
646 #define smm_sig_mask_lsb        12
647 #define smm_sig_shift           (63 - smm_sig_mask_lsb)
648 #define smm_sig_mask            (0x3LL << smm_sig_shift)
649 #define smm_sig_bus0_bits       (0x2LL << smm_sig_shift)
650 #define smm_sig_bus2_bits       (0x1LL << smm_sig_shift)
651         u8  pad_0xa40_0xc00[0xc00 - 0xa40];                     /* 0xa40 */
652
653         /* DMA Command Error Area */
654         u64 mfc_cer_R;                                          /* 0xc00 */
655 #define MFC_CER_Q               (1 << 31)
656 #define MFC_CER_SPU_QUEUE       MFC_CER_Q
657         u8  pad_0xc08_0x1000[0x1000 - 0xc08];                   /* 0xc08 */
658
659         /* PV1_ImplRegs: Implementation-dependent privileged-state 1 regs */
660         /* DMA Command Error Area */
661         u64 spu_ecc_cntl_RW;                                    /* 0x1000 */
662 #define SPU_ECC_CNTL_E                  (1ull << 0ull)
663 #define SPU_ECC_CNTL_ENABLE             SPU_ECC_CNTL_E
664 #define SPU_ECC_CNTL_DISABLE            (~SPU_ECC_CNTL_E & 1L)
665 #define SPU_ECC_CNTL_S                  (1ull << 1ull)
666 #define SPU_ECC_STOP_AFTER_ERROR        SPU_ECC_CNTL_S
667 #define SPU_ECC_CONTINUE_AFTER_ERROR    (~SPU_ECC_CNTL_S & 2L)
668 #define SPU_ECC_CNTL_B                  (1ull << 2ull)
669 #define SPU_ECC_BACKGROUND_ENABLE       SPU_ECC_CNTL_B
670 #define SPU_ECC_BACKGROUND_DISABLE      (~SPU_ECC_CNTL_B & 4L)
671 #define SPU_ECC_CNTL_I_SHIFT            3ull
672 #define SPU_ECC_CNTL_I_MASK             (3ull << SPU_ECC_CNTL_I_SHIFT)
673 #define SPU_ECC_WRITE_ALWAYS            (~SPU_ECC_CNTL_I & 12L)
674 #define SPU_ECC_WRITE_CORRECTABLE       (1ull << SPU_ECC_CNTL_I_SHIFT)
675 #define SPU_ECC_WRITE_UNCORRECTABLE     (3ull << SPU_ECC_CNTL_I_SHIFT)
676 #define SPU_ECC_CNTL_D                  (1ull << 5ull)
677 #define SPU_ECC_DETECTION_ENABLE        SPU_ECC_CNTL_D
678 #define SPU_ECC_DETECTION_DISABLE       (~SPU_ECC_CNTL_D & 32L)
679         u64 spu_ecc_stat_RW;                                    /* 0x1008 */
680 #define SPU_ECC_CORRECTED_ERROR         (1ull << 0ul)
681 #define SPU_ECC_UNCORRECTED_ERROR       (1ull << 1ul)
682 #define SPU_ECC_SCRUB_COMPLETE          (1ull << 2ul)
683 #define SPU_ECC_SCRUB_IN_PROGRESS       (1ull << 3ul)
684 #define SPU_ECC_INSTRUCTION_ERROR       (1ull << 4ul)
685 #define SPU_ECC_DATA_ERROR              (1ull << 5ul)
686 #define SPU_ECC_DMA_ERROR               (1ull << 6ul)
687 #define SPU_ECC_STATUS_CNT_MASK         (256ull << 8)
688         u64 spu_ecc_addr_RW;                                    /* 0x1010 */
689         u64 spu_err_mask_RW;                                    /* 0x1018 */
690 #define SPU_ERR_ILLEGAL_INSTR           (1ull << 0ul)
691 #define SPU_ERR_ILLEGAL_CHANNEL         (1ull << 1ul)
692         u8  pad_0x1020_0x1028[0x1028 - 0x1020];                 /* 0x1020 */
693
694         /* SPU Debug-Trace Bus (DTB) Selection Registers */
695         u64 spu_trig0_sel;                                      /* 0x1028 */
696         u64 spu_trig1_sel;                                      /* 0x1030 */
697         u64 spu_trig2_sel;                                      /* 0x1038 */
698         u64 spu_trig3_sel;                                      /* 0x1040 */
699         u64 spu_trace_sel;                                      /* 0x1048 */
700 #define spu_trace_sel_mask              0x1f1fLL
701 #define spu_trace_sel_bus0_bits         0x1000LL
702 #define spu_trace_sel_bus2_bits         0x0010LL
703         u64 spu_event0_sel;                                     /* 0x1050 */
704         u64 spu_event1_sel;                                     /* 0x1058 */
705         u64 spu_event2_sel;                                     /* 0x1060 */
706         u64 spu_event3_sel;                                     /* 0x1068 */
707         u64 spu_trace_cntl;                                     /* 0x1070 */
708 } __attribute__ ((aligned(0x2000)));
709
710 #endif /* __KERNEL__ */
711 #endif