[IA64] Add ACPI based P-state support
[linux-2.6.git] / include / asm-ia64 / pal.h
1 #ifndef _ASM_IA64_PAL_H
2 #define _ASM_IA64_PAL_H
3
4 /*
5  * Processor Abstraction Layer definitions.
6  *
7  * This is based on Intel IA-64 Architecture Software Developer's Manual rev 1.0
8  * chapter 11 IA-64 Processor Abstraction Layer
9  *
10  * Copyright (C) 1998-2001 Hewlett-Packard Co
11  *      David Mosberger-Tang <davidm@hpl.hp.com>
12  *      Stephane Eranian <eranian@hpl.hp.com>
13  * Copyright (C) 1999 VA Linux Systems
14  * Copyright (C) 1999 Walt Drummond <drummond@valinux.com>
15  * Copyright (C) 1999 Srinivasa Prasad Thirumalachar <sprasad@sprasad.engr.sgi.com>
16  *
17  * 99/10/01     davidm  Make sure we pass zero for reserved parameters.
18  * 00/03/07     davidm  Updated pal_cache_flush() to be in sync with PAL v2.6.
19  * 00/03/23     cfleck  Modified processor min-state save area to match updated PAL & SAL info
20  * 00/05/24     eranian Updated to latest PAL spec, fix structures bugs, added
21  * 00/05/25     eranian Support for stack calls, and static physical calls
22  * 00/06/18     eranian Support for stacked physical calls
23  */
24
25 /*
26  * Note that some of these calls use a static-register only calling
27  * convention which has nothing to do with the regular calling
28  * convention.
29  */
30 #define PAL_CACHE_FLUSH         1       /* flush i/d cache */
31 #define PAL_CACHE_INFO          2       /* get detailed i/d cache info */
32 #define PAL_CACHE_INIT          3       /* initialize i/d cache */
33 #define PAL_CACHE_SUMMARY       4       /* get summary of cache heirarchy */
34 #define PAL_MEM_ATTRIB          5       /* list supported memory attributes */
35 #define PAL_PTCE_INFO           6       /* purge TLB info */
36 #define PAL_VM_INFO             7       /* return supported virtual memory features */
37 #define PAL_VM_SUMMARY          8       /* return summary on supported vm features */
38 #define PAL_BUS_GET_FEATURES    9       /* return processor bus interface features settings */
39 #define PAL_BUS_SET_FEATURES    10      /* set processor bus features */
40 #define PAL_DEBUG_INFO          11      /* get number of debug registers */
41 #define PAL_FIXED_ADDR          12      /* get fixed component of processors's directed address */
42 #define PAL_FREQ_BASE           13      /* base frequency of the platform */
43 #define PAL_FREQ_RATIOS         14      /* ratio of processor, bus and ITC frequency */
44 #define PAL_PERF_MON_INFO       15      /* return performance monitor info */
45 #define PAL_PLATFORM_ADDR       16      /* set processor interrupt block and IO port space addr */
46 #define PAL_PROC_GET_FEATURES   17      /* get configurable processor features & settings */
47 #define PAL_PROC_SET_FEATURES   18      /* enable/disable configurable processor features */
48 #define PAL_RSE_INFO            19      /* return rse information */
49 #define PAL_VERSION             20      /* return version of PAL code */
50 #define PAL_MC_CLEAR_LOG        21      /* clear all processor log info */
51 #define PAL_MC_DRAIN            22      /* drain operations which could result in an MCA */
52 #define PAL_MC_EXPECTED         23      /* set/reset expected MCA indicator */
53 #define PAL_MC_DYNAMIC_STATE    24      /* get processor dynamic state */
54 #define PAL_MC_ERROR_INFO       25      /* get processor MCA info and static state */
55 #define PAL_MC_RESUME           26      /* Return to interrupted process */
56 #define PAL_MC_REGISTER_MEM     27      /* Register memory for PAL to use during MCAs and inits */
57 #define PAL_HALT                28      /* enter the low power HALT state */
58 #define PAL_HALT_LIGHT          29      /* enter the low power light halt state*/
59 #define PAL_COPY_INFO           30      /* returns info needed to relocate PAL */
60 #define PAL_CACHE_LINE_INIT     31      /* init tags & data of cache line */
61 #define PAL_PMI_ENTRYPOINT      32      /* register PMI memory entry points with the processor */
62 #define PAL_ENTER_IA_32_ENV     33      /* enter IA-32 system environment */
63 #define PAL_VM_PAGE_SIZE        34      /* return vm TC and page walker page sizes */
64
65 #define PAL_MEM_FOR_TEST        37      /* get amount of memory needed for late processor test */
66 #define PAL_CACHE_PROT_INFO     38      /* get i/d cache protection info */
67 #define PAL_REGISTER_INFO       39      /* return AR and CR register information*/
68 #define PAL_SHUTDOWN            40      /* enter processor shutdown state */
69 #define PAL_PREFETCH_VISIBILITY 41      /* Make Processor Prefetches Visible */
70 #define PAL_LOGICAL_TO_PHYSICAL 42      /* returns information on logical to physical processor mapping */
71
72 #define PAL_COPY_PAL            256     /* relocate PAL procedures and PAL PMI */
73 #define PAL_HALT_INFO           257     /* return the low power capabilities of processor */
74 #define PAL_TEST_PROC           258     /* perform late processor self-test */
75 #define PAL_CACHE_READ          259     /* read tag & data of cacheline for diagnostic testing */
76 #define PAL_CACHE_WRITE         260     /* write tag & data of cacheline for diagnostic testing */
77 #define PAL_VM_TR_READ          261     /* read contents of translation register */
78 #define PAL_GET_PSTATE          262     /* get the current P-state */
79 #define PAL_SET_PSTATE          263     /* set the P-state */
80
81 #ifndef __ASSEMBLY__
82
83 #include <linux/types.h>
84 #include <asm/fpu.h>
85
86 /*
87  * Data types needed to pass information into PAL procedures and
88  * interpret information returned by them.
89  */
90
91 /* Return status from the PAL procedure */
92 typedef s64                             pal_status_t;
93
94 #define PAL_STATUS_SUCCESS              0       /* No error */
95 #define PAL_STATUS_UNIMPLEMENTED        (-1)    /* Unimplemented procedure */
96 #define PAL_STATUS_EINVAL               (-2)    /* Invalid argument */
97 #define PAL_STATUS_ERROR                (-3)    /* Error */
98 #define PAL_STATUS_CACHE_INIT_FAIL      (-4)    /* Could not initialize the
99                                                  * specified level and type of
100                                                  * cache without sideeffects
101                                                  * and "restrict" was 1
102                                                  */
103
104 /* Processor cache level in the heirarchy */
105 typedef u64                             pal_cache_level_t;
106 #define PAL_CACHE_LEVEL_L0              0       /* L0 */
107 #define PAL_CACHE_LEVEL_L1              1       /* L1 */
108 #define PAL_CACHE_LEVEL_L2              2       /* L2 */
109
110
111 /* Processor cache type at a particular level in the heirarchy */
112
113 typedef u64                             pal_cache_type_t;
114 #define PAL_CACHE_TYPE_INSTRUCTION      1       /* Instruction cache */
115 #define PAL_CACHE_TYPE_DATA             2       /* Data or unified cache */
116 #define PAL_CACHE_TYPE_INSTRUCTION_DATA 3       /* Both Data & Instruction */
117
118
119 #define PAL_CACHE_FLUSH_INVALIDATE      1       /* Invalidate clean lines */
120 #define PAL_CACHE_FLUSH_CHK_INTRS       2       /* check for interrupts/mc while flushing */
121
122 /* Processor cache line size in bytes  */
123 typedef int                             pal_cache_line_size_t;
124
125 /* Processor cache line state */
126 typedef u64                             pal_cache_line_state_t;
127 #define PAL_CACHE_LINE_STATE_INVALID    0       /* Invalid */
128 #define PAL_CACHE_LINE_STATE_SHARED     1       /* Shared */
129 #define PAL_CACHE_LINE_STATE_EXCLUSIVE  2       /* Exclusive */
130 #define PAL_CACHE_LINE_STATE_MODIFIED   3       /* Modified */
131
132 typedef struct pal_freq_ratio {
133         u64 den : 32, num : 32; /* numerator & denominator */
134 } itc_ratio, proc_ratio;
135
136 typedef union  pal_cache_config_info_1_s {
137         struct {
138                 u64             u               : 1,    /* 0 Unified cache ? */
139                                 at              : 2,    /* 2-1 Cache mem attr*/
140                                 reserved        : 5,    /* 7-3 Reserved */
141                                 associativity   : 8,    /* 16-8 Associativity*/
142                                 line_size       : 8,    /* 23-17 Line size */
143                                 stride          : 8,    /* 31-24 Stride */
144                                 store_latency   : 8,    /*39-32 Store latency*/
145                                 load_latency    : 8,    /* 47-40 Load latency*/
146                                 store_hints     : 8,    /* 55-48 Store hints*/
147                                 load_hints      : 8;    /* 63-56 Load hints */
148         } pcci1_bits;
149         u64                     pcci1_data;
150 } pal_cache_config_info_1_t;
151
152 typedef union  pal_cache_config_info_2_s {
153         struct {
154                 u64             cache_size      : 32,   /*cache size in bytes*/
155
156
157                                 alias_boundary  : 8,    /* 39-32 aliased addr
158                                                          * separation for max
159                                                          * performance.
160                                                          */
161                                 tag_ls_bit      : 8,    /* 47-40 LSb of addr*/
162                                 tag_ms_bit      : 8,    /* 55-48 MSb of addr*/
163                                 reserved        : 8;    /* 63-56 Reserved */
164         } pcci2_bits;
165         u64                     pcci2_data;
166 } pal_cache_config_info_2_t;
167
168
169 typedef struct pal_cache_config_info_s {
170         pal_status_t                    pcci_status;
171         pal_cache_config_info_1_t       pcci_info_1;
172         pal_cache_config_info_2_t       pcci_info_2;
173         u64                             pcci_reserved;
174 } pal_cache_config_info_t;
175
176 #define pcci_ld_hints           pcci_info_1.pcci1_bits.load_hints
177 #define pcci_st_hints           pcci_info_1.pcci1_bits.store_hints
178 #define pcci_ld_latency         pcci_info_1.pcci1_bits.load_latency
179 #define pcci_st_latency         pcci_info_1.pcci1_bits.store_latency
180 #define pcci_stride             pcci_info_1.pcci1_bits.stride
181 #define pcci_line_size          pcci_info_1.pcci1_bits.line_size
182 #define pcci_assoc              pcci_info_1.pcci1_bits.associativity
183 #define pcci_cache_attr         pcci_info_1.pcci1_bits.at
184 #define pcci_unified            pcci_info_1.pcci1_bits.u
185 #define pcci_tag_msb            pcci_info_2.pcci2_bits.tag_ms_bit
186 #define pcci_tag_lsb            pcci_info_2.pcci2_bits.tag_ls_bit
187 #define pcci_alias_boundary     pcci_info_2.pcci2_bits.alias_boundary
188 #define pcci_cache_size         pcci_info_2.pcci2_bits.cache_size
189
190
191
192 /* Possible values for cache attributes */
193
194 #define PAL_CACHE_ATTR_WT               0       /* Write through cache */
195 #define PAL_CACHE_ATTR_WB               1       /* Write back cache */
196 #define PAL_CACHE_ATTR_WT_OR_WB         2       /* Either write thru or write
197                                                  * back depending on TLB
198                                                  * memory attributes
199                                                  */
200
201
202 /* Possible values for cache hints */
203
204 #define PAL_CACHE_HINT_TEMP_1           0       /* Temporal level 1 */
205 #define PAL_CACHE_HINT_NTEMP_1          1       /* Non-temporal level 1 */
206 #define PAL_CACHE_HINT_NTEMP_ALL        3       /* Non-temporal all levels */
207
208 /* Processor cache protection  information */
209 typedef union pal_cache_protection_element_u {
210         u32                     pcpi_data;
211         struct {
212                 u32             data_bits       : 8, /* # data bits covered by
213                                                       * each unit of protection
214                                                       */
215
216                                 tagprot_lsb     : 6, /* Least -do- */
217                                 tagprot_msb     : 6, /* Most Sig. tag address
218                                                       * bit that this
219                                                       * protection covers.
220                                                       */
221                                 prot_bits       : 6, /* # of protection bits */
222                                 method          : 4, /* Protection method */
223                                 t_d             : 2; /* Indicates which part
224                                                       * of the cache this
225                                                       * protection encoding
226                                                       * applies.
227                                                       */
228         } pcp_info;
229 } pal_cache_protection_element_t;
230
231 #define pcpi_cache_prot_part    pcp_info.t_d
232 #define pcpi_prot_method        pcp_info.method
233 #define pcpi_prot_bits          pcp_info.prot_bits
234 #define pcpi_tagprot_msb        pcp_info.tagprot_msb
235 #define pcpi_tagprot_lsb        pcp_info.tagprot_lsb
236 #define pcpi_data_bits          pcp_info.data_bits
237
238 /* Processor cache part encodings */
239 #define PAL_CACHE_PROT_PART_DATA        0       /* Data protection  */
240 #define PAL_CACHE_PROT_PART_TAG         1       /* Tag  protection */
241 #define PAL_CACHE_PROT_PART_TAG_DATA    2       /* Tag+data protection (tag is
242                                                  * more significant )
243                                                  */
244 #define PAL_CACHE_PROT_PART_DATA_TAG    3       /* Data+tag protection (data is
245                                                  * more significant )
246                                                  */
247 #define PAL_CACHE_PROT_PART_MAX         6
248
249
250 typedef struct pal_cache_protection_info_s {
251         pal_status_t                    pcpi_status;
252         pal_cache_protection_element_t  pcp_info[PAL_CACHE_PROT_PART_MAX];
253 } pal_cache_protection_info_t;
254
255
256 /* Processor cache protection method encodings */
257 #define PAL_CACHE_PROT_METHOD_NONE              0       /* No protection */
258 #define PAL_CACHE_PROT_METHOD_ODD_PARITY        1       /* Odd parity */
259 #define PAL_CACHE_PROT_METHOD_EVEN_PARITY       2       /* Even parity */
260 #define PAL_CACHE_PROT_METHOD_ECC               3       /* ECC protection */
261
262
263 /* Processor cache line identification in the heirarchy */
264 typedef union pal_cache_line_id_u {
265         u64                     pclid_data;
266         struct {
267                 u64             cache_type      : 8,    /* 7-0 cache type */
268                                 level           : 8,    /* 15-8 level of the
269                                                          * cache in the
270                                                          * heirarchy.
271                                                          */
272                                 way             : 8,    /* 23-16 way in the set
273                                                          */
274                                 part            : 8,    /* 31-24 part of the
275                                                          * cache
276                                                          */
277                                 reserved        : 32;   /* 63-32 is reserved*/
278         } pclid_info_read;
279         struct {
280                 u64             cache_type      : 8,    /* 7-0 cache type */
281                                 level           : 8,    /* 15-8 level of the
282                                                          * cache in the
283                                                          * heirarchy.
284                                                          */
285                                 way             : 8,    /* 23-16 way in the set
286                                                          */
287                                 part            : 8,    /* 31-24 part of the
288                                                          * cache
289                                                          */
290                                 mesi            : 8,    /* 39-32 cache line
291                                                          * state
292                                                          */
293                                 start           : 8,    /* 47-40 lsb of data to
294                                                          * invert
295                                                          */
296                                 length          : 8,    /* 55-48 #bits to
297                                                          * invert
298                                                          */
299                                 trigger         : 8;    /* 63-56 Trigger error
300                                                          * by doing a load
301                                                          * after the write
302                                                          */
303
304         } pclid_info_write;
305 } pal_cache_line_id_u_t;
306
307 #define pclid_read_part         pclid_info_read.part
308 #define pclid_read_way          pclid_info_read.way
309 #define pclid_read_level        pclid_info_read.level
310 #define pclid_read_cache_type   pclid_info_read.cache_type
311
312 #define pclid_write_trigger     pclid_info_write.trigger
313 #define pclid_write_length      pclid_info_write.length
314 #define pclid_write_start       pclid_info_write.start
315 #define pclid_write_mesi        pclid_info_write.mesi
316 #define pclid_write_part        pclid_info_write.part
317 #define pclid_write_way         pclid_info_write.way
318 #define pclid_write_level       pclid_info_write.level
319 #define pclid_write_cache_type  pclid_info_write.cache_type
320
321 /* Processor cache line part encodings */
322 #define PAL_CACHE_LINE_ID_PART_DATA             0       /* Data */
323 #define PAL_CACHE_LINE_ID_PART_TAG              1       /* Tag */
324 #define PAL_CACHE_LINE_ID_PART_DATA_PROT        2       /* Data protection */
325 #define PAL_CACHE_LINE_ID_PART_TAG_PROT         3       /* Tag protection */
326 #define PAL_CACHE_LINE_ID_PART_DATA_TAG_PROT    4       /* Data+tag
327                                                          * protection
328                                                          */
329 typedef struct pal_cache_line_info_s {
330         pal_status_t            pcli_status;            /* Return status of the read cache line
331                                                          * info call.
332                                                          */
333         u64                     pcli_data;              /* 64-bit data, tag, protection bits .. */
334         u64                     pcli_data_len;          /* data length in bits */
335         pal_cache_line_state_t  pcli_cache_line_state;  /* mesi state */
336
337 } pal_cache_line_info_t;
338
339
340 /* Machine Check related crap */
341
342 /* Pending event status bits  */
343 typedef u64                                     pal_mc_pending_events_t;
344
345 #define PAL_MC_PENDING_MCA                      (1 << 0)
346 #define PAL_MC_PENDING_INIT                     (1 << 1)
347
348 /* Error information type */
349 typedef u64                                     pal_mc_info_index_t;
350
351 #define PAL_MC_INFO_PROCESSOR                   0       /* Processor */
352 #define PAL_MC_INFO_CACHE_CHECK                 1       /* Cache check */
353 #define PAL_MC_INFO_TLB_CHECK                   2       /* Tlb check */
354 #define PAL_MC_INFO_BUS_CHECK                   3       /* Bus check */
355 #define PAL_MC_INFO_REQ_ADDR                    4       /* Requestor address */
356 #define PAL_MC_INFO_RESP_ADDR                   5       /* Responder address */
357 #define PAL_MC_INFO_TARGET_ADDR                 6       /* Target address */
358 #define PAL_MC_INFO_IMPL_DEP                    7       /* Implementation
359                                                          * dependent
360                                                          */
361
362
363 typedef struct pal_process_state_info_s {
364         u64             reserved1       : 2,
365                         rz              : 1,    /* PAL_CHECK processor
366                                                  * rendezvous
367                                                  * successful.
368                                                  */
369
370                         ra              : 1,    /* PAL_CHECK attempted
371                                                  * a rendezvous.
372                                                  */
373                         me              : 1,    /* Distinct multiple
374                                                  * errors occurred
375                                                  */
376
377                         mn              : 1,    /* Min. state save
378                                                  * area has been
379                                                  * registered with PAL
380                                                  */
381
382                         sy              : 1,    /* Storage integrity
383                                                  * synched
384                                                  */
385
386
387                         co              : 1,    /* Continuable */
388                         ci              : 1,    /* MC isolated */
389                         us              : 1,    /* Uncontained storage
390                                                  * damage.
391                                                  */
392
393
394                         hd              : 1,    /* Non-essential hw
395                                                  * lost (no loss of
396                                                  * functionality)
397                                                  * causing the
398                                                  * processor to run in
399                                                  * degraded mode.
400                                                  */
401
402                         tl              : 1,    /* 1 => MC occurred
403                                                  * after an instr was
404                                                  * executed but before
405                                                  * the trap that
406                                                  * resulted from instr
407                                                  * execution was
408                                                  * generated.
409                                                  * (Trap Lost )
410                                                  */
411                         mi              : 1,    /* More information available
412                                                  * call PAL_MC_ERROR_INFO
413                                                  */
414                         pi              : 1,    /* Precise instruction pointer */
415                         pm              : 1,    /* Precise min-state save area */
416
417                         dy              : 1,    /* Processor dynamic
418                                                  * state valid
419                                                  */
420
421
422                         in              : 1,    /* 0 = MC, 1 = INIT */
423                         rs              : 1,    /* RSE valid */
424                         cm              : 1,    /* MC corrected */
425                         ex              : 1,    /* MC is expected */
426                         cr              : 1,    /* Control regs valid*/
427                         pc              : 1,    /* Perf cntrs valid */
428                         dr              : 1,    /* Debug regs valid */
429                         tr              : 1,    /* Translation regs
430                                                  * valid
431                                                  */
432                         rr              : 1,    /* Region regs valid */
433                         ar              : 1,    /* App regs valid */
434                         br              : 1,    /* Branch regs valid */
435                         pr              : 1,    /* Predicate registers
436                                                  * valid
437                                                  */
438
439                         fp              : 1,    /* fp registers valid*/
440                         b1              : 1,    /* Preserved bank one
441                                                  * general registers
442                                                  * are valid
443                                                  */
444                         b0              : 1,    /* Preserved bank zero
445                                                  * general registers
446                                                  * are valid
447                                                  */
448                         gr              : 1,    /* General registers
449                                                  * are valid
450                                                  * (excl. banked regs)
451                                                  */
452                         dsize           : 16,   /* size of dynamic
453                                                  * state returned
454                                                  * by the processor
455                                                  */
456
457                         reserved2       : 11,
458                         cc              : 1,    /* Cache check */
459                         tc              : 1,    /* TLB check */
460                         bc              : 1,    /* Bus check */
461                         rc              : 1,    /* Register file check */
462                         uc              : 1;    /* Uarch check */
463
464 } pal_processor_state_info_t;
465
466 typedef struct pal_cache_check_info_s {
467         u64             op              : 4,    /* Type of cache
468                                                  * operation that
469                                                  * caused the machine
470                                                  * check.
471                                                  */
472                         level           : 2,    /* Cache level */
473                         reserved1       : 2,
474                         dl              : 1,    /* Failure in data part
475                                                  * of cache line
476                                                  */
477                         tl              : 1,    /* Failure in tag part
478                                                  * of cache line
479                                                  */
480                         dc              : 1,    /* Failure in dcache */
481                         ic              : 1,    /* Failure in icache */
482                         mesi            : 3,    /* Cache line state */
483                         mv              : 1,    /* mesi valid */
484                         way             : 5,    /* Way in which the
485                                                  * error occurred
486                                                  */
487                         wiv             : 1,    /* Way field valid */
488                         reserved2       : 10,
489
490                         index           : 20,   /* Cache line index */
491                         reserved3       : 2,
492
493                         is              : 1,    /* instruction set (1 == ia32) */
494                         iv              : 1,    /* instruction set field valid */
495                         pl              : 2,    /* privilege level */
496                         pv              : 1,    /* privilege level field valid */
497                         mcc             : 1,    /* Machine check corrected */
498                         tv              : 1,    /* Target address
499                                                  * structure is valid
500                                                  */
501                         rq              : 1,    /* Requester identifier
502                                                  * structure is valid
503                                                  */
504                         rp              : 1,    /* Responder identifier
505                                                  * structure is valid
506                                                  */
507                         pi              : 1;    /* Precise instruction pointer
508                                                  * structure is valid
509                                                  */
510 } pal_cache_check_info_t;
511
512 typedef struct pal_tlb_check_info_s {
513
514         u64             tr_slot         : 8,    /* Slot# of TR where
515                                                  * error occurred
516                                                  */
517                         trv             : 1,    /* tr_slot field is valid */
518                         reserved1       : 1,
519                         level           : 2,    /* TLB level where failure occurred */
520                         reserved2       : 4,
521                         dtr             : 1,    /* Fail in data TR */
522                         itr             : 1,    /* Fail in inst TR */
523                         dtc             : 1,    /* Fail in data TC */
524                         itc             : 1,    /* Fail in inst. TC */
525                         op              : 4,    /* Cache operation */
526                         reserved3       : 30,
527
528                         is              : 1,    /* instruction set (1 == ia32) */
529                         iv              : 1,    /* instruction set field valid */
530                         pl              : 2,    /* privilege level */
531                         pv              : 1,    /* privilege level field valid */
532                         mcc             : 1,    /* Machine check corrected */
533                         tv              : 1,    /* Target address
534                                                  * structure is valid
535                                                  */
536                         rq              : 1,    /* Requester identifier
537                                                  * structure is valid
538                                                  */
539                         rp              : 1,    /* Responder identifier
540                                                  * structure is valid
541                                                  */
542                         pi              : 1;    /* Precise instruction pointer
543                                                  * structure is valid
544                                                  */
545 } pal_tlb_check_info_t;
546
547 typedef struct pal_bus_check_info_s {
548         u64             size            : 5,    /* Xaction size */
549                         ib              : 1,    /* Internal bus error */
550                         eb              : 1,    /* External bus error */
551                         cc              : 1,    /* Error occurred
552                                                  * during cache-cache
553                                                  * transfer.
554                                                  */
555                         type            : 8,    /* Bus xaction type*/
556                         sev             : 5,    /* Bus error severity*/
557                         hier            : 2,    /* Bus hierarchy level */
558                         reserved1       : 1,
559                         bsi             : 8,    /* Bus error status
560                                                  * info
561                                                  */
562                         reserved2       : 22,
563
564                         is              : 1,    /* instruction set (1 == ia32) */
565                         iv              : 1,    /* instruction set field valid */
566                         pl              : 2,    /* privilege level */
567                         pv              : 1,    /* privilege level field valid */
568                         mcc             : 1,    /* Machine check corrected */
569                         tv              : 1,    /* Target address
570                                                  * structure is valid
571                                                  */
572                         rq              : 1,    /* Requester identifier
573                                                  * structure is valid
574                                                  */
575                         rp              : 1,    /* Responder identifier
576                                                  * structure is valid
577                                                  */
578                         pi              : 1;    /* Precise instruction pointer
579                                                  * structure is valid
580                                                  */
581 } pal_bus_check_info_t;
582
583 typedef struct pal_reg_file_check_info_s {
584         u64             id              : 4,    /* Register file identifier */
585                         op              : 4,    /* Type of register
586                                                  * operation that
587                                                  * caused the machine
588                                                  * check.
589                                                  */
590                         reg_num         : 7,    /* Register number */
591                         rnv             : 1,    /* reg_num valid */
592                         reserved2       : 38,
593
594                         is              : 1,    /* instruction set (1 == ia32) */
595                         iv              : 1,    /* instruction set field valid */
596                         pl              : 2,    /* privilege level */
597                         pv              : 1,    /* privilege level field valid */
598                         mcc             : 1,    /* Machine check corrected */
599                         reserved3       : 3,
600                         pi              : 1;    /* Precise instruction pointer
601                                                  * structure is valid
602                                                  */
603 } pal_reg_file_check_info_t;
604
605 typedef struct pal_uarch_check_info_s {
606         u64             sid             : 5,    /* Structure identification */
607                         level           : 3,    /* Level of failure */
608                         array_id        : 4,    /* Array identification */
609                         op              : 4,    /* Type of
610                                                  * operation that
611                                                  * caused the machine
612                                                  * check.
613                                                  */
614                         way             : 6,    /* Way of structure */
615                         wv              : 1,    /* way valid */
616                         xv              : 1,    /* index valid */
617                         reserved1       : 8,
618                         index           : 8,    /* Index or set of the uarch
619                                                  * structure that failed.
620                                                  */
621                         reserved2       : 24,
622
623                         is              : 1,    /* instruction set (1 == ia32) */
624                         iv              : 1,    /* instruction set field valid */
625                         pl              : 2,    /* privilege level */
626                         pv              : 1,    /* privilege level field valid */
627                         mcc             : 1,    /* Machine check corrected */
628                         tv              : 1,    /* Target address
629                                                  * structure is valid
630                                                  */
631                         rq              : 1,    /* Requester identifier
632                                                  * structure is valid
633                                                  */
634                         rp              : 1,    /* Responder identifier
635                                                  * structure is valid
636                                                  */
637                         pi              : 1;    /* Precise instruction pointer
638                                                  * structure is valid
639                                                  */
640 } pal_uarch_check_info_t;
641
642 typedef union pal_mc_error_info_u {
643         u64                             pmei_data;
644         pal_processor_state_info_t      pme_processor;
645         pal_cache_check_info_t          pme_cache;
646         pal_tlb_check_info_t            pme_tlb;
647         pal_bus_check_info_t            pme_bus;
648         pal_reg_file_check_info_t       pme_reg_file;
649         pal_uarch_check_info_t          pme_uarch;
650 } pal_mc_error_info_t;
651
652 #define pmci_proc_unknown_check                 pme_processor.uc
653 #define pmci_proc_bus_check                     pme_processor.bc
654 #define pmci_proc_tlb_check                     pme_processor.tc
655 #define pmci_proc_cache_check                   pme_processor.cc
656 #define pmci_proc_dynamic_state_size            pme_processor.dsize
657 #define pmci_proc_gpr_valid                     pme_processor.gr
658 #define pmci_proc_preserved_bank0_gpr_valid     pme_processor.b0
659 #define pmci_proc_preserved_bank1_gpr_valid     pme_processor.b1
660 #define pmci_proc_fp_valid                      pme_processor.fp
661 #define pmci_proc_predicate_regs_valid          pme_processor.pr
662 #define pmci_proc_branch_regs_valid             pme_processor.br
663 #define pmci_proc_app_regs_valid                pme_processor.ar
664 #define pmci_proc_region_regs_valid             pme_processor.rr
665 #define pmci_proc_translation_regs_valid        pme_processor.tr
666 #define pmci_proc_debug_regs_valid              pme_processor.dr
667 #define pmci_proc_perf_counters_valid           pme_processor.pc
668 #define pmci_proc_control_regs_valid            pme_processor.cr
669 #define pmci_proc_machine_check_expected        pme_processor.ex
670 #define pmci_proc_machine_check_corrected       pme_processor.cm
671 #define pmci_proc_rse_valid                     pme_processor.rs
672 #define pmci_proc_machine_check_or_init         pme_processor.in
673 #define pmci_proc_dynamic_state_valid           pme_processor.dy
674 #define pmci_proc_operation                     pme_processor.op
675 #define pmci_proc_trap_lost                     pme_processor.tl
676 #define pmci_proc_hardware_damage               pme_processor.hd
677 #define pmci_proc_uncontained_storage_damage    pme_processor.us
678 #define pmci_proc_machine_check_isolated        pme_processor.ci
679 #define pmci_proc_continuable                   pme_processor.co
680 #define pmci_proc_storage_intergrity_synced     pme_processor.sy
681 #define pmci_proc_min_state_save_area_regd      pme_processor.mn
682 #define pmci_proc_distinct_multiple_errors      pme_processor.me
683 #define pmci_proc_pal_attempted_rendezvous      pme_processor.ra
684 #define pmci_proc_pal_rendezvous_complete       pme_processor.rz
685
686
687 #define pmci_cache_level                        pme_cache.level
688 #define pmci_cache_line_state                   pme_cache.mesi
689 #define pmci_cache_line_state_valid             pme_cache.mv
690 #define pmci_cache_line_index                   pme_cache.index
691 #define pmci_cache_instr_cache_fail             pme_cache.ic
692 #define pmci_cache_data_cache_fail              pme_cache.dc
693 #define pmci_cache_line_tag_fail                pme_cache.tl
694 #define pmci_cache_line_data_fail               pme_cache.dl
695 #define pmci_cache_operation                    pme_cache.op
696 #define pmci_cache_way_valid                    pme_cache.wv
697 #define pmci_cache_target_address_valid         pme_cache.tv
698 #define pmci_cache_way                          pme_cache.way
699 #define pmci_cache_mc                           pme_cache.mc
700
701 #define pmci_tlb_instr_translation_cache_fail   pme_tlb.itc
702 #define pmci_tlb_data_translation_cache_fail    pme_tlb.dtc
703 #define pmci_tlb_instr_translation_reg_fail     pme_tlb.itr
704 #define pmci_tlb_data_translation_reg_fail      pme_tlb.dtr
705 #define pmci_tlb_translation_reg_slot           pme_tlb.tr_slot
706 #define pmci_tlb_mc                             pme_tlb.mc
707
708 #define pmci_bus_status_info                    pme_bus.bsi
709 #define pmci_bus_req_address_valid              pme_bus.rq
710 #define pmci_bus_resp_address_valid             pme_bus.rp
711 #define pmci_bus_target_address_valid           pme_bus.tv
712 #define pmci_bus_error_severity                 pme_bus.sev
713 #define pmci_bus_transaction_type               pme_bus.type
714 #define pmci_bus_cache_cache_transfer           pme_bus.cc
715 #define pmci_bus_transaction_size               pme_bus.size
716 #define pmci_bus_internal_error                 pme_bus.ib
717 #define pmci_bus_external_error                 pme_bus.eb
718 #define pmci_bus_mc                             pme_bus.mc
719
720 /*
721  * NOTE: this min_state_save area struct only includes the 1KB
722  * architectural state save area.  The other 3 KB is scratch space
723  * for PAL.
724  */
725
726 typedef struct pal_min_state_area_s {
727         u64     pmsa_nat_bits;          /* nat bits for saved GRs  */
728         u64     pmsa_gr[15];            /* GR1  - GR15             */
729         u64     pmsa_bank0_gr[16];      /* GR16 - GR31             */
730         u64     pmsa_bank1_gr[16];      /* GR16 - GR31             */
731         u64     pmsa_pr;                /* predicate registers     */
732         u64     pmsa_br0;               /* branch register 0       */
733         u64     pmsa_rsc;               /* ar.rsc                  */
734         u64     pmsa_iip;               /* cr.iip                  */
735         u64     pmsa_ipsr;              /* cr.ipsr                 */
736         u64     pmsa_ifs;               /* cr.ifs                  */
737         u64     pmsa_xip;               /* previous iip            */
738         u64     pmsa_xpsr;              /* previous psr            */
739         u64     pmsa_xfs;               /* previous ifs            */
740         u64     pmsa_br1;               /* branch register 1       */
741         u64     pmsa_reserved[70];      /* pal_min_state_area should total to 1KB */
742 } pal_min_state_area_t;
743
744
745 struct ia64_pal_retval {
746         /*
747          * A zero status value indicates call completed without error.
748          * A negative status value indicates reason of call failure.
749          * A positive status value indicates success but an
750          * informational value should be printed (e.g., "reboot for
751          * change to take effect").
752          */
753         s64 status;
754         u64 v0;
755         u64 v1;
756         u64 v2;
757 };
758
759 /*
760  * Note: Currently unused PAL arguments are generally labeled
761  * "reserved" so the value specified in the PAL documentation
762  * (generally 0) MUST be passed.  Reserved parameters are not optional
763  * parameters.
764  */
765 extern struct ia64_pal_retval ia64_pal_call_static (u64, u64, u64, u64, u64);
766 extern struct ia64_pal_retval ia64_pal_call_stacked (u64, u64, u64, u64);
767 extern struct ia64_pal_retval ia64_pal_call_phys_static (u64, u64, u64, u64);
768 extern struct ia64_pal_retval ia64_pal_call_phys_stacked (u64, u64, u64, u64);
769 extern void ia64_save_scratch_fpregs (struct ia64_fpreg *);
770 extern void ia64_load_scratch_fpregs (struct ia64_fpreg *);
771
772 #define PAL_CALL(iprv,a0,a1,a2,a3) do {                 \
773         struct ia64_fpreg fr[6];                        \
774         ia64_save_scratch_fpregs(fr);                   \
775         iprv = ia64_pal_call_static(a0, a1, a2, a3, 0); \
776         ia64_load_scratch_fpregs(fr);                   \
777 } while (0)
778
779 #define PAL_CALL_IC_OFF(iprv,a0,a1,a2,a3) do {          \
780         struct ia64_fpreg fr[6];                        \
781         ia64_save_scratch_fpregs(fr);                   \
782         iprv = ia64_pal_call_static(a0, a1, a2, a3, 1); \
783         ia64_load_scratch_fpregs(fr);                   \
784 } while (0)
785
786 #define PAL_CALL_STK(iprv,a0,a1,a2,a3) do {             \
787         struct ia64_fpreg fr[6];                        \
788         ia64_save_scratch_fpregs(fr);                   \
789         iprv = ia64_pal_call_stacked(a0, a1, a2, a3);   \
790         ia64_load_scratch_fpregs(fr);                   \
791 } while (0)
792
793 #define PAL_CALL_PHYS(iprv,a0,a1,a2,a3) do {                    \
794         struct ia64_fpreg fr[6];                                \
795         ia64_save_scratch_fpregs(fr);                           \
796         iprv = ia64_pal_call_phys_static(a0, a1, a2, a3);       \
797         ia64_load_scratch_fpregs(fr);                           \
798 } while (0)
799
800 #define PAL_CALL_PHYS_STK(iprv,a0,a1,a2,a3) do {                \
801         struct ia64_fpreg fr[6];                                \
802         ia64_save_scratch_fpregs(fr);                           \
803         iprv = ia64_pal_call_phys_stacked(a0, a1, a2, a3);      \
804         ia64_load_scratch_fpregs(fr);                           \
805 } while (0)
806
807 typedef int (*ia64_pal_handler) (u64, ...);
808 extern ia64_pal_handler ia64_pal;
809 extern void ia64_pal_handler_init (void *);
810
811 extern ia64_pal_handler ia64_pal;
812
813 extern pal_cache_config_info_t          l0d_cache_config_info;
814 extern pal_cache_config_info_t          l0i_cache_config_info;
815 extern pal_cache_config_info_t          l1_cache_config_info;
816 extern pal_cache_config_info_t          l2_cache_config_info;
817
818 extern pal_cache_protection_info_t      l0d_cache_protection_info;
819 extern pal_cache_protection_info_t      l0i_cache_protection_info;
820 extern pal_cache_protection_info_t      l1_cache_protection_info;
821 extern pal_cache_protection_info_t      l2_cache_protection_info;
822
823 extern pal_cache_config_info_t          pal_cache_config_info_get(pal_cache_level_t,
824                                                                   pal_cache_type_t);
825
826 extern pal_cache_protection_info_t      pal_cache_protection_info_get(pal_cache_level_t,
827                                                                       pal_cache_type_t);
828
829
830 extern void                             pal_error(int);
831
832
833 /* Useful wrappers for the current list of pal procedures */
834
835 typedef union pal_bus_features_u {
836         u64     pal_bus_features_val;
837         struct {
838                 u64     pbf_reserved1                           :       29;
839                 u64     pbf_req_bus_parking                     :       1;
840                 u64     pbf_bus_lock_mask                       :       1;
841                 u64     pbf_enable_half_xfer_rate               :       1;
842                 u64     pbf_reserved2                           :       22;
843                 u64     pbf_disable_xaction_queueing            :       1;
844                 u64     pbf_disable_resp_err_check              :       1;
845                 u64     pbf_disable_berr_check                  :       1;
846                 u64     pbf_disable_bus_req_internal_err_signal :       1;
847                 u64     pbf_disable_bus_req_berr_signal         :       1;
848                 u64     pbf_disable_bus_init_event_check        :       1;
849                 u64     pbf_disable_bus_init_event_signal       :       1;
850                 u64     pbf_disable_bus_addr_err_check          :       1;
851                 u64     pbf_disable_bus_addr_err_signal         :       1;
852                 u64     pbf_disable_bus_data_err_check          :       1;
853         } pal_bus_features_s;
854 } pal_bus_features_u_t;
855
856 extern void pal_bus_features_print (u64);
857
858 /* Provide information about configurable processor bus features */
859 static inline s64
860 ia64_pal_bus_get_features (pal_bus_features_u_t *features_avail,
861                            pal_bus_features_u_t *features_status,
862                            pal_bus_features_u_t *features_control)
863 {
864         struct ia64_pal_retval iprv;
865         PAL_CALL_PHYS(iprv, PAL_BUS_GET_FEATURES, 0, 0, 0);
866         if (features_avail)
867                 features_avail->pal_bus_features_val = iprv.v0;
868         if (features_status)
869                 features_status->pal_bus_features_val = iprv.v1;
870         if (features_control)
871                 features_control->pal_bus_features_val = iprv.v2;
872         return iprv.status;
873 }
874
875 /* Enables/disables specific processor bus features */
876 static inline s64
877 ia64_pal_bus_set_features (pal_bus_features_u_t feature_select)
878 {
879         struct ia64_pal_retval iprv;
880         PAL_CALL_PHYS(iprv, PAL_BUS_SET_FEATURES, feature_select.pal_bus_features_val, 0, 0);
881         return iprv.status;
882 }
883
884 /* Get detailed cache information */
885 static inline s64
886 ia64_pal_cache_config_info (u64 cache_level, u64 cache_type, pal_cache_config_info_t *conf)
887 {
888         struct ia64_pal_retval iprv;
889
890         PAL_CALL(iprv, PAL_CACHE_INFO, cache_level, cache_type, 0);
891
892         if (iprv.status == 0) {
893                 conf->pcci_status                 = iprv.status;
894                 conf->pcci_info_1.pcci1_data      = iprv.v0;
895                 conf->pcci_info_2.pcci2_data      = iprv.v1;
896                 conf->pcci_reserved               = iprv.v2;
897         }
898         return iprv.status;
899
900 }
901
902 /* Get detailed cche protection information */
903 static inline s64
904 ia64_pal_cache_prot_info (u64 cache_level, u64 cache_type, pal_cache_protection_info_t *prot)
905 {
906         struct ia64_pal_retval iprv;
907
908         PAL_CALL(iprv, PAL_CACHE_PROT_INFO, cache_level, cache_type, 0);
909
910         if (iprv.status == 0) {
911                 prot->pcpi_status           = iprv.status;
912                 prot->pcp_info[0].pcpi_data = iprv.v0 & 0xffffffff;
913                 prot->pcp_info[1].pcpi_data = iprv.v0 >> 32;
914                 prot->pcp_info[2].pcpi_data = iprv.v1 & 0xffffffff;
915                 prot->pcp_info[3].pcpi_data = iprv.v1 >> 32;
916                 prot->pcp_info[4].pcpi_data = iprv.v2 & 0xffffffff;
917                 prot->pcp_info[5].pcpi_data = iprv.v2 >> 32;
918         }
919         return iprv.status;
920 }
921
922 /*
923  * Flush the processor instruction or data caches.  *PROGRESS must be
924  * initialized to zero before calling this for the first time..
925  */
926 static inline s64
927 ia64_pal_cache_flush (u64 cache_type, u64 invalidate, u64 *progress, u64 *vector)
928 {
929         struct ia64_pal_retval iprv;
930         PAL_CALL_IC_OFF(iprv, PAL_CACHE_FLUSH, cache_type, invalidate, *progress);
931         if (vector)
932                 *vector = iprv.v0;
933         *progress = iprv.v1;
934         return iprv.status;
935 }
936
937
938 /* Initialize the processor controlled caches */
939 static inline s64
940 ia64_pal_cache_init (u64 level, u64 cache_type, u64 rest)
941 {
942         struct ia64_pal_retval iprv;
943         PAL_CALL(iprv, PAL_CACHE_INIT, level, cache_type, rest);
944         return iprv.status;
945 }
946
947 /* Initialize the tags and data of a data or unified cache line of
948  * processor controlled cache to known values without the availability
949  * of backing memory.
950  */
951 static inline s64
952 ia64_pal_cache_line_init (u64 physical_addr, u64 data_value)
953 {
954         struct ia64_pal_retval iprv;
955         PAL_CALL(iprv, PAL_CACHE_LINE_INIT, physical_addr, data_value, 0);
956         return iprv.status;
957 }
958
959
960 /* Read the data and tag of a processor controlled cache line for diags */
961 static inline s64
962 ia64_pal_cache_read (pal_cache_line_id_u_t line_id, u64 physical_addr)
963 {
964         struct ia64_pal_retval iprv;
965         PAL_CALL(iprv, PAL_CACHE_READ, line_id.pclid_data, physical_addr, 0);
966         return iprv.status;
967 }
968
969 /* Return summary information about the heirarchy of caches controlled by the processor */
970 static inline s64
971 ia64_pal_cache_summary (u64 *cache_levels, u64 *unique_caches)
972 {
973         struct ia64_pal_retval iprv;
974         PAL_CALL(iprv, PAL_CACHE_SUMMARY, 0, 0, 0);
975         if (cache_levels)
976                 *cache_levels = iprv.v0;
977         if (unique_caches)
978                 *unique_caches = iprv.v1;
979         return iprv.status;
980 }
981
982 /* Write the data and tag of a processor-controlled cache line for diags */
983 static inline s64
984 ia64_pal_cache_write (pal_cache_line_id_u_t line_id, u64 physical_addr, u64 data)
985 {
986         struct ia64_pal_retval iprv;
987         PAL_CALL(iprv, PAL_CACHE_WRITE, line_id.pclid_data, physical_addr, data);
988         return iprv.status;
989 }
990
991
992 /* Return the parameters needed to copy relocatable PAL procedures from ROM to memory */
993 static inline s64
994 ia64_pal_copy_info (u64 copy_type, u64 num_procs, u64 num_iopics,
995                     u64 *buffer_size, u64 *buffer_align)
996 {
997         struct ia64_pal_retval iprv;
998         PAL_CALL(iprv, PAL_COPY_INFO, copy_type, num_procs, num_iopics);
999         if (buffer_size)
1000                 *buffer_size = iprv.v0;
1001         if (buffer_align)
1002                 *buffer_align = iprv.v1;
1003         return iprv.status;
1004 }
1005
1006 /* Copy relocatable PAL procedures from ROM to memory */
1007 static inline s64
1008 ia64_pal_copy_pal (u64 target_addr, u64 alloc_size, u64 processor, u64 *pal_proc_offset)
1009 {
1010         struct ia64_pal_retval iprv;
1011         PAL_CALL(iprv, PAL_COPY_PAL, target_addr, alloc_size, processor);
1012         if (pal_proc_offset)
1013                 *pal_proc_offset = iprv.v0;
1014         return iprv.status;
1015 }
1016
1017 /* Return the number of instruction and data debug register pairs */
1018 static inline s64
1019 ia64_pal_debug_info (u64 *inst_regs,  u64 *data_regs)
1020 {
1021         struct ia64_pal_retval iprv;
1022         PAL_CALL(iprv, PAL_DEBUG_INFO, 0, 0, 0);
1023         if (inst_regs)
1024                 *inst_regs = iprv.v0;
1025         if (data_regs)
1026                 *data_regs = iprv.v1;
1027
1028         return iprv.status;
1029 }
1030
1031 #ifdef TBD
1032 /* Switch from IA64-system environment to IA-32 system environment */
1033 static inline s64
1034 ia64_pal_enter_ia32_env (ia32_env1, ia32_env2, ia32_env3)
1035 {
1036         struct ia64_pal_retval iprv;
1037         PAL_CALL(iprv, PAL_ENTER_IA_32_ENV, ia32_env1, ia32_env2, ia32_env3);
1038         return iprv.status;
1039 }
1040 #endif
1041
1042 /* Get unique geographical address of this processor on its bus */
1043 static inline s64
1044 ia64_pal_fixed_addr (u64 *global_unique_addr)
1045 {
1046         struct ia64_pal_retval iprv;
1047         PAL_CALL(iprv, PAL_FIXED_ADDR, 0, 0, 0);
1048         if (global_unique_addr)
1049                 *global_unique_addr = iprv.v0;
1050         return iprv.status;
1051 }
1052
1053 /* Get base frequency of the platform if generated by the processor */
1054 static inline s64
1055 ia64_pal_freq_base (u64 *platform_base_freq)
1056 {
1057         struct ia64_pal_retval iprv;
1058         PAL_CALL(iprv, PAL_FREQ_BASE, 0, 0, 0);
1059         if (platform_base_freq)
1060                 *platform_base_freq = iprv.v0;
1061         return iprv.status;
1062 }
1063
1064 /*
1065  * Get the ratios for processor frequency, bus frequency and interval timer to
1066  * to base frequency of the platform
1067  */
1068 static inline s64
1069 ia64_pal_freq_ratios (struct pal_freq_ratio *proc_ratio, struct pal_freq_ratio *bus_ratio,
1070                       struct pal_freq_ratio *itc_ratio)
1071 {
1072         struct ia64_pal_retval iprv;
1073         PAL_CALL(iprv, PAL_FREQ_RATIOS, 0, 0, 0);
1074         if (proc_ratio)
1075                 *(u64 *)proc_ratio = iprv.v0;
1076         if (bus_ratio)
1077                 *(u64 *)bus_ratio = iprv.v1;
1078         if (itc_ratio)
1079                 *(u64 *)itc_ratio = iprv.v2;
1080         return iprv.status;
1081 }
1082
1083 /* Make the processor enter HALT or one of the implementation dependent low
1084  * power states where prefetching and execution are suspended and cache and
1085  * TLB coherency is not maintained.
1086  */
1087 static inline s64
1088 ia64_pal_halt (u64 halt_state)
1089 {
1090         struct ia64_pal_retval iprv;
1091         PAL_CALL(iprv, PAL_HALT, halt_state, 0, 0);
1092         return iprv.status;
1093 }
1094
1095 typedef union pal_power_mgmt_info_u {
1096         u64                     ppmi_data;
1097         struct {
1098                u64              exit_latency            : 16,
1099                                 entry_latency           : 16,
1100                                 power_consumption       : 28,
1101                                 im                      : 1,
1102                                 co                      : 1,
1103                                 reserved                : 2;
1104         } pal_power_mgmt_info_s;
1105 } pal_power_mgmt_info_u_t;
1106
1107 /* Return information about processor's optional power management capabilities. */
1108 static inline s64
1109 ia64_pal_halt_info (pal_power_mgmt_info_u_t *power_buf)
1110 {
1111         struct ia64_pal_retval iprv;
1112         PAL_CALL_STK(iprv, PAL_HALT_INFO, (unsigned long) power_buf, 0, 0);
1113         return iprv.status;
1114 }
1115
1116 /* Get the current P-state information */
1117 static inline s64
1118 ia64_pal_get_pstate (u64 *pstate_index)
1119 {
1120         struct ia64_pal_retval iprv;
1121         PAL_CALL_STK(iprv, PAL_GET_PSTATE, 0, 0, 0);
1122         *pstate_index = iprv.v0;
1123         return iprv.status;
1124 }
1125
1126 /* Set the P-state */
1127 static inline s64
1128 ia64_pal_set_pstate (u64 pstate_index)
1129 {
1130         struct ia64_pal_retval iprv;
1131         PAL_CALL_STK(iprv, PAL_SET_PSTATE, pstate_index, 0, 0);
1132         return iprv.status;
1133 }
1134
1135 /* Cause the processor to enter LIGHT HALT state, where prefetching and execution are
1136  * suspended, but cache and TLB coherency is maintained.
1137  */
1138 static inline s64
1139 ia64_pal_halt_light (void)
1140 {
1141         struct ia64_pal_retval iprv;
1142         PAL_CALL(iprv, PAL_HALT_LIGHT, 0, 0, 0);
1143         return iprv.status;
1144 }
1145
1146 /* Clear all the processor error logging   registers and reset the indicator that allows
1147  * the error logging registers to be written. This procedure also checks the pending
1148  * machine check bit and pending INIT bit and reports their states.
1149  */
1150 static inline s64
1151 ia64_pal_mc_clear_log (u64 *pending_vector)
1152 {
1153         struct ia64_pal_retval iprv;
1154         PAL_CALL(iprv, PAL_MC_CLEAR_LOG, 0, 0, 0);
1155         if (pending_vector)
1156                 *pending_vector = iprv.v0;
1157         return iprv.status;
1158 }
1159
1160 /* Ensure that all outstanding transactions in a processor are completed or that any
1161  * MCA due to thes outstanding transaction is taken.
1162  */
1163 static inline s64
1164 ia64_pal_mc_drain (void)
1165 {
1166         struct ia64_pal_retval iprv;
1167         PAL_CALL(iprv, PAL_MC_DRAIN, 0, 0, 0);
1168         return iprv.status;
1169 }
1170
1171 /* Return the machine check dynamic processor state */
1172 static inline s64
1173 ia64_pal_mc_dynamic_state (u64 offset, u64 *size, u64 *pds)
1174 {
1175         struct ia64_pal_retval iprv;
1176         PAL_CALL(iprv, PAL_MC_DYNAMIC_STATE, offset, 0, 0);
1177         if (size)
1178                 *size = iprv.v0;
1179         if (pds)
1180                 *pds = iprv.v1;
1181         return iprv.status;
1182 }
1183
1184 /* Return processor machine check information */
1185 static inline s64
1186 ia64_pal_mc_error_info (u64 info_index, u64 type_index, u64 *size, u64 *error_info)
1187 {
1188         struct ia64_pal_retval iprv;
1189         PAL_CALL(iprv, PAL_MC_ERROR_INFO, info_index, type_index, 0);
1190         if (size)
1191                 *size = iprv.v0;
1192         if (error_info)
1193                 *error_info = iprv.v1;
1194         return iprv.status;
1195 }
1196
1197 /* Inform PALE_CHECK whether a machine check is expected so that PALE_CHECK willnot
1198  * attempt to correct any expected machine checks.
1199  */
1200 static inline s64
1201 ia64_pal_mc_expected (u64 expected, u64 *previous)
1202 {
1203         struct ia64_pal_retval iprv;
1204         PAL_CALL(iprv, PAL_MC_EXPECTED, expected, 0, 0);
1205         if (previous)
1206                 *previous = iprv.v0;
1207         return iprv.status;
1208 }
1209
1210 /* Register a platform dependent location with PAL to which it can save
1211  * minimal processor state in the event of a machine check or initialization
1212  * event.
1213  */
1214 static inline s64
1215 ia64_pal_mc_register_mem (u64 physical_addr)
1216 {
1217         struct ia64_pal_retval iprv;
1218         PAL_CALL(iprv, PAL_MC_REGISTER_MEM, physical_addr, 0, 0);
1219         return iprv.status;
1220 }
1221
1222 /* Restore minimal architectural processor state, set CMC interrupt if necessary
1223  * and resume execution
1224  */
1225 static inline s64
1226 ia64_pal_mc_resume (u64 set_cmci, u64 save_ptr)
1227 {
1228         struct ia64_pal_retval iprv;
1229         PAL_CALL(iprv, PAL_MC_RESUME, set_cmci, save_ptr, 0);
1230         return iprv.status;
1231 }
1232
1233 /* Return the memory attributes implemented by the processor */
1234 static inline s64
1235 ia64_pal_mem_attrib (u64 *mem_attrib)
1236 {
1237         struct ia64_pal_retval iprv;
1238         PAL_CALL(iprv, PAL_MEM_ATTRIB, 0, 0, 0);
1239         if (mem_attrib)
1240                 *mem_attrib = iprv.v0 & 0xff;
1241         return iprv.status;
1242 }
1243
1244 /* Return the amount of memory needed for second phase of processor
1245  * self-test and the required alignment of memory.
1246  */
1247 static inline s64
1248 ia64_pal_mem_for_test (u64 *bytes_needed, u64 *alignment)
1249 {
1250         struct ia64_pal_retval iprv;
1251         PAL_CALL(iprv, PAL_MEM_FOR_TEST, 0, 0, 0);
1252         if (bytes_needed)
1253                 *bytes_needed = iprv.v0;
1254         if (alignment)
1255                 *alignment = iprv.v1;
1256         return iprv.status;
1257 }
1258
1259 typedef union pal_perf_mon_info_u {
1260         u64                       ppmi_data;
1261         struct {
1262                u64              generic         : 8,
1263                                 width           : 8,
1264                                 cycles          : 8,
1265                                 retired         : 8,
1266                                 reserved        : 32;
1267         } pal_perf_mon_info_s;
1268 } pal_perf_mon_info_u_t;
1269
1270 /* Return the performance monitor information about what can be counted
1271  * and how to configure the monitors to count the desired events.
1272  */
1273 static inline s64
1274 ia64_pal_perf_mon_info (u64 *pm_buffer, pal_perf_mon_info_u_t *pm_info)
1275 {
1276         struct ia64_pal_retval iprv;
1277         PAL_CALL(iprv, PAL_PERF_MON_INFO, (unsigned long) pm_buffer, 0, 0);
1278         if (pm_info)
1279                 pm_info->ppmi_data = iprv.v0;
1280         return iprv.status;
1281 }
1282
1283 /* Specifies the physical address of the processor interrupt block
1284  * and I/O port space.
1285  */
1286 static inline s64
1287 ia64_pal_platform_addr (u64 type, u64 physical_addr)
1288 {
1289         struct ia64_pal_retval iprv;
1290         PAL_CALL(iprv, PAL_PLATFORM_ADDR, type, physical_addr, 0);
1291         return iprv.status;
1292 }
1293
1294 /* Set the SAL PMI entrypoint in memory */
1295 static inline s64
1296 ia64_pal_pmi_entrypoint (u64 sal_pmi_entry_addr)
1297 {
1298         struct ia64_pal_retval iprv;
1299         PAL_CALL(iprv, PAL_PMI_ENTRYPOINT, sal_pmi_entry_addr, 0, 0);
1300         return iprv.status;
1301 }
1302
1303 struct pal_features_s;
1304 /* Provide information about configurable processor features */
1305 static inline s64
1306 ia64_pal_proc_get_features (u64 *features_avail,
1307                             u64 *features_status,
1308                             u64 *features_control)
1309 {
1310         struct ia64_pal_retval iprv;
1311         PAL_CALL_PHYS(iprv, PAL_PROC_GET_FEATURES, 0, 0, 0);
1312         if (iprv.status == 0) {
1313                 *features_avail   = iprv.v0;
1314                 *features_status  = iprv.v1;
1315                 *features_control = iprv.v2;
1316         }
1317         return iprv.status;
1318 }
1319
1320 /* Enable/disable processor dependent features */
1321 static inline s64
1322 ia64_pal_proc_set_features (u64 feature_select)
1323 {
1324         struct ia64_pal_retval iprv;
1325         PAL_CALL_PHYS(iprv, PAL_PROC_SET_FEATURES, feature_select, 0, 0);
1326         return iprv.status;
1327 }
1328
1329 /*
1330  * Put everything in a struct so we avoid the global offset table whenever
1331  * possible.
1332  */
1333 typedef struct ia64_ptce_info_s {
1334         u64             base;
1335         u32             count[2];
1336         u32             stride[2];
1337 } ia64_ptce_info_t;
1338
1339 /* Return the information required for the architected loop used to purge
1340  * (initialize) the entire TC
1341  */
1342 static inline s64
1343 ia64_get_ptce (ia64_ptce_info_t *ptce)
1344 {
1345         struct ia64_pal_retval iprv;
1346
1347         if (!ptce)
1348                 return -1;
1349
1350         PAL_CALL(iprv, PAL_PTCE_INFO, 0, 0, 0);
1351         if (iprv.status == 0) {
1352                 ptce->base = iprv.v0;
1353                 ptce->count[0] = iprv.v1 >> 32;
1354                 ptce->count[1] = iprv.v1 & 0xffffffff;
1355                 ptce->stride[0] = iprv.v2 >> 32;
1356                 ptce->stride[1] = iprv.v2 & 0xffffffff;
1357         }
1358         return iprv.status;
1359 }
1360
1361 /* Return info about implemented application and control registers. */
1362 static inline s64
1363 ia64_pal_register_info (u64 info_request, u64 *reg_info_1, u64 *reg_info_2)
1364 {
1365         struct ia64_pal_retval iprv;
1366         PAL_CALL(iprv, PAL_REGISTER_INFO, info_request, 0, 0);
1367         if (reg_info_1)
1368                 *reg_info_1 = iprv.v0;
1369         if (reg_info_2)
1370                 *reg_info_2 = iprv.v1;
1371         return iprv.status;
1372 }
1373
1374 typedef union pal_hints_u {
1375         u64                     ph_data;
1376         struct {
1377                u64              si              : 1,
1378                                 li              : 1,
1379                                 reserved        : 62;
1380         } pal_hints_s;
1381 } pal_hints_u_t;
1382
1383 /* Return information about the register stack and RSE for this processor
1384  * implementation.
1385  */
1386 static inline s64
1387 ia64_pal_rse_info (u64 *num_phys_stacked, pal_hints_u_t *hints)
1388 {
1389         struct ia64_pal_retval iprv;
1390         PAL_CALL(iprv, PAL_RSE_INFO, 0, 0, 0);
1391         if (num_phys_stacked)
1392                 *num_phys_stacked = iprv.v0;
1393         if (hints)
1394                 hints->ph_data = iprv.v1;
1395         return iprv.status;
1396 }
1397
1398 /* Cause the processor to enter SHUTDOWN state, where prefetching and execution are
1399  * suspended, but cause cache and TLB coherency to be maintained.
1400  * This is usually called in IA-32 mode.
1401  */
1402 static inline s64
1403 ia64_pal_shutdown (void)
1404 {
1405         struct ia64_pal_retval iprv;
1406         PAL_CALL(iprv, PAL_SHUTDOWN, 0, 0, 0);
1407         return iprv.status;
1408 }
1409
1410 /* Perform the second phase of processor self-test. */
1411 static inline s64
1412 ia64_pal_test_proc (u64 test_addr, u64 test_size, u64 attributes, u64 *self_test_state)
1413 {
1414         struct ia64_pal_retval iprv;
1415         PAL_CALL(iprv, PAL_TEST_PROC, test_addr, test_size, attributes);
1416         if (self_test_state)
1417                 *self_test_state = iprv.v0;
1418         return iprv.status;
1419 }
1420
1421 typedef union  pal_version_u {
1422         u64     pal_version_val;
1423         struct {
1424                 u64     pv_pal_b_rev            :       8;
1425                 u64     pv_pal_b_model          :       8;
1426                 u64     pv_reserved1            :       8;
1427                 u64     pv_pal_vendor           :       8;
1428                 u64     pv_pal_a_rev            :       8;
1429                 u64     pv_pal_a_model          :       8;
1430                 u64     pv_reserved2            :       16;
1431         } pal_version_s;
1432 } pal_version_u_t;
1433
1434
1435 /* Return PAL version information */
1436 static inline s64
1437 ia64_pal_version (pal_version_u_t *pal_min_version, pal_version_u_t *pal_cur_version)
1438 {
1439         struct ia64_pal_retval iprv;
1440         PAL_CALL_PHYS(iprv, PAL_VERSION, 0, 0, 0);
1441         if (pal_min_version)
1442                 pal_min_version->pal_version_val = iprv.v0;
1443
1444         if (pal_cur_version)
1445                 pal_cur_version->pal_version_val = iprv.v1;
1446
1447         return iprv.status;
1448 }
1449
1450 typedef union pal_tc_info_u {
1451         u64                     pti_val;
1452         struct {
1453                u64              num_sets        :       8,
1454                                 associativity   :       8,
1455                                 num_entries     :       16,
1456                                 pf              :       1,
1457                                 unified         :       1,
1458                                 reduce_tr       :       1,
1459                                 reserved        :       29;
1460         } pal_tc_info_s;
1461 } pal_tc_info_u_t;
1462
1463 #define tc_reduce_tr            pal_tc_info_s.reduce_tr
1464 #define tc_unified              pal_tc_info_s.unified
1465 #define tc_pf                   pal_tc_info_s.pf
1466 #define tc_num_entries          pal_tc_info_s.num_entries
1467 #define tc_associativity        pal_tc_info_s.associativity
1468 #define tc_num_sets             pal_tc_info_s.num_sets
1469
1470
1471 /* Return information about the virtual memory characteristics of the processor
1472  * implementation.
1473  */
1474 static inline s64
1475 ia64_pal_vm_info (u64 tc_level, u64 tc_type,  pal_tc_info_u_t *tc_info, u64 *tc_pages)
1476 {
1477         struct ia64_pal_retval iprv;
1478         PAL_CALL(iprv, PAL_VM_INFO, tc_level, tc_type, 0);
1479         if (tc_info)
1480                 tc_info->pti_val = iprv.v0;
1481         if (tc_pages)
1482                 *tc_pages = iprv.v1;
1483         return iprv.status;
1484 }
1485
1486 /* Get page size information about the virtual memory characteristics of the processor
1487  * implementation.
1488  */
1489 static inline s64
1490 ia64_pal_vm_page_size (u64 *tr_pages, u64 *vw_pages)
1491 {
1492         struct ia64_pal_retval iprv;
1493         PAL_CALL(iprv, PAL_VM_PAGE_SIZE, 0, 0, 0);
1494         if (tr_pages)
1495                 *tr_pages = iprv.v0;
1496         if (vw_pages)
1497                 *vw_pages = iprv.v1;
1498         return iprv.status;
1499 }
1500
1501 typedef union pal_vm_info_1_u {
1502         u64                     pvi1_val;
1503         struct {
1504                 u64             vw              : 1,
1505                                 phys_add_size   : 7,
1506                                 key_size        : 8,
1507                                 max_pkr         : 8,
1508                                 hash_tag_id     : 8,
1509                                 max_dtr_entry   : 8,
1510                                 max_itr_entry   : 8,
1511                                 max_unique_tcs  : 8,
1512                                 num_tc_levels   : 8;
1513         } pal_vm_info_1_s;
1514 } pal_vm_info_1_u_t;
1515
1516 typedef union pal_vm_info_2_u {
1517         u64                     pvi2_val;
1518         struct {
1519                 u64             impl_va_msb     : 8,
1520                                 rid_size        : 8,
1521                                 reserved        : 48;
1522         } pal_vm_info_2_s;
1523 } pal_vm_info_2_u_t;
1524
1525 /* Get summary information about the virtual memory characteristics of the processor
1526  * implementation.
1527  */
1528 static inline s64
1529 ia64_pal_vm_summary (pal_vm_info_1_u_t *vm_info_1, pal_vm_info_2_u_t *vm_info_2)
1530 {
1531         struct ia64_pal_retval iprv;
1532         PAL_CALL(iprv, PAL_VM_SUMMARY, 0, 0, 0);
1533         if (vm_info_1)
1534                 vm_info_1->pvi1_val = iprv.v0;
1535         if (vm_info_2)
1536                 vm_info_2->pvi2_val = iprv.v1;
1537         return iprv.status;
1538 }
1539
1540 typedef union pal_itr_valid_u {
1541         u64                     piv_val;
1542         struct {
1543                u64              access_rights_valid     : 1,
1544                                 priv_level_valid        : 1,
1545                                 dirty_bit_valid         : 1,
1546                                 mem_attr_valid          : 1,
1547                                 reserved                : 60;
1548         } pal_tr_valid_s;
1549 } pal_tr_valid_u_t;
1550
1551 /* Read a translation register */
1552 static inline s64
1553 ia64_pal_tr_read (u64 reg_num, u64 tr_type, u64 *tr_buffer, pal_tr_valid_u_t *tr_valid)
1554 {
1555         struct ia64_pal_retval iprv;
1556         PAL_CALL_PHYS_STK(iprv, PAL_VM_TR_READ, reg_num, tr_type,(u64)ia64_tpa(tr_buffer));
1557         if (tr_valid)
1558                 tr_valid->piv_val = iprv.v0;
1559         return iprv.status;
1560 }
1561
1562 /*
1563  * PAL_PREFETCH_VISIBILITY transaction types
1564  */
1565 #define PAL_VISIBILITY_VIRTUAL          0
1566 #define PAL_VISIBILITY_PHYSICAL         1
1567
1568 /*
1569  * PAL_PREFETCH_VISIBILITY return codes
1570  */
1571 #define PAL_VISIBILITY_OK               1
1572 #define PAL_VISIBILITY_OK_REMOTE_NEEDED 0
1573 #define PAL_VISIBILITY_INVAL_ARG        -2
1574 #define PAL_VISIBILITY_ERROR            -3
1575
1576 static inline s64
1577 ia64_pal_prefetch_visibility (s64 trans_type)
1578 {
1579         struct ia64_pal_retval iprv;
1580         PAL_CALL(iprv, PAL_PREFETCH_VISIBILITY, trans_type, 0, 0);
1581         return iprv.status;
1582 }
1583
1584 /* data structure for getting information on logical to physical mappings */
1585 typedef union pal_log_overview_u {
1586         struct {
1587                 u64     num_log         :16,    /* Total number of logical
1588                                                  * processors on this die
1589                                                  */
1590                         tpc             :8,     /* Threads per core */
1591                         reserved3       :8,     /* Reserved */
1592                         cpp             :8,     /* Cores per processor */
1593                         reserved2       :8,     /* Reserved */
1594                         ppid            :8,     /* Physical processor ID */
1595                         reserved1       :8;     /* Reserved */
1596         } overview_bits;
1597         u64 overview_data;
1598 } pal_log_overview_t;
1599
1600 typedef union pal_proc_n_log_info1_u{
1601         struct {
1602                 u64     tid             :16,    /* Thread id */
1603                         reserved2       :16,    /* Reserved */
1604                         cid             :16,    /* Core id */
1605                         reserved1       :16;    /* Reserved */
1606         } ppli1_bits;
1607         u64     ppli1_data;
1608 } pal_proc_n_log_info1_t;
1609
1610 typedef union pal_proc_n_log_info2_u {
1611         struct {
1612                 u64     la              :16,    /* Logical address */
1613                         reserved        :48;    /* Reserved */
1614         } ppli2_bits;
1615         u64     ppli2_data;
1616 } pal_proc_n_log_info2_t;
1617
1618 typedef struct pal_logical_to_physical_s
1619 {
1620         pal_log_overview_t overview;
1621         pal_proc_n_log_info1_t ppli1;
1622         pal_proc_n_log_info2_t ppli2;
1623 } pal_logical_to_physical_t;
1624
1625 #define overview_num_log        overview.overview_bits.num_log
1626 #define overview_tpc            overview.overview_bits.tpc
1627 #define overview_cpp            overview.overview_bits.cpp
1628 #define overview_ppid           overview.overview_bits.ppid
1629 #define log1_tid                ppli1.ppli1_bits.tid
1630 #define log1_cid                ppli1.ppli1_bits.cid
1631 #define log2_la                 ppli2.ppli2_bits.la
1632
1633 /* Get information on logical to physical processor mappings. */
1634 static inline s64
1635 ia64_pal_logical_to_phys(u64 proc_number, pal_logical_to_physical_t *mapping)
1636 {
1637         struct ia64_pal_retval iprv;
1638
1639         PAL_CALL(iprv, PAL_LOGICAL_TO_PHYSICAL, proc_number, 0, 0);
1640
1641         if (iprv.status == PAL_STATUS_SUCCESS)
1642         {
1643                 if (proc_number == 0)
1644                         mapping->overview.overview_data = iprv.v0;
1645                 mapping->ppli1.ppli1_data = iprv.v1;
1646                 mapping->ppli2.ppli2_data = iprv.v2;
1647         }
1648
1649         return iprv.status;
1650 }
1651 #endif /* __ASSEMBLY__ */
1652
1653 #endif /* _ASM_IA64_PAL_H */