viafb: split global index up
[linux-2.6.git] / drivers / video / via / lcd.c
1 /*
2  * Copyright 1998-2008 VIA Technologies, Inc. All Rights Reserved.
3  * Copyright 2001-2008 S3 Graphics, Inc. All Rights Reserved.
4
5  * This program is free software; you can redistribute it and/or
6  * modify it under the terms of the GNU General Public
7  * License as published by the Free Software Foundation;
8  * either version 2, or (at your option) any later version.
9
10  * This program is distributed in the hope that it will be useful,
11  * but WITHOUT ANY WARRANTIES OR REPRESENTATIONS; without even
12  * the implied warranty of MERCHANTABILITY or FITNESS FOR
13  * A PARTICULAR PURPOSE.See the GNU General Public License
14  * for more details.
15
16  * You should have received a copy of the GNU General Public License
17  * along with this program; if not, write to the Free Software
18  * Foundation, Inc.,
19  * 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
20  */
21
22 #include "global.h"
23 #include "lcdtbl.h"
24
25 #define viafb_compact_res(x, y) (((x)<<16)|(y))
26
27 static struct iga2_shadow_crtc_timing iga2_shadow_crtc_reg = {
28         /* IGA2 Shadow Horizontal Total */
29         {IGA2_SHADOW_HOR_TOTAL_REG_NUM, {{CR6D, 0, 7}, {CR71, 3, 3} } },
30         /* IGA2 Shadow Horizontal Blank End */
31         {IGA2_SHADOW_HOR_BLANK_END_REG_NUM, {{CR6E, 0, 7} } },
32         /* IGA2 Shadow Vertical Total */
33         {IGA2_SHADOW_VER_TOTAL_REG_NUM, {{CR6F, 0, 7}, {CR71, 0, 2} } },
34         /* IGA2 Shadow Vertical Addressable Video */
35         {IGA2_SHADOW_VER_ADDR_REG_NUM, {{CR70, 0, 7}, {CR71, 4, 6} } },
36         /* IGA2 Shadow Vertical Blank Start */
37         {IGA2_SHADOW_VER_BLANK_START_REG_NUM,
38          {{CR72, 0, 7}, {CR74, 4, 6} } },
39         /* IGA2 Shadow Vertical Blank End */
40         {IGA2_SHADOW_VER_BLANK_END_REG_NUM, {{CR73, 0, 7}, {CR74, 0, 2} } },
41         /* IGA2 Shadow Vertical Sync Start */
42         {IGA2_SHADOW_VER_SYNC_START_REG_NUM, {{CR75, 0, 7}, {CR76, 4, 6} } },
43         /* IGA2 Shadow Vertical Sync End */
44         {IGA2_SHADOW_VER_SYNC_END_REG_NUM, {{CR76, 0, 3} } }
45 };
46
47 static struct _lcd_scaling_factor lcd_scaling_factor = {
48         /* LCD Horizontal Scaling Factor Register */
49         {LCD_HOR_SCALING_FACTOR_REG_NUM,
50          {{CR9F, 0, 1}, {CR77, 0, 7}, {CR79, 4, 5} } },
51         /* LCD Vertical Scaling Factor Register */
52         {LCD_VER_SCALING_FACTOR_REG_NUM,
53          {{CR79, 3, 3}, {CR78, 0, 7}, {CR79, 6, 7} } }
54 };
55 static struct _lcd_scaling_factor lcd_scaling_factor_CLE = {
56         /* LCD Horizontal Scaling Factor Register */
57         {LCD_HOR_SCALING_FACTOR_REG_NUM_CLE, {{CR77, 0, 7}, {CR79, 4, 5} } },
58         /* LCD Vertical Scaling Factor Register */
59         {LCD_VER_SCALING_FACTOR_REG_NUM_CLE, {{CR78, 0, 7}, {CR79, 6, 7} } }
60 };
61
62 static int check_lvds_chip(int device_id_subaddr, int device_id);
63 static bool lvds_identify_integratedlvds(void);
64 static int fp_id_to_vindex(int panel_id);
65 static int lvds_register_read(int index);
66 static void load_lcd_scaling(int set_hres, int set_vres, int panel_hres,
67                       int panel_vres);
68 static void load_lcd_k400_patch_tbl(int set_hres, int set_vres,
69         int panel_id);
70 static void load_lcd_p880_patch_tbl(int set_hres, int set_vres,
71         int panel_id);
72 static void load_lcd_patch_regs(int set_hres, int set_vres,
73         int panel_id, int set_iga);
74 static void via_pitch_alignment_patch_lcd(
75         struct lvds_setting_information *plvds_setting_info,
76                                    struct lvds_chip_information
77                                    *plvds_chip_info);
78 static void lcd_patch_skew_dvp0(struct lvds_setting_information
79                          *plvds_setting_info,
80                          struct lvds_chip_information *plvds_chip_info);
81 static void lcd_patch_skew_dvp1(struct lvds_setting_information
82                          *plvds_setting_info,
83                          struct lvds_chip_information *plvds_chip_info);
84 static void lcd_patch_skew(struct lvds_setting_information
85         *plvds_setting_info, struct lvds_chip_information *plvds_chip_info);
86
87 static void integrated_lvds_disable(struct lvds_setting_information
88                              *plvds_setting_info,
89                              struct lvds_chip_information *plvds_chip_info);
90 static void integrated_lvds_enable(struct lvds_setting_information
91                             *plvds_setting_info,
92                             struct lvds_chip_information *plvds_chip_info);
93 static void lcd_powersequence_off(void);
94 static void lcd_powersequence_on(void);
95 static void fill_lcd_format(void);
96 static void check_diport_of_integrated_lvds(
97         struct lvds_chip_information *plvds_chip_info,
98                                      struct lvds_setting_information
99                                      *plvds_setting_info);
100 static struct display_timing lcd_centering_timging(struct display_timing
101                                             mode_crt_reg,
102                                            struct display_timing panel_crt_reg);
103 static void load_crtc_shadow_timing(struct display_timing mode_timing,
104                              struct display_timing panel_timing);
105 static void viafb_load_scaling_factor_for_p4m900(int set_hres,
106         int set_vres, int panel_hres, int panel_vres);
107
108 static int check_lvds_chip(int device_id_subaddr, int device_id)
109 {
110         if (lvds_register_read(device_id_subaddr) == device_id)
111                 return OK;
112         else
113                 return FAIL;
114 }
115
116 void viafb_init_lcd_size(void)
117 {
118         DEBUG_MSG(KERN_INFO "viafb_init_lcd_size()\n");
119         DEBUG_MSG(KERN_INFO
120                 "viaparinfo->lvds_setting_info->get_lcd_size_method %d\n",
121                 viaparinfo->lvds_setting_info->get_lcd_size_method);
122
123         switch (viaparinfo->lvds_setting_info->get_lcd_size_method) {
124         case GET_LCD_SIZE_BY_SYSTEM_BIOS:
125                 break;
126         case GET_LCD_SZIE_BY_HW_STRAPPING:
127                 break;
128         case GET_LCD_SIZE_BY_VGA_BIOS:
129                 DEBUG_MSG(KERN_INFO "Get LCD Size method by VGA BIOS !!\n");
130                 viaparinfo->lvds_setting_info->lcd_panel_size =
131                     fp_id_to_vindex(viafb_lcd_panel_id);
132                 DEBUG_MSG(KERN_INFO "LCD Panel_ID = %d\n",
133                           viaparinfo->lvds_setting_info->lcd_panel_id);
134                 DEBUG_MSG(KERN_INFO "LCD Panel Size = %d\n",
135                           viaparinfo->lvds_setting_info->lcd_panel_size);
136                 break;
137         case GET_LCD_SIZE_BY_USER_SETTING:
138                 DEBUG_MSG(KERN_INFO "Get LCD Size method by user setting !!\n");
139                 viaparinfo->lvds_setting_info->lcd_panel_size =
140                     fp_id_to_vindex(viafb_lcd_panel_id);
141                 DEBUG_MSG(KERN_INFO "LCD Panel_ID = %d\n",
142                           viaparinfo->lvds_setting_info->lcd_panel_id);
143                 DEBUG_MSG(KERN_INFO "LCD Panel Size = %d\n",
144                           viaparinfo->lvds_setting_info->lcd_panel_size);
145                 break;
146         default:
147                 DEBUG_MSG(KERN_INFO "viafb_init_lcd_size fail\n");
148                 viaparinfo->lvds_setting_info->lcd_panel_id =
149                         LCD_PANEL_ID1_800X600;
150                 viaparinfo->lvds_setting_info->lcd_panel_size =
151                     fp_id_to_vindex(LCD_PANEL_ID1_800X600);
152         }
153         viaparinfo->lvds_setting_info2->lcd_panel_id =
154                 viaparinfo->lvds_setting_info->lcd_panel_id;
155         viaparinfo->lvds_setting_info2->lcd_panel_size =
156                 viaparinfo->lvds_setting_info->lcd_panel_size;
157         viaparinfo->lvds_setting_info2->lcd_panel_hres =
158                 viaparinfo->lvds_setting_info->lcd_panel_hres;
159         viaparinfo->lvds_setting_info2->lcd_panel_vres =
160                 viaparinfo->lvds_setting_info->lcd_panel_vres;
161         viaparinfo->lvds_setting_info2->device_lcd_dualedge =
162             viaparinfo->lvds_setting_info->device_lcd_dualedge;
163         viaparinfo->lvds_setting_info2->LCDDithering =
164                 viaparinfo->lvds_setting_info->LCDDithering;
165 }
166
167 static bool lvds_identify_integratedlvds(void)
168 {
169         if (viafb_display_hardware_layout == HW_LAYOUT_LCD_EXTERNAL_LCD2) {
170                 /* Two dual channel LCD (Internal LVDS + External LVDS): */
171                 /* If we have an external LVDS, such as VT1636, we should
172                    have its chip ID already. */
173                 if (viaparinfo->chip_info->lvds_chip_info.lvds_chip_name) {
174                         viaparinfo->chip_info->lvds_chip_info2.lvds_chip_name =
175                             INTEGRATED_LVDS;
176                         DEBUG_MSG(KERN_INFO "Support two dual channel LVDS!\
177                                   (Internal LVDS + External LVDS)\n");
178                 } else {
179                         viaparinfo->chip_info->lvds_chip_info.lvds_chip_name =
180                             INTEGRATED_LVDS;
181                         DEBUG_MSG(KERN_INFO "Not found external LVDS,\
182                                   so can't support two dual channel LVDS!\n");
183                 }
184         } else if (viafb_display_hardware_layout == HW_LAYOUT_LCD1_LCD2) {
185                 /* Two single channel LCD (Internal LVDS + Internal LVDS): */
186                 viaparinfo->chip_info->lvds_chip_info.lvds_chip_name =
187                 INTEGRATED_LVDS;
188                 viaparinfo->chip_info->lvds_chip_info2.lvds_chip_name =
189                         INTEGRATED_LVDS;
190                 DEBUG_MSG(KERN_INFO "Support two single channel LVDS!\
191                           (Internal LVDS + Internal LVDS)\n");
192         } else if (viafb_display_hardware_layout != HW_LAYOUT_DVI_ONLY) {
193                 /* If we have found external LVDS, just use it,
194                    otherwise, we will use internal LVDS as default. */
195                 if (!viaparinfo->chip_info->lvds_chip_info.lvds_chip_name) {
196                         viaparinfo->chip_info->lvds_chip_info.lvds_chip_name =
197                             INTEGRATED_LVDS;
198                         DEBUG_MSG(KERN_INFO "Found Integrated LVDS!\n");
199                 }
200         } else {
201                 viaparinfo->chip_info->lvds_chip_info.lvds_chip_name =
202                         NON_LVDS_TRANSMITTER;
203                 DEBUG_MSG(KERN_INFO "Do not support LVDS!\n");
204                 return false;
205         }
206
207         return true;
208 }
209
210 int viafb_lvds_trasmitter_identify(void)
211 {
212         viaparinfo->shared->i2c_stuff.i2c_port = I2CPORTINDEX;
213         if (viafb_lvds_identify_vt1636()) {
214                 viaparinfo->chip_info->lvds_chip_info.i2c_port = I2CPORTINDEX;
215                 DEBUG_MSG(KERN_INFO
216                           "Found VIA VT1636 LVDS on port i2c 0x31 \n");
217         } else {
218                 viaparinfo->shared->i2c_stuff.i2c_port = GPIOPORTINDEX;
219                 if (viafb_lvds_identify_vt1636()) {
220                         viaparinfo->chip_info->lvds_chip_info.i2c_port =
221                                 GPIOPORTINDEX;
222                         DEBUG_MSG(KERN_INFO
223                                   "Found VIA VT1636 LVDS on port gpio 0x2c \n");
224                 }
225         }
226
227         if (viaparinfo->chip_info->gfx_chip_name == UNICHROME_CX700)
228                 lvds_identify_integratedlvds();
229
230         if (viaparinfo->chip_info->lvds_chip_info.lvds_chip_name)
231                 return true;
232         /* Check for VT1631: */
233         viaparinfo->chip_info->lvds_chip_info.lvds_chip_name = VT1631_LVDS;
234         viaparinfo->chip_info->lvds_chip_info.lvds_chip_slave_addr =
235                 VT1631_LVDS_I2C_ADDR;
236
237         if (check_lvds_chip(VT1631_DEVICE_ID_REG, VT1631_DEVICE_ID) != FAIL) {
238                 DEBUG_MSG(KERN_INFO "\n VT1631 LVDS ! \n");
239                 DEBUG_MSG(KERN_INFO "\n %2d",
240                           viaparinfo->chip_info->lvds_chip_info.lvds_chip_name);
241                 DEBUG_MSG(KERN_INFO "\n %2d",
242                           viaparinfo->chip_info->lvds_chip_info.lvds_chip_name);
243                 return OK;
244         }
245
246         viaparinfo->chip_info->lvds_chip_info.lvds_chip_name =
247                 NON_LVDS_TRANSMITTER;
248         viaparinfo->chip_info->lvds_chip_info.lvds_chip_slave_addr =
249                 VT1631_LVDS_I2C_ADDR;
250         return FAIL;
251 }
252
253 static int fp_id_to_vindex(int panel_id)
254 {
255         DEBUG_MSG(KERN_INFO "fp_get_panel_id()\n");
256
257         if (panel_id > LCD_PANEL_ID_MAXIMUM)
258                 viafb_lcd_panel_id = panel_id =
259                 viafb_read_reg(VIACR, CR3F) & 0x0F;
260
261         switch (panel_id) {
262         case 0x0:
263                 viaparinfo->lvds_setting_info->lcd_panel_hres = 640;
264                 viaparinfo->lvds_setting_info->lcd_panel_vres = 480;
265                 viaparinfo->lvds_setting_info->lcd_panel_id =
266                         LCD_PANEL_ID0_640X480;
267                 viaparinfo->lvds_setting_info->device_lcd_dualedge = 0;
268                 viaparinfo->lvds_setting_info->LCDDithering = 1;
269                 return VIA_RES_640X480;
270                 break;
271         case 0x1:
272                 viaparinfo->lvds_setting_info->lcd_panel_hres = 800;
273                 viaparinfo->lvds_setting_info->lcd_panel_vres = 600;
274                 viaparinfo->lvds_setting_info->lcd_panel_id =
275                         LCD_PANEL_ID1_800X600;
276                 viaparinfo->lvds_setting_info->device_lcd_dualedge = 0;
277                 viaparinfo->lvds_setting_info->LCDDithering = 1;
278                 return VIA_RES_800X600;
279                 break;
280         case 0x2:
281                 viaparinfo->lvds_setting_info->lcd_panel_hres = 1024;
282                 viaparinfo->lvds_setting_info->lcd_panel_vres = 768;
283                 viaparinfo->lvds_setting_info->lcd_panel_id =
284                         LCD_PANEL_ID2_1024X768;
285                 viaparinfo->lvds_setting_info->device_lcd_dualedge = 0;
286                 viaparinfo->lvds_setting_info->LCDDithering = 1;
287                 return VIA_RES_1024X768;
288                 break;
289         case 0x3:
290                 viaparinfo->lvds_setting_info->lcd_panel_hres = 1280;
291                 viaparinfo->lvds_setting_info->lcd_panel_vres = 768;
292                 viaparinfo->lvds_setting_info->lcd_panel_id =
293                         LCD_PANEL_ID3_1280X768;
294                 viaparinfo->lvds_setting_info->device_lcd_dualedge = 0;
295                 viaparinfo->lvds_setting_info->LCDDithering = 1;
296                 return VIA_RES_1280X768;
297                 break;
298         case 0x4:
299                 viaparinfo->lvds_setting_info->lcd_panel_hres = 1280;
300                 viaparinfo->lvds_setting_info->lcd_panel_vres = 1024;
301                 viaparinfo->lvds_setting_info->lcd_panel_id =
302                         LCD_PANEL_ID4_1280X1024;
303                 viaparinfo->lvds_setting_info->device_lcd_dualedge = 1;
304                 viaparinfo->lvds_setting_info->LCDDithering = 1;
305                 return VIA_RES_1280X1024;
306                 break;
307         case 0x5:
308                 viaparinfo->lvds_setting_info->lcd_panel_hres = 1400;
309                 viaparinfo->lvds_setting_info->lcd_panel_vres = 1050;
310                 viaparinfo->lvds_setting_info->lcd_panel_id =
311                         LCD_PANEL_ID5_1400X1050;
312                 viaparinfo->lvds_setting_info->device_lcd_dualedge = 1;
313                 viaparinfo->lvds_setting_info->LCDDithering = 1;
314                 return VIA_RES_1400X1050;
315                 break;
316         case 0x6:
317                 viaparinfo->lvds_setting_info->lcd_panel_hres = 1600;
318                 viaparinfo->lvds_setting_info->lcd_panel_vres = 1200;
319                 viaparinfo->lvds_setting_info->lcd_panel_id =
320                         LCD_PANEL_ID6_1600X1200;
321                 viaparinfo->lvds_setting_info->device_lcd_dualedge = 1;
322                 viaparinfo->lvds_setting_info->LCDDithering = 1;
323                 return VIA_RES_1600X1200;
324                 break;
325         case 0x8:
326                 viaparinfo->lvds_setting_info->lcd_panel_hres = 800;
327                 viaparinfo->lvds_setting_info->lcd_panel_vres = 480;
328                 viaparinfo->lvds_setting_info->lcd_panel_id =
329                         LCD_PANEL_IDA_800X480;
330                 viaparinfo->lvds_setting_info->device_lcd_dualedge = 0;
331                 viaparinfo->lvds_setting_info->LCDDithering = 1;
332                 return VIA_RES_800X480;
333                 break;
334         case 0x9:
335                 viaparinfo->lvds_setting_info->lcd_panel_hres = 1024;
336                 viaparinfo->lvds_setting_info->lcd_panel_vres = 768;
337                 viaparinfo->lvds_setting_info->lcd_panel_id =
338                         LCD_PANEL_ID2_1024X768;
339                 viaparinfo->lvds_setting_info->device_lcd_dualedge = 1;
340                 viaparinfo->lvds_setting_info->LCDDithering = 1;
341                 return VIA_RES_1024X768;
342                 break;
343         case 0xA:
344                 viaparinfo->lvds_setting_info->lcd_panel_hres = 1024;
345                 viaparinfo->lvds_setting_info->lcd_panel_vres = 768;
346                 viaparinfo->lvds_setting_info->lcd_panel_id =
347                         LCD_PANEL_ID2_1024X768;
348                 viaparinfo->lvds_setting_info->device_lcd_dualedge = 0;
349                 viaparinfo->lvds_setting_info->LCDDithering = 0;
350                 return VIA_RES_1024X768;
351                 break;
352         case 0xB:
353                 viaparinfo->lvds_setting_info->lcd_panel_hres = 1024;
354                 viaparinfo->lvds_setting_info->lcd_panel_vres = 768;
355                 viaparinfo->lvds_setting_info->lcd_panel_id =
356                         LCD_PANEL_ID2_1024X768;
357                 viaparinfo->lvds_setting_info->device_lcd_dualedge = 1;
358                 viaparinfo->lvds_setting_info->LCDDithering = 0;
359                 return VIA_RES_1024X768;
360                 break;
361         case 0xC:
362                 viaparinfo->lvds_setting_info->lcd_panel_hres = 1280;
363                 viaparinfo->lvds_setting_info->lcd_panel_vres = 768;
364                 viaparinfo->lvds_setting_info->lcd_panel_id =
365                         LCD_PANEL_ID3_1280X768;
366                 viaparinfo->lvds_setting_info->device_lcd_dualedge = 0;
367                 viaparinfo->lvds_setting_info->LCDDithering = 0;
368                 return VIA_RES_1280X768;
369                 break;
370         case 0xD:
371                 viaparinfo->lvds_setting_info->lcd_panel_hres = 1280;
372                 viaparinfo->lvds_setting_info->lcd_panel_vres = 1024;
373                 viaparinfo->lvds_setting_info->lcd_panel_id =
374                         LCD_PANEL_ID4_1280X1024;
375                 viaparinfo->lvds_setting_info->device_lcd_dualedge = 1;
376                 viaparinfo->lvds_setting_info->LCDDithering = 0;
377                 return VIA_RES_1280X1024;
378                 break;
379         case 0xE:
380                 viaparinfo->lvds_setting_info->lcd_panel_hres = 1400;
381                 viaparinfo->lvds_setting_info->lcd_panel_vres = 1050;
382                 viaparinfo->lvds_setting_info->lcd_panel_id =
383                         LCD_PANEL_ID5_1400X1050;
384                 viaparinfo->lvds_setting_info->device_lcd_dualedge = 1;
385                 viaparinfo->lvds_setting_info->LCDDithering = 0;
386                 return VIA_RES_1400X1050;
387                 break;
388         case 0xF:
389                 viaparinfo->lvds_setting_info->lcd_panel_hres = 1600;
390                 viaparinfo->lvds_setting_info->lcd_panel_vres = 1200;
391                 viaparinfo->lvds_setting_info->lcd_panel_id =
392                         LCD_PANEL_ID6_1600X1200;
393                 viaparinfo->lvds_setting_info->device_lcd_dualedge = 1;
394                 viaparinfo->lvds_setting_info->LCDDithering = 0;
395                 return VIA_RES_1600X1200;
396                 break;
397         case 0x10:
398                 viaparinfo->lvds_setting_info->lcd_panel_hres = 1366;
399                 viaparinfo->lvds_setting_info->lcd_panel_vres = 768;
400                 viaparinfo->lvds_setting_info->lcd_panel_id =
401                         LCD_PANEL_ID7_1366X768;
402                 viaparinfo->lvds_setting_info->device_lcd_dualedge = 0;
403                 viaparinfo->lvds_setting_info->LCDDithering = 0;
404                 return VIA_RES_1368X768;
405                 break;
406         case 0x11:
407                 viaparinfo->lvds_setting_info->lcd_panel_hres = 1024;
408                 viaparinfo->lvds_setting_info->lcd_panel_vres = 600;
409                 viaparinfo->lvds_setting_info->lcd_panel_id =
410                         LCD_PANEL_ID8_1024X600;
411                 viaparinfo->lvds_setting_info->device_lcd_dualedge = 0;
412                 viaparinfo->lvds_setting_info->LCDDithering = 1;
413                 return VIA_RES_1024X600;
414                 break;
415         case 0x12:
416                 viaparinfo->lvds_setting_info->lcd_panel_hres = 1280;
417                 viaparinfo->lvds_setting_info->lcd_panel_vres = 768;
418                 viaparinfo->lvds_setting_info->lcd_panel_id =
419                         LCD_PANEL_ID3_1280X768;
420                 viaparinfo->lvds_setting_info->device_lcd_dualedge = 1;
421                 viaparinfo->lvds_setting_info->LCDDithering = 1;
422                 return VIA_RES_1280X768;
423                 break;
424         case 0x13:
425                 viaparinfo->lvds_setting_info->lcd_panel_hres = 1280;
426                 viaparinfo->lvds_setting_info->lcd_panel_vres = 800;
427                 viaparinfo->lvds_setting_info->lcd_panel_id =
428                         LCD_PANEL_ID9_1280X800;
429                 viaparinfo->lvds_setting_info->device_lcd_dualedge = 0;
430                 viaparinfo->lvds_setting_info->LCDDithering = 1;
431                 return VIA_RES_1280X800;
432                 break;
433         case 0x14:
434                 viaparinfo->lvds_setting_info->lcd_panel_hres = 1360;
435                 viaparinfo->lvds_setting_info->lcd_panel_vres = 768;
436                 viaparinfo->lvds_setting_info->lcd_panel_id =
437                         LCD_PANEL_IDB_1360X768;
438                 viaparinfo->lvds_setting_info->device_lcd_dualedge = 0;
439                 viaparinfo->lvds_setting_info->LCDDithering = 0;
440                 return VIA_RES_1360X768;
441                 break;
442         case 0x15:
443                 viaparinfo->lvds_setting_info->lcd_panel_hres = 1280;
444                 viaparinfo->lvds_setting_info->lcd_panel_vres = 768;
445                 viaparinfo->lvds_setting_info->lcd_panel_id =
446                         LCD_PANEL_ID3_1280X768;
447                 viaparinfo->lvds_setting_info->device_lcd_dualedge = 1;
448                 viaparinfo->lvds_setting_info->LCDDithering = 0;
449                 return VIA_RES_1280X768;
450                 break;
451         case 0x16:
452                 viaparinfo->lvds_setting_info->lcd_panel_hres = 480;
453                 viaparinfo->lvds_setting_info->lcd_panel_vres = 640;
454                 viaparinfo->lvds_setting_info->lcd_panel_id =
455                         LCD_PANEL_IDC_480X640;
456                 viaparinfo->lvds_setting_info->device_lcd_dualedge = 0;
457                 viaparinfo->lvds_setting_info->LCDDithering = 1;
458                 return VIA_RES_480X640;
459                 break;
460         default:
461                 viaparinfo->lvds_setting_info->lcd_panel_hres = 800;
462                 viaparinfo->lvds_setting_info->lcd_panel_vres = 600;
463                 viaparinfo->lvds_setting_info->lcd_panel_id =
464                         LCD_PANEL_ID1_800X600;
465                 viaparinfo->lvds_setting_info->device_lcd_dualedge = 0;
466                 viaparinfo->lvds_setting_info->LCDDithering = 1;
467                 return VIA_RES_800X600;
468         }
469 }
470
471 static int lvds_register_read(int index)
472 {
473         u8 data;
474
475         viaparinfo->shared->i2c_stuff.i2c_port = GPIOPORTINDEX;
476         viafb_i2c_readbyte((u8) viaparinfo->chip_info->
477             lvds_chip_info.lvds_chip_slave_addr,
478                         (u8) index, &data);
479         return data;
480 }
481
482 static void load_lcd_scaling(int set_hres, int set_vres, int panel_hres,
483                       int panel_vres)
484 {
485         int reg_value = 0;
486         int viafb_load_reg_num;
487         struct io_register *reg = NULL;
488
489         DEBUG_MSG(KERN_INFO "load_lcd_scaling()!!\n");
490
491         /* LCD Scaling Enable */
492         viafb_write_reg_mask(CR79, VIACR, 0x07, BIT0 + BIT1 + BIT2);
493         if (UNICHROME_P4M900 == viaparinfo->chip_info->gfx_chip_name) {
494                 viafb_load_scaling_factor_for_p4m900(set_hres, set_vres,
495                                                panel_hres, panel_vres);
496                 return;
497         }
498
499         /* Check if expansion for horizontal */
500         if (set_hres != panel_hres) {
501                 /* Load Horizontal Scaling Factor */
502                 switch (viaparinfo->chip_info->gfx_chip_name) {
503                 case UNICHROME_CLE266:
504                 case UNICHROME_K400:
505                         reg_value =
506                             CLE266_LCD_HOR_SCF_FORMULA(set_hres, panel_hres);
507                         viafb_load_reg_num =
508                             lcd_scaling_factor_CLE.lcd_hor_scaling_factor.
509                             reg_num;
510                         reg = lcd_scaling_factor_CLE.lcd_hor_scaling_factor.reg;
511                         viafb_load_reg(reg_value,
512                                 viafb_load_reg_num, reg, VIACR);
513                         break;
514                 case UNICHROME_K800:
515                 case UNICHROME_PM800:
516                 case UNICHROME_CN700:
517                 case UNICHROME_CX700:
518                 case UNICHROME_K8M890:
519                 case UNICHROME_P4M890:
520                         reg_value =
521                             K800_LCD_HOR_SCF_FORMULA(set_hres, panel_hres);
522                         /* Horizontal scaling enabled */
523                         viafb_write_reg_mask(CRA2, VIACR, 0xC0, BIT7 + BIT6);
524                         viafb_load_reg_num =
525                             lcd_scaling_factor.lcd_hor_scaling_factor.reg_num;
526                         reg = lcd_scaling_factor.lcd_hor_scaling_factor.reg;
527                         viafb_load_reg(reg_value,
528                                 viafb_load_reg_num, reg, VIACR);
529                         break;
530                 }
531
532                 DEBUG_MSG(KERN_INFO "Horizontal Scaling value = %d", reg_value);
533         } else {
534                 /* Horizontal scaling disabled */
535                 viafb_write_reg_mask(CRA2, VIACR, 0x00, BIT7);
536         }
537
538         /* Check if expansion for vertical */
539         if (set_vres != panel_vres) {
540                 /* Load Vertical Scaling Factor */
541                 switch (viaparinfo->chip_info->gfx_chip_name) {
542                 case UNICHROME_CLE266:
543                 case UNICHROME_K400:
544                         reg_value =
545                             CLE266_LCD_VER_SCF_FORMULA(set_vres, panel_vres);
546                         viafb_load_reg_num =
547                             lcd_scaling_factor_CLE.lcd_ver_scaling_factor.
548                             reg_num;
549                         reg = lcd_scaling_factor_CLE.lcd_ver_scaling_factor.reg;
550                         viafb_load_reg(reg_value,
551                                 viafb_load_reg_num, reg, VIACR);
552                         break;
553                 case UNICHROME_K800:
554                 case UNICHROME_PM800:
555                 case UNICHROME_CN700:
556                 case UNICHROME_CX700:
557                 case UNICHROME_K8M890:
558                 case UNICHROME_P4M890:
559                         reg_value =
560                             K800_LCD_VER_SCF_FORMULA(set_vres, panel_vres);
561                         /* Vertical scaling enabled */
562                         viafb_write_reg_mask(CRA2, VIACR, 0x08, BIT3);
563                         viafb_load_reg_num =
564                             lcd_scaling_factor.lcd_ver_scaling_factor.reg_num;
565                         reg = lcd_scaling_factor.lcd_ver_scaling_factor.reg;
566                         viafb_load_reg(reg_value,
567                                 viafb_load_reg_num, reg, VIACR);
568                         break;
569                 }
570
571                 DEBUG_MSG(KERN_INFO "Vertical Scaling value = %d", reg_value);
572         } else {
573                 /* Vertical scaling disabled */
574                 viafb_write_reg_mask(CRA2, VIACR, 0x00, BIT3);
575         }
576 }
577
578 static void load_lcd_k400_patch_tbl(int set_hres, int set_vres,
579         int panel_id)
580 {
581         u32 compact_mode = viafb_compact_res(set_hres, set_vres);
582         int reg_num = 0;
583         struct io_reg *lcd_patch_reg = NULL;
584
585         switch (panel_id) {
586                 /* LCD 800x600 */
587         case LCD_PANEL_ID1_800X600:
588                 switch (compact_mode) {
589                 case viafb_compact_res(640, 400):
590                 case viafb_compact_res(640, 480):
591                         reg_num = NUM_TOTAL_K400_LCD_RES_6X4_8X6;
592                         lcd_patch_reg = K400_LCD_RES_6X4_8X6;
593                         break;
594                 case viafb_compact_res(720, 480):
595                 case viafb_compact_res(720, 576):
596                         reg_num = NUM_TOTAL_K400_LCD_RES_7X4_8X6;
597                         lcd_patch_reg = K400_LCD_RES_7X4_8X6;
598                         break;
599                 }
600                 break;
601
602                 /* LCD 1024x768 */
603         case LCD_PANEL_ID2_1024X768:
604                 switch (compact_mode) {
605                 case viafb_compact_res(640, 400):
606                 case viafb_compact_res(640, 480):
607                         reg_num = NUM_TOTAL_K400_LCD_RES_6X4_10X7;
608                         lcd_patch_reg = K400_LCD_RES_6X4_10X7;
609                         break;
610                 case viafb_compact_res(720, 480):
611                 case viafb_compact_res(720, 576):
612                         reg_num = NUM_TOTAL_K400_LCD_RES_7X4_10X7;
613                         lcd_patch_reg = K400_LCD_RES_7X4_10X7;
614                         break;
615                 case viafb_compact_res(800, 600):
616                         reg_num = NUM_TOTAL_K400_LCD_RES_8X6_10X7;
617                         lcd_patch_reg = K400_LCD_RES_8X6_10X7;
618                         break;
619                 }
620                 break;
621
622                 /* LCD 1280x1024 */
623         case LCD_PANEL_ID4_1280X1024:
624                 switch (compact_mode) {
625                 case viafb_compact_res(640, 400):
626                 case viafb_compact_res(640, 480):
627                         reg_num = NUM_TOTAL_K400_LCD_RES_6X4_12X10;
628                         lcd_patch_reg = K400_LCD_RES_6X4_12X10;
629                         break;
630                 case viafb_compact_res(720, 480):
631                 case viafb_compact_res(720, 576):
632                         reg_num = NUM_TOTAL_K400_LCD_RES_7X4_12X10;
633                         lcd_patch_reg = K400_LCD_RES_7X4_12X10;
634                         break;
635                 case viafb_compact_res(800, 600):
636                         reg_num = NUM_TOTAL_K400_LCD_RES_8X6_12X10;
637                         lcd_patch_reg = K400_LCD_RES_8X6_12X10;
638                         break;
639                 case viafb_compact_res(1024, 768):
640                         reg_num = NUM_TOTAL_K400_LCD_RES_10X7_12X10;
641                         lcd_patch_reg = K400_LCD_RES_10X7_12X10;
642                         break;
643
644                 }
645                 break;
646
647                 /* LCD 1400x1050 */
648         case LCD_PANEL_ID5_1400X1050:
649                 switch (compact_mode) {
650                 case viafb_compact_res(640, 480):
651                         reg_num = NUM_TOTAL_K400_LCD_RES_6X4_14X10;
652                         lcd_patch_reg = K400_LCD_RES_6X4_14X10;
653                         break;
654                 case viafb_compact_res(800, 600):
655                         reg_num = NUM_TOTAL_K400_LCD_RES_8X6_14X10;
656                         lcd_patch_reg = K400_LCD_RES_8X6_14X10;
657                         break;
658                 case viafb_compact_res(1024, 768):
659                         reg_num = NUM_TOTAL_K400_LCD_RES_10X7_14X10;
660                         lcd_patch_reg = K400_LCD_RES_10X7_14X10;
661                         break;
662                 case viafb_compact_res(1280, 768):
663                 case viafb_compact_res(1280, 800):
664                 case viafb_compact_res(1280, 960):
665                 case viafb_compact_res(1280, 1024):
666                         reg_num = NUM_TOTAL_K400_LCD_RES_12X10_14X10;
667                         lcd_patch_reg = K400_LCD_RES_12X10_14X10;
668                         break;
669                 }
670                 break;
671
672                 /* LCD 1600x1200 */
673         case LCD_PANEL_ID6_1600X1200:
674                 switch (compact_mode) {
675                 case viafb_compact_res(640, 400):
676                 case viafb_compact_res(640, 480):
677                         reg_num = NUM_TOTAL_K400_LCD_RES_6X4_16X12;
678                         lcd_patch_reg = K400_LCD_RES_6X4_16X12;
679                         break;
680                 case viafb_compact_res(720, 480):
681                 case viafb_compact_res(720, 576):
682                         reg_num = NUM_TOTAL_K400_LCD_RES_7X4_16X12;
683                         lcd_patch_reg = K400_LCD_RES_7X4_16X12;
684                         break;
685                 case viafb_compact_res(800, 600):
686                         reg_num = NUM_TOTAL_K400_LCD_RES_8X6_16X12;
687                         lcd_patch_reg = K400_LCD_RES_8X6_16X12;
688                         break;
689                 case viafb_compact_res(1024, 768):
690                         reg_num = NUM_TOTAL_K400_LCD_RES_10X7_16X12;
691                         lcd_patch_reg = K400_LCD_RES_10X7_16X12;
692                         break;
693                 case viafb_compact_res(1280, 768):
694                 case viafb_compact_res(1280, 800):
695                 case viafb_compact_res(1280, 960):
696                 case viafb_compact_res(1280, 1024):
697                         reg_num = NUM_TOTAL_K400_LCD_RES_12X10_16X12;
698                         lcd_patch_reg = K400_LCD_RES_12X10_16X12;
699                         break;
700                 }
701                 break;
702
703                 /* LCD 1366x768 */
704         case LCD_PANEL_ID7_1366X768:
705                 switch (compact_mode) {
706                 case viafb_compact_res(640, 480):
707                         reg_num = NUM_TOTAL_K400_LCD_RES_6X4_1366X7;
708                         lcd_patch_reg = K400_LCD_RES_6X4_1366X7;
709                         break;
710                 case viafb_compact_res(720, 480):
711                 case viafb_compact_res(720, 576):
712                         reg_num = NUM_TOTAL_K400_LCD_RES_7X4_1366X7;
713                         lcd_patch_reg = K400_LCD_RES_7X4_1366X7;
714                         break;
715                 case viafb_compact_res(800, 600):
716                         reg_num = NUM_TOTAL_K400_LCD_RES_8X6_1366X7;
717                         lcd_patch_reg = K400_LCD_RES_8X6_1366X7;
718                         break;
719                 case viafb_compact_res(1024, 768):
720                         reg_num = NUM_TOTAL_K400_LCD_RES_10X7_1366X7;
721                         lcd_patch_reg = K400_LCD_RES_10X7_1366X7;
722                         break;
723                 case viafb_compact_res(1280, 768):
724                 case viafb_compact_res(1280, 800):
725                 case viafb_compact_res(1280, 960):
726                 case viafb_compact_res(1280, 1024):
727                         reg_num = NUM_TOTAL_K400_LCD_RES_12X10_1366X7;
728                         lcd_patch_reg = K400_LCD_RES_12X10_1366X7;
729                         break;
730                 }
731                 break;
732
733                 /* LCD 1360x768 */
734         case LCD_PANEL_IDB_1360X768:
735                 break;
736         }
737         if (reg_num != 0) {
738                 /* H.W. Reset : ON */
739                 viafb_write_reg_mask(CR17, VIACR, 0x00, BIT7);
740
741                 viafb_write_regx(lcd_patch_reg, reg_num);
742
743                 /* H.W. Reset : OFF */
744                 viafb_write_reg_mask(CR17, VIACR, 0x80, BIT7);
745
746                 /* Reset PLL */
747                 viafb_write_reg_mask(SR40, VIASR, 0x02, BIT1);
748                 viafb_write_reg_mask(SR40, VIASR, 0x00, BIT1);
749
750                 /* Fire! */
751                 outb(inb(VIARMisc) | (BIT2 + BIT3), VIAWMisc);
752         }
753 }
754
755 static void load_lcd_p880_patch_tbl(int set_hres, int set_vres,
756         int panel_id)
757 {
758         u32 compact_mode = viafb_compact_res(set_hres, set_vres);
759         int reg_num = 0;
760         struct io_reg *lcd_patch_reg = NULL;
761
762         switch (panel_id) {
763         case LCD_PANEL_ID5_1400X1050:
764                 switch (compact_mode) {
765                 case viafb_compact_res(640, 480):
766                         reg_num = NUM_TOTAL_P880_LCD_RES_6X4_14X10;
767                         lcd_patch_reg = P880_LCD_RES_6X4_14X10;
768                         break;
769                 case viafb_compact_res(800, 600):
770                         reg_num = NUM_TOTAL_P880_LCD_RES_8X6_14X10;
771                         lcd_patch_reg = P880_LCD_RES_8X6_14X10;
772                         break;
773                 }
774                 break;
775         case LCD_PANEL_ID6_1600X1200:
776                 switch (compact_mode) {
777                 case viafb_compact_res(640, 400):
778                 case viafb_compact_res(640, 480):
779                         reg_num = NUM_TOTAL_P880_LCD_RES_6X4_16X12;
780                         lcd_patch_reg = P880_LCD_RES_6X4_16X12;
781                         break;
782                 case viafb_compact_res(720, 480):
783                 case viafb_compact_res(720, 576):
784                         reg_num = NUM_TOTAL_P880_LCD_RES_7X4_16X12;
785                         lcd_patch_reg = P880_LCD_RES_7X4_16X12;
786                         break;
787                 case viafb_compact_res(800, 600):
788                         reg_num = NUM_TOTAL_P880_LCD_RES_8X6_16X12;
789                         lcd_patch_reg = P880_LCD_RES_8X6_16X12;
790                         break;
791                 case viafb_compact_res(1024, 768):
792                         reg_num = NUM_TOTAL_P880_LCD_RES_10X7_16X12;
793                         lcd_patch_reg = P880_LCD_RES_10X7_16X12;
794                         break;
795                 case viafb_compact_res(1280, 768):
796                 case viafb_compact_res(1280, 960):
797                 case viafb_compact_res(1280, 1024):
798                         reg_num = NUM_TOTAL_P880_LCD_RES_12X10_16X12;
799                         lcd_patch_reg = P880_LCD_RES_12X10_16X12;
800                         break;
801                 }
802                 break;
803
804         }
805         if (reg_num != 0) {
806                 /* H.W. Reset : ON */
807                 viafb_write_reg_mask(CR17, VIACR, 0x00, BIT7);
808
809                 viafb_write_regx(lcd_patch_reg, reg_num);
810
811                 /* H.W. Reset : OFF */
812                 viafb_write_reg_mask(CR17, VIACR, 0x80, BIT7);
813
814                 /* Reset PLL */
815                 viafb_write_reg_mask(SR40, VIASR, 0x02, BIT1);
816                 viafb_write_reg_mask(SR40, VIASR, 0x00, BIT1);
817
818                 /* Fire! */
819                 outb(inb(VIARMisc) | (BIT2 + BIT3), VIAWMisc);
820         }
821 }
822
823 static void load_lcd_patch_regs(int set_hres, int set_vres,
824         int panel_id, int set_iga)
825 {
826         viafb_unlock_crt();
827
828         /* Patch for simultaneous & Expansion */
829         if ((set_iga == IGA1_IGA2) &&
830                 (viaparinfo->lvds_setting_info->display_method ==
831             LCD_EXPANDSION)) {
832                 switch (viaparinfo->chip_info->gfx_chip_name) {
833                 case UNICHROME_CLE266:
834                 case UNICHROME_K400:
835                         load_lcd_k400_patch_tbl(set_hres, set_vres, panel_id);
836                         break;
837                 case UNICHROME_K800:
838                         break;
839                 case UNICHROME_PM800:
840                 case UNICHROME_CN700:
841                 case UNICHROME_CX700:
842                         load_lcd_p880_patch_tbl(set_hres, set_vres, panel_id);
843                 }
844         }
845
846         viafb_lock_crt();
847 }
848
849 static void via_pitch_alignment_patch_lcd(
850         struct lvds_setting_information *plvds_setting_info,
851                                    struct lvds_chip_information
852                                    *plvds_chip_info)
853 {
854         unsigned char cr13, cr35, cr65, cr66, cr67;
855         unsigned long dwScreenPitch = 0;
856         unsigned long dwPitch;
857
858         dwPitch = plvds_setting_info->h_active * (plvds_setting_info->bpp >> 3);
859         if (dwPitch & 0x1F) {
860                 dwScreenPitch = ((dwPitch + 31) & ~31) >> 3;
861                 if (plvds_setting_info->iga_path == IGA2) {
862                         if (plvds_setting_info->bpp > 8) {
863                                 cr66 = (unsigned char)(dwScreenPitch & 0xFF);
864                                 viafb_write_reg(CR66, VIACR, cr66);
865                                 cr67 = viafb_read_reg(VIACR, CR67) & 0xFC;
866                                 cr67 |=
867                                     (unsigned
868                                      char)((dwScreenPitch & 0x300) >> 8);
869                                 viafb_write_reg(CR67, VIACR, cr67);
870                         }
871
872                         /* Fetch Count */
873                         cr67 = viafb_read_reg(VIACR, CR67) & 0xF3;
874                         cr67 |= (unsigned char)((dwScreenPitch & 0x600) >> 7);
875                         viafb_write_reg(CR67, VIACR, cr67);
876                         cr65 = (unsigned char)((dwScreenPitch >> 1) & 0xFF);
877                         cr65 += 2;
878                         viafb_write_reg(CR65, VIACR, cr65);
879                 } else {
880                         if (plvds_setting_info->bpp > 8) {
881                                 cr13 = (unsigned char)(dwScreenPitch & 0xFF);
882                                 viafb_write_reg(CR13, VIACR, cr13);
883                                 cr35 = viafb_read_reg(VIACR, CR35) & 0x1F;
884                                 cr35 |=
885                                     (unsigned
886                                      char)((dwScreenPitch & 0x700) >> 3);
887                                 viafb_write_reg(CR35, VIACR, cr35);
888                         }
889                 }
890         }
891 }
892 static void lcd_patch_skew_dvp0(struct lvds_setting_information
893                          *plvds_setting_info,
894                          struct lvds_chip_information *plvds_chip_info)
895 {
896         if (VT1636_LVDS == plvds_chip_info->lvds_chip_name) {
897                 switch (viaparinfo->chip_info->gfx_chip_name) {
898                 case UNICHROME_P4M900:
899                         viafb_vt1636_patch_skew_on_vt3364(plvds_setting_info,
900                                                     plvds_chip_info);
901                         break;
902                 case UNICHROME_P4M890:
903                         viafb_vt1636_patch_skew_on_vt3327(plvds_setting_info,
904                                                     plvds_chip_info);
905                         break;
906                 }
907         }
908 }
909 static void lcd_patch_skew_dvp1(struct lvds_setting_information
910                          *plvds_setting_info,
911                          struct lvds_chip_information *plvds_chip_info)
912 {
913         if (VT1636_LVDS == plvds_chip_info->lvds_chip_name) {
914                 switch (viaparinfo->chip_info->gfx_chip_name) {
915                 case UNICHROME_CX700:
916                         viafb_vt1636_patch_skew_on_vt3324(plvds_setting_info,
917                                                     plvds_chip_info);
918                         break;
919                 }
920         }
921 }
922 static void lcd_patch_skew(struct lvds_setting_information
923         *plvds_setting_info, struct lvds_chip_information *plvds_chip_info)
924 {
925         DEBUG_MSG(KERN_INFO "lcd_patch_skew\n");
926         switch (plvds_chip_info->output_interface) {
927         case INTERFACE_DVP0:
928                 lcd_patch_skew_dvp0(plvds_setting_info, plvds_chip_info);
929                 break;
930         case INTERFACE_DVP1:
931                 lcd_patch_skew_dvp1(plvds_setting_info, plvds_chip_info);
932                 break;
933         case INTERFACE_DFP_LOW:
934                 if (UNICHROME_P4M900 == viaparinfo->chip_info->gfx_chip_name) {
935                         viafb_write_reg_mask(CR99, VIACR, 0x08,
936                                        BIT0 + BIT1 + BIT2 + BIT3);
937                 }
938                 break;
939         }
940 }
941
942 /* LCD Set Mode */
943 void viafb_lcd_set_mode(struct crt_mode_table *mode_crt_table,
944                   struct lvds_setting_information *plvds_setting_info,
945                   struct lvds_chip_information *plvds_chip_info)
946 {
947         int set_iga = plvds_setting_info->iga_path;
948         int mode_bpp = plvds_setting_info->bpp;
949         int set_hres = plvds_setting_info->h_active;
950         int set_vres = plvds_setting_info->v_active;
951         int panel_hres = plvds_setting_info->lcd_panel_hres;
952         int panel_vres = plvds_setting_info->lcd_panel_vres;
953         u32 pll_D_N;
954         int offset;
955         struct display_timing mode_crt_reg, panel_crt_reg;
956         struct crt_mode_table *panel_crt_table = NULL;
957         struct VideoModeTable *vmode_tbl = viafb_get_mode(panel_hres,
958                 panel_vres);
959
960         DEBUG_MSG(KERN_INFO "viafb_lcd_set_mode!!\n");
961         /* Get mode table */
962         mode_crt_reg = mode_crt_table->crtc;
963         /* Get panel table Pointer */
964         panel_crt_table = vmode_tbl->crtc;
965         panel_crt_reg = panel_crt_table->crtc;
966         DEBUG_MSG(KERN_INFO "bellow viafb_lcd_set_mode!!\n");
967         if (VT1636_LVDS == plvds_chip_info->lvds_chip_name)
968                 viafb_init_lvds_vt1636(plvds_setting_info, plvds_chip_info);
969         plvds_setting_info->vclk = panel_crt_table->clk;
970         if (set_iga == IGA1) {
971                 /* IGA1 doesn't have LCD scaling, so set it as centering. */
972                 viafb_load_crtc_timing(lcd_centering_timging
973                                  (mode_crt_reg, panel_crt_reg), IGA1);
974         } else {
975                 /* Expansion */
976                 if ((plvds_setting_info->display_method ==
977                      LCD_EXPANDSION) & ((set_hres != panel_hres)
978                                         || (set_vres != panel_vres))) {
979                         /* expansion timing IGA2 loaded panel set timing*/
980                         viafb_load_crtc_timing(panel_crt_reg, IGA2);
981                         DEBUG_MSG(KERN_INFO "viafb_load_crtc_timing!!\n");
982                         load_lcd_scaling(set_hres, set_vres, panel_hres,
983                                          panel_vres);
984                         DEBUG_MSG(KERN_INFO "load_lcd_scaling!!\n");
985                 } else {        /* Centering */
986                         /* centering timing IGA2 always loaded panel
987                            and mode releative timing */
988                         viafb_load_crtc_timing(lcd_centering_timging
989                                          (mode_crt_reg, panel_crt_reg), IGA2);
990                         viafb_write_reg_mask(CR79, VIACR, 0x00,
991                                 BIT0 + BIT1 + BIT2);
992                         /* LCD scaling disabled */
993                 }
994         }
995
996         if (set_iga == IGA1_IGA2) {
997                 load_crtc_shadow_timing(mode_crt_reg, panel_crt_reg);
998                 /* Fill shadow registers */
999
1000                 switch (plvds_setting_info->lcd_panel_id) {
1001                 case LCD_PANEL_ID0_640X480:
1002                         offset = 80;
1003                         break;
1004                 case LCD_PANEL_ID1_800X600:
1005                 case LCD_PANEL_IDA_800X480:
1006                         offset = 110;
1007                         break;
1008                 case LCD_PANEL_ID2_1024X768:
1009                         offset = 150;
1010                         break;
1011                 case LCD_PANEL_ID3_1280X768:
1012                 case LCD_PANEL_ID4_1280X1024:
1013                 case LCD_PANEL_ID5_1400X1050:
1014                 case LCD_PANEL_ID9_1280X800:
1015                         offset = 190;
1016                         break;
1017                 case LCD_PANEL_ID6_1600X1200:
1018                         offset = 250;
1019                         break;
1020                 case LCD_PANEL_ID7_1366X768:
1021                 case LCD_PANEL_IDB_1360X768:
1022                         offset = 212;
1023                         break;
1024                 default:
1025                         offset = 140;
1026                         break;
1027                 }
1028
1029                 /* Offset for simultaneous */
1030                 viafb_set_secondary_pitch(offset << 3);
1031                 DEBUG_MSG(KERN_INFO "viafb_load_reg!!\n");
1032                 viafb_load_fetch_count_reg(set_hres, 4, IGA2);
1033                 /* Fetch count for simultaneous */
1034         } else {                /* SAMM */
1035                 /* Fetch count for IGA2 only */
1036                 viafb_load_fetch_count_reg(set_hres, mode_bpp / 8, set_iga);
1037
1038                 if ((viaparinfo->chip_info->gfx_chip_name != UNICHROME_CLE266)
1039                     && (viaparinfo->chip_info->gfx_chip_name != UNICHROME_K400))
1040                         viafb_load_FIFO_reg(set_iga, set_hres, set_vres);
1041
1042                 viafb_set_color_depth(mode_bpp / 8, set_iga);
1043         }
1044
1045         fill_lcd_format();
1046
1047         pll_D_N = viafb_get_clk_value(panel_crt_table[0].clk);
1048         DEBUG_MSG(KERN_INFO "PLL=0x%x", pll_D_N);
1049         viafb_set_vclock(pll_D_N, set_iga);
1050
1051         viafb_set_output_path(DEVICE_LCD, set_iga,
1052                 plvds_chip_info->output_interface);
1053         lcd_patch_skew(plvds_setting_info, plvds_chip_info);
1054
1055         /* If K8M800, enable LCD Prefetch Mode. */
1056         if ((viaparinfo->chip_info->gfx_chip_name == UNICHROME_K800)
1057             || (UNICHROME_K8M890 == viaparinfo->chip_info->gfx_chip_name))
1058                 viafb_write_reg_mask(CR6A, VIACR, 0x01, BIT0);
1059
1060         load_lcd_patch_regs(set_hres, set_vres,
1061                             plvds_setting_info->lcd_panel_id, set_iga);
1062
1063         DEBUG_MSG(KERN_INFO "load_lcd_patch_regs!!\n");
1064
1065         /* Patch for non 32bit alignment mode */
1066         via_pitch_alignment_patch_lcd(plvds_setting_info, plvds_chip_info);
1067 }
1068
1069 static void integrated_lvds_disable(struct lvds_setting_information
1070                              *plvds_setting_info,
1071                              struct lvds_chip_information *plvds_chip_info)
1072 {
1073         bool turn_off_first_powersequence = false;
1074         bool turn_off_second_powersequence = false;
1075         if (INTERFACE_LVDS0LVDS1 == plvds_chip_info->output_interface)
1076                 turn_off_first_powersequence = true;
1077         if (INTERFACE_LVDS0 == plvds_chip_info->output_interface)
1078                 turn_off_first_powersequence = true;
1079         if (INTERFACE_LVDS1 == plvds_chip_info->output_interface)
1080                 turn_off_second_powersequence = true;
1081         if (turn_off_second_powersequence) {
1082                 /* Use second power sequence control: */
1083
1084                 /* Turn off power sequence. */
1085                 viafb_write_reg_mask(CRD4, VIACR, 0, BIT1);
1086
1087                 /* Turn off back light. */
1088                 viafb_write_reg_mask(CRD3, VIACR, 0xC0, BIT6 + BIT7);
1089         }
1090         if (turn_off_first_powersequence) {
1091                 /* Use first power sequence control: */
1092
1093                 /* Turn off power sequence. */
1094                 viafb_write_reg_mask(CR6A, VIACR, 0, BIT3);
1095
1096                 /* Turn off back light. */
1097                 viafb_write_reg_mask(CR91, VIACR, 0xC0, BIT6 + BIT7);
1098         }
1099
1100         /* Turn DFP High/Low Pad off. */
1101         viafb_write_reg_mask(SR2A, VIASR, 0, BIT0 + BIT1 + BIT2 + BIT3);
1102
1103         /* Power off LVDS channel. */
1104         switch (plvds_chip_info->output_interface) {
1105         case INTERFACE_LVDS0:
1106                 {
1107                         viafb_write_reg_mask(CRD2, VIACR, 0x80, BIT7);
1108                         break;
1109                 }
1110
1111         case INTERFACE_LVDS1:
1112                 {
1113                         viafb_write_reg_mask(CRD2, VIACR, 0x40, BIT6);
1114                         break;
1115                 }
1116
1117         case INTERFACE_LVDS0LVDS1:
1118                 {
1119                         viafb_write_reg_mask(CRD2, VIACR, 0xC0, BIT6 + BIT7);
1120                         break;
1121                 }
1122         }
1123 }
1124
1125 static void integrated_lvds_enable(struct lvds_setting_information
1126                             *plvds_setting_info,
1127                             struct lvds_chip_information *plvds_chip_info)
1128 {
1129         DEBUG_MSG(KERN_INFO "integrated_lvds_enable, out_interface:%d\n",
1130                   plvds_chip_info->output_interface);
1131         if (plvds_setting_info->lcd_mode == LCD_SPWG)
1132                 viafb_write_reg_mask(CRD2, VIACR, 0x00, BIT0 + BIT1);
1133         else
1134                 viafb_write_reg_mask(CRD2, VIACR, 0x03, BIT0 + BIT1);
1135
1136         switch (plvds_chip_info->output_interface) {
1137         case INTERFACE_LVDS0LVDS1:
1138         case INTERFACE_LVDS0:
1139                 /* Use first power sequence control: */
1140                 /* Use hardware control power sequence. */
1141                 viafb_write_reg_mask(CR91, VIACR, 0, BIT0);
1142                 /* Turn on back light. */
1143                 viafb_write_reg_mask(CR91, VIACR, 0, BIT6 + BIT7);
1144                 /* Turn on hardware power sequence. */
1145                 viafb_write_reg_mask(CR6A, VIACR, 0x08, BIT3);
1146                 break;
1147         case INTERFACE_LVDS1:
1148                 /* Use second power sequence control: */
1149                 /* Use hardware control power sequence. */
1150                 viafb_write_reg_mask(CRD3, VIACR, 0, BIT0);
1151                 /* Turn on back light. */
1152                 viafb_write_reg_mask(CRD3, VIACR, 0, BIT6 + BIT7);
1153                 /* Turn on hardware power sequence. */
1154                 viafb_write_reg_mask(CRD4, VIACR, 0x02, BIT1);
1155                 break;
1156         }
1157
1158         /* Turn DFP High/Low pad on. */
1159         viafb_write_reg_mask(SR2A, VIASR, 0x0F, BIT0 + BIT1 + BIT2 + BIT3);
1160
1161         /* Power on LVDS channel. */
1162         switch (plvds_chip_info->output_interface) {
1163         case INTERFACE_LVDS0:
1164                 {
1165                         viafb_write_reg_mask(CRD2, VIACR, 0, BIT7);
1166                         break;
1167                 }
1168
1169         case INTERFACE_LVDS1:
1170                 {
1171                         viafb_write_reg_mask(CRD2, VIACR, 0, BIT6);
1172                         break;
1173                 }
1174
1175         case INTERFACE_LVDS0LVDS1:
1176                 {
1177                         viafb_write_reg_mask(CRD2, VIACR, 0, BIT6 + BIT7);
1178                         break;
1179                 }
1180         }
1181 }
1182
1183 void viafb_lcd_disable(void)
1184 {
1185
1186         if (viaparinfo->chip_info->gfx_chip_name == UNICHROME_CLE266) {
1187                 lcd_powersequence_off();
1188                 /* DI1 pad off */
1189                 viafb_write_reg_mask(SR1E, VIASR, 0x00, 0x30);
1190         } else if (viaparinfo->chip_info->gfx_chip_name == UNICHROME_CX700) {
1191                 if (viafb_LCD2_ON
1192                     && (INTEGRATED_LVDS ==
1193                         viaparinfo->chip_info->lvds_chip_info2.lvds_chip_name))
1194                         integrated_lvds_disable(viaparinfo->lvds_setting_info,
1195                                 &viaparinfo->chip_info->lvds_chip_info2);
1196                 if (INTEGRATED_LVDS ==
1197                         viaparinfo->chip_info->lvds_chip_info.lvds_chip_name)
1198                         integrated_lvds_disable(viaparinfo->lvds_setting_info,
1199                                 &viaparinfo->chip_info->lvds_chip_info);
1200                 if (VT1636_LVDS == viaparinfo->chip_info->
1201                         lvds_chip_info.lvds_chip_name)
1202                         viafb_disable_lvds_vt1636(viaparinfo->lvds_setting_info,
1203                                 &viaparinfo->chip_info->lvds_chip_info);
1204         } else if (VT1636_LVDS ==
1205         viaparinfo->chip_info->lvds_chip_info.lvds_chip_name) {
1206                 viafb_disable_lvds_vt1636(viaparinfo->lvds_setting_info,
1207                                     &viaparinfo->chip_info->lvds_chip_info);
1208         } else {
1209                 /* DFP-HL pad off          */
1210                 viafb_write_reg_mask(SR2A, VIASR, 0x00, 0x0F);
1211                 /* Backlight off           */
1212                 viafb_write_reg_mask(SR3D, VIASR, 0x00, 0x20);
1213                 /* 24 bit DI data paht off */
1214                 viafb_write_reg_mask(CR91, VIACR, 0x80, 0x80);
1215                 /* Simultaneout disabled   */
1216                 viafb_write_reg_mask(CR6B, VIACR, 0x00, 0x08);
1217         }
1218
1219         /* Disable expansion bit   */
1220         viafb_write_reg_mask(CR79, VIACR, 0x00, 0x01);
1221         /* CRT path set to IGA1    */
1222         viafb_write_reg_mask(SR16, VIASR, 0x00, 0x40);
1223         /* Simultaneout disabled   */
1224         viafb_write_reg_mask(CR6B, VIACR, 0x00, 0x08);
1225         /* IGA2 path disabled      */
1226         viafb_write_reg_mask(CR6A, VIACR, 0x00, 0x80);
1227
1228 }
1229
1230 void viafb_lcd_enable(void)
1231 {
1232         if (viaparinfo->chip_info->gfx_chip_name == UNICHROME_CLE266) {
1233                 /* DI1 pad on */
1234                 viafb_write_reg_mask(SR1E, VIASR, 0x30, 0x30);
1235                 lcd_powersequence_on();
1236         } else if (viaparinfo->chip_info->gfx_chip_name == UNICHROME_CX700) {
1237                 if (viafb_LCD2_ON && (INTEGRATED_LVDS ==
1238                         viaparinfo->chip_info->lvds_chip_info2.lvds_chip_name))
1239                         integrated_lvds_enable(viaparinfo->lvds_setting_info2, \
1240                                 &viaparinfo->chip_info->lvds_chip_info2);
1241                 if (INTEGRATED_LVDS ==
1242                         viaparinfo->chip_info->lvds_chip_info.lvds_chip_name)
1243                         integrated_lvds_enable(viaparinfo->lvds_setting_info,
1244                                 &viaparinfo->chip_info->lvds_chip_info);
1245                 if (VT1636_LVDS == viaparinfo->chip_info->
1246                         lvds_chip_info.lvds_chip_name)
1247                         viafb_enable_lvds_vt1636(viaparinfo->
1248                         lvds_setting_info, &viaparinfo->chip_info->
1249                         lvds_chip_info);
1250         } else if (VT1636_LVDS ==
1251         viaparinfo->chip_info->lvds_chip_info.lvds_chip_name) {
1252                 viafb_enable_lvds_vt1636(viaparinfo->lvds_setting_info,
1253                                    &viaparinfo->chip_info->lvds_chip_info);
1254         } else {
1255                 /* DFP-HL pad on           */
1256                 viafb_write_reg_mask(SR2A, VIASR, 0x0F, 0x0F);
1257                 /* Backlight on            */
1258                 viafb_write_reg_mask(SR3D, VIASR, 0x20, 0x20);
1259                 /* 24 bit DI data paht on  */
1260                 viafb_write_reg_mask(CR91, VIACR, 0x00, 0x80);
1261
1262                 /* Set data source selection bit by iga path */
1263                 if (viaparinfo->lvds_setting_info->iga_path == IGA1) {
1264                         /* DFP-H set to IGA1       */
1265                         viafb_write_reg_mask(CR97, VIACR, 0x00, 0x10);
1266                         /* DFP-L set to IGA1       */
1267                         viafb_write_reg_mask(CR99, VIACR, 0x00, 0x10);
1268                 } else {
1269                         /* DFP-H set to IGA2       */
1270                         viafb_write_reg_mask(CR97, VIACR, 0x10, 0x10);
1271                         /* DFP-L set to IGA2       */
1272                         viafb_write_reg_mask(CR99, VIACR, 0x10, 0x10);
1273                 }
1274                 /* LCD enabled             */
1275                 viafb_write_reg_mask(CR6A, VIACR, 0x48, 0x48);
1276         }
1277
1278         if ((viaparinfo->lvds_setting_info->iga_path == IGA1)
1279             || (viaparinfo->lvds_setting_info->iga_path == IGA1_IGA2)) {
1280                 /* CRT path set to IGA2    */
1281                 viafb_write_reg_mask(SR16, VIASR, 0x40, 0x40);
1282                 /* IGA2 path disabled      */
1283                 viafb_write_reg_mask(CR6A, VIACR, 0x00, 0x80);
1284                 /* IGA2 path enabled       */
1285         } else {                /* IGA2 */
1286                 viafb_write_reg_mask(CR6A, VIACR, 0x80, 0x80);
1287         }
1288
1289 }
1290
1291 static void lcd_powersequence_off(void)
1292 {
1293         int i, mask, data;
1294
1295         /* Software control power sequence */
1296         viafb_write_reg_mask(CR91, VIACR, 0x11, 0x11);
1297
1298         for (i = 0; i < 3; i++) {
1299                 mask = PowerSequenceOff[0][i];
1300                 data = PowerSequenceOff[1][i] & mask;
1301                 viafb_write_reg_mask(CR91, VIACR, (u8) data, (u8) mask);
1302                 udelay(PowerSequenceOff[2][i]);
1303         }
1304
1305         /* Disable LCD */
1306         viafb_write_reg_mask(CR6A, VIACR, 0x00, 0x08);
1307 }
1308
1309 static void lcd_powersequence_on(void)
1310 {
1311         int i, mask, data;
1312
1313         /* Software control power sequence */
1314         viafb_write_reg_mask(CR91, VIACR, 0x11, 0x11);
1315
1316         /* Enable LCD */
1317         viafb_write_reg_mask(CR6A, VIACR, 0x08, 0x08);
1318
1319         for (i = 0; i < 3; i++) {
1320                 mask = PowerSequenceOn[0][i];
1321                 data = PowerSequenceOn[1][i] & mask;
1322                 viafb_write_reg_mask(CR91, VIACR, (u8) data, (u8) mask);
1323                 udelay(PowerSequenceOn[2][i]);
1324         }
1325
1326         udelay(1);
1327 }
1328
1329 static void fill_lcd_format(void)
1330 {
1331         u8 bdithering = 0, bdual = 0;
1332
1333         if (viaparinfo->lvds_setting_info->device_lcd_dualedge)
1334                 bdual = BIT4;
1335         if (viaparinfo->lvds_setting_info->LCDDithering)
1336                 bdithering = BIT0;
1337         /* Dual & Dithering */
1338         viafb_write_reg_mask(CR88, VIACR, (bdithering | bdual), BIT4 + BIT0);
1339 }
1340
1341 static void check_diport_of_integrated_lvds(
1342         struct lvds_chip_information *plvds_chip_info,
1343                                      struct lvds_setting_information
1344                                      *plvds_setting_info)
1345 {
1346         /* Determine LCD DI Port by hardware layout. */
1347         switch (viafb_display_hardware_layout) {
1348         case HW_LAYOUT_LCD_ONLY:
1349                 {
1350                         if (plvds_setting_info->device_lcd_dualedge) {
1351                                 plvds_chip_info->output_interface =
1352                                     INTERFACE_LVDS0LVDS1;
1353                         } else {
1354                                 plvds_chip_info->output_interface =
1355                                     INTERFACE_LVDS0;
1356                         }
1357
1358                         break;
1359                 }
1360
1361         case HW_LAYOUT_DVI_ONLY:
1362                 {
1363                         plvds_chip_info->output_interface = INTERFACE_NONE;
1364                         break;
1365                 }
1366
1367         case HW_LAYOUT_LCD1_LCD2:
1368         case HW_LAYOUT_LCD_EXTERNAL_LCD2:
1369                 {
1370                         plvds_chip_info->output_interface =
1371                             INTERFACE_LVDS0LVDS1;
1372                         break;
1373                 }
1374
1375         case HW_LAYOUT_LCD_DVI:
1376                 {
1377                         plvds_chip_info->output_interface = INTERFACE_LVDS1;
1378                         break;
1379                 }
1380
1381         default:
1382                 {
1383                         plvds_chip_info->output_interface = INTERFACE_LVDS1;
1384                         break;
1385                 }
1386         }
1387
1388         DEBUG_MSG(KERN_INFO
1389                   "Display Hardware Layout: 0x%x, LCD DI Port: 0x%x\n",
1390                   viafb_display_hardware_layout,
1391                   plvds_chip_info->output_interface);
1392 }
1393
1394 void viafb_init_lvds_output_interface(struct lvds_chip_information
1395                                 *plvds_chip_info,
1396                                 struct lvds_setting_information
1397                                 *plvds_setting_info)
1398 {
1399         if (INTERFACE_NONE != plvds_chip_info->output_interface) {
1400                 /*Do nothing, lcd port is specified by module parameter */
1401                 return;
1402         }
1403
1404         switch (plvds_chip_info->lvds_chip_name) {
1405
1406         case VT1636_LVDS:
1407                 switch (viaparinfo->chip_info->gfx_chip_name) {
1408                 case UNICHROME_CX700:
1409                         plvds_chip_info->output_interface = INTERFACE_DVP1;
1410                         break;
1411                 case UNICHROME_CN700:
1412                         plvds_chip_info->output_interface = INTERFACE_DFP_LOW;
1413                         break;
1414                 default:
1415                         plvds_chip_info->output_interface = INTERFACE_DVP0;
1416                         break;
1417                 }
1418                 break;
1419
1420         case INTEGRATED_LVDS:
1421                 check_diport_of_integrated_lvds(plvds_chip_info,
1422                                                 plvds_setting_info);
1423                 break;
1424
1425         default:
1426                 switch (viaparinfo->chip_info->gfx_chip_name) {
1427                 case UNICHROME_K8M890:
1428                 case UNICHROME_P4M900:
1429                 case UNICHROME_P4M890:
1430                         plvds_chip_info->output_interface = INTERFACE_DFP_LOW;
1431                         break;
1432                 default:
1433                         plvds_chip_info->output_interface = INTERFACE_DFP;
1434                         break;
1435                 }
1436                 break;
1437         }
1438 }
1439
1440 static struct display_timing lcd_centering_timging(struct display_timing
1441                                             mode_crt_reg,
1442                                             struct display_timing panel_crt_reg)
1443 {
1444         struct display_timing crt_reg;
1445
1446         crt_reg.hor_total = panel_crt_reg.hor_total;
1447         crt_reg.hor_addr = mode_crt_reg.hor_addr;
1448         crt_reg.hor_blank_start =
1449             (panel_crt_reg.hor_addr - mode_crt_reg.hor_addr) / 2 +
1450             crt_reg.hor_addr;
1451         crt_reg.hor_blank_end = panel_crt_reg.hor_blank_end;
1452         crt_reg.hor_sync_start =
1453             (panel_crt_reg.hor_sync_start -
1454              panel_crt_reg.hor_blank_start) + crt_reg.hor_blank_start;
1455         crt_reg.hor_sync_end = panel_crt_reg.hor_sync_end;
1456
1457         crt_reg.ver_total = panel_crt_reg.ver_total;
1458         crt_reg.ver_addr = mode_crt_reg.ver_addr;
1459         crt_reg.ver_blank_start =
1460             (panel_crt_reg.ver_addr - mode_crt_reg.ver_addr) / 2 +
1461             crt_reg.ver_addr;
1462         crt_reg.ver_blank_end = panel_crt_reg.ver_blank_end;
1463         crt_reg.ver_sync_start =
1464             (panel_crt_reg.ver_sync_start -
1465              panel_crt_reg.ver_blank_start) + crt_reg.ver_blank_start;
1466         crt_reg.ver_sync_end = panel_crt_reg.ver_sync_end;
1467
1468         return crt_reg;
1469 }
1470
1471 static void load_crtc_shadow_timing(struct display_timing mode_timing,
1472                              struct display_timing panel_timing)
1473 {
1474         struct io_register *reg = NULL;
1475         int i;
1476         int viafb_load_reg_Num = 0;
1477         int reg_value = 0;
1478
1479         if (viaparinfo->lvds_setting_info->display_method == LCD_EXPANDSION) {
1480                 /* Expansion */
1481                 for (i = 12; i < 20; i++) {
1482                         switch (i) {
1483                         case H_TOTAL_SHADOW_INDEX:
1484                                 reg_value =
1485                                     IGA2_HOR_TOTAL_SHADOW_FORMULA
1486                                     (panel_timing.hor_total);
1487                                 viafb_load_reg_Num =
1488                                     iga2_shadow_crtc_reg.hor_total_shadow.
1489                                     reg_num;
1490                                 reg = iga2_shadow_crtc_reg.hor_total_shadow.reg;
1491                                 break;
1492                         case H_BLANK_END_SHADOW_INDEX:
1493                                 reg_value =
1494                                     IGA2_HOR_BLANK_END_SHADOW_FORMULA
1495                                     (panel_timing.hor_blank_start,
1496                                      panel_timing.hor_blank_end);
1497                                 viafb_load_reg_Num =
1498                                     iga2_shadow_crtc_reg.
1499                                     hor_blank_end_shadow.reg_num;
1500                                 reg =
1501                                     iga2_shadow_crtc_reg.
1502                                     hor_blank_end_shadow.reg;
1503                                 break;
1504                         case V_TOTAL_SHADOW_INDEX:
1505                                 reg_value =
1506                                     IGA2_VER_TOTAL_SHADOW_FORMULA
1507                                     (panel_timing.ver_total);
1508                                 viafb_load_reg_Num =
1509                                     iga2_shadow_crtc_reg.ver_total_shadow.
1510                                     reg_num;
1511                                 reg = iga2_shadow_crtc_reg.ver_total_shadow.reg;
1512                                 break;
1513                         case V_ADDR_SHADOW_INDEX:
1514                                 reg_value =
1515                                     IGA2_VER_ADDR_SHADOW_FORMULA
1516                                     (panel_timing.ver_addr);
1517                                 viafb_load_reg_Num =
1518                                     iga2_shadow_crtc_reg.ver_addr_shadow.
1519                                     reg_num;
1520                                 reg = iga2_shadow_crtc_reg.ver_addr_shadow.reg;
1521                                 break;
1522                         case V_BLANK_SATRT_SHADOW_INDEX:
1523                                 reg_value =
1524                                     IGA2_VER_BLANK_START_SHADOW_FORMULA
1525                                     (panel_timing.ver_blank_start);
1526                                 viafb_load_reg_Num =
1527                                     iga2_shadow_crtc_reg.
1528                                     ver_blank_start_shadow.reg_num;
1529                                 reg =
1530                                     iga2_shadow_crtc_reg.
1531                                     ver_blank_start_shadow.reg;
1532                                 break;
1533                         case V_BLANK_END_SHADOW_INDEX:
1534                                 reg_value =
1535                                     IGA2_VER_BLANK_END_SHADOW_FORMULA
1536                                     (panel_timing.ver_blank_start,
1537                                      panel_timing.ver_blank_end);
1538                                 viafb_load_reg_Num =
1539                                     iga2_shadow_crtc_reg.
1540                                     ver_blank_end_shadow.reg_num;
1541                                 reg =
1542                                     iga2_shadow_crtc_reg.
1543                                     ver_blank_end_shadow.reg;
1544                                 break;
1545                         case V_SYNC_SATRT_SHADOW_INDEX:
1546                                 reg_value =
1547                                     IGA2_VER_SYNC_START_SHADOW_FORMULA
1548                                     (panel_timing.ver_sync_start);
1549                                 viafb_load_reg_Num =
1550                                     iga2_shadow_crtc_reg.
1551                                     ver_sync_start_shadow.reg_num;
1552                                 reg =
1553                                     iga2_shadow_crtc_reg.
1554                                     ver_sync_start_shadow.reg;
1555                                 break;
1556                         case V_SYNC_END_SHADOW_INDEX:
1557                                 reg_value =
1558                                     IGA2_VER_SYNC_END_SHADOW_FORMULA
1559                                     (panel_timing.ver_sync_start,
1560                                      panel_timing.ver_sync_end);
1561                                 viafb_load_reg_Num =
1562                                     iga2_shadow_crtc_reg.
1563                                     ver_sync_end_shadow.reg_num;
1564                                 reg =
1565                                     iga2_shadow_crtc_reg.
1566                                     ver_sync_end_shadow.reg;
1567                                 break;
1568                         }
1569                         viafb_load_reg(reg_value,
1570                                 viafb_load_reg_Num, reg, VIACR);
1571                 }
1572         } else {                /* Centering */
1573                 for (i = 12; i < 20; i++) {
1574                         switch (i) {
1575                         case H_TOTAL_SHADOW_INDEX:
1576                                 reg_value =
1577                                     IGA2_HOR_TOTAL_SHADOW_FORMULA
1578                                     (panel_timing.hor_total);
1579                                 viafb_load_reg_Num =
1580                                     iga2_shadow_crtc_reg.hor_total_shadow.
1581                                     reg_num;
1582                                 reg = iga2_shadow_crtc_reg.hor_total_shadow.reg;
1583                                 break;
1584                         case H_BLANK_END_SHADOW_INDEX:
1585                                 reg_value =
1586                                     IGA2_HOR_BLANK_END_SHADOW_FORMULA
1587                                     (panel_timing.hor_blank_start,
1588                                      panel_timing.hor_blank_end);
1589                                 viafb_load_reg_Num =
1590                                     iga2_shadow_crtc_reg.
1591                                     hor_blank_end_shadow.reg_num;
1592                                 reg =
1593                                     iga2_shadow_crtc_reg.
1594                                     hor_blank_end_shadow.reg;
1595                                 break;
1596                         case V_TOTAL_SHADOW_INDEX:
1597                                 reg_value =
1598                                     IGA2_VER_TOTAL_SHADOW_FORMULA
1599                                     (panel_timing.ver_total);
1600                                 viafb_load_reg_Num =
1601                                     iga2_shadow_crtc_reg.ver_total_shadow.
1602                                     reg_num;
1603                                 reg = iga2_shadow_crtc_reg.ver_total_shadow.reg;
1604                                 break;
1605                         case V_ADDR_SHADOW_INDEX:
1606                                 reg_value =
1607                                     IGA2_VER_ADDR_SHADOW_FORMULA
1608                                     (mode_timing.ver_addr);
1609                                 viafb_load_reg_Num =
1610                                     iga2_shadow_crtc_reg.ver_addr_shadow.
1611                                     reg_num;
1612                                 reg = iga2_shadow_crtc_reg.ver_addr_shadow.reg;
1613                                 break;
1614                         case V_BLANK_SATRT_SHADOW_INDEX:
1615                                 reg_value =
1616                                     IGA2_VER_BLANK_START_SHADOW_FORMULA
1617                                     (mode_timing.ver_blank_start);
1618                                 viafb_load_reg_Num =
1619                                     iga2_shadow_crtc_reg.
1620                                     ver_blank_start_shadow.reg_num;
1621                                 reg =
1622                                     iga2_shadow_crtc_reg.
1623                                     ver_blank_start_shadow.reg;
1624                                 break;
1625                         case V_BLANK_END_SHADOW_INDEX:
1626                                 reg_value =
1627                                     IGA2_VER_BLANK_END_SHADOW_FORMULA
1628                                     (panel_timing.ver_blank_start,
1629                                      panel_timing.ver_blank_end);
1630                                 viafb_load_reg_Num =
1631                                     iga2_shadow_crtc_reg.
1632                                     ver_blank_end_shadow.reg_num;
1633                                 reg =
1634                                     iga2_shadow_crtc_reg.
1635                                     ver_blank_end_shadow.reg;
1636                                 break;
1637                         case V_SYNC_SATRT_SHADOW_INDEX:
1638                                 reg_value =
1639                                     IGA2_VER_SYNC_START_SHADOW_FORMULA(
1640                                     (panel_timing.ver_sync_start -
1641                                     panel_timing.ver_blank_start) +
1642                                     (panel_timing.ver_addr -
1643                                     mode_timing.ver_addr) / 2 +
1644                                     mode_timing.ver_addr);
1645                                 viafb_load_reg_Num =
1646                                     iga2_shadow_crtc_reg.ver_sync_start_shadow.
1647                                     reg_num;
1648                                 reg =
1649                                     iga2_shadow_crtc_reg.ver_sync_start_shadow.
1650                                     reg;
1651                                 break;
1652                         case V_SYNC_END_SHADOW_INDEX:
1653                                 reg_value =
1654                                     IGA2_VER_SYNC_END_SHADOW_FORMULA(
1655                                     (panel_timing.ver_sync_start -
1656                                     panel_timing.ver_blank_start) +
1657                                     (panel_timing.ver_addr -
1658                                     mode_timing.ver_addr) / 2 +
1659                                     mode_timing.ver_addr,
1660                                     panel_timing.ver_sync_end);
1661                                 viafb_load_reg_Num =
1662                                     iga2_shadow_crtc_reg.ver_sync_end_shadow.
1663                                     reg_num;
1664                                 reg =
1665                                     iga2_shadow_crtc_reg.ver_sync_end_shadow.
1666                                     reg;
1667                                 break;
1668                         }
1669                         viafb_load_reg(reg_value,
1670                                 viafb_load_reg_Num, reg, VIACR);
1671                 }
1672         }
1673 }
1674
1675 bool viafb_lcd_get_mobile_state(bool *mobile)
1676 {
1677         unsigned char *romptr, *tableptr;
1678         u8 core_base;
1679         unsigned char *biosptr;
1680         /* Rom address */
1681         u32 romaddr = 0x000C0000;
1682         u16 start_pattern = 0;
1683
1684         biosptr = ioremap(romaddr, 0x10000);
1685
1686         memcpy(&start_pattern, biosptr, 2);
1687         /* Compare pattern */
1688         if (start_pattern == 0xAA55) {
1689                 /* Get the start of Table */
1690                 /* 0x1B means BIOS offset position */
1691                 romptr = biosptr + 0x1B;
1692                 tableptr = biosptr + *((u16 *) romptr);
1693
1694                 /* Get the start of biosver structure */
1695                 /* 18 means BIOS version position. */
1696                 romptr = tableptr + 18;
1697                 romptr = biosptr + *((u16 *) romptr);
1698
1699                 /* The offset should be 44, but the
1700                    actual image is less three char. */
1701                 /* pRom += 44; */
1702                 romptr += 41;
1703
1704                 core_base = *romptr++;
1705
1706                 if (core_base & 0x8)
1707                         *mobile = false;
1708                 else
1709                         *mobile = true;
1710                 /* release memory */
1711                 iounmap(biosptr);
1712
1713                 return true;
1714         } else {
1715                 iounmap(biosptr);
1716                 return false;
1717         }
1718 }
1719
1720 static void viafb_load_scaling_factor_for_p4m900(int set_hres,
1721         int set_vres, int panel_hres, int panel_vres)
1722 {
1723         int h_scaling_factor;
1724         int v_scaling_factor;
1725         u8 cra2 = 0;
1726         u8 cr77 = 0;
1727         u8 cr78 = 0;
1728         u8 cr79 = 0;
1729         u8 cr9f = 0;
1730         /* Check if expansion for horizontal */
1731         if (set_hres < panel_hres) {
1732                 /* Load Horizontal Scaling Factor */
1733
1734                 /* For VIA_K8M800 or later chipsets. */
1735                 h_scaling_factor =
1736                     K800_LCD_HOR_SCF_FORMULA(set_hres, panel_hres);
1737                 /* HSCaleFactor[1:0] at CR9F[1:0] */
1738                 cr9f = h_scaling_factor & 0x0003;
1739                 /* HSCaleFactor[9:2] at CR77[7:0] */
1740                 cr77 = (h_scaling_factor & 0x03FC) >> 2;
1741                 /* HSCaleFactor[11:10] at CR79[5:4] */
1742                 cr79 = (h_scaling_factor & 0x0C00) >> 10;
1743                 cr79 <<= 4;
1744
1745                 /* Horizontal scaling enabled */
1746                 cra2 = 0xC0;
1747
1748                 DEBUG_MSG(KERN_INFO "Horizontal Scaling value = %d\n",
1749                           h_scaling_factor);
1750         } else {
1751                 /* Horizontal scaling disabled */
1752                 cra2 = 0x00;
1753         }
1754
1755         /* Check if expansion for vertical */
1756         if (set_vres < panel_vres) {
1757                 /* Load Vertical Scaling Factor */
1758
1759                 /* For VIA_K8M800 or later chipsets. */
1760                 v_scaling_factor =
1761                     K800_LCD_VER_SCF_FORMULA(set_vres, panel_vres);
1762
1763                 /* Vertical scaling enabled */
1764                 cra2 |= 0x08;
1765                 /* VSCaleFactor[0] at CR79[3] */
1766                 cr79 |= ((v_scaling_factor & 0x0001) << 3);
1767                 /* VSCaleFactor[8:1] at CR78[7:0] */
1768                 cr78 |= (v_scaling_factor & 0x01FE) >> 1;
1769                 /* VSCaleFactor[10:9] at CR79[7:6] */
1770                 cr79 |= ((v_scaling_factor & 0x0600) >> 9) << 6;
1771
1772                 DEBUG_MSG(KERN_INFO "Vertical Scaling value = %d\n",
1773                           v_scaling_factor);
1774         } else {
1775                 /* Vertical scaling disabled */
1776                 cra2 |= 0x00;
1777         }
1778
1779         viafb_write_reg_mask(CRA2, VIACR, cra2, BIT3 + BIT6 + BIT7);
1780         viafb_write_reg_mask(CR77, VIACR, cr77, 0xFF);
1781         viafb_write_reg_mask(CR78, VIACR, cr78, 0xFF);
1782         viafb_write_reg_mask(CR79, VIACR, cr79, 0xF8);
1783         viafb_write_reg_mask(CR9F, VIACR, cr9f, BIT0 + BIT1);
1784 }