video: tegra: host: Move device data to nvhost_device
[linux-2.6.git] / drivers / video / tegra / host / t30 / t30.c
1 /*
2  * drivers/video/tegra/host/t30/t30.c
3  *
4  * Tegra Graphics Init for T30 Architecture Chips
5  *
6  * Copyright (c) 2011, NVIDIA Corporation.
7  *
8  * This program is free software; you can redistribute it and/or modify
9  * it under the terms of the GNU General Public License as published by
10  * the Free Software Foundation; either version 2 of the License, or
11  * (at your option) any later version.
12  *
13  * This program is distributed in the hope that it will be useful, but WITHOUT
14  * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
15  * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
16  * more details.
17  *
18  * You should have received a copy of the GNU General Public License along
19  * with this program; if not, write to the Free Software Foundation, Inc.,
20  * 51 Franklin Street, Fifth Floor, Boston, MA  02110-1301, USA.
21  */
22
23 #include <linux/mutex.h>
24 #include <mach/powergate.h>
25 #include "dev.h"
26 #include "t30.h"
27 #include "gr3d/gr3d.h"
28 #include "mpe/mpe.h"
29 #include "gr3d/gr3d_t30.h"
30 #include "gr3d/scale3d.h"
31 #include "host1x/host1x_hardware.h"
32 #include "host1x/host1x_cdma.h"
33 #include "host1x/host1x_syncpt.h"
34 #include "gr3d/scale3d.h"
35 #include "../chip_support.h"
36
37 #define NVMODMUTEX_2D_FULL   (1)
38 #define NVMODMUTEX_2D_SIMPLE (2)
39 #define NVMODMUTEX_2D_SB_A   (3)
40 #define NVMODMUTEX_2D_SB_B   (4)
41 #define NVMODMUTEX_3D        (5)
42 #define NVMODMUTEX_DISPLAYA  (6)
43 #define NVMODMUTEX_DISPLAYB  (7)
44 #define NVMODMUTEX_VI        (8)
45 #define NVMODMUTEX_DSI       (9)
46
47 #ifndef TEGRA_POWERGATE_3D1
48 #define TEGRA_POWERGATE_3D1 -1
49 #endif
50
51 static struct nvhost_device devices[] = {
52 {
53         /* channel 0 */
54         .name          = "display",
55         .id            = -1,
56         .syncpts       = BIT(NVSYNCPT_DISP0_A) | BIT(NVSYNCPT_DISP1_A) |
57                          BIT(NVSYNCPT_DISP0_B) | BIT(NVSYNCPT_DISP1_B) |
58                          BIT(NVSYNCPT_DISP0_C) | BIT(NVSYNCPT_DISP1_C) |
59                          BIT(NVSYNCPT_VBLANK0) | BIT(NVSYNCPT_VBLANK1),
60         .modulemutexes = BIT(NVMODMUTEX_DISPLAYA) | BIT(NVMODMUTEX_DISPLAYB),
61         NVHOST_MODULE_NO_POWERGATE_IDS,
62         NVHOST_DEFAULT_CLOCKGATE_DELAY,
63 },
64 {
65         /* channel 1 */
66         .name          = "gr3d",
67         .id            = -1,
68         .syncpts       = BIT(NVSYNCPT_3D),
69         .waitbases     = BIT(NVWAITBASE_3D),
70         .modulemutexes = BIT(NVMODMUTEX_3D),
71         .class         = NV_GRAPHICS_3D_CLASS_ID,
72         .prepare_poweroff = nvhost_gr3d_prepare_power_off,
73         .busy = nvhost_scale3d_notify_busy,
74         .idle = nvhost_scale3d_notify_idle,
75         .init = nvhost_scale3d_init,
76         .deinit = nvhost_scale3d_deinit,
77         .suspend = nvhost_scale3d_suspend,
78         .clocks = {{"gr3d", UINT_MAX},
79                         {"gr3d2", UINT_MAX},
80                         {"emc", UINT_MAX} },
81         .powergate_ids = {TEGRA_POWERGATE_3D,
82                         TEGRA_POWERGATE_3D1},
83         NVHOST_DEFAULT_CLOCKGATE_DELAY,
84         .can_powergate = true,
85         .powergate_delay = 100,
86 },
87 {
88         /* channel 2 */
89         .name          = "gr2d",
90         .id            = -1,
91         .syncpts       = BIT(NVSYNCPT_2D_0) | BIT(NVSYNCPT_2D_1),
92         .waitbases     = BIT(NVWAITBASE_2D_0) | BIT(NVWAITBASE_2D_1),
93         .modulemutexes = BIT(NVMODMUTEX_2D_FULL) | BIT(NVMODMUTEX_2D_SIMPLE) |
94                          BIT(NVMODMUTEX_2D_SB_A) | BIT(NVMODMUTEX_2D_SB_B),
95         .clocks = {{"gr2d", 0},
96                         {"epp", 0},
97                         {"emc", 300000000} },
98         NVHOST_MODULE_NO_POWERGATE_IDS,
99         .clockgate_delay = 0,
100 },
101 {
102         /* channel 3 */
103         .name          =  "isp",
104         .id            = -1,
105         .syncpts       = 0,
106         NVHOST_MODULE_NO_POWERGATE_IDS,
107         NVHOST_DEFAULT_CLOCKGATE_DELAY,
108 },
109 {
110         /* channel 4 */
111         .name          = "vi",
112         .id            = -1,
113         .syncpts       = BIT(NVSYNCPT_CSI_VI_0) | BIT(NVSYNCPT_CSI_VI_1) |
114                          BIT(NVSYNCPT_VI_ISP_0) | BIT(NVSYNCPT_VI_ISP_1) |
115                          BIT(NVSYNCPT_VI_ISP_2) | BIT(NVSYNCPT_VI_ISP_3) |
116                          BIT(NVSYNCPT_VI_ISP_4),
117         .modulemutexes = BIT(NVMODMUTEX_VI),
118         .exclusive     = true,
119         NVHOST_MODULE_NO_POWERGATE_IDS,
120         NVHOST_DEFAULT_CLOCKGATE_DELAY,
121 },
122 {
123         /* channel 5 */
124         .name          = "mpe",
125         .id            = -1,
126         .syncpts       = BIT(NVSYNCPT_MPE) | BIT(NVSYNCPT_MPE_EBM_EOF) |
127                          BIT(NVSYNCPT_MPE_WR_SAFE),
128         .waitbases     = BIT(NVWAITBASE_MPE),
129         .class         = NV_VIDEO_ENCODE_MPEG_CLASS_ID,
130         .waitbasesync  = true,
131         .keepalive     = true,
132         .prepare_poweroff = nvhost_mpe_prepare_power_off,
133         .clocks = {{"mpe", UINT_MAX}, {"emc", UINT_MAX}, {} },
134         .powergate_ids  = {TEGRA_POWERGATE_MPE, -1},
135         NVHOST_DEFAULT_CLOCKGATE_DELAY,
136         .can_powergate  = true,
137         .powergate_delay = 100,
138 },
139 {
140         /* channel 6 */
141         .name          = "dsi",
142         .id            = -1,
143         .syncpts       = BIT(NVSYNCPT_DSI),
144         .modulemutexes = BIT(NVMODMUTEX_DSI),
145         NVHOST_MODULE_NO_POWERGATE_IDS,
146         NVHOST_DEFAULT_CLOCKGATE_DELAY,
147 } };
148
149 #define NVHOST_CHANNEL_BASE 0
150
151 static inline int t30_nvhost_hwctx_handler_init(
152         struct nvhost_hwctx_handler *h,
153         const char *module)
154 {
155         if (strcmp(module, "gr3d") == 0)
156                 return nvhost_gr3d_t30_ctxhandler_init(h);
157         else if (strcmp(module, "mpe") == 0)
158                 return nvhost_mpe_ctxhandler_init(h);
159
160         return 0;
161 }
162
163 static inline void __iomem *t30_channel_aperture(void __iomem *p, int ndx)
164 {
165         ndx += NVHOST_CHANNEL_BASE;
166         p += NV_HOST1X_CHANNEL0_BASE;
167         p += ndx * NV_HOST1X_CHANNEL_MAP_SIZE_BYTES;
168         return p;
169 }
170
171 static int t30_channel_init(struct nvhost_channel *ch,
172                             struct nvhost_master *dev, int index)
173 {
174         ch->chid = index;
175         ch->dev = &devices[index];
176         mutex_init(&ch->reflock);
177         mutex_init(&ch->submitlock);
178
179         nvhost_device_register(ch->dev);
180         ch->aperture = t30_channel_aperture(dev->aperture, index);
181
182         return t30_nvhost_hwctx_handler_init(&ch->ctxhandler, ch->dev->name);
183 }
184
185 int nvhost_init_t30_channel_support(struct nvhost_master *host)
186 {
187         int result = nvhost_init_t20_channel_support(host);
188         host->op.channel.init = t30_channel_init;
189
190         return result;
191 }
192 int nvhost_init_t30_debug_support(struct nvhost_master *host)
193 {
194         nvhost_init_t20_debug_support(host);
195         host->op.debug.debug_init = nvhost_scale3d_debug_init;
196
197         return 0;
198 }
199
200 int nvhost_init_t30_support(struct nvhost_master *host)
201 {
202         int err;
203
204         /* don't worry about cleaning up on failure... "remove" does it. */
205         err = nvhost_init_t30_channel_support(host);
206         if (err)
207                 return err;
208         err = host1x_init_cdma_support(host);
209         if (err)
210                 return err;
211         err = nvhost_init_t30_debug_support(host);
212         if (err)
213                 return err;
214         err = host1x_init_syncpt_support(host);
215         if (err)
216                 return err;
217         err = nvhost_init_t20_intr_support(host);
218         if (err)
219                 return err;
220         err = nvhost_init_t20_cpuaccess_support(host);
221         if (err)
222                 return err;
223         return 0;
224 }