arm: tegra: pcie: Rename/Restructure the driver
[linux-2.6.git] / drivers / video / tegra / host / t30 / t30.c
1 /*
2  * drivers/video/tegra/host/t30/t30.c
3  *
4  * Tegra Graphics Init for T30 Architecture Chips
5  *
6  * Copyright (c) 2011-2012, NVIDIA Corporation.
7  *
8  * This program is free software; you can redistribute it and/or modify it
9  * under the terms and conditions of the GNU General Public License,
10  * version 2, as published by the Free Software Foundation.
11  *
12  * This program is distributed in the hope it will be useful, but WITHOUT
13  * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
14  * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
15  * more details.
16  *
17  * You should have received a copy of the GNU General Public License
18  * along with this program.  If not, see <http://www.gnu.org/licenses/>.
19  */
20
21 #include <linux/nvhost_ioctl.h>
22 #include <mach/powergate.h>
23 #include <mach/iomap.h>
24 #include "t20/t20.h"
25 #include "t30.h"
26 #include "gr3d/gr3d_t30.h"
27 #include "gr3d/scale3d.h"
28 #include "mpe/mpe.h"
29 #include "host1x/host1x.h"
30 #include "host1x/host1x01_hardware.h"
31 #include "chip_support.h"
32 #include "nvhost_channel.h"
33 #include "nvhost_memmgr.h"
34 #include "host1x/host1x_syncpt.h"
35
36 #define NVMODMUTEX_2D_FULL      (1)
37 #define NVMODMUTEX_2D_SIMPLE    (2)
38 #define NVMODMUTEX_2D_SB_A      (3)
39 #define NVMODMUTEX_2D_SB_B      (4)
40 #define NVMODMUTEX_3D           (5)
41 #define NVMODMUTEX_DISPLAYA     (6)
42 #define NVMODMUTEX_DISPLAYB     (7)
43 #define NVMODMUTEX_VI           (8)
44 #define NVMODMUTEX_DSI          (9)
45
46 static int t30_num_alloc_channels = 0;
47
48 static struct resource tegra_host1x01_resources[] = {
49         {
50                 .start = TEGRA_HOST1X_BASE,
51                 .end = TEGRA_HOST1X_BASE + TEGRA_HOST1X_SIZE - 1,
52                 .flags = IORESOURCE_MEM,
53         },
54         {
55                 .start = INT_SYNCPT_THRESH_BASE,
56                 .end = INT_SYNCPT_THRESH_BASE + INT_SYNCPT_THRESH_NR - 1,
57                 .flags = IORESOURCE_IRQ,
58         },
59         {
60                 .start = INT_HOST1X_MPCORE_GENERAL,
61                 .end = INT_HOST1X_MPCORE_GENERAL,
62                 .flags = IORESOURCE_IRQ,
63         },
64 };
65
66 static const char *s_syncpt_names[32] = {
67         "gfx_host",
68         "", "", "", "", "", "", "",
69         "disp0_a", "disp1_a", "avp_0",
70         "csi_vi_0", "csi_vi_1",
71         "vi_isp_0", "vi_isp_1", "vi_isp_2", "vi_isp_3", "vi_isp_4",
72         "2d_0", "2d_1",
73         "disp0_b", "disp1_b",
74         "3d",
75         "mpe",
76         "disp0_c", "disp1_c",
77         "vblank0", "vblank1",
78         "mpe_ebm_eof", "mpe_wr_safe",
79         "2d_tinyblt",
80         "dsi"
81 };
82
83 static struct host1x_device_info host1x01_info = {
84         .nb_channels    = 8,
85         .nb_pts         = 32,
86         .nb_mlocks      = 16,
87         .nb_bases       = 8,
88         .syncpt_names   = s_syncpt_names,
89         .client_managed = NVSYNCPTS_CLIENT_MANAGED,
90 };
91
92 static struct nvhost_device tegra_host1x01_device = {
93         .dev            = {.platform_data = &host1x01_info},
94         .name           = "host1x",
95         .id             = -1,
96         .resource       = tegra_host1x01_resources,
97         .num_resources  = ARRAY_SIZE(tegra_host1x01_resources),
98         .clocks         = {{"host1x", UINT_MAX}, {} },
99         NVHOST_MODULE_NO_POWERGATE_IDS,
100 };
101
102 static struct nvhost_device tegra_display01_device = {
103         .name           = "display",
104         .id             = -1,
105         .index          = 0,
106         .syncpts        = BIT(NVSYNCPT_DISP0_A) | BIT(NVSYNCPT_DISP1_A) |
107                           BIT(NVSYNCPT_DISP0_B) | BIT(NVSYNCPT_DISP1_B) |
108                           BIT(NVSYNCPT_DISP0_C) | BIT(NVSYNCPT_DISP1_C) |
109                           BIT(NVSYNCPT_VBLANK0) | BIT(NVSYNCPT_VBLANK1),
110         .modulemutexes  = BIT(NVMODMUTEX_DISPLAYA) | BIT(NVMODMUTEX_DISPLAYB),
111         NVHOST_MODULE_NO_POWERGATE_IDS,
112         NVHOST_DEFAULT_CLOCKGATE_DELAY,
113         .moduleid       = NVHOST_MODULE_NONE,
114 };
115
116 static struct nvhost_device tegra_gr3d02_device = {
117         .name           = "gr3d",
118         .version        = 2,
119         .id             = -1,
120         .index          = 1,
121         .syncpts        = BIT(NVSYNCPT_3D),
122         .waitbases      = BIT(NVWAITBASE_3D),
123         .modulemutexes  = BIT(NVMODMUTEX_3D),
124         .class          = NV_GRAPHICS_3D_CLASS_ID,
125         .clocks         = { {"gr3d", UINT_MAX},
126                             {"gr3d2", UINT_MAX},
127                             {"emc", UINT_MAX} },
128         .powergate_ids = { TEGRA_POWERGATE_3D,
129                            TEGRA_POWERGATE_3D1 },
130         NVHOST_DEFAULT_CLOCKGATE_DELAY,
131         .can_powergate = true,
132         .powerup_reset = true,
133         .powergate_delay = 250,
134         .moduleid       = NVHOST_MODULE_NONE,
135 };
136
137 static struct nvhost_device tegra_gr2d02_device = {
138         .name           = "gr2d",
139         .id             = -1,
140         .index          = 2,
141         .syncpts        = BIT(NVSYNCPT_2D_0) | BIT(NVSYNCPT_2D_1),
142         .waitbases      = BIT(NVWAITBASE_2D_0) | BIT(NVWAITBASE_2D_1),
143         .modulemutexes  = BIT(NVMODMUTEX_2D_FULL) | BIT(NVMODMUTEX_2D_SIMPLE) |
144                           BIT(NVMODMUTEX_2D_SB_A) | BIT(NVMODMUTEX_2D_SB_B),
145         .clocks         = { {"gr2d", UINT_MAX},
146                           {"epp", 0},
147                           {"emc", 300000000} },
148         NVHOST_MODULE_NO_POWERGATE_IDS,
149         .clockgate_delay = 0,
150         .moduleid       = NVHOST_MODULE_NONE,
151 };
152
153 static struct resource isp_resources_t20[] = {
154         {
155                 .name = "regs",
156                 .start = TEGRA_ISP_BASE,
157                 .end = TEGRA_ISP_BASE + TEGRA_ISP_SIZE - 1,
158                 .flags = IORESOURCE_MEM,
159         }
160 };
161
162 static struct nvhost_device tegra_isp01_device = {
163         .name           = "isp",
164         .id             = -1,
165         .resource = isp_resources_t20,
166         .num_resources = ARRAY_SIZE(isp_resources_t20),
167         .index          = 3,
168         .syncpts        = 0,
169         NVHOST_MODULE_NO_POWERGATE_IDS,
170         NVHOST_DEFAULT_CLOCKGATE_DELAY,
171         .moduleid       = NVHOST_MODULE_ISP,
172 };
173
174 static struct resource vi_resources[] = {
175         {
176                 .name = "regs",
177                 .start = TEGRA_VI_BASE,
178                 .end = TEGRA_VI_BASE + TEGRA_VI_SIZE - 1,
179                 .flags = IORESOURCE_MEM,
180         },
181 };
182
183 static struct nvhost_device tegra_vi01_device = {
184         .name           = "vi",
185         .resource = vi_resources,
186         .num_resources = ARRAY_SIZE(vi_resources),
187         .id             = -1,
188         .index          = 4,
189         .syncpts        = BIT(NVSYNCPT_CSI_VI_0) | BIT(NVSYNCPT_CSI_VI_1) |
190                           BIT(NVSYNCPT_VI_ISP_0) | BIT(NVSYNCPT_VI_ISP_1) |
191                           BIT(NVSYNCPT_VI_ISP_2) | BIT(NVSYNCPT_VI_ISP_3) |
192                           BIT(NVSYNCPT_VI_ISP_4),
193         .modulemutexes  = BIT(NVMODMUTEX_VI),
194         .exclusive      = true,
195         NVHOST_MODULE_NO_POWERGATE_IDS,
196         NVHOST_DEFAULT_CLOCKGATE_DELAY,
197         .moduleid       = NVHOST_MODULE_VI,
198 };
199
200 static struct resource tegra_mpe01_resources[] = {
201         {
202                 .name = "regs",
203                 .start = TEGRA_MPE_BASE,
204                 .end = TEGRA_MPE_BASE + TEGRA_MPE_SIZE - 1,
205                 .flags = IORESOURCE_MEM,
206         },
207 };
208
209 static struct nvhost_device tegra_mpe02_device = {
210         .name           = "mpe",
211         .version        = 2,
212         .id             = -1,
213         .resource       = tegra_mpe01_resources,
214         .num_resources  = ARRAY_SIZE(tegra_mpe01_resources),
215         .index          = 5,
216         .syncpts        = BIT(NVSYNCPT_MPE) | BIT(NVSYNCPT_MPE_EBM_EOF) |
217                           BIT(NVSYNCPT_MPE_WR_SAFE),
218         .waitbases      = BIT(NVWAITBASE_MPE),
219         .class          = NV_VIDEO_ENCODE_MPEG_CLASS_ID,
220         .waitbasesync   = true,
221         .keepalive      = true,
222         .clocks         = { {"mpe", UINT_MAX},
223                             {"emc", UINT_MAX} },
224         .powergate_ids  = {TEGRA_POWERGATE_MPE, -1},
225         NVHOST_DEFAULT_CLOCKGATE_DELAY,
226         .can_powergate  = true,
227         .powergate_delay = 100,
228         .moduleid       = NVHOST_MODULE_MPE,
229 };
230
231 static struct nvhost_device tegra_dsi01_device = {
232         .name           = "dsi",
233         .id             = -1,
234         .index          = 6,
235         .syncpts        = BIT(NVSYNCPT_DSI),
236         .modulemutexes  = BIT(NVMODMUTEX_DSI),
237         NVHOST_MODULE_NO_POWERGATE_IDS,
238         NVHOST_DEFAULT_CLOCKGATE_DELAY,
239         .moduleid       = NVHOST_MODULE_NONE,
240 };
241
242 static struct nvhost_device *t30_devices[] = {
243         &tegra_host1x01_device,
244         &tegra_display01_device,
245         &tegra_gr3d02_device,
246         &tegra_gr2d02_device,
247         &tegra_isp01_device,
248         &tegra_vi01_device,
249         &tegra_mpe02_device,
250         &tegra_dsi01_device,
251 };
252
253 int tegra3_register_host1x_devices(void)
254 {
255         return nvhost_add_devices(t30_devices, ARRAY_SIZE(t30_devices));
256 }
257
258 static void t30_free_nvhost_channel(struct nvhost_channel *ch)
259 {
260         nvhost_free_channel_internal(ch, &t30_num_alloc_channels);
261 }
262
263 static struct nvhost_channel *t30_alloc_nvhost_channel(
264                 struct nvhost_device *dev)
265 {
266         return nvhost_alloc_channel_internal(dev->index,
267                 nvhost_get_host(dev)->info.nb_channels,
268                 &t30_num_alloc_channels);
269 }
270
271 #include "host1x/host1x_channel.c"
272 #include "host1x/host1x_cdma.c"
273 #include "host1x/host1x_debug.c"
274 #include "host1x/host1x_syncpt.c"
275 #include "host1x/host1x_intr.c"
276
277 int nvhost_init_t30_support(struct nvhost_master *host,
278         struct nvhost_chip_support *op)
279 {
280         int err;
281
282         op->channel = host1x_channel_ops;
283         op->cdma = host1x_cdma_ops;
284         op->push_buffer = host1x_pushbuffer_ops;
285         op->debug = host1x_debug_ops;
286         op->debug.debug_init = nvhost_scale3d_debug_init;
287         host->sync_aperture = host->aperture + HOST1X_CHANNEL_SYNC_REG_BASE;
288         op->syncpt = host1x_syncpt_ops;
289         op->intr = host1x_intr_ops;
290         err = nvhost_memmgr_init(op);
291         if (err)
292                 return err;
293
294         op->nvhost_dev.alloc_nvhost_channel = t30_alloc_nvhost_channel;
295         op->nvhost_dev.free_nvhost_channel = t30_free_nvhost_channel;
296
297         return 0;
298 }