video: tegra: host: Remove Tegra11 ops from master
[linux-2.6.git] / drivers / video / tegra / host / t114 / t114.c
1 /*
2  * drivers/video/tegra/host/t114/t114.c
3  *
4  * Tegra Graphics Init for T114 Architecture Chips
5  *
6  * Copyright (c) 2010-2012, NVIDIA Corporation.
7  *
8  * This program is free software; you can redistribute it and/or modify
9  * it under the terms of the GNU General Public License as published by
10  * the Free Software Foundation; either version 2 of the License, or
11  * (at your option) any later version.
12  *
13  * This program is distributed in the hope that it will be useful, but WITHOUT
14  * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
15  * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
16  * more details.
17  *
18  * You should have received a copy of the GNU General Public License along
19  * with this program; if not, write to the Free Software Foundation, Inc.,
20  * 51 Franklin Street, Fifth Floor, Boston, MA  02110-1301, USA.
21  */
22
23 #include <linux/mutex.h>
24 #include <mach/powergate.h>
25 #include "dev.h"
26 #include "host1x/host1x_cdma.h"
27 #include "t20/t20.h"
28 #include "t30/t30.h"
29 #include "t114.h"
30 #include "host1x/host1x_hardware.h"
31 #include "host1x/host1x_syncpt.h"
32 #include "gr3d/gr3d.h"
33 #include "gr3d/gr3d_t114.h"
34 #include "gr3d/scale3d.h"
35 #include "msenc/msenc.h"
36 #include "tsec/tsec.h"
37
38 #define NVMODMUTEX_2D_FULL   (1)
39 #define NVMODMUTEX_2D_SIMPLE (2)
40 #define NVMODMUTEX_2D_SB_A   (3)
41 #define NVMODMUTEX_2D_SB_B   (4)
42 #define NVMODMUTEX_3D        (5)
43 #define NVMODMUTEX_DISPLAYA  (6)
44 #define NVMODMUTEX_DISPLAYB  (7)
45 #define NVMODMUTEX_VI        (8)
46 #define NVMODMUTEX_DSI       (9)
47
48 #define HOST_EMC_FLOOR 300000000
49
50 static struct nvhost_device devices[] = {
51 {
52         /* channel 0 */
53         .name          = "display",
54         .id            = -1,
55         .index         = 0,
56         .syncpts       = BIT(NVSYNCPT_DISP0_A) | BIT(NVSYNCPT_DISP1_A) |
57                          BIT(NVSYNCPT_DISP0_B) | BIT(NVSYNCPT_DISP1_B) |
58                          BIT(NVSYNCPT_DISP0_C) | BIT(NVSYNCPT_DISP1_C) |
59                          BIT(NVSYNCPT_VBLANK0) | BIT(NVSYNCPT_VBLANK1),
60         .modulemutexes = BIT(NVMODMUTEX_DISPLAYA) | BIT(NVMODMUTEX_DISPLAYB),
61         NVHOST_MODULE_NO_POWERGATE_IDS,
62         NVHOST_DEFAULT_CLOCKGATE_DELAY,
63         .moduleid      = NVHOST_MODULE_NONE,
64 },
65 {
66         /* channel 1 */
67         .name          = "gr3d",
68         .id            = -1,
69         .index         = 1,
70         .syncpts       = BIT(NVSYNCPT_3D),
71         .waitbases     = BIT(NVWAITBASE_3D),
72         .modulemutexes = BIT(NVMODMUTEX_3D),
73         .class         = NV_GRAPHICS_3D_CLASS_ID,
74         .prepare_poweroff = nvhost_gr3d_prepare_power_off,
75         .busy = nvhost_scale3d_notify_busy,
76         .idle = nvhost_scale3d_notify_idle,
77         .init = nvhost_scale3d_init,
78         .deinit = nvhost_scale3d_deinit,
79         .alloc_hwctx_handler = t114_nvhost_3dctx_handler_init,
80         .clocks = {{"gr3d", UINT_MAX},
81                         {"emc", HOST_EMC_FLOOR} },
82         NVHOST_MODULE_NO_POWERGATE_IDS,
83         NVHOST_DEFAULT_CLOCKGATE_DELAY,
84         .moduleid      = NVHOST_MODULE_NONE,
85 },
86 {
87         /* channel 2 */
88         .name          = "gr2d",
89         .id            = -1,
90         .index         = 2,
91         .syncpts       = BIT(NVSYNCPT_2D_0) | BIT(NVSYNCPT_2D_1),
92         .waitbases     = BIT(NVWAITBASE_2D_0) | BIT(NVWAITBASE_2D_1),
93         .modulemutexes = BIT(NVMODMUTEX_2D_FULL) | BIT(NVMODMUTEX_2D_SIMPLE) |
94                          BIT(NVMODMUTEX_2D_SB_A) | BIT(NVMODMUTEX_2D_SB_B),
95         .clocks = {{"gr2d", 0},
96                         {"epp", UINT_MAX},
97                         {"emc", HOST_EMC_FLOOR} },
98         NVHOST_MODULE_NO_POWERGATE_IDS,
99         NVHOST_DEFAULT_CLOCKGATE_DELAY,
100         .moduleid      = NVHOST_MODULE_NONE,
101 },
102 {
103         /* channel 3 */
104         .name    = "isp",
105         .id      = -1,
106         .index   = 3,
107         .syncpts = 0,
108         NVHOST_MODULE_NO_POWERGATE_IDS,
109         NVHOST_DEFAULT_CLOCKGATE_DELAY,
110         .moduleid      = NVHOST_MODULE_ISP,
111 },
112 {
113         /* channel 4 */
114         .name          = "vi",
115         .id            = -1,
116         .index         = 4,
117         .syncpts       = BIT(NVSYNCPT_CSI_VI_0) | BIT(NVSYNCPT_CSI_VI_1) |
118                          BIT(NVSYNCPT_VI_ISP_0) | BIT(NVSYNCPT_VI_ISP_1) |
119                          BIT(NVSYNCPT_VI_ISP_2) | BIT(NVSYNCPT_VI_ISP_3) |
120                          BIT(NVSYNCPT_VI_ISP_4),
121         .modulemutexes = BIT(NVMODMUTEX_VI),
122         .exclusive     = true,
123         NVHOST_MODULE_NO_POWERGATE_IDS,
124         NVHOST_DEFAULT_CLOCKGATE_DELAY,
125         .moduleid      = NVHOST_MODULE_VI,
126 },
127 {
128         /* channel 5 */
129         .name          = "msenc",
130         .id            = -1,
131         .index         = 5,
132         .syncpts       = BIT(NVSYNCPT_MSENC),
133         .waitbases     = BIT(NVWAITBASE_MSENC),
134         .class         = NV_VIDEO_ENCODE_MSENC_CLASS_ID,
135         .exclusive     = false,
136         .keepalive     = true,
137         .init          = nvhost_msenc_init,
138         .deinit        = nvhost_msenc_deinit,
139         .clocks = {{"msenc", UINT_MAX}, {"emc", HOST_EMC_FLOOR} },
140         NVHOST_MODULE_NO_POWERGATE_IDS,
141         NVHOST_DEFAULT_CLOCKGATE_DELAY,
142         .moduleid      = NVHOST_MODULE_MSENC,
143 },
144 {
145         /* channel 6 */
146         .name          = "dsi",
147         .id            = -1,
148         .index         = 6,
149         .syncpts       = BIT(NVSYNCPT_DSI),
150         .modulemutexes = BIT(NVMODMUTEX_DSI),
151         NVHOST_MODULE_NO_POWERGATE_IDS,
152         NVHOST_DEFAULT_CLOCKGATE_DELAY,
153         .moduleid      = NVHOST_MODULE_NONE,
154 },
155 {
156         /* channel 7 */
157         .name          = "tsec",
158         .id            = -1,
159         .index         = 7,
160         .syncpts       = BIT(NVSYNCPT_TSEC),
161         .waitbases     = BIT(NVWAITBASE_TSEC),
162         .class         = NV_TSEC_CLASS_ID,
163         .exclusive     = false,
164         .init          = nvhost_tsec_init,
165         .deinit        = nvhost_tsec_deinit,
166         .clocks = {{"tsec", UINT_MAX}, {"emc", HOST_EMC_FLOOR} },
167         NVHOST_MODULE_NO_POWERGATE_IDS,
168         NVHOST_DEFAULT_CLOCKGATE_DELAY,
169         .moduleid      = NVHOST_MODULE_TSEC,
170 } };
171
172 static inline int t114_nvhost_hwctx_handler_init(struct nvhost_channel *ch)
173 {
174         int err = 0;
175         unsigned long syncpts = ch->dev->syncpts;
176         unsigned long waitbases = ch->dev->waitbases;
177         u32 syncpt = find_first_bit(&syncpts, BITS_PER_LONG);
178         u32 waitbase = find_first_bit(&waitbases, BITS_PER_LONG);
179
180         if (ch->dev->alloc_hwctx_handler) {
181                 ch->ctxhandler = ch->dev->alloc_hwctx_handler(syncpt,
182                                 waitbase, ch);
183                 if (!ch->ctxhandler)
184                         err = -ENOMEM;
185         }
186
187         return err;
188 }
189
190 static inline void __iomem *t114_channel_aperture(void __iomem *p, int ndx)
191 {
192         p += NV_HOST1X_CHANNEL0_BASE;
193         p += ndx * NV_HOST1X_CHANNEL_MAP_SIZE_BYTES;
194         return p;
195 }
196
197 static int t114_channel_init(struct nvhost_channel *ch,
198                             struct nvhost_master *dev, int index)
199 {
200         ch->chid = index;
201         mutex_init(&ch->reflock);
202         mutex_init(&ch->submitlock);
203
204         ch->aperture = t114_channel_aperture(dev->aperture, index);
205
206         return t114_nvhost_hwctx_handler_init(ch);
207 }
208
209 int nvhost_init_t114_channel_support(struct nvhost_master *host,
210         struct nvhost_chip_support *op)
211 {
212         int result = nvhost_init_t20_channel_support(host, op);
213         /* We're using 8 out of 9 channels supported by hw */
214         host->nb_channels = NV_HOST1X_CHANNELS_T114-1;
215         op->channel.init = t114_channel_init;
216
217         return result;
218 }
219
220 static struct nvhost_device *t114_get_nvhost_device(struct nvhost_master *host,
221                 char *name)
222 {
223         int i;
224
225         for (i = 0; i < host->nb_channels; i++) {
226                 if (strcmp(devices[i].name, name) == 0)
227                         return &devices[i];
228         }
229
230         return NULL;
231 }
232
233 int nvhost_init_t114_support(struct nvhost_master *host,
234         struct nvhost_chip_support *op)
235 {
236         int err;
237
238         /* don't worry about cleaning up on failure... "remove" does it. */
239         err = nvhost_init_t114_channel_support(host, op);
240         if (err)
241                 return err;
242         err = host1x_init_cdma_support(op);
243         if (err)
244                 return err;
245         err = nvhost_init_t20_debug_support(op);
246         if (err)
247                 return err;
248         err = host1x_init_syncpt_support(host, op);
249         if (err)
250                 return err;
251         err = nvhost_init_t20_intr_support(op);
252         if (err)
253                 return err;
254         op->nvhost_dev.get_nvhost_device = t114_get_nvhost_device;
255
256         return 0;
257 }