video: tegra: host: Adjust Tegra11 3D context handler
[linux-2.6.git] / drivers / video / tegra / host / t114 / t114.c
1 /*
2  * drivers/video/tegra/host/t114/t114.c
3  *
4  * Tegra Graphics Init for T114 Architecture Chips
5  *
6  * Copyright (c) 2010-2012, NVIDIA Corporation.
7  *
8  * This program is free software; you can redistribute it and/or modify
9  * it under the terms of the GNU General Public License as published by
10  * the Free Software Foundation; either version 2 of the License, or
11  * (at your option) any later version.
12  *
13  * This program is distributed in the hope that it will be useful, but WITHOUT
14  * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
15  * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
16  * more details.
17  *
18  * You should have received a copy of the GNU General Public License along
19  * with this program; if not, write to the Free Software Foundation, Inc.,
20  * 51 Franklin Street, Fifth Floor, Boston, MA  02110-1301, USA.
21  */
22
23 #include <linux/mutex.h>
24 #include <mach/powergate.h>
25 #include "dev.h"
26 #include "host1x/host1x_cdma.h"
27 #include "t20/t20.h"
28 #include "t30/t30.h"
29 #include "t114.h"
30 #include "host1x/host1x_hardware.h"
31 #include "host1x/host1x_syncpt.h"
32 #include "gr3d/gr3d.h"
33 #include "gr3d/gr3d_t114.h"
34 #include "gr3d/scale3d.h"
35 #include "msenc/msenc.h"
36 #include "tsec/tsec.h"
37
38 #define NVMODMUTEX_2D_FULL   (1)
39 #define NVMODMUTEX_2D_SIMPLE (2)
40 #define NVMODMUTEX_2D_SB_A   (3)
41 #define NVMODMUTEX_2D_SB_B   (4)
42 #define NVMODMUTEX_3D        (5)
43 #define NVMODMUTEX_DISPLAYA  (6)
44 #define NVMODMUTEX_DISPLAYB  (7)
45 #define NVMODMUTEX_VI        (8)
46 #define NVMODMUTEX_DSI       (9)
47
48 #define HOST_EMC_FLOOR 300000000
49
50 static struct nvhost_device devices[] = {
51 {
52         /* channel 0 */
53         .name          = "display",
54         .syncpts       = BIT(NVSYNCPT_DISP0_A) | BIT(NVSYNCPT_DISP1_A) |
55                          BIT(NVSYNCPT_DISP0_B) | BIT(NVSYNCPT_DISP1_B) |
56                          BIT(NVSYNCPT_DISP0_C) | BIT(NVSYNCPT_DISP1_C) |
57                          BIT(NVSYNCPT_VBLANK0) | BIT(NVSYNCPT_VBLANK1),
58         .modulemutexes = BIT(NVMODMUTEX_DISPLAYA) | BIT(NVMODMUTEX_DISPLAYB),
59         NVHOST_MODULE_NO_POWERGATE_IDS,
60         NVHOST_DEFAULT_CLOCKGATE_DELAY,
61         .moduleid      = NVHOST_MODULE_NONE,
62 },
63 {
64         /* channel 1 */
65         .name          = "gr3d",
66         .syncpts       = BIT(NVSYNCPT_3D),
67         .waitbases     = BIT(NVWAITBASE_3D),
68         .modulemutexes = BIT(NVMODMUTEX_3D),
69         .class         = NV_GRAPHICS_3D_CLASS_ID,
70         .prepare_poweroff = nvhost_gr3d_prepare_power_off,
71         .busy = nvhost_scale3d_notify_busy,
72         .idle = nvhost_scale3d_notify_idle,
73         .init = nvhost_scale3d_init,
74         .deinit = nvhost_scale3d_deinit,
75         .alloc_hwctx_handler = t114_nvhost_3dctx_handler_init,
76         .clocks = {{"gr3d", UINT_MAX},
77                         {"emc", HOST_EMC_FLOOR} },
78         NVHOST_MODULE_NO_POWERGATE_IDS,
79         NVHOST_DEFAULT_CLOCKGATE_DELAY,
80         .moduleid      = NVHOST_MODULE_NONE,
81 },
82 {
83         /* channel 2 */
84         .name          = "gr2d",
85         .syncpts       = BIT(NVSYNCPT_2D_0) | BIT(NVSYNCPT_2D_1),
86         .waitbases     = BIT(NVWAITBASE_2D_0) | BIT(NVWAITBASE_2D_1),
87         .modulemutexes = BIT(NVMODMUTEX_2D_FULL) | BIT(NVMODMUTEX_2D_SIMPLE) |
88                          BIT(NVMODMUTEX_2D_SB_A) | BIT(NVMODMUTEX_2D_SB_B),
89         .clocks = {{"gr2d", 0},
90                         {"epp", UINT_MAX},
91                         {"emc", HOST_EMC_FLOOR} },
92         NVHOST_MODULE_NO_POWERGATE_IDS,
93         NVHOST_DEFAULT_CLOCKGATE_DELAY,
94         .moduleid      = NVHOST_MODULE_NONE,
95 },
96 {
97         /* channel 3 */
98         .name    = "isp",
99         .syncpts = 0,
100         NVHOST_MODULE_NO_POWERGATE_IDS,
101         NVHOST_DEFAULT_CLOCKGATE_DELAY,
102         .moduleid      = NVHOST_MODULE_ISP,
103 },
104 {
105         /* channel 4 */
106         .name          = "vi",
107         .syncpts       = BIT(NVSYNCPT_CSI_VI_0) | BIT(NVSYNCPT_CSI_VI_1) |
108                          BIT(NVSYNCPT_VI_ISP_0) | BIT(NVSYNCPT_VI_ISP_1) |
109                          BIT(NVSYNCPT_VI_ISP_2) | BIT(NVSYNCPT_VI_ISP_3) |
110                          BIT(NVSYNCPT_VI_ISP_4),
111         .modulemutexes = BIT(NVMODMUTEX_VI),
112         .exclusive     = true,
113         NVHOST_MODULE_NO_POWERGATE_IDS,
114         NVHOST_DEFAULT_CLOCKGATE_DELAY,
115         .moduleid      = NVHOST_MODULE_VI,
116 },
117 {
118         /* channel 5 */
119         .name          = "msenc",
120         .syncpts       = BIT(NVSYNCPT_MSENC),
121         .waitbases     = BIT(NVWAITBASE_MSENC),
122         .class         = NV_VIDEO_ENCODE_MSENC_CLASS_ID,
123         .exclusive     = true,
124         .keepalive     = true,
125         .init          = nvhost_msenc_init,
126         .deinit        = nvhost_msenc_deinit,
127         .clocks = {{"msenc", UINT_MAX}, {"emc", HOST_EMC_FLOOR} },
128         NVHOST_MODULE_NO_POWERGATE_IDS,
129         NVHOST_DEFAULT_CLOCKGATE_DELAY,
130         .moduleid      = NVHOST_MODULE_MSENC,
131 },
132 {
133         /* channel 6 */
134         .name          = "dsi",
135         .syncpts       = BIT(NVSYNCPT_DSI),
136         .modulemutexes = BIT(NVMODMUTEX_DSI),
137         NVHOST_MODULE_NO_POWERGATE_IDS,
138         NVHOST_DEFAULT_CLOCKGATE_DELAY,
139         .moduleid      = NVHOST_MODULE_NONE,
140 },
141 {
142         /* channel 7 */
143         .name          = "tsec",
144         .syncpts       = BIT(NVSYNCPT_TSEC),
145         .waitbases     = BIT(NVWAITBASE_TSEC),
146         .class         = NV_TSEC_CLASS_ID,
147         .exclusive     = true,
148         .init          = nvhost_tsec_init,
149         .deinit        = nvhost_tsec_deinit,
150         .clocks = {{"tsec", UINT_MAX}, {"emc", HOST_EMC_FLOOR} },
151         NVHOST_MODULE_NO_POWERGATE_IDS,
152         NVHOST_DEFAULT_CLOCKGATE_DELAY,
153         .moduleid      = NVHOST_MODULE_TSEC,
154 } };
155
156 static inline int t114_nvhost_hwctx_handler_init(struct nvhost_channel *ch)
157 {
158         int err = 0;
159         unsigned long syncpts = ch->dev->syncpts;
160         unsigned long waitbases = ch->dev->waitbases;
161         u32 syncpt = find_first_bit(&syncpts, BITS_PER_LONG);
162         u32 waitbase = find_first_bit(&waitbases, BITS_PER_LONG);
163
164         if (ch->dev->alloc_hwctx_handler) {
165                 ch->ctxhandler = ch->dev->alloc_hwctx_handler(syncpt,
166                                 waitbase, ch);
167                 if (!ch->ctxhandler)
168                         err = -ENOMEM;
169         }
170
171         return err;
172 }
173
174 static inline void __iomem *t114_channel_aperture(void __iomem *p, int ndx)
175 {
176         p += NV_HOST1X_CHANNEL0_BASE;
177         p += ndx * NV_HOST1X_CHANNEL_MAP_SIZE_BYTES;
178         return p;
179 }
180
181 static int t114_channel_init(struct nvhost_channel *ch,
182                             struct nvhost_master *dev, int index)
183 {
184         ch->chid = index;
185         ch->dev = &devices[index];
186         mutex_init(&ch->reflock);
187         mutex_init(&ch->submitlock);
188
189         nvhost_device_register(ch->dev);
190         ch->aperture = t114_channel_aperture(dev->aperture, index);
191
192         return t114_nvhost_hwctx_handler_init(ch);
193 }
194
195 int nvhost_init_t114_channel_support(struct nvhost_master *host)
196 {
197         int result = nvhost_init_t20_channel_support(host);
198         /* We're using 8 out of 9 channels supported by hw */
199         host->nb_channels = NV_HOST1X_CHANNELS_T114-1;
200         host->op.channel.init = t114_channel_init;
201
202         return result;
203 }
204
205 int nvhost_init_t114_support(struct nvhost_master *host)
206 {
207         int err;
208
209         /* don't worry about cleaning up on failure... "remove" does it. */
210         err = nvhost_init_t114_channel_support(host);
211         if (err)
212                 return err;
213         err = host1x_init_cdma_support(host);
214         if (err)
215                 return err;
216         err = nvhost_init_t20_debug_support(host);
217         if (err)
218                 return err;
219         err = host1x_init_syncpt_support(host);
220         if (err)
221                 return err;
222         err = nvhost_init_t20_intr_support(host);
223         if (err)
224                 return err;
225         return 0;
226 }