video: tegra: host: Add common header for classids
[linux-2.6.git] / drivers / video / tegra / host / t114 / t114.c
1 /*
2  * drivers/video/tegra/host/t114/t114.c
3  *
4  * Tegra Graphics Init for Tegra11 Architecture Chips
5  *
6  * Copyright (c) 2011-2012, NVIDIA Corporation.
7  *
8  * This program is free software; you can redistribute it and/or modify it
9  * under the terms and conditions of the GNU General Public License,
10  * version 2, as published by the Free Software Foundation.
11  *
12  * This program is distributed in the hope it will be useful, but WITHOUT
13  * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
14  * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
15  * more details.
16  *
17  * You should have received a copy of the GNU General Public License
18  * along with this program.  If not, see <http://www.gnu.org/licenses/>.
19  */
20
21 #include <linux/mutex.h>
22 #include <linux/kernel.h>
23 #include <linux/nvhost_ioctl.h>
24 #include <mach/powergate.h>
25 #include <mach/iomap.h>
26 #include "t20/t20.h"
27 #include "t30/t30.h"
28 #include "t114.h"
29 #include "gr3d/gr3d_t114.h"
30 #include "gr3d/scale3d.h"
31 #include "host1x/host1x02_hardware.h"
32 #include "msenc/msenc.h"
33 #include "tsec/tsec.h"
34 #include "host1x/host1x.h"
35 #include "chip_support.h"
36 #include "nvhost_channel.h"
37 #include "nvhost_memmgr.h"
38 #include "host1x/host1x_syncpt.h"
39 #include "chip_support.h"
40 #include "gr3d/pod_scaling.h"
41 #include "class_ids.h"
42
43 #define NVMODMUTEX_2D_FULL   (1)
44 #define NVMODMUTEX_2D_SIMPLE (2)
45 #define NVMODMUTEX_2D_SB_A   (3)
46 #define NVMODMUTEX_2D_SB_B   (4)
47 #define NVMODMUTEX_3D        (5)
48 #define NVMODMUTEX_DISPLAYA  (6)
49 #define NVMODMUTEX_DISPLAYB  (7)
50 #define NVMODMUTEX_VI        (8)
51 #define NVMODMUTEX_DSI       (9)
52
53 static int t114_num_alloc_channels = 0;
54
55 static struct resource tegra_host1x02_resources[] = {
56         {
57                 .start = TEGRA_HOST1X_BASE,
58                 .end = TEGRA_HOST1X_BASE + TEGRA_HOST1X_SIZE - 1,
59                 .flags = IORESOURCE_MEM,
60         },
61         {
62                 .start = INT_SYNCPT_THRESH_BASE,
63                 .end = INT_SYNCPT_THRESH_BASE + INT_SYNCPT_THRESH_NR - 1,
64                 .flags = IORESOURCE_IRQ,
65         },
66         {
67                 .start = INT_HOST1X_MPCORE_GENERAL,
68                 .end = INT_HOST1X_MPCORE_GENERAL,
69                 .flags = IORESOURCE_IRQ,
70         },
71 };
72
73 static const char *s_syncpt_names[32] = {
74         "gfx_host",
75         "", "", "", "", "", "", "",
76         "disp0_a", "disp1_a", "avp_0",
77         "csi_vi_0", "csi_vi_1",
78         "vi_isp_0", "vi_isp_1", "vi_isp_2", "vi_isp_3", "vi_isp_4",
79         "2d_0", "2d_1",
80         "disp0_b", "disp1_b",
81         "3d",
82         "mpe",
83         "disp0_c", "disp1_c",
84         "vblank0", "vblank1",
85         "mpe_ebm_eof", "mpe_wr_safe",
86         "2d_tinyblt",
87         "dsi"
88 };
89
90 static struct host1x_device_info host1x02_info = {
91         .nb_channels    = 9,
92         .nb_pts         = 32,
93         .nb_mlocks      = 16,
94         .nb_bases       = 12,
95         .syncpt_names   = s_syncpt_names,
96         .client_managed = NVSYNCPTS_CLIENT_MANAGED,
97 };
98
99 static struct nvhost_device tegra_host1x02_device = {
100         .dev            = {.platform_data = &host1x02_info},
101         .name           = "host1x",
102         .id             = -1,
103         .resource       = tegra_host1x02_resources,
104         .num_resources  = ARRAY_SIZE(tegra_host1x02_resources),
105         .clocks         = {{"host1x", 102000000}, {} },
106         NVHOST_MODULE_NO_POWERGATE_IDS,
107 };
108
109 static struct nvhost_device tegra_display01_device = {
110         .name          = "display",
111         .id            = -1,
112         .index         = 0,
113         .syncpts       = BIT(NVSYNCPT_DISP0_A) | BIT(NVSYNCPT_DISP1_A) |
114                          BIT(NVSYNCPT_DISP0_B) | BIT(NVSYNCPT_DISP1_B) |
115                          BIT(NVSYNCPT_DISP0_C) | BIT(NVSYNCPT_DISP1_C) |
116                          BIT(NVSYNCPT_VBLANK0) | BIT(NVSYNCPT_VBLANK1),
117         .modulemutexes = BIT(NVMODMUTEX_DISPLAYA) | BIT(NVMODMUTEX_DISPLAYB),
118         NVHOST_MODULE_NO_POWERGATE_IDS,
119         NVHOST_DEFAULT_CLOCKGATE_DELAY,
120         .moduleid      = NVHOST_MODULE_NONE,
121 };
122
123 static struct nvhost_device tegra_gr3d03_device = {
124         .name          = "gr3d",
125         .version       = 3,
126         .id            = -1,
127         .index         = 1,
128         .syncpts       = BIT(NVSYNCPT_3D),
129         .waitbases     = BIT(NVWAITBASE_3D),
130         .modulemutexes = BIT(NVMODMUTEX_3D),
131         .class         = NV_GRAPHICS_3D_CLASS_ID,
132         .clocks = {{"gr3d", UINT_MAX, 8},
133                         {"emc", UINT_MAX, 75} },
134         .powergate_ids = { TEGRA_POWERGATE_3D, -1 },
135         NVHOST_DEFAULT_CLOCKGATE_DELAY,
136         .can_powergate = true,
137         .powergate_delay = 250,
138         .moduleid      = NVHOST_MODULE_NONE,
139 };
140
141 static struct nvhost_device tegra_gr2d03_device = {
142         .name          = "gr2d",
143         .id            = -1,
144         .index         = 2,
145         .syncpts       = BIT(NVSYNCPT_2D_0) | BIT(NVSYNCPT_2D_1),
146         .waitbases     = BIT(NVWAITBASE_2D_0) | BIT(NVWAITBASE_2D_1),
147         .modulemutexes = BIT(NVMODMUTEX_2D_FULL) | BIT(NVMODMUTEX_2D_SIMPLE) |
148                          BIT(NVMODMUTEX_2D_SB_A) | BIT(NVMODMUTEX_2D_SB_B),
149         .clocks        = { {"gr2d", 0, 7},
150                         {"epp", 0, 10},
151                         {"emc", 300000000, 75 } },
152         NVHOST_MODULE_NO_POWERGATE_IDS,
153         .clockgate_delay = 0,
154         .moduleid       = NVHOST_MODULE_NONE,
155         .serialize      = true,
156 };
157
158 static struct resource isp_resources[] = {
159         {
160                 .name = "regs",
161                 .start = TEGRA_ISP_BASE,
162                 .end = TEGRA_ISP_BASE + TEGRA_ISP_SIZE - 1,
163                 .flags = IORESOURCE_MEM,
164         }
165 };
166
167 static struct nvhost_device tegra_isp01_device = {
168         .name           = "isp",
169         .id             = -1,
170         .resource       = isp_resources,
171         .num_resources  = ARRAY_SIZE(isp_resources),
172         .index          = 3,
173         .syncpts        = BIT(NVSYNCPT_VI_ISP_2) | BIT(NVSYNCPT_VI_ISP_3) |
174                           BIT(NVSYNCPT_VI_ISP_4),
175         .clocks         = { {"epp", 0, 10} },
176         .keepalive      = true,
177         NVHOST_MODULE_NO_POWERGATE_IDS,
178         NVHOST_DEFAULT_CLOCKGATE_DELAY,
179         .moduleid       = NVHOST_MODULE_ISP,
180 };
181
182 static struct resource vi_resources[] = {
183         {
184                 .name = "regs",
185                 .start = TEGRA_VI_BASE,
186                 .end = TEGRA_VI_BASE + TEGRA_VI_SIZE - 1,
187                 .flags = IORESOURCE_MEM,
188         },
189 };
190
191 static struct nvhost_device tegra_vi01_device = {
192         .name          = "vi",
193         .resource      = vi_resources,
194         .num_resources = ARRAY_SIZE(vi_resources),
195         .id            = -1,
196         .index         = 4,
197         .syncpts       = BIT(NVSYNCPT_CSI_VI_0) | BIT(NVSYNCPT_CSI_VI_1) |
198                          BIT(NVSYNCPT_VI_ISP_0) | BIT(NVSYNCPT_VI_ISP_1) |
199                          BIT(NVSYNCPT_VI_ISP_2) | BIT(NVSYNCPT_VI_ISP_3) |
200                          BIT(NVSYNCPT_VI_ISP_4),
201         .modulemutexes = BIT(NVMODMUTEX_VI),
202         .exclusive     = true,
203         NVHOST_MODULE_NO_POWERGATE_IDS,
204         NVHOST_DEFAULT_CLOCKGATE_DELAY,
205         .moduleid      = NVHOST_MODULE_VI,
206 };
207
208 static struct resource msenc_resources[] = {
209         {
210                 .name = "regs",
211                 .start = TEGRA_MSENC_BASE,
212                 .end = TEGRA_MSENC_BASE + TEGRA_MSENC_SIZE - 1,
213                 .flags = IORESOURCE_MEM,
214         },
215 };
216
217 static struct nvhost_device tegra_msenc02_device = {
218         .name          = "msenc",
219         .version       = NVHOST_ENCODE_MSENC_VER(2, 0),
220         .id            = -1,
221         .resource      = msenc_resources,
222         .num_resources = ARRAY_SIZE(msenc_resources),
223         .index         = 5,
224         .syncpts       = BIT(NVSYNCPT_MSENC),
225         .waitbases     = BIT(NVWAITBASE_MSENC),
226         .class         = NV_VIDEO_ENCODE_MSENC_CLASS_ID,
227         .exclusive     = false,
228         .keepalive     = true,
229         .clocks        = { {"msenc", UINT_MAX, 107},
230                         {"emc", 300000000, 75} },
231         NVHOST_MODULE_NO_POWERGATE_IDS,
232         NVHOST_DEFAULT_CLOCKGATE_DELAY,
233         .moduleid      = NVHOST_MODULE_MSENC,
234 };
235
236 static struct nvhost_device tegra_dsi01_device = {
237         .name          = "dsi",
238         .id            = -1,
239         .index         = 6,
240         .syncpts       = BIT(NVSYNCPT_DSI),
241         .modulemutexes = BIT(NVMODMUTEX_DSI),
242         NVHOST_MODULE_NO_POWERGATE_IDS,
243         NVHOST_DEFAULT_CLOCKGATE_DELAY,
244         .moduleid      = NVHOST_MODULE_NONE,
245 };
246
247 static struct resource tsec_resources[] = {
248         {
249                 .name = "regs",
250                 .start = TEGRA_TSEC_BASE,
251                 .end = TEGRA_TSEC_BASE + TEGRA_TSEC_SIZE - 1,
252                 .flags = IORESOURCE_MEM,
253         },
254 };
255
256 static struct nvhost_device tegra_tsec01_device = {
257         /* channel 7 */
258         .name          = "tsec",
259         .version       = NVHOST_ENCODE_TSEC_VER(1,0),
260         .id            = -1,
261         .resource      = tsec_resources,
262         .num_resources = ARRAY_SIZE(tsec_resources),
263         .index         = 7,
264         .syncpts       = BIT(NVSYNCPT_TSEC),
265         .waitbases     = BIT(NVWAITBASE_TSEC),
266         .class         = NV_TSEC_CLASS_ID,
267         .exclusive     = false,
268         .clocks        = { {"tsec", UINT_MAX, 108},
269                         {"emc", 300000000, 75} },
270         NVHOST_MODULE_NO_POWERGATE_IDS,
271         NVHOST_DEFAULT_CLOCKGATE_DELAY,
272         .moduleid      = NVHOST_MODULE_TSEC,
273 };
274
275 static struct nvhost_device *t11_devices[] = {
276         &tegra_host1x02_device,
277         &tegra_display01_device,
278         &tegra_gr3d03_device,
279         &tegra_gr2d03_device,
280         &tegra_isp01_device,
281         &tegra_vi01_device,
282         &tegra_msenc02_device,
283         &tegra_dsi01_device,
284         &tegra_tsec01_device,
285 };
286
287 int tegra11_register_host1x_devices(void)
288 {
289         return nvhost_add_devices(t11_devices, ARRAY_SIZE(t11_devices));
290 }
291
292 static void t114_free_nvhost_channel(struct nvhost_channel *ch)
293 {
294         nvhost_free_channel_internal(ch, &t114_num_alloc_channels);
295 }
296
297 static struct nvhost_channel *t114_alloc_nvhost_channel(
298                 struct nvhost_device *dev)
299 {
300         return nvhost_alloc_channel_internal(dev->index,
301                 nvhost_get_host(dev)->info.nb_channels,
302                 &t114_num_alloc_channels);
303 }
304
305 #include "host1x/host1x_channel.c"
306 #include "host1x/host1x_cdma.c"
307 #include "host1x/host1x_debug.c"
308 #include "host1x/host1x_syncpt.c"
309 #include "host1x/host1x_intr.c"
310 #include "host1x/host1x_actmon.c"
311 #include "host1x/host1x_tickctrl.c"
312
313 int nvhost_init_t114_support(struct nvhost_master *host,
314         struct nvhost_chip_support *op)
315 {
316         int err;
317
318         op->channel = host1x_channel_ops;
319         op->cdma = host1x_cdma_ops;
320         op->push_buffer = host1x_pushbuffer_ops;
321         op->debug = host1x_debug_ops;
322         host->sync_aperture = host->aperture + HOST1X_CHANNEL_SYNC_REG_BASE;
323         op->syncpt = host1x_syncpt_ops;
324         op->intr = host1x_intr_ops;
325         err = nvhost_memmgr_init(op);
326         if (err)
327                 return err;
328         op->nvhost_dev.alloc_nvhost_channel = t114_alloc_nvhost_channel;
329         op->nvhost_dev.free_nvhost_channel = t114_free_nvhost_channel;
330         op->actmon = host1x_actmon_ops;
331         op->tickctrl = host1x_tickctrl_ops;
332
333         return 0;
334 }