2 * drivers/video/tegra/host/t114/t114.c
4 * Tegra Graphics Init for Tegra11 Architecture Chips
6 * Copyright (c) 2011-2012, NVIDIA Corporation.
8 * This program is free software; you can redistribute it and/or modify it
9 * under the terms and conditions of the GNU General Public License,
10 * version 2, as published by the Free Software Foundation.
12 * This program is distributed in the hope it will be useful, but WITHOUT
13 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
14 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
17 * You should have received a copy of the GNU General Public License
18 * along with this program. If not, see <http://www.gnu.org/licenses/>.
21 #include <linux/mutex.h>
22 #include <linux/kernel.h>
23 #include <linux/nvhost_ioctl.h>
24 #include <mach/powergate.h>
25 #include <mach/iomap.h>
29 #include "gr3d/gr3d_t114.h"
30 #include "gr3d/scale3d.h"
31 #include "host1x/host1x02_hardware.h"
32 #include "msenc/msenc.h"
33 #include "tsec/tsec.h"
34 #include "host1x/host1x.h"
35 #include "chip_support.h"
36 #include "nvhost_channel.h"
37 #include "nvhost_memmgr.h"
38 #include "host1x/host1x_syncpt.h"
39 #include "chip_support.h"
40 #include "gr3d/pod_scaling.h"
42 #define NVMODMUTEX_2D_FULL (1)
43 #define NVMODMUTEX_2D_SIMPLE (2)
44 #define NVMODMUTEX_2D_SB_A (3)
45 #define NVMODMUTEX_2D_SB_B (4)
46 #define NVMODMUTEX_3D (5)
47 #define NVMODMUTEX_DISPLAYA (6)
48 #define NVMODMUTEX_DISPLAYB (7)
49 #define NVMODMUTEX_VI (8)
50 #define NVMODMUTEX_DSI (9)
52 static int t114_num_alloc_channels = 0;
54 static struct resource tegra_host1x02_resources[] = {
56 .start = TEGRA_HOST1X_BASE,
57 .end = TEGRA_HOST1X_BASE + TEGRA_HOST1X_SIZE - 1,
58 .flags = IORESOURCE_MEM,
61 .start = INT_SYNCPT_THRESH_BASE,
62 .end = INT_SYNCPT_THRESH_BASE + INT_SYNCPT_THRESH_NR - 1,
63 .flags = IORESOURCE_IRQ,
66 .start = INT_HOST1X_MPCORE_GENERAL,
67 .end = INT_HOST1X_MPCORE_GENERAL,
68 .flags = IORESOURCE_IRQ,
72 static const char *s_syncpt_names[32] = {
74 "", "", "", "", "", "", "",
75 "disp0_a", "disp1_a", "avp_0",
76 "csi_vi_0", "csi_vi_1",
77 "vi_isp_0", "vi_isp_1", "vi_isp_2", "vi_isp_3", "vi_isp_4",
84 "mpe_ebm_eof", "mpe_wr_safe",
89 static struct host1x_device_info host1x02_info = {
94 .syncpt_names = s_syncpt_names,
95 .client_managed = NVSYNCPTS_CLIENT_MANAGED,
98 static struct nvhost_device tegra_host1x02_device = {
99 .dev = {.platform_data = &host1x02_info},
102 .resource = tegra_host1x02_resources,
103 .num_resources = ARRAY_SIZE(tegra_host1x02_resources),
104 .clocks = {{"host1x", 102000000}, {} },
105 NVHOST_MODULE_NO_POWERGATE_IDS,
108 static struct nvhost_device tegra_display01_device = {
112 .syncpts = BIT(NVSYNCPT_DISP0_A) | BIT(NVSYNCPT_DISP1_A) |
113 BIT(NVSYNCPT_DISP0_B) | BIT(NVSYNCPT_DISP1_B) |
114 BIT(NVSYNCPT_DISP0_C) | BIT(NVSYNCPT_DISP1_C) |
115 BIT(NVSYNCPT_VBLANK0) | BIT(NVSYNCPT_VBLANK1),
116 .modulemutexes = BIT(NVMODMUTEX_DISPLAYA) | BIT(NVMODMUTEX_DISPLAYB),
117 NVHOST_MODULE_NO_POWERGATE_IDS,
118 NVHOST_DEFAULT_CLOCKGATE_DELAY,
119 .moduleid = NVHOST_MODULE_NONE,
122 static struct nvhost_device tegra_gr3d03_device = {
127 .syncpts = BIT(NVSYNCPT_3D),
128 .waitbases = BIT(NVWAITBASE_3D),
129 .modulemutexes = BIT(NVMODMUTEX_3D),
130 .class = NV_GRAPHICS_3D_CLASS_ID,
131 .clocks = {{"gr3d", UINT_MAX},
133 .powergate_ids = { TEGRA_POWERGATE_3D, -1 },
134 NVHOST_DEFAULT_CLOCKGATE_DELAY,
135 .can_powergate = true,
136 .powergate_delay = 250,
137 .moduleid = NVHOST_MODULE_NONE,
140 static struct nvhost_device tegra_gr2d03_device = {
144 .syncpts = BIT(NVSYNCPT_2D_0) | BIT(NVSYNCPT_2D_1),
145 .waitbases = BIT(NVWAITBASE_2D_0) | BIT(NVWAITBASE_2D_1),
146 .modulemutexes = BIT(NVMODMUTEX_2D_FULL) | BIT(NVMODMUTEX_2D_SIMPLE) |
147 BIT(NVMODMUTEX_2D_SB_A) | BIT(NVMODMUTEX_2D_SB_B),
148 .clocks = {{"gr2d", 0},
150 {"emc", 300000000} },
151 NVHOST_MODULE_NO_POWERGATE_IDS,
152 .clockgate_delay = 0,
153 .moduleid = NVHOST_MODULE_NONE,
157 static struct resource isp_resources[] = {
160 .start = TEGRA_ISP_BASE,
161 .end = TEGRA_ISP_BASE + TEGRA_ISP_SIZE - 1,
162 .flags = IORESOURCE_MEM,
166 static struct nvhost_device tegra_isp01_device = {
169 .resource = isp_resources,
170 .num_resources = ARRAY_SIZE(isp_resources),
172 .syncpts = BIT(NVSYNCPT_VI_ISP_2) | BIT(NVSYNCPT_VI_ISP_3) |
173 BIT(NVSYNCPT_VI_ISP_4),
174 .clocks = { {"epp", 0} },
176 NVHOST_MODULE_NO_POWERGATE_IDS,
177 NVHOST_DEFAULT_CLOCKGATE_DELAY,
178 .moduleid = NVHOST_MODULE_ISP,
181 static struct resource vi_resources[] = {
184 .start = TEGRA_VI_BASE,
185 .end = TEGRA_VI_BASE + TEGRA_VI_SIZE - 1,
186 .flags = IORESOURCE_MEM,
190 static struct nvhost_device tegra_vi01_device = {
192 .resource = vi_resources,
193 .num_resources = ARRAY_SIZE(vi_resources),
196 .syncpts = BIT(NVSYNCPT_CSI_VI_0) | BIT(NVSYNCPT_CSI_VI_1) |
197 BIT(NVSYNCPT_VI_ISP_0) | BIT(NVSYNCPT_VI_ISP_1) |
198 BIT(NVSYNCPT_VI_ISP_2) | BIT(NVSYNCPT_VI_ISP_3) |
199 BIT(NVSYNCPT_VI_ISP_4),
200 .modulemutexes = BIT(NVMODMUTEX_VI),
202 NVHOST_MODULE_NO_POWERGATE_IDS,
203 NVHOST_DEFAULT_CLOCKGATE_DELAY,
204 .moduleid = NVHOST_MODULE_VI,
207 static struct resource msenc_resources[] = {
210 .start = TEGRA_MSENC_BASE,
211 .end = TEGRA_MSENC_BASE + TEGRA_MSENC_SIZE - 1,
212 .flags = IORESOURCE_MEM,
216 static struct nvhost_device tegra_msenc02_device = {
218 .version = NVHOST_ENCODE_MSENC_VER(2, 0),
220 .resource = msenc_resources,
221 .num_resources = ARRAY_SIZE(msenc_resources),
223 .syncpts = BIT(NVSYNCPT_MSENC),
224 .waitbases = BIT(NVWAITBASE_MSENC),
225 .class = NV_VIDEO_ENCODE_MSENC_CLASS_ID,
228 .clocks = {{"msenc", UINT_MAX}, {"emc", 300000000} },
229 NVHOST_MODULE_NO_POWERGATE_IDS,
230 NVHOST_DEFAULT_CLOCKGATE_DELAY,
231 .moduleid = NVHOST_MODULE_MSENC,
234 static struct nvhost_device tegra_dsi01_device = {
238 .syncpts = BIT(NVSYNCPT_DSI),
239 .modulemutexes = BIT(NVMODMUTEX_DSI),
240 NVHOST_MODULE_NO_POWERGATE_IDS,
241 NVHOST_DEFAULT_CLOCKGATE_DELAY,
242 .moduleid = NVHOST_MODULE_NONE,
245 static struct resource tsec_resources[] = {
248 .start = TEGRA_TSEC_BASE,
249 .end = TEGRA_TSEC_BASE + TEGRA_TSEC_SIZE - 1,
250 .flags = IORESOURCE_MEM,
254 static struct nvhost_device tegra_tsec01_device = {
257 .version = NVHOST_ENCODE_TSEC_VER(1,0),
259 .resource = tsec_resources,
260 .num_resources = ARRAY_SIZE(tsec_resources),
262 .syncpts = BIT(NVSYNCPT_TSEC),
263 .waitbases = BIT(NVWAITBASE_TSEC),
264 .class = NV_TSEC_CLASS_ID,
266 .clocks = {{"tsec", UINT_MAX}, {"emc", 300000000} },
267 NVHOST_MODULE_NO_POWERGATE_IDS,
268 NVHOST_DEFAULT_CLOCKGATE_DELAY,
269 .moduleid = NVHOST_MODULE_TSEC,
272 static struct nvhost_device *t11_devices[] = {
273 &tegra_host1x02_device,
274 &tegra_display01_device,
275 &tegra_gr3d03_device,
276 &tegra_gr2d03_device,
279 &tegra_msenc02_device,
281 &tegra_tsec01_device,
284 int tegra11_register_host1x_devices(void)
286 return nvhost_add_devices(t11_devices, ARRAY_SIZE(t11_devices));
289 static void t114_free_nvhost_channel(struct nvhost_channel *ch)
291 nvhost_free_channel_internal(ch, &t114_num_alloc_channels);
294 static struct nvhost_channel *t114_alloc_nvhost_channel(
295 struct nvhost_device *dev)
297 return nvhost_alloc_channel_internal(dev->index,
298 nvhost_get_host(dev)->info.nb_channels,
299 &t114_num_alloc_channels);
302 #include "host1x/host1x_channel.c"
303 #include "host1x/host1x_cdma.c"
304 #include "host1x/host1x_debug.c"
305 #include "host1x/host1x_syncpt.c"
306 #include "host1x/host1x_intr.c"
307 #include "host1x/host1x_actmon.c"
308 #include "host1x/host1x_tickctrl.c"
310 int nvhost_init_t114_support(struct nvhost_master *host,
311 struct nvhost_chip_support *op)
315 op->channel = host1x_channel_ops;
316 op->cdma = host1x_cdma_ops;
317 op->push_buffer = host1x_pushbuffer_ops;
318 op->debug = host1x_debug_ops;
319 host->sync_aperture = host->aperture + HOST1X_CHANNEL_SYNC_REG_BASE;
320 op->syncpt = host1x_syncpt_ops;
321 op->intr = host1x_intr_ops;
322 err = nvhost_memmgr_init(op);
325 op->nvhost_dev.alloc_nvhost_channel = t114_alloc_nvhost_channel;
326 op->nvhost_dev.free_nvhost_channel = t114_free_nvhost_channel;
327 op->actmon = host1x_actmon_ops;
328 op->tickctrl = host1x_tickctrl_ops;