video: tegra: host: Correct number of wait bases
[linux-2.6.git] / drivers / video / tegra / host / t114 / t114.c
1 /*
2  * drivers/video/tegra/host/t114/t114.c
3  *
4  * Tegra Graphics Init for Tegra11 Architecture Chips
5  *
6  * Copyright (c) 2011-2012, NVIDIA Corporation.
7  *
8  * This program is free software; you can redistribute it and/or modify it
9  * under the terms and conditions of the GNU General Public License,
10  * version 2, as published by the Free Software Foundation.
11  *
12  * This program is distributed in the hope it will be useful, but WITHOUT
13  * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
14  * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
15  * more details.
16  *
17  * You should have received a copy of the GNU General Public License
18  * along with this program.  If not, see <http://www.gnu.org/licenses/>.
19  */
20
21 #include <linux/mutex.h>
22 #include <linux/kernel.h>
23 #include <linux/nvhost_ioctl.h>
24 #include <mach/powergate.h>
25 #include <mach/iomap.h>
26 #include "t20/t20.h"
27 #include "t30/t30.h"
28 #include "t114.h"
29 #include "gr3d/gr3d_t114.h"
30 #include "gr3d/scale3d.h"
31 #include "host1x/host1x02_hardware.h"
32 #include "msenc/msenc.h"
33 #include "tsec/tsec.h"
34 #include "host1x/host1x.h"
35 #include "chip_support.h"
36 #include "nvhost_channel.h"
37 #include "nvhost_memmgr.h"
38 #include "host1x/host1x_syncpt.h"
39 #include "chip_support.h"
40 #include "gr3d/pod_scaling.h"
41
42 #define NVMODMUTEX_2D_FULL   (1)
43 #define NVMODMUTEX_2D_SIMPLE (2)
44 #define NVMODMUTEX_2D_SB_A   (3)
45 #define NVMODMUTEX_2D_SB_B   (4)
46 #define NVMODMUTEX_3D        (5)
47 #define NVMODMUTEX_DISPLAYA  (6)
48 #define NVMODMUTEX_DISPLAYB  (7)
49 #define NVMODMUTEX_VI        (8)
50 #define NVMODMUTEX_DSI       (9)
51
52 static int t114_num_alloc_channels = 0;
53
54 static struct resource tegra_host1x02_resources[] = {
55         {
56                 .start = TEGRA_HOST1X_BASE,
57                 .end = TEGRA_HOST1X_BASE + TEGRA_HOST1X_SIZE - 1,
58                 .flags = IORESOURCE_MEM,
59         },
60         {
61                 .start = INT_SYNCPT_THRESH_BASE,
62                 .end = INT_SYNCPT_THRESH_BASE + INT_SYNCPT_THRESH_NR - 1,
63                 .flags = IORESOURCE_IRQ,
64         },
65         {
66                 .start = INT_HOST1X_MPCORE_GENERAL,
67                 .end = INT_HOST1X_MPCORE_GENERAL,
68                 .flags = IORESOURCE_IRQ,
69         },
70 };
71
72 static const char *s_syncpt_names[32] = {
73         "gfx_host",
74         "", "", "", "", "", "", "",
75         "disp0_a", "disp1_a", "avp_0",
76         "csi_vi_0", "csi_vi_1",
77         "vi_isp_0", "vi_isp_1", "vi_isp_2", "vi_isp_3", "vi_isp_4",
78         "2d_0", "2d_1",
79         "disp0_b", "disp1_b",
80         "3d",
81         "mpe",
82         "disp0_c", "disp1_c",
83         "vblank0", "vblank1",
84         "mpe_ebm_eof", "mpe_wr_safe",
85         "2d_tinyblt",
86         "dsi"
87 };
88
89 static struct host1x_device_info host1x02_info = {
90         .nb_channels    = 9,
91         .nb_pts         = 32,
92         .nb_mlocks      = 16,
93         .nb_bases       = 12,
94         .syncpt_names   = s_syncpt_names,
95         .client_managed = NVSYNCPTS_CLIENT_MANAGED,
96 };
97
98 static struct nvhost_device tegra_host1x02_device = {
99         .dev            = {.platform_data = &host1x02_info},
100         .name           = "host1x",
101         .id             = -1,
102         .resource       = tegra_host1x02_resources,
103         .num_resources  = ARRAY_SIZE(tegra_host1x02_resources),
104         .clocks         = {{"host1x", 102000000}, {} },
105         NVHOST_MODULE_NO_POWERGATE_IDS,
106 };
107
108 static struct nvhost_device tegra_display01_device = {
109         .name          = "display",
110         .id            = -1,
111         .index         = 0,
112         .syncpts       = BIT(NVSYNCPT_DISP0_A) | BIT(NVSYNCPT_DISP1_A) |
113                          BIT(NVSYNCPT_DISP0_B) | BIT(NVSYNCPT_DISP1_B) |
114                          BIT(NVSYNCPT_DISP0_C) | BIT(NVSYNCPT_DISP1_C) |
115                          BIT(NVSYNCPT_VBLANK0) | BIT(NVSYNCPT_VBLANK1),
116         .modulemutexes = BIT(NVMODMUTEX_DISPLAYA) | BIT(NVMODMUTEX_DISPLAYB),
117         NVHOST_MODULE_NO_POWERGATE_IDS,
118         NVHOST_DEFAULT_CLOCKGATE_DELAY,
119         .moduleid      = NVHOST_MODULE_NONE,
120 };
121
122 static struct nvhost_device tegra_gr3d03_device = {
123         .name          = "gr3d",
124         .version       = 3,
125         .id            = -1,
126         .index         = 1,
127         .syncpts       = BIT(NVSYNCPT_3D),
128         .waitbases     = BIT(NVWAITBASE_3D),
129         .modulemutexes = BIT(NVMODMUTEX_3D),
130         .class         = NV_GRAPHICS_3D_CLASS_ID,
131         .clocks = {{"gr3d", UINT_MAX, 8},
132                         {"emc", UINT_MAX, 75} },
133         .powergate_ids = { TEGRA_POWERGATE_3D, -1 },
134         NVHOST_DEFAULT_CLOCKGATE_DELAY,
135         .can_powergate = true,
136         .powergate_delay = 250,
137         .moduleid      = NVHOST_MODULE_NONE,
138 };
139
140 static struct nvhost_device tegra_gr2d03_device = {
141         .name          = "gr2d",
142         .id            = -1,
143         .index         = 2,
144         .syncpts       = BIT(NVSYNCPT_2D_0) | BIT(NVSYNCPT_2D_1),
145         .waitbases     = BIT(NVWAITBASE_2D_0) | BIT(NVWAITBASE_2D_1),
146         .modulemutexes = BIT(NVMODMUTEX_2D_FULL) | BIT(NVMODMUTEX_2D_SIMPLE) |
147                          BIT(NVMODMUTEX_2D_SB_A) | BIT(NVMODMUTEX_2D_SB_B),
148         .clocks        = { {"gr2d", 0, 7},
149                         {"epp", 0, 10},
150                         {"emc", 300000000, 75 } },
151         NVHOST_MODULE_NO_POWERGATE_IDS,
152         .clockgate_delay = 0,
153         .moduleid       = NVHOST_MODULE_NONE,
154         .serialize      = true,
155 };
156
157 static struct resource isp_resources[] = {
158         {
159                 .name = "regs",
160                 .start = TEGRA_ISP_BASE,
161                 .end = TEGRA_ISP_BASE + TEGRA_ISP_SIZE - 1,
162                 .flags = IORESOURCE_MEM,
163         }
164 };
165
166 static struct nvhost_device tegra_isp01_device = {
167         .name           = "isp",
168         .id             = -1,
169         .resource       = isp_resources,
170         .num_resources  = ARRAY_SIZE(isp_resources),
171         .index          = 3,
172         .syncpts        = BIT(NVSYNCPT_VI_ISP_2) | BIT(NVSYNCPT_VI_ISP_3) |
173                           BIT(NVSYNCPT_VI_ISP_4),
174         .clocks         = { {"epp", 0, 10} },
175         .keepalive      = true,
176         NVHOST_MODULE_NO_POWERGATE_IDS,
177         NVHOST_DEFAULT_CLOCKGATE_DELAY,
178         .moduleid       = NVHOST_MODULE_ISP,
179 };
180
181 static struct resource vi_resources[] = {
182         {
183                 .name = "regs",
184                 .start = TEGRA_VI_BASE,
185                 .end = TEGRA_VI_BASE + TEGRA_VI_SIZE - 1,
186                 .flags = IORESOURCE_MEM,
187         },
188 };
189
190 static struct nvhost_device tegra_vi01_device = {
191         .name          = "vi",
192         .resource      = vi_resources,
193         .num_resources = ARRAY_SIZE(vi_resources),
194         .id            = -1,
195         .index         = 4,
196         .syncpts       = BIT(NVSYNCPT_CSI_VI_0) | BIT(NVSYNCPT_CSI_VI_1) |
197                          BIT(NVSYNCPT_VI_ISP_0) | BIT(NVSYNCPT_VI_ISP_1) |
198                          BIT(NVSYNCPT_VI_ISP_2) | BIT(NVSYNCPT_VI_ISP_3) |
199                          BIT(NVSYNCPT_VI_ISP_4),
200         .modulemutexes = BIT(NVMODMUTEX_VI),
201         .exclusive     = true,
202         NVHOST_MODULE_NO_POWERGATE_IDS,
203         NVHOST_DEFAULT_CLOCKGATE_DELAY,
204         .moduleid      = NVHOST_MODULE_VI,
205 };
206
207 static struct resource msenc_resources[] = {
208         {
209                 .name = "regs",
210                 .start = TEGRA_MSENC_BASE,
211                 .end = TEGRA_MSENC_BASE + TEGRA_MSENC_SIZE - 1,
212                 .flags = IORESOURCE_MEM,
213         },
214 };
215
216 static struct nvhost_device tegra_msenc02_device = {
217         .name          = "msenc",
218         .version       = NVHOST_ENCODE_MSENC_VER(2, 0),
219         .id            = -1,
220         .resource      = msenc_resources,
221         .num_resources = ARRAY_SIZE(msenc_resources),
222         .index         = 5,
223         .syncpts       = BIT(NVSYNCPT_MSENC),
224         .waitbases     = BIT(NVWAITBASE_MSENC),
225         .class         = NV_VIDEO_ENCODE_MSENC_CLASS_ID,
226         .exclusive     = false,
227         .keepalive     = true,
228         .clocks        = { {"msenc", UINT_MAX, 107},
229                         {"emc", 300000000, 75} },
230         NVHOST_MODULE_NO_POWERGATE_IDS,
231         NVHOST_DEFAULT_CLOCKGATE_DELAY,
232         .moduleid      = NVHOST_MODULE_MSENC,
233 };
234
235 static struct nvhost_device tegra_dsi01_device = {
236         .name          = "dsi",
237         .id            = -1,
238         .index         = 6,
239         .syncpts       = BIT(NVSYNCPT_DSI),
240         .modulemutexes = BIT(NVMODMUTEX_DSI),
241         NVHOST_MODULE_NO_POWERGATE_IDS,
242         NVHOST_DEFAULT_CLOCKGATE_DELAY,
243         .moduleid      = NVHOST_MODULE_NONE,
244 };
245
246 static struct resource tsec_resources[] = {
247         {
248                 .name = "regs",
249                 .start = TEGRA_TSEC_BASE,
250                 .end = TEGRA_TSEC_BASE + TEGRA_TSEC_SIZE - 1,
251                 .flags = IORESOURCE_MEM,
252         },
253 };
254
255 static struct nvhost_device tegra_tsec01_device = {
256         /* channel 7 */
257         .name          = "tsec",
258         .version       = NVHOST_ENCODE_TSEC_VER(1,0),
259         .id            = -1,
260         .resource      = tsec_resources,
261         .num_resources = ARRAY_SIZE(tsec_resources),
262         .index         = 7,
263         .syncpts       = BIT(NVSYNCPT_TSEC),
264         .waitbases     = BIT(NVWAITBASE_TSEC),
265         .class         = NV_TSEC_CLASS_ID,
266         .exclusive     = false,
267         .clocks        = { {"tsec", UINT_MAX, 108},
268                         {"emc", 300000000, 75} },
269         NVHOST_MODULE_NO_POWERGATE_IDS,
270         NVHOST_DEFAULT_CLOCKGATE_DELAY,
271         .moduleid      = NVHOST_MODULE_TSEC,
272 };
273
274 static struct nvhost_device *t11_devices[] = {
275         &tegra_host1x02_device,
276         &tegra_display01_device,
277         &tegra_gr3d03_device,
278         &tegra_gr2d03_device,
279         &tegra_isp01_device,
280         &tegra_vi01_device,
281         &tegra_msenc02_device,
282         &tegra_dsi01_device,
283         &tegra_tsec01_device,
284 };
285
286 int tegra11_register_host1x_devices(void)
287 {
288         return nvhost_add_devices(t11_devices, ARRAY_SIZE(t11_devices));
289 }
290
291 static void t114_free_nvhost_channel(struct nvhost_channel *ch)
292 {
293         nvhost_free_channel_internal(ch, &t114_num_alloc_channels);
294 }
295
296 static struct nvhost_channel *t114_alloc_nvhost_channel(
297                 struct nvhost_device *dev)
298 {
299         return nvhost_alloc_channel_internal(dev->index,
300                 nvhost_get_host(dev)->info.nb_channels,
301                 &t114_num_alloc_channels);
302 }
303
304 #include "host1x/host1x_channel.c"
305 #include "host1x/host1x_cdma.c"
306 #include "host1x/host1x_debug.c"
307 #include "host1x/host1x_syncpt.c"
308 #include "host1x/host1x_intr.c"
309 #include "host1x/host1x_actmon.c"
310 #include "host1x/host1x_tickctrl.c"
311
312 int nvhost_init_t114_support(struct nvhost_master *host,
313         struct nvhost_chip_support *op)
314 {
315         int err;
316
317         op->channel = host1x_channel_ops;
318         op->cdma = host1x_cdma_ops;
319         op->push_buffer = host1x_pushbuffer_ops;
320         op->debug = host1x_debug_ops;
321         host->sync_aperture = host->aperture + HOST1X_CHANNEL_SYNC_REG_BASE;
322         op->syncpt = host1x_syncpt_ops;
323         op->intr = host1x_intr_ops;
324         err = nvhost_memmgr_init(op);
325         if (err)
326                 return err;
327         op->nvhost_dev.alloc_nvhost_channel = t114_alloc_nvhost_channel;
328         op->nvhost_dev.free_nvhost_channel = t114_free_nvhost_channel;
329         op->actmon = host1x_actmon_ops;
330         op->tickctrl = host1x_tickctrl_ops;
331
332         return 0;
333 }