video: tegra: host: Add Tegra11x host1x initialization
[linux-2.6.git] / drivers / video / tegra / host / t114 / t114.c
1 /*
2  * drivers/video/tegra/host/t114/t114.c
3  *
4  * Tegra Graphics Init for T114 Architecture Chips
5  *
6  * Copyright (c) 2010-2012, NVIDIA Corporation.
7  *
8  * This program is free software; you can redistribute it and/or modify
9  * it under the terms of the GNU General Public License as published by
10  * the Free Software Foundation; either version 2 of the License, or
11  * (at your option) any later version.
12  *
13  * This program is distributed in the hope that it will be useful, but WITHOUT
14  * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
15  * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
16  * more details.
17  *
18  * You should have received a copy of the GNU General Public License along
19  * with this program; if not, write to the Free Software Foundation, Inc.,
20  * 51 Franklin Street, Fifth Floor, Boston, MA  02110-1301, USA.
21  */
22
23 #include <linux/mutex.h>
24 #include <mach/powergate.h>
25 #include "../dev.h"
26 #include "host1x/host1x_cdma.h"
27 #include "t20/t20.h"
28 #include "t30/t30.h"
29 #include "t114.h"
30 #include "host1x/host1x_hardware.h"
31 #include "host1x/host1x_syncpt.h"
32 #include "gr3d/gr3d.h"
33 #include "gr3d/gr3d_t114.h"
34 #include "gr3d/scale3d.h"
35
36 #define NVMODMUTEX_2D_FULL   (1)
37 #define NVMODMUTEX_2D_SIMPLE (2)
38 #define NVMODMUTEX_2D_SB_A   (3)
39 #define NVMODMUTEX_2D_SB_B   (4)
40 #define NVMODMUTEX_3D        (5)
41 #define NVMODMUTEX_DISPLAYA  (6)
42 #define NVMODMUTEX_DISPLAYB  (7)
43 #define NVMODMUTEX_VI        (8)
44 #define NVMODMUTEX_DSI       (9)
45
46 #define HOST_EMC_FLOOR 300000000
47
48 static struct nvhost_device devices[] = {
49 {
50         /* channel 0 */
51         .name          = "display",
52         .syncpts       = BIT(NVSYNCPT_DISP0_A) | BIT(NVSYNCPT_DISP1_A) |
53                          BIT(NVSYNCPT_DISP0_B) | BIT(NVSYNCPT_DISP1_B) |
54                          BIT(NVSYNCPT_DISP0_C) | BIT(NVSYNCPT_DISP1_C) |
55                          BIT(NVSYNCPT_VBLANK0) | BIT(NVSYNCPT_VBLANK1),
56         .modulemutexes = BIT(NVMODMUTEX_DISPLAYA) | BIT(NVMODMUTEX_DISPLAYB),
57         NVHOST_MODULE_NO_POWERGATE_IDS,
58         NVHOST_DEFAULT_CLOCKGATE_DELAY,
59 },
60 {
61         /* channel 1 */
62         .name          = "gr3d",
63         .syncpts       = BIT(NVSYNCPT_3D),
64         .waitbases     = BIT(NVWAITBASE_3D),
65         .modulemutexes = BIT(NVMODMUTEX_3D),
66         .class         = NV_GRAPHICS_3D_CLASS_ID,
67         .prepare_poweroff = nvhost_gr3d_prepare_power_off,
68         .busy = nvhost_scale3d_notify_busy,
69         .idle = nvhost_scale3d_notify_idle,
70         .init = nvhost_scale3d_init,
71         .deinit = nvhost_scale3d_deinit,
72         .clocks = {{"gr3d", UINT_MAX},
73                         {"emc", HOST_EMC_FLOOR} },
74         NVHOST_MODULE_NO_POWERGATE_IDS,
75         NVHOST_DEFAULT_CLOCKGATE_DELAY,
76 },
77 {
78         /* channel 2 */
79         .name          = "gr2d",
80         .syncpts       = BIT(NVSYNCPT_2D_0) | BIT(NVSYNCPT_2D_1),
81         .waitbases     = BIT(NVWAITBASE_2D_0) | BIT(NVWAITBASE_2D_1),
82         .modulemutexes = BIT(NVMODMUTEX_2D_FULL) | BIT(NVMODMUTEX_2D_SIMPLE) |
83                          BIT(NVMODMUTEX_2D_SB_A) | BIT(NVMODMUTEX_2D_SB_B),
84         .clocks = {{"gr2d", 0},
85                         {"epp", UINT_MAX},
86                         {"emc", HOST_EMC_FLOOR} },
87         NVHOST_MODULE_NO_POWERGATE_IDS,
88         NVHOST_DEFAULT_CLOCKGATE_DELAY,
89 },
90 {
91         /* channel 3 */
92         .name    = "isp",
93         .syncpts = 0,
94         NVHOST_MODULE_NO_POWERGATE_IDS,
95         NVHOST_DEFAULT_CLOCKGATE_DELAY,
96 },
97 {
98         /* channel 4 */
99         .name          = "vi",
100         .syncpts       = BIT(NVSYNCPT_CSI_VI_0) | BIT(NVSYNCPT_CSI_VI_1) |
101                          BIT(NVSYNCPT_VI_ISP_0) | BIT(NVSYNCPT_VI_ISP_1) |
102                          BIT(NVSYNCPT_VI_ISP_2) | BIT(NVSYNCPT_VI_ISP_3) |
103                          BIT(NVSYNCPT_VI_ISP_4),
104         .modulemutexes = BIT(NVMODMUTEX_VI),
105         .exclusive     = true,
106         NVHOST_MODULE_NO_POWERGATE_IDS,
107         NVHOST_DEFAULT_CLOCKGATE_DELAY,
108 },
109 {
110         /* channel 5 */
111         .name          = "msenc",
112         .syncpts       = BIT(NVSYNCPT_MSENC),
113         .waitbases     = BIT(NVWAITBASE_MSENC),
114         .class         = NV_VIDEO_ENCODE_MSENC_CLASS_ID,
115         .exclusive     = true,
116         .keepalive     = true,
117         NVHOST_MODULE_NO_POWERGATE_IDS,
118         NVHOST_DEFAULT_CLOCKGATE_DELAY,
119 },
120 {
121         /* channel 6 */
122         .name          = "dsi",
123         .syncpts       = BIT(NVSYNCPT_DSI),
124         .modulemutexes = BIT(NVMODMUTEX_DSI),
125         NVHOST_MODULE_NO_POWERGATE_IDS,
126         NVHOST_DEFAULT_CLOCKGATE_DELAY,
127 },
128 {
129         /* channel 7 */
130         .name          = "tsec",
131         .syncpts       = BIT(NVSYNCPT_TSEC),
132         .waitbases     = BIT(NVWAITBASE_TSEC),
133         .class         = NV_TSEC_CLASS_ID,
134         .exclusive     = true,
135         NVHOST_MODULE_NO_POWERGATE_IDS,
136         NVHOST_DEFAULT_CLOCKGATE_DELAY,
137 } };
138
139 static inline int t114_nvhost_hwctx_handler_init(
140         struct nvhost_hwctx_handler *h,
141         const char *module)
142 {
143         if (strcmp(module, "gr3d") == 0)
144                 return t114_nvhost_3dctx_handler_init(h);
145
146         return 0;
147 }
148
149 static inline void __iomem *t114_channel_aperture(void __iomem *p, int ndx)
150 {
151         p += NV_HOST1X_CHANNEL0_BASE;
152         p += ndx * NV_HOST1X_CHANNEL_MAP_SIZE_BYTES;
153         return p;
154 }
155
156 static int t114_channel_init(struct nvhost_channel *ch,
157                             struct nvhost_master *dev, int index)
158 {
159         ch->chid = index;
160         ch->dev = &devices[index];
161         mutex_init(&ch->reflock);
162         mutex_init(&ch->submitlock);
163
164         nvhost_device_register(ch->dev);
165         ch->aperture = t114_channel_aperture(dev->aperture, index);
166
167         return t114_nvhost_hwctx_handler_init(&ch->ctxhandler, ch->dev->name);
168 }
169
170 int nvhost_init_t114_channel_support(struct nvhost_master *host)
171 {
172         int result = nvhost_init_t20_channel_support(host);
173         host->op.channel.init = t114_channel_init;
174
175         return result;
176 }
177
178 int nvhost_init_t114_support(struct nvhost_master *host)
179 {
180         int err;
181
182         /* don't worry about cleaning up on failure... "remove" does it. */
183         err = nvhost_init_t114_channel_support(host);
184         if (err)
185                 return err;
186         err = host1x_init_cdma_support(host);
187         if (err)
188                 return err;
189         err = nvhost_init_t20_debug_support(host);
190         if (err)
191                 return err;
192         err = host1x_init_syncpt_support(host);
193         if (err)
194                 return err;
195         err = nvhost_init_t20_intr_support(host);
196         if (err)
197                 return err;
198         err = nvhost_init_t20_cpuaccess_support(host);
199         if (err)
200                 return err;
201         return 0;
202 }