video: tegra: dc: power optimize DC and host1x clk
[linux-2.6.git] / drivers / video / tegra / dc / hdmi.c
1 /*
2  * drivers/video/tegra/dc/hdmi.c
3  *
4  * Copyright (C) 2010 Google, Inc.
5  * Author: Erik Gilling <konkers@android.com>
6  *
7  * Copyright (c) 2010-2012, NVIDIA CORPORATION, All rights reserved.
8  *
9  * This software is licensed under the terms of the GNU General Public
10  * License version 2, as published by the Free Software Foundation, and
11  * may be copied, distributed, and modified under those terms.
12  *
13  * This program is distributed in the hope that it will be useful,
14  * but WITHOUT ANY WARRANTY; without even the implied warranty of
15  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
16  * GNU General Public License for more details.
17  *
18  */
19
20 #include <linux/clk.h>
21 #include <linux/delay.h>
22 #include <linux/err.h>
23 #include <linux/fb.h>
24 #include <linux/gpio.h>
25 #include <linux/interrupt.h>
26 #include <linux/kernel.h>
27 #include <linux/slab.h>
28 #include <linux/spinlock.h>
29 #ifdef CONFIG_SWITCH
30 #include <linux/switch.h>
31 #endif
32 #include <linux/workqueue.h>
33 #include <linux/debugfs.h>
34 #include <linux/seq_file.h>
35 #include <linux/device.h>
36
37 #include <mach/clk.h>
38 #include <mach/dc.h>
39 #include <mach/fb.h>
40 #include <linux/nvhost.h>
41 #include <mach/hdmi-audio.h>
42
43 #include <video/tegrafb.h>
44
45 #include "dc_reg.h"
46 #include "dc_priv.h"
47 #include "hdmi_reg.h"
48 #include "hdmi.h"
49 #include "edid.h"
50 #include "nvhdcp.h"
51
52 /* datasheet claims this will always be 216MHz */
53 #define HDMI_AUDIOCLK_FREQ              216000000
54
55 #define HDMI_REKEY_DEFAULT              56
56
57 #define HDMI_ELD_RESERVED1_INDEX                1
58 #define HDMI_ELD_RESERVED2_INDEX                3
59 #define HDMI_ELD_VER_INDEX                      0
60 #define HDMI_ELD_BASELINE_LEN_INDEX             2
61 #define HDMI_ELD_CEA_VER_MNL_INDEX              4
62 #define HDMI_ELD_SAD_CNT_CON_TYP_SAI_HDCP_INDEX         5
63 #define HDMI_ELD_AUD_SYNC_DELAY_INDEX   6
64 #define HDMI_ELD_SPK_ALLOC_INDEX                7
65 #define HDMI_ELD_PORT_ID_INDEX          8
66 #define HDMI_ELD_MANF_NAME_INDEX                16
67 #define HDMI_ELD_PRODUCT_CODE_INDEX             18
68 #define HDMI_ELD_MONITOR_NAME_INDEX             20
69
70 /* These two values need to be cross checked in case of
71      addition/removal from tegra_dc_hdmi_aspect_ratios[] */
72 #define TEGRA_DC_HDMI_MIN_ASPECT_RATIO_PERCENT  80
73 #define TEGRA_DC_HDMI_MAX_ASPECT_RATIO_PERCENT  320
74
75 /* Percentage equivalent of standard aspect ratios
76     accurate upto two decimal digits */
77 static int tegra_dc_hdmi_aspect_ratios[] = {
78         /*   3:2        */      150,
79         /*   4:3        */      133,
80         /*   4:5        */       80,
81         /*   5:4        */      125,
82         /*   9:5        */      180,
83         /*  16:5        */      320,
84         /*  16:9        */      178,
85         /* 16:10        */      160,
86         /* 19:10        */      190,
87         /* 25:16        */      156,
88         /* 64:35        */      183,
89         /* 72:35        */      206
90 };
91
92 struct tegra_dc_hdmi_data {
93         struct tegra_dc                 *dc;
94         struct tegra_edid               *edid;
95         struct tegra_edid_hdmi_eld              eld;
96         struct tegra_nvhdcp             *nvhdcp;
97         struct delayed_work             work;
98
99         struct resource                 *base_res;
100         void __iomem                    *base;
101         struct clk                      *clk;
102
103         struct clk                      *disp1_clk;
104         struct clk                      *disp2_clk;
105         struct clk                      *hda_clk;
106         struct clk                      *hda2codec_clk;
107         struct clk                      *hda2hdmi_clk;
108
109 #ifdef CONFIG_SWITCH
110         struct switch_dev               hpd_switch;
111 #endif
112
113         spinlock_t                      suspend_lock;
114         bool                            suspended;
115         bool                            eld_retrieved;
116         bool                            clk_enabled;
117         unsigned                        audio_freq;
118         unsigned                        audio_source;
119         bool                            audio_inject_null;
120
121         bool                            dvi;
122 };
123
124 struct tegra_dc_hdmi_data *dc_hdmi;
125
126 const struct fb_videomode tegra_dc_hdmi_supported_modes[] = {
127         /* 1280x720p 60hz: EIA/CEA-861-B Format 4 */
128         {
129                 .xres =         1280,
130                 .yres =         720,
131                 .pixclock =     KHZ2PICOS(74250),
132                 .hsync_len =    40,     /* h_sync_width */
133                 .vsync_len =    5,      /* v_sync_width */
134                 .left_margin =  220,    /* h_back_porch */
135                 .upper_margin = 20,     /* v_back_porch */
136                 .right_margin = 110,    /* h_front_porch */
137                 .lower_margin = 5,      /* v_front_porch */
138                 .vmode =        FB_VMODE_NONINTERLACED,
139                 .sync = FB_SYNC_HOR_HIGH_ACT | FB_SYNC_VERT_HIGH_ACT,
140         },
141
142         /* 1280x720p 60hz: EIA/CEA-861-B Format 4 (Stereo)*/
143         {
144                 .xres =         1280,
145                 .yres =         720,
146                 .pixclock =     KHZ2PICOS(74250),
147                 .hsync_len =    40,     /* h_sync_width */
148                 .vsync_len =    5,      /* v_sync_width */
149                 .left_margin =  220,    /* h_back_porch */
150                 .upper_margin = 20,     /* v_back_porch */
151                 .right_margin = 110,    /* h_front_porch */
152                 .lower_margin = 5,      /* v_front_porch */
153                 .vmode = FB_VMODE_NONINTERLACED |
154 #ifndef CONFIG_TEGRA_HDMI_74MHZ_LIMIT
155                                  FB_VMODE_STEREO_FRAME_PACK,
156 #else
157                                  FB_VMODE_STEREO_LEFT_RIGHT,
158 #endif
159                 .sync = FB_SYNC_HOR_HIGH_ACT | FB_SYNC_VERT_HIGH_ACT,
160         },
161
162         /* 720x480p 59.94hz: EIA/CEA-861-B Formats 2 & 3 */
163         {
164                 .xres =         720,
165                 .yres =         480,
166                 .pixclock =     KHZ2PICOS(27000),
167                 .hsync_len =    62,     /* h_sync_width */
168                 .vsync_len =    6,      /* v_sync_width */
169                 .left_margin =  60,     /* h_back_porch */
170                 .upper_margin = 30,     /* v_back_porch */
171                 .right_margin = 16,     /* h_front_porch */
172                 .lower_margin = 9,      /* v_front_porch */
173                 .vmode =        FB_VMODE_NONINTERLACED,
174                 .sync = 0,
175         },
176
177         /* 640x480p 60hz: EIA/CEA-861-B Format 1 */
178         {
179                 .xres =         640,
180                 .yres =         480,
181                 .pixclock =     KHZ2PICOS(25200),
182                 .hsync_len =    96,     /* h_sync_width */
183                 .vsync_len =    2,      /* v_sync_width */
184                 .left_margin =  48,     /* h_back_porch */
185                 .upper_margin = 33,     /* v_back_porch */
186                 .right_margin = 16,     /* h_front_porch */
187                 .lower_margin = 10,     /* v_front_porch */
188                 .vmode =        FB_VMODE_NONINTERLACED,
189                 .sync = 0,
190         },
191
192         /* 720x576p 50hz EIA/CEA-861-B Formats 17 & 18 */
193         {
194                 .xres =         720,
195                 .yres =         576,
196                 .pixclock =     KHZ2PICOS(27000),
197                 .hsync_len =    64,     /* h_sync_width */
198                 .vsync_len =    5,      /* v_sync_width */
199                 .left_margin =  68,     /* h_back_porch */
200                 .upper_margin = 39,     /* v_back_porch */
201                 .right_margin = 12,     /* h_front_porch */
202                 .lower_margin = 5,      /* v_front_porch */
203                 .vmode =        FB_VMODE_NONINTERLACED,
204                 .sync = 0,
205         },
206
207         /* 1920x1080p 23.98/24hz: EIA/CEA-861-B Format 32 (Stereo)*/
208         {
209                 .xres =         1920,
210                 .yres =         1080,
211                 .pixclock =     KHZ2PICOS(74250),
212                 .hsync_len =    44,     /* h_sync_width */
213                 .vsync_len =    5,      /* v_sync_width */
214                 .left_margin =  148,    /* h_back_porch */
215                 .upper_margin = 36,     /* v_back_porch */
216                 .right_margin = 638,    /* h_front_porch */
217                 .lower_margin = 4,      /* v_front_porch */
218                 .vmode = FB_VMODE_NONINTERLACED |
219 #ifndef CONFIG_TEGRA_HDMI_74MHZ_LIMIT
220                                  FB_VMODE_STEREO_FRAME_PACK,
221 #else
222                                  FB_VMODE_STEREO_LEFT_RIGHT,
223 #endif
224                 .sync = FB_SYNC_HOR_HIGH_ACT | FB_SYNC_VERT_HIGH_ACT,
225         },
226
227         /* 1920x1080p 30Hz EIA/CEA-861-B Format 34 */
228         {
229                 .xres =         1920,
230                 .yres =         1080,
231                 .pixclock =     KHZ2PICOS(74250),
232                 .hsync_len =    44,     /* h_sync_width */
233                 .vsync_len =    5,      /* v_sync_width */
234                 .left_margin =  148,    /* h_back_porch */
235                 .upper_margin = 36,     /* v_back_porch */
236                 .right_margin = 88,     /* h_front_porch */
237                 .lower_margin = 4,      /* v_front_porch */
238                 .vmode =        FB_VMODE_NONINTERLACED,
239                 .sync = FB_SYNC_HOR_HIGH_ACT | FB_SYNC_VERT_HIGH_ACT,
240         },
241
242         /* 1920x1080p 59.94/60hz CVT */
243         {
244                 .xres =         1920,
245                 .yres =         1080,
246                 .pixclock =     KHZ2PICOS(138500),
247                 .hsync_len =    32,     /* h_sync_width */
248                 .vsync_len =    5,      /* v_sync_width */
249                 .left_margin =  80,     /* h_back_porch */
250                 .upper_margin = 23,     /* v_back_porch */
251                 .right_margin = 48,     /* h_front_porch */
252                 .lower_margin = 3,      /* v_front_porch */
253                 .vmode = FB_VMODE_NONINTERLACED,
254                 .sync = FB_SYNC_VERT_HIGH_ACT,
255         },
256
257         /* 1920x1080p 59.94/60hz EIA/CEA-861-B Format 16 */
258         {
259                 .xres =         1920,
260                 .yres =         1080,
261                 .pixclock =     KHZ2PICOS(148500),
262                 .hsync_len =    44,     /* h_sync_width */
263                 .vsync_len =    5,      /* v_sync_width */
264                 .left_margin =  148,    /* h_back_porch */
265                 .upper_margin = 36,     /* v_back_porch */
266                 .right_margin = 88,     /* h_front_porch */
267                 .lower_margin = 4,      /* v_front_porch */
268                 .vmode =        FB_VMODE_NONINTERLACED,
269                 .sync = FB_SYNC_HOR_HIGH_ACT | FB_SYNC_VERT_HIGH_ACT,
270         },
271
272         /*
273         * Few VGA/SVGA modes to support monitors with lower
274         * resolutions or to support HDMI<->DVI connection
275         */
276
277         /* 640x480p 75hz */
278         {
279                 .xres =         640,
280                 .yres =         480,
281                 .pixclock =     KHZ2PICOS(31500),
282                 .hsync_len =    96,     /* h_sync_width */
283                 .vsync_len =    2,      /* v_sync_width */
284                 .left_margin =  48,     /* h_back_porch */
285                 .upper_margin = 32,     /* v_back_porch */
286                 .right_margin = 16,     /* h_front_porch */
287                 .lower_margin = 1,      /* v_front_porch */
288                 .vmode =        FB_VMODE_NONINTERLACED,
289                 .sync = 0,
290         },
291         /* 720x400p 59hz */
292         {
293                 .xres =         720,
294                 .yres =         400,
295                 .pixclock =     KHZ2PICOS(35500),
296                 .hsync_len =    72,     /* h_sync_width */
297                 .vsync_len =    3,      /* v_sync_width */
298                 .left_margin =  108,    /* h_back_porch */
299                 .upper_margin = 42,     /* v_back_porch */
300                 .right_margin = 36,     /* h_front_porch */
301                 .lower_margin = 1,      /* v_front_porch */
302                 .vmode =        FB_VMODE_NONINTERLACED,
303                 .sync  = FB_SYNC_VERT_HIGH_ACT,
304         },
305         /* 800x600p 60hz */
306         {
307                 .xres =         800,
308                 .yres =         600,
309                 .pixclock =     KHZ2PICOS(40000),
310                 .hsync_len =    128,    /* h_sync_width */
311                 .vsync_len =    4,      /* v_sync_width */
312                 .left_margin =  88,     /* h_back_porch */
313                 .upper_margin = 23,     /* v_back_porch */
314                 .right_margin = 40,     /* h_front_porch */
315                 .lower_margin = 1,      /* v_front_porch */
316                 .vmode =        FB_VMODE_NONINTERLACED,
317                 .sync = FB_SYNC_HOR_HIGH_ACT | FB_SYNC_VERT_HIGH_ACT,
318         },
319         /* 800x600p 75hz */
320         {
321                 .xres =         800,
322                 .yres =         600,
323                 .pixclock =     KHZ2PICOS(49500),
324                 .hsync_len =    80,     /* h_sync_width */
325                 .vsync_len =    2,      /* v_sync_width */
326                 .left_margin =  160,    /* h_back_porch */
327                 .upper_margin = 21,     /* v_back_porch */
328                 .right_margin = 16,     /* h_front_porch */
329                 .lower_margin = 1,      /* v_front_porch */
330                 .vmode =        FB_VMODE_NONINTERLACED,
331                 .sync = FB_SYNC_HOR_HIGH_ACT | FB_SYNC_VERT_HIGH_ACT,
332         },
333         /* 1024x768p 60hz */
334         {
335                 .xres =         1024,
336                 .yres =         768,
337                 .pixclock =     KHZ2PICOS(65000),
338                 .hsync_len =    136,    /* h_sync_width */
339                 .vsync_len =    6,      /* v_sync_width */
340                 .left_margin =  160,    /* h_back_porch */
341                 .upper_margin = 29,     /* v_back_porch */
342                 .right_margin = 24,     /* h_front_porch */
343                 .lower_margin = 3,      /* v_front_porch */
344                 .vmode =        FB_VMODE_NONINTERLACED,
345                 .sync = 0,
346         },
347         /* 1024x768p 75hz */
348         {
349                 .xres =         1024,
350                 .yres =         768,
351                 .pixclock =     KHZ2PICOS(78800),
352                 .hsync_len =    96,     /* h_sync_width */
353                 .vsync_len =    3,      /* v_sync_width */
354                 .left_margin =  176,    /* h_back_porch */
355                 .upper_margin = 28,     /* v_back_porch */
356                 .right_margin = 16,     /* h_front_porch */
357                 .lower_margin = 1,      /* v_front_porch */
358                 .vmode =        FB_VMODE_NONINTERLACED,
359                 .sync = 0,
360         },
361         /* 1152x864p 75hz */
362         {
363                 .xres =         1152,
364                 .yres =         864,
365                 .pixclock =     KHZ2PICOS(108000),
366                 .hsync_len =    128,    /* h_sync_width */
367                 .vsync_len =    3,      /* v_sync_width */
368                 .left_margin =  256,    /* h_back_porch */
369                 .upper_margin = 32,     /* v_back_porch */
370                 .right_margin = 64,     /* h_front_porch */
371                 .lower_margin = 1,      /* v_front_porch */
372                 .vmode =        FB_VMODE_NONINTERLACED,
373                 .sync = FB_SYNC_HOR_HIGH_ACT | FB_SYNC_VERT_HIGH_ACT,
374         },
375         /* 1280x800p 60hz */
376         {
377                 .xres =         1280,
378                 .yres =         800,
379                 .pixclock =     KHZ2PICOS(83460),
380                 .hsync_len =    136,    /* h_sync_width */
381                 .vsync_len =    3,      /* v_sync_width */
382                 .left_margin =  200,    /* h_back_porch */
383                 .upper_margin = 24,     /* v_back_porch */
384                 .right_margin = 64,     /* h_front_porch */
385                 .lower_margin = 1,      /* v_front_porch */
386                 .vmode =        FB_VMODE_NONINTERLACED,
387                 .sync =         FB_SYNC_VERT_HIGH_ACT,
388         },
389         /* 1280x960p 60hz */
390         {
391                 .xres =         1280,
392                 .yres =         960,
393                 .pixclock =     KHZ2PICOS(108000),
394                 .hsync_len =    136,    /* h_sync_width */
395                 .vsync_len =    3,      /* v_sync_width */
396                 .left_margin =  216,    /* h_back_porch */
397                 .upper_margin = 30,     /* v_back_porch */
398                 .right_margin = 80,     /* h_front_porch */
399                 .lower_margin = 1,      /* v_front_porch */
400                 .vmode =        FB_VMODE_NONINTERLACED,
401                 .sync =         FB_SYNC_VERT_HIGH_ACT,
402         },
403         /* 1280x1024p 60hz */
404         {
405                 .xres =         1280,
406                 .yres =         1024,
407                 .pixclock =     KHZ2PICOS(108000),
408                 .hsync_len =    112,    /* h_sync_width */
409                 .vsync_len =    3,      /* v_sync_width */
410                 .left_margin =  248,    /* h_back_porch */
411                 .upper_margin = 38,     /* v_back_porch */
412                 .right_margin = 48,     /* h_front_porch */
413                 .lower_margin = 1,      /* v_front_porch */
414                 .vmode =        FB_VMODE_NONINTERLACED,
415                 .sync = FB_SYNC_HOR_HIGH_ACT | FB_SYNC_VERT_HIGH_ACT,
416         },
417         /* 1280x1024p 75hz */
418         {
419                 .xres =         1280,
420                 .yres =         1024,
421                 .pixclock =     KHZ2PICOS(135000),
422                 .hsync_len =    144,    /* h_sync_width */
423                 .vsync_len =    3,      /* v_sync_width */
424                 .left_margin =  248,    /* h_back_porch */
425                 .upper_margin = 38,     /* v_back_porch */
426                 .right_margin = 16,     /* h_front_porch */
427                 .lower_margin = 1,      /* v_front_porch */
428                 .vmode =        FB_VMODE_NONINTERLACED,
429                 .sync = FB_SYNC_HOR_HIGH_ACT | FB_SYNC_VERT_HIGH_ACT,
430         },
431         /* 1368x768p 60hz */
432         {
433                 .xres =         1368,
434                 .yres =         768,
435                 .pixclock =     KHZ2PICOS(85860),
436                 .hsync_len =    144,    /* h_sync_width */
437                 .vsync_len =    3,      /* v_sync_width */
438                 .left_margin =  216,    /* h_back_porch */
439                 .upper_margin = 23,     /* v_back_porch */
440                 .right_margin = 72,     /* h_front_porch */
441                 .lower_margin = 1,      /* v_front_porch */
442                 .vmode =        FB_VMODE_NONINTERLACED,
443                 .sync =         FB_SYNC_VERT_HIGH_ACT,
444         },
445         /* 1440x900p 60hz */
446         {
447                 .xres =         1440,
448                 .yres =         900,
449                 .pixclock =     KHZ2PICOS(106470),
450                 .hsync_len =    152,    /* h_sync_width */
451                 .vsync_len =    3,      /* v_sync_width */
452                 .left_margin =  232,    /* h_back_porch */
453                 .upper_margin = 28,     /* v_back_porch */
454                 .right_margin = 80,     /* h_front_porch */
455                 .lower_margin = 1,      /* v_front_porch */
456                 .vmode =        FB_VMODE_NONINTERLACED,
457                 .sync =         FB_SYNC_VERT_HIGH_ACT,
458         },
459         /* 1600x1200p 60hz */
460         {
461                 .xres =         1600,
462                 .yres =         1200,
463                 .pixclock =     KHZ2PICOS(162000),
464                 .hsync_len =    192,    /* h_sync_width */
465                 .vsync_len =    3,      /* v_sync_width */
466                 .left_margin =  304,    /* h_back_porch */
467                 .upper_margin = 46,     /* v_back_porch */
468                 .right_margin = 64,     /* h_front_porch */
469                 .lower_margin = 1,      /* v_front_porch */
470                 .vmode =        FB_VMODE_NONINTERLACED,
471                 .sync = FB_SYNC_HOR_HIGH_ACT | FB_SYNC_VERT_HIGH_ACT,
472         },
473         /* 1600x1200p 75hz */
474         {
475                 .xres =         1600,
476                 .yres =         1200,
477                 .pixclock =     KHZ2PICOS(202500),
478                 .hsync_len =    192,    /* h_sync_width */
479                 .vsync_len =    3,      /* v_sync_width */
480                 .left_margin =  304,    /* h_back_porch */
481                 .upper_margin = 46,     /* v_back_porch */
482                 .right_margin = 64,     /* h_front_porch */
483                 .lower_margin = 1,      /* v_front_porch */
484                 .vmode =        FB_VMODE_NONINTERLACED,
485                 .sync = FB_SYNC_HOR_HIGH_ACT | FB_SYNC_VERT_HIGH_ACT,
486         },
487         /* 1680x1050p 59.94/60hz */
488         {
489                 .xres =         1680,
490                 .yres =         1050,
491                 .pixclock =     KHZ2PICOS(147140),
492                 .hsync_len =    184,    /* h_sync_width */
493                 .vsync_len =    3,      /* v_sync_width */
494                 .left_margin =  288,    /* h_back_porch */
495                 .upper_margin = 33,     /* v_back_porch */
496                 .right_margin = 104,    /* h_front_porch */
497                 .lower_margin = 1,      /* v_front_porch */
498                 .vmode =        FB_VMODE_NONINTERLACED,
499                 .sync = FB_SYNC_VERT_HIGH_ACT,
500         },
501 };
502
503 /* CVT timing representation of VESA modes*/
504 const struct fb_videomode tegra_dc_hdmi_supported_cvt_modes[] = {
505
506         /* 640x480p 60hz */
507         {
508                 .refresh =      60,
509                 .xres =         640,
510                 .yres =         480,
511                 .pixclock =     KHZ2PICOS(23750),
512                 .hsync_len =    64,     /* h_sync_width */
513                 .vsync_len =    4,      /* v_sync_width */
514                 .left_margin =  80,     /* h_back_porch */
515                 .upper_margin = 17,     /* v_back_porch */
516                 .right_margin = 16,     /* h_front_porch */
517                 .lower_margin = 3,      /* v_front_porch */
518                 .vmode =        FB_VMODE_NONINTERLACED,
519                 .sync = FB_SYNC_VERT_HIGH_ACT,
520         },
521         /* 640x480p 75hz */
522         {
523                 .refresh =      75,
524                 .xres =         640,
525                 .yres =         480,
526                 .pixclock =     KHZ2PICOS(30750),
527                 .hsync_len =    64,     /* h_sync_width */
528                 .vsync_len =    4,      /* v_sync_width */
529                 .left_margin =  88,     /* h_back_porch */
530                 .upper_margin = 21,     /* v_back_porch */
531                 .right_margin = 24,     /* h_front_porch */
532                 .lower_margin = 3,      /* v_front_porch */
533                 .vmode =        FB_VMODE_NONINTERLACED,
534                 .sync = FB_SYNC_VERT_HIGH_ACT,
535         },
536         /* 720x400p 59hz */
537         {
538                 .refresh =      59,
539                 .xres =         720,
540                 .yres =         400,
541                 .pixclock =     KHZ2PICOS(22000),
542                 .hsync_len =    64,     /* h_sync_width */
543                 .vsync_len =    10,     /* v_sync_width */
544                 .left_margin =  88,     /* h_back_porch */
545                 .upper_margin = 14,     /* v_back_porch */
546                 .right_margin = 24,     /* h_front_porch */
547                 .lower_margin = 3,      /* v_front_porch */
548                 .vmode =        FB_VMODE_NONINTERLACED,
549                 .sync  = FB_SYNC_VERT_HIGH_ACT,
550         },
551         /* 800x600p 60hz */
552         {
553                 .refresh =      60,
554                 .xres =         800,
555                 .yres =         600,
556                 .pixclock =     KHZ2PICOS(38250),
557                 .hsync_len =    80,     /* h_sync_width */
558                 .vsync_len =    4,      /* v_sync_width */
559                 .left_margin =  112,    /* h_back_porch */
560                 .upper_margin = 21,     /* v_back_porch */
561                 .right_margin = 32,     /* h_front_porch */
562                 .lower_margin = 3,      /* v_front_porch */
563                 .vmode =        FB_VMODE_NONINTERLACED,
564                 .sync =         FB_SYNC_VERT_HIGH_ACT,
565         },
566         /* 800x600p 75hz */
567         {
568                 .refresh =      75,
569                 .xres =         800,
570                 .yres =         600,
571                 .pixclock =     KHZ2PICOS(49000),
572                 .hsync_len =    80,     /* h_sync_width */
573                 .vsync_len =    4,      /* v_sync_width */
574                 .left_margin =  120,    /* h_back_porch */
575                 .upper_margin = 26,     /* v_back_porch */
576                 .right_margin = 40,     /* h_front_porch */
577                 .lower_margin = 3,      /* v_front_porch */
578                 .vmode =        FB_VMODE_NONINTERLACED,
579                 .sync = FB_SYNC_VERT_HIGH_ACT,
580         },
581         /* 1024x768p 60hz */
582         {
583                 .refresh =      60,
584                 .xres =         1024,
585                 .yres =         768,
586                 .pixclock =     KHZ2PICOS(63500),
587                 .hsync_len =    104,    /* h_sync_width */
588                 .vsync_len =    4,      /* v_sync_width */
589                 .left_margin =  152,    /* h_back_porch */
590                 .upper_margin = 27,     /* v_back_porch */
591                 .right_margin = 48,     /* h_front_porch */
592                 .lower_margin = 3,      /* v_front_porch */
593                 .vmode =        FB_VMODE_NONINTERLACED,
594                 .sync = FB_SYNC_VERT_HIGH_ACT,
595         },
596         /* 1024x768p 75hz */
597         {
598                 .refresh =      75,
599                 .xres =         1024,
600                 .yres =         768,
601                 .pixclock =     KHZ2PICOS(82000),
602                 .hsync_len =    104,    /* h_sync_width */
603                 .vsync_len =    4,      /* v_sync_width */
604                 .left_margin =  168,    /* h_back_porch */
605                 .upper_margin = 34,     /* v_back_porch */
606                 .right_margin = 64,     /* h_front_porch */
607                 .lower_margin = 3,      /* v_front_porch */
608                 .vmode =        FB_VMODE_NONINTERLACED,
609                 .sync = FB_SYNC_VERT_HIGH_ACT,
610         },
611         /* 1152x864p 75hz */
612         {
613                 .refresh =      75,
614                 .xres =         1152,
615                 .yres =         864,
616                 .pixclock =     KHZ2PICOS(104500),
617                 .hsync_len =    120,    /* h_sync_width */
618                 .vsync_len =    10,     /* v_sync_width */
619                 .left_margin =  192,    /* h_back_porch */
620                 .upper_margin = 38,     /* v_back_porch */
621                 .right_margin = 72,     /* h_front_porch */
622                 .lower_margin = 3,      /* v_front_porch */
623                 .vmode =        FB_VMODE_NONINTERLACED,
624                 .sync = FB_SYNC_VERT_HIGH_ACT,
625         },
626         /* 1280x800p 60hz */
627         {
628                 .refresh =      60,
629                 .xres =         1280,
630                 .yres =         800,
631                 .pixclock =     KHZ2PICOS(83500),
632                 .hsync_len =    128,    /* h_sync_width */
633                 .vsync_len =    6,      /* v_sync_width */
634                 .left_margin =  200,    /* h_back_porch */
635                 .upper_margin = 28,     /* v_back_porch */
636                 .right_margin = 72,     /* h_front_porch */
637                 .lower_margin = 3,      /* v_front_porch */
638                 .vmode =        FB_VMODE_NONINTERLACED,
639                 .sync =         FB_SYNC_VERT_HIGH_ACT,
640         },
641         /* 1280x960p 60hz */
642         {
643                 .refresh =      60,
644                 .xres =         1280,
645                 .yres =         960,
646                 .pixclock =     KHZ2PICOS(101250),
647                 .hsync_len =    128,    /* h_sync_width */
648                 .vsync_len =    4,      /* v_sync_width */
649                 .left_margin =  208,    /* h_back_porch */
650                 .upper_margin = 33,     /* v_back_porch */
651                 .right_margin = 80,     /* h_front_porch */
652                 .lower_margin = 3,      /* v_front_porch */
653                 .vmode =        FB_VMODE_NONINTERLACED,
654                 .sync = FB_SYNC_VERT_HIGH_ACT,
655         },
656         /* 1280x1024p 60hz */
657         {
658                 .refresh =      60,
659                 .xres =         1280,
660                 .yres =         1024,
661                 .pixclock =     KHZ2PICOS(109000),
662                 .hsync_len =    136,    /* h_sync_width */
663                 .vsync_len =    7,      /* v_sync_width */
664                 .left_margin =  216,    /* h_back_porch */
665                 .upper_margin = 36,     /* v_back_porch */
666                 .right_margin = 80,     /* h_front_porch */
667                 .lower_margin = 3,      /* v_front_porch */
668                 .vmode =        FB_VMODE_NONINTERLACED,
669                 .sync = FB_SYNC_VERT_HIGH_ACT,
670         },
671
672         /* 1280x1024p 75hz */
673         {
674                 .refresh =      75,
675                 .xres =         1280,
676                 .yres =         1024,
677                 .pixclock =     KHZ2PICOS(138750),
678                 .hsync_len =    136,    /* h_sync_width */
679                 .vsync_len =    7,      /* v_sync_width */
680                 .left_margin =  224,    /* h_back_porch */
681                 .upper_margin = 45,     /* v_back_porch */
682                 .right_margin = 88,     /* h_front_porch */
683                 .lower_margin = 3,      /* v_front_porch */
684                 .vmode =        FB_VMODE_NONINTERLACED,
685                 .sync = FB_SYNC_VERT_HIGH_ACT,
686         },
687         /* 1368x768p 60hz */
688         {
689                 .refresh =      60,
690                 .xres =         1368,
691                 .yres =         768,
692                 .pixclock =     KHZ2PICOS(85250),
693                 .hsync_len =    136,    /* h_sync_width */
694                 .vsync_len =    10,     /* v_sync_width */
695                 .left_margin =  208,    /* h_back_porch */
696                 .upper_margin = 27,     /* v_back_porch */
697                 .right_margin = 72,     /* h_front_porch */
698                 .lower_margin = 3,      /* v_front_porch */
699                 .vmode =        FB_VMODE_NONINTERLACED,
700                 .sync =         FB_SYNC_VERT_HIGH_ACT,
701         },
702         /* 1440x900p 60hz */
703         {
704                 .refresh =      60,
705                 .xres =         1440,
706                 .yres =         900,
707                 .pixclock =     KHZ2PICOS(106500),
708                 .hsync_len =    152,    /* h_sync_width */
709                 .vsync_len =    6,      /* v_sync_width */
710                 .left_margin =  232,    /* h_back_porch */
711                 .upper_margin = 31,     /* v_back_porch */
712                 .right_margin = 80,     /* h_front_porch */
713                 .lower_margin = 3,      /* v_front_porch */
714                 .vmode =        FB_VMODE_NONINTERLACED,
715                 .sync =         FB_SYNC_VERT_HIGH_ACT,
716         },
717         /* 1600x1200p 60hz */
718         {
719                 .refresh =      60,
720                 .xres =         1600,
721                 .yres =         1200,
722                 .pixclock =     KHZ2PICOS(161000),
723                 .hsync_len =    168,    /* h_sync_width */
724                 .vsync_len =    4,      /* v_sync_width */
725                 .left_margin =  280,    /* h_back_porch */
726                 .upper_margin = 42,     /* v_back_porch */
727                 .right_margin = 112,    /* h_front_porch */
728                 .lower_margin = 3,      /* v_front_porch */
729                 .vmode =        FB_VMODE_NONINTERLACED,
730                 .sync = FB_SYNC_VERT_HIGH_ACT,
731         },
732         /* 1600x1200p 75hz */
733         {
734                 .refresh =      75,
735                 .xres =         1600,
736                 .yres =         1200,
737                 .pixclock =     KHZ2PICOS(204750),
738                 .hsync_len =    168,    /* h_sync_width */
739                 .vsync_len =    4,      /* v_sync_width */
740                 .left_margin =  288,    /* h_back_porch */
741                 .upper_margin = 52,     /* v_back_porch */
742                 .right_margin = 120,    /* h_front_porch */
743                 .lower_margin = 3,      /* v_front_porch */
744                 .vmode =        FB_VMODE_NONINTERLACED,
745                 .sync = FB_SYNC_VERT_HIGH_ACT,
746         },
747         /* 1680x1050p 59.94/60hz */
748         {
749                 .refresh =      60,
750                 .xres =         1680,
751                 .yres =         1050,
752                 .pixclock =     KHZ2PICOS(140000),
753                 .hsync_len =    168,    /* h_sync_width */
754                 .vsync_len =    10,     /* v_sync_width */
755                 .left_margin =  272,    /* h_back_porch */
756                 .upper_margin = 36,     /* v_back_porch */
757                 .right_margin = 104,    /* h_front_porch */
758                 .lower_margin = 3,      /* v_front_porch */
759                 .vmode =        FB_VMODE_NONINTERLACED,
760                 .sync = FB_SYNC_VERT_HIGH_ACT,
761         },
762 };
763
764 /* table of electrical settings, must be in acending order. */
765 struct tdms_config {
766         int pclk;
767         u32 pll0;
768         u32 pll1;
769         u32 pe_current; /* pre-emphasis */
770         u32 drive_current;
771 };
772
773 #ifndef CONFIG_ARCH_TEGRA_2x_SOC
774 const struct tdms_config tdms_config[] = {
775         { /* 480p modes */
776         .pclk = 27000000,
777         .pll0 = SOR_PLL_BG_V17_S(3) | SOR_PLL_ICHPMP(1) | SOR_PLL_RESISTORSEL |
778                 SOR_PLL_VCOCAP(0) | SOR_PLL_TX_REG_LOAD(0),
779         .pll1 = SOR_PLL_TMDS_TERM_ENABLE,
780         .pe_current = PE_CURRENT0(PE_CURRENT_0_0_mA) |
781                 PE_CURRENT1(PE_CURRENT_0_0_mA) |
782                 PE_CURRENT2(PE_CURRENT_0_0_mA) |
783                 PE_CURRENT3(PE_CURRENT_0_0_mA),
784         .drive_current = DRIVE_CURRENT_LANE0(DRIVE_CURRENT_5_250_mA) |
785                 DRIVE_CURRENT_LANE1(DRIVE_CURRENT_5_250_mA) |
786                 DRIVE_CURRENT_LANE2(DRIVE_CURRENT_5_250_mA) |
787                 DRIVE_CURRENT_LANE3(DRIVE_CURRENT_5_250_mA),
788         },
789         { /* 720p modes */
790         .pclk = 74250000,
791         .pll0 = SOR_PLL_BG_V17_S(3) | SOR_PLL_ICHPMP(1) | SOR_PLL_RESISTORSEL |
792                 SOR_PLL_VCOCAP(1) | SOR_PLL_TX_REG_LOAD(0),
793         .pll1 = SOR_PLL_TMDS_TERM_ENABLE | SOR_PLL_PE_EN,
794         .pe_current = PE_CURRENT0(PE_CURRENT_5_0_mA) |
795                 PE_CURRENT1(PE_CURRENT_5_0_mA) |
796                 PE_CURRENT2(PE_CURRENT_5_0_mA) |
797                 PE_CURRENT3(PE_CURRENT_5_0_mA),
798         .drive_current = DRIVE_CURRENT_LANE0(DRIVE_CURRENT_5_250_mA) |
799                 DRIVE_CURRENT_LANE1(DRIVE_CURRENT_5_250_mA) |
800                 DRIVE_CURRENT_LANE2(DRIVE_CURRENT_5_250_mA) |
801                 DRIVE_CURRENT_LANE3(DRIVE_CURRENT_5_250_mA),
802         },
803         { /* 1080p modes */
804         .pclk = INT_MAX,
805         .pll0 = SOR_PLL_BG_V17_S(3) | SOR_PLL_ICHPMP(1) | SOR_PLL_RESISTORSEL |
806                 SOR_PLL_VCOCAP(3) | SOR_PLL_TX_REG_LOAD(0),
807         .pll1 = SOR_PLL_TMDS_TERM_ENABLE | SOR_PLL_PE_EN,
808         .pe_current = PE_CURRENT0(PE_CURRENT_5_0_mA) |
809                 PE_CURRENT1(PE_CURRENT_5_0_mA) |
810                 PE_CURRENT2(PE_CURRENT_5_0_mA) |
811                 PE_CURRENT3(PE_CURRENT_5_0_mA),
812         .drive_current = DRIVE_CURRENT_LANE0(DRIVE_CURRENT_5_250_mA) |
813                 DRIVE_CURRENT_LANE1(DRIVE_CURRENT_5_250_mA) |
814                 DRIVE_CURRENT_LANE2(DRIVE_CURRENT_5_250_mA) |
815                 DRIVE_CURRENT_LANE3(DRIVE_CURRENT_5_250_mA),
816         },
817 };
818 #else /*  CONFIG_ARCH_TEGRA_2x_SOC */
819 const struct tdms_config tdms_config[] = {
820         { /* 480p modes */
821         .pclk = 27000000,
822         .pll0 = SOR_PLL_BG_V17_S(3) | SOR_PLL_ICHPMP(1) | SOR_PLL_RESISTORSEL |
823                 SOR_PLL_VCOCAP(0) | SOR_PLL_TX_REG_LOAD(3),
824         .pll1 = SOR_PLL_TMDS_TERM_ENABLE,
825         .pe_current = PE_CURRENT0(PE_CURRENT_0_0_mA) |
826                 PE_CURRENT1(PE_CURRENT_0_0_mA) |
827                 PE_CURRENT2(PE_CURRENT_0_0_mA) |
828                 PE_CURRENT3(PE_CURRENT_0_0_mA),
829         .drive_current = DRIVE_CURRENT_LANE0(DRIVE_CURRENT_7_125_mA) |
830                 DRIVE_CURRENT_LANE1(DRIVE_CURRENT_7_125_mA) |
831                 DRIVE_CURRENT_LANE2(DRIVE_CURRENT_7_125_mA) |
832                 DRIVE_CURRENT_LANE3(DRIVE_CURRENT_7_125_mA),
833         },
834         { /* 720p modes */
835         .pclk = 74250000,
836         .pll0 = SOR_PLL_BG_V17_S(3) | SOR_PLL_ICHPMP(1) | SOR_PLL_RESISTORSEL |
837                 SOR_PLL_VCOCAP(1) | SOR_PLL_TX_REG_LOAD(3),
838         .pll1 = SOR_PLL_TMDS_TERM_ENABLE | SOR_PLL_PE_EN,
839         .pe_current = PE_CURRENT0(PE_CURRENT_6_0_mA) |
840                 PE_CURRENT1(PE_CURRENT_6_0_mA) |
841                 PE_CURRENT2(PE_CURRENT_6_0_mA) |
842                 PE_CURRENT3(PE_CURRENT_6_0_mA),
843         .drive_current = DRIVE_CURRENT_LANE0(DRIVE_CURRENT_7_125_mA) |
844                 DRIVE_CURRENT_LANE1(DRIVE_CURRENT_7_125_mA) |
845                 DRIVE_CURRENT_LANE2(DRIVE_CURRENT_7_125_mA) |
846                 DRIVE_CURRENT_LANE3(DRIVE_CURRENT_7_125_mA),
847         },
848         { /* 1080p modes */
849         .pclk = INT_MAX,
850         .pll0 = SOR_PLL_BG_V17_S(3) | SOR_PLL_ICHPMP(1) | SOR_PLL_RESISTORSEL |
851                 SOR_PLL_VCOCAP(1) | SOR_PLL_TX_REG_LOAD(3),
852         .pll1 = SOR_PLL_TMDS_TERM_ENABLE | SOR_PLL_PE_EN,
853         .pe_current = PE_CURRENT0(PE_CURRENT_6_0_mA) |
854                 PE_CURRENT1(PE_CURRENT_6_0_mA) |
855                 PE_CURRENT2(PE_CURRENT_6_0_mA) |
856                 PE_CURRENT3(PE_CURRENT_6_0_mA),
857         .drive_current = DRIVE_CURRENT_LANE0(DRIVE_CURRENT_7_125_mA) |
858                 DRIVE_CURRENT_LANE1(DRIVE_CURRENT_7_125_mA) |
859                 DRIVE_CURRENT_LANE2(DRIVE_CURRENT_7_125_mA) |
860                 DRIVE_CURRENT_LANE3(DRIVE_CURRENT_7_125_mA),
861         },
862 };
863 #endif
864
865 struct tegra_hdmi_audio_config {
866         unsigned pix_clock;
867         unsigned n;
868         unsigned cts;
869         unsigned aval;
870 };
871
872
873 const struct tegra_hdmi_audio_config tegra_hdmi_audio_32k[] = {
874         {25200000,      4096,   25200,  24000},
875         {27000000,      4096,   27000,  24000},
876         {74250000,      4096,   74250,  24000},
877         {148500000,     4096,   148500, 24000},
878         {0,             0,      0},
879 };
880
881 const struct tegra_hdmi_audio_config tegra_hdmi_audio_44_1k[] = {
882         {25200000,      5880,   26250,  25000},
883         {27000000,      5880,   28125,  25000},
884         {74250000,      4704,   61875,  20000},
885         {148500000,     4704,   123750, 20000},
886         {0,             0,      0},
887 };
888
889 const struct tegra_hdmi_audio_config tegra_hdmi_audio_48k[] = {
890         {25200000,      6144,   25200,  24000},
891         {27000000,      6144,   27000,  24000},
892         {74250000,      6144,   74250,  24000},
893         {148500000,     6144,   148500, 24000},
894         {0,             0,      0},
895 };
896
897 const struct tegra_hdmi_audio_config tegra_hdmi_audio_88_2k[] = {
898         {25200000,      11760,  26250,  25000},
899         {27000000,      11760,  28125,  25000},
900         {74250000,      9408,   61875,  20000},
901         {148500000,     9408,   123750, 20000},
902         {0,             0,      0},
903 };
904
905 const struct tegra_hdmi_audio_config tegra_hdmi_audio_96k[] = {
906         {25200000,      12288,  25200,  24000},
907         {27000000,      12288,  27000,  24000},
908         {74250000,      12288,  74250,  24000},
909         {148500000,     12288,  148500, 24000},
910         {0,             0,      0},
911 };
912
913 const struct tegra_hdmi_audio_config tegra_hdmi_audio_176_4k[] = {
914         {25200000,      23520,  26250,  25000},
915         {27000000,      23520,  28125,  25000},
916         {74250000,      18816,  61875,  20000},
917         {148500000,     18816,  123750, 20000},
918         {0,             0,      0},
919 };
920
921 const struct tegra_hdmi_audio_config tegra_hdmi_audio_192k[] = {
922         {25200000,      24576,  25200,  24000},
923         {27000000,      24576,  27000,  24000},
924         {74250000,      24576,  74250,  24000},
925         {148500000,     24576,  148500, 24000},
926         {0,             0,      0},
927 };
928
929 static const struct tegra_hdmi_audio_config
930 *tegra_hdmi_get_audio_config(unsigned audio_freq, unsigned pix_clock)
931 {
932         const struct tegra_hdmi_audio_config *table;
933
934         switch (audio_freq) {
935         case AUDIO_FREQ_32K:
936                 table = tegra_hdmi_audio_32k;
937                 break;
938         case AUDIO_FREQ_44_1K:
939                 table = tegra_hdmi_audio_44_1k;
940                 break;
941         case AUDIO_FREQ_48K:
942                 table = tegra_hdmi_audio_48k;
943                 break;
944         case AUDIO_FREQ_88_2K:
945                 table = tegra_hdmi_audio_88_2k;
946                 break;
947         case AUDIO_FREQ_96K:
948                 table = tegra_hdmi_audio_96k;
949                 break;
950         case AUDIO_FREQ_176_4K:
951                 table = tegra_hdmi_audio_176_4k;
952                 break;
953         case AUDIO_FREQ_192K:
954                 table = tegra_hdmi_audio_192k;
955                 break;
956         default:
957                 return NULL;
958         }
959
960         while (table->pix_clock) {
961                 if (table->pix_clock == pix_clock)
962                         return table;
963                 table++;
964         }
965
966         return NULL;
967 }
968
969
970 unsigned long tegra_hdmi_readl(struct tegra_dc_hdmi_data *hdmi,
971                                              unsigned long reg)
972 {
973         unsigned long ret;
974         ret = readl(hdmi->base + reg * 4);
975         trace_printk("readl %p=%#08lx\n", hdmi->base + reg * 4, ret);
976         return ret;
977 }
978
979 void tegra_hdmi_writel(struct tegra_dc_hdmi_data *hdmi,
980                                      unsigned long val, unsigned long reg)
981 {
982         trace_printk("writel %p=%#08lx\n", hdmi->base + reg * 4, val);
983         writel(val, hdmi->base + reg * 4);
984 }
985
986 static inline void tegra_hdmi_clrsetbits(struct tegra_dc_hdmi_data *hdmi,
987                                          unsigned long reg, unsigned long clr,
988                                          unsigned long set)
989 {
990         unsigned long val = tegra_hdmi_readl(hdmi, reg);
991         val &= ~clr;
992         val |= set;
993         tegra_hdmi_writel(hdmi, val, reg);
994 }
995
996 #ifdef CONFIG_DEBUG_FS
997 static int dbg_hdmi_show(struct seq_file *s, void *unused)
998 {
999         struct tegra_dc_hdmi_data *hdmi = s->private;
1000
1001 #define DUMP_REG(a) do {                                                \
1002                 seq_printf(s, "%-32s\t%03x\t%08lx\n",                   \
1003                        #a, a, tegra_hdmi_readl(hdmi, a));               \
1004         } while (0)
1005
1006         tegra_dc_io_start(hdmi->dc);
1007         clk_enable(hdmi->clk);
1008
1009         DUMP_REG(HDMI_CTXSW);
1010         DUMP_REG(HDMI_NV_PDISP_SOR_STATE0);
1011         DUMP_REG(HDMI_NV_PDISP_SOR_STATE1);
1012         DUMP_REG(HDMI_NV_PDISP_SOR_STATE2);
1013         DUMP_REG(HDMI_NV_PDISP_RG_HDCP_AN_MSB);
1014         DUMP_REG(HDMI_NV_PDISP_RG_HDCP_AN_LSB);
1015         DUMP_REG(HDMI_NV_PDISP_RG_HDCP_CN_MSB);
1016         DUMP_REG(HDMI_NV_PDISP_RG_HDCP_CN_LSB);
1017         DUMP_REG(HDMI_NV_PDISP_RG_HDCP_AKSV_MSB);
1018         DUMP_REG(HDMI_NV_PDISP_RG_HDCP_AKSV_LSB);
1019         DUMP_REG(HDMI_NV_PDISP_RG_HDCP_BKSV_MSB);
1020         DUMP_REG(HDMI_NV_PDISP_RG_HDCP_BKSV_LSB);
1021         DUMP_REG(HDMI_NV_PDISP_RG_HDCP_CKSV_MSB);
1022         DUMP_REG(HDMI_NV_PDISP_RG_HDCP_CKSV_LSB);
1023         DUMP_REG(HDMI_NV_PDISP_RG_HDCP_DKSV_MSB);
1024         DUMP_REG(HDMI_NV_PDISP_RG_HDCP_DKSV_LSB);
1025         DUMP_REG(HDMI_NV_PDISP_RG_HDCP_CTRL);
1026         DUMP_REG(HDMI_NV_PDISP_RG_HDCP_CMODE);
1027         DUMP_REG(HDMI_NV_PDISP_RG_HDCP_MPRIME_MSB);
1028         DUMP_REG(HDMI_NV_PDISP_RG_HDCP_MPRIME_LSB);
1029         DUMP_REG(HDMI_NV_PDISP_RG_HDCP_SPRIME_MSB);
1030         DUMP_REG(HDMI_NV_PDISP_RG_HDCP_SPRIME_LSB2);
1031         DUMP_REG(HDMI_NV_PDISP_RG_HDCP_SPRIME_LSB1);
1032         DUMP_REG(HDMI_NV_PDISP_RG_HDCP_RI);
1033         DUMP_REG(HDMI_NV_PDISP_RG_HDCP_CS_MSB);
1034         DUMP_REG(HDMI_NV_PDISP_RG_HDCP_CS_LSB);
1035         DUMP_REG(HDMI_NV_PDISP_HDMI_AUDIO_EMU0);
1036         DUMP_REG(HDMI_NV_PDISP_HDMI_AUDIO_EMU_RDATA0);
1037         DUMP_REG(HDMI_NV_PDISP_HDMI_AUDIO_EMU1);
1038         DUMP_REG(HDMI_NV_PDISP_HDMI_AUDIO_EMU2);
1039         DUMP_REG(HDMI_NV_PDISP_HDMI_AUDIO_INFOFRAME_CTRL);
1040         DUMP_REG(HDMI_NV_PDISP_HDMI_AUDIO_INFOFRAME_STATUS);
1041         DUMP_REG(HDMI_NV_PDISP_HDMI_AUDIO_INFOFRAME_HEADER);
1042         DUMP_REG(HDMI_NV_PDISP_HDMI_AUDIO_INFOFRAME_SUBPACK0_LOW);
1043         DUMP_REG(HDMI_NV_PDISP_HDMI_AUDIO_INFOFRAME_SUBPACK0_HIGH);
1044         DUMP_REG(HDMI_NV_PDISP_HDMI_AVI_INFOFRAME_CTRL);
1045         DUMP_REG(HDMI_NV_PDISP_HDMI_AVI_INFOFRAME_STATUS);
1046         DUMP_REG(HDMI_NV_PDISP_HDMI_AVI_INFOFRAME_HEADER);
1047         DUMP_REG(HDMI_NV_PDISP_HDMI_AVI_INFOFRAME_SUBPACK0_LOW);
1048         DUMP_REG(HDMI_NV_PDISP_HDMI_AVI_INFOFRAME_SUBPACK0_HIGH);
1049         DUMP_REG(HDMI_NV_PDISP_HDMI_AVI_INFOFRAME_SUBPACK1_LOW);
1050         DUMP_REG(HDMI_NV_PDISP_HDMI_AVI_INFOFRAME_SUBPACK1_HIGH);
1051         DUMP_REG(HDMI_NV_PDISP_HDMI_GENERIC_CTRL);
1052         DUMP_REG(HDMI_NV_PDISP_HDMI_GENERIC_STATUS);
1053         DUMP_REG(HDMI_NV_PDISP_HDMI_GENERIC_HEADER);
1054         DUMP_REG(HDMI_NV_PDISP_HDMI_GENERIC_SUBPACK0_LOW);
1055         DUMP_REG(HDMI_NV_PDISP_HDMI_GENERIC_SUBPACK0_HIGH);
1056         DUMP_REG(HDMI_NV_PDISP_HDMI_GENERIC_SUBPACK1_LOW);
1057         DUMP_REG(HDMI_NV_PDISP_HDMI_GENERIC_SUBPACK1_HIGH);
1058         DUMP_REG(HDMI_NV_PDISP_HDMI_GENERIC_SUBPACK2_LOW);
1059         DUMP_REG(HDMI_NV_PDISP_HDMI_GENERIC_SUBPACK2_HIGH);
1060         DUMP_REG(HDMI_NV_PDISP_HDMI_GENERIC_SUBPACK3_LOW);
1061         DUMP_REG(HDMI_NV_PDISP_HDMI_GENERIC_SUBPACK3_HIGH);
1062         DUMP_REG(HDMI_NV_PDISP_HDMI_ACR_CTRL);
1063         DUMP_REG(HDMI_NV_PDISP_HDMI_ACR_0320_SUBPACK_LOW);
1064         DUMP_REG(HDMI_NV_PDISP_HDMI_ACR_0320_SUBPACK_HIGH);
1065         DUMP_REG(HDMI_NV_PDISP_HDMI_ACR_0441_SUBPACK_LOW);
1066         DUMP_REG(HDMI_NV_PDISP_HDMI_ACR_0441_SUBPACK_HIGH);
1067         DUMP_REG(HDMI_NV_PDISP_HDMI_ACR_0882_SUBPACK_LOW);
1068         DUMP_REG(HDMI_NV_PDISP_HDMI_ACR_0882_SUBPACK_HIGH);
1069         DUMP_REG(HDMI_NV_PDISP_HDMI_ACR_1764_SUBPACK_LOW);
1070         DUMP_REG(HDMI_NV_PDISP_HDMI_ACR_1764_SUBPACK_HIGH);
1071         DUMP_REG(HDMI_NV_PDISP_HDMI_ACR_0480_SUBPACK_LOW);
1072         DUMP_REG(HDMI_NV_PDISP_HDMI_ACR_0480_SUBPACK_HIGH);
1073         DUMP_REG(HDMI_NV_PDISP_HDMI_ACR_0960_SUBPACK_LOW);
1074         DUMP_REG(HDMI_NV_PDISP_HDMI_ACR_0960_SUBPACK_HIGH);
1075         DUMP_REG(HDMI_NV_PDISP_HDMI_ACR_1920_SUBPACK_LOW);
1076         DUMP_REG(HDMI_NV_PDISP_HDMI_ACR_1920_SUBPACK_HIGH);
1077         DUMP_REG(HDMI_NV_PDISP_HDMI_CTRL);
1078         DUMP_REG(HDMI_NV_PDISP_HDMI_VSYNC_KEEPOUT);
1079         DUMP_REG(HDMI_NV_PDISP_HDMI_VSYNC_WINDOW);
1080         DUMP_REG(HDMI_NV_PDISP_HDMI_GCP_CTRL);
1081         DUMP_REG(HDMI_NV_PDISP_HDMI_GCP_STATUS);
1082         DUMP_REG(HDMI_NV_PDISP_HDMI_GCP_SUBPACK);
1083         DUMP_REG(HDMI_NV_PDISP_HDMI_CHANNEL_STATUS1);
1084         DUMP_REG(HDMI_NV_PDISP_HDMI_CHANNEL_STATUS2);
1085         DUMP_REG(HDMI_NV_PDISP_HDMI_EMU0);
1086         DUMP_REG(HDMI_NV_PDISP_HDMI_EMU1);
1087         DUMP_REG(HDMI_NV_PDISP_HDMI_EMU1_RDATA);
1088         DUMP_REG(HDMI_NV_PDISP_HDMI_SPARE);
1089         DUMP_REG(HDMI_NV_PDISP_HDMI_SPDIF_CHN_STATUS1);
1090         DUMP_REG(HDMI_NV_PDISP_HDMI_SPDIF_CHN_STATUS2);
1091         DUMP_REG(HDMI_NV_PDISP_HDCPRIF_ROM_CTRL);
1092         DUMP_REG(HDMI_NV_PDISP_SOR_CAP);
1093         DUMP_REG(HDMI_NV_PDISP_SOR_PWR);
1094         DUMP_REG(HDMI_NV_PDISP_SOR_TEST);
1095         DUMP_REG(HDMI_NV_PDISP_SOR_PLL0);
1096         DUMP_REG(HDMI_NV_PDISP_SOR_PLL1);
1097         DUMP_REG(HDMI_NV_PDISP_SOR_PLL2);
1098         DUMP_REG(HDMI_NV_PDISP_SOR_CSTM);
1099         DUMP_REG(HDMI_NV_PDISP_SOR_LVDS);
1100         DUMP_REG(HDMI_NV_PDISP_SOR_CRCA);
1101         DUMP_REG(HDMI_NV_PDISP_SOR_CRCB);
1102         DUMP_REG(HDMI_NV_PDISP_SOR_BLANK);
1103         DUMP_REG(HDMI_NV_PDISP_SOR_SEQ_CTL);
1104         DUMP_REG(HDMI_NV_PDISP_SOR_SEQ_INST0);
1105         DUMP_REG(HDMI_NV_PDISP_SOR_SEQ_INST1);
1106         DUMP_REG(HDMI_NV_PDISP_SOR_SEQ_INST2);
1107         DUMP_REG(HDMI_NV_PDISP_SOR_SEQ_INST3);
1108         DUMP_REG(HDMI_NV_PDISP_SOR_SEQ_INST4);
1109         DUMP_REG(HDMI_NV_PDISP_SOR_SEQ_INST5);
1110         DUMP_REG(HDMI_NV_PDISP_SOR_SEQ_INST6);
1111         DUMP_REG(HDMI_NV_PDISP_SOR_SEQ_INST7);
1112         DUMP_REG(HDMI_NV_PDISP_SOR_SEQ_INST8);
1113         DUMP_REG(HDMI_NV_PDISP_SOR_SEQ_INST9);
1114         DUMP_REG(HDMI_NV_PDISP_SOR_SEQ_INSTA);
1115         DUMP_REG(HDMI_NV_PDISP_SOR_SEQ_INSTB);
1116         DUMP_REG(HDMI_NV_PDISP_SOR_SEQ_INSTC);
1117         DUMP_REG(HDMI_NV_PDISP_SOR_SEQ_INSTD);
1118         DUMP_REG(HDMI_NV_PDISP_SOR_SEQ_INSTE);
1119         DUMP_REG(HDMI_NV_PDISP_SOR_SEQ_INSTF);
1120         DUMP_REG(HDMI_NV_PDISP_SOR_VCRCA0);
1121         DUMP_REG(HDMI_NV_PDISP_SOR_VCRCA1);
1122         DUMP_REG(HDMI_NV_PDISP_SOR_CCRCA0);
1123         DUMP_REG(HDMI_NV_PDISP_SOR_CCRCA1);
1124         DUMP_REG(HDMI_NV_PDISP_SOR_EDATAA0);
1125         DUMP_REG(HDMI_NV_PDISP_SOR_EDATAA1);
1126         DUMP_REG(HDMI_NV_PDISP_SOR_COUNTA0);
1127         DUMP_REG(HDMI_NV_PDISP_SOR_COUNTA1);
1128         DUMP_REG(HDMI_NV_PDISP_SOR_DEBUGA0);
1129         DUMP_REG(HDMI_NV_PDISP_SOR_DEBUGA1);
1130         DUMP_REG(HDMI_NV_PDISP_SOR_TRIG);
1131         DUMP_REG(HDMI_NV_PDISP_SOR_MSCHECK);
1132         DUMP_REG(HDMI_NV_PDISP_SOR_LANE_DRIVE_CURRENT);
1133         DUMP_REG(HDMI_NV_PDISP_AUDIO_DEBUG0);
1134         DUMP_REG(HDMI_NV_PDISP_AUDIO_DEBUG1);
1135         DUMP_REG(HDMI_NV_PDISP_AUDIO_DEBUG2);
1136         DUMP_REG(HDMI_NV_PDISP_AUDIO_FS(0));
1137         DUMP_REG(HDMI_NV_PDISP_AUDIO_FS(1));
1138         DUMP_REG(HDMI_NV_PDISP_AUDIO_FS(2));
1139         DUMP_REG(HDMI_NV_PDISP_AUDIO_FS(3));
1140         DUMP_REG(HDMI_NV_PDISP_AUDIO_FS(4));
1141         DUMP_REG(HDMI_NV_PDISP_AUDIO_FS(5));
1142         DUMP_REG(HDMI_NV_PDISP_AUDIO_FS(6));
1143         DUMP_REG(HDMI_NV_PDISP_AUDIO_PULSE_WIDTH);
1144         DUMP_REG(HDMI_NV_PDISP_AUDIO_THRESHOLD);
1145         DUMP_REG(HDMI_NV_PDISP_AUDIO_CNTRL0);
1146         DUMP_REG(HDMI_NV_PDISP_AUDIO_N);
1147         DUMP_REG(HDMI_NV_PDISP_HDCPRIF_ROM_TIMING);
1148         DUMP_REG(HDMI_NV_PDISP_SOR_REFCLK);
1149         DUMP_REG(HDMI_NV_PDISP_CRC_CONTROL);
1150         DUMP_REG(HDMI_NV_PDISP_INPUT_CONTROL);
1151         DUMP_REG(HDMI_NV_PDISP_SCRATCH);
1152         DUMP_REG(HDMI_NV_PDISP_PE_CURRENT);
1153         DUMP_REG(HDMI_NV_PDISP_KEY_CTRL);
1154         DUMP_REG(HDMI_NV_PDISP_KEY_DEBUG0);
1155         DUMP_REG(HDMI_NV_PDISP_KEY_DEBUG1);
1156         DUMP_REG(HDMI_NV_PDISP_KEY_DEBUG2);
1157         DUMP_REG(HDMI_NV_PDISP_KEY_HDCP_KEY_0);
1158         DUMP_REG(HDMI_NV_PDISP_KEY_HDCP_KEY_1);
1159         DUMP_REG(HDMI_NV_PDISP_KEY_HDCP_KEY_2);
1160         DUMP_REG(HDMI_NV_PDISP_KEY_HDCP_KEY_3);
1161         DUMP_REG(HDMI_NV_PDISP_KEY_HDCP_KEY_TRIG);
1162         DUMP_REG(HDMI_NV_PDISP_KEY_SKEY_INDEX);
1163 #undef DUMP_REG
1164
1165         clk_disable(hdmi->clk);
1166         tegra_dc_io_end(hdmi->dc);
1167
1168         return 0;
1169 }
1170
1171 static int dbg_hdmi_open(struct inode *inode, struct file *file)
1172 {
1173         return single_open(file, dbg_hdmi_show, inode->i_private);
1174 }
1175
1176 static const struct file_operations dbg_fops = {
1177         .open           = dbg_hdmi_open,
1178         .read           = seq_read,
1179         .llseek         = seq_lseek,
1180         .release        = single_release,
1181 };
1182
1183 static struct dentry *hdmidir;
1184
1185 static void tegra_dc_hdmi_debug_create(struct tegra_dc_hdmi_data *hdmi)
1186 {
1187         struct dentry *retval;
1188
1189         hdmidir = debugfs_create_dir("tegra_hdmi", NULL);
1190         if (!hdmidir)
1191                 return;
1192         retval = debugfs_create_file("regs", S_IRUGO, hdmidir, hdmi,
1193                 &dbg_fops);
1194         if (!retval)
1195                 goto free_out;
1196         return;
1197 free_out:
1198         debugfs_remove_recursive(hdmidir);
1199         hdmidir = NULL;
1200         return;
1201 }
1202 #else
1203 static inline void tegra_dc_hdmi_debug_create(struct tegra_dc_hdmi_data *hdmi)
1204 { }
1205 #endif
1206
1207 #define PIXCLOCK_TOLERANCE      200
1208
1209 static int tegra_dc_calc_clock_per_frame(const struct fb_videomode *mode)
1210 {
1211         return (mode->left_margin + mode->xres +
1212                 mode->right_margin + mode->hsync_len) *
1213                (mode->upper_margin + mode->yres +
1214                 mode->lower_margin + mode->vsync_len);
1215 }
1216
1217 static bool tegra_dc_hdmi_valid_pixclock(const struct tegra_dc *dc,
1218                                         const struct fb_videomode *mode)
1219 {
1220         unsigned max_pixclock = tegra_dc_get_out_max_pixclock(dc);
1221         if (max_pixclock) {
1222                 /* this might look counter-intuitive,
1223                  * but pixclock's unit is picos(not Khz)
1224                  */
1225                 return mode->pixclock >= max_pixclock;
1226         } else {
1227                 return true;
1228         }
1229 }
1230
1231 static bool tegra_dc_cvt_mode_equal(const struct fb_videomode *mode1,
1232                                 const struct fb_videomode *mode2)
1233 {
1234         return (mode1->xres == mode2->xres &&
1235                 mode1->yres == mode2->yres &&
1236                 mode1->refresh == mode2->refresh &&
1237                 mode1->vmode == mode2->vmode);
1238 }
1239
1240 static bool tegra_dc_reload_mode(struct fb_videomode *mode)
1241 {
1242         int i = 0;
1243         for (i = 0; i < ARRAY_SIZE(tegra_dc_hdmi_supported_cvt_modes); i++) {
1244                 const struct fb_videomode *cvt_mode
1245                                 = &tegra_dc_hdmi_supported_cvt_modes[i];
1246                 if (tegra_dc_cvt_mode_equal(cvt_mode, mode)) {
1247                         memcpy(mode, cvt_mode, sizeof(*mode));
1248                         return true;
1249                 }
1250         }
1251         return false;
1252 }
1253
1254 static bool tegra_dc_hdmi_valid_asp_ratio(const struct tegra_dc *dc,
1255                                         struct fb_videomode *mode)
1256 {
1257         int count = 0;
1258         int m_aspratio = 0;
1259         int s_aspratio = 0;
1260
1261         /* To check the aspect upto two decimal digits, calculate in % */
1262         m_aspratio = (mode->xres*100 / mode->yres);
1263
1264         if ((m_aspratio < TEGRA_DC_HDMI_MIN_ASPECT_RATIO_PERCENT) ||
1265                         (m_aspratio > TEGRA_DC_HDMI_MAX_ASPECT_RATIO_PERCENT))
1266                                 return false;
1267
1268         /* Check from the table of  supported aspect ratios, allow
1269             difference of 1% for second decimal digit calibration */
1270         for (count = 0; count < ARRAY_SIZE(tegra_dc_hdmi_aspect_ratios);
1271                  count++) {
1272                         s_aspratio =  tegra_dc_hdmi_aspect_ratios[count];
1273                         if ((m_aspratio == s_aspratio) ||
1274                                 (abs(m_aspratio - s_aspratio) == 1))
1275                                 return true;
1276         }
1277
1278         return false;
1279 }
1280
1281
1282 static bool tegra_dc_hdmi_mode_filter(const struct tegra_dc *dc,
1283                                         struct fb_videomode *mode)
1284 {
1285         if (mode->vmode & FB_VMODE_INTERLACED)
1286                 return false;
1287
1288         /* Ignore modes with a 0 pixel clock */
1289         if (!mode->pixclock)
1290                 return false;
1291
1292 #ifdef CONFIG_TEGRA_HDMI_74MHZ_LIMIT
1293                 if (PICOS2KHZ(mode->pixclock) > 74250)
1294                         return false;
1295 #endif
1296
1297         /* Check if the mode's pixel clock is more than the max rate*/
1298         if (!tegra_dc_hdmi_valid_pixclock(dc, mode))
1299                 return false;
1300
1301         /* Check if the mode's aspect ratio is supported */
1302         if (!tegra_dc_hdmi_valid_asp_ratio(dc, mode))
1303                 return false;
1304
1305         /* Check some of DC's constraints */
1306         if (mode->hsync_len > 1 && mode->vsync_len > 1 &&
1307                 mode->lower_margin + mode->vsync_len + mode->upper_margin > 1 &&
1308                 mode->xres >= 16 && mode->yres >= 16) {
1309
1310                 if (mode->lower_margin == 1) {
1311                         /* This might be the case for HDMI<->DVI
1312                          * where std VESA representation will not
1313                          * pass constraint V_FRONT_PORCH >=
1314                          * V_REF_TO_SYNC + 1.So reload mode in
1315                          * CVT timing standards.
1316                          */
1317                         if (!tegra_dc_reload_mode(mode))
1318                                 return false;
1319                 }
1320                 mode->flag = FB_MODE_IS_DETAILED;
1321                 mode->refresh = (PICOS2KHZ(mode->pixclock) * 1000) /
1322                                 tegra_dc_calc_clock_per_frame(mode);
1323                 return true;
1324         }
1325
1326         return false;
1327 }
1328
1329 static bool tegra_dc_hdmi_hpd(struct tegra_dc *dc)
1330 {
1331         return tegra_dc_hpd(dc);
1332 }
1333
1334
1335 void tegra_dc_hdmi_detect_config(struct tegra_dc *dc,
1336                                                 struct fb_monspecs *specs)
1337 {
1338         struct tegra_dc_hdmi_data *hdmi = tegra_dc_get_outdata(dc);
1339
1340         /* monitors like to lie about these but they are still useful for
1341          * detecting aspect ratios
1342          */
1343         dc->out->h_size = specs->max_x * 1000;
1344         dc->out->v_size = specs->max_y * 1000;
1345
1346         hdmi->dvi = !(specs->misc & FB_MISC_HDMI);
1347
1348         tegra_fb_update_monspecs(dc->fb, specs, tegra_dc_hdmi_mode_filter);
1349 #ifdef CONFIG_SWITCH
1350         hdmi->hpd_switch.state = 0;
1351         switch_set_state(&hdmi->hpd_switch, 1);
1352 #endif
1353         dev_info(&dc->ndev->dev, "display detected\n");
1354
1355         dc->connected = true;
1356         tegra_dc_ext_process_hotplug(dc->ndev->id);
1357 }
1358
1359 /* This function is used to enable DC1 and HDMI for the purpose of testing. */
1360 bool tegra_dc_hdmi_detect_test(struct tegra_dc *dc, unsigned char *edid_ptr)
1361 {
1362         int err;
1363         struct fb_monspecs specs;
1364         struct tegra_dc_hdmi_data *hdmi = tegra_dc_get_outdata(dc);
1365
1366         if (!hdmi || !edid_ptr) {
1367                 dev_err(&dc->ndev->dev, "HDMI test failed to get arguments.\n");
1368                 return false;
1369         }
1370
1371         err = tegra_edid_get_monspecs_test(hdmi->edid, &specs, edid_ptr);
1372         if (err < 0) {
1373                 /* Check if there's a hard-wired mode, if so, enable it */
1374                 if (dc->out->n_modes)
1375                         tegra_dc_enable(dc);
1376                 else {
1377                         dev_err(&dc->ndev->dev, "error reading edid\n");
1378                         goto fail;
1379                 }
1380 #ifdef CONFIG_SWITCH
1381                 hdmi->hpd_switch.state = 0;
1382                 switch_set_state(&hdmi->hpd_switch, 1);
1383 #endif
1384                 dev_info(&dc->ndev->dev, "display detected\n");
1385
1386                 dc->connected = true;
1387                 tegra_dc_ext_process_hotplug(dc->ndev->id);
1388         } else {
1389                 err = tegra_edid_get_eld(hdmi->edid, &hdmi->eld);
1390                 if (err < 0) {
1391                         dev_err(&dc->ndev->dev, "error populating eld\n");
1392                         goto fail;
1393                 }
1394                 hdmi->eld_retrieved = true;
1395
1396                 tegra_dc_hdmi_detect_config(dc, &specs);
1397         }
1398
1399         return true;
1400
1401 fail:
1402         hdmi->eld_retrieved = false;
1403 #ifdef CONFIG_SWITCH
1404         switch_set_state(&hdmi->hpd_switch, 0);
1405 #endif
1406         tegra_nvhdcp_set_plug(hdmi->nvhdcp, 0);
1407         return false;
1408 }
1409 EXPORT_SYMBOL(tegra_dc_hdmi_detect_test);
1410
1411 static bool tegra_dc_hdmi_detect(struct tegra_dc *dc)
1412 {
1413         struct tegra_dc_hdmi_data *hdmi = tegra_dc_get_outdata(dc);
1414         struct fb_monspecs specs;
1415         int err;
1416
1417         if (!tegra_dc_hdmi_hpd(dc))
1418                 goto fail;
1419
1420         err = tegra_edid_get_monspecs(hdmi->edid, &specs);
1421         if (err < 0) {
1422                 if (dc->out->n_modes)
1423                         tegra_dc_enable(dc);
1424                 else {
1425                         dev_err(&dc->ndev->dev, "error reading edid\n");
1426                         goto fail;
1427                 }
1428 #ifdef CONFIG_SWITCH
1429                 hdmi->hpd_switch.state = 0;
1430                 switch_set_state(&hdmi->hpd_switch, 1);
1431 #endif
1432                 dev_info(&dc->ndev->dev, "display detected\n");
1433
1434                 dc->connected = true;
1435                 tegra_dc_ext_process_hotplug(dc->ndev->id);
1436         } else {
1437                 err = tegra_edid_get_eld(hdmi->edid, &hdmi->eld);
1438                 if (err < 0) {
1439                         dev_err(&dc->ndev->dev, "error populating eld\n");
1440                         goto fail;
1441                 }
1442                 hdmi->eld_retrieved = true;
1443
1444                 tegra_dc_hdmi_detect_config(dc, &specs);
1445         }
1446
1447         return true;
1448
1449 fail:
1450         hdmi->eld_retrieved = false;
1451 #ifdef CONFIG_SWITCH
1452         switch_set_state(&hdmi->hpd_switch, 0);
1453 #endif
1454         tegra_nvhdcp_set_plug(hdmi->nvhdcp, 0);
1455         return false;
1456 }
1457
1458
1459 static void tegra_dc_hdmi_detect_worker(struct work_struct *work)
1460 {
1461         struct tegra_dc_hdmi_data *hdmi =
1462                 container_of(to_delayed_work(work), struct tegra_dc_hdmi_data, work);
1463         struct tegra_dc *dc = hdmi->dc;
1464
1465         if (!tegra_dc_hdmi_detect(dc)) {
1466                 tegra_fb_update_monspecs(dc->fb, NULL, NULL);
1467
1468                 dc->connected = false;
1469                 tegra_dc_ext_process_hotplug(dc->ndev->id);
1470         }
1471 }
1472
1473 static irqreturn_t tegra_dc_hdmi_irq(int irq, void *ptr)
1474 {
1475         struct tegra_dc *dc = ptr;
1476         struct tegra_dc_hdmi_data *hdmi = tegra_dc_get_outdata(dc);
1477         unsigned long flags;
1478
1479         spin_lock_irqsave(&hdmi->suspend_lock, flags);
1480         if (!hdmi->suspended) {
1481                 __cancel_delayed_work(&hdmi->work);
1482                 if (tegra_dc_hdmi_hpd(dc))
1483                         queue_delayed_work(system_nrt_wq, &hdmi->work,
1484                                            msecs_to_jiffies(100));
1485                 else
1486                         queue_delayed_work(system_nrt_wq, &hdmi->work,
1487                                            msecs_to_jiffies(30));
1488         }
1489         spin_unlock_irqrestore(&hdmi->suspend_lock, flags);
1490
1491         return IRQ_HANDLED;
1492 }
1493
1494 static void tegra_dc_hdmi_suspend(struct tegra_dc *dc)
1495 {
1496         struct tegra_dc_hdmi_data *hdmi = tegra_dc_get_outdata(dc);
1497         unsigned long flags;
1498
1499         tegra_nvhdcp_suspend(hdmi->nvhdcp);
1500         spin_lock_irqsave(&hdmi->suspend_lock, flags);
1501         hdmi->suspended = true;
1502         spin_unlock_irqrestore(&hdmi->suspend_lock, flags);
1503 }
1504
1505 static void tegra_dc_hdmi_resume(struct tegra_dc *dc)
1506 {
1507         struct tegra_dc_hdmi_data *hdmi = tegra_dc_get_outdata(dc);
1508         unsigned long flags;
1509
1510         spin_lock_irqsave(&hdmi->suspend_lock, flags);
1511         hdmi->suspended = false;
1512
1513         if (tegra_dc_hdmi_hpd(dc))
1514                 queue_delayed_work(system_nrt_wq, &hdmi->work,
1515                                    msecs_to_jiffies(100));
1516         else
1517                 queue_delayed_work(system_nrt_wq, &hdmi->work,
1518                                    msecs_to_jiffies(30));
1519
1520         spin_unlock_irqrestore(&hdmi->suspend_lock, flags);
1521         tegra_nvhdcp_resume(hdmi->nvhdcp);
1522 }
1523
1524 #ifdef CONFIG_SWITCH
1525 static ssize_t underscan_show(struct device *dev,
1526                                 struct device_attribute *attr, char *buf)
1527 {
1528         struct tegra_dc_hdmi_data *hdmi =
1529                         container_of(dev_get_drvdata(dev), struct tegra_dc_hdmi_data, hpd_switch);
1530
1531         if (hdmi->edid)
1532                 return sprintf(buf, "%d\n", tegra_edid_underscan_supported(hdmi->edid));
1533         else
1534                 return 0;
1535 }
1536
1537 static DEVICE_ATTR(underscan, S_IRUGO | S_IWUSR, underscan_show, NULL);
1538 #endif
1539
1540 static int tegra_dc_hdmi_init(struct tegra_dc *dc)
1541 {
1542         struct tegra_dc_hdmi_data *hdmi;
1543         struct resource *res;
1544         struct resource *base_res;
1545 #ifdef CONFIG_SWITCH
1546         int ret;
1547 #endif
1548         void __iomem *base;
1549         struct clk *clk = NULL;
1550         struct clk *disp1_clk = NULL;
1551         struct clk *disp2_clk = NULL;
1552         int err;
1553
1554         hdmi = kzalloc(sizeof(*hdmi), GFP_KERNEL);
1555         if (!hdmi)
1556                 return -ENOMEM;
1557
1558         res = nvhost_get_resource_byname(dc->ndev, IORESOURCE_MEM, "hdmi_regs");
1559         if (!res) {
1560                 dev_err(&dc->ndev->dev, "hdmi: no mem resource\n");
1561                 err = -ENOENT;
1562                 goto err_free_hdmi;
1563         }
1564
1565         base_res = request_mem_region(res->start, resource_size(res), dc->ndev->name);
1566         if (!base_res) {
1567                 dev_err(&dc->ndev->dev, "hdmi: request_mem_region failed\n");
1568                 err = -EBUSY;
1569                 goto err_free_hdmi;
1570         }
1571
1572         base = ioremap(res->start, resource_size(res));
1573         if (!base) {
1574                 dev_err(&dc->ndev->dev, "hdmi: registers can't be mapped\n");
1575                 err = -EBUSY;
1576                 goto err_release_resource_reg;
1577         }
1578
1579         clk = clk_get(&dc->ndev->dev, "hdmi");
1580         if (IS_ERR_OR_NULL(clk)) {
1581                 dev_err(&dc->ndev->dev, "hdmi: can't get clock\n");
1582                 err = -ENOENT;
1583                 goto err_iounmap_reg;
1584         }
1585
1586         disp1_clk = clk_get_sys("tegradc.0", NULL);
1587         if (IS_ERR_OR_NULL(disp1_clk)) {
1588                 dev_err(&dc->ndev->dev, "hdmi: can't disp1 clock\n");
1589                 err = -ENOENT;
1590                 goto err_put_clock;
1591         }
1592
1593         disp2_clk = clk_get_sys("tegradc.1", NULL);
1594         if (IS_ERR_OR_NULL(disp2_clk)) {
1595                 dev_err(&dc->ndev->dev, "hdmi: can't disp2 clock\n");
1596                 err = -ENOENT;
1597                 goto err_put_clock;
1598         }
1599
1600 #if !defined(CONFIG_ARCH_TEGRA_2x_SOC)
1601         hdmi->hda_clk = clk_get_sys("tegra30-hda", "hda");
1602         if (IS_ERR_OR_NULL(hdmi->hda_clk)) {
1603                 dev_err(&dc->ndev->dev, "hdmi: can't get hda clock\n");
1604                 err = -ENOENT;
1605                 goto err_put_clock;
1606         }
1607
1608         hdmi->hda2codec_clk = clk_get_sys("tegra30-hda", "hda2codec");
1609         if (IS_ERR_OR_NULL(hdmi->hda2codec_clk)) {
1610                 dev_err(&dc->ndev->dev, "hdmi: can't get hda2codec clock\n");
1611                 err = -ENOENT;
1612                 goto err_put_clock;
1613         }
1614
1615         hdmi->hda2hdmi_clk = clk_get_sys("tegra30-hda", "hda2hdmi");
1616         if (IS_ERR_OR_NULL(hdmi->hda2hdmi_clk)) {
1617                 dev_err(&dc->ndev->dev, "hdmi: can't get hda2hdmi clock\n");
1618                 err = -ENOENT;
1619                 goto err_put_clock;
1620         }
1621 #endif
1622
1623         hdmi->edid = tegra_edid_create(dc->out->dcc_bus);
1624         if (IS_ERR_OR_NULL(hdmi->edid)) {
1625                 dev_err(&dc->ndev->dev, "hdmi: can't create edid\n");
1626                 err = PTR_ERR(hdmi->edid);
1627                 goto err_put_clock;
1628         }
1629
1630 #ifdef CONFIG_TEGRA_NVHDCP
1631         hdmi->nvhdcp = tegra_nvhdcp_create(hdmi, dc->ndev->id,
1632                         dc->out->dcc_bus);
1633         if (IS_ERR_OR_NULL(hdmi->nvhdcp)) {
1634                 dev_err(&dc->ndev->dev, "hdmi: can't create nvhdcp\n");
1635                 err = PTR_ERR(hdmi->nvhdcp);
1636                 goto err_edid_destroy;
1637         }
1638 #else
1639         hdmi->nvhdcp = NULL;
1640 #endif
1641
1642         INIT_DELAYED_WORK(&hdmi->work, tegra_dc_hdmi_detect_worker);
1643
1644         hdmi->dc = dc;
1645         hdmi->base = base;
1646         hdmi->base_res = base_res;
1647         hdmi->clk = clk;
1648         hdmi->disp1_clk = disp1_clk;
1649         hdmi->disp2_clk = disp2_clk;
1650         hdmi->suspended = false;
1651         hdmi->eld_retrieved= false;
1652         hdmi->clk_enabled = false;
1653         hdmi->audio_freq = 44100;
1654         hdmi->audio_source = AUTO;
1655         spin_lock_init(&hdmi->suspend_lock);
1656
1657 #ifdef CONFIG_SWITCH
1658         hdmi->hpd_switch.name = "hdmi";
1659         ret = switch_dev_register(&hdmi->hpd_switch);
1660
1661         if (!ret)
1662                 ret = device_create_file(hdmi->hpd_switch.dev,
1663                         &dev_attr_underscan);
1664         BUG_ON(ret != 0);
1665 #endif
1666
1667         dc->out->depth = 24;
1668
1669         tegra_dc_set_outdata(dc, hdmi);
1670
1671         dc_hdmi = hdmi;
1672         /* boards can select default content protection policy */
1673         if (dc->out->flags & TEGRA_DC_OUT_NVHDCP_POLICY_ON_DEMAND)
1674                 tegra_nvhdcp_set_policy(hdmi->nvhdcp,
1675                         TEGRA_NVHDCP_POLICY_ON_DEMAND);
1676         else
1677                 tegra_nvhdcp_set_policy(hdmi->nvhdcp,
1678                         TEGRA_NVHDCP_POLICY_ALWAYS_ON);
1679
1680         tegra_dc_hdmi_debug_create(hdmi);
1681
1682         /* TODO: support non-hotplug */
1683         if (request_irq(gpio_to_irq(dc->out->hotplug_gpio), tegra_dc_hdmi_irq,
1684                 IRQF_TRIGGER_RISING | IRQF_TRIGGER_FALLING,
1685                 dev_name(&dc->ndev->dev), dc)) {
1686                 dev_err(&dc->ndev->dev, "hdmi: request_irq %d failed\n",
1687                         gpio_to_irq(dc->out->hotplug_gpio));
1688                 err = -EBUSY;
1689                 goto err_nvhdcp_destroy;
1690         }
1691
1692         return 0;
1693
1694 err_nvhdcp_destroy:
1695         if (hdmi->nvhdcp)
1696                 tegra_nvhdcp_destroy(hdmi->nvhdcp);
1697 err_edid_destroy:
1698         tegra_edid_destroy(hdmi->edid);
1699 err_put_clock:
1700 #if !defined(CONFIG_ARCH_TEGRA_2x_SOC)
1701         if (!IS_ERR_OR_NULL(hdmi->hda2hdmi_clk))
1702                 clk_put(hdmi->hda2hdmi_clk);
1703         if (!IS_ERR_OR_NULL(hdmi->hda2codec_clk))
1704                 clk_put(hdmi->hda2codec_clk);
1705         if (!IS_ERR_OR_NULL(hdmi->hda_clk))
1706                 clk_put(hdmi->hda_clk);
1707 #endif
1708         if (!IS_ERR_OR_NULL(disp2_clk))
1709                 clk_put(disp2_clk);
1710         if (!IS_ERR_OR_NULL(disp1_clk))
1711                 clk_put(disp1_clk);
1712         if (!IS_ERR_OR_NULL(clk))
1713                 clk_put(clk);
1714 err_iounmap_reg:
1715         iounmap(base);
1716 err_release_resource_reg:
1717         release_resource(base_res);
1718 err_free_hdmi:
1719         kfree(hdmi);
1720         return err;
1721 }
1722
1723 static void tegra_dc_hdmi_destroy(struct tegra_dc *dc)
1724 {
1725         struct tegra_dc_hdmi_data *hdmi = tegra_dc_get_outdata(dc);
1726
1727         free_irq(gpio_to_irq(dc->out->hotplug_gpio), dc);
1728         cancel_delayed_work_sync(&hdmi->work);
1729 #ifdef CONFIG_SWITCH
1730         switch_dev_unregister(&hdmi->hpd_switch);
1731 #endif
1732         iounmap(hdmi->base);
1733         release_resource(hdmi->base_res);
1734 #if !defined(CONFIG_ARCH_TEGRA_2x_SOC)
1735         clk_put(hdmi->hda2hdmi_clk);
1736         clk_put(hdmi->hda2codec_clk);
1737         clk_put(hdmi->hda_clk);
1738 #endif
1739         clk_put(hdmi->clk);
1740         clk_put(hdmi->disp1_clk);
1741         clk_put(hdmi->disp2_clk);
1742         tegra_edid_destroy(hdmi->edid);
1743         tegra_nvhdcp_destroy(hdmi->nvhdcp);
1744
1745         kfree(hdmi);
1746
1747 }
1748
1749 static void tegra_dc_hdmi_setup_audio_fs_tables(struct tegra_dc *dc)
1750 {
1751         struct tegra_dc_hdmi_data *hdmi = tegra_dc_get_outdata(dc);
1752         int i;
1753         unsigned freqs[] = {
1754                 32000,
1755                 44100,
1756                 48000,
1757                 88200,
1758                 96000,
1759                 176400,
1760                 192000,
1761         };
1762
1763         for (i = 0; i < ARRAY_SIZE(freqs); i++) {
1764                 unsigned f = freqs[i];
1765                 unsigned eight_half;
1766                 unsigned delta;;
1767
1768                 if (f > 96000)
1769                         delta = 2;
1770                 else if (f > 48000)
1771                         delta = 6;
1772                 else
1773                         delta = 9;
1774
1775                 eight_half = (8 * HDMI_AUDIOCLK_FREQ) / (f * 128);
1776                 tegra_hdmi_writel(hdmi, AUDIO_FS_LOW(eight_half - delta) |
1777                                   AUDIO_FS_HIGH(eight_half + delta),
1778                                   HDMI_NV_PDISP_AUDIO_FS(i));
1779         }
1780 }
1781
1782 #if !defined(CONFIG_ARCH_TEGRA_2x_SOC)
1783 static void tegra_dc_hdmi_setup_eld_buff(struct tegra_dc *dc)
1784 {
1785         int i;
1786         int j;
1787         u8 tmp;
1788
1789         struct tegra_dc_hdmi_data *hdmi = tegra_dc_get_outdata(dc);
1790
1791         /* program ELD stuff */
1792         for (i = 0; i < HDMI_ELD_MONITOR_NAME_INDEX; i++) {
1793                 switch (i) {
1794                 case HDMI_ELD_VER_INDEX:
1795                         tmp = (hdmi->eld.eld_ver << 3);
1796                         tegra_hdmi_writel(hdmi, (i << 8) | tmp,
1797                                   HDMI_NV_PDISP_SOR_AUDIO_HDA_ELD_BUFWR_0);
1798                         break;
1799                 case HDMI_ELD_BASELINE_LEN_INDEX:
1800                         break;
1801                 case HDMI_ELD_CEA_VER_MNL_INDEX:
1802                         tmp = (hdmi->eld.cea_edid_ver << 5);
1803                         tmp |= (hdmi->eld.mnl & 0x1f);
1804                         tegra_hdmi_writel(hdmi, (i << 8) | tmp,
1805                                           HDMI_NV_PDISP_SOR_AUDIO_HDA_ELD_BUFWR_0);
1806                         break;
1807                 case HDMI_ELD_SAD_CNT_CON_TYP_SAI_HDCP_INDEX:
1808                         tmp = (hdmi->eld.sad_count << 4);
1809                         tmp |= (hdmi->eld.conn_type & 0xC);
1810                         tmp |= (hdmi->eld.support_ai & 0x2);
1811                         tmp |= (hdmi->eld.support_hdcp & 0x1);
1812                         tegra_hdmi_writel(hdmi, (i << 8) | tmp,
1813                                           HDMI_NV_PDISP_SOR_AUDIO_HDA_ELD_BUFWR_0);
1814                         break;
1815                 case HDMI_ELD_AUD_SYNC_DELAY_INDEX:
1816                         tegra_hdmi_writel(hdmi, (i << 8) | (hdmi->eld.aud_synch_delay),
1817                                           HDMI_NV_PDISP_SOR_AUDIO_HDA_ELD_BUFWR_0);
1818                         break;
1819                 case HDMI_ELD_SPK_ALLOC_INDEX:
1820                         tegra_hdmi_writel(hdmi, (i << 8) | (hdmi->eld.spk_alloc),
1821                                           HDMI_NV_PDISP_SOR_AUDIO_HDA_ELD_BUFWR_0);
1822                         break;
1823                 case HDMI_ELD_PORT_ID_INDEX:
1824                         for (j = 0; j < 8;j++) {
1825                                 tegra_hdmi_writel(hdmi, ((i +j) << 8) | (hdmi->eld.port_id[j]),
1826                                           HDMI_NV_PDISP_SOR_AUDIO_HDA_ELD_BUFWR_0);
1827                         }
1828                         break;
1829                 case HDMI_ELD_MANF_NAME_INDEX:
1830                         for (j = 0; j < 2;j++) {
1831                                 tegra_hdmi_writel(hdmi, ((i +j) << 8) | (hdmi->eld.manufacture_id[j]),
1832                                           HDMI_NV_PDISP_SOR_AUDIO_HDA_ELD_BUFWR_0);
1833                         }
1834                         break;
1835                 case HDMI_ELD_PRODUCT_CODE_INDEX:
1836                         for (j = 0; j < 2;j++) {
1837                                 tegra_hdmi_writel(hdmi, ((i +j) << 8) | (hdmi->eld.product_id[j]),
1838                                           HDMI_NV_PDISP_SOR_AUDIO_HDA_ELD_BUFWR_0);
1839                         }
1840                         break;
1841                 }
1842         }
1843         for (j = 0; j < hdmi->eld.mnl;j++) {
1844                 tegra_hdmi_writel(hdmi, ((j + HDMI_ELD_MONITOR_NAME_INDEX) << 8) |
1845                                   (hdmi->eld.monitor_name[j]),
1846                                   HDMI_NV_PDISP_SOR_AUDIO_HDA_ELD_BUFWR_0);
1847         }
1848         for (j = 0; j < hdmi->eld.sad_count;j++) {
1849                 tegra_hdmi_writel(hdmi, ((j + HDMI_ELD_MONITOR_NAME_INDEX + hdmi->eld.mnl) << 8) |
1850                                   (hdmi->eld.sad[j]),
1851                                   HDMI_NV_PDISP_SOR_AUDIO_HDA_ELD_BUFWR_0);
1852         }
1853                 /* set presence andvalid bit  */
1854         tegra_hdmi_writel(hdmi, 3, HDMI_NV_PDISP_SOR_AUDIO_HDA_PRESENSE_0);
1855 }
1856 #endif
1857
1858 static int tegra_dc_hdmi_setup_audio(struct tegra_dc *dc, unsigned audio_freq,
1859                                         unsigned audio_source)
1860 {
1861         struct tegra_dc_hdmi_data *hdmi = tegra_dc_get_outdata(dc);
1862         const struct tegra_hdmi_audio_config *config;
1863         unsigned long audio_n;
1864 #if !defined(CONFIG_ARCH_TEGRA_2x_SOC)
1865         unsigned long reg_addr = 0;
1866 #endif
1867         unsigned a_source = AUDIO_CNTRL0_SOURCE_SELECT_AUTO;
1868
1869         if (HDA == audio_source)
1870                 a_source = AUDIO_CNTRL0_SOURCE_SELECT_HDAL;
1871         else if (SPDIF == audio_source)
1872                 a_source = AUDIO_CNTRL0_SOURCE_SELECT_SPDIF;
1873
1874 #if !defined(CONFIG_ARCH_TEGRA_2x_SOC)
1875         if (hdmi->audio_inject_null)
1876                 a_source |= AUDIO_CNTRL0_INJECT_NULLSMPL;
1877
1878         tegra_hdmi_writel(hdmi,a_source,
1879                           HDMI_NV_PDISP_SOR_AUDIO_CNTRL0_0);
1880         tegra_hdmi_writel(hdmi,
1881                           AUDIO_CNTRL0_ERROR_TOLERANCE(6) |
1882                           AUDIO_CNTRL0_FRAMES_PER_BLOCK(0xc0),
1883                           HDMI_NV_PDISP_AUDIO_CNTRL0);
1884 #else
1885         tegra_hdmi_writel(hdmi,
1886                           AUDIO_CNTRL0_ERROR_TOLERANCE(6) |
1887                           AUDIO_CNTRL0_FRAMES_PER_BLOCK(0xc0) |
1888                           a_source,
1889                           HDMI_NV_PDISP_AUDIO_CNTRL0);
1890 #endif
1891         config = tegra_hdmi_get_audio_config(audio_freq, dc->mode.pclk);
1892         if (!config) {
1893                 dev_err(&dc->ndev->dev,
1894                         "hdmi: can't set audio to %d at %d pix_clock",
1895                         audio_freq, dc->mode.pclk);
1896                 return -EINVAL;
1897         }
1898
1899         tegra_hdmi_writel(hdmi, 0, HDMI_NV_PDISP_HDMI_ACR_CTRL);
1900
1901         audio_n = AUDIO_N_RESETF | AUDIO_N_GENERATE_ALTERNALTE |
1902                 AUDIO_N_VALUE(config->n - 1);
1903         tegra_hdmi_writel(hdmi, audio_n, HDMI_NV_PDISP_AUDIO_N);
1904
1905         tegra_hdmi_writel(hdmi, ACR_SUBPACK_N(config->n) | ACR_ENABLE,
1906                           HDMI_NV_PDISP_HDMI_ACR_0441_SUBPACK_HIGH);
1907
1908         tegra_hdmi_writel(hdmi, ACR_SUBPACK_CTS(config->cts),
1909                           HDMI_NV_PDISP_HDMI_ACR_0441_SUBPACK_LOW);
1910
1911         tegra_hdmi_writel(hdmi, SPARE_HW_CTS | SPARE_FORCE_SW_CTS |
1912                           SPARE_CTS_RESET_VAL(1),
1913                           HDMI_NV_PDISP_HDMI_SPARE);
1914
1915         audio_n &= ~AUDIO_N_RESETF;
1916         tegra_hdmi_writel(hdmi, audio_n, HDMI_NV_PDISP_AUDIO_N);
1917
1918 #if !defined(CONFIG_ARCH_TEGRA_2x_SOC)
1919         switch (audio_freq) {
1920         case AUDIO_FREQ_32K:
1921                 reg_addr = HDMI_NV_PDISP_SOR_AUDIO_AVAL_0320_0;
1922                 break;
1923         case AUDIO_FREQ_44_1K:
1924                 reg_addr = HDMI_NV_PDISP_SOR_AUDIO_AVAL_0441_0;
1925                 break;
1926         case AUDIO_FREQ_48K:
1927                 reg_addr = HDMI_NV_PDISP_SOR_AUDIO_AVAL_0480_0;
1928                 break;
1929         case AUDIO_FREQ_88_2K:
1930                 reg_addr = HDMI_NV_PDISP_SOR_AUDIO_AVAL_0882_0;
1931                 break;
1932         case AUDIO_FREQ_96K:
1933                 reg_addr = HDMI_NV_PDISP_SOR_AUDIO_AVAL_0960_0;
1934                 break;
1935         case AUDIO_FREQ_176_4K:
1936                 reg_addr = HDMI_NV_PDISP_SOR_AUDIO_AVAL_1764_0;
1937                 break;
1938         case AUDIO_FREQ_192K:
1939                 reg_addr = HDMI_NV_PDISP_SOR_AUDIO_AVAL_1920_0;
1940                 break;
1941         }
1942
1943         tegra_hdmi_writel(hdmi, config->aval, reg_addr);
1944 #endif
1945         tegra_dc_hdmi_setup_audio_fs_tables(dc);
1946
1947         return 0;
1948 }
1949
1950 int tegra_hdmi_setup_audio_freq_source(unsigned audio_freq, unsigned audio_source)
1951 {
1952         struct tegra_dc_hdmi_data *hdmi = dc_hdmi;
1953
1954         if (!hdmi)
1955                 return -EAGAIN;
1956
1957         /* check for know freq */
1958         if (AUDIO_FREQ_32K == audio_freq ||
1959                 AUDIO_FREQ_44_1K== audio_freq ||
1960                 AUDIO_FREQ_48K== audio_freq ||
1961                 AUDIO_FREQ_88_2K== audio_freq ||
1962                 AUDIO_FREQ_96K== audio_freq ||
1963                 AUDIO_FREQ_176_4K== audio_freq ||
1964                 AUDIO_FREQ_192K== audio_freq) {
1965                 /* If we can program HDMI, then proceed */
1966                 if (hdmi->clk_enabled)
1967                         tegra_dc_hdmi_setup_audio(hdmi->dc, audio_freq,audio_source);
1968
1969                 /* Store it for using it in enable */
1970                 hdmi->audio_freq = audio_freq;
1971                 hdmi->audio_source = audio_source;
1972         }
1973         else
1974                 return -EINVAL;
1975
1976         return 0;
1977 }
1978 EXPORT_SYMBOL(tegra_hdmi_setup_audio_freq_source);
1979
1980 #if !defined(CONFIG_ARCH_TEGRA_2x_SOC)
1981 int tegra_hdmi_audio_null_sample_inject(bool on)
1982 {
1983         struct tegra_dc_hdmi_data *hdmi = dc_hdmi;
1984         unsigned int val = 0;
1985
1986         if (!hdmi)
1987                 return -EAGAIN;
1988
1989         if (hdmi->audio_inject_null != on) {
1990                 hdmi->audio_inject_null = on;
1991                 if (hdmi->clk_enabled) {
1992                         val = tegra_hdmi_readl(hdmi,
1993                                 HDMI_NV_PDISP_SOR_AUDIO_CNTRL0_0);
1994                         val &= ~AUDIO_CNTRL0_INJECT_NULLSMPL;
1995                         if (on)
1996                                 val |= AUDIO_CNTRL0_INJECT_NULLSMPL;
1997                         tegra_hdmi_writel(hdmi,val,
1998                                 HDMI_NV_PDISP_SOR_AUDIO_CNTRL0_0);
1999                 }
2000         }
2001
2002         return 0;
2003 }
2004 EXPORT_SYMBOL(tegra_hdmi_audio_null_sample_inject);
2005
2006 int tegra_hdmi_setup_hda_presence()
2007 {
2008         struct tegra_dc_hdmi_data *hdmi = dc_hdmi;
2009
2010         if (!hdmi)
2011                 return -EAGAIN;
2012
2013         if (hdmi->clk_enabled && hdmi->eld_retrieved) {
2014                 /* If HDA_PRESENCE is already set reset it */
2015                 if (tegra_hdmi_readl(hdmi,
2016                                      HDMI_NV_PDISP_SOR_AUDIO_HDA_PRESENSE_0))
2017                         tegra_hdmi_writel(hdmi, 0,
2018                                      HDMI_NV_PDISP_SOR_AUDIO_HDA_PRESENSE_0);
2019
2020                 tegra_dc_hdmi_setup_eld_buff(hdmi->dc);
2021         }
2022         else
2023                 return -ENODEV;
2024
2025         return 0;
2026 }
2027 EXPORT_SYMBOL(tegra_hdmi_setup_hda_presence);
2028 #endif
2029
2030 static void tegra_dc_hdmi_write_infopack(struct tegra_dc *dc, int header_reg,
2031                                          u8 type, u8 version, void *data, int len)
2032 {
2033         struct tegra_dc_hdmi_data *hdmi = tegra_dc_get_outdata(dc);
2034         u32 subpack[2];  /* extra byte for zero padding of subpack */
2035         int i;
2036         u8 csum;
2037
2038         /* first byte of data is the checksum */
2039         csum = type + version + len - 1;
2040         for (i = 1; i < len; i++)
2041                 csum +=((u8 *)data)[i];
2042         ((u8 *)data)[0] = 0x100 - csum;
2043
2044         tegra_hdmi_writel(hdmi, INFOFRAME_HEADER_TYPE(type) |
2045                           INFOFRAME_HEADER_VERSION(version) |
2046                           INFOFRAME_HEADER_LEN(len - 1),
2047                           header_reg);
2048
2049         /* The audio inforame only has one set of subpack registers.  The hdmi
2050          * block pads the rest of the data as per the spec so we have to fixup
2051          * the length before filling in the subpacks.
2052          */
2053         if (header_reg == HDMI_NV_PDISP_HDMI_AUDIO_INFOFRAME_HEADER)
2054                 len = 6;
2055
2056         /* each subpack 7 bytes devided into:
2057          *   subpack_low - bytes 0 - 3
2058          *   subpack_high - bytes 4 - 6 (with byte 7 padded to 0x00)
2059          */
2060         for (i = 0; i < len; i++) {
2061                 int subpack_idx = i % 7;
2062
2063                 if (subpack_idx == 0)
2064                         memset(subpack, 0x0, sizeof(subpack));
2065
2066                 ((u8 *)subpack)[subpack_idx] = ((u8 *)data)[i];
2067
2068                 if (subpack_idx == 6 || (i + 1 == len)) {
2069                         int reg = header_reg + 1 + (i / 7) * 2;
2070
2071                         tegra_hdmi_writel(hdmi, subpack[0], reg);
2072                         tegra_hdmi_writel(hdmi, subpack[1], reg + 1);
2073                 }
2074         }
2075 }
2076
2077 static void tegra_dc_hdmi_setup_avi_infoframe(struct tegra_dc *dc, bool dvi)
2078 {
2079         struct tegra_dc_hdmi_data *hdmi = tegra_dc_get_outdata(dc);
2080         struct hdmi_avi_infoframe avi;
2081
2082         if (dvi) {
2083                 tegra_hdmi_writel(hdmi, 0x0,
2084                                   HDMI_NV_PDISP_HDMI_AVI_INFOFRAME_CTRL);
2085                 return;
2086         }
2087
2088         memset(&avi, 0x0, sizeof(avi));
2089
2090         avi.r = HDMI_AVI_R_SAME;
2091
2092         if ((dc->mode.h_active == 720) && ((dc->mode.v_active == 480) || (dc->mode.v_active == 576)))
2093                 tegra_dc_writel(dc, 0x00101010, DC_DISP_BORDER_COLOR);
2094         else
2095                 tegra_dc_writel(dc, 0x00000000, DC_DISP_BORDER_COLOR);
2096
2097         if (dc->mode.v_active == 480) {
2098                 if (dc->mode.h_active == 640) {
2099                         avi.m = HDMI_AVI_M_4_3;
2100                         avi.vic = 1;
2101                 } else {
2102                         avi.m = HDMI_AVI_M_16_9;
2103                         avi.vic = 3;
2104                 }
2105         } else if (dc->mode.v_active == 576) {
2106                 /* CEC modes 17 and 18 differ only by the pysical size of the
2107                  * screen so we have to calculation the physical aspect
2108                  * ratio.  4 * 10 / 3  is 13
2109                  */
2110                 if ((dc->out->h_size * 10) / dc->out->v_size > 14) {
2111                         avi.m = HDMI_AVI_M_16_9;
2112                         avi.vic = 18;
2113                 } else {
2114                         avi.m = HDMI_AVI_M_4_3;
2115                         avi.vic = 17;
2116                 }
2117         } else if (dc->mode.v_active == 720 ||
2118                 (dc->mode.v_active == 1470 && dc->mode.stereo_mode)) {
2119                 /* VIC for both 720p and 720p 3D mode */
2120                 avi.m = HDMI_AVI_M_16_9;
2121                 if (dc->mode.h_front_porch == 110)
2122                         avi.vic = 4; /* 60 Hz */
2123                 else
2124                         avi.vic = 19; /* 50 Hz */
2125         } else if (dc->mode.v_active == 1080 ||
2126                 (dc->mode.v_active == 2205 && dc->mode.stereo_mode)) {
2127                 /* VIC for both 1080p and 1080p 3D mode */
2128                 avi.m = HDMI_AVI_M_16_9;
2129                 if (dc->mode.h_front_porch == 88) {
2130                         if (dc->mode.pclk > 74250000)
2131                                 avi.vic = 16; /* 60 Hz */
2132                         else
2133                                 avi.vic = 34; /* 30 Hz */
2134                 } else if (dc->mode.h_front_porch == 528)
2135                         avi.vic = 31; /* 50 Hz */
2136                 else
2137                         avi.vic = 32; /* 24 Hz */
2138         } else {
2139                 avi.m = HDMI_AVI_M_16_9;
2140                 avi.vic = 0;
2141         }
2142
2143
2144         tegra_dc_hdmi_write_infopack(dc, HDMI_NV_PDISP_HDMI_AVI_INFOFRAME_HEADER,
2145                                      HDMI_INFOFRAME_TYPE_AVI,
2146                                      HDMI_AVI_VERSION,
2147                                      &avi, sizeof(avi));
2148
2149         tegra_hdmi_writel(hdmi, INFOFRAME_CTRL_ENABLE,
2150                           HDMI_NV_PDISP_HDMI_AVI_INFOFRAME_CTRL);
2151 }
2152
2153 static void tegra_dc_hdmi_setup_stereo_infoframe(struct tegra_dc *dc)
2154 {
2155         struct tegra_dc_hdmi_data *hdmi = tegra_dc_get_outdata(dc);
2156         struct hdmi_stereo_infoframe stereo;
2157         u32 val;
2158
2159         if (!dc->mode.stereo_mode) {
2160                 val  = tegra_hdmi_readl(hdmi, HDMI_NV_PDISP_HDMI_GENERIC_CTRL);
2161                 val &= ~GENERIC_CTRL_ENABLE;
2162                 tegra_hdmi_writel(hdmi, val, HDMI_NV_PDISP_HDMI_GENERIC_CTRL);
2163                 return;
2164         }
2165
2166         memset(&stereo, 0x0, sizeof(stereo));
2167
2168         stereo.regid0 = 0x03;
2169         stereo.regid1 = 0x0c;
2170         stereo.regid2 = 0x00;
2171         stereo.hdmi_video_format = 2; /* 3D_Structure present */
2172 #ifndef CONFIG_TEGRA_HDMI_74MHZ_LIMIT
2173         stereo._3d_structure = 0; /* frame packing */
2174 #else
2175         stereo._3d_structure = 8; /* side-by-side (half) */
2176         stereo._3d_ext_data = 0; /* something which fits into 00XX bit req */
2177 #endif
2178
2179         tegra_dc_hdmi_write_infopack(dc, HDMI_NV_PDISP_HDMI_GENERIC_HEADER,
2180                                         HDMI_INFOFRAME_TYPE_VENDOR,
2181                                         HDMI_VENDOR_VERSION,
2182                                         &stereo, 6);
2183
2184         val  = tegra_hdmi_readl(hdmi, HDMI_NV_PDISP_HDMI_GENERIC_CTRL);
2185         val |= GENERIC_CTRL_ENABLE;
2186
2187         tegra_hdmi_writel(hdmi, val, HDMI_NV_PDISP_HDMI_GENERIC_CTRL);
2188 }
2189
2190 static void tegra_dc_hdmi_setup_audio_infoframe(struct tegra_dc *dc, bool dvi)
2191 {
2192         struct tegra_dc_hdmi_data *hdmi = tegra_dc_get_outdata(dc);
2193         struct hdmi_audio_infoframe audio;
2194
2195         if (dvi) {
2196                 tegra_hdmi_writel(hdmi, 0x0,
2197                                   HDMI_NV_PDISP_HDMI_AUDIO_INFOFRAME_CTRL);
2198                 return;
2199         }
2200
2201         memset(&audio, 0x0, sizeof(audio));
2202
2203         audio.cc = HDMI_AUDIO_CC_2;
2204         tegra_dc_hdmi_write_infopack(dc, HDMI_NV_PDISP_HDMI_AUDIO_INFOFRAME_HEADER,
2205                                      HDMI_INFOFRAME_TYPE_AUDIO,
2206                                      HDMI_AUDIO_VERSION,
2207                                      &audio, sizeof(audio));
2208
2209         tegra_hdmi_writel(hdmi, INFOFRAME_CTRL_ENABLE,
2210                           HDMI_NV_PDISP_HDMI_AUDIO_INFOFRAME_CTRL);
2211 }
2212
2213 static void tegra_dc_hdmi_setup_tdms(struct tegra_dc_hdmi_data *hdmi,
2214                 const struct tdms_config *tc)
2215 {
2216         tegra_hdmi_writel(hdmi, tc->pll0, HDMI_NV_PDISP_SOR_PLL0);
2217         tegra_hdmi_writel(hdmi, tc->pll1, HDMI_NV_PDISP_SOR_PLL1);
2218
2219         tegra_hdmi_writel(hdmi, tc->pe_current, HDMI_NV_PDISP_PE_CURRENT);
2220
2221         tegra_hdmi_writel(hdmi,
2222                           tc->drive_current | DRIVE_CURRENT_FUSE_OVERRIDE,
2223                           HDMI_NV_PDISP_SOR_LANE_DRIVE_CURRENT);
2224 }
2225
2226 static void tegra_dc_hdmi_enable(struct tegra_dc *dc)
2227 {
2228         struct tegra_dc_hdmi_data *hdmi = tegra_dc_get_outdata(dc);
2229         int pulse_start;
2230         int dispclk_div_8_2;
2231         int retries;
2232         int rekey;
2233         int err;
2234         unsigned long val;
2235         unsigned i;
2236         unsigned long oldrate;
2237
2238         /* enbale power, clocks, resets, etc. */
2239
2240         /* The upstream DC needs to be clocked for accesses to HDMI to not
2241          * hard lock the system.  Because we don't know if HDMI is conencted
2242          * to disp1 or disp2 we need to enable both until we set the DC mux.
2243          */
2244         clk_enable(hdmi->disp1_clk);
2245         clk_enable(hdmi->disp2_clk);
2246
2247 #if !defined(CONFIG_ARCH_TEGRA_2x_SOC)
2248         /* Enabling HDA clocks before asserting HDA PD and ELDV bits */
2249         clk_enable(hdmi->hda_clk);
2250         clk_enable(hdmi->hda2codec_clk);
2251         clk_enable(hdmi->hda2hdmi_clk);
2252 #endif
2253
2254         /* back off multiplier before attaching to parent at new rate. */
2255         oldrate = clk_get_rate(hdmi->clk);
2256         clk_set_rate(hdmi->clk, oldrate / 2);
2257
2258         tegra_dc_setup_clk(dc, hdmi->clk);
2259         clk_set_rate(hdmi->clk, dc->mode.pclk);
2260
2261         clk_enable(hdmi->clk);
2262         tegra_periph_reset_assert(hdmi->clk);
2263         mdelay(1);
2264         tegra_periph_reset_deassert(hdmi->clk);
2265
2266         /* TODO: copy HDCP keys from KFUSE to HDMI */
2267
2268         /* Program display timing registers: handled by dc */
2269
2270         /* program HDMI registers and SOR sequencer */
2271
2272         tegra_dc_writel(dc, VSYNC_H_POSITION(1), DC_DISP_DISP_TIMING_OPTIONS);
2273         tegra_dc_writel(dc, DITHER_CONTROL_DISABLE | BASE_COLOR_SIZE888,
2274                         DC_DISP_DISP_COLOR_CONTROL);
2275
2276         /* video_preamble uses h_pulse2 */
2277         pulse_start = dc->mode.h_ref_to_sync + dc->mode.h_sync_width +
2278                 dc->mode.h_back_porch - 10;
2279         tegra_dc_writel(dc, H_PULSE_2_ENABLE, DC_DISP_DISP_SIGNAL_OPTIONS0);
2280         tegra_dc_writel(dc,
2281                         PULSE_MODE_NORMAL |
2282                         PULSE_POLARITY_HIGH |
2283                         PULSE_QUAL_VACTIVE |
2284                         PULSE_LAST_END_A,
2285                         DC_DISP_H_PULSE2_CONTROL);
2286         tegra_dc_writel(dc, PULSE_START(pulse_start) | PULSE_END(pulse_start + 8),
2287                   DC_DISP_H_PULSE2_POSITION_A);
2288
2289         tegra_hdmi_writel(hdmi,
2290                           VSYNC_WINDOW_END(0x210) |
2291                           VSYNC_WINDOW_START(0x200) |
2292                           VSYNC_WINDOW_ENABLE,
2293                           HDMI_NV_PDISP_HDMI_VSYNC_WINDOW);
2294
2295         if ((dc->mode.h_active == 720) && ((dc->mode.v_active == 480) || (dc->mode.v_active == 576)))
2296                 tegra_hdmi_writel(hdmi,
2297                                   (dc->ndev->id ? HDMI_SRC_DISPLAYB : HDMI_SRC_DISPLAYA) |
2298                                   ARM_VIDEO_RANGE_FULL,
2299                                   HDMI_NV_PDISP_INPUT_CONTROL);
2300         else
2301                 tegra_hdmi_writel(hdmi,
2302                                   (dc->ndev->id ? HDMI_SRC_DISPLAYB : HDMI_SRC_DISPLAYA) |
2303                                   ARM_VIDEO_RANGE_LIMITED,
2304                                   HDMI_NV_PDISP_INPUT_CONTROL);
2305
2306         clk_disable(hdmi->disp1_clk);
2307         clk_disable(hdmi->disp2_clk);
2308
2309         dispclk_div_8_2 = clk_get_rate(hdmi->clk) / 1000000 * 4;
2310         tegra_hdmi_writel(hdmi,
2311                           SOR_REFCLK_DIV_INT(dispclk_div_8_2 >> 2) |
2312                           SOR_REFCLK_DIV_FRAC(dispclk_div_8_2),
2313                           HDMI_NV_PDISP_SOR_REFCLK);
2314
2315         hdmi->clk_enabled = true;
2316
2317         if (!hdmi->dvi) {
2318                 err = tegra_dc_hdmi_setup_audio(dc, hdmi->audio_freq,
2319                         hdmi->audio_source);
2320
2321                 if (err < 0)
2322                         hdmi->dvi = true;
2323         }
2324
2325 #if !defined(CONFIG_ARCH_TEGRA_2x_SOC)
2326         if (hdmi->eld_retrieved)
2327                 tegra_dc_hdmi_setup_eld_buff(dc);
2328 #endif
2329
2330         rekey = HDMI_REKEY_DEFAULT;
2331         val = HDMI_CTRL_REKEY(rekey);
2332         val |= HDMI_CTRL_MAX_AC_PACKET((dc->mode.h_sync_width +
2333                                         dc->mode.h_back_porch +
2334                                         dc->mode.h_front_porch -
2335                                         rekey - 18) / 32);
2336         if (!hdmi->dvi)
2337                 val |= HDMI_CTRL_ENABLE;
2338         tegra_hdmi_writel(hdmi, val, HDMI_NV_PDISP_HDMI_CTRL);
2339
2340         if (hdmi->dvi)
2341                 tegra_hdmi_writel(hdmi, 0x0,
2342                                   HDMI_NV_PDISP_HDMI_GENERIC_CTRL);
2343         else
2344                 tegra_hdmi_writel(hdmi, GENERIC_CTRL_AUDIO,
2345                                   HDMI_NV_PDISP_HDMI_GENERIC_CTRL);
2346
2347         tegra_dc_hdmi_setup_avi_infoframe(dc, hdmi->dvi);
2348         tegra_dc_hdmi_setup_audio_infoframe(dc, hdmi->dvi);
2349         tegra_dc_hdmi_setup_stereo_infoframe(dc);
2350
2351         /* TMDS CONFIG */
2352         for (i = 0; i < ARRAY_SIZE(tdms_config); i++) {
2353                 if (dc->mode.pclk <= tdms_config[i].pclk) {
2354                         tegra_dc_hdmi_setup_tdms(hdmi, &tdms_config[i]);
2355                         break;
2356                 }
2357         }
2358
2359         tegra_hdmi_writel(hdmi,
2360                           SOR_SEQ_CTL_PU_PC(0) |
2361                           SOR_SEQ_PU_PC_ALT(0) |
2362                           SOR_SEQ_PD_PC(8) |
2363                           SOR_SEQ_PD_PC_ALT(8),
2364                           HDMI_NV_PDISP_SOR_SEQ_CTL);
2365
2366         val = SOR_SEQ_INST_WAIT_TIME(1) |
2367                 SOR_SEQ_INST_WAIT_UNITS_VSYNC |
2368                 SOR_SEQ_INST_HALT |
2369                 SOR_SEQ_INST_PIN_A_LOW |
2370                 SOR_SEQ_INST_PIN_B_LOW |
2371                 SOR_SEQ_INST_DRIVE_PWM_OUT_LO;
2372
2373         tegra_hdmi_writel(hdmi, val, HDMI_NV_PDISP_SOR_SEQ_INST0);
2374         tegra_hdmi_writel(hdmi, val, HDMI_NV_PDISP_SOR_SEQ_INST8);
2375
2376         val = 0x1c800;
2377         val &= ~SOR_CSTM_ROTCLK(~0);
2378         val |= SOR_CSTM_ROTCLK(2);
2379         tegra_hdmi_writel(hdmi, val, HDMI_NV_PDISP_SOR_CSTM);
2380
2381
2382         tegra_dc_writel(dc, DISP_CTRL_MODE_STOP, DC_CMD_DISPLAY_COMMAND);
2383         tegra_dc_writel(dc, GENERAL_ACT_REQ << 8, DC_CMD_STATE_CONTROL);
2384         tegra_dc_writel(dc, GENERAL_ACT_REQ, DC_CMD_STATE_CONTROL);
2385
2386
2387         /* start SOR */
2388         tegra_hdmi_writel(hdmi,
2389                           SOR_PWR_NORMAL_STATE_PU |
2390                           SOR_PWR_NORMAL_START_NORMAL |
2391                           SOR_PWR_SAFE_STATE_PD |
2392                           SOR_PWR_SETTING_NEW_TRIGGER,
2393                           HDMI_NV_PDISP_SOR_PWR);
2394         tegra_hdmi_writel(hdmi,
2395                           SOR_PWR_NORMAL_STATE_PU |
2396                           SOR_PWR_NORMAL_START_NORMAL |
2397                           SOR_PWR_SAFE_STATE_PD |
2398                           SOR_PWR_SETTING_NEW_DONE,
2399                           HDMI_NV_PDISP_SOR_PWR);
2400
2401         retries = 1000;
2402         do {
2403                 BUG_ON(--retries < 0);
2404                 val = tegra_hdmi_readl(hdmi, HDMI_NV_PDISP_SOR_PWR);
2405         } while (val & SOR_PWR_SETTING_NEW_PENDING);
2406
2407         val = SOR_STATE_ASY_CRCMODE_COMPLETE |
2408                 SOR_STATE_ASY_OWNER_HEAD0 |
2409                 SOR_STATE_ASY_SUBOWNER_BOTH |
2410                 SOR_STATE_ASY_PROTOCOL_SINGLE_TMDS_A |
2411                 SOR_STATE_ASY_DEPOL_POS;
2412
2413         if (dc->mode.flags & TEGRA_DC_MODE_FLAG_NEG_H_SYNC)
2414                 val |= SOR_STATE_ASY_HSYNCPOL_NEG;
2415         else
2416                 val |= SOR_STATE_ASY_HSYNCPOL_POS;
2417
2418         if (dc->mode.flags & TEGRA_DC_MODE_FLAG_NEG_V_SYNC)
2419                 val |= SOR_STATE_ASY_VSYNCPOL_NEG;
2420         else
2421                 val |= SOR_STATE_ASY_VSYNCPOL_POS;
2422
2423         tegra_hdmi_writel(hdmi, val, HDMI_NV_PDISP_SOR_STATE2);
2424
2425         val = SOR_STATE_ASY_HEAD_OPMODE_AWAKE | SOR_STATE_ASY_ORMODE_NORMAL;
2426         tegra_hdmi_writel(hdmi, val, HDMI_NV_PDISP_SOR_STATE1);
2427
2428         tegra_hdmi_writel(hdmi, 0, HDMI_NV_PDISP_SOR_STATE0);
2429         tegra_hdmi_writel(hdmi, SOR_STATE_UPDATE, HDMI_NV_PDISP_SOR_STATE0);
2430         tegra_hdmi_writel(hdmi, val | SOR_STATE_ATTACHED,
2431                           HDMI_NV_PDISP_SOR_STATE1);
2432         tegra_hdmi_writel(hdmi, 0, HDMI_NV_PDISP_SOR_STATE0);
2433
2434         tegra_dc_writel(dc, HDMI_ENABLE, DC_DISP_DISP_WIN_OPTIONS);
2435
2436         tegra_dc_writel(dc, PW0_ENABLE | PW1_ENABLE | PW2_ENABLE | PW3_ENABLE |
2437                         PW4_ENABLE | PM0_ENABLE | PM1_ENABLE,
2438                         DC_CMD_DISPLAY_POWER_CONTROL);
2439
2440         tegra_dc_writel(dc, DISP_CTRL_MODE_C_DISPLAY, DC_CMD_DISPLAY_COMMAND);
2441         tegra_dc_writel(dc, GENERAL_ACT_REQ << 8, DC_CMD_STATE_CONTROL);
2442         tegra_dc_writel(dc, GENERAL_ACT_REQ, DC_CMD_STATE_CONTROL);
2443
2444         tegra_nvhdcp_set_plug(hdmi->nvhdcp, 1);
2445 }
2446
2447 static void tegra_dc_hdmi_disable(struct tegra_dc *dc)
2448 {
2449         struct tegra_dc_hdmi_data *hdmi = tegra_dc_get_outdata(dc);
2450
2451         tegra_nvhdcp_set_plug(hdmi->nvhdcp, 0);
2452
2453 #if !defined(CONFIG_ARCH_TEGRA_2x_SOC)
2454         tegra_hdmi_writel(hdmi, 0, HDMI_NV_PDISP_SOR_AUDIO_HDA_PRESENSE_0);
2455         /* sleep 1ms before disabling clocks to ensure HDA gets the interrupt */
2456         msleep(1);
2457         clk_disable(hdmi->hda2hdmi_clk);
2458         clk_disable(hdmi->hda2codec_clk);
2459         clk_disable(hdmi->hda_clk);
2460 #endif
2461         tegra_periph_reset_assert(hdmi->clk);
2462         hdmi->clk_enabled = false;
2463         clk_disable(hdmi->clk);
2464         tegra_dvfs_set_rate(hdmi->clk, 0);
2465 }
2466
2467 struct tegra_dc_out_ops tegra_dc_hdmi_ops = {
2468         .init = tegra_dc_hdmi_init,
2469         .destroy = tegra_dc_hdmi_destroy,
2470         .enable = tegra_dc_hdmi_enable,
2471         .disable = tegra_dc_hdmi_disable,
2472         .detect = tegra_dc_hdmi_detect,
2473         .suspend = tegra_dc_hdmi_suspend,
2474         .resume = tegra_dc_hdmi_resume,
2475         .mode_filter = tegra_dc_hdmi_mode_filter,
2476 };
2477
2478 struct tegra_dc_edid *tegra_dc_get_edid(struct tegra_dc *dc)
2479 {
2480         struct tegra_dc_hdmi_data *hdmi;
2481
2482         /* TODO: Support EDID on non-HDMI devices */
2483         if (dc->out->type != TEGRA_DC_OUT_HDMI)
2484                 return ERR_PTR(-ENODEV);
2485
2486         hdmi = tegra_dc_get_outdata(dc);
2487
2488         return tegra_edid_get_data(hdmi->edid);
2489 }
2490 EXPORT_SYMBOL(tegra_dc_get_edid);
2491
2492 void tegra_dc_put_edid(struct tegra_dc_edid *edid)
2493 {
2494         tegra_edid_put_data(edid);
2495 }
2496 EXPORT_SYMBOL(tegra_dc_put_edid);