video: tegra: dsi: Fix read in lp write config
[linux-2.6.git] / drivers / video / tegra / dc / dsi.c
1 /*
2  * drivers/video/tegra/dc/dsi.c
3  *
4  * Copyright (c) 2011, NVIDIA Corporation.
5  *
6  * This software is licensed under the terms of the GNU General Public
7  * License version 2, as published by the Free Software Foundation, and
8  * may be copied, distributed, and modified under those terms.
9  *
10  * This program is distributed in the hope that it will be useful,
11  * but WITHOUT ANY WARRANTY; without even the implied warranty of
12  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
13  * GNU General Public License for more details.
14  *
15  */
16
17 #include <linux/clk.h>
18 #include <linux/delay.h>
19 #include <linux/err.h>
20 #include <linux/fb.h>
21 #include <linux/gpio.h>
22 #include <linux/interrupt.h>
23 #include <linux/kernel.h>
24 #include <linux/slab.h>
25 #include <linux/spinlock.h>
26 #include <linux/workqueue.h>
27
28 #include <mach/clk.h>
29 #include <mach/dc.h>
30 #include <mach/fb.h>
31 #include <mach/csi.h>
32 #include <linux/nvhost.h>
33 #include <../gpio-names.h>
34
35 #include "dc_reg.h"
36 #include "dc_priv.h"
37 #include "dsi_regs.h"
38 #include "dsi.h"
39
40 #define DSI_USE_SYNC_POINTS             1
41 #define S_TO_MS(x)                      (1000 * (x))
42
43 #define DSI_MODULE_NOT_INIT             0x0
44 #define DSI_MODULE_INIT                 0x1
45
46 #define DSI_LPHS_NOT_INIT               0x0
47 #define DSI_LPHS_IN_LP_MODE             0x1
48 #define DSI_LPHS_IN_HS_MODE             0x2
49
50 #define DSI_VIDEO_TYPE_NOT_INIT         0x0
51 #define DSI_VIDEO_TYPE_VIDEO_MODE       0x1
52 #define DSI_VIDEO_TYPE_CMD_MODE         0x2
53
54 #define DSI_DRIVEN_MODE_NOT_INIT        0x0
55 #define DSI_DRIVEN_MODE_DC              0x1
56 #define DSI_DRIVEN_MODE_HOST            0x2
57
58 #define DSI_PHYCLK_OUT_DIS              0x0
59 #define DSI_PHYCLK_OUT_EN               0x1
60
61 #define DSI_PHYCLK_NOT_INIT             0x0
62 #define DSI_PHYCLK_CONTINUOUS           0x1
63 #define DSI_PHYCLK_TX_ONLY              0x2
64
65 #define DSI_CLK_BURST_NOT_INIT          0x0
66 #define DSI_CLK_BURST_NONE_BURST        0x1
67 #define DSI_CLK_BURST_BURST_MODE        0x2
68
69 #define DSI_DC_STREAM_DISABLE           0x0
70 #define DSI_DC_STREAM_ENABLE            0x1
71
72 #define DSI_LP_OP_NOT_INIT              0x0
73 #define DSI_LP_OP_WRITE                 0x1
74 #define DSI_LP_OP_READ                  0x2
75
76 static bool enable_read_debug;
77 module_param(enable_read_debug, bool, 0644);
78 MODULE_PARM_DESC(enable_read_debug,
79                 "Enable to print read fifo and return packet type");
80
81 struct dsi_status {
82         unsigned init:2;
83
84         unsigned lphs:2;
85
86         unsigned vtype:2;
87         unsigned driven:2;
88
89         unsigned clk_out:2;
90         unsigned clk_mode:2;
91         unsigned clk_burst:2;
92
93         unsigned lp_op:2;
94
95         unsigned dc_stream:1;
96 };
97
98 /* source of video data */
99 enum {
100         TEGRA_DSI_DRIVEN_BY_DC,
101         TEGRA_DSI_DRIVEN_BY_HOST,
102 };
103
104 struct tegra_dc_dsi_data {
105         struct tegra_dc *dc;
106         void __iomem *base;
107         struct resource *base_res;
108
109         struct clk *dc_clk;
110         struct clk *dsi_clk;
111         bool clk_ref;
112
113         struct mutex lock;
114
115         /* data from board info */
116         struct tegra_dsi_out info;
117
118         struct dsi_status status;
119
120         u8 driven_mode;
121         u8 controller_index;
122
123         u8 pixel_scaler_mul;
124         u8 pixel_scaler_div;
125
126         u32 default_shift_clk_div;
127         u32 default_pixel_clk_khz;
128         u32 default_hs_clk_khz;
129
130         u32 shift_clk_div;
131         u32 target_hs_clk_khz;
132         u32 target_lp_clk_khz;
133
134         u32 syncpt_id;
135         u32 syncpt_val;
136
137         u16 current_bit_clk_ns;
138         u32 current_dsi_clk_khz;
139
140         u32 dsi_control_val;
141
142         bool ulpm;
143         bool enabled;
144 };
145
146 const u32 dsi_pkt_seq_reg[NUMOF_PKT_SEQ] = {
147         DSI_PKT_SEQ_0_LO,
148         DSI_PKT_SEQ_0_HI,
149         DSI_PKT_SEQ_1_LO,
150         DSI_PKT_SEQ_1_HI,
151         DSI_PKT_SEQ_2_LO,
152         DSI_PKT_SEQ_2_HI,
153         DSI_PKT_SEQ_3_LO,
154         DSI_PKT_SEQ_3_HI,
155         DSI_PKT_SEQ_4_LO,
156         DSI_PKT_SEQ_4_HI,
157         DSI_PKT_SEQ_5_LO,
158         DSI_PKT_SEQ_5_HI,
159 };
160
161 const u32 dsi_pkt_seq_video_non_burst_syne[NUMOF_PKT_SEQ] = {
162         PKT_ID0(CMD_VS) | PKT_LEN0(0) | PKT_ID1(CMD_EOT) | PKT_LEN1(0) | PKT_LP,
163         0,
164         PKT_ID0(CMD_VE) | PKT_LEN0(0) | PKT_ID1(CMD_EOT) | PKT_LEN1(0) | PKT_LP,
165         0,
166         PKT_ID0(CMD_HS) | PKT_LEN0(0) | PKT_ID1(CMD_EOT) | PKT_LEN1(0) | PKT_LP,
167         0,
168         PKT_ID0(CMD_HS) | PKT_LEN0(0) | PKT_ID1(CMD_BLNK) | PKT_LEN1(1) |
169         PKT_ID2(CMD_HE) | PKT_LEN2(0),
170         PKT_ID3(CMD_BLNK) | PKT_LEN3(2) | PKT_ID4(CMD_RGB) | PKT_LEN4(3) |
171         PKT_ID5(CMD_BLNK) | PKT_LEN5(4),
172         PKT_ID0(CMD_HS) | PKT_LEN0(0) | PKT_ID1(CMD_EOT) | PKT_LEN1(0) | PKT_LP,
173         0,
174         PKT_ID0(CMD_HS) | PKT_LEN0(0) | PKT_ID1(CMD_BLNK) | PKT_LEN1(1) |
175         PKT_ID2(CMD_HE) | PKT_LEN2(0),
176         PKT_ID3(CMD_BLNK) | PKT_LEN3(2) | PKT_ID4(CMD_RGB) | PKT_LEN4(3) |
177         PKT_ID5(CMD_BLNK) | PKT_LEN5(4),
178 };
179
180 const u32 dsi_pkt_seq_video_non_burst[NUMOF_PKT_SEQ] = {
181         PKT_ID0(CMD_VS) | PKT_LEN0(0) | PKT_ID1(CMD_EOT) | PKT_LEN1(0) | PKT_LP,
182         0,
183         PKT_ID0(CMD_HS) | PKT_LEN0(0) | PKT_ID1(CMD_EOT) | PKT_LEN1(0) | PKT_LP,
184         0,
185         PKT_ID0(CMD_HS) | PKT_LEN0(0) | PKT_ID1(CMD_EOT) | PKT_LEN1(0) | PKT_LP,
186         0,
187         PKT_ID0(CMD_HS) | PKT_LEN0(0) | PKT_ID1(CMD_BLNK) | PKT_LEN1(2) |
188         PKT_ID2(CMD_RGB) | PKT_LEN2(3),
189         PKT_ID3(CMD_BLNK) | PKT_LEN3(4),
190         PKT_ID0(CMD_HS) | PKT_LEN0(0) | PKT_ID1(CMD_EOT) | PKT_LEN1(0) | PKT_LP,
191         0,
192         PKT_ID0(CMD_HS) | PKT_LEN0(0) | PKT_ID1(CMD_BLNK) | PKT_LEN1(2) |
193         PKT_ID2(CMD_RGB) | PKT_LEN2(3),
194         PKT_ID3(CMD_BLNK) | PKT_LEN3(4),
195 };
196
197 static const u32 dsi_pkt_seq_video_burst[NUMOF_PKT_SEQ] = {
198         PKT_ID0(CMD_VS) | PKT_LEN0(0) | PKT_ID1(CMD_EOT) | PKT_LEN1(7) | PKT_LP,
199         0,
200         PKT_ID0(CMD_HS) | PKT_LEN0(0) | PKT_ID1(CMD_EOT) | PKT_LEN1(7) | PKT_LP,
201         0,
202         PKT_ID0(CMD_HS) | PKT_LEN0(0) | PKT_ID1(CMD_EOT) | PKT_LEN1(7) | PKT_LP,
203         0,
204         PKT_ID0(CMD_HS) | PKT_LEN0(0) | PKT_ID1(CMD_BLNK) | PKT_LEN1(2)|
205         PKT_ID2(CMD_RGB) | PKT_LEN2(3) | PKT_LP,
206         PKT_ID0(CMD_EOT) | PKT_LEN0(7),
207         PKT_ID0(CMD_HS) | PKT_LEN0(0) | PKT_ID1(CMD_EOT) | PKT_LEN1(7) | PKT_LP,
208         0,
209         PKT_ID0(CMD_HS) | PKT_LEN0(0) | PKT_ID1(CMD_BLNK) | PKT_LEN1(2)|
210         PKT_ID2(CMD_RGB) | PKT_LEN2(3) | PKT_LP,
211         PKT_ID0(CMD_EOT) | PKT_LEN0(7),
212 };
213
214 static const u32 dsi_pkt_seq_video_burst_no_eot[NUMOF_PKT_SEQ] = {
215         PKT_ID0(CMD_VS) | PKT_LEN0(0) | PKT_ID1(CMD_EOT) | PKT_LEN1(0) | PKT_LP,
216         0,
217         PKT_ID0(CMD_HS) | PKT_LEN0(0) | PKT_ID1(CMD_EOT) | PKT_LEN1(0) | PKT_LP,
218         0,
219         PKT_ID0(CMD_HS) | PKT_LEN0(0) | PKT_ID1(CMD_EOT) | PKT_LEN1(0) | PKT_LP,
220         0,
221         PKT_ID0(CMD_HS) | PKT_LEN0(0) | PKT_ID1(CMD_BLNK) | PKT_LEN1(2)|
222         PKT_ID2(CMD_RGB) | PKT_LEN2(3) | PKT_LP,
223         PKT_ID0(CMD_EOT) | PKT_LEN0(0),
224         PKT_ID0(CMD_HS) | PKT_LEN0(0) | PKT_ID1(CMD_EOT) | PKT_LEN1(0) | PKT_LP,
225         0,
226         PKT_ID0(CMD_HS) | PKT_LEN0(0) | PKT_ID1(CMD_BLNK) | PKT_LEN1(2)|
227         PKT_ID2(CMD_RGB) | PKT_LEN2(3) | PKT_LP,
228         PKT_ID0(CMD_EOT) | PKT_LEN0(0),
229 };
230
231 /* TODO: verify with hw about this format */
232 const u32 dsi_pkt_seq_cmd_mode[NUMOF_PKT_SEQ] = {
233         0,
234         0,
235         0,
236         0,
237         0,
238         0,
239         PKT_ID0(CMD_LONGW) | PKT_LEN0(3) | PKT_ID1(CMD_EOT) | PKT_LEN1(7),
240         0,
241         0,
242         0,
243         PKT_ID0(CMD_LONGW) | PKT_LEN0(3) | PKT_ID1(CMD_EOT) | PKT_LEN1(7),
244         0,
245 };
246
247 const u32 init_reg[] = {
248         DSI_INT_ENABLE,
249         DSI_INT_STATUS,
250         DSI_INT_MASK,
251         DSI_INIT_SEQ_DATA_0,
252         DSI_INIT_SEQ_DATA_1,
253         DSI_INIT_SEQ_DATA_2,
254         DSI_INIT_SEQ_DATA_3,
255         DSI_INIT_SEQ_DATA_4,
256         DSI_INIT_SEQ_DATA_5,
257         DSI_INIT_SEQ_DATA_6,
258         DSI_INIT_SEQ_DATA_7,
259         DSI_DCS_CMDS,
260         DSI_PKT_SEQ_0_LO,
261         DSI_PKT_SEQ_1_LO,
262         DSI_PKT_SEQ_2_LO,
263         DSI_PKT_SEQ_3_LO,
264         DSI_PKT_SEQ_4_LO,
265         DSI_PKT_SEQ_5_LO,
266         DSI_PKT_SEQ_0_HI,
267         DSI_PKT_SEQ_1_HI,
268         DSI_PKT_SEQ_2_HI,
269         DSI_PKT_SEQ_3_HI,
270         DSI_PKT_SEQ_4_HI,
271         DSI_PKT_SEQ_5_HI,
272         DSI_CONTROL,
273         DSI_HOST_DSI_CONTROL,
274         DSI_PAD_CONTROL,
275         DSI_PAD_CONTROL_CD,
276         DSI_SOL_DELAY,
277         DSI_MAX_THRESHOLD,
278         DSI_TRIGGER,
279         DSI_TX_CRC,
280         DSI_INIT_SEQ_CONTROL,
281         DSI_PKT_LEN_0_1,
282         DSI_PKT_LEN_2_3,
283         DSI_PKT_LEN_4_5,
284         DSI_PKT_LEN_6_7,
285 };
286
287 inline unsigned long tegra_dsi_readl(struct tegra_dc_dsi_data *dsi, u32 reg)
288 {
289         return readl(dsi->base + reg * 4);
290 }
291 EXPORT_SYMBOL(tegra_dsi_readl);
292
293 inline void tegra_dsi_writel(struct tegra_dc_dsi_data *dsi, u32 val, u32 reg)
294 {
295         writel(val, dsi->base + reg * 4);
296 }
297 EXPORT_SYMBOL(tegra_dsi_writel);
298
299 static int tegra_dsi_syncpt(struct tegra_dc_dsi_data *dsi)
300 {
301         u32 val;
302         int ret;
303
304         ret = 0;
305
306         dsi->syncpt_val = nvhost_syncpt_read(
307                         &dsi->dc->ndev->host->syncpt, dsi->syncpt_id);
308
309         val = DSI_INCR_SYNCPT_COND(OP_DONE) |
310                 DSI_INCR_SYNCPT_INDX(dsi->syncpt_id);
311         tegra_dsi_writel(dsi, val, DSI_INCR_SYNCPT);
312
313         /* TODO: Use interrupt rather than polling */
314         ret = nvhost_syncpt_wait(&dsi->dc->ndev->host->syncpt,
315                 dsi->syncpt_id, dsi->syncpt_val + 1);
316         if (ret < 0) {
317                 printk(KERN_ERR "DSI sync point failure\n");
318                 goto fail;
319         }
320
321         (dsi->syncpt_val)++;
322         return 0;
323 fail:
324         return ret;
325 }
326
327 static u32 tegra_dsi_get_hs_clk_rate(struct tegra_dc_dsi_data *dsi)
328 {
329         u32 dsi_clock_rate_khz;
330
331         switch (dsi->info.video_burst_mode) {
332         case TEGRA_DSI_VIDEO_BURST_MODE_LOW_SPEED:
333         case TEGRA_DSI_VIDEO_BURST_MODE_MEDIUM_SPEED:
334         case TEGRA_DSI_VIDEO_BURST_MODE_FAST_SPEED:
335         case TEGRA_DSI_VIDEO_BURST_MODE_FASTEST_SPEED:
336                 /* Calculate DSI HS clock rate for DSI burst mode */
337                 dsi_clock_rate_khz = dsi->default_pixel_clk_khz *
338                                                         dsi->shift_clk_div;
339                 break;
340         case TEGRA_DSI_VIDEO_NONE_BURST_MODE:
341         case TEGRA_DSI_VIDEO_NONE_BURST_MODE_WITH_SYNC_END:
342         case TEGRA_DSI_VIDEO_BURST_MODE_LOWEST_SPEED:
343         default:
344                 /* Clock rate is default DSI clock rate for non-burst mode */
345                 dsi_clock_rate_khz = dsi->default_hs_clk_khz;
346                 break;
347         }
348
349         return dsi_clock_rate_khz;
350 }
351
352 static u32 tegra_dsi_get_lp_clk_rate(struct tegra_dc_dsi_data *dsi, u8 lp_op)
353 {
354         u32 dsi_clock_rate_khz;
355
356         if (dsi->info.enable_hs_clock_on_lp_cmd_mode)
357                 if (dsi->info.hs_clk_in_lp_cmd_mode_freq_khz)
358                         dsi_clock_rate_khz =
359                                 dsi->info.hs_clk_in_lp_cmd_mode_freq_khz;
360                 else
361                         dsi_clock_rate_khz = tegra_dsi_get_hs_clk_rate(dsi);
362         else
363                 if (lp_op == DSI_LP_OP_READ)
364                         dsi_clock_rate_khz =
365                                 dsi->info.lp_read_cmd_mode_freq_khz;
366                 else
367                         dsi_clock_rate_khz =
368                                 dsi->info.lp_cmd_mode_freq_khz;
369
370         return dsi_clock_rate_khz;
371 }
372
373 static u32 tegra_dsi_get_shift_clk_div(struct tegra_dc_dsi_data *dsi)
374 {
375         u32 shift_clk_div;
376         u32 max_shift_clk_div;
377         u32 burst_width;
378         u32 burst_width_max;
379
380         /* Get the real value of default shift_clk_div. default_shift_clk_div
381          * holds the real value of shift_clk_div.
382          */
383         shift_clk_div = dsi->default_shift_clk_div;
384
385         /* Calculate shift_clk_div which can matche the video_burst_mode. */
386         if (dsi->info.video_burst_mode >=
387                         TEGRA_DSI_VIDEO_BURST_MODE_LOWEST_SPEED) {
388                 /* The max_shift_clk_div is multiplied by 10 to save the
389                  * fraction
390                  */
391                 if (dsi->info.max_panel_freq_khz >= dsi->default_hs_clk_khz)
392                         max_shift_clk_div = dsi->info.max_panel_freq_khz
393                                 * shift_clk_div * 10 / dsi->default_hs_clk_khz;
394                 else
395                         max_shift_clk_div = shift_clk_div * 10;
396
397                 burst_width = dsi->info.video_burst_mode
398                                 - TEGRA_DSI_VIDEO_BURST_MODE_LOWEST_SPEED;
399                 burst_width_max = TEGRA_DSI_VIDEO_BURST_MODE_FASTEST_SPEED
400                                 - TEGRA_DSI_VIDEO_BURST_MODE_LOWEST_SPEED;
401
402                 shift_clk_div = (max_shift_clk_div - shift_clk_div * 10) *
403                         burst_width / (burst_width_max * 10) + shift_clk_div;
404         }
405
406         return shift_clk_div;
407 }
408
409 static void tegra_dsi_init_sw(struct tegra_dc *dc,
410                         struct tegra_dc_dsi_data *dsi)
411 {
412         u32 h_width_pixels;
413         u32 v_width_lines;
414         u32 pixel_clk_hz;
415         u32 byte_clk_hz;
416         u32 plld_clk_mhz;
417
418         switch (dsi->info.pixel_format) {
419         case TEGRA_DSI_PIXEL_FORMAT_16BIT_P:
420                 /* 2 bytes per pixel */
421                 dsi->pixel_scaler_mul = 2;
422                 dsi->pixel_scaler_div = 1;
423                 break;
424         case TEGRA_DSI_PIXEL_FORMAT_18BIT_P:
425                 /* 2.25 bytes per pixel */
426                 dsi->pixel_scaler_mul = 9;
427                 dsi->pixel_scaler_div = 4;
428                 break;
429         case TEGRA_DSI_PIXEL_FORMAT_18BIT_NP:
430         case TEGRA_DSI_PIXEL_FORMAT_24BIT_P:
431                 /* 3 bytes per pixel */
432                 dsi->pixel_scaler_mul = 3;
433                 dsi->pixel_scaler_div = 1;
434                 break;
435         default:
436                 break;
437         }
438
439         dsi->controller_index = dc->ndev->id;
440         dsi->ulpm = false;
441         dsi->enabled = false;
442         dsi->clk_ref = false;
443
444         dsi->dsi_control_val =
445                         DSI_CONTROL_VIRTUAL_CHANNEL(dsi->info.virtual_channel) |
446                         DSI_CONTROL_NUM_DATA_LANES(dsi->info.n_data_lanes - 1) |
447                         DSI_CONTROL_VID_SOURCE(dsi->controller_index) |
448                         DSI_CONTROL_DATA_FORMAT(dsi->info.pixel_format);
449
450         /* Below we are going to calculate dsi and dc clock rate.
451          * Calcuate the horizontal and vertical width.
452          */
453         h_width_pixels = dc->mode.h_back_porch + dc->mode.h_front_porch +
454                         dc->mode.h_sync_width + dc->mode.h_active;
455         v_width_lines = dc->mode.v_back_porch + dc->mode.v_front_porch +
456                         dc->mode.v_sync_width + dc->mode.v_active;
457
458         /* Calculate minimum required pixel rate. */
459         pixel_clk_hz = h_width_pixels * v_width_lines * dsi->info.refresh_rate;
460
461         dc->pixel_clk = pixel_clk_hz;
462
463         /* Calculate minimum byte rate on DSI interface. */
464         byte_clk_hz = (pixel_clk_hz * dsi->pixel_scaler_mul) /
465                         (dsi->pixel_scaler_div * dsi->info.n_data_lanes);
466
467         /* Round up to multiple of mega hz. */
468         plld_clk_mhz = DIV_ROUND_UP((byte_clk_hz * NUMOF_BIT_PER_BYTE),
469                                                                 1000000);
470
471         /* Calculate default real shift_clk_div. */
472         dsi->default_shift_clk_div = (NUMOF_BIT_PER_BYTE / 2) *
473                 dsi->pixel_scaler_mul / (dsi->pixel_scaler_div *
474                 dsi->info.n_data_lanes);
475         /* Calculate default DSI hs clock. DSI interface is double data rate.
476          * Data is transferred on both rising and falling edge of clk, div by 2
477          * to get the actual clock rate.
478          */
479         dsi->default_hs_clk_khz = plld_clk_mhz * 1000 / 2;
480         dsi->default_pixel_clk_khz = plld_clk_mhz * 1000 / 2
481                                                 / dsi->default_shift_clk_div;
482
483         /* Get the actual shift_clk_div and clock rates. */
484         dsi->shift_clk_div = tegra_dsi_get_shift_clk_div(dsi);
485         dsi->target_lp_clk_khz =
486                         tegra_dsi_get_lp_clk_rate(dsi, DSI_LP_OP_WRITE);
487         dsi->target_hs_clk_khz = tegra_dsi_get_hs_clk_rate(dsi);
488
489         dev_info(&dc->ndev->dev, "DSI: HS clock rate is %d\n",
490                                                         dsi->target_hs_clk_khz);
491
492         dsi->controller_index = dc->ndev->id;
493
494 #if DSI_USE_SYNC_POINTS
495         dsi->syncpt_id = NVSYNCPT_DSI;
496 #endif
497
498         /*
499          * Force video clock to be continuous mode if
500          * enable_hs_clock_on_lp_cmd_mode is set
501          */
502         if (dsi->info.enable_hs_clock_on_lp_cmd_mode) {
503                 if (dsi->info.video_clock_mode !=
504                                         TEGRA_DSI_VIDEO_CLOCK_CONTINUOUS)
505                         printk(KERN_WARNING "Force clock continuous mode\n");
506
507                 dsi->info.video_clock_mode = TEGRA_DSI_VIDEO_CLOCK_CONTINUOUS;
508         }
509
510 }
511
512 static void tegra_dsi_get_phy_timing(struct tegra_dc_dsi_data *dsi,
513                                 struct dsi_phy_timing_inclk *phy_timing_clk,
514                                 u32 clk_ns)
515 {
516
517         phy_timing_clk->t_hsdexit = dsi->info.phy_timing.t_hsdexit_ns ?
518                         (dsi->info.phy_timing.t_hsdexit_ns / clk_ns) :
519                         (T_HSEXIT_DEFAULT(clk_ns));
520
521         phy_timing_clk->t_hstrail = dsi->info.phy_timing.t_hstrail_ns ?
522                         (dsi->info.phy_timing.t_hstrail_ns / clk_ns) :
523                         (T_HSTRAIL_DEFAULT(clk_ns));
524
525         phy_timing_clk->t_datzero = dsi->info.phy_timing.t_datzero_ns ?
526                         (dsi->info.phy_timing.t_datzero_ns / clk_ns) :
527                         (T_DATZERO_DEFAULT(clk_ns));
528
529         phy_timing_clk->t_hsprepr = dsi->info.phy_timing.t_hsprepr_ns ?
530                         (dsi->info.phy_timing.t_hsprepr_ns / clk_ns) :
531                         (T_HSPREPR_DEFAULT(clk_ns));
532
533         phy_timing_clk->t_clktrail = dsi->info.phy_timing.t_clktrail_ns ?
534                                 (dsi->info.phy_timing.t_clktrail_ns / clk_ns) :
535                                 (T_CLKTRAIL_DEFAULT(clk_ns));
536
537         phy_timing_clk->t_clkpost = dsi->info.phy_timing.t_clkpost_ns ?
538                                 (dsi->info.phy_timing.t_clkpost_ns / clk_ns) :
539                                 (T_CLKPOST_DEFAULT(clk_ns));
540
541         phy_timing_clk->t_clkzero = dsi->info.phy_timing.t_clkzero_ns ?
542                                 (dsi->info.phy_timing.t_clkzero_ns / clk_ns) :
543                                 (T_CLKZERO_DEFAULT(clk_ns));
544
545         phy_timing_clk->t_tlpx = dsi->info.phy_timing.t_tlpx_ns ?
546                                 (dsi->info.phy_timing.t_tlpx_ns / clk_ns) :
547                                 (T_TLPX_DEFAULT(clk_ns));
548
549         phy_timing_clk->t_clkpre = T_CLKPRE_DEFAULT(clk_ns);
550         phy_timing_clk->t_clkprepare = T_CLKPREPARE_DEFAULT(clk_ns);
551         phy_timing_clk->t_wakeup = T_WAKEUP_DEFAULT(clk_ns);
552
553         phy_timing_clk->t_taget = 5 * phy_timing_clk->t_tlpx;
554         phy_timing_clk->t_tasure = 2 * phy_timing_clk->t_tlpx;
555         phy_timing_clk->t_tago = 4 * phy_timing_clk->t_tlpx;
556 }
557
558 static void tegra_dsi_set_phy_timing(struct tegra_dc_dsi_data *dsi)
559 {
560         u32 val;
561         struct dsi_phy_timing_inclk phy_timing;
562
563         tegra_dsi_get_phy_timing(dsi, &phy_timing, dsi->current_bit_clk_ns);
564
565         val = DSI_PHY_TIMING_0_THSDEXIT(phy_timing.t_hsdexit) |
566                         DSI_PHY_TIMING_0_THSTRAIL(phy_timing.t_hstrail) |
567                         DSI_PHY_TIMING_0_TDATZERO(phy_timing.t_datzero) |
568                         DSI_PHY_TIMING_0_THSPREPR(phy_timing.t_hsprepr);
569         tegra_dsi_writel(dsi, val, DSI_PHY_TIMING_0);
570
571         val = DSI_PHY_TIMING_1_TCLKTRAIL(phy_timing.t_clktrail) |
572                         DSI_PHY_TIMING_1_TCLKPOST(phy_timing.t_clkpost) |
573                         DSI_PHY_TIMING_1_TCLKZERO(phy_timing.t_clkzero) |
574                         DSI_PHY_TIMING_1_TTLPX(phy_timing.t_tlpx);
575         tegra_dsi_writel(dsi, val, DSI_PHY_TIMING_1);
576
577         val = DSI_PHY_TIMING_2_TCLKPREPARE(phy_timing.t_clkprepare) |
578                 DSI_PHY_TIMING_2_TCLKPRE(phy_timing.t_clkpre) |
579                         DSI_PHY_TIMING_2_TWAKEUP(phy_timing.t_wakeup);
580         tegra_dsi_writel(dsi, val, DSI_PHY_TIMING_2);
581
582         val = DSI_BTA_TIMING_TTAGET(phy_timing.t_taget) |
583                         DSI_BTA_TIMING_TTASURE(phy_timing.t_tasure) |
584                         DSI_BTA_TIMING_TTAGO(phy_timing.t_tago);
585         tegra_dsi_writel(dsi, val, DSI_BTA_TIMING);
586 }
587
588 static u32 tegra_dsi_sol_delay_burst(struct tegra_dc *dc,
589                                 struct tegra_dc_dsi_data *dsi)
590 {
591         u32 dsi_to_pixel_clk_ratio;
592         u32 temp;
593         u32 temp1;
594         u32 mipi_clk_adj_kHz;
595         u32 sol_delay;
596         struct tegra_dc_mode *dc_modes = &dc->mode;
597
598         /* Get Fdsi/Fpixel ration (note: Fdsi is in bit format) */
599         dsi_to_pixel_clk_ratio = (dsi->current_dsi_clk_khz * 2 +
600                 dsi->default_pixel_clk_khz - 1) / dsi->default_pixel_clk_khz;
601
602         /* Convert Fdsi to byte format */
603         dsi_to_pixel_clk_ratio *= 1000/8;
604
605         /* Multiplying by 1000 so that we don't loose the fraction part */
606         temp = dc_modes->h_active * 1000;
607         temp1 = dc_modes->h_active + dc_modes->h_back_porch +
608                         dc_modes->h_sync_width;
609
610         sol_delay = temp1 * dsi_to_pixel_clk_ratio -
611                         temp * dsi->pixel_scaler_mul /
612                         (dsi->pixel_scaler_div * dsi->info.n_data_lanes);
613
614         /* Do rounding on sol delay */
615         sol_delay = (sol_delay + 1000 - 1)/1000;
616
617         /* TODO:
618          * 1. find out the correct sol fifo depth to use
619          * 2. verify with hw about the clamping function
620          */
621         if (sol_delay > (480 * 4)) {
622                 sol_delay = (480 * 4);
623                 mipi_clk_adj_kHz = sol_delay +
624                         (dc_modes->h_active * dsi->pixel_scaler_mul) /
625                         (dsi->info.n_data_lanes * dsi->pixel_scaler_div);
626
627                 mipi_clk_adj_kHz *= (dsi->default_pixel_clk_khz / temp1);
628
629                 mipi_clk_adj_kHz *= 4;
630         }
631
632         dsi->target_hs_clk_khz = mipi_clk_adj_kHz;
633
634         return sol_delay;
635 }
636
637 static void tegra_dsi_set_sol_delay(struct tegra_dc *dc,
638                                 struct tegra_dc_dsi_data *dsi)
639 {
640         u32 sol_delay;
641
642         if (dsi->info.video_burst_mode == TEGRA_DSI_VIDEO_NONE_BURST_MODE ||
643                 dsi->info.video_burst_mode ==
644                                 TEGRA_DSI_VIDEO_NONE_BURST_MODE_WITH_SYNC_END) {
645                 sol_delay = NUMOF_BIT_PER_BYTE * dsi->pixel_scaler_mul /
646                         (dsi->pixel_scaler_div * dsi->info.n_data_lanes);
647                 dsi->status.clk_burst = DSI_CLK_BURST_NONE_BURST;
648         } else {
649                 sol_delay = tegra_dsi_sol_delay_burst(dc, dsi);
650                 dsi->status.clk_burst = DSI_CLK_BURST_BURST_MODE;
651         }
652
653         tegra_dsi_writel(dsi, DSI_SOL_DELAY_SOL_DELAY(sol_delay),
654                                                                 DSI_SOL_DELAY);
655 }
656
657 static void tegra_dsi_set_timeout(struct tegra_dc_dsi_data *dsi)
658 {
659         u32 val;
660         u32 bytes_per_frame;
661         u32 timeout = 0;
662
663         /* TODO: verify the following equation */
664         bytes_per_frame = dsi->current_dsi_clk_khz * 1000 * 2 /
665                                                 (dsi->info.refresh_rate * 8);
666         timeout = bytes_per_frame / DSI_CYCLE_COUNTER_VALUE;
667         timeout = (timeout + DSI_HTX_TO_MARGIN) & 0xffff;
668
669         val = DSI_TIMEOUT_0_LRXH_TO(DSI_LRXH_TO_VALUE) |
670                         DSI_TIMEOUT_0_HTX_TO(timeout);
671         tegra_dsi_writel(dsi, val, DSI_TIMEOUT_0);
672
673         if (dsi->info.panel_reset_timeout_msec)
674                 timeout = (dsi->info.panel_reset_timeout_msec * 1000*1000)
675                                         / dsi->current_bit_clk_ns;
676         else
677                 timeout = DSI_PR_TO_VALUE;
678
679         val = DSI_TIMEOUT_1_PR_TO(timeout) |
680                 DSI_TIMEOUT_1_TA_TO(DSI_TA_TO_VALUE);
681         tegra_dsi_writel(dsi, val, DSI_TIMEOUT_1);
682
683         val = DSI_TO_TALLY_P_RESET_STATUS(IN_RESET) |
684                 DSI_TO_TALLY_TA_TALLY(DSI_TA_TALLY_VALUE)|
685                 DSI_TO_TALLY_LRXH_TALLY(DSI_LRXH_TALLY_VALUE)|
686                 DSI_TO_TALLY_HTX_TALLY(DSI_HTX_TALLY_VALUE);
687         tegra_dsi_writel(dsi, val, DSI_TO_TALLY);
688 }
689
690 static void tegra_dsi_setup_video_mode_pkt_length(struct tegra_dc *dc,
691                                                 struct tegra_dc_dsi_data *dsi)
692 {
693         u32 val;
694         u32 hact_pkt_len;
695         u32 hsa_pkt_len;
696         u32 hbp_pkt_len;
697         u32 hfp_pkt_len;
698
699         hact_pkt_len = dc->mode.h_active * dsi->pixel_scaler_mul /
700                                                         dsi->pixel_scaler_div;
701         hsa_pkt_len = dc->mode.h_sync_width * dsi->pixel_scaler_mul /
702                                                         dsi->pixel_scaler_div;
703         hbp_pkt_len = dc->mode.h_back_porch * dsi->pixel_scaler_mul /
704                                                         dsi->pixel_scaler_div;
705         hfp_pkt_len = dc->mode.h_front_porch * dsi->pixel_scaler_mul /
706                                                         dsi->pixel_scaler_div;
707
708         if (dsi->info.video_burst_mode !=
709                                 TEGRA_DSI_VIDEO_NONE_BURST_MODE_WITH_SYNC_END)
710                 hbp_pkt_len += hsa_pkt_len;
711
712         hsa_pkt_len -= DSI_HSYNC_BLNK_PKT_OVERHEAD;
713         hbp_pkt_len -= DSI_HBACK_PORCH_PKT_OVERHEAD;
714         hfp_pkt_len -= DSI_HFRONT_PORCH_PKT_OVERHEAD;
715
716         val = DSI_PKT_LEN_0_1_LENGTH_0(0) |
717                         DSI_PKT_LEN_0_1_LENGTH_1(hsa_pkt_len);
718         tegra_dsi_writel(dsi, val, DSI_PKT_LEN_0_1);
719
720         val = DSI_PKT_LEN_2_3_LENGTH_2(hbp_pkt_len) |
721                         DSI_PKT_LEN_2_3_LENGTH_3(hact_pkt_len);
722         tegra_dsi_writel(dsi, val, DSI_PKT_LEN_2_3);
723
724         val = DSI_PKT_LEN_4_5_LENGTH_4(hfp_pkt_len) |
725                         DSI_PKT_LEN_4_5_LENGTH_5(0);
726         tegra_dsi_writel(dsi, val, DSI_PKT_LEN_4_5);
727
728         val = DSI_PKT_LEN_6_7_LENGTH_6(0) | DSI_PKT_LEN_6_7_LENGTH_7(0);
729         tegra_dsi_writel(dsi, val, DSI_PKT_LEN_6_7);
730 }
731
732 static void tegra_dsi_setup_cmd_mode_pkt_length(struct tegra_dc *dc,
733                                                 struct tegra_dc_dsi_data *dsi)
734 {
735         unsigned long   val;
736         unsigned long   act_bytes;
737
738         act_bytes = dc->mode.h_active * dsi->pixel_scaler_mul /
739                         dsi->pixel_scaler_div + 1;
740
741         val = DSI_PKT_LEN_0_1_LENGTH_0(0) | DSI_PKT_LEN_0_1_LENGTH_1(0);
742         tegra_dsi_writel(dsi, val, DSI_PKT_LEN_0_1);
743
744         val = DSI_PKT_LEN_2_3_LENGTH_2(0) | DSI_PKT_LEN_2_3_LENGTH_3(act_bytes);
745         tegra_dsi_writel(dsi, val, DSI_PKT_LEN_2_3);
746
747         val = DSI_PKT_LEN_4_5_LENGTH_4(0) | DSI_PKT_LEN_4_5_LENGTH_5(act_bytes);
748         tegra_dsi_writel(dsi, val, DSI_PKT_LEN_4_5);
749
750         val = DSI_PKT_LEN_6_7_LENGTH_6(0) | DSI_PKT_LEN_6_7_LENGTH_7(0x0f0f);
751         tegra_dsi_writel(dsi, val, DSI_PKT_LEN_6_7);
752 }
753
754 static void tegra_dsi_set_pkt_length(struct tegra_dc *dc,
755                                 struct tegra_dc_dsi_data *dsi)
756 {
757         if (dsi->driven_mode == TEGRA_DSI_DRIVEN_BY_HOST)
758                 return;
759
760         if (dsi->info.video_data_type == TEGRA_DSI_VIDEO_TYPE_VIDEO_MODE)
761                 tegra_dsi_setup_video_mode_pkt_length(dc, dsi);
762         else
763                 tegra_dsi_setup_cmd_mode_pkt_length(dc, dsi);
764 }
765
766 static void tegra_dsi_set_pkt_seq(struct tegra_dc *dc,
767                                 struct tegra_dc_dsi_data *dsi)
768 {
769         const u32 *pkt_seq;
770         u32 rgb_info;
771         u32 pkt_seq_3_5_rgb_lo;
772         u32 pkt_seq_3_5_rgb_hi;
773         u32     val;
774         u32 reg;
775         u8  i;
776
777         if (dsi->driven_mode == TEGRA_DSI_DRIVEN_BY_HOST)
778                 return;
779
780         switch (dsi->info.pixel_format) {
781         case TEGRA_DSI_PIXEL_FORMAT_16BIT_P:
782                 rgb_info = CMD_RGB_16BPP;
783                 break;
784         case TEGRA_DSI_PIXEL_FORMAT_18BIT_P:
785                 rgb_info = CMD_RGB_18BPP;
786                 break;
787         case TEGRA_DSI_PIXEL_FORMAT_18BIT_NP:
788                 rgb_info = CMD_RGB_18BPPNP;
789                 break;
790         case TEGRA_DSI_PIXEL_FORMAT_24BIT_P:
791         default:
792                 rgb_info = CMD_RGB_24BPP;
793                 break;
794         }
795
796         pkt_seq_3_5_rgb_lo = 0;
797         pkt_seq_3_5_rgb_hi = 0;
798         if (dsi->info.video_data_type == TEGRA_DSI_VIDEO_TYPE_COMMAND_MODE)
799                 pkt_seq = dsi_pkt_seq_cmd_mode;
800         else {
801                 switch (dsi->info.video_burst_mode) {
802                 case TEGRA_DSI_VIDEO_BURST_MODE_LOWEST_SPEED:
803                 case TEGRA_DSI_VIDEO_BURST_MODE_LOW_SPEED:
804                 case TEGRA_DSI_VIDEO_BURST_MODE_MEDIUM_SPEED:
805                 case TEGRA_DSI_VIDEO_BURST_MODE_FAST_SPEED:
806                 case TEGRA_DSI_VIDEO_BURST_MODE_FASTEST_SPEED:
807                         pkt_seq_3_5_rgb_lo =
808                                         DSI_PKT_SEQ_3_LO_PKT_32_ID(rgb_info);
809                         if (!dsi->info.no_pkt_seq_eot)
810                                 pkt_seq = dsi_pkt_seq_video_burst;
811                         else
812                                 pkt_seq = dsi_pkt_seq_video_burst_no_eot;
813                         break;
814                 case TEGRA_DSI_VIDEO_NONE_BURST_MODE_WITH_SYNC_END:
815                         pkt_seq_3_5_rgb_hi =
816                                         DSI_PKT_SEQ_3_HI_PKT_34_ID(rgb_info);
817                         pkt_seq = dsi_pkt_seq_video_non_burst_syne;
818                         break;
819                 case TEGRA_DSI_VIDEO_NONE_BURST_MODE:
820                 default:
821                         pkt_seq_3_5_rgb_lo =
822                                         DSI_PKT_SEQ_3_LO_PKT_32_ID(rgb_info);
823                         pkt_seq = dsi_pkt_seq_video_non_burst;
824                         break;
825                 }
826         }
827
828         for (i = 0; i < NUMOF_PKT_SEQ; i++) {
829                 val = pkt_seq[i];
830                 reg = dsi_pkt_seq_reg[i];
831                 if ((reg == DSI_PKT_SEQ_3_LO) || (reg == DSI_PKT_SEQ_5_LO))
832                         val |= pkt_seq_3_5_rgb_lo;
833                 if ((reg == DSI_PKT_SEQ_3_HI) || (reg == DSI_PKT_SEQ_5_HI))
834                         val |= pkt_seq_3_5_rgb_hi;
835                 tegra_dsi_writel(dsi, val, reg);
836         }
837 }
838
839 static void tegra_dsi_stop_dc_stream(struct tegra_dc *dc,
840                                         struct tegra_dc_dsi_data *dsi)
841 {
842         tegra_dc_writel(dc, 0, DC_DISP_DISP_WIN_OPTIONS);
843         tegra_dc_writel(dc, GENERAL_ACT_REQ << 8, DC_CMD_STATE_CONTROL);
844         tegra_dc_writel(dc, GENERAL_ACT_REQ, DC_CMD_STATE_CONTROL);
845
846         dsi->status.dc_stream = DSI_DC_STREAM_DISABLE;
847 }
848
849 void tegra_dsi_stop_dc_stream_at_frame_end(struct tegra_dc *dc,
850                                                 struct tegra_dc_dsi_data *dsi)
851 {
852         int val;
853         long timeout;
854         u32 frame_period = DIV_ROUND_UP(S_TO_MS(1), dsi->info.refresh_rate);
855
856         /* stop dc */
857         tegra_dsi_stop_dc_stream(dc, dsi);
858
859         /* enable frame end interrupt */
860         val = tegra_dc_readl(dc, DC_CMD_INT_MASK);
861         val |= FRAME_END_INT;
862         tegra_dc_writel(dc, val, DC_CMD_INT_MASK);
863
864         /* wait for frame_end completion */
865         timeout = wait_for_completion_interruptible_timeout(
866                         &dc->frame_end_complete,
867                         msecs_to_jiffies(frame_period));
868
869         /* disable frame end interrupt */
870         val = tegra_dc_readl(dc, DC_CMD_INT_MASK);
871         val &= ~FRAME_END_INT;
872         tegra_dc_writel(dc, val, DC_CMD_INT_MASK);
873
874         if (timeout == 0)
875                 printk(KERN_WARNING "DC doesn't stop at end of frame.\n");
876 }
877
878 static void tegra_dsi_start_dc_stream(struct tegra_dc *dc,
879                                         struct tegra_dc_dsi_data *dsi)
880 {
881         u32 val;
882
883         tegra_dc_writel(dc, DSI_ENABLE, DC_DISP_DISP_WIN_OPTIONS);
884
885         /* TODO: clean up */
886         tegra_dc_writel(dc, PW0_ENABLE | PW1_ENABLE | PW2_ENABLE | PW3_ENABLE |
887                         PW4_ENABLE | PM0_ENABLE | PM1_ENABLE,
888                         DC_CMD_DISPLAY_POWER_CONTROL);
889
890         /* Configure one-shot mode or continuous mode */
891         if (dc->out->flags & TEGRA_DC_OUT_ONE_SHOT_MODE) {
892                 /* disable LSPI/LCD_DE output */
893                 val = PIN_OUTPUT_LSPI_OUTPUT_DIS;
894                 tegra_dc_writel(dc, val, DC_COM_PIN_OUTPUT_ENABLE3);
895
896                 /* enable MSF & set MSF polarity */
897                 val = MSF_ENABLE | MSF_LSPI;
898                 if (!dsi->info.te_polarity_low)
899                         val |= MSF_POLARITY_HIGH;
900                 else
901                         val |= MSF_POLARITY_LOW;
902                 tegra_dc_writel(dc, val, DC_CMD_DISPLAY_COMMAND_OPTION0);
903
904                 /* set non-continuous mode */
905                 tegra_dc_writel(dc, DISP_CTRL_MODE_NC_DISPLAY,
906                                                 DC_CMD_DISPLAY_COMMAND);
907                 tegra_dc_writel(dc, GENERAL_UPDATE, DC_CMD_STATE_CONTROL);
908                 tegra_dc_writel(dc, GENERAL_ACT_REQ | NC_HOST_TRIG,
909                                                 DC_CMD_STATE_CONTROL);
910         } else {
911                 /* set continuous mode */
912                 tegra_dc_writel(dc, DISP_CTRL_MODE_C_DISPLAY,
913                                                 DC_CMD_DISPLAY_COMMAND);
914                 tegra_dc_writel(dc, GENERAL_UPDATE, DC_CMD_STATE_CONTROL);
915                 tegra_dc_writel(dc, GENERAL_ACT_REQ, DC_CMD_STATE_CONTROL);
916         }
917
918         dsi->status.dc_stream = DSI_DC_STREAM_ENABLE;
919 }
920
921 static void tegra_dsi_set_dc_clk(struct tegra_dc *dc,
922                                 struct tegra_dc_dsi_data *dsi)
923 {
924         u32 shift_clk_div_register;
925         u32 val;
926
927         /* Get the corresponding register value of shift_clk_div. */
928         shift_clk_div_register = dsi->shift_clk_div * 2 - 2;
929
930 #ifdef CONFIG_TEGRA_FPGA_PLATFORM
931         shift_clk_div_register = 1;
932 #endif
933
934         /* TODO: find out if PCD3 option is required */
935         val = PIXEL_CLK_DIVIDER_PCD1 |
936                 SHIFT_CLK_DIVIDER(shift_clk_div_register);
937         tegra_dc_writel(dc, val, DC_DISP_DISP_CLOCK_CONTROL);
938 }
939
940 static void tegra_dsi_set_dsi_clk(struct tegra_dc *dc,
941                         struct tegra_dc_dsi_data *dsi, u32 clk)
942 {
943         u32 rm;
944
945         rm = clk % 1000;
946         if (rm != 0)
947                 clk -= rm;
948
949         clk *= 2;       /*
950                          * Value for PLLD routine is required to be twice as
951                          * the desired clock rate
952                          */
953
954         dc->mode.pclk = clk*1000;
955         tegra_dc_setup_clk(dc, dsi->dsi_clk);
956         if (dsi->clk_ref == true)
957                 clk_disable(dsi->dsi_clk);
958         else
959                 dsi->clk_ref = true;
960         clk_enable(dsi->dsi_clk);
961         tegra_periph_reset_deassert(dsi->dsi_clk);
962
963         dsi->current_dsi_clk_khz = clk_get_rate(dsi->dsi_clk) / 1000;
964
965         dsi->current_bit_clk_ns =  1000*1000 / (dsi->current_dsi_clk_khz * 2);
966 }
967
968 static void tegra_dsi_hs_clk_out_enable(struct tegra_dc_dsi_data *dsi)
969 {
970         u32 val;
971
972         val = tegra_dsi_readl(dsi, DSI_CONTROL);
973         val &= ~DSI_CONTROL_HS_CLK_CTRL(1);
974
975         if (dsi->info.video_clock_mode == TEGRA_DSI_VIDEO_CLOCK_CONTINUOUS) {
976                 val |= DSI_CONTROL_HS_CLK_CTRL(CONTINUOUS);
977                 dsi->status.clk_mode = DSI_PHYCLK_CONTINUOUS;
978         } else {
979                 val |= DSI_CONTROL_HS_CLK_CTRL(TX_ONLY);
980                 dsi->status.clk_mode = DSI_PHYCLK_TX_ONLY;
981         }
982         tegra_dsi_writel(dsi, val, DSI_CONTROL);
983
984         val = tegra_dsi_readl(dsi, DSI_HOST_DSI_CONTROL);
985         val &= ~DSI_HOST_DSI_CONTROL_HIGH_SPEED_TRANS(1);
986         val |= DSI_HOST_DSI_CONTROL_HIGH_SPEED_TRANS(TEGRA_DSI_HIGH);
987         tegra_dsi_writel(dsi, val, DSI_HOST_DSI_CONTROL);
988
989         dsi->status.clk_out = DSI_PHYCLK_OUT_EN;
990 }
991
992 static void tegra_dsi_hs_clk_out_enable_in_lp(struct tegra_dc_dsi_data *dsi)
993 {
994         u32 val;
995         tegra_dsi_hs_clk_out_enable(dsi);
996
997         val = tegra_dsi_readl(dsi, DSI_HOST_DSI_CONTROL);
998         val &= ~DSI_HOST_DSI_CONTROL_HIGH_SPEED_TRANS(1);
999         val |= DSI_HOST_DSI_CONTROL_HIGH_SPEED_TRANS(TEGRA_DSI_LOW);
1000         tegra_dsi_writel(dsi, val, DSI_HOST_DSI_CONTROL);
1001 }
1002
1003 static void tegra_dsi_hs_clk_out_disable(struct tegra_dc *dc,
1004                                                 struct tegra_dc_dsi_data *dsi)
1005 {
1006         u32 val;
1007
1008         if (dsi->status.dc_stream == DSI_DC_STREAM_ENABLE)
1009                 tegra_dsi_stop_dc_stream(dc, dsi);
1010
1011         val = tegra_dsi_readl(dsi, DSI_CONTROL);
1012         val &= ~DSI_CONTROL_HS_CLK_CTRL(1);
1013         val |= DSI_CONTROL_HS_CLK_CTRL(TX_ONLY);
1014         tegra_dsi_writel(dsi, val, DSI_CONTROL);
1015
1016         /* TODO: issue a cmd */
1017
1018         val = tegra_dsi_readl(dsi, DSI_HOST_DSI_CONTROL);
1019         val &= ~DSI_HOST_DSI_CONTROL_HIGH_SPEED_TRANS(1);
1020         val |= DSI_HOST_DSI_CONTROL_HIGH_SPEED_TRANS(TEGRA_DSI_LOW);
1021         tegra_dsi_writel(dsi, val, DSI_HOST_DSI_CONTROL);
1022
1023         dsi->status.clk_mode = DSI_PHYCLK_NOT_INIT;
1024         dsi->status.clk_out = DSI_PHYCLK_OUT_DIS;
1025 }
1026
1027 static void tegra_dsi_set_control_reg_lp(struct tegra_dc_dsi_data *dsi)
1028 {
1029         u32 dsi_control;
1030         u32 host_dsi_control;
1031         u32 max_threshold;
1032
1033         dsi_control = dsi->dsi_control_val | DSI_CTRL_HOST_DRIVEN;
1034         host_dsi_control = HOST_DSI_CTRL_COMMON |
1035                         HOST_DSI_CTRL_HOST_DRIVEN |
1036                         DSI_HOST_DSI_CONTROL_HIGH_SPEED_TRANS(TEGRA_DSI_LOW);
1037         max_threshold = DSI_MAX_THRESHOLD_MAX_THRESHOLD(DSI_HOST_FIFO_DEPTH);
1038
1039         tegra_dsi_writel(dsi, max_threshold, DSI_MAX_THRESHOLD);
1040         tegra_dsi_writel(dsi, dsi_control, DSI_CONTROL);
1041         tegra_dsi_writel(dsi, host_dsi_control, DSI_HOST_DSI_CONTROL);
1042
1043         dsi->status.driven = DSI_DRIVEN_MODE_HOST;
1044         dsi->status.clk_burst = DSI_CLK_BURST_NOT_INIT;
1045         dsi->status.vtype = DSI_VIDEO_TYPE_NOT_INIT;
1046 }
1047
1048 static void tegra_dsi_set_control_reg_hs(struct tegra_dc_dsi_data *dsi)
1049 {
1050         u32 dsi_control;
1051         u32 host_dsi_control;
1052         u32 max_threshold;
1053         u32 dcs_cmd;
1054
1055         dsi_control = dsi->dsi_control_val;
1056         host_dsi_control = HOST_DSI_CTRL_COMMON;
1057         max_threshold = 0;
1058         dcs_cmd = 0;
1059
1060         if (dsi->driven_mode == TEGRA_DSI_DRIVEN_BY_HOST) {
1061                 dsi_control |= DSI_CTRL_HOST_DRIVEN;
1062                 host_dsi_control |= HOST_DSI_CTRL_HOST_DRIVEN;
1063                 max_threshold =
1064                         DSI_MAX_THRESHOLD_MAX_THRESHOLD(DSI_HOST_FIFO_DEPTH);
1065                 dsi->status.driven = DSI_DRIVEN_MODE_HOST;
1066         } else {
1067                 dsi_control |= DSI_CTRL_DC_DRIVEN;
1068                 host_dsi_control |= HOST_DSI_CTRL_DC_DRIVEN;
1069                 max_threshold =
1070                         DSI_MAX_THRESHOLD_MAX_THRESHOLD(DSI_VIDEO_FIFO_DEPTH);
1071                 dsi->status.driven = DSI_DRIVEN_MODE_DC;
1072         }
1073
1074         if (dsi->info.video_data_type == TEGRA_DSI_VIDEO_TYPE_COMMAND_MODE) {
1075                 dsi_control |= DSI_CTRL_CMD_MODE;
1076                 dcs_cmd = DSI_DCS_CMDS_LT5_DCS_CMD(DSI_WRITE_MEMORY_START)|
1077                         DSI_DCS_CMDS_LT3_DCS_CMD(DSI_WRITE_MEMORY_CONTINUE);
1078                 dsi->status.vtype = DSI_VIDEO_TYPE_CMD_MODE;
1079
1080         } else {
1081                 dsi_control |= DSI_CTRL_VIDEO_MODE;
1082                 dsi->status.vtype = DSI_VIDEO_TYPE_VIDEO_MODE;
1083         }
1084
1085         tegra_dsi_writel(dsi, max_threshold, DSI_MAX_THRESHOLD);
1086         tegra_dsi_writel(dsi, dcs_cmd, DSI_DCS_CMDS);
1087         tegra_dsi_writel(dsi, dsi_control, DSI_CONTROL);
1088         tegra_dsi_writel(dsi, host_dsi_control, DSI_HOST_DSI_CONTROL);
1089 }
1090
1091 static void tegra_dsi_pad_calibration(struct tegra_dc_dsi_data *dsi)
1092 {
1093         u32 val;
1094
1095         val =   DSI_PAD_CONTROL_PAD_LPUPADJ(0x1) |
1096                 DSI_PAD_CONTROL_PAD_LPDNADJ(0x1) |
1097                 DSI_PAD_CONTROL_PAD_PREEMP_EN(0x1) |
1098                 DSI_PAD_CONTROL_PAD_SLEWDNADJ(0x6) |
1099                 DSI_PAD_CONTROL_PAD_SLEWUPADJ(0x6);
1100         if (!dsi->ulpm) {
1101                 val |=  DSI_PAD_CONTROL_PAD_PDIO(0) |
1102                         DSI_PAD_CONTROL_PAD_PDIO_CLK(0) |
1103                         DSI_PAD_CONTROL_PAD_PULLDN_ENAB(TEGRA_DSI_DISABLE);
1104         } else {
1105                 val |=  DSI_PAD_CONTROL_PAD_PDIO(0x3) |
1106                         DSI_PAD_CONTROL_PAD_PDIO_CLK(0x1) |
1107                         DSI_PAD_CONTROL_PAD_PULLDN_ENAB(TEGRA_DSI_ENABLE);
1108         }
1109         tegra_dsi_writel(dsi, val, DSI_PAD_CONTROL);
1110
1111         val = MIPI_CAL_TERMOSA(0x4);
1112         tegra_vi_csi_writel(val, CSI_CILA_MIPI_CAL_CONFIG_0);
1113
1114         val = MIPI_CAL_TERMOSB(0x4);
1115         tegra_vi_csi_writel(val, CSI_CILB_MIPI_CAL_CONFIG_0);
1116
1117         val = MIPI_CAL_HSPUOSD(0x3) | MIPI_CAL_HSPDOSD(0x4);
1118         tegra_vi_csi_writel(val, CSI_DSI_MIPI_CAL_CONFIG);
1119
1120         val = PAD_DRIV_DN_REF(0x5) | PAD_DRIV_UP_REF(0x7);
1121         tegra_vi_csi_writel(val, CSI_MIPIBIAS_PAD_CONFIG);
1122 }
1123
1124 static int tegra_dsi_init_hw(struct tegra_dc *dc,
1125                                                 struct tegra_dc_dsi_data *dsi)
1126 {
1127         u32 val;
1128         u32 i;
1129
1130         val = DSI_POWER_CONTROL_LEG_DSI_ENABLE(TEGRA_DSI_DISABLE);
1131         tegra_dsi_writel(dsi, val, DSI_POWER_CONTROL);
1132
1133         tegra_dsi_set_dsi_clk(dc, dsi, dsi->target_lp_clk_khz);
1134         if (dsi->info.dsi_instance) {
1135                 /* TODO:Set the misc register*/
1136         }
1137
1138         /* TODO: only need to change the timing for bta */
1139         tegra_dsi_set_phy_timing(dsi);
1140
1141         if (dsi->status.dc_stream == DSI_DC_STREAM_ENABLE)
1142                 tegra_dsi_stop_dc_stream(dc, dsi);
1143
1144         /* Initializing DSI registers */
1145         for (i = 0; i < ARRAY_SIZE(init_reg); i++)
1146                 tegra_dsi_writel(dsi, 0, init_reg[i]);
1147
1148         tegra_dsi_writel(dsi, dsi->dsi_control_val, DSI_CONTROL);
1149
1150         tegra_dsi_pad_calibration(dsi);
1151
1152         val = DSI_POWER_CONTROL_LEG_DSI_ENABLE(TEGRA_DSI_ENABLE);
1153         tegra_dsi_writel(dsi, val, DSI_POWER_CONTROL);
1154
1155         while (tegra_dsi_readl(dsi, DSI_POWER_CONTROL) != val)
1156                 tegra_dsi_writel(dsi, val, DSI_POWER_CONTROL);
1157
1158         dsi->status.init = DSI_MODULE_INIT;
1159         dsi->status.lphs = DSI_LPHS_NOT_INIT;
1160         dsi->status.vtype = DSI_VIDEO_TYPE_NOT_INIT;
1161         dsi->status.driven = DSI_DRIVEN_MODE_NOT_INIT;
1162         dsi->status.clk_out = DSI_PHYCLK_OUT_DIS;
1163         dsi->status.clk_mode = DSI_PHYCLK_NOT_INIT;
1164         dsi->status.clk_burst = DSI_CLK_BURST_NOT_INIT;
1165         dsi->status.dc_stream = DSI_DC_STREAM_DISABLE;
1166         dsi->status.lp_op = DSI_LP_OP_NOT_INIT;
1167
1168         return 0;
1169 }
1170
1171 static int tegra_dsi_set_to_lp_mode(struct tegra_dc *dc,
1172                         struct tegra_dc_dsi_data *dsi, u8 lp_op)
1173 {
1174         int err;
1175
1176         if (dsi->status.init != DSI_MODULE_INIT) {
1177                 err = -EPERM;
1178                 goto fail;
1179         }
1180
1181         if (dsi->status.lphs == DSI_LPHS_IN_LP_MODE &&
1182                         dsi->status.lp_op == lp_op)
1183                 goto success;
1184
1185         if (dsi->status.dc_stream == DSI_DC_STREAM_ENABLE)
1186                 tegra_dsi_stop_dc_stream_at_frame_end(dc, dsi);
1187
1188         /* disable/enable hs clk according to enable_hs_clock_on_lp_cmd_mode */
1189         if ((dsi->status.clk_out == DSI_PHYCLK_OUT_EN) &&
1190                 (!dsi->info.enable_hs_clock_on_lp_cmd_mode))
1191                 tegra_dsi_hs_clk_out_disable(dc, dsi);
1192
1193         dsi->target_lp_clk_khz = tegra_dsi_get_lp_clk_rate(dsi, lp_op);
1194         if (dsi->current_dsi_clk_khz != dsi->target_lp_clk_khz) {
1195                 tegra_dsi_set_dsi_clk(dc, dsi, dsi->target_lp_clk_khz);
1196                 tegra_dsi_set_timeout(dsi);
1197         }
1198
1199         tegra_dsi_set_control_reg_lp(dsi);
1200
1201         if ((dsi->status.clk_out == DSI_PHYCLK_OUT_DIS) &&
1202                 (dsi->info.enable_hs_clock_on_lp_cmd_mode))
1203                 tegra_dsi_hs_clk_out_enable_in_lp(dsi);
1204
1205         dsi->status.lphs = DSI_LPHS_IN_LP_MODE;
1206         dsi->status.lp_op = lp_op;
1207 success:
1208         err = 0;
1209 fail:
1210         return err;
1211 }
1212
1213 static int tegra_dsi_set_to_hs_mode(struct tegra_dc *dc,
1214                                         struct tegra_dc_dsi_data *dsi)
1215 {
1216         int err;
1217
1218         if (dsi->status.init != DSI_MODULE_INIT) {
1219                 err = -EPERM;
1220                 goto fail;
1221         }
1222
1223         if (dsi->status.lphs == DSI_LPHS_IN_HS_MODE)
1224                 goto success;
1225
1226         if (dsi->status.dc_stream == DSI_DC_STREAM_ENABLE)
1227                 tegra_dsi_stop_dc_stream_at_frame_end(dc, dsi);
1228
1229         if ((dsi->status.clk_out == DSI_PHYCLK_OUT_EN) &&
1230                 (!dsi->info.enable_hs_clock_on_lp_cmd_mode))
1231                 tegra_dsi_hs_clk_out_disable(dc, dsi);
1232
1233         if (dsi->current_dsi_clk_khz != dsi->target_hs_clk_khz) {
1234                 tegra_dsi_set_dsi_clk(dc, dsi, dsi->target_hs_clk_khz);
1235                 tegra_dsi_set_timeout(dsi);
1236         }
1237
1238         tegra_dsi_set_phy_timing(dsi);
1239
1240         if (dsi->driven_mode == TEGRA_DSI_DRIVEN_BY_DC) {
1241                 tegra_dsi_set_pkt_seq(dc, dsi);
1242                 tegra_dsi_set_pkt_length(dc, dsi);
1243                 tegra_dsi_set_sol_delay(dc, dsi);
1244                 tegra_dsi_set_dc_clk(dc, dsi);
1245         }
1246
1247         tegra_dsi_set_control_reg_hs(dsi);
1248
1249         if (dsi->status.clk_out == DSI_PHYCLK_OUT_DIS)
1250                 tegra_dsi_hs_clk_out_enable(dsi);
1251
1252         dsi->status.lphs = DSI_LPHS_IN_HS_MODE;
1253 success:
1254         dsi->status.lp_op = DSI_LP_OP_NOT_INIT;
1255         err = 0;
1256 fail:
1257         return err;
1258 }
1259
1260 static bool tegra_dsi_is_controller_idle(struct tegra_dc_dsi_data *dsi)
1261 {
1262         u32 timeout = 0;
1263         bool retVal;
1264
1265         retVal = false;
1266         while (timeout <= DSI_MAX_COMMAND_DELAY_USEC) {
1267                 if (!tegra_dsi_readl(dsi, DSI_TRIGGER)) {
1268                         retVal = true;
1269                         break;
1270                 }
1271                 udelay(DSI_COMMAND_DELAY_STEPS_USEC);
1272                 timeout += DSI_COMMAND_DELAY_STEPS_USEC;
1273         }
1274
1275         return retVal;
1276 }
1277
1278 static int tegra_dsi_host_trigger(struct tegra_dc_dsi_data *dsi)
1279 {
1280         int status = 0;
1281
1282         if (tegra_dsi_readl(dsi, DSI_TRIGGER)) {
1283                 status = -EBUSY;
1284                 goto fail;
1285         }
1286
1287         tegra_dsi_writel(dsi,
1288                 DSI_TRIGGER_HOST_TRIGGER(TEGRA_DSI_ENABLE), DSI_TRIGGER);
1289
1290 #if DSI_USE_SYNC_POINTS
1291         status = tegra_dsi_syncpt(dsi);
1292         if (status < 0) {
1293                 printk(KERN_ERR "DSI syncpt for host trigger failed\n");
1294                 goto fail;
1295         }
1296 #else
1297         if (!tegra_dsi_is_controller_idle(dsi))
1298                 status = -EIO;
1299 #endif
1300
1301 fail:
1302         return status;
1303 }
1304
1305 static int _tegra_dsi_write_data(struct tegra_dc_dsi_data *dsi,
1306                                         u8 *pdata, u8 data_id, u16 data_len)
1307 {
1308         u8 virtual_channel;
1309         u8 *pval;
1310         u32 val;
1311         int err;
1312
1313         err = 0;
1314
1315         virtual_channel = dsi->info.virtual_channel <<
1316                                                 DSI_VIR_CHANNEL_BIT_POSITION;
1317
1318         /* always use hw for ecc */
1319         val = (virtual_channel | data_id) << 0 |
1320                         data_len << 8;
1321         tegra_dsi_writel(dsi, val, DSI_WR_DATA);
1322
1323         /* if pdata != NULL, pkt type is long pkt */
1324         if (pdata != NULL) {
1325                 while (data_len) {
1326                         if (data_len >= 4) {
1327                                 val = ((u32 *) pdata)[0];
1328                                 data_len -= 4;
1329                                 pdata += 4;
1330                         } else {
1331                                 val = 0;
1332                                 pval = (u8 *) &val;
1333                                 do
1334                                         *pval++ = *pdata++;
1335                                 while (--data_len);
1336                         }
1337                         tegra_dsi_writel(dsi, val, DSI_WR_DATA);
1338                 }
1339         }
1340
1341         err = tegra_dsi_host_trigger(dsi);
1342         if (err < 0)
1343                 printk(KERN_ERR "DSI host trigger failed\n");
1344
1345         return err;
1346 }
1347
1348 int tegra_dsi_write_data(struct tegra_dc *dc,
1349                         struct tegra_dc_dsi_data *dsi,
1350                         u8 *pdata, u8 data_id, u16 data_len)
1351 {
1352         bool switch_back_to_hs_mode;
1353         bool switch_back_to_dc_mode;
1354         int err;
1355
1356         err = 0;
1357         switch_back_to_hs_mode = false;
1358         switch_back_to_dc_mode = false;
1359
1360         if ((dsi->status.init != DSI_MODULE_INIT) ||
1361                 (dsi->status.lphs == DSI_LPHS_NOT_INIT) ||
1362                 (dsi->status.lp_op == DSI_LP_OP_NOT_INIT)) {
1363                 err = -EPERM;
1364                 goto fail;
1365         }
1366
1367         if (!tegra_dsi_is_controller_idle(dsi)) {
1368                 err = -EBUSY;
1369                 goto fail;
1370         }
1371
1372         err = 0;
1373
1374         if (dsi->status.lphs == DSI_LPHS_IN_HS_MODE) {
1375                 if (dsi->info.hs_cmd_mode_supported) {
1376                         if (dsi->status.driven == DSI_DRIVEN_MODE_DC) {
1377                                 dsi->driven_mode = TEGRA_DSI_DRIVEN_BY_HOST;
1378                                 tegra_dsi_set_to_hs_mode(dc, dsi);
1379                                 switch_back_to_dc_mode = true;
1380                         }
1381                 } else {
1382                         tegra_dsi_set_to_lp_mode(dc, dsi, DSI_LP_OP_WRITE);
1383                         switch_back_to_hs_mode = true;
1384                 }
1385         }
1386
1387         err = _tegra_dsi_write_data(dsi, pdata, data_id, data_len);
1388
1389
1390         if (switch_back_to_dc_mode)
1391                 dsi->driven_mode = TEGRA_DSI_DRIVEN_BY_DC;
1392         if (switch_back_to_dc_mode || switch_back_to_hs_mode)
1393                 tegra_dsi_set_to_hs_mode(dc, dsi);
1394
1395 fail:
1396         return err;
1397 }
1398 EXPORT_SYMBOL(tegra_dsi_write_data);
1399
1400 static int tegra_dsi_send_panel_cmd(struct tegra_dc *dc,
1401                                         struct tegra_dc_dsi_data *dsi,
1402                                         struct tegra_dsi_cmd *cmd,
1403                                         u32 n_cmd)
1404 {
1405         u32 i;
1406         int err;
1407
1408         err = 0;
1409         for (i = 0; i < n_cmd; i++) {
1410                 struct tegra_dsi_cmd *cur_cmd;
1411                 cur_cmd = &cmd[i];
1412
1413                 if (cur_cmd->cmd_type == TEGRA_DSI_DELAY_MS)
1414                         mdelay(cur_cmd->sp_len_dly.delay_ms);
1415                 else {
1416                         err = tegra_dsi_write_data(dc, dsi,
1417                                                 cur_cmd->pdata,
1418                                                 cur_cmd->data_id,
1419                                                 cur_cmd->sp_len_dly.data_len);
1420                         if (err < 0)
1421                                 break;
1422                 }
1423         }
1424         return err;
1425 }
1426
1427 static u8 get_8bit_ecc(u32 header)
1428 {
1429         char ecc_parity[24] = {
1430                 0x07, 0x0b, 0x0d, 0x0e, 0x13, 0x15, 0x16, 0x19,
1431                 0x1a, 0x1c, 0x23, 0x25, 0x26, 0x29, 0x2a, 0x2c,
1432                 0x31, 0x32, 0x34, 0x38, 0x1f, 0x2f, 0x37, 0x3b
1433         };
1434         u8 ecc_byte;
1435         int i;
1436
1437         ecc_byte = 0;
1438         for (i = 0; i < 24; i++)
1439                 ecc_byte ^= ((header >> i) & 1) ? ecc_parity[i] : 0x00;
1440
1441         return ecc_byte;
1442 }
1443
1444 /* This function is written to send DCS short write (1 parameter) only.
1445  * This means the cmd will contain only 1 byte of index and 1 byte of value.
1446  * The data type ID is fixed at 0x15 and the ECC is calculated based on the
1447  * data in pdata.
1448  * The command will be sent by hardware every frame.
1449  * pdata should contain both the index + value for each cmd.
1450  * data_len will be the total number of bytes in pdata.
1451  */
1452 int tegra_dsi_send_panel_short_cmd(struct tegra_dc *dc, u8 *pdata, u8 data_len)
1453 {
1454         u8 ecc8bits = 0, data_len_orig = 0;
1455         u32 val = 0, pkthdr = 0;
1456         int err = 0, count = 0;
1457         struct tegra_dc_dsi_data *dsi = tegra_dc_get_outdata(dc);
1458
1459         data_len_orig = data_len;
1460         if (pdata != NULL) {
1461                 while (data_len) {
1462                         if (data_len >= 2) {
1463                                 pkthdr = (CMD_SHORTW |
1464                                         (((u16 *)pdata)[0]) << 8 | 0x00 << 24);
1465                                 ecc8bits = get_8bit_ecc(pkthdr);
1466                                 val = (pkthdr | (ecc8bits << 24));
1467                                 data_len -= 2;
1468                                 pdata += 2;
1469                                 count++;
1470                         }
1471                         switch (count) {
1472                         case 1:
1473                                 tegra_dsi_writel(dsi, val, DSI_INIT_SEQ_DATA_0);
1474                                 break;
1475                         case 2:
1476                                 tegra_dsi_writel(dsi, val, DSI_INIT_SEQ_DATA_1);
1477                                 break;
1478                         case 3:
1479                                 tegra_dsi_writel(dsi, val, DSI_INIT_SEQ_DATA_2);
1480                                 break;
1481                         case 4:
1482                                 tegra_dsi_writel(dsi, val, DSI_INIT_SEQ_DATA_3);
1483                                 break;
1484                         case 5:
1485                                 tegra_dsi_writel(dsi, val, DSI_INIT_SEQ_DATA_4);
1486                                 break;
1487                         case 6:
1488                                 tegra_dsi_writel(dsi, val, DSI_INIT_SEQ_DATA_5);
1489                                 break;
1490                         case 7:
1491                                 tegra_dsi_writel(dsi, val, DSI_INIT_SEQ_DATA_6);
1492                                 break;
1493                         case 8:
1494                                 tegra_dsi_writel(dsi, val, DSI_INIT_SEQ_DATA_7);
1495                                 break;
1496                         default:
1497                                 err = 1;
1498                                 break;
1499                         }
1500                 }
1501         }
1502
1503         val = DSI_INIT_SEQ_CONTROL_DSI_FRAME_INIT_BYTE_COUNT(data_len_orig * 2)
1504                 | DSI_INIT_SEQ_CONTROL_DSI_SEND_INIT_SEQUENCE(1);
1505         tegra_dsi_writel(dsi, val, DSI_INIT_SEQ_CONTROL);
1506
1507         return err;
1508 }
1509 EXPORT_SYMBOL(tegra_dsi_send_panel_short_cmd);
1510
1511 static int tegra_dsi_bta(struct tegra_dc_dsi_data *dsi)
1512 {
1513         u32 val;
1514         u32 poll_time;
1515         int err;
1516
1517         poll_time = 0;
1518         err = 0;
1519
1520         val = tegra_dsi_readl(dsi, DSI_HOST_DSI_CONTROL);
1521         val |= DSI_HOST_DSI_CONTROL_IMM_BTA(TEGRA_DSI_ENABLE);
1522         tegra_dsi_writel(dsi, val, DSI_HOST_DSI_CONTROL);
1523
1524 #if DSI_USE_SYNC_POINTS
1525         /* FIXME: Workaround for nvhost_syncpt_read */
1526         dsi->syncpt_val = nvhost_syncpt_update_min(
1527                         &dsi->dc->ndev->host->syncpt, dsi->syncpt_id);
1528
1529         val = DSI_INCR_SYNCPT_COND(OP_DONE) |
1530                 DSI_INCR_SYNCPT_INDX(dsi->syncpt_id);
1531         tegra_dsi_writel(dsi, val, DSI_INCR_SYNCPT);
1532
1533         /* TODO: Use interrupt rather than polling */
1534         err = nvhost_syncpt_wait(&dsi->dc->ndev->host->syncpt,
1535                 dsi->syncpt_id, dsi->syncpt_val + 1);
1536         if (err < 0)
1537                 printk(KERN_ERR "DSI sync point failure\n");
1538         else
1539                 (dsi->syncpt_val)++;
1540 #else
1541         while (poll_time <  DSI_STATUS_POLLING_DURATION_USEC) {
1542                 val = tegra_dsi_readl(dsi, DSI_HOST_DSI_CONTROL);
1543                 val &= DSI_HOST_DSI_CONTROL_IMM_BTA(TEGRA_DSI_ENABLE);
1544                 if (!val)
1545                         break;
1546                 udelay(DSI_STATUS_POLLING_DELAY_USEC);
1547                 poll_time += DSI_STATUS_POLLING_DELAY_USEC;
1548         }
1549         if (poll_time > DSI_STATUS_POLLING_DURATION_USEC)
1550                 err = -EBUSY;
1551 #endif
1552
1553         return err;
1554 }
1555
1556 static void tegra_dsi_read_fifo(struct tegra_dc *dc,
1557                         struct tegra_dc_dsi_data *dsi,
1558                         u32 rd_fifo_cnt, u8 *read_fifo)
1559 {
1560         u32 val;
1561         u32 i;
1562
1563         /* Read data from FIFO */
1564         for (i = 0; i < rd_fifo_cnt; i++) {
1565                 val = tegra_dsi_readl(dsi, DSI_RD_DATA);
1566                 if (enable_read_debug)
1567                         printk(KERN_INFO "Read data[%d]: 0x%x\n", i, val);
1568                 memcpy(read_fifo, &val, 4);
1569                 read_fifo += 4;
1570         }
1571
1572         /* Make sure all the data is read from the FIFO */
1573         val = tegra_dsi_readl(dsi, DSI_STATUS);
1574         val &= DSI_STATUS_RD_FIFO_COUNT(0x1f);
1575         if (val)
1576                 dev_err(&dc->ndev->dev, "DSI FIFO_RD_CNT not zero"
1577                 " even after reading FIFO_RD_CNT words from read fifo\n");
1578 }
1579
1580 static int tegra_dsi_parse_read_response(struct tegra_dc *dc,
1581                                         u32 rd_fifo_cnt, u8 *read_fifo)
1582 {
1583         int err;
1584         u32 payload_size;
1585
1586         payload_size = 0;
1587         err = 0;
1588
1589         printk(KERN_INFO "escape sequence[0x%x]\n", read_fifo[0]);
1590         switch (read_fifo[4] & 0xff) {
1591         case GEN_LONG_RD_RES:
1592                 /* Fall through */
1593         case DCS_LONG_RD_RES:
1594                 payload_size = (read_fifo[5] |
1595                                 (read_fifo[6] << 8)) & 0xFFFF;
1596                 printk(KERN_INFO "Long read response Packet\n"
1597                                 "payload_size[0x%x]\n", payload_size);
1598                 break;
1599         case GEN_1_BYTE_SHORT_RD_RES:
1600                 /* Fall through */
1601         case DCS_1_BYTE_SHORT_RD_RES:
1602                 payload_size = 1;
1603                 printk(KERN_INFO "Short read response Packet\n"
1604                         "payload_size[0x%x]\n", payload_size);
1605                 break;
1606         case GEN_2_BYTE_SHORT_RD_RES:
1607                 /* Fall through */
1608         case DCS_2_BYTE_SHORT_RD_RES:
1609                 payload_size = 2;
1610                 printk(KERN_INFO "Short read response Packet\n"
1611                         "payload_size[0x%x]\n", payload_size);
1612                 break;
1613         case ACK_ERR_RES:
1614                 payload_size = 2;
1615                 printk(KERN_INFO "Acknowledge error report response\n"
1616                         "Packet payload_size[0x%x]\n", payload_size);
1617                 break;
1618         default:
1619                 /*reading from RD_FIFO_COUNT*/
1620                 printk(KERN_INFO "Invalid read response payload_size\n");
1621                 err = -EINVAL;
1622                 break;
1623         }
1624         return err;
1625 }
1626
1627 int tegra_dsi_read_data(struct tegra_dc *dc,
1628                                 struct tegra_dc_dsi_data *dsi,
1629                                 u32 max_ret_payload_size,
1630                                 u32 panel_reg_addr, u8 *read_data)
1631 {
1632         u32 val;
1633         int err;
1634         u32 poll_time;
1635         u32 rd_fifo_cnt;
1636         bool switch_back_to_hs_mode;
1637         bool restart_dc_stream;
1638         bool switch_back_to_dc_mode;
1639
1640         err = 0;
1641         switch_back_to_hs_mode = false;
1642         restart_dc_stream = false;
1643         switch_back_to_dc_mode = false;
1644
1645         if ((dsi->status.init != DSI_MODULE_INIT) ||
1646                 (dsi->status.lphs == DSI_LPHS_NOT_INIT) ||
1647                 (dsi->status.driven == DSI_DRIVEN_MODE_NOT_INIT)) {
1648                 err = -EPERM;
1649                 goto fail;
1650         }
1651
1652         tegra_dc_io_start(dc);
1653
1654         val = tegra_dsi_readl(dsi, DSI_STATUS);
1655         val &= DSI_STATUS_RD_FIFO_COUNT(0x1f);
1656         if (val) {
1657                 err = -EBUSY;
1658                 dev_err(&dc->ndev->dev, "DSI fifo count not zero\n");
1659                 goto fail;
1660         }
1661
1662         if (!tegra_dsi_is_controller_idle(dsi)) {
1663                 err = -EBUSY;
1664                 dev_err(&dc->ndev->dev, "DSI trigger bit is already set\n");
1665                 goto fail;
1666         }
1667
1668         val = tegra_dsi_readl(dsi, DSI_STATUS);
1669         val &= (DSI_STATUS_LB_OVERFLOW(0x1) | DSI_STATUS_LB_UNDERFLOW(0x1));
1670         if (val) {
1671                 dev_warn(&dc->ndev->dev, "Reset overflow/underflow\n");
1672                 val = tegra_dsi_readl(dsi, DSI_HOST_DSI_CONTROL);
1673                 val |= DSI_HOST_CONTROL_FIFO_STAT_RESET(0x1);
1674                 tegra_dsi_writel(dsi, val, DSI_HOST_DSI_CONTROL);
1675                 ndelay(200);
1676         }
1677
1678         if (dsi->status.lphs == DSI_LPHS_IN_HS_MODE) {
1679                 if (dsi->status.driven == DSI_DRIVEN_MODE_DC) {
1680                         if (dsi->status.dc_stream == DSI_DC_STREAM_ENABLE) {
1681                                 tegra_dsi_stop_dc_stream_at_frame_end(dc, dsi);
1682                                 restart_dc_stream = true;
1683                         }
1684                         dsi->driven_mode = TEGRA_DSI_DRIVEN_BY_HOST;
1685                         switch_back_to_dc_mode = true;
1686                         if (dsi->info.hs_cmd_mode_supported) {
1687                                 err = tegra_dsi_set_to_hs_mode(dc, dsi);
1688                                 if (err < 0) {
1689                                         dev_err(&dc->ndev->dev,
1690                                         "DSI failed to go to HS host driven mode\n");
1691                                         goto fail;
1692                                 }
1693                         }
1694                 }
1695                 if (!dsi->info.hs_cmd_mode_supported) {
1696                         err =
1697                         tegra_dsi_set_to_lp_mode(dc, dsi, DSI_LP_OP_WRITE);
1698                         if (err < 0) {
1699                                 dev_err(&dc->ndev->dev,
1700                                 "DSI failed to go to LP mode\n");
1701                                 goto fail;
1702                         }
1703                         switch_back_to_hs_mode = true;
1704                 }
1705         }
1706
1707         /* Set max return payload size in words */
1708         err = _tegra_dsi_write_data(dsi, NULL,
1709                 dsi_command_max_return_pkt_size,
1710                 max_ret_payload_size);
1711         if (err < 0) {
1712                 dev_err(&dc->ndev->dev,
1713                                 "DSI write failed\n");
1714                 goto fail;
1715         }
1716
1717         /* DCS to read given panel register */
1718         err = _tegra_dsi_write_data(dsi, NULL,
1719                 dsi_command_dcs_read_with_no_params,
1720                 panel_reg_addr);
1721         if (err < 0) {
1722                 dev_err(&dc->ndev->dev,
1723                                 "DSI write failed\n");
1724                 goto fail;
1725         }
1726
1727         if (dsi->status.lp_op == DSI_LP_OP_WRITE) {
1728                 err = tegra_dsi_set_to_lp_mode(dc, dsi, DSI_LP_OP_READ);
1729                 if (err < 0) {
1730                         dev_err(&dc->ndev->dev,
1731                         "DSI failed to go to LP mode\n");
1732                         goto fail;
1733                 }
1734         }
1735
1736         err = tegra_dsi_bta(dsi);
1737         if (err < 0) {
1738                 dev_err(&dc->ndev->dev,
1739                         "DSI IMM BTA timeout\n");
1740                 goto fail;
1741         }
1742
1743         poll_time = 0;
1744         while (poll_time <  DSI_DELAY_FOR_READ_FIFO) {
1745                 mdelay(1);
1746                 val = tegra_dsi_readl(dsi, DSI_STATUS);
1747                 rd_fifo_cnt = val & DSI_STATUS_RD_FIFO_COUNT(0x1f);
1748                 if (rd_fifo_cnt << 2 > DSI_READ_FIFO_DEPTH)
1749                         dev_err(&dc->ndev->dev,
1750                         "DSI RD_FIFO_CNT is greater than RD_FIFO_DEPTH\n");
1751                         break;
1752                 poll_time++;
1753         }
1754
1755         if (rd_fifo_cnt == 0) {
1756                 dev_info(&dc->ndev->dev,
1757                         "DSI RD_FIFO_CNT is zero\n");
1758                 err = -EINVAL;
1759                 goto fail;
1760         }
1761
1762         if (val & DSI_STATUS_LB_UNDERFLOW(0x1) ||
1763                 val & DSI_STATUS_LB_OVERFLOW(0x1)) {
1764                 dev_err(&dc->ndev->dev,
1765                         "DSI overflow/underflow error\n");
1766                 err = -EINVAL;
1767                 goto fail;
1768         }
1769
1770         tegra_dsi_read_fifo(dc, dsi, rd_fifo_cnt, read_data);
1771
1772         if (enable_read_debug)
1773                 err = tegra_dsi_parse_read_response
1774                                 (dc, rd_fifo_cnt, read_data);
1775 fail:
1776         if (switch_back_to_dc_mode)
1777                 dsi->driven_mode = TEGRA_DSI_DRIVEN_BY_DC;
1778         if (switch_back_to_dc_mode || switch_back_to_hs_mode)
1779                 tegra_dsi_set_to_hs_mode(dc, dsi);
1780         if (restart_dc_stream)
1781                 tegra_dsi_start_dc_stream(dc, dsi);
1782
1783         tegra_dc_io_end(dc);
1784
1785         return err;
1786 }
1787 EXPORT_SYMBOL(tegra_dsi_read_data);
1788
1789 static int tegra_dsi_enter_ulpm(struct tegra_dc_dsi_data *dsi)
1790 {
1791         u32 val;
1792         int ret;
1793
1794         ret = 0;
1795
1796         val = tegra_dsi_readl(dsi, DSI_HOST_DSI_CONTROL);
1797         val &= ~DSI_HOST_DSI_CONTROL_ULTRA_LOW_POWER(3);
1798         val |= DSI_HOST_DSI_CONTROL_ULTRA_LOW_POWER(ENTER_ULPM);
1799         tegra_dsi_writel(dsi, val, DSI_HOST_DSI_CONTROL);
1800
1801 #if DSI_USE_SYNC_POINTS
1802         ret = tegra_dsi_syncpt(dsi);
1803         if (ret < 0) {
1804                 printk(KERN_ERR "DSI syncpt for ulpm enter failed\n");
1805                 goto fail;
1806         }
1807 #else
1808         /* TODO: Find exact delay required */
1809         mdelay(10);
1810 #endif
1811         dsi->ulpm = true;
1812 fail:
1813         return ret;
1814 }
1815
1816 static int tegra_dsi_exit_ulpm(struct tegra_dc_dsi_data *dsi)
1817 {
1818         u32 val;
1819         int ret;
1820
1821         ret = 0;
1822
1823         val = tegra_dsi_readl(dsi, DSI_HOST_DSI_CONTROL);
1824         val &= ~DSI_HOST_DSI_CONTROL_ULTRA_LOW_POWER(3);
1825         val |= DSI_HOST_DSI_CONTROL_ULTRA_LOW_POWER(EXIT_ULPM);
1826         tegra_dsi_writel(dsi, val, DSI_HOST_DSI_CONTROL);
1827
1828 #if DSI_USE_SYNC_POINTS
1829         ret = tegra_dsi_syncpt(dsi);
1830         if (ret < 0) {
1831                 printk(KERN_ERR "DSI syncpt for ulpm exit failed\n");
1832                 goto fail;
1833         }
1834 #else
1835         /* TODO: Find exact delay required */
1836         mdelay(10);
1837 #endif
1838         dsi->ulpm = false;
1839
1840         val = tegra_dsi_readl(dsi, DSI_HOST_DSI_CONTROL);
1841         val &= ~DSI_HOST_DSI_CONTROL_ULTRA_LOW_POWER(0x3);
1842         val |= DSI_HOST_DSI_CONTROL_ULTRA_LOW_POWER(NORMAL);
1843         tegra_dsi_writel(dsi, val, DSI_HOST_DSI_CONTROL);
1844 fail:
1845         return ret;
1846
1847 }
1848
1849 static void tegra_dc_dsi_enable(struct tegra_dc *dc)
1850 {
1851         struct tegra_dc_dsi_data *dsi = tegra_dc_get_outdata(dc);
1852         int err;
1853         u32 val;
1854
1855         tegra_dc_io_start(dc);
1856         mutex_lock(&dsi->lock);
1857
1858         /* Stop DC stream before configuring DSI registers
1859          * to avoid visible glitches on panel during transition
1860          * from bootloader to kernel driver
1861          */
1862         tegra_dsi_stop_dc_stream_at_frame_end(dc, dsi);
1863
1864         if (dsi->enabled) {
1865                 if (dsi->ulpm) {
1866                         if (tegra_dsi_exit_ulpm(dsi) < 0) {
1867                                 printk(KERN_ERR "DSI failed to exit ulpm\n");
1868                                 goto fail;
1869                         }
1870                 }
1871
1872                 if (dsi->info.panel_reset) {
1873                         err = tegra_dsi_send_panel_cmd(dc, dsi,
1874                                                         dsi->info.dsi_init_cmd,
1875                                                         dsi->info.n_init_cmd);
1876                         if (err < 0) {
1877                                 dev_err(&dc->ndev->dev,
1878                                 "dsi: error sending dsi init cmd\n");
1879                                 goto fail;
1880                         }
1881                 } else if (dsi->info.dsi_late_resume_cmd) {
1882                         err = tegra_dsi_send_panel_cmd(dc, dsi,
1883                                                 dsi->info.dsi_late_resume_cmd,
1884                                                 dsi->info.n_late_resume_cmd);
1885                         if (err < 0) {
1886                                 dev_err(&dc->ndev->dev,
1887                                 "dsi: error sending late resume cmd\n");
1888                                 goto fail;
1889                         }
1890                 }
1891         } else {
1892                 err = tegra_dsi_init_hw(dc, dsi);
1893                 if (err < 0) {
1894                         dev_err(&dc->ndev->dev,
1895                                 "dsi: not able to init dsi hardware\n");
1896                         goto fail;
1897                 }
1898
1899                 if (dsi->ulpm) {
1900                         if (tegra_dsi_enter_ulpm(dsi) < 0) {
1901                                 printk(KERN_ERR "DSI failed to enter ulpm\n");
1902                                 goto fail;
1903                         }
1904                         val = DSI_PAD_CONTROL_PAD_PDIO(0) |
1905                                 DSI_PAD_CONTROL_PAD_PDIO_CLK(0) |
1906                                 DSI_PAD_CONTROL_PAD_PULLDN_ENAB
1907                                                 (TEGRA_DSI_DISABLE);
1908                         tegra_dsi_writel(dsi, val, DSI_PAD_CONTROL);
1909                         if (tegra_dsi_exit_ulpm(dsi) < 0) {
1910                                 printk(KERN_ERR "DSI failed to exit ulpm\n");
1911                                 goto fail;
1912                         }
1913                 }
1914
1915                 err = tegra_dsi_set_to_lp_mode(dc, dsi, DSI_LP_OP_WRITE);
1916                 if (err < 0) {
1917                         dev_err(&dc->ndev->dev,
1918                                 "dsi: not able to set to lp mode\n");
1919                         goto fail;
1920                 }
1921
1922                 err = tegra_dsi_send_panel_cmd(dc, dsi, dsi->info.dsi_init_cmd,
1923                                                 dsi->info.n_init_cmd);
1924                 if (err < 0) {
1925                         dev_err(&dc->ndev->dev,
1926                                 "dsi: error while sending dsi init cmd\n");
1927                         goto fail;
1928                 }
1929
1930                 err = tegra_dsi_set_to_hs_mode(dc, dsi);
1931                 if (err < 0) {
1932                         dev_err(&dc->ndev->dev,
1933                                 "dsi: not able to set to hs mode\n");
1934                         goto fail;
1935                 }
1936
1937                 dsi->enabled = true;
1938         }
1939
1940         if (dsi->status.driven == DSI_DRIVEN_MODE_DC)
1941                 tegra_dsi_start_dc_stream(dc, dsi);
1942 fail:
1943         mutex_unlock(&dsi->lock);
1944         tegra_dc_io_end(dc);
1945 }
1946
1947 static void _tegra_dc_dsi_init(struct tegra_dc *dc)
1948 {
1949         struct tegra_dc_dsi_data *dsi = tegra_dc_get_outdata(dc);
1950
1951         tegra_dsi_init_sw(dc, dsi);
1952         /* TODO: Configure the CSI pad configuration */
1953 }
1954
1955 static int tegra_dc_dsi_cp_p_cmd(struct tegra_dsi_cmd *src,
1956                                         struct tegra_dsi_cmd *dst, u16 n_cmd)
1957 {
1958         u16 i;
1959         u16 len;
1960
1961         memcpy(dst, src, sizeof(*dst) * n_cmd);
1962
1963         for (i = 0; i < n_cmd; i++)
1964                 if (src[i].pdata) {
1965                         len = sizeof(*src[i].pdata) *
1966                                         src[i].sp_len_dly.data_len;
1967                         dst[i].pdata = kzalloc(len, GFP_KERNEL);
1968                         if (!dst[i].pdata)
1969                                 goto free_cmd_pdata;
1970                         memcpy(dst[i].pdata, src[i].pdata, len);
1971                 }
1972
1973         return 0;
1974
1975 free_cmd_pdata:
1976         for (--i; i >= 0; i--)
1977                 if (dst[i].pdata)
1978                         kfree(dst[i].pdata);
1979         return -ENOMEM;
1980 }
1981
1982 static int tegra_dc_dsi_cp_info(struct tegra_dc_dsi_data *dsi,
1983                                         struct tegra_dsi_out *p_dsi)
1984 {
1985         struct tegra_dsi_cmd *p_init_cmd;
1986         struct tegra_dsi_cmd *p_early_suspend_cmd;
1987         struct tegra_dsi_cmd *p_late_resume_cmd;
1988         struct tegra_dsi_cmd *p_suspend_cmd;
1989         int err;
1990
1991         if (p_dsi->n_data_lanes > MAX_DSI_DATA_LANES)
1992                 return -EINVAL;
1993
1994         p_init_cmd = kzalloc(sizeof(*p_init_cmd) *
1995                                 p_dsi->n_init_cmd, GFP_KERNEL);
1996         if (!p_init_cmd)
1997                 return -ENOMEM;
1998
1999         if (p_dsi->dsi_early_suspend_cmd) {
2000                 p_early_suspend_cmd = kzalloc(sizeof(*p_early_suspend_cmd) *
2001                                         p_dsi->n_early_suspend_cmd,
2002                                         GFP_KERNEL);
2003                 if (!p_early_suspend_cmd) {
2004                         err = -ENOMEM;
2005                         goto err_free_init_cmd;
2006                 }
2007         }
2008
2009         if (p_dsi->dsi_late_resume_cmd) {
2010                 p_late_resume_cmd = kzalloc(sizeof(*p_late_resume_cmd) *
2011                                         p_dsi->n_late_resume_cmd,
2012                                         GFP_KERNEL);
2013                 if (!p_late_resume_cmd) {
2014                         err = -ENOMEM;
2015                         goto err_free_p_early_suspend_cmd;
2016                 }
2017         }
2018
2019         p_suspend_cmd = kzalloc(sizeof(*p_suspend_cmd) * p_dsi->n_suspend_cmd,
2020                                 GFP_KERNEL);
2021         if (!p_suspend_cmd) {
2022                 err = -ENOMEM;
2023                 goto err_free_p_late_resume_cmd;
2024         }
2025
2026         memcpy(&dsi->info, p_dsi, sizeof(dsi->info));
2027
2028         /* Copy panel init cmd */
2029         err = tegra_dc_dsi_cp_p_cmd(p_dsi->dsi_init_cmd,
2030                                                 p_init_cmd, p_dsi->n_init_cmd);
2031         if (err < 0)
2032                 goto err_free;
2033         dsi->info.dsi_init_cmd = p_init_cmd;
2034
2035         /* Copy panel early suspend cmd */
2036         if (p_dsi->dsi_early_suspend_cmd) {
2037                 err = tegra_dc_dsi_cp_p_cmd(p_dsi->dsi_early_suspend_cmd,
2038                                         p_early_suspend_cmd,
2039                                         p_dsi->n_early_suspend_cmd);
2040                 if (err < 0)
2041                         goto err_free;
2042                 dsi->info.dsi_early_suspend_cmd = p_early_suspend_cmd;
2043         }
2044
2045         /* Copy panel late resume cmd */
2046         if (p_dsi->dsi_late_resume_cmd) {
2047                 err = tegra_dc_dsi_cp_p_cmd(p_dsi->dsi_late_resume_cmd,
2048                                                 p_late_resume_cmd,
2049                                                 p_dsi->n_late_resume_cmd);
2050                 if (err < 0)
2051                         goto err_free;
2052                 dsi->info.dsi_late_resume_cmd = p_late_resume_cmd;
2053         }
2054
2055         /* Copy panel suspend cmd */
2056         err = tegra_dc_dsi_cp_p_cmd(p_dsi->dsi_suspend_cmd, p_suspend_cmd,
2057                                         p_dsi->n_suspend_cmd);
2058         if (err < 0)
2059                 goto err_free;
2060         dsi->info.dsi_suspend_cmd = p_suspend_cmd;
2061
2062         if (!dsi->info.panel_reset_timeout_msec)
2063                 dsi->info.panel_reset_timeout_msec =
2064                                                 DEFAULT_PANEL_RESET_TIMEOUT;
2065
2066         if (!dsi->info.panel_buffer_size_byte)
2067                 dsi->info.panel_buffer_size_byte = DEFAULT_PANEL_BUFFER_BYTE;
2068
2069         if (!dsi->info.max_panel_freq_khz) {
2070                 dsi->info.max_panel_freq_khz = DEFAULT_MAX_DSI_PHY_CLK_KHZ;
2071
2072                 if (dsi->info.video_burst_mode >
2073                                 TEGRA_DSI_VIDEO_NONE_BURST_MODE_WITH_SYNC_END){
2074                         dev_err(&dsi->dc->ndev->dev, "DSI: max_panel_freq_khz"
2075                                         "is not set for DSI burst mode.\n");
2076                         dsi->info.video_burst_mode =
2077                                 TEGRA_DSI_VIDEO_BURST_MODE_LOWEST_SPEED;
2078                 }
2079         }
2080
2081         if (!dsi->info.lp_cmd_mode_freq_khz)
2082                 dsi->info.lp_cmd_mode_freq_khz = DEFAULT_LP_CMD_MODE_CLK_KHZ;
2083
2084         if (!dsi->info.chip_id || !dsi->info.chip_rev)
2085                 printk(KERN_WARNING "DSI: Failed to get chip info\n");
2086
2087         if (!dsi->info.lp_read_cmd_mode_freq_khz)
2088                 dsi->info.lp_read_cmd_mode_freq_khz =
2089                         dsi->info.lp_cmd_mode_freq_khz;
2090
2091         /* host mode is for testing only */
2092         dsi->driven_mode = TEGRA_DSI_DRIVEN_BY_DC;
2093         return 0;
2094
2095 err_free:
2096         kfree(p_suspend_cmd);
2097 err_free_p_late_resume_cmd:
2098         kfree(p_late_resume_cmd);
2099 err_free_p_early_suspend_cmd:
2100         kfree(p_early_suspend_cmd);
2101 err_free_init_cmd:
2102         kfree(p_init_cmd);
2103         return err;
2104 }
2105
2106 static int tegra_dc_dsi_init(struct tegra_dc *dc)
2107 {
2108         struct tegra_dc_dsi_data *dsi;
2109         struct resource *res;
2110         struct resource *base_res;
2111         void __iomem *base;
2112         struct clk *dc_clk = NULL;
2113         struct clk *dsi_clk = NULL;
2114         struct tegra_dsi_out *dsi_pdata;
2115         int err;
2116
2117         err = 0;
2118
2119         dsi = kzalloc(sizeof(*dsi), GFP_KERNEL);
2120         if (!dsi)
2121                 return -ENOMEM;
2122
2123         res = nvhost_get_resource_byname(dc->ndev, IORESOURCE_MEM,
2124                                         "dsi_regs");
2125         if (!res) {
2126                 dev_err(&dc->ndev->dev, "dsi: no mem resource\n");
2127                 err = -ENOENT;
2128                 goto err_free_dsi;
2129         }
2130
2131         base_res = request_mem_region(res->start, resource_size(res),
2132                                 dc->ndev->name);
2133         if (!base_res) {
2134                 dev_err(&dc->ndev->dev, "dsi: request_mem_region failed\n");
2135                 err = -EBUSY;
2136                 goto err_free_dsi;
2137         }
2138
2139         base = ioremap(res->start, resource_size(res));
2140         if (!base) {
2141                 dev_err(&dc->ndev->dev, "dsi: registers can't be mapped\n");
2142                 err = -EBUSY;
2143                 goto err_release_regs;
2144         }
2145
2146         dsi_pdata = dc->pdata->default_out->dsi;
2147         if (!dsi_pdata) {
2148                 dev_err(&dc->ndev->dev, "dsi: dsi data not available\n");
2149                 goto err_release_regs;
2150         }
2151
2152         if (dsi_pdata->dsi_instance)
2153                 dsi_clk = clk_get(&dc->ndev->dev, "dsib");
2154         else
2155                 dsi_clk = clk_get(&dc->ndev->dev, "dsia");
2156
2157         if (IS_ERR_OR_NULL(dsi_clk)) {
2158                 dev_err(&dc->ndev->dev, "dsi: can't get clock\n");
2159                 err = -EBUSY;
2160                 goto err_release_regs;
2161         }
2162
2163         dc_clk = clk_get_sys(dev_name(&dc->ndev->dev), NULL);
2164         if (IS_ERR_OR_NULL(dc_clk)) {
2165                 dev_err(&dc->ndev->dev, "dsi: dc clock %s unavailable\n",
2166                         dev_name(&dc->ndev->dev));
2167                 err = -EBUSY;
2168                 goto err_clk_put;
2169         }
2170
2171         mutex_init(&dsi->lock);
2172         dsi->dc = dc;
2173         dsi->base = base;
2174         dsi->base_res = base_res;
2175         dsi->dc_clk = dc_clk;
2176         dsi->dsi_clk = dsi_clk;
2177
2178         err = tegra_dc_dsi_cp_info(dsi, dsi_pdata);
2179         if (err < 0)
2180                 goto err_dsi_data;
2181
2182         tegra_dc_set_outdata(dc, dsi);
2183         _tegra_dc_dsi_init(dc);
2184
2185         return 0;
2186
2187 err_dsi_data:
2188 err_clk_put:
2189         clk_put(dsi_clk);
2190 err_release_regs:
2191         release_resource(base_res);
2192 err_free_dsi:
2193         kfree(dsi);
2194
2195         return err;
2196 }
2197
2198 static void tegra_dc_dsi_destroy(struct tegra_dc *dc)
2199 {
2200         struct tegra_dc_dsi_data *dsi = tegra_dc_get_outdata(dc);
2201         u16 i;
2202         u32 val;
2203
2204         mutex_lock(&dsi->lock);
2205
2206         /* free up the pdata */
2207         for (i = 0; i < dsi->info.n_init_cmd; i++) {
2208                 if (dsi->info.dsi_init_cmd[i].pdata)
2209                         kfree(dsi->info.dsi_init_cmd[i].pdata);
2210         }
2211         kfree(dsi->info.dsi_init_cmd);
2212
2213         /* Disable dc stream */
2214         if (dsi->status.dc_stream == DSI_DC_STREAM_ENABLE)
2215                 tegra_dsi_stop_dc_stream(dc, dsi);
2216
2217         /* Disable dsi phy clock */
2218         if (dsi->status.clk_out == DSI_PHYCLK_OUT_EN)
2219                 tegra_dsi_hs_clk_out_disable(dc, dsi);
2220
2221         val = DSI_POWER_CONTROL_LEG_DSI_ENABLE(TEGRA_DSI_DISABLE);
2222         tegra_dsi_writel(dsi, val, DSI_POWER_CONTROL);
2223
2224         iounmap(dsi->base);
2225         release_resource(dsi->base_res);
2226
2227         clk_put(dsi->dc_clk);
2228         clk_put(dsi->dsi_clk);
2229
2230         mutex_unlock(&dsi->lock);
2231
2232         mutex_destroy(&dsi->lock);
2233         kfree(dsi);
2234 }
2235
2236 static int tegra_dsi_deep_sleep(struct tegra_dc *dc,
2237                                 struct tegra_dc_dsi_data *dsi)
2238 {
2239         int err = 0;
2240         int val;
2241         struct clk *parent_clk = NULL;
2242         struct clk *base_clk = NULL;
2243
2244         if (!dsi->enabled) {
2245                 err = -EPERM;
2246                 goto fail;
2247         }
2248
2249         err = tegra_dsi_set_to_lp_mode(dc, dsi, DSI_LP_OP_WRITE);
2250         if (err < 0) {
2251                 dev_err(&dc->ndev->dev,
2252                 "DSI failed to go to LP mode\n");
2253                 goto fail;
2254         }
2255
2256         /* Suspend panel */
2257         err = tegra_dsi_send_panel_cmd(dc, dsi,
2258                         dsi->info.dsi_suspend_cmd,
2259                         dsi->info.n_suspend_cmd);
2260         if (err < 0) {
2261                 dev_err(&dc->ndev->dev,
2262                         "dsi: Error sending suspend cmd\n");
2263                 goto fail;
2264         }
2265
2266         if (!dsi->ulpm) {
2267                 err = tegra_dsi_enter_ulpm(dsi);
2268                 if (err < 0) {
2269                         dev_err(&dc->ndev->dev,
2270                                 "DSI failed to enter ulpm\n");
2271                         goto fail;
2272                 }
2273         }
2274
2275         /* Suspend pad */
2276         val = tegra_dsi_readl(dsi, DSI_PAD_CONTROL);
2277         val = DSI_PAD_CONTROL_PAD_PDIO(0x3) |
2278                 DSI_PAD_CONTROL_PAD_PDIO_CLK(0x1) |
2279                 DSI_PAD_CONTROL_PAD_PULLDN_ENAB(TEGRA_DSI_ENABLE);
2280         tegra_dsi_writel(dsi, val, DSI_PAD_CONTROL);
2281
2282         /* Suspend core-logic */
2283         val = DSI_POWER_CONTROL_LEG_DSI_ENABLE(TEGRA_DSI_DISABLE);
2284         tegra_dsi_writel(dsi, val, DSI_POWER_CONTROL);
2285
2286         /* Disable dsi fast and slow clock */
2287         parent_clk = clk_get_parent(dsi->dsi_clk);
2288         base_clk = clk_get_parent(parent_clk);
2289         if (dsi->info.dsi_instance)
2290                 tegra_clk_cfg_ex(base_clk,
2291                                 TEGRA_CLK_PLLD_CSI_OUT_ENB,
2292                                 0);
2293         else
2294                 tegra_clk_cfg_ex(base_clk,
2295                                 TEGRA_CLK_PLLD_DSI_OUT_ENB,
2296                                 0);
2297
2298         /* Disable dsi source clock */
2299         clk_disable(dsi->dsi_clk);
2300
2301         dsi->clk_ref = false;
2302         dsi->enabled = false;
2303
2304         return 0;
2305 fail:
2306         return err;
2307 }
2308
2309 static void tegra_dc_dsi_disable(struct tegra_dc *dc)
2310 {
2311         int err;
2312         struct tegra_dc_dsi_data *dsi = tegra_dc_get_outdata(dc);
2313
2314         tegra_dc_io_start(dc);
2315         mutex_lock(&dsi->lock);
2316
2317         if (dsi->status.dc_stream == DSI_DC_STREAM_ENABLE)
2318                 tegra_dsi_stop_dc_stream_at_frame_end(dc, dsi);
2319
2320         if (dsi->info.power_saving_suspend) {
2321                 if (tegra_dsi_deep_sleep(dc, dsi) < 0) {
2322                         printk(KERN_ERR "DSI failed to enter deep sleep\n");
2323                         goto fail;
2324                 }
2325         } else {
2326                 if (dsi->info.dsi_early_suspend_cmd) {
2327                         err = tegra_dsi_send_panel_cmd(dc, dsi,
2328                                 dsi->info.dsi_early_suspend_cmd,
2329                                 dsi->info.n_early_suspend_cmd);
2330                         if (err < 0) {
2331                                 dev_err(&dc->ndev->dev,
2332                                 "dsi: Error sending early suspend cmd\n");
2333                                 goto fail;
2334                         }
2335                 }
2336
2337                 if (!dsi->ulpm) {
2338                         if (tegra_dsi_enter_ulpm(dsi) < 0) {
2339                                 printk(KERN_ERR "DSI failed to enter ulpm\n");
2340                                 goto fail;
2341                         }
2342                 }
2343         }
2344
2345 fail:
2346         mutex_unlock(&dsi->lock);
2347         tegra_dc_io_end(dc);
2348 }
2349
2350 #ifdef CONFIG_PM
2351 static void tegra_dc_dsi_suspend(struct tegra_dc *dc)
2352 {
2353         struct tegra_dc_dsi_data *dsi;
2354
2355         dsi = tegra_dc_get_outdata(dc);
2356
2357         tegra_dc_io_start(dc);
2358         mutex_lock(&dsi->lock);
2359
2360         if (!dsi->enabled)
2361                 goto fail;
2362
2363         if (!dsi->info.power_saving_suspend) {
2364                 if (dsi->ulpm) {
2365                         if (tegra_dsi_exit_ulpm(dsi) < 0) {
2366                                 printk(KERN_ERR "DSI failed to exit ulpm");
2367                                 goto fail;
2368                         }
2369                 }
2370
2371                 if (tegra_dsi_deep_sleep(dc, dsi) < 0) {
2372                         printk(KERN_ERR "DSI failed to enter deep sleep\n");
2373                         goto fail;
2374                 }
2375         }
2376 fail:
2377         mutex_unlock(&dsi->lock);
2378         tegra_dc_io_end(dc);
2379 }
2380
2381 static void tegra_dc_dsi_resume(struct tegra_dc *dc)
2382 {
2383         /* Not required since tegra_dc_dsi_enable
2384          * will reconfigure the controller from scratch
2385          */
2386 }
2387 #endif
2388
2389 struct tegra_dc_out_ops tegra_dc_dsi_ops = {
2390         .init = tegra_dc_dsi_init,
2391         .destroy = tegra_dc_dsi_destroy,
2392         .enable = tegra_dc_dsi_enable,
2393         .disable = tegra_dc_dsi_disable,
2394 #ifdef CONFIG_PM
2395         .suspend = tegra_dc_dsi_suspend,
2396         .resume = tegra_dc_dsi_resume,
2397 #endif
2398 };