video: dsi: tegra: Stop dc stream before configuring dsi
[linux-2.6.git] / drivers / video / tegra / dc / dsi.c
1 /*
2  * drivers/video/tegra/dc/dsi.c
3  *
4  * Copyright (c) 2011, NVIDIA Corporation.
5  *
6  * This software is licensed under the terms of the GNU General Public
7  * License version 2, as published by the Free Software Foundation, and
8  * may be copied, distributed, and modified under those terms.
9  *
10  * This program is distributed in the hope that it will be useful,
11  * but WITHOUT ANY WARRANTY; without even the implied warranty of
12  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
13  * GNU General Public License for more details.
14  *
15  */
16
17 #include <linux/clk.h>
18 #include <linux/delay.h>
19 #include <linux/err.h>
20 #include <linux/fb.h>
21 #include <linux/gpio.h>
22 #include <linux/interrupt.h>
23 #include <linux/kernel.h>
24 #include <linux/slab.h>
25 #include <linux/spinlock.h>
26 #include <linux/workqueue.h>
27
28 #include <mach/clk.h>
29 #include <mach/dc.h>
30 #include <mach/fb.h>
31 #include <mach/nvhost.h>
32 #include <../gpio-names.h>
33
34 #include "dc_reg.h"
35 #include "dc_priv.h"
36 #include "dsi_regs.h"
37 #include "dsi.h"
38
39 #define DSI_USE_SYNC_POINTS 1
40
41 #define DSI_STOP_DC_DURATION_MSEC 1000
42
43 #define DSI_MODULE_NOT_INIT             0x0
44 #define DSI_MODULE_INIT                 0x1
45
46 #define DSI_LPHS_NOT_INIT               0x0
47 #define DSI_LPHS_IN_LP_MODE             0x1
48 #define DSI_LPHS_IN_HS_MODE             0x2
49
50 #define DSI_VIDEO_TYPE_NOT_INIT         0x0
51 #define DSI_VIDEO_TYPE_VIDEO_MODE       0x1
52 #define DSI_VIDEO_TYPE_CMD_MODE         0x2
53
54 #define DSI_DRIVEN_MODE_NOT_INIT        0x0
55 #define DSI_DRIVEN_MODE_DC              0x1
56 #define DSI_DRIVEN_MODE_HOST            0x2
57
58 #define DSI_PHYCLK_OUT_DIS              0x0
59 #define DSI_PHYCLK_OUT_EN               0x1
60
61 #define DSI_PHYCLK_NOT_INIT             0x0
62 #define DSI_PHYCLK_CONTINUOUS           0x1
63 #define DSI_PHYCLK_TX_ONLY              0x2
64
65 #define DSI_CLK_BURST_NOT_INIT          0x0
66 #define DSI_CLK_BURST_NONE_BURST        0x1
67 #define DSI_CLK_BURST_BURST_MODE        0x2
68
69 #define DSI_DC_STREAM_DISABLE           0x0
70 #define DSI_DC_STREAM_ENABLE            0x1
71
72 struct dsi_status {
73         unsigned        init:2;
74
75         unsigned        lphs:2;
76
77         unsigned        vtype:2;
78         unsigned        driven:2;
79
80         unsigned        clk_out:2;
81         unsigned        clk_mode:2;
82         unsigned        clk_burst:2;
83
84         unsigned        dc_stream:1;
85 };
86
87 /* source of video data */
88 enum{
89         TEGRA_DSI_DRIVEN_BY_DC,
90         TEGRA_DSI_DRIVEN_BY_HOST,
91 };
92
93 struct tegra_dc_dsi_data {
94         struct tegra_dc *dc;
95         void __iomem    *base;
96         struct resource *base_res;
97
98         struct clk              *dc_clk;
99         struct clk              *dsi_clk;
100
101         struct mutex    lock;
102
103         /* data from board info */
104         struct tegra_dsi_out info;
105
106         struct dsi_status       status;
107
108         u8              driven_mode;
109         u8              controller_index;
110
111         u8              pixel_scaler_mul;
112         u8              pixel_scaler_div;
113
114         u32             default_pixel_clk_khz;
115         u32             default_hs_clk_khz;
116
117         u32             target_hs_clk_khz;
118         u32             target_lp_clk_khz;
119
120         u32             syncpt_id;
121         u32             syncpt_val;
122
123         u16             current_bit_clk_ns;
124         u32             current_dsi_clk_khz;
125
126         u32             dsi_control_val;
127
128         bool            ulpm;
129 };
130
131 const u32 dsi_pkt_seq_reg[NUMOF_PKT_SEQ] = {
132         DSI_PKT_SEQ_0_LO,
133         DSI_PKT_SEQ_0_HI,
134         DSI_PKT_SEQ_1_LO,
135         DSI_PKT_SEQ_1_HI,
136         DSI_PKT_SEQ_2_LO,
137         DSI_PKT_SEQ_2_HI,
138         DSI_PKT_SEQ_3_LO,
139         DSI_PKT_SEQ_3_HI,
140         DSI_PKT_SEQ_4_LO,
141         DSI_PKT_SEQ_4_HI,
142         DSI_PKT_SEQ_5_LO,
143         DSI_PKT_SEQ_5_HI,
144 };
145
146 const u32 dsi_pkt_seq_video_non_burst_syne[NUMOF_PKT_SEQ] = {
147         PKT_ID0(CMD_VS) | PKT_LEN0(0) | PKT_ID1(CMD_EOT) | PKT_LEN1(0) | PKT_LP,
148         0,
149         PKT_ID0(CMD_VE) | PKT_LEN0(0) | PKT_ID1(CMD_EOT) | PKT_LEN1(0) | PKT_LP,
150         0,
151         PKT_ID0(CMD_HS) | PKT_LEN0(0) | PKT_ID1(CMD_EOT) | PKT_LEN1(0) | PKT_LP,
152         0,
153         PKT_ID0(CMD_HS) | PKT_LEN0(0) | PKT_ID1(CMD_BLNK) | PKT_LEN1(1) |
154                 PKT_ID2(CMD_HE) | PKT_LEN2(0),
155         PKT_ID3(CMD_BLNK) | PKT_LEN3(2) | PKT_ID4(CMD_RGB) | PKT_LEN4(3) |
156                 PKT_ID5(CMD_BLNK) | PKT_LEN5(4),
157         PKT_ID0(CMD_HS) | PKT_LEN0(0) | PKT_ID1(CMD_EOT) | PKT_LEN1(0) | PKT_LP,
158         0,
159         PKT_ID0(CMD_HS) | PKT_LEN0(0) | PKT_ID1(CMD_BLNK) | PKT_LEN1(1) |
160                 PKT_ID2(CMD_HE) | PKT_LEN2(0),
161         PKT_ID3(CMD_BLNK) | PKT_LEN3(2) | PKT_ID4(CMD_RGB) | PKT_LEN4(3) |
162                 PKT_ID5(CMD_BLNK) | PKT_LEN5(4),
163 };
164
165 const u32 dsi_pkt_seq_video_non_burst[NUMOF_PKT_SEQ] = {
166         PKT_ID0(CMD_VS) | PKT_LEN0(0) | PKT_ID1(CMD_EOT) | PKT_LEN1(0) | PKT_LP,
167         0,
168         PKT_ID0(CMD_HS) | PKT_LEN0(0) | PKT_ID1(CMD_EOT) | PKT_LEN1(0) | PKT_LP,
169         0,
170         PKT_ID0(CMD_HS) | PKT_LEN0(0) | PKT_ID1(CMD_EOT) | PKT_LEN1(0) | PKT_LP,
171         0,
172         PKT_ID0(CMD_HS) | PKT_LEN0(0) | PKT_ID1(CMD_BLNK) | PKT_LEN1(2) |
173                 PKT_ID2(CMD_RGB) | PKT_LEN2(3),
174         PKT_ID3(CMD_BLNK) | PKT_LEN3(4),
175         PKT_ID0(CMD_HS) | PKT_LEN0(0) | PKT_ID1(CMD_EOT) | PKT_LEN1(0) | PKT_LP,
176         0,
177         PKT_ID0(CMD_HS) | PKT_LEN0(0) | PKT_ID1(CMD_BLNK) | PKT_LEN1(2) |
178                 PKT_ID2(CMD_RGB) | PKT_LEN2(3),
179         PKT_ID3(CMD_BLNK) | PKT_LEN3(4),
180 };
181
182 static const u32 dsi_pkt_seq_video_burst[NUMOF_PKT_SEQ] = {
183         PKT_ID0(CMD_VS) | PKT_LEN0(0) | PKT_ID1(CMD_EOT) | PKT_LEN1(7) | PKT_LP,
184         0,
185         PKT_ID0(CMD_HS) | PKT_LEN0(0) | PKT_ID1(CMD_EOT) | PKT_LEN1(7) | PKT_LP,
186         0,
187         PKT_ID0(CMD_HS) | PKT_LEN0(0) | PKT_ID1(CMD_EOT) | PKT_LEN1(7) | PKT_LP,
188         0,
189         PKT_ID0(CMD_HS) | PKT_LEN0(0) | PKT_ID1(CMD_BLNK) | PKT_LEN1(2)|
190         PKT_ID2(CMD_RGB) | PKT_LEN2(3) | PKT_LP,
191         PKT_ID0(CMD_EOT) | PKT_LEN0(7),
192         PKT_ID0(CMD_HS) | PKT_LEN0(0) | PKT_ID1(CMD_EOT) | PKT_LEN1(7) | PKT_LP,
193         0,
194         PKT_ID0(CMD_HS) | PKT_LEN0(0) | PKT_ID1(CMD_BLNK) | PKT_LEN1(2)|
195         PKT_ID2(CMD_RGB) | PKT_LEN2(3) | PKT_LP,
196         PKT_ID0(CMD_EOT) | PKT_LEN0(7),
197 };
198
199 static const u32 dsi_pkt_seq_video_burst_no_eot[NUMOF_PKT_SEQ] = {
200         PKT_ID0(CMD_VS) | PKT_LEN0(0) | PKT_ID1(CMD_EOT) | PKT_LEN1(0) | PKT_LP,
201         0,
202         PKT_ID0(CMD_HS) | PKT_LEN0(0) | PKT_ID1(CMD_EOT) | PKT_LEN1(0) | PKT_LP,
203         0,
204         PKT_ID0(CMD_HS) | PKT_LEN0(0) | PKT_ID1(CMD_EOT) | PKT_LEN1(0) | PKT_LP,
205         0,
206         PKT_ID0(CMD_HS) | PKT_LEN0(0) | PKT_ID1(CMD_BLNK) | PKT_LEN1(2)|
207         PKT_ID2(CMD_RGB) | PKT_LEN2(3) | PKT_LP,
208         PKT_ID0(CMD_EOT) | PKT_LEN0(0),
209         PKT_ID0(CMD_HS) | PKT_LEN0(0) | PKT_ID1(CMD_EOT) | PKT_LEN1(0) | PKT_LP,
210         0,
211         PKT_ID0(CMD_HS) | PKT_LEN0(0) | PKT_ID1(CMD_BLNK) | PKT_LEN1(2)|
212         PKT_ID2(CMD_RGB) | PKT_LEN2(3) | PKT_LP,
213         PKT_ID0(CMD_EOT) | PKT_LEN0(0),
214 };
215
216 /* TODO: verify with hw about this format */
217 const u32 dsi_pkt_seq_cmd_mode [NUMOF_PKT_SEQ] = {
218         0,
219         0,
220         0,
221         0,
222         0,
223         0,
224         PKT_ID0(CMD_LONGW) | PKT_LEN0(3) | PKT_ID1(CMD_EOT) | PKT_LEN1(7),
225         0,
226         0,
227         0,
228         PKT_ID0(CMD_LONGW) | PKT_LEN0(3) | PKT_ID1(CMD_EOT) | PKT_LEN1(7),
229         0,
230 };
231
232 const u32 init_reg[] = {
233         DSI_WR_DATA,
234         DSI_INT_ENABLE,
235         DSI_INT_STATUS,
236         DSI_INT_MASK,
237         DSI_INIT_SEQ_DATA_0,
238         DSI_INIT_SEQ_DATA_1,
239         DSI_INIT_SEQ_DATA_2,
240         DSI_INIT_SEQ_DATA_3,
241         DSI_DCS_CMDS,
242         DSI_PKT_SEQ_0_LO,
243         DSI_PKT_SEQ_1_LO,
244         DSI_PKT_SEQ_2_LO,
245         DSI_PKT_SEQ_3_LO,
246         DSI_PKT_SEQ_4_LO,
247         DSI_PKT_SEQ_5_LO,
248         DSI_PKT_SEQ_0_HI,
249         DSI_PKT_SEQ_1_HI,
250         DSI_PKT_SEQ_2_HI,
251         DSI_PKT_SEQ_3_HI,
252         DSI_PKT_SEQ_4_HI,
253         DSI_PKT_SEQ_5_HI,
254         DSI_CONTROL,
255         DSI_HOST_DSI_CONTROL,
256         DSI_PAD_CONTROL,
257         DSI_PAD_CONTROL_CD,
258         DSI_SOL_DELAY,
259         DSI_MAX_THRESHOLD,
260         DSI_TRIGGER,
261         DSI_TX_CRC,
262         DSI_INIT_SEQ_CONTROL,
263         DSI_PKT_LEN_0_1,
264         DSI_PKT_LEN_2_3,
265         DSI_PKT_LEN_4_5,
266         DSI_PKT_LEN_6_7,
267 };
268
269 static inline unsigned long tegra_dsi_readl(struct tegra_dc_dsi_data *dsi,
270                                                                         u32 reg)
271 {
272         return readl(dsi->base + reg * 4);
273 }
274
275 static inline void tegra_dsi_writel(struct tegra_dc_dsi_data *dsi,u32 val,
276                                                                         u32 reg)
277 {
278         writel(val, dsi->base + reg * 4);
279 }
280
281 static u32 tegra_dsi_get_hs_clk_rate(struct tegra_dc_dsi_data *dsi)
282 {
283         u32 dsi_clock_rate_khz;
284
285         switch (dsi->info.video_burst_mode) {
286         case TEGRA_DSI_VIDEO_BURST_MODE_LOW_SPEED:
287         case TEGRA_DSI_VIDEO_BURST_MODE_MEDIUM_SPEED:
288         case TEGRA_DSI_VIDEO_BURST_MODE_FAST_SPEED:
289         case TEGRA_DSI_VIDEO_BURST_MODE_FASTEST_SPEED:
290                 /* TODO: implement algo for these speed rate */
291
292         case TEGRA_DSI_VIDEO_BURST_MODE_MANUAL:
293                 if (dsi->info.burst_mode_freq_khz) {
294                         dsi_clock_rate_khz = dsi->info.burst_mode_freq_khz;
295                         break;
296                 }
297         case TEGRA_DSI_VIDEO_NONE_BURST_MODE:
298         case TEGRA_DSI_VIDEO_NONE_BURST_MODE_WITH_SYNC_END:
299         case TEGRA_DSI_VIDEO_BURST_MODE_LOWEST_SPEED:
300         default:
301                 dsi_clock_rate_khz = dsi->default_hs_clk_khz;
302                 break;
303         }
304
305         return dsi_clock_rate_khz;
306 }
307
308 static u32 tegra_dsi_get_lp_clk_rate(struct tegra_dc_dsi_data *dsi)
309 {
310         u32 dsi_clock_rate_khz;
311
312         if (dsi->info.enable_hs_clock_on_lp_cmd_mode)
313                 if (dsi->info.hs_clk_in_lp_cmd_mode_freq_khz)
314                         dsi_clock_rate_khz =
315                                 dsi->info.hs_clk_in_lp_cmd_mode_freq_khz;
316                 else
317                         dsi_clock_rate_khz = tegra_dsi_get_hs_clk_rate(dsi);
318         else
319                 dsi_clock_rate_khz = dsi->info.lp_cmd_mode_freq_khz;
320
321         return dsi_clock_rate_khz;
322 }
323
324 static void tegra_dsi_init_sw(struct tegra_dc *dc,
325                                                 struct tegra_dc_dsi_data *dsi)
326 {
327         u32 h_width_pixels;
328         u32 v_width_lines;
329         u32 pixel_clk_hz;
330         u32 byte_clk_hz;
331
332         switch (dsi->info.pixel_format) {
333                 case TEGRA_DSI_PIXEL_FORMAT_16BIT_P:
334                         /* 2 bytes per pixel */
335                         dsi->pixel_scaler_mul = 2;
336                         dsi->pixel_scaler_div = 1;
337                         break;
338                 case TEGRA_DSI_PIXEL_FORMAT_18BIT_P:
339                         /* 2.25 bytes per pixel */
340                         dsi->pixel_scaler_mul = 9;
341                         dsi->pixel_scaler_div = 4;
342                         break;
343                 case TEGRA_DSI_PIXEL_FORMAT_18BIT_NP:
344                 case TEGRA_DSI_PIXEL_FORMAT_24BIT_P:
345                         /* 3 bytes per pixel */
346                         dsi->pixel_scaler_mul = 3;
347                         dsi->pixel_scaler_div = 1;
348                         break;
349                 default:
350                         break;
351         }
352
353         h_width_pixels = dc->mode.h_back_porch + dc->mode.h_front_porch +
354                         dc->mode.h_sync_width + dc->mode.h_active;
355         v_width_lines = dc->mode.v_back_porch + dc->mode.v_front_porch +
356                         dc->mode.v_sync_width + dc->mode.v_active;
357
358         /* The slowest pixel rate that is required */
359         /*   for the given display timing       */
360         pixel_clk_hz = h_width_pixels * v_width_lines * dsi->info.refresh_rate;
361
362         /* Pixel byte rate on DSI interface */
363         byte_clk_hz     = (pixel_clk_hz * dsi->pixel_scaler_mul) /
364                         (dsi->pixel_scaler_div * dsi->info.n_data_lanes);
365
366         dsi->default_pixel_clk_khz = pixel_clk_hz / 1000;
367
368         printk("dsi: default pixel rate %d khz\n", dsi->default_pixel_clk_khz);
369
370         /*
371          * Pixel bit rate on DSI. Since DSI interface is double data rate (
372          * transferring data on both rising and falling edge of clk), div by 2
373          * to get the actual clock rate.
374          */
375         dsi->default_hs_clk_khz =
376                         (byte_clk_hz * NUMOF_BIT_PER_BYTE) / (1000 * 2);
377
378         dsi->controller_index = dc->ndev->id;
379         dsi->ulpm = false;
380
381         dsi->dsi_control_val =
382                         DSI_CONTROL_VIRTUAL_CHANNEL(dsi->info.virtual_channel) |
383                         DSI_CONTROL_NUM_DATA_LANES(dsi->info.n_data_lanes - 1) |
384                         DSI_CONTROL_VID_SOURCE(dsi->controller_index) |
385                         DSI_CONTROL_DATA_FORMAT(dsi->info.pixel_format);
386
387         dsi->target_lp_clk_khz = tegra_dsi_get_lp_clk_rate(dsi);
388         dsi->target_hs_clk_khz = tegra_dsi_get_hs_clk_rate(dsi);
389
390 #if DSI_USE_SYNC_POINTS
391         dsi->syncpt_id = NVSYNCPT_DSI;
392 #endif
393
394         /*
395          * Force video clock to be continuous mode if
396          * enable_hs_clock_on_lp_cmd_mode is set
397          */
398         if (dsi->info.enable_hs_clock_on_lp_cmd_mode) {
399                 if (dsi->info.video_clock_mode != TEGRA_DSI_VIDEO_CLOCK_CONTINUOUS)
400                         printk("Force to clock continuous mode\n");
401
402                 dsi->info.video_clock_mode = TEGRA_DSI_VIDEO_CLOCK_CONTINUOUS;
403         }
404
405 }
406
407 static void tegra_dsi_get_phy_timing(struct tegra_dc_dsi_data *dsi,
408                                 struct dsi_phy_timing_inclk *phy_timing_clk,
409                                 u32 clk_ns)
410 {
411
412         phy_timing_clk->t_hsdexit = dsi->info.phy_timing.t_hsdexit_ns ?
413                         (dsi->info.phy_timing.t_hsdexit_ns / clk_ns) :
414                         (T_HSEXIT_DEFAULT(clk_ns));
415
416         phy_timing_clk->t_hstrail = dsi->info.phy_timing.t_hstrail_ns ?
417                         (dsi->info.phy_timing.t_hstrail_ns / clk_ns) :
418                         (T_HSTRAIL_DEFAULT(clk_ns));
419
420         phy_timing_clk->t_datzero = dsi->info.phy_timing.t_datzero_ns ?
421                         (dsi->info.phy_timing.t_datzero_ns / clk_ns) :
422                         (T_DATZERO_DEFAULT(clk_ns));
423
424         phy_timing_clk->t_hsprepr = dsi->info.phy_timing.t_hsprepr_ns ?
425                         (dsi->info.phy_timing.t_hsprepr_ns / clk_ns) :
426                         (T_HSPREPR_DEFAULT(clk_ns));
427
428         phy_timing_clk->t_clktrail = dsi->info.phy_timing.t_clktrail_ns ?
429                                 (dsi->info.phy_timing.t_clktrail_ns / clk_ns) :
430                                 (T_CLKTRAIL_DEFAULT(clk_ns));
431
432         phy_timing_clk->t_clkpost = dsi->info.phy_timing.t_clkpost_ns ?
433                                 (dsi->info.phy_timing.t_clkpost_ns / clk_ns) :
434                                 (T_CLKPOST_DEFAULT(clk_ns));
435
436         phy_timing_clk->t_clkzero = dsi->info.phy_timing.t_clkzero_ns ?
437                                 (dsi->info.phy_timing.t_clkzero_ns / clk_ns) :
438                                 (T_CLKZERO_DEFAULT(clk_ns));
439
440         phy_timing_clk->t_tlpx = dsi->info.phy_timing.t_tlpx_ns ?
441                                 (dsi->info.phy_timing.t_tlpx_ns / clk_ns) :
442                                 (T_TLPX_DEFAULT(clk_ns));
443
444         phy_timing_clk->t_clkpre = T_CLKPRE_DEFAULT(clk_ns);
445         phy_timing_clk->t_clkprepare = T_CLKPREPARE_DEFAULT(clk_ns);
446         phy_timing_clk->t_wakeup = T_WAKEUP_DEFAULT(clk_ns);
447
448         phy_timing_clk->t_taget = 5 * phy_timing_clk->t_tlpx;
449         phy_timing_clk->t_tasure = 2 * phy_timing_clk->t_tlpx;
450         phy_timing_clk->t_tago = 4 * phy_timing_clk->t_tlpx;
451 }
452
453 static void tegra_dsi_set_phy_timing(struct tegra_dc_dsi_data *dsi)
454 {
455         u32 val;
456         struct dsi_phy_timing_inclk     phy_timing;
457
458         tegra_dsi_get_phy_timing(dsi, &phy_timing, dsi->current_bit_clk_ns);
459
460         val = DSI_PHY_TIMING_0_THSDEXIT(phy_timing.t_hsdexit) |
461                         DSI_PHY_TIMING_0_THSTRAIL(phy_timing.t_hstrail) |
462                         DSI_PHY_TIMING_0_TDATZERO(phy_timing.t_datzero) |
463                         DSI_PHY_TIMING_0_THSPREPR(phy_timing.t_hsprepr);
464         tegra_dsi_writel(dsi, val, DSI_PHY_TIMING_0);
465
466         val = DSI_PHY_TIMING_1_TCLKTRAIL(phy_timing.t_clktrail) |
467                         DSI_PHY_TIMING_1_TCLKPOST(phy_timing.t_clkpost) |
468                         DSI_PHY_TIMING_1_TCLKZERO(phy_timing.t_clkzero) |
469                         DSI_PHY_TIMING_1_TTLPX(phy_timing.t_tlpx);
470         tegra_dsi_writel(dsi, val, DSI_PHY_TIMING_1);
471
472         val = DSI_PHY_TIMING_2_TCLKPREPARE(phy_timing.t_clkprepare) |
473                 DSI_PHY_TIMING_2_TCLKPRE(phy_timing.t_clkpre) |
474                         DSI_PHY_TIMING_2_TWAKEUP(phy_timing.t_wakeup);
475         tegra_dsi_writel(dsi, val, DSI_PHY_TIMING_2);
476
477         val = DSI_BTA_TIMING_TTAGET(phy_timing.t_taget) |
478                         DSI_BTA_TIMING_TTASURE(phy_timing.t_tasure) |
479                         DSI_BTA_TIMING_TTAGO(phy_timing.t_tago);
480         tegra_dsi_writel(dsi, val, DSI_BTA_TIMING);
481 }
482
483 static u32 tegra_dsi_sol_delay_burst(struct tegra_dc *dc,
484                                                 struct tegra_dc_dsi_data *dsi)
485 {
486         u32 dsi_to_pixel_clk_ratio;
487         u32 temp;
488         u32 temp1;
489         u32 mipi_clk_adj_kHz;
490         u32 sol_delay;
491         struct tegra_dc_mode *dc_modes = &dc->mode;
492
493         /* Get Fdsi/Fpixel ration (note: Fdsi si in bit format) */
494         dsi_to_pixel_clk_ratio = (dsi->current_dsi_clk_khz * 2 +
495                 dsi->default_pixel_clk_khz - 1) / dsi->default_pixel_clk_khz;
496
497         /* Convert Fdsi to byte format */
498         dsi_to_pixel_clk_ratio *= 1000/8;
499
500         /* Multiplying by 1000 so that we don't loose the fraction part */
501         temp = dc_modes->h_active * 1000;
502         temp1 = dc_modes->h_active + dc_modes->h_back_porch +
503                         dc_modes->h_sync_width;
504
505         sol_delay = temp1 * dsi_to_pixel_clk_ratio -
506                         temp * dsi->pixel_scaler_mul /
507                         (dsi->pixel_scaler_div * dsi->info.n_data_lanes);
508
509         /* Do rounding on sol delay */
510         sol_delay = (sol_delay + 1000 - 1)/1000;
511
512         /* TODO:
513          * 1. find out the correct sol fifo depth to use
514          * 2. verify with hw about the clamping function
515          */
516         if (sol_delay > (480 * 4)) {
517                 sol_delay = (480 * 4);
518                 mipi_clk_adj_kHz = sol_delay +
519                         (dc_modes->h_active * dsi->pixel_scaler_mul) /
520                         (dsi->info.n_data_lanes * dsi->pixel_scaler_div);
521
522                 mipi_clk_adj_kHz *= (dsi->default_pixel_clk_khz / temp1);
523
524                 mipi_clk_adj_kHz *= 4;
525         }
526
527         dsi->target_hs_clk_khz = mipi_clk_adj_kHz;
528
529         return sol_delay;
530 }
531
532 static void tegra_dsi_set_sol_delay(struct tegra_dc *dc,
533                                                 struct tegra_dc_dsi_data *dsi)
534 {
535         u32 sol_delay;
536
537         if (dsi->info.video_burst_mode == TEGRA_DSI_VIDEO_NONE_BURST_MODE ||
538                 dsi->info.video_burst_mode ==
539                                 TEGRA_DSI_VIDEO_NONE_BURST_MODE_WITH_SYNC_END) {
540                 sol_delay = NUMOF_BIT_PER_BYTE * dsi->pixel_scaler_mul /
541                         (dsi->pixel_scaler_div * dsi->info.n_data_lanes);
542                 dsi->status.clk_burst = DSI_CLK_BURST_NONE_BURST;
543         } else {
544                 sol_delay = tegra_dsi_sol_delay_burst(dc, dsi);
545                 dsi->status.clk_burst = DSI_CLK_BURST_BURST_MODE;
546         }
547
548         tegra_dsi_writel(dsi, DSI_SOL_DELAY_SOL_DELAY(sol_delay),
549                                                                 DSI_SOL_DELAY);
550 }
551
552 static void tegra_dsi_set_timeout(struct tegra_dc_dsi_data *dsi)
553 {
554         u32 val;
555         u32 bytes_per_frame;
556         u32 timeout = 0;
557
558         /* TODO: verify the following eq */
559         bytes_per_frame = dsi->current_dsi_clk_khz * 1000 * 2 /
560                                                 (dsi->info.refresh_rate * 8);
561         timeout = bytes_per_frame / DSI_CYCLE_COUNTER_VALUE;
562         timeout = (timeout + DSI_HTX_TO_MARGIN) & 0xffff;
563
564         val = DSI_TIMEOUT_0_LRXH_TO(DSI_LRXH_TO_VALUE) |
565                         DSI_TIMEOUT_0_HTX_TO(timeout);
566         tegra_dsi_writel(dsi, val, DSI_TIMEOUT_0);
567
568         if (dsi->info.panel_reset_timeout_msec)
569                 timeout = (dsi->info.panel_reset_timeout_msec * 1000*1000)
570                                         / dsi->current_bit_clk_ns;
571         else
572                 timeout = DSI_PR_TO_VALUE;
573
574         val = DSI_TIMEOUT_1_PR_TO(timeout) |
575                 DSI_TIMEOUT_1_TA_TO(DSI_TA_TO_VALUE);
576         tegra_dsi_writel(dsi, val, DSI_TIMEOUT_1);
577
578         val = DSI_TO_TALLY_P_RESET_STATUS(IN_RESET) |
579                 DSI_TO_TALLY_TA_TALLY(DSI_TA_TALLY_VALUE)|
580                 DSI_TO_TALLY_LRXH_TALLY(DSI_LRXH_TALLY_VALUE)|
581                 DSI_TO_TALLY_HTX_TALLY(DSI_HTX_TALLY_VALUE);
582         tegra_dsi_writel(dsi, val, DSI_TO_TALLY);
583 }
584
585 static void tegra_dsi_setup_video_mode_pkt_length(struct tegra_dc *dc,
586                                                 struct tegra_dc_dsi_data *dsi)
587 {
588         u32 val;
589         u32 hact_pkt_len;
590         u32 hsa_pkt_len;
591         u32 hbp_pkt_len;
592         u32 hfp_pkt_len;
593
594         hact_pkt_len = dc->mode.h_active * dsi->pixel_scaler_mul /
595                                                         dsi->pixel_scaler_div;
596         hsa_pkt_len = dc->mode.h_sync_width * dsi->pixel_scaler_mul /
597                                                         dsi->pixel_scaler_div;
598         hbp_pkt_len = dc->mode.h_back_porch * dsi->pixel_scaler_mul /
599                                                         dsi->pixel_scaler_div;
600         hfp_pkt_len = dc->mode.h_front_porch * dsi->pixel_scaler_mul /
601                                                         dsi->pixel_scaler_div;
602
603         if (dsi->info.video_burst_mode !=
604                                 TEGRA_DSI_VIDEO_NONE_BURST_MODE_WITH_SYNC_END)
605                 hbp_pkt_len += hsa_pkt_len;
606
607         hsa_pkt_len -= DSI_HSYNC_BLNK_PKT_OVERHEAD;
608         hbp_pkt_len -= DSI_HBACK_PORCH_PKT_OVERHEAD;
609         hfp_pkt_len -= DSI_HFRONT_PORCH_PKT_OVERHEAD;
610
611         val = DSI_PKT_LEN_0_1_LENGTH_0(0) | DSI_PKT_LEN_0_1_LENGTH_1(hsa_pkt_len);
612         tegra_dsi_writel(dsi, val, DSI_PKT_LEN_0_1);
613
614         val = DSI_PKT_LEN_2_3_LENGTH_2(hbp_pkt_len) |
615                         DSI_PKT_LEN_2_3_LENGTH_3(hact_pkt_len);
616         tegra_dsi_writel(dsi, val, DSI_PKT_LEN_2_3);
617
618         val = DSI_PKT_LEN_4_5_LENGTH_4(hfp_pkt_len) | DSI_PKT_LEN_4_5_LENGTH_5(0);
619         tegra_dsi_writel(dsi, val, DSI_PKT_LEN_4_5);
620
621         val = DSI_PKT_LEN_6_7_LENGTH_6(0) | DSI_PKT_LEN_6_7_LENGTH_7(0);
622         tegra_dsi_writel(dsi, val, DSI_PKT_LEN_6_7);
623 }
624
625 static void tegra_dsi_setup_cmd_mode_pkt_length(struct tegra_dc *dc,
626                                                 struct tegra_dc_dsi_data *dsi)
627 {
628         unsigned long   val;
629         unsigned long   act_bytes;
630
631         act_bytes = dc->mode.h_active * dsi->pixel_scaler_mul /
632                         dsi->pixel_scaler_div + 1;
633
634         val = DSI_PKT_LEN_0_1_LENGTH_0(0) | DSI_PKT_LEN_0_1_LENGTH_1(0);
635         tegra_dsi_writel(dsi, val, DSI_PKT_LEN_0_1);
636
637         val = DSI_PKT_LEN_2_3_LENGTH_2(0) | DSI_PKT_LEN_2_3_LENGTH_3(act_bytes);
638         tegra_dsi_writel(dsi, val, DSI_PKT_LEN_2_3);
639
640         val = DSI_PKT_LEN_4_5_LENGTH_4(0) | DSI_PKT_LEN_4_5_LENGTH_5(act_bytes);
641         tegra_dsi_writel(dsi, val, DSI_PKT_LEN_4_5);
642
643         val = DSI_PKT_LEN_6_7_LENGTH_6(0) | DSI_PKT_LEN_6_7_LENGTH_7(0x0f0f);
644         tegra_dsi_writel(dsi, val, DSI_PKT_LEN_6_7);
645 }
646
647 static void tegra_dsi_set_pkt_length(struct tegra_dc *dc,
648                                                 struct tegra_dc_dsi_data *dsi)
649 {
650         if (dsi->driven_mode == TEGRA_DSI_DRIVEN_BY_HOST)
651                 return;
652
653         if (dsi->info.video_data_type == TEGRA_DSI_VIDEO_TYPE_VIDEO_MODE)
654                 tegra_dsi_setup_video_mode_pkt_length(dc, dsi);
655         else
656                 tegra_dsi_setup_cmd_mode_pkt_length(dc, dsi);
657 }
658
659 static void tegra_dsi_set_pkt_seq(struct tegra_dc *dc,
660                                                 struct tegra_dc_dsi_data *dsi)
661 {
662         const u32 *pkt_seq;
663         u32 rgb_info;
664         u32 pkt_seq_3_5_rgb_lo;
665         u32 pkt_seq_3_5_rgb_hi;
666         u32     val;
667         u32 reg;
668         u8  i;
669
670         if (dsi->driven_mode == TEGRA_DSI_DRIVEN_BY_HOST)
671                 return;
672
673         switch(dsi->info.pixel_format) {
674         case TEGRA_DSI_PIXEL_FORMAT_16BIT_P:
675                 rgb_info = CMD_RGB_16BPP;
676                 break;
677         case TEGRA_DSI_PIXEL_FORMAT_18BIT_P:
678                 rgb_info = CMD_RGB_18BPP;
679                 break;
680         case TEGRA_DSI_PIXEL_FORMAT_18BIT_NP:
681                 rgb_info = CMD_RGB_18BPPNP;
682                 break;
683         case TEGRA_DSI_PIXEL_FORMAT_24BIT_P:
684         default:
685                 rgb_info = CMD_RGB_24BPP;
686                 break;
687         }
688
689         pkt_seq_3_5_rgb_lo = 0;
690         pkt_seq_3_5_rgb_hi = 0;
691         if (dsi->info.video_data_type == TEGRA_DSI_VIDEO_TYPE_COMMAND_MODE)
692                 pkt_seq = dsi_pkt_seq_cmd_mode;
693         else {
694                 switch (dsi->info.video_burst_mode) {
695                 case TEGRA_DSI_VIDEO_BURST_MODE_LOWEST_SPEED:
696                 case TEGRA_DSI_VIDEO_BURST_MODE_LOW_SPEED:
697                 case TEGRA_DSI_VIDEO_BURST_MODE_MEDIUM_SPEED:
698                 case TEGRA_DSI_VIDEO_BURST_MODE_FAST_SPEED:
699                 case TEGRA_DSI_VIDEO_BURST_MODE_FASTEST_SPEED:
700                 case TEGRA_DSI_VIDEO_BURST_MODE_MANUAL:
701                         pkt_seq_3_5_rgb_lo = DSI_PKT_SEQ_3_LO_PKT_32_ID(rgb_info);
702                         if(!dsi->info.no_pkt_seq_eot)
703                                 pkt_seq = dsi_pkt_seq_video_burst;
704                         else
705                                 pkt_seq = dsi_pkt_seq_video_burst_no_eot;
706                         break;
707                 case TEGRA_DSI_VIDEO_NONE_BURST_MODE_WITH_SYNC_END:
708                         pkt_seq_3_5_rgb_hi = DSI_PKT_SEQ_3_HI_PKT_34_ID(rgb_info);
709                         pkt_seq = dsi_pkt_seq_video_non_burst_syne;
710                         break;
711                 case TEGRA_DSI_VIDEO_NONE_BURST_MODE:
712                 default:
713                         pkt_seq_3_5_rgb_lo = DSI_PKT_SEQ_3_LO_PKT_32_ID(rgb_info);
714                         pkt_seq = dsi_pkt_seq_video_non_burst;
715                         break;
716                 }
717         }
718
719         for (i = 0; i < NUMOF_PKT_SEQ; i++) {
720                 val = pkt_seq[i];
721                 reg = dsi_pkt_seq_reg[i];
722                 if ((reg == DSI_PKT_SEQ_3_LO) || (reg == DSI_PKT_SEQ_5_LO))
723                         val |= pkt_seq_3_5_rgb_lo;
724                 if ((reg == DSI_PKT_SEQ_3_HI) || (reg == DSI_PKT_SEQ_5_HI))
725                         val |= pkt_seq_3_5_rgb_hi;
726                 tegra_dsi_writel(dsi, val, reg);
727         }
728 }
729
730 static void tegra_dsi_stop_dc_stream(struct tegra_dc *dc,
731                                                 struct tegra_dc_dsi_data *dsi)
732 {
733         tegra_dc_writel(dc, 0, DC_DISP_DISP_WIN_OPTIONS);
734         tegra_dc_writel(dc, GENERAL_ACT_REQ << 8, DC_CMD_STATE_CONTROL);
735         tegra_dc_writel(dc, GENERAL_ACT_REQ, DC_CMD_STATE_CONTROL);
736
737         dsi->status.dc_stream = DSI_DC_STREAM_DISABLE;
738 }
739
740 void tegra_dsi_stop_dc_stream_at_frame_end(struct tegra_dc *dc, struct tegra_dc_dsi_data *dsi)
741 {
742         int val;
743         long timeout;
744
745         /* stop dc */
746         tegra_dsi_stop_dc_stream(dc, dsi);
747
748         /* enable vblank interrupt */
749         val = tegra_dc_readl(dc, DC_CMD_INT_ENABLE);
750         val |= V_BLANK_INT;
751         tegra_dc_writel(dc, val, DC_CMD_INT_ENABLE);
752
753         val = tegra_dc_readl(dc, DC_CMD_INT_MASK);
754         val |= V_BLANK_INT;
755         tegra_dc_writel(dc, val, DC_CMD_INT_MASK);
756
757         /* wait for vblank completion */
758         timeout = wait_for_completion_interruptible_timeout(
759                 &dc->vblank_complete, DSI_STOP_DC_DURATION_MSEC);
760
761         /* disable vblank interrupt */
762         val = tegra_dc_readl(dc, DC_CMD_INT_ENABLE);
763         val &= ~V_BLANK_INT;
764         tegra_dc_writel(dc, val, DC_CMD_INT_ENABLE);
765
766         if(timeout == 0)
767                 printk("Warning: dc dosen't stop at the end of the frame.\n");
768 }
769
770 static void tegra_dsi_start_dc_stream(struct tegra_dc *dc,
771                                                 struct tegra_dc_dsi_data *dsi)
772 {
773         u32 val;
774
775         tegra_dc_writel(dc, DSI_ENABLE, DC_DISP_DISP_WIN_OPTIONS);
776
777         /* TODO: clean up */
778         val = PIN_INPUT_LSPI_INPUT_EN;
779         tegra_dc_writel(dc, val, DC_COM_PIN_INPUT_ENABLE3);
780
781         val = PIN_OUTPUT_LSPI_OUTPUT_DIS;
782         tegra_dc_writel(dc, val, DC_COM_PIN_OUTPUT_ENABLE3);
783
784         tegra_dc_writel(dc, PW0_ENABLE | PW1_ENABLE | PW2_ENABLE | PW3_ENABLE |
785                         PW4_ENABLE | PM0_ENABLE | PM1_ENABLE,
786                         DC_CMD_DISPLAY_POWER_CONTROL);
787
788         val = MSF_POLARITY_HIGH | MSF_ENABLE | MSF_LSPI;
789         tegra_dc_writel(dc, val, DC_CMD_DISPLAY_COMMAND_OPTION0);
790
791
792         /* TODO: using continuous video mode for now */
793         /* if (dsi->info.panel_has_frame_buffer) {*/
794         if (0) {
795                 tegra_dc_writel(dc, DISP_CTRL_MODE_NC_DISPLAY, DC_CMD_DISPLAY_COMMAND);
796                 tegra_dc_writel(dc, GENERAL_UPDATE, DC_CMD_STATE_CONTROL);
797                 val = GENERAL_ACT_REQ | NC_HOST_TRIG;
798                 tegra_dc_writel(dc, val, DC_CMD_STATE_CONTROL);
799         } else {
800                 tegra_dc_writel(dc, DISP_CTRL_MODE_C_DISPLAY, DC_CMD_DISPLAY_COMMAND);
801                 tegra_dc_writel(dc, GENERAL_ACT_REQ << 8, DC_CMD_STATE_CONTROL);
802                 tegra_dc_writel(dc, GENERAL_ACT_REQ, DC_CMD_STATE_CONTROL);
803         }
804
805         dsi->status.dc_stream = DSI_DC_STREAM_ENABLE;
806 }
807
808 static void tegra_dsi_set_dc_clk(struct tegra_dc *dc,
809                                                 struct tegra_dc_dsi_data *dsi)
810 {
811         u32 shift_clk_div;
812         u32 val;
813
814         if (dsi->info.video_burst_mode == TEGRA_DSI_VIDEO_NONE_BURST_MODE ||
815                 dsi->info.video_burst_mode ==
816                                 TEGRA_DSI_VIDEO_NONE_BURST_MODE_WITH_SYNC_END)
817                 shift_clk_div = NUMOF_BIT_PER_BYTE * dsi->pixel_scaler_mul /
818                         (dsi->pixel_scaler_div * dsi->info.n_data_lanes) - 2;
819         else
820                 shift_clk_div = (dsi->current_dsi_clk_khz * 2 +
821                                                 dsi->default_hs_clk_khz - 1) /
822                                                 (dsi->default_hs_clk_khz) - 2;
823
824 #ifdef CONFIG_TEGRA_FPGA_PLATFORM
825         shift_clk_div = 1;
826 #endif
827
828         /* TODO: find out if PCD3 option is required */
829         val = PIXEL_CLK_DIVIDER_PCD1 | SHIFT_CLK_DIVIDER(shift_clk_div);
830         tegra_dc_writel(dc, val, DC_DISP_DISP_CLOCK_CONTROL);
831
832         clk_enable(dsi->dc_clk);
833 }
834
835 static void tegra_dsi_set_dsi_clk(struct tegra_dc *dc,
836                                         struct tegra_dc_dsi_data *dsi, u32 clk)
837 {
838         u32 rm;
839
840         rm = clk % 1000;
841         if (rm != 0)
842                 clk -= rm;
843
844         clk *= 2;       /* Value for PLLD routine is required to be twice as */
845                         /* the desired clock rate */
846
847         dc->mode.pclk = clk*1000;
848         tegra_dc_setup_clk(dc, dsi->dsi_clk);
849         clk_enable(dsi->dsi_clk);
850         tegra_periph_reset_deassert(dsi->dsi_clk);
851
852         dsi->current_dsi_clk_khz = clk_get_rate(dsi->dsi_clk) / 1000;
853
854         dsi->current_bit_clk_ns =  1000*1000 / (dsi->current_dsi_clk_khz * 2);
855 }
856
857 static void tegra_dsi_hs_clk_out_enable(struct tegra_dc_dsi_data *dsi)
858 {
859         u32 val;
860
861         val = tegra_dsi_readl(dsi, DSI_CONTROL);
862         val &= ~DSI_CONTROL_HS_CLK_CTRL(1);
863
864         if (dsi->info.video_clock_mode == TEGRA_DSI_VIDEO_CLOCK_CONTINUOUS) {
865                 val |= DSI_CONTROL_HS_CLK_CTRL(CONTINUOUS);
866                 dsi->status.clk_mode = DSI_PHYCLK_CONTINUOUS;
867         } else {
868                 val |= DSI_CONTROL_HS_CLK_CTRL(TX_ONLY);
869                 dsi->status.clk_mode = DSI_PHYCLK_TX_ONLY;
870         }
871         tegra_dsi_writel(dsi, val, DSI_CONTROL);
872
873         val = tegra_dsi_readl(dsi, DSI_HOST_DSI_CONTROL);
874         val &= ~DSI_HOST_DSI_CONTROL_HIGH_SPEED_TRANS(1);
875         val |= DSI_HOST_DSI_CONTROL_HIGH_SPEED_TRANS(TEGRA_DSI_HIGH);
876         tegra_dsi_writel(dsi, val, DSI_HOST_DSI_CONTROL);
877
878         dsi->status.clk_out = DSI_PHYCLK_OUT_EN;
879 }
880
881 static void tegra_dsi_hs_clk_out_enable_in_lp(struct tegra_dc_dsi_data *dsi)
882 {
883         u32 val;
884         tegra_dsi_hs_clk_out_enable(dsi);
885
886         val = tegra_dsi_readl(dsi, DSI_HOST_DSI_CONTROL);
887         val &= ~DSI_HOST_DSI_CONTROL_HIGH_SPEED_TRANS(1);
888         val |= DSI_HOST_DSI_CONTROL_HIGH_SPEED_TRANS(TEGRA_DSI_LOW);
889         tegra_dsi_writel(dsi, val, DSI_HOST_DSI_CONTROL);
890 }
891
892 static void tegra_dsi_hs_clk_out_disable(struct tegra_dc *dc,
893                                                 struct tegra_dc_dsi_data *dsi)
894 {
895         u32 val;
896
897         if (dsi->status.dc_stream == DSI_DC_STREAM_ENABLE)
898                 tegra_dsi_stop_dc_stream(dc, dsi);
899
900         val = tegra_dsi_readl(dsi, DSI_CONTROL);
901         val &= ~DSI_CONTROL_HS_CLK_CTRL(1);
902         val |= DSI_CONTROL_HS_CLK_CTRL(TX_ONLY);
903         tegra_dsi_writel(dsi, val, DSI_CONTROL);
904
905         /* TODO: issue a cmd */
906
907         val = tegra_dsi_readl(dsi, DSI_HOST_DSI_CONTROL);
908         val &= ~DSI_HOST_DSI_CONTROL_HIGH_SPEED_TRANS(1);
909         val |= DSI_HOST_DSI_CONTROL_HIGH_SPEED_TRANS(TEGRA_DSI_LOW);
910         tegra_dsi_writel(dsi, val, DSI_HOST_DSI_CONTROL);
911
912         dsi->status.clk_mode = DSI_PHYCLK_NOT_INIT;
913         dsi->status.clk_out = DSI_PHYCLK_OUT_DIS;
914 }
915
916 static void tegra_dsi_set_control_reg_lp(struct tegra_dc_dsi_data *dsi)
917 {
918         u32 dsi_control;
919         u32 host_dsi_control;
920         u32 max_threshold;
921
922         dsi_control = dsi->dsi_control_val | DSI_CTRL_HOST_DRIVEN;
923         host_dsi_control = HOST_DSI_CTRL_COMMON |
924                         HOST_DSI_CTRL_HOST_DRIVEN |
925                         DSI_HOST_DSI_CONTROL_HIGH_SPEED_TRANS(TEGRA_DSI_LOW);
926         max_threshold = DSI_MAX_THRESHOLD_MAX_THRESHOLD(DSI_HOST_FIFO_DEPTH);
927
928         tegra_dsi_writel(dsi, max_threshold, DSI_MAX_THRESHOLD);
929         tegra_dsi_writel(dsi, dsi_control, DSI_CONTROL);
930         tegra_dsi_writel(dsi, host_dsi_control, DSI_HOST_DSI_CONTROL);
931
932         dsi->status.driven = DSI_DRIVEN_MODE_HOST;
933         dsi->status.clk_burst = DSI_CLK_BURST_NOT_INIT;
934         dsi->status.vtype = DSI_VIDEO_TYPE_NOT_INIT;
935 }
936
937 static void tegra_dsi_set_control_reg_hs(struct tegra_dc_dsi_data *dsi)
938 {
939         u32 dsi_control;
940         u32 host_dsi_control;
941         u32 max_threshold;
942         u32 dcs_cmd;
943
944         dsi_control = dsi->dsi_control_val;
945         host_dsi_control = HOST_DSI_CTRL_COMMON;
946         max_threshold = 0;
947         dcs_cmd = 0;
948
949         if (dsi->driven_mode == TEGRA_DSI_DRIVEN_BY_HOST) {
950                 dsi_control |= DSI_CTRL_HOST_DRIVEN;
951                 host_dsi_control |= HOST_DSI_CTRL_HOST_DRIVEN;
952                 max_threshold = DSI_MAX_THRESHOLD_MAX_THRESHOLD(DSI_HOST_FIFO_DEPTH);
953                 dsi->status.driven = DSI_DRIVEN_MODE_HOST;
954         } else {
955                 dsi_control |= DSI_CTRL_DC_DRIVEN;
956                 host_dsi_control |= HOST_DSI_CTRL_DC_DRIVEN;
957                 max_threshold = DSI_MAX_THRESHOLD_MAX_THRESHOLD(DSI_VIDEO_FIFO_DEPTH);
958                 dsi->status.driven = DSI_DRIVEN_MODE_DC;
959         }
960
961         if (dsi->info.video_data_type == TEGRA_DSI_VIDEO_TYPE_COMMAND_MODE) {
962                 dsi_control |= DSI_CTRL_CMD_MODE;
963                 host_dsi_control |= HOST_DSI_CTRL_CMD_MODE;
964                 dcs_cmd = DSI_DCS_CMDS_LT5_DCS_CMD(DSI_WRITE_MEMORY_START)|
965                                 DSI_DCS_CMDS_LT3_DCS_CMD(DSI_WRITE_MEMORY_CONTINUE);
966                 dsi->status.vtype = DSI_VIDEO_TYPE_CMD_MODE;
967
968         } else {
969                 dsi_control |= DSI_CTRL_VIDEO_MODE;
970                 host_dsi_control |= HOST_DSI_CTRL_VIDEO_MODE;
971                 dsi->status.vtype = DSI_VIDEO_TYPE_VIDEO_MODE;
972         }
973
974         tegra_dsi_writel(dsi, max_threshold, DSI_MAX_THRESHOLD);
975         tegra_dsi_writel(dsi, dcs_cmd, DSI_DCS_CMDS);
976         tegra_dsi_writel(dsi, dsi_control, DSI_CONTROL);
977         tegra_dsi_writel(dsi, host_dsi_control, DSI_HOST_DSI_CONTROL);
978 }
979
980 static int tegra_dsi_init_hw(struct tegra_dc *dc,
981                                                 struct tegra_dc_dsi_data *dsi)
982 {
983         u32 val;
984         u32 i;
985
986         tegra_dsi_set_dsi_clk(dc, dsi, dsi->target_lp_clk_khz);
987         if (dsi->info.dsi_instance) {
988                 /* TODO:Set the misc register*/
989         }
990
991         /* TODO: only need to change the timing for bta */
992         tegra_dsi_set_phy_timing(dsi);
993
994         if (dsi->status.dc_stream == DSI_DC_STREAM_ENABLE)
995                 tegra_dsi_stop_dc_stream(dc, dsi);
996
997         /* Initializing DSI registers */
998         for (i = 0; i < ARRAY_SIZE(init_reg); i++) {
999                 tegra_dsi_writel(dsi, 0, init_reg[i]);
1000         }
1001         tegra_dsi_writel(dsi, dsi->dsi_control_val, DSI_CONTROL);
1002
1003         val = DSI_PAD_CONTROL_PAD_PDIO(0) |
1004                         DSI_PAD_CONTROL_PAD_PDIO_CLK(0) |
1005                         DSI_PAD_CONTROL_PAD_PULLDN_ENAB(TEGRA_DSI_DISABLE);
1006         tegra_dsi_writel(dsi, val, DSI_PAD_CONTROL);
1007
1008         val = DSI_POWER_CONTROL_LEG_DSI_ENABLE(TEGRA_DSI_ENABLE);
1009         tegra_dsi_writel(dsi, val, DSI_POWER_CONTROL);
1010
1011         while (tegra_dsi_readl(dsi, DSI_POWER_CONTROL) != val) {
1012                 tegra_dsi_writel(dsi, val, DSI_POWER_CONTROL);
1013         }
1014
1015         dsi->status.init = DSI_MODULE_INIT;
1016         dsi->status.lphs = DSI_LPHS_NOT_INIT;
1017         dsi->status.vtype = DSI_VIDEO_TYPE_NOT_INIT;
1018         dsi->status.driven = DSI_DRIVEN_MODE_NOT_INIT;
1019         dsi->status.clk_out = DSI_PHYCLK_OUT_DIS;
1020         dsi->status.clk_mode = DSI_PHYCLK_NOT_INIT;
1021         dsi->status.clk_burst = DSI_CLK_BURST_NOT_INIT;
1022         dsi->status.dc_stream = DSI_DC_STREAM_DISABLE;
1023
1024         return 0;
1025 }
1026
1027 static int tegra_dsi_set_to_lp_mode(struct tegra_dc *dc,
1028                                                 struct tegra_dc_dsi_data *dsi)
1029 {
1030         int     err;
1031
1032         if (dsi->status.init != DSI_MODULE_INIT) {
1033                 err = -EPERM;
1034                 goto fail;
1035         }
1036
1037         if (dsi->status.lphs == DSI_LPHS_IN_LP_MODE)
1038                 goto success;
1039
1040         if (dsi->status.dc_stream == DSI_DC_STREAM_ENABLE)
1041                 tegra_dsi_stop_dc_stream_at_frame_end(dc, dsi);
1042
1043         /* disable/enable hs clock according to enable_hs_clock_on_lp_cmd_mode */
1044         if ((dsi->status.clk_out == DSI_PHYCLK_OUT_EN) &&
1045                 (!dsi->info.enable_hs_clock_on_lp_cmd_mode))
1046                 tegra_dsi_hs_clk_out_disable(dc, dsi);
1047
1048         if (dsi->current_dsi_clk_khz != dsi->target_lp_clk_khz){
1049                 tegra_dsi_set_dsi_clk(dc, dsi, dsi->target_lp_clk_khz);
1050                 tegra_dsi_set_timeout(dsi);
1051         }
1052
1053         tegra_dsi_set_control_reg_lp(dsi);
1054
1055         if ((dsi->status.clk_out == DSI_PHYCLK_OUT_DIS) &&
1056                 (dsi->info.enable_hs_clock_on_lp_cmd_mode))
1057                 tegra_dsi_hs_clk_out_enable_in_lp(dsi);
1058
1059 success:
1060         dsi->status.lphs = DSI_LPHS_IN_LP_MODE;
1061         err = 0;
1062 fail:
1063         return err;
1064 }
1065
1066 static int tegra_dsi_set_to_hs_mode(struct tegra_dc *dc,
1067                                                 struct tegra_dc_dsi_data *dsi)
1068 {
1069         int err;
1070
1071         if (dsi->status.init != DSI_MODULE_INIT) {
1072                 err = -EPERM;
1073                 goto fail;
1074         }
1075
1076         if (dsi->status.dc_stream == DSI_DC_STREAM_ENABLE)
1077                 tegra_dsi_stop_dc_stream_at_frame_end(dc, dsi);
1078
1079         if ((dsi->status.clk_out == DSI_PHYCLK_OUT_EN) &&
1080                 (!dsi->info.enable_hs_clock_on_lp_cmd_mode))
1081                 tegra_dsi_hs_clk_out_disable(dc, dsi);
1082
1083         if (dsi->current_dsi_clk_khz != dsi->target_hs_clk_khz) {
1084                 tegra_dsi_set_dsi_clk(dc, dsi, dsi->target_hs_clk_khz);
1085                 tegra_dsi_set_timeout(dsi);
1086         }
1087
1088         tegra_dsi_set_phy_timing(dsi);
1089
1090         if (dsi->driven_mode == TEGRA_DSI_DRIVEN_BY_DC){
1091                 tegra_dsi_set_pkt_seq(dc, dsi);
1092                 tegra_dsi_set_pkt_length(dc, dsi);
1093                 tegra_dsi_set_sol_delay(dc, dsi);
1094                 tegra_dsi_set_dc_clk(dc, dsi);
1095         }
1096
1097         tegra_dsi_set_control_reg_hs(dsi);
1098
1099         if (dsi->status.clk_out == DSI_PHYCLK_OUT_DIS)
1100                 tegra_dsi_hs_clk_out_enable(dsi);
1101
1102         dsi->status.lphs = DSI_LPHS_IN_HS_MODE;
1103         err = 0;
1104 fail:
1105         return err;
1106 }
1107
1108 static bool tegra_dsi_is_controller_idle(struct tegra_dc_dsi_data *dsi)
1109 {
1110         u32 timeout = 0;
1111         bool retVal;
1112
1113         retVal = false;
1114         while (timeout <= DSI_MAX_COMMAND_DELAY_USEC) {
1115                 if (!tegra_dsi_readl(dsi, DSI_TRIGGER)) {
1116                         retVal = true;
1117                         break;
1118                 }
1119                 udelay(DSI_COMMAND_DELAY_STEPS_USEC);
1120                 timeout += DSI_COMMAND_DELAY_STEPS_USEC;
1121         }
1122
1123         return retVal;
1124 }
1125
1126 static bool tegra_dsi_host_trigger(struct tegra_dc_dsi_data *dsi)
1127 {
1128         bool status;
1129         u32 val;
1130
1131         status = false;
1132
1133         if (tegra_dsi_readl(dsi, DSI_TRIGGER))
1134                 goto fail;
1135
1136 #if DSI_USE_SYNC_POINTS
1137         val = DSI_INCR_SYNCPT_COND(OP_DONE) |
1138                 DSI_INCR_SYNCPT_INDX(dsi->syncpt_id);
1139         tegra_dsi_writel(dsi, val, DSI_INCR_SYNCPT);
1140
1141         dsi->syncpt_val = nvhost_syncpt_read(
1142                         &dsi->dc->ndev->host->syncpt, dsi->syncpt_id);
1143
1144         tegra_dsi_writel(dsi,
1145                 DSI_TRIGGER_HOST_TRIGGER(TEGRA_DSI_ENABLE), DSI_TRIGGER);
1146
1147         /* TODO: Use interrupt rather than polling */
1148         if (nvhost_syncpt_wait(&dsi->dc->ndev->host->syncpt,
1149                 dsi->syncpt_id, dsi->syncpt_val + 1) < 0) {
1150                 printk(KERN_ERR "DSI sync point failure\n");
1151                 status = false;
1152                 goto fail;
1153         }
1154
1155         (dsi->syncpt_val)++;
1156         status = true;
1157 #else
1158         tegra_dsi_writel(dsi,
1159                 DSI_TRIGGER_HOST_TRIGGER(TEGRA_DSI_ENABLE), DSI_TRIGGER);
1160         status = tegra_dsi_is_controller_idle(dsi);
1161 #endif
1162
1163 fail:
1164         return status;
1165 }
1166
1167 static int _tegra_dsi_write_data(struct tegra_dc_dsi_data *dsi,
1168                                         u8* pdata, u8 data_id, u16 data_len)
1169 {
1170         u8 virtual_channel;
1171         u8 *pval;
1172         u32 val;
1173         int err;
1174
1175         err = 0;
1176
1177         virtual_channel = dsi->info.virtual_channel << DSI_VIR_CHANNEL_BIT_POSITION;
1178
1179         /* always use hw for ecc */
1180         val = (virtual_channel | data_id) << 0 |
1181                         data_len << 8;
1182         tegra_dsi_writel(dsi, val, DSI_WR_DATA);
1183
1184         /* if pdata != NULL, pkt type is long pkt */
1185         if (pdata != NULL) {
1186                 while (data_len) {
1187                         if (data_len >= 4) {
1188                                 val = ((u32*) pdata)[0];
1189                                 data_len -= 4;
1190                                 pdata += 4;
1191                         } else {
1192                                 val = 0;
1193                                 pval = (u8*) &val;
1194                                 do
1195                                         *pval++ = *pdata++;
1196                                 while(--data_len);
1197                         }
1198                         tegra_dsi_writel(dsi, val, DSI_WR_DATA);
1199                 }
1200         }
1201
1202         if (!tegra_dsi_host_trigger(dsi))
1203                 err = -EIO;
1204
1205         return err;
1206 }
1207
1208 static int tegra_dsi_write_data(struct tegra_dc *dc,
1209                                         struct tegra_dc_dsi_data *dsi,
1210                                         u8* pdata, u8 data_id, u16 data_len)
1211 {
1212         bool switch_back_to_hs_mode;
1213         bool switch_back_to_dc_mode;
1214         int err;
1215
1216         err = 0;
1217         switch_back_to_hs_mode = false;
1218         switch_back_to_dc_mode = false;
1219
1220         if ((dsi->status.init != DSI_MODULE_INIT) ||
1221                 (dsi->status.lphs == DSI_LPHS_NOT_INIT)) {
1222                 err = -EPERM;
1223                 goto fail;
1224         }
1225
1226         if (!tegra_dsi_is_controller_idle(dsi)) {
1227                 err = -EBUSY;
1228                 goto fail;
1229         }
1230
1231         err = 0;
1232
1233         if (dsi->status.lphs == DSI_LPHS_IN_HS_MODE) {
1234                 if (dsi->info.hs_cmd_mode_supported) {
1235                         if (dsi->status.driven == DSI_DRIVEN_MODE_DC) {
1236                                 dsi->driven_mode = TEGRA_DSI_DRIVEN_BY_HOST;
1237                                 tegra_dsi_set_to_hs_mode(dc, dsi);
1238                                 switch_back_to_dc_mode = true;
1239                         }
1240                 } else {
1241                         tegra_dsi_set_to_lp_mode(dc, dsi);
1242                         switch_back_to_hs_mode = true;
1243                 }
1244         }
1245
1246         err = _tegra_dsi_write_data(dsi, pdata, data_id, data_len);
1247
1248
1249         if (switch_back_to_dc_mode)
1250                 dsi->driven_mode = TEGRA_DSI_DRIVEN_BY_DC;
1251         if (switch_back_to_dc_mode || switch_back_to_hs_mode)
1252                 tegra_dsi_set_to_hs_mode(dc, dsi);
1253
1254 fail:
1255         return err;
1256 }
1257
1258 static int tegra_dsi_send_panel_cmd(struct tegra_dc *dc,
1259                                                 struct tegra_dc_dsi_data *dsi,
1260                                                 struct tegra_dsi_cmd *cmd,
1261                                                 u32 n_cmd)
1262 {
1263         u32 i;
1264         int err;
1265
1266         err = 0;
1267         for (i = 0; i < n_cmd; i++) {
1268                 struct tegra_dsi_cmd *cur_cmd;
1269                 cur_cmd = &cmd[i];
1270
1271                 if (cur_cmd->cmd_type == TEGRA_DSI_DELAY_MS)
1272                         mdelay(cur_cmd->sp_len_dly.delay_ms);
1273                 else {
1274                         err = tegra_dsi_write_data(dc, dsi,
1275                                                 cur_cmd->pdata,
1276                                                 cur_cmd->data_id,
1277                                                 cur_cmd->sp_len_dly.data_len);
1278                         if (err < 0)
1279                                 break;
1280                 }
1281         }
1282         return err;
1283 }
1284
1285 static int tegra_dsi_bta(struct tegra_dc_dsi_data *dsi)
1286 {
1287         u32 val;
1288         u32 poll_time;
1289         int err;
1290
1291         poll_time = 0;
1292         err = 0;
1293
1294 #if DSI_USE_SYNC_POINTS
1295         val = DSI_INCR_SYNCPT_COND(OP_DONE) |
1296                 DSI_INCR_SYNCPT_INDX(dsi->syncpt_id);
1297         tegra_dsi_writel(dsi, val, DSI_INCR_SYNCPT);
1298
1299         /* FIXME: Workaround for nvhost_syncpt_read */
1300         dsi->syncpt_val = nvhost_syncpt_update_min(
1301                         &dsi->dc->ndev->host->syncpt, dsi->syncpt_id);
1302
1303         val = tegra_dsi_readl(dsi, DSI_HOST_DSI_CONTROL);
1304         val |= DSI_HOST_DSI_CONTROL_IMM_BTA(TEGRA_DSI_ENABLE);
1305         tegra_dsi_writel(dsi, val, DSI_HOST_DSI_CONTROL);
1306
1307         /* TODO: Use interrupt rather than polling */
1308         err = nvhost_syncpt_wait(&dsi->dc->ndev->host->syncpt,
1309                 dsi->syncpt_id, dsi->syncpt_val + 1);
1310         if (err < 0)
1311                 printk(KERN_ERR "DSI sync point failure\n");
1312         else
1313                 (dsi->syncpt_val)++;
1314 #else
1315         val = tegra_dsi_readl(dsi, DSI_HOST_DSI_CONTROL);
1316         val |= DSI_HOST_DSI_CONTROL_IMM_BTA(TEGRA_DSI_ENABLE);
1317         tegra_dsi_writel(dsi, val, DSI_HOST_DSI_CONTROL);
1318
1319         while (poll_time <  DSI_STATUS_POLLING_DURATION_USEC) {
1320                 val = tegra_dsi_readl(dsi, DSI_HOST_DSI_CONTROL);
1321                 val &= DSI_HOST_DSI_CONTROL_IMM_BTA(TEGRA_DSI_ENABLE);
1322                 if (!val)
1323                         break;
1324                 udelay(DSI_STATUS_POLLING_DELAY_USEC);
1325                 poll_time += DSI_STATUS_POLLING_DELAY_USEC;
1326         }
1327         if (poll_time > DSI_STATUS_POLLING_DURATION_USEC)
1328                 err = -EBUSY;
1329 #endif
1330
1331         return err;
1332 }
1333
1334 static void tegra_dsi_read_fifo(struct tegra_dc *dc,
1335                         struct tegra_dc_dsi_data *dsi,
1336                         u32 rd_fifo_cnt,
1337                         u8 *read_fifo)
1338 {
1339         u32 val;
1340         u32 i;
1341
1342         /* Read data from FIFO */
1343         for (i = 0; i < rd_fifo_cnt; i++) {
1344                 val = tegra_dsi_readl(dsi, DSI_RD_DATA);
1345                 printk(KERN_INFO "Read data[%d]: 0x%x\n", i, val);
1346                 memcpy(read_fifo, &val, 4);
1347                 read_fifo += 4;
1348         }
1349
1350         /* Make sure all the data is read from the FIFO */
1351         val = tegra_dsi_readl(dsi, DSI_STATUS);
1352         val &= DSI_STATUS_RD_FIFO_COUNT(0x1f);
1353         if (val)
1354                 dev_err(&dc->ndev->dev, "DSI FIFO_RD_CNT not zero"
1355                 " even after reading FIFO_RD_CNT words from read fifo\n");
1356 }
1357
1358 static int tegra_dsi_parse_read_response(struct tegra_dc *dc,
1359                                 u32 rd_fifo_cnt, u8 *read_fifo)
1360 {
1361         int err;
1362         u32 payload_size;
1363
1364         payload_size = 0;
1365         err = 0;
1366
1367         printk(KERN_INFO "escape sequence[0x%x]\n", read_fifo[0]);
1368         switch (read_fifo[4] & 0xff) {
1369         case GEN_LONG_RD_RES:
1370                 /* Fall through */
1371         case DCS_LONG_RD_RES:
1372                 payload_size = (read_fifo[5] |
1373                                 (read_fifo[6] << 8)) & 0xFFFF;
1374                 printk(KERN_INFO "Long read response Packet\n"
1375                                 "payload_size[0x%x]\n", payload_size);
1376                 break;
1377         case GEN_1_BYTE_SHORT_RD_RES:
1378                 /* Fall through */
1379         case DCS_1_BYTE_SHORT_RD_RES:
1380                 payload_size = 1;
1381                 printk(KERN_INFO "Short read response Packet\n"
1382                         "payload_size[0x%x]\n", payload_size);
1383                 break;
1384         case GEN_2_BYTE_SHORT_RD_RES:
1385                 /* Fall through */
1386         case DCS_2_BYTE_SHORT_RD_RES:
1387                 payload_size = 2;
1388                 printk(KERN_INFO "Short read response Packet\n"
1389                         "payload_size[0x%x]\n", payload_size);
1390                 break;
1391         case ACK_ERR_RES:
1392                 payload_size = 2;
1393                 printk(KERN_INFO "Acknowledge error report response\n"
1394                         "Packet payload_size[0x%x]\n", payload_size);
1395                 break;
1396         default:
1397                 /*reading from RD_FIFO_COUNT*/
1398                 printk(KERN_INFO "Invalid read response payload_size\n");
1399                 err = -EINVAL;
1400                 break;
1401         }
1402         return err;
1403 }
1404
1405 static int tegra_dsi_read_data(struct tegra_dc *dc,
1406                                 struct tegra_dc_dsi_data *dsi,
1407                                 u32 max_ret_payload_size,
1408                                 u32 panel_reg_addr, u8 *read_data)
1409 {
1410         u32 val;
1411         int err;
1412         u32 poll_time;
1413         u32 rd_fifo_cnt;
1414         bool switch_back_to_hs_mode;
1415         bool restart_dc_stream;
1416         bool switch_back_to_dc_mode;
1417
1418         err = 0;
1419         switch_back_to_hs_mode = false;
1420         restart_dc_stream = false;
1421         switch_back_to_dc_mode = false;
1422
1423         if ((dsi->status.init != DSI_MODULE_INIT) ||
1424                 (dsi->status.lphs == DSI_LPHS_NOT_INIT) ||
1425                 (dsi->status.driven == DSI_DRIVEN_MODE_NOT_INIT)) {
1426                 err = -EPERM;
1427                 goto fail;
1428         }
1429
1430         val = tegra_dsi_readl(dsi, DSI_STATUS);
1431         val &= DSI_STATUS_RD_FIFO_COUNT(0x1f);
1432         if (val) {
1433                 err = -EBUSY;
1434                 dev_err(&dc->ndev->dev, "DSI fifo count not zero\n");
1435                 goto fail;
1436         }
1437
1438         if (!tegra_dsi_is_controller_idle(dsi)) {
1439                 err = -EBUSY;
1440                 dev_err(&dc->ndev->dev, "DSI trigger bit is already set\n");
1441                 goto fail;
1442         }
1443
1444         if (dsi->status.lphs == DSI_LPHS_IN_HS_MODE) {
1445                 if (dsi->status.driven == DSI_DRIVEN_MODE_DC) {
1446                         if (dsi->status.dc_stream == DSI_DC_STREAM_ENABLE)
1447                                 restart_dc_stream = true;
1448                         dsi->driven_mode = TEGRA_DSI_DRIVEN_BY_HOST;
1449                         switch_back_to_dc_mode = true;
1450                         if (dsi->info.hs_cmd_mode_supported) {
1451                                 err = tegra_dsi_set_to_hs_mode(dc, dsi);
1452                                 if (err < 0) {
1453                                         dev_err(&dc->ndev->dev,
1454                                         "DSI failed to go to HS mode host driven\n");
1455                                         goto fail;
1456                                 }
1457                         }
1458                 }
1459                 if (!dsi->info.hs_cmd_mode_supported) {
1460                         err = tegra_dsi_set_to_lp_mode(dc, dsi);
1461                         if (err < 0) {
1462                                 dev_err(&dc->ndev->dev,
1463                                 "DSI failed to go to LP mode\n");
1464                                 goto fail;
1465                         }
1466                         switch_back_to_hs_mode = true;
1467                 }
1468         }
1469
1470         /* Set max return payload size in words */
1471         err = _tegra_dsi_write_data(dsi, NULL,
1472                 dsi_command_max_return_pkt_size,
1473                 max_ret_payload_size);
1474         if (err < 0) {
1475                 dev_err(&dc->ndev->dev,
1476                                 "DSI write failed\n");
1477                 goto fail;
1478         }
1479
1480         /* DCS to read given panel register */
1481         err = _tegra_dsi_write_data(dsi, NULL,
1482                 dsi_command_dcs_read_with_no_params,
1483                 panel_reg_addr);
1484         if (err < 0) {
1485                 dev_err(&dc->ndev->dev,
1486                                 "DSI write failed\n");
1487                 goto fail;
1488         }
1489
1490         err = tegra_dsi_bta(dsi);
1491         if (err < 0) {
1492                 dev_err(&dc->ndev->dev,
1493                         "DSI IMM BTA timeout\n");
1494                 goto fail;
1495         }
1496
1497         poll_time = 0;
1498         while (poll_time <  DSI_DELAY_FOR_READ_FIFO) {
1499                 mdelay(1);
1500                 val = tegra_dsi_readl(dsi, DSI_STATUS);
1501                 rd_fifo_cnt = val & DSI_STATUS_RD_FIFO_COUNT(0x1f);
1502                 if (rd_fifo_cnt << 2 > DSI_READ_FIFO_DEPTH)
1503                         dev_err(&dc->ndev->dev,
1504                         "DSI RD_FIFO_CNT is greater than RD_FIFO_DEPTH\n");
1505                         break;
1506                 poll_time++;
1507         }
1508
1509         if (rd_fifo_cnt == 0) {
1510                 dev_info(&dc->ndev->dev,
1511                         "DSI RD_FIFO_CNT is zero\n");
1512                 err = -EINVAL;
1513                 goto fail;
1514         }
1515
1516         if (val & DSI_STATUS_LB_UNDERFLOW(0x1) ||
1517                 val & DSI_STATUS_LB_OVERFLOW(0x1)) {
1518                 dev_err(&dc->ndev->dev,
1519                         "DSI overflow/underflow error\n");
1520                 err = -EINVAL;
1521                 goto fail;
1522         }
1523
1524         tegra_dsi_read_fifo(dc, dsi, rd_fifo_cnt, read_data);
1525
1526         err = tegra_dsi_parse_read_response(dc, rd_fifo_cnt, read_data);
1527 fail:
1528         if (switch_back_to_dc_mode)
1529                 dsi->driven_mode = TEGRA_DSI_DRIVEN_BY_DC;
1530         if (switch_back_to_dc_mode || switch_back_to_hs_mode)
1531                 tegra_dsi_set_to_hs_mode(dc, dsi);
1532         if (restart_dc_stream)
1533                 tegra_dsi_start_dc_stream(dc, dsi);
1534
1535         return err;
1536 }
1537
1538 static void tegra_dsi_enter_ulpm(struct tegra_dc_dsi_data *dsi)
1539 {
1540         u32 val;
1541
1542         val = tegra_dsi_readl(dsi, DSI_HOST_DSI_CONTROL);
1543         val &= ~DSI_HOST_DSI_CONTROL_ULTRA_LOW_POWER(3);
1544         val |= DSI_HOST_DSI_CONTROL_ULTRA_LOW_POWER(ENTER_ULPM);
1545         tegra_dsi_writel(dsi, val, DSI_HOST_DSI_CONTROL);
1546
1547         dsi->ulpm = true;
1548 }
1549
1550 static void tegra_dsi_exit_ulpm(struct tegra_dc_dsi_data *dsi)
1551 {
1552         u32 val;
1553
1554         val = tegra_dsi_readl(dsi, DSI_HOST_DSI_CONTROL);
1555         val &= ~DSI_HOST_DSI_CONTROL_ULTRA_LOW_POWER(3);
1556         val |= DSI_HOST_DSI_CONTROL_ULTRA_LOW_POWER(EXIT_ULPM);
1557         tegra_dsi_writel(dsi, val, DSI_HOST_DSI_CONTROL);
1558
1559         val &= ~DSI_HOST_DSI_CONTROL_ULTRA_LOW_POWER(3);
1560         val |= DSI_HOST_DSI_CONTROL_ULTRA_LOW_POWER(NORMAL);
1561         tegra_dsi_writel(dsi, val, DSI_HOST_DSI_CONTROL);
1562
1563         /* TODO: Find exact delay required */
1564         mdelay(5);
1565         dsi->ulpm = false;
1566 }
1567
1568 static void tegra_dc_dsi_enable(struct tegra_dc *dc)
1569 {
1570         struct tegra_dc_dsi_data *dsi = tegra_dc_get_outdata(dc);
1571         int err;
1572
1573         tegra_dc_io_start(dc);
1574         mutex_lock(&dsi->lock);
1575
1576         /* Stop DC stream before configuring DSI registers
1577          * to avoid visible glitches on panel during transition
1578          * from bootloader to kernel driver
1579          */
1580         tegra_dsi_stop_dc_stream_at_frame_end(dc, dsi);
1581
1582         if (dsi->ulpm) {
1583                 tegra_dsi_exit_ulpm(dsi);
1584                 if (dsi->info.panel_reset) {
1585                         err = tegra_dsi_send_panel_cmd(dc, dsi,
1586                                                         dsi->info.dsi_init_cmd,
1587                                                         dsi->info.n_init_cmd);
1588                         if (err < 0) {
1589                                 dev_err(&dc->ndev->dev,
1590                                 "dsi: error while sending dsi init cmd\n");
1591                                 return;
1592                         }
1593                 }
1594         } else {
1595                 err = tegra_dsi_init_hw(dc, dsi);
1596                 if (err < 0) {
1597                         dev_err(&dc->ndev->dev,
1598                                 "dsi: not able to init dsi hardware\n");
1599                         return;
1600                 }
1601
1602                 err = tegra_dsi_set_to_lp_mode(dc, dsi);
1603                 if (err < 0) {
1604                         dev_err(&dc->ndev->dev,
1605                                 "dsi: not able to set to lp mode\n");
1606                         return;
1607                 }
1608
1609                 err = tegra_dsi_send_panel_cmd(dc, dsi, dsi->info.dsi_init_cmd,
1610                                                 dsi->info.n_init_cmd);
1611                 if (err < 0) {
1612                         dev_err(&dc->ndev->dev,
1613                                 "dsi: error while sending dsi init cmd\n");
1614                         return;
1615                 }
1616
1617                 err = tegra_dsi_set_to_hs_mode(dc, dsi);
1618                 if (err < 0) {
1619                                 dev_err(&dc->ndev->dev,
1620                                         "dsi: not able to set to hs mode\n");
1621                         return;
1622                 }
1623         }
1624
1625         if (dsi->status.driven == DSI_DRIVEN_MODE_DC) {
1626                 tegra_dsi_start_dc_stream(dc, dsi);
1627         }
1628
1629         mutex_unlock(&dsi->lock);
1630         tegra_dc_io_end(dc);
1631 }
1632
1633 static void _tegra_dc_dsi_init(struct tegra_dc *dc)
1634 {
1635         struct tegra_dc_dsi_data *dsi = tegra_dc_get_outdata(dc);
1636
1637         tegra_dsi_init_sw(dc, dsi);
1638         /* TODO: Configure the CSI pad configuration */
1639 }
1640
1641 static int tegra_dc_dsi_cp_p_cmd(struct tegra_dsi_cmd* src,
1642                                         struct tegra_dsi_cmd* dst, u16 n_cmd)
1643 {
1644         u16 i;
1645         u16 len;
1646
1647         memcpy(dst, src, sizeof(*dst) * n_cmd);
1648
1649         for (i = 0; i < n_cmd; i++)
1650                 if (src[i].pdata) {
1651                         len = sizeof(*src[i].pdata) * src[i].sp_len_dly.data_len;
1652                         dst[i].pdata = kzalloc(len, GFP_KERNEL);
1653                         if (!dst[i].pdata)
1654                                 goto free_cmd_pdata;
1655                         memcpy(dst[i].pdata, src[i].pdata, len);
1656                 }
1657
1658         return 0;
1659
1660 free_cmd_pdata:
1661         for (--i; i >=0; i--)
1662                 if (dst[i].pdata)
1663                         kfree(dst[i].pdata);
1664         return -ENOMEM;
1665 }
1666
1667 static int tegra_dc_dsi_cp_info(struct tegra_dc_dsi_data* dsi,
1668                                                 struct tegra_dsi_out* p_dsi)
1669 {
1670         struct tegra_dsi_cmd* p_init_cmd;
1671         struct tegra_dsi_cmd *p_suspend_cmd;
1672         int err;
1673
1674         if (p_dsi->n_data_lanes > MAX_DSI_DATA_LANES)
1675                 return -EINVAL;
1676
1677         p_init_cmd = kzalloc(sizeof(*p_init_cmd) * p_dsi->n_init_cmd, GFP_KERNEL);
1678         if (!p_init_cmd)
1679                 return -ENOMEM;
1680
1681         p_suspend_cmd = kzalloc(sizeof(*p_suspend_cmd) * p_dsi->n_suspend_cmd,
1682                                 GFP_KERNEL);
1683         if (!p_suspend_cmd) {
1684                 err = -ENOMEM;
1685                 goto err_free_p_init_cmd;
1686         }
1687
1688         memcpy(&dsi->info, p_dsi, sizeof(dsi->info));
1689
1690         err = tegra_dc_dsi_cp_p_cmd(p_dsi->dsi_init_cmd,
1691                                                 p_init_cmd, p_dsi->n_init_cmd);
1692         if (err < 0)
1693                 goto err_free;
1694         dsi->info.dsi_init_cmd = p_init_cmd;
1695
1696         err = tegra_dc_dsi_cp_p_cmd(p_dsi->dsi_suspend_cmd, p_suspend_cmd,
1697                                         p_dsi->n_suspend_cmd);
1698         if (err < 0)
1699                 goto err_free;
1700         dsi->info.dsi_suspend_cmd = p_suspend_cmd;
1701
1702         if (!dsi->info.panel_reset_timeout_msec)
1703                 dsi->info.panel_reset_timeout_msec = DEFAULT_PANEL_RESET_TIMEOUT;
1704
1705         if (!dsi->info.panel_buffer_size_byte)
1706                 dsi->info.panel_buffer_size_byte = DEFAULT_PANEL_BUFFER_BYTE;
1707
1708         if (!dsi->info.max_panel_freq_khz)
1709                 dsi->info.max_panel_freq_khz = DEFAULT_MAX_DSI_PHY_CLK_KHZ;
1710
1711         if (!dsi->info.lp_cmd_mode_freq_khz)
1712                 dsi->info.lp_cmd_mode_freq_khz = DEFAULT_LP_CMD_MODE_CLK_KHZ;
1713
1714         /* host mode is for testing only*/
1715         dsi->driven_mode = TEGRA_DSI_DRIVEN_BY_DC;
1716
1717         return 0;
1718
1719 err_free:
1720         kfree(p_suspend_cmd);
1721 err_free_p_init_cmd:
1722         kfree(p_init_cmd);
1723         return err;
1724 }
1725
1726 static int tegra_dc_dsi_init(struct tegra_dc *dc)
1727 {
1728         struct tegra_dc_dsi_data *dsi;
1729         struct resource *res;
1730         struct resource *base_res;
1731         void __iomem *base;
1732         struct clk *dc_clk = NULL;
1733         struct clk *dsi_clk = NULL;
1734         struct tegra_dsi_out *dsi_pdata;
1735         int err;
1736
1737         err = 0;
1738
1739         dsi = kzalloc(sizeof(*dsi), GFP_KERNEL);
1740         if (!dsi)
1741                 return -ENOMEM;
1742
1743         res = nvhost_get_resource_byname(dc->ndev, IORESOURCE_MEM,
1744                                         "dsi_regs");
1745         if (!res) {
1746                 dev_err(&dc->ndev->dev, "dsi: no mem resource\n");
1747                 err = -ENOENT;
1748                 goto err_free_dsi;
1749         }
1750
1751         base_res = request_mem_region(res->start, resource_size(res),
1752                                 dc->ndev->name);
1753         if (!base_res) {
1754                 dev_err(&dc->ndev->dev, "dsi: request_mem_region failed\n");
1755                 err = -EBUSY;
1756                 goto err_free_dsi;
1757         }
1758
1759         base = ioremap(res->start, resource_size(res));
1760         if (!base) {
1761                 dev_err(&dc->ndev->dev, "dsi: registers can't be mapped\n");
1762                 err = -EBUSY;
1763                 goto err_release_regs;
1764         }
1765
1766         dsi_pdata = dc->pdata->default_out->dsi;
1767         if (!dsi_pdata) {
1768                 dev_err(&dc->ndev->dev, "dsi: dsi data not available\n");
1769                 goto err_release_regs;
1770         }
1771
1772         if (dsi_pdata->dsi_instance)
1773                 dsi_clk = clk_get(&dc->ndev->dev, "dsib");
1774         else
1775                 dsi_clk = clk_get(&dc->ndev->dev, "dsia");
1776
1777         if (IS_ERR_OR_NULL(dsi_clk)) {
1778                 dev_err(&dc->ndev->dev, "dsi: can't get clock\n");
1779                 err = -EBUSY;
1780                 goto err_release_regs;
1781         }
1782
1783         dc_clk = clk_get_sys(dev_name(&dc->ndev->dev), NULL);
1784         if (IS_ERR_OR_NULL(dc_clk)) {
1785                 dev_err(&dc->ndev->dev, "dsi: dc clock %s unavailable\n",
1786                         dev_name(&dc->ndev->dev));
1787                 err = -EBUSY;
1788                 goto err_clk_put;
1789         }
1790
1791         err = tegra_dc_dsi_cp_info(dsi, dsi_pdata);
1792         if (err < 0)
1793                 goto err_dsi_data;
1794
1795         mutex_init(&dsi->lock);
1796         dsi->dc = dc;
1797         dsi->base = base;
1798         dsi->base_res = base_res;
1799         dsi->dc_clk = dc_clk;
1800         dsi->dsi_clk = dsi_clk;
1801
1802         tegra_dc_set_outdata(dc, dsi);
1803         _tegra_dc_dsi_init(dc);
1804
1805         return 0;
1806
1807 err_dsi_data:
1808 err_clk_put:
1809         clk_put(dsi_clk);
1810 err_release_regs:
1811         release_resource(base_res);
1812 err_free_dsi:
1813         kfree(dsi);
1814
1815         return err;
1816 }
1817
1818 static void tegra_dc_dsi_destroy(struct tegra_dc *dc)
1819 {
1820         struct tegra_dc_dsi_data *dsi = tegra_dc_get_outdata(dc);
1821         u16 i;
1822         u32 val;
1823
1824         mutex_lock(&dsi->lock);
1825
1826         /* free up the pdata*/
1827         for(i = 0; i < dsi->info.n_init_cmd; i++){
1828                 if(dsi->info.dsi_init_cmd[i].pdata)
1829                         kfree(dsi->info.dsi_init_cmd[i].pdata);
1830         }
1831         kfree(dsi->info.dsi_init_cmd);
1832
1833         /* Disable dc stream*/
1834         if(dsi->status.dc_stream == DSI_DC_STREAM_ENABLE)
1835                 tegra_dsi_stop_dc_stream(dc, dsi);
1836
1837         /* Disable dsi phy clock*/
1838         if(dsi->status.clk_out == DSI_PHYCLK_OUT_EN)
1839                 tegra_dsi_hs_clk_out_disable(dc, dsi);
1840
1841         val = DSI_POWER_CONTROL_LEG_DSI_ENABLE(TEGRA_DSI_DISABLE);
1842         tegra_dsi_writel(dsi, val, DSI_POWER_CONTROL);
1843
1844         iounmap(dsi->base);
1845         release_resource(dsi->base_res);
1846
1847         clk_put(dsi->dc_clk);
1848         clk_put(dsi->dsi_clk);
1849
1850         mutex_unlock(&dsi->lock);
1851
1852         mutex_destroy(&dsi->lock);
1853         kfree(dsi);
1854 }
1855
1856 static void tegra_dc_dsi_disable(struct tegra_dc *dc)
1857 {
1858         struct tegra_dc_dsi_data *dsi = tegra_dc_get_outdata(dc);
1859
1860         mutex_lock(&dsi->lock);
1861
1862         if (dsi->status.dc_stream == DSI_DC_STREAM_ENABLE)
1863                 tegra_dsi_stop_dc_stream(dc, dsi);
1864
1865         if (!dsi->ulpm)
1866                 tegra_dsi_enter_ulpm(dsi);
1867
1868         mutex_unlock(&dsi->lock);
1869 }
1870
1871 #ifdef CONFIG_PM
1872 static void tegra_dc_dsi_suspend(struct tegra_dc *dc)
1873 {
1874         struct tegra_dc_dsi_data *dsi;
1875         int err;
1876
1877         dsi = tegra_dc_get_outdata(dc);
1878
1879         tegra_dc_io_start(dc);
1880         mutex_lock(&dsi->lock);
1881
1882         if (dsi->ulpm)
1883                 tegra_dsi_exit_ulpm(dsi);
1884
1885         err = tegra_dsi_send_panel_cmd(dc, dsi, dsi->info.dsi_suspend_cmd,
1886                                 dsi->info.n_suspend_cmd);
1887         if (err < 0) {
1888                 dev_err(&dc->ndev->dev,
1889                         "dsi: error while sending dsi suspend cmd\n");
1890                 return;
1891         }
1892
1893         clk_disable(dsi->dsi_clk);
1894
1895         mutex_unlock(&dsi->lock);
1896         tegra_dc_io_end(dc);
1897 }
1898
1899 static void tegra_dc_dsi_resume(struct tegra_dc *dc)
1900 {
1901         /* Not required since tegra_dc_dsi_enable
1902          * will reconfigure the controller from scratch
1903          */
1904 }
1905 #endif
1906
1907 struct tegra_dc_out_ops tegra_dc_dsi_ops = {
1908         .init = tegra_dc_dsi_init,
1909         .destroy = tegra_dc_dsi_destroy,
1910         .enable = tegra_dc_dsi_enable,
1911         .disable = tegra_dc_dsi_disable,
1912 #ifdef CONFIG_PM
1913         .suspend = tegra_dc_dsi_suspend,
1914         .resume = tegra_dc_dsi_resume,
1915 #endif
1916 };