video: dsi: tegra: Read from dsi panel
[linux-2.6.git] / drivers / video / tegra / dc / dsi.c
1 /*
2  * drivers/video/tegra/dc/dsi.c
3  *
4  * Copyright (c) 2011, NVIDIA Corporation.
5  *
6  * This software is licensed under the terms of the GNU General Public
7  * License version 2, as published by the Free Software Foundation, and
8  * may be copied, distributed, and modified under those terms.
9  *
10  * This program is distributed in the hope that it will be useful,
11  * but WITHOUT ANY WARRANTY; without even the implied warranty of
12  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
13  * GNU General Public License for more details.
14  *
15  */
16
17 #include <linux/clk.h>
18 #include <linux/delay.h>
19 #include <linux/err.h>
20 #include <linux/fb.h>
21 #include <linux/gpio.h>
22 #include <linux/interrupt.h>
23 #include <linux/kernel.h>
24 #include <linux/slab.h>
25 #include <linux/spinlock.h>
26 #include <linux/workqueue.h>
27
28 #include <mach/clk.h>
29 #include <mach/dc.h>
30 #include <mach/fb.h>
31 #include <mach/nvhost.h>
32 #include <../gpio-names.h>
33
34 #include "dc_reg.h"
35 #include "dc_priv.h"
36 #include "dsi_regs.h"
37 #include "dsi.h"
38
39 #define DSI_USE_SYNC_POINTS 0
40
41 #define DSI_STOP_DC_DURATION_MSEC 1000
42
43 #define DSI_MODULE_NOT_INIT             0x0
44 #define DSI_MODULE_INIT                 0x1
45
46 #define DSI_LPHS_NOT_INIT               0x0
47 #define DSI_LPHS_IN_LP_MODE             0x1
48 #define DSI_LPHS_IN_HS_MODE             0x2
49
50 #define DSI_VIDEO_TYPE_NOT_INIT         0x0
51 #define DSI_VIDEO_TYPE_VIDEO_MODE       0x1
52 #define DSI_VIDEO_TYPE_CMD_MODE         0x2
53
54 #define DSI_DRIVEN_MODE_NOT_INIT        0x0
55 #define DSI_DRIVEN_MODE_DC              0x1
56 #define DSI_DRIVEN_MODE_HOST            0x2
57
58 #define DSI_PHYCLK_OUT_DIS              0x0
59 #define DSI_PHYCLK_OUT_EN               0x1
60
61 #define DSI_PHYCLK_NOT_INIT             0x0
62 #define DSI_PHYCLK_CONTINUOUS           0x1
63 #define DSI_PHYCLK_TX_ONLY              0x2
64
65 #define DSI_CLK_BURST_NOT_INIT          0x0
66 #define DSI_CLK_BURST_NONE_BURST        0x1
67 #define DSI_CLK_BURST_BURST_MODE        0x2
68
69 #define DSI_DC_STREAM_DISABLE           0x0
70 #define DSI_DC_STREAM_ENABLE            0x1
71
72 struct dsi_status {
73         unsigned        init:2;
74
75         unsigned        lphs:2;
76
77         unsigned        vtype:2;
78         unsigned        driven:2;
79
80         unsigned        clk_out:2;
81         unsigned        clk_mode:2;
82         unsigned        clk_burst:2;
83
84         unsigned        dc_stream:1;
85 };
86
87 /* source of video data */
88 enum{
89         TEGRA_DSI_DRIVEN_BY_DC,
90         TEGRA_DSI_DRIVEN_BY_HOST,
91 };
92
93 struct tegra_dc_dsi_data {
94         struct tegra_dc *dc;
95         void __iomem    *base;
96         struct resource *base_res;
97
98         struct clk              *dc_clk;
99         struct clk              *dsi_clk;
100
101         struct mutex    lock;
102
103         /* data from board info */
104         struct tegra_dsi_out info;
105
106         struct dsi_status       status;
107
108         u8              driven_mode;
109         u8              controller_index;
110
111         u8              pixel_scaler_mul;
112         u8              pixel_scaler_div;
113
114         u32             default_pixel_clk_khz;
115         u32             default_hs_clk_khz;
116
117         u32             target_hs_clk_khz;
118         u32             target_lp_clk_khz;
119
120         u16             current_bit_clk_ns;
121         u32             current_dsi_clk_khz;
122
123         u32             dsi_control_val;
124 };
125
126 const u32 dsi_pkt_seq_reg[NUMOF_PKT_SEQ] = {
127         DSI_PKT_SEQ_0_LO,
128         DSI_PKT_SEQ_0_HI,
129         DSI_PKT_SEQ_1_LO,
130         DSI_PKT_SEQ_1_HI,
131         DSI_PKT_SEQ_2_LO,
132         DSI_PKT_SEQ_2_HI,
133         DSI_PKT_SEQ_3_LO,
134         DSI_PKT_SEQ_3_HI,
135         DSI_PKT_SEQ_4_LO,
136         DSI_PKT_SEQ_4_HI,
137         DSI_PKT_SEQ_5_LO,
138         DSI_PKT_SEQ_5_HI,
139 };
140
141 const u32 dsi_pkt_seq_video_non_burst_syne[NUMOF_PKT_SEQ] = {
142         PKT_ID0(CMD_VS) | PKT_LEN0(0) | PKT_ID1(CMD_EOT) | PKT_LEN1(0) | PKT_LP,
143         0,
144         PKT_ID0(CMD_VE) | PKT_LEN0(0) | PKT_ID1(CMD_EOT) | PKT_LEN1(0) | PKT_LP,
145         0,
146         PKT_ID0(CMD_HS) | PKT_LEN0(0) | PKT_ID1(CMD_EOT) | PKT_LEN1(0) | PKT_LP,
147         0,
148         PKT_ID0(CMD_HS) | PKT_LEN0(0) | PKT_ID1(CMD_BLNK) | PKT_LEN1(1) |
149                 PKT_ID2(CMD_HE) | PKT_LEN2(0),
150         PKT_ID3(CMD_BLNK) | PKT_LEN3(2) | PKT_ID4(CMD_RGB) | PKT_LEN4(3) |
151                 PKT_ID5(CMD_BLNK) | PKT_LEN5(4),
152         PKT_ID0(CMD_HS) | PKT_LEN0(0) | PKT_ID1(CMD_EOT) | PKT_LEN1(0) | PKT_LP,
153         0,
154         PKT_ID0(CMD_HS) | PKT_LEN0(0) | PKT_ID1(CMD_BLNK) | PKT_LEN1(1) |
155                 PKT_ID2(CMD_HE) | PKT_LEN2(0),
156         PKT_ID3(CMD_BLNK) | PKT_LEN3(2) | PKT_ID4(CMD_RGB) | PKT_LEN4(3) |
157                 PKT_ID5(CMD_BLNK) | PKT_LEN5(4),
158 };
159
160 const u32 dsi_pkt_seq_video_non_burst[NUMOF_PKT_SEQ] = {
161         PKT_ID0(CMD_VS) | PKT_LEN0(0) | PKT_ID1(CMD_EOT) | PKT_LEN1(0) | PKT_LP,
162         0,
163         PKT_ID0(CMD_HS) | PKT_LEN0(0) | PKT_ID1(CMD_EOT) | PKT_LEN1(0) | PKT_LP,
164         0,
165         PKT_ID0(CMD_HS) | PKT_LEN0(0) | PKT_ID1(CMD_EOT) | PKT_LEN1(0) | PKT_LP,
166         0,
167         PKT_ID0(CMD_HS) | PKT_LEN0(0) | PKT_ID1(CMD_BLNK) | PKT_LEN1(2) |
168                 PKT_ID2(CMD_RGB) | PKT_LEN2(3),
169         PKT_ID3(CMD_BLNK) | PKT_LEN3(4),
170         PKT_ID0(CMD_HS) | PKT_LEN0(0) | PKT_ID1(CMD_EOT) | PKT_LEN1(0) | PKT_LP,
171         0,
172         PKT_ID0(CMD_HS) | PKT_LEN0(0) | PKT_ID1(CMD_BLNK) | PKT_LEN1(2) |
173                 PKT_ID2(CMD_RGB) | PKT_LEN2(3),
174         PKT_ID3(CMD_BLNK) | PKT_LEN3(4),
175 };
176
177 static const u32 dsi_pkt_seq_video_burst[NUMOF_PKT_SEQ] = {
178         PKT_ID0(CMD_NULL) | PKT_LEN0(4) | PKT_ID1(CMD_VS) | PKT_LEN1(0) |
179                 PKT_ID2(CMD_EOT) | PKT_LEN2(0) | PKT_LP,
180         0,
181         PKT_ID0(CMD_NULL) | PKT_LEN0(4) | PKT_ID1(CMD_HS) | PKT_LEN1(0) |
182                 PKT_ID2(CMD_EOT) | PKT_LEN2(0) | PKT_LP,
183         0,
184         PKT_ID0(CMD_NULL) | PKT_LEN0(4) | PKT_ID1(CMD_HS) | PKT_LEN1(0) |
185                 PKT_ID2(CMD_EOT) | PKT_LEN2(0) | PKT_LP,
186         PKT_ID0(CMD_BLNK) | PKT_LEN0(4) | PKT_ID1(CMD_HS) | PKT_LEN1(0) |
187                 PKT_ID2(CMD_BLNK) | PKT_LEN2(2),
188         PKT_ID3(CMD_RGB) | PKT_LEN3(3) | PKT_ID4(CMD_EOT) | PKT_LEN4(0),
189         PKT_ID0(CMD_NULL) | PKT_LEN0(4) | PKT_ID1(CMD_HS) | PKT_LEN1(0) |
190                 PKT_ID2(CMD_EOT) | PKT_LEN2(0) | PKT_LP,
191         0,
192         PKT_ID0(CMD_BLNK) | PKT_LEN0(4) | PKT_ID1(CMD_HS) | PKT_LEN1(0) |
193                 PKT_ID2(CMD_BLNK) | PKT_LEN2(2),
194         PKT_ID3(CMD_RGB) | PKT_LEN3(3) | PKT_ID4(CMD_EOT) | PKT_LEN4(0),
195 };
196
197 /* TODO: verify with hw about this format */
198 const u32 dsi_pkt_seq_cmd_mode [NUMOF_PKT_SEQ] = {
199         0,
200         0,
201         0,
202         0,
203         0,
204         0,
205         PKT_ID0(CMD_LONGW) | PKT_LEN0(3) | PKT_ID1(CMD_EOT) | PKT_LEN1(7),
206         0,
207         0,
208         0,
209         PKT_ID0(CMD_LONGW) | PKT_LEN0(3) | PKT_ID1(CMD_EOT) | PKT_LEN1(7),
210         0,
211 };
212
213 const u32 init_reg[] = {
214         DSI_WR_DATA,
215         DSI_INT_ENABLE,
216         DSI_INT_STATUS,
217         DSI_INT_MASK,
218         DSI_INIT_SEQ_DATA_0,
219         DSI_INIT_SEQ_DATA_1,
220         DSI_INIT_SEQ_DATA_2,
221         DSI_INIT_SEQ_DATA_3,
222         DSI_DCS_CMDS,
223         DSI_PKT_SEQ_0_LO,
224         DSI_PKT_SEQ_1_LO,
225         DSI_PKT_SEQ_2_LO,
226         DSI_PKT_SEQ_3_LO,
227         DSI_PKT_SEQ_4_LO,
228         DSI_PKT_SEQ_5_LO,
229         DSI_PKT_SEQ_0_HI,
230         DSI_PKT_SEQ_1_HI,
231         DSI_PKT_SEQ_2_HI,
232         DSI_PKT_SEQ_3_HI,
233         DSI_PKT_SEQ_4_HI,
234         DSI_PKT_SEQ_5_HI,
235         DSI_CONTROL,
236         DSI_HOST_DSI_CONTROL,
237         DSI_PAD_CONTROL,
238         DSI_PAD_CONTROL_CD,
239         DSI_SOL_DELAY,
240         DSI_MAX_THRESHOLD,
241         DSI_TRIGGER,
242         DSI_TX_CRC,
243         DSI_INIT_SEQ_CONTROL,
244         DSI_PKT_LEN_0_1,
245         DSI_PKT_LEN_2_3,
246         DSI_PKT_LEN_4_5,
247         DSI_PKT_LEN_6_7,
248 };
249
250 static inline unsigned long tegra_dsi_readl(struct tegra_dc_dsi_data *dsi,
251                                                                         u32 reg)
252 {
253         return readl(dsi->base + reg * 4);
254 }
255
256 static inline void tegra_dsi_writel(struct tegra_dc_dsi_data *dsi,u32 val,
257                                                                         u32 reg)
258 {
259         writel(val, dsi->base + reg * 4);
260 }
261
262 static u32 tegra_dsi_get_hs_clk_rate(struct tegra_dc_dsi_data *dsi)
263 {
264         u32 dsi_clock_rate_khz;
265
266         switch (dsi->info.video_burst_mode) {
267         case TEGRA_DSI_VIDEO_BURST_MODE_LOW_SPEED:
268         case TEGRA_DSI_VIDEO_BURST_MODE_MEDIUM_SPEED:
269         case TEGRA_DSI_VIDEO_BURST_MODE_FAST_SPEED:
270         case TEGRA_DSI_VIDEO_BURST_MODE_FASTEST_SPEED:
271                 /* TODO: implement algo for these speed rate */
272
273         case TEGRA_DSI_VIDEO_BURST_MODE_MANUAL:
274                 if (dsi->info.burst_mode_freq_khz) {
275                         dsi_clock_rate_khz = dsi->info.burst_mode_freq_khz;
276                         break;
277                 }
278         case TEGRA_DSI_VIDEO_NONE_BURST_MODE:
279         case TEGRA_DSI_VIDEO_NONE_BURST_MODE_WITH_SYNC_END:
280         case TEGRA_DSI_VIDEO_BURST_MODE_LOWEST_SPEED:
281         default:
282                 dsi_clock_rate_khz = dsi->default_hs_clk_khz;
283                 break;
284         }
285
286         return dsi_clock_rate_khz;
287 }
288
289 static u32 tegra_dsi_get_lp_clk_rate(struct tegra_dc_dsi_data *dsi)
290 {
291         u32 dsi_clock_rate_khz;
292
293         if (dsi->info.enable_hs_clock_on_lp_cmd_mode)
294                 if (dsi->info.hs_clk_in_lp_cmd_mode_freq_khz)
295                         dsi_clock_rate_khz =
296                                 dsi->info.hs_clk_in_lp_cmd_mode_freq_khz;
297                 else
298                         dsi_clock_rate_khz = tegra_dsi_get_hs_clk_rate(dsi);
299         else
300                 dsi_clock_rate_khz = dsi->info.lp_cmd_mode_freq_khz;
301
302         return dsi_clock_rate_khz;
303 }
304
305 static void tegra_dsi_init_sw(struct tegra_dc *dc,
306                                                 struct tegra_dc_dsi_data *dsi)
307 {
308         u32 h_width_pixels;
309         u32 v_width_lines;
310         u32 pixel_clk_hz;
311         u32 byte_clk_hz;
312
313         switch (dsi->info.pixel_format) {
314                 case TEGRA_DSI_PIXEL_FORMAT_16BIT_P:
315                         /* 2 bytes per pixel */
316                         dsi->pixel_scaler_mul = 2;
317                         dsi->pixel_scaler_div = 1;
318                         break;
319                 case TEGRA_DSI_PIXEL_FORMAT_18BIT_P:
320                         /* 2.25 bytes per pixel */
321                         dsi->pixel_scaler_mul = 9;
322                         dsi->pixel_scaler_div = 4;
323                         break;
324                 case TEGRA_DSI_PIXEL_FORMAT_18BIT_NP:
325                 case TEGRA_DSI_PIXEL_FORMAT_24BIT_P:
326                         /* 3 bytes per pixel */
327                         dsi->pixel_scaler_mul = 3;
328                         dsi->pixel_scaler_div = 1;
329                         break;
330                 default:
331                         break;
332         }
333
334         h_width_pixels = dc->mode.h_back_porch + dc->mode.h_front_porch +
335                         dc->mode.h_sync_width + dc->mode.h_active;
336         v_width_lines = dc->mode.v_back_porch + dc->mode.v_front_porch +
337                         dc->mode.v_sync_width + dc->mode.v_active;
338
339         /* The slowest pixel rate that is required */
340         /*   for the given display timing       */
341         pixel_clk_hz = h_width_pixels * v_width_lines * dsi->info.refresh_rate;
342
343         /* Pixel byte rate on DSI interface */
344         byte_clk_hz     = (pixel_clk_hz * dsi->pixel_scaler_mul) /
345                         (dsi->pixel_scaler_div * dsi->info.n_data_lanes);
346
347         dsi->default_pixel_clk_khz = pixel_clk_hz / 1000;
348
349         printk("dsi: default pixel rate %d khz\n", dsi->default_pixel_clk_khz);
350
351         /*
352          * Pixel bit rate on DSI. Since DSI interface is double data rate (
353          * transferring data on both rising and falling edge of clk), div by 2
354          * to get the actual clock rate.
355          */
356         dsi->default_hs_clk_khz =
357                         (byte_clk_hz * NUMOF_BIT_PER_BYTE) / (1000 * 2);
358
359         dsi->controller_index = dc->ndev->id;
360
361         dsi->dsi_control_val =
362                         DSI_CONTROL_VIRTUAL_CHANNEL(dsi->info.virtual_channel) |
363                         DSI_CONTROL_NUM_DATA_LANES(dsi->info.n_data_lanes - 1) |
364                         DSI_CONTROL_VID_SOURCE(dsi->controller_index) |
365                         DSI_CONTROL_DATA_FORMAT(dsi->info.pixel_format);
366
367         dsi->target_lp_clk_khz = tegra_dsi_get_lp_clk_rate(dsi);
368         dsi->target_hs_clk_khz = tegra_dsi_get_hs_clk_rate(dsi);
369
370         /*
371          * Force video clock to be continuous mode if
372          * enable_hs_clock_on_lp_cmd_mode is set
373          */
374         if (dsi->info.enable_hs_clock_on_lp_cmd_mode) {
375                 if (dsi->info.video_clock_mode != TEGRA_DSI_VIDEO_CLOCK_CONTINUOUS)
376                         printk("Force to clock continuous mode\n");
377
378                 dsi->info.video_clock_mode = TEGRA_DSI_VIDEO_CLOCK_CONTINUOUS;
379         }
380
381 }
382
383 static void tegra_dsi_get_phy_timing(struct tegra_dc_dsi_data *dsi,
384                                 struct dsi_phy_timing_inclk *phy_timing_clk,
385                                 u32 clk_ns)
386 {
387
388         phy_timing_clk->t_hsdexit = dsi->info.phy_timing.t_hsdexit_ns ?
389                         (dsi->info.phy_timing.t_hsdexit_ns / clk_ns) :
390                         (T_HSEXIT_DEFAULT(clk_ns));
391
392         phy_timing_clk->t_hstrail = dsi->info.phy_timing.t_hstrail_ns ?
393                         (dsi->info.phy_timing.t_hstrail_ns / clk_ns) :
394                         (T_HSTRAIL_DEFAULT(clk_ns));
395
396         phy_timing_clk->t_datzero = dsi->info.phy_timing.t_datzero_ns ?
397                         (dsi->info.phy_timing.t_datzero_ns / clk_ns) :
398                         (T_DATZERO_DEFAULT(clk_ns));
399
400         phy_timing_clk->t_hsprepr = dsi->info.phy_timing.t_hsprepr_ns ?
401                         (dsi->info.phy_timing.t_hsprepr_ns / clk_ns) :
402                         (T_HSPREPR_DEFAULT(clk_ns));
403
404         phy_timing_clk->t_clktrail = dsi->info.phy_timing.t_clktrail_ns ?
405                                 (dsi->info.phy_timing.t_clktrail_ns / clk_ns) :
406                                 (T_CLKTRAIL_DEFAULT(clk_ns));
407
408         phy_timing_clk->t_clkpost = dsi->info.phy_timing.t_clkpost_ns ?
409                                 (dsi->info.phy_timing.t_clkpost_ns / clk_ns) :
410                                 (T_CLKPOST_DEFAULT(clk_ns));
411
412         phy_timing_clk->t_clkzero = dsi->info.phy_timing.t_clkzero_ns ?
413                                 (dsi->info.phy_timing.t_clkzero_ns / clk_ns) :
414                                 (T_CLKZERO_DEFAULT(clk_ns));
415
416         phy_timing_clk->t_tlpx = dsi->info.phy_timing.t_tlpx_ns ?
417                                 (dsi->info.phy_timing.t_tlpx_ns / clk_ns) :
418                                 (T_TLPX_DEFAULT(clk_ns));
419
420         phy_timing_clk->t_clkpre = T_CLKPRE_DEFAULT(clk_ns);
421         phy_timing_clk->t_clkprepare = T_CLKPREPARE_DEFAULT(clk_ns);
422         phy_timing_clk->t_wakeup = T_WAKEUP_DEFAULT(clk_ns);
423
424         phy_timing_clk->t_taget = 5 * phy_timing_clk->t_tlpx;
425         phy_timing_clk->t_tasure = 2 * phy_timing_clk->t_tlpx;
426         phy_timing_clk->t_tago = 4 * phy_timing_clk->t_tlpx;
427 }
428
429 static void tegra_dsi_set_phy_timing(struct tegra_dc_dsi_data *dsi)
430 {
431         u32 val;
432         struct dsi_phy_timing_inclk     phy_timing;
433
434         tegra_dsi_get_phy_timing(dsi, &phy_timing, dsi->current_bit_clk_ns);
435
436         val = DSI_PHY_TIMING_0_THSDEXIT(phy_timing.t_hsdexit) |
437                         DSI_PHY_TIMING_0_THSTRAIL(phy_timing.t_hstrail) |
438                         DSI_PHY_TIMING_0_TDATZERO(phy_timing.t_datzero) |
439                         DSI_PHY_TIMING_0_THSPREPR(phy_timing.t_hsprepr);
440         tegra_dsi_writel(dsi, val, DSI_PHY_TIMING_0);
441
442         val = DSI_PHY_TIMING_1_TCLKTRAIL(phy_timing.t_clktrail) |
443                         DSI_PHY_TIMING_1_TCLKPOST(phy_timing.t_clkpost) |
444                         DSI_PHY_TIMING_1_TCLKZERO(phy_timing.t_clkzero) |
445                         DSI_PHY_TIMING_1_TTLPX(phy_timing.t_tlpx);
446         tegra_dsi_writel(dsi, val, DSI_PHY_TIMING_1);
447
448         val = DSI_PHY_TIMING_2_TCLKPREPARE(phy_timing.t_clkprepare) |
449                 DSI_PHY_TIMING_2_TCLKPRE(phy_timing.t_clkpre) |
450                         DSI_PHY_TIMING_2_TWAKEUP(phy_timing.t_wakeup);
451         tegra_dsi_writel(dsi, val, DSI_PHY_TIMING_2);
452
453         val = DSI_BTA_TIMING_TTAGET(phy_timing.t_taget) |
454                         DSI_BTA_TIMING_TTASURE(phy_timing.t_tasure) |
455                         DSI_BTA_TIMING_TTAGO(phy_timing.t_tago);
456         tegra_dsi_writel(dsi, val, DSI_BTA_TIMING);
457 }
458
459 static u32 tegra_dsi_sol_delay_burst(struct tegra_dc *dc,
460                                                 struct tegra_dc_dsi_data *dsi)
461 {
462         u32 dsi_to_pixel_clk_ratio;
463         u32 temp;
464         u32 temp1;
465         u32 mipi_clk_adj_kHz;
466         u32 sol_delay;
467         struct tegra_dc_mode *dc_modes = &dc->mode;
468
469         /* Get Fdsi/Fpixel ration (note: Fdsi si in bit format) */
470         dsi_to_pixel_clk_ratio = (dsi->current_dsi_clk_khz * 2 +
471                 dsi->default_pixel_clk_khz - 1) / dsi->default_pixel_clk_khz;
472
473         /* Convert Fdsi to byte format */
474         dsi_to_pixel_clk_ratio *= 1000/8;
475
476         /* Multiplying by 1000 so that we don't loose the fraction part */
477         temp = dc_modes->h_active * 1000;
478         temp1 = dc_modes->h_active + dc_modes->h_back_porch +
479                         dc_modes->h_sync_width;
480
481         sol_delay = temp1 * dsi_to_pixel_clk_ratio -
482                         temp * dsi->pixel_scaler_mul /
483                         (dsi->pixel_scaler_div * dsi->info.n_data_lanes);
484
485         /* Do rounding on sol delay */
486         sol_delay = (sol_delay + 1000 - 1)/1000;
487
488         /* TODO:
489          * 1. find out the correct sol fifo depth to use
490          * 2. verify with hw about the clamping function
491          */
492         if (sol_delay > (480 * 4)) {
493                 sol_delay = (480 * 4);
494                 mipi_clk_adj_kHz = sol_delay +
495                         (dc_modes->h_active * dsi->pixel_scaler_mul) /
496                         (dsi->info.n_data_lanes * dsi->pixel_scaler_div);
497
498                 mipi_clk_adj_kHz *= (dsi->default_pixel_clk_khz / temp1);
499
500                 mipi_clk_adj_kHz *= 4;
501         }
502
503         dsi->target_hs_clk_khz = mipi_clk_adj_kHz;
504
505         return sol_delay;
506 }
507
508 static void tegra_dsi_set_sol_delay(struct tegra_dc *dc,
509                                                 struct tegra_dc_dsi_data *dsi)
510 {
511         u32 sol_delay;
512
513         if (dsi->info.video_burst_mode == TEGRA_DSI_VIDEO_NONE_BURST_MODE ||
514                 dsi->info.video_burst_mode ==
515                                 TEGRA_DSI_VIDEO_NONE_BURST_MODE_WITH_SYNC_END) {
516                 sol_delay = NUMOF_BIT_PER_BYTE * dsi->pixel_scaler_mul /
517                         (dsi->pixel_scaler_div * dsi->info.n_data_lanes);
518                 dsi->status.clk_burst = DSI_CLK_BURST_NONE_BURST;
519         } else {
520                 sol_delay = tegra_dsi_sol_delay_burst(dc, dsi);
521                 dsi->status.clk_burst = DSI_CLK_BURST_BURST_MODE;
522         }
523
524         tegra_dsi_writel(dsi, DSI_SOL_DELAY_SOL_DELAY(sol_delay),
525                                                                 DSI_SOL_DELAY);
526 }
527
528 static void tegra_dsi_set_timeout(struct tegra_dc_dsi_data *dsi)
529 {
530         u32 val;
531         u32 bytes_per_frame;
532         u32 timeout = 0;
533
534         /* TODO: verify the following eq */
535         bytes_per_frame = dsi->current_dsi_clk_khz * 1000 * 2 /
536                                                 (dsi->info.refresh_rate * 8);
537         timeout = bytes_per_frame / DSI_CYCLE_COUNTER_VALUE;
538         timeout = (timeout + DSI_HTX_TO_MARGIN) & 0xffff;
539
540         val = DSI_TIMEOUT_0_LRXH_TO(DSI_LRXH_TO_VALUE) |
541                         DSI_TIMEOUT_0_HTX_TO(timeout);
542         tegra_dsi_writel(dsi, val, DSI_TIMEOUT_0);
543
544         if (dsi->info.panel_reset_timeout_msec)
545                 timeout = (dsi->info.panel_reset_timeout_msec * 1000*1000)
546                                         / dsi->current_bit_clk_ns;
547         else
548                 timeout = DSI_PR_TO_VALUE;
549
550         val = DSI_TIMEOUT_1_PR_TO(timeout) |
551                 DSI_TIMEOUT_1_TA_TO(DSI_TA_TO_VALUE);
552         tegra_dsi_writel(dsi, val, DSI_TIMEOUT_1);
553
554         val = DSI_TO_TALLY_P_RESET_STATUS(IN_RESET) |
555                 DSI_TO_TALLY_TA_TALLY(DSI_TA_TALLY_VALUE)|
556                 DSI_TO_TALLY_LRXH_TALLY(DSI_LRXH_TALLY_VALUE)|
557                 DSI_TO_TALLY_HTX_TALLY(DSI_HTX_TALLY_VALUE);
558         tegra_dsi_writel(dsi, val, DSI_TO_TALLY);
559 }
560
561 static void tegra_dsi_setup_video_mode_pkt_length(struct tegra_dc *dc,
562                                                 struct tegra_dc_dsi_data *dsi)
563 {
564         u32 val;
565         u32 hact_pkt_len;
566         u32 hsa_pkt_len;
567         u32 hbp_pkt_len;
568         u32 hfp_pkt_len;
569
570         hact_pkt_len = dc->mode.h_active * dsi->pixel_scaler_mul /
571                                                         dsi->pixel_scaler_div;
572         hsa_pkt_len = dc->mode.h_sync_width * dsi->pixel_scaler_mul /
573                                                         dsi->pixel_scaler_div;
574         hbp_pkt_len = dc->mode.h_back_porch * dsi->pixel_scaler_mul /
575                                                         dsi->pixel_scaler_div;
576         hfp_pkt_len = dc->mode.h_front_porch * dsi->pixel_scaler_mul /
577                                                         dsi->pixel_scaler_div;
578
579         if (dsi->info.video_burst_mode !=
580                                 TEGRA_DSI_VIDEO_NONE_BURST_MODE_WITH_SYNC_END)
581                 hbp_pkt_len += hsa_pkt_len;
582
583         hsa_pkt_len -= DSI_HSYNC_BLNK_PKT_OVERHEAD;
584         hbp_pkt_len -= DSI_HBACK_PORCH_PKT_OVERHEAD;
585         hfp_pkt_len -= DSI_HFRONT_PORCH_PKT_OVERHEAD;
586
587         val = DSI_PKT_LEN_0_1_LENGTH_0(0) | DSI_PKT_LEN_0_1_LENGTH_1(hsa_pkt_len);
588         tegra_dsi_writel(dsi, val, DSI_PKT_LEN_0_1);
589
590         val = DSI_PKT_LEN_2_3_LENGTH_2(hbp_pkt_len) |
591                         DSI_PKT_LEN_2_3_LENGTH_3(hact_pkt_len);
592         tegra_dsi_writel(dsi, val, DSI_PKT_LEN_2_3);
593
594         val = DSI_PKT_LEN_4_5_LENGTH_4(hfp_pkt_len) | DSI_PKT_LEN_4_5_LENGTH_5(0);
595         tegra_dsi_writel(dsi, val, DSI_PKT_LEN_4_5);
596
597         val = DSI_PKT_LEN_6_7_LENGTH_6(0) | DSI_PKT_LEN_6_7_LENGTH_7(0);
598         tegra_dsi_writel(dsi, val, DSI_PKT_LEN_6_7);
599 }
600
601 static void tegra_dsi_setup_cmd_mode_pkt_length(struct tegra_dc *dc,
602                                                 struct tegra_dc_dsi_data *dsi)
603 {
604         unsigned long   val;
605         unsigned long   act_bytes;
606
607         act_bytes = dc->mode.h_active * dsi->pixel_scaler_mul /
608                         dsi->pixel_scaler_div + 1;
609
610         val = DSI_PKT_LEN_0_1_LENGTH_0(0) | DSI_PKT_LEN_0_1_LENGTH_1(0);
611         tegra_dsi_writel(dsi, val, DSI_PKT_LEN_0_1);
612
613         val = DSI_PKT_LEN_2_3_LENGTH_2(0) | DSI_PKT_LEN_2_3_LENGTH_3(act_bytes);
614         tegra_dsi_writel(dsi, val, DSI_PKT_LEN_2_3);
615
616         val = DSI_PKT_LEN_4_5_LENGTH_4(0) | DSI_PKT_LEN_4_5_LENGTH_5(act_bytes);
617         tegra_dsi_writel(dsi, val, DSI_PKT_LEN_4_5);
618
619         val = DSI_PKT_LEN_6_7_LENGTH_6(0) | DSI_PKT_LEN_6_7_LENGTH_7(0x0f0f);
620         tegra_dsi_writel(dsi, val, DSI_PKT_LEN_6_7);
621 }
622
623 static void tegra_dsi_set_pkt_length(struct tegra_dc *dc,
624                                                 struct tegra_dc_dsi_data *dsi)
625 {
626         if (dsi->driven_mode == TEGRA_DSI_DRIVEN_BY_HOST)
627                 return;
628
629         if (dsi->info.video_data_type == TEGRA_DSI_VIDEO_TYPE_VIDEO_MODE)
630                 tegra_dsi_setup_video_mode_pkt_length(dc, dsi);
631         else
632                 tegra_dsi_setup_cmd_mode_pkt_length(dc, dsi);
633 }
634
635 static void tegra_dsi_set_pkt_seq(struct tegra_dc *dc,
636                                                 struct tegra_dc_dsi_data *dsi)
637 {
638         const u32 *pkt_seq;
639         u32 rgb_info;
640         u32 pkt_seq_3_5_rgb_lo;
641         u32 pkt_seq_3_5_rgb_hi;
642         u32     val;
643         u32 reg;
644         u8  i;
645
646         if (dsi->driven_mode == TEGRA_DSI_DRIVEN_BY_HOST)
647                 return;
648
649         switch(dsi->info.pixel_format) {
650         case TEGRA_DSI_PIXEL_FORMAT_16BIT_P:
651                 rgb_info = CMD_RGB_16BPP;
652                 break;
653         case TEGRA_DSI_PIXEL_FORMAT_18BIT_P:
654                 rgb_info = CMD_RGB_18BPP;
655                 break;
656         case TEGRA_DSI_PIXEL_FORMAT_18BIT_NP:
657                 rgb_info = CMD_RGB_18BPPNP;
658                 break;
659         case TEGRA_DSI_PIXEL_FORMAT_24BIT_P:
660         default:
661                 rgb_info = CMD_RGB_24BPP;
662                 break;
663         }
664
665         pkt_seq_3_5_rgb_lo = 0;
666         pkt_seq_3_5_rgb_hi = 0;
667         if (dsi->info.video_data_type == TEGRA_DSI_VIDEO_TYPE_COMMAND_MODE)
668                 pkt_seq = dsi_pkt_seq_cmd_mode;
669         else {
670                 switch (dsi->info.video_burst_mode) {
671                 case TEGRA_DSI_VIDEO_BURST_MODE_LOWEST_SPEED:
672                 case TEGRA_DSI_VIDEO_BURST_MODE_LOW_SPEED:
673                 case TEGRA_DSI_VIDEO_BURST_MODE_MEDIUM_SPEED:
674                 case TEGRA_DSI_VIDEO_BURST_MODE_FAST_SPEED:
675                 case TEGRA_DSI_VIDEO_BURST_MODE_FASTEST_SPEED:
676                 case TEGRA_DSI_VIDEO_BURST_MODE_MANUAL:
677                         pkt_seq_3_5_rgb_hi = DSI_PKT_SEQ_3_HI_PKT_33_ID(rgb_info);
678                         pkt_seq = dsi_pkt_seq_video_burst;
679                         break;
680                 case TEGRA_DSI_VIDEO_NONE_BURST_MODE_WITH_SYNC_END:
681                         pkt_seq_3_5_rgb_hi = DSI_PKT_SEQ_3_HI_PKT_34_ID(rgb_info);
682                         pkt_seq = dsi_pkt_seq_video_non_burst_syne;
683                         break;
684                 case TEGRA_DSI_VIDEO_NONE_BURST_MODE:
685                 default:
686                         pkt_seq_3_5_rgb_lo = DSI_PKT_SEQ_3_LO_PKT_32_ID(rgb_info);
687                         pkt_seq = dsi_pkt_seq_video_non_burst;
688                         break;
689                 }
690         }
691
692         for (i = 0; i < NUMOF_PKT_SEQ; i++) {
693                 val = pkt_seq[i];
694                 reg = dsi_pkt_seq_reg[i];
695                 if ((reg == DSI_PKT_SEQ_3_LO) || (reg == DSI_PKT_SEQ_5_LO))
696                         val |= pkt_seq_3_5_rgb_lo;
697                 if ((reg == DSI_PKT_SEQ_3_HI) || (reg == DSI_PKT_SEQ_5_HI))
698                         val |= pkt_seq_3_5_rgb_hi;
699                 tegra_dsi_writel(dsi, val, reg);
700         }
701 }
702
703 static void tegra_dsi_stop_dc_stream(struct tegra_dc *dc,
704                                                 struct tegra_dc_dsi_data *dsi)
705 {
706         tegra_dc_writel(dc, 0, DC_DISP_DISP_WIN_OPTIONS);
707         tegra_dc_writel(dc, GENERAL_ACT_REQ << 8, DC_CMD_STATE_CONTROL);
708         tegra_dc_writel(dc, GENERAL_ACT_REQ, DC_CMD_STATE_CONTROL);
709
710         dsi->status.dc_stream = DSI_DC_STREAM_DISABLE;
711 }
712
713 void tegra_dsi_stop_dc_stream_at_frame_end(struct tegra_dc *dc, struct tegra_dc_dsi_data *dsi)
714 {
715         int val;
716         long timeout;
717
718         /* stop dc */
719         tegra_dsi_stop_dc_stream(dc, dsi);
720
721         /* enable vblank interrupt */
722         val = tegra_dc_readl(dc, DC_CMD_INT_ENABLE);
723         val |= V_BLANK_INT;
724         tegra_dc_writel(dc, val, DC_CMD_INT_ENABLE);
725
726         val = tegra_dc_readl(dc, DC_CMD_INT_MASK);
727         val |= V_BLANK_INT;
728         tegra_dc_writel(dc, val, DC_CMD_INT_MASK);
729
730         /* wait for vblank completion */
731         timeout = wait_for_completion_interruptible_timeout(
732                 &dc->v_blank_complete, DSI_STOP_DC_DURATION_MSEC);
733
734         /* disable vblank interrupt */
735         val = tegra_dc_readl(dc, DC_CMD_INT_ENABLE);
736         val &= ~V_BLANK_INT;
737         tegra_dc_writel(dc, val, DC_CMD_INT_ENABLE);
738
739         if(timeout == 0)
740                 printk("Warning: dc dosen't stop at the end of the frame.\n");
741 }
742
743 static void tegra_dsi_start_dc_stream(struct tegra_dc *dc,
744                                                 struct tegra_dc_dsi_data *dsi)
745 {
746         u32 val;
747
748         tegra_dc_writel(dc, DSI_ENABLE, DC_DISP_DISP_WIN_OPTIONS);
749
750         /* TODO: clean up */
751         val = PIN_INPUT_LSPI_INPUT_EN;
752         tegra_dc_writel(dc, val, DC_COM_PIN_INPUT_ENABLE3);
753
754         val = PIN_OUTPUT_LSPI_OUTPUT_DIS;
755         tegra_dc_writel(dc, val, DC_COM_PIN_OUTPUT_ENABLE3);
756
757         tegra_dc_writel(dc, PW0_ENABLE | PW1_ENABLE | PW2_ENABLE | PW3_ENABLE |
758                         PW4_ENABLE | PM0_ENABLE | PM1_ENABLE,
759                         DC_CMD_DISPLAY_POWER_CONTROL);
760
761         val = MSF_POLARITY_HIGH | MSF_ENABLE | MSF_LSPI;
762         tegra_dc_writel(dc, val, DC_CMD_DISPLAY_COMMAND_OPTION0);
763
764
765         /* TODO: using continuous video mode for now */
766         /* if (dsi->info.panel_has_frame_buffer) {*/
767         if (0) {
768                 tegra_dc_writel(dc, DISP_CTRL_MODE_NC_DISPLAY, DC_CMD_DISPLAY_COMMAND);
769                 tegra_dc_writel(dc, GENERAL_UPDATE, DC_CMD_STATE_CONTROL);
770                 val = GENERAL_ACT_REQ | NC_HOST_TRIG;
771                 tegra_dc_writel(dc, val, DC_CMD_STATE_CONTROL);
772         } else {
773                 tegra_dc_writel(dc, DISP_CTRL_MODE_C_DISPLAY, DC_CMD_DISPLAY_COMMAND);
774                 tegra_dc_writel(dc, GENERAL_ACT_REQ << 8, DC_CMD_STATE_CONTROL);
775                 tegra_dc_writel(dc, GENERAL_ACT_REQ, DC_CMD_STATE_CONTROL);
776         }
777
778         dsi->status.dc_stream = DSI_DC_STREAM_ENABLE;
779 }
780
781 static void tegra_dsi_set_dc_clk(struct tegra_dc *dc,
782                                                 struct tegra_dc_dsi_data *dsi)
783 {
784         u32 shift_clk_div;
785         u32 val;
786
787         if (dsi->info.video_burst_mode == TEGRA_DSI_VIDEO_NONE_BURST_MODE ||
788                 dsi->info.video_burst_mode ==
789                                 TEGRA_DSI_VIDEO_NONE_BURST_MODE_WITH_SYNC_END)
790                 shift_clk_div = NUMOF_BIT_PER_BYTE * dsi->pixel_scaler_mul /
791                         (dsi->pixel_scaler_div * dsi->info.n_data_lanes) - 2;
792         else
793                 shift_clk_div = (dsi->current_dsi_clk_khz * 2 +
794                                                 dsi->default_hs_clk_khz - 1) /
795                                                 (dsi->default_hs_clk_khz) - 2;
796
797 #ifdef CONFIG_TEGRA_FPGA_PLATFORM
798         shift_clk_div = 1;
799 #endif
800
801         /* TODO: find out if PCD3 option is required */
802         val = PIXEL_CLK_DIVIDER_PCD1 | SHIFT_CLK_DIVIDER(shift_clk_div);
803         tegra_dc_writel(dc, val, DC_DISP_DISP_CLOCK_CONTROL);
804
805         clk_enable(dsi->dc_clk);
806 }
807
808 static void tegra_dsi_set_dsi_clk(struct tegra_dc *dc,
809                                         struct tegra_dc_dsi_data *dsi, u32 clk)
810 {
811         u32 rm;
812
813         rm = clk % 1000;
814         if (rm != 0)
815                 clk -= rm;
816
817         clk *= 2;       /* Value for PLLD routine is required to be twice as */
818                         /* the desired clock rate */
819
820         dc->mode.pclk = clk*1000;
821         tegra_dc_setup_clk(dc, dsi->dsi_clk);
822         clk_enable(dsi->dsi_clk);
823         tegra_periph_reset_deassert(dsi->dsi_clk);
824
825         dsi->current_dsi_clk_khz = clk_get_rate(dsi->dsi_clk) / 1000;
826
827         dsi->current_bit_clk_ns =  1000*1000 / (dsi->current_dsi_clk_khz * 2);
828 }
829
830 static void tegra_dsi_hs_clk_out_enable(struct tegra_dc_dsi_data *dsi)
831 {
832         u32 val;
833
834         val = tegra_dsi_readl(dsi, DSI_CONTROL);
835         val &= ~DSI_CONTROL_HS_CLK_CTRL(1);
836
837         if (dsi->info.video_clock_mode == TEGRA_DSI_VIDEO_CLOCK_CONTINUOUS) {
838                 val |= DSI_CONTROL_HS_CLK_CTRL(CONTINUOUS);
839                 dsi->status.clk_mode = DSI_PHYCLK_CONTINUOUS;
840         } else {
841                 val |= DSI_CONTROL_HS_CLK_CTRL(TX_ONLY);
842                 dsi->status.clk_mode = DSI_PHYCLK_TX_ONLY;
843         }
844         tegra_dsi_writel(dsi, val, DSI_CONTROL);
845
846         val = tegra_dsi_readl(dsi, DSI_HOST_DSI_CONTROL);
847         val &= ~DSI_HOST_DSI_CONTROL_HIGH_SPEED_TRANS(1);
848         val |= DSI_HOST_DSI_CONTROL_HIGH_SPEED_TRANS(TEGRA_DSI_HIGH);
849         tegra_dsi_writel(dsi, val, DSI_HOST_DSI_CONTROL);
850
851         dsi->status.clk_out = DSI_PHYCLK_OUT_EN;
852 }
853
854 static void tegra_dsi_hs_clk_out_enable_in_lp(struct tegra_dc_dsi_data *dsi)
855 {
856         u32 val;
857         tegra_dsi_hs_clk_out_enable(dsi);
858
859         val = tegra_dsi_readl(dsi, DSI_HOST_DSI_CONTROL);
860         val &= ~DSI_HOST_DSI_CONTROL_HIGH_SPEED_TRANS(1);
861         val |= DSI_HOST_DSI_CONTROL_HIGH_SPEED_TRANS(TEGRA_DSI_LOW);
862         tegra_dsi_writel(dsi, val, DSI_HOST_DSI_CONTROL);
863 }
864
865 static void tegra_dsi_hs_clk_out_disable(struct tegra_dc *dc,
866                                                 struct tegra_dc_dsi_data *dsi)
867 {
868         u32 val;
869
870         if (dsi->status.dc_stream == DSI_DC_STREAM_ENABLE)
871                 tegra_dsi_stop_dc_stream(dc, dsi);
872
873         val = tegra_dsi_readl(dsi, DSI_CONTROL);
874         val &= ~DSI_CONTROL_HS_CLK_CTRL(1);
875         val |= DSI_CONTROL_HS_CLK_CTRL(TX_ONLY);
876         tegra_dsi_writel(dsi, val, DSI_CONTROL);
877
878         /* TODO: issue a cmd */
879
880         val = tegra_dsi_readl(dsi, DSI_HOST_DSI_CONTROL);
881         val &= ~DSI_HOST_DSI_CONTROL_HIGH_SPEED_TRANS(1);
882         val |= DSI_HOST_DSI_CONTROL_HIGH_SPEED_TRANS(TEGRA_DSI_LOW);
883         tegra_dsi_writel(dsi, val, DSI_HOST_DSI_CONTROL);
884
885         dsi->status.clk_mode = DSI_PHYCLK_NOT_INIT;
886         dsi->status.clk_out = DSI_PHYCLK_OUT_DIS;
887 }
888
889 static void tegra_dsi_set_control_reg_lp(struct tegra_dc_dsi_data *dsi)
890 {
891         u32 dsi_control;
892         u32 host_dsi_control;
893         u32 max_threshold;
894
895         dsi_control = dsi->dsi_control_val | DSI_CTRL_HOST_DRIVEN;
896         host_dsi_control = HOST_DSI_CTRL_COMMON |
897                         HOST_DSI_CTRL_HOST_DRIVEN |
898                         DSI_HOST_DSI_CONTROL_HIGH_SPEED_TRANS(TEGRA_DSI_LOW);
899         max_threshold = DSI_MAX_THRESHOLD_MAX_THRESHOLD(DSI_HOST_FIFO_DEPTH);
900
901         tegra_dsi_writel(dsi, max_threshold, DSI_MAX_THRESHOLD);
902         tegra_dsi_writel(dsi, dsi_control, DSI_CONTROL);
903         tegra_dsi_writel(dsi, host_dsi_control, DSI_HOST_DSI_CONTROL);
904
905         dsi->status.driven = DSI_DRIVEN_MODE_HOST;
906         dsi->status.clk_burst = DSI_CLK_BURST_NOT_INIT;
907         dsi->status.vtype = DSI_VIDEO_TYPE_NOT_INIT;
908 }
909
910 static void tegra_dsi_set_control_reg_hs(struct tegra_dc_dsi_data *dsi)
911 {
912         u32 dsi_control;
913         u32 host_dsi_control;
914         u32 max_threshold;
915         u32 dcs_cmd;
916
917         dsi_control = dsi->dsi_control_val;
918         host_dsi_control = HOST_DSI_CTRL_COMMON;
919         max_threshold = 0;
920         dcs_cmd = 0;
921
922         if (dsi->driven_mode == TEGRA_DSI_DRIVEN_BY_HOST) {
923                 dsi_control |= DSI_CTRL_HOST_DRIVEN;
924                 host_dsi_control |= HOST_DSI_CTRL_HOST_DRIVEN;
925                 max_threshold = DSI_MAX_THRESHOLD_MAX_THRESHOLD(DSI_HOST_FIFO_DEPTH);
926                 dsi->status.driven = DSI_DRIVEN_MODE_HOST;
927         } else {
928                 dsi_control |= DSI_CTRL_DC_DRIVEN;
929                 host_dsi_control |= HOST_DSI_CTRL_DC_DRIVEN;
930                 max_threshold = DSI_MAX_THRESHOLD_MAX_THRESHOLD(DSI_VIDEO_FIFO_DEPTH);
931                 dsi->status.driven = DSI_DRIVEN_MODE_DC;
932         }
933
934         if (dsi->info.video_data_type == TEGRA_DSI_VIDEO_TYPE_COMMAND_MODE) {
935                 dsi_control |= DSI_CTRL_CMD_MODE;
936                 host_dsi_control |= HOST_DSI_CTRL_CMD_MODE;
937                 dcs_cmd = DSI_DCS_CMDS_LT5_DCS_CMD(DSI_WRITE_MEMORY_START)|
938                                 DSI_DCS_CMDS_LT3_DCS_CMD(DSI_WRITE_MEMORY_CONTINUE);
939                 dsi->status.vtype = DSI_VIDEO_TYPE_CMD_MODE;
940
941         } else {
942                 dsi_control |= DSI_CTRL_VIDEO_MODE;
943                 host_dsi_control |= HOST_DSI_CTRL_VIDEO_MODE;
944                 dsi->status.vtype = DSI_VIDEO_TYPE_VIDEO_MODE;
945         }
946
947         tegra_dsi_writel(dsi, max_threshold, DSI_MAX_THRESHOLD);
948         tegra_dsi_writel(dsi, dcs_cmd, DSI_DCS_CMDS);
949         tegra_dsi_writel(dsi, dsi_control, DSI_CONTROL);
950         tegra_dsi_writel(dsi, host_dsi_control, DSI_HOST_DSI_CONTROL);
951 }
952
953 static int tegra_dsi_init_hw(struct tegra_dc *dc,
954                                                 struct tegra_dc_dsi_data *dsi)
955 {
956         u32 val;
957         u32 i;
958         int err;
959         tegra_dsi_set_dsi_clk(dc, dsi, dsi->target_lp_clk_khz);
960         if (dsi->info.dsi_instance) {
961                 /* TODO:Set the misc register*/
962         }
963
964         /* TODO: only need to change the timing for bta */
965         tegra_dsi_set_phy_timing(dsi);
966
967         err = gpio_request(TEGRA_GPIO_PJ1, "DSI TE");
968         if (err < 0)
969                 goto fail;
970
971         err = gpio_direction_input(TEGRA_GPIO_PJ1);
972         if (err < 0) {
973                 gpio_free(TEGRA_GPIO_PJ1);
974                 goto fail;
975         }
976         tegra_gpio_enable(TEGRA_GPIO_PJ1);
977
978         if (dsi->status.dc_stream == DSI_DC_STREAM_ENABLE)
979                 tegra_dsi_stop_dc_stream(dc, dsi);
980
981         /* Initializing DSI registers */
982         for (i = 0; i < ARRAY_SIZE(init_reg); i++) {
983                 tegra_dsi_writel(dsi, 0, init_reg[i]);
984         }
985         tegra_dsi_writel(dsi, dsi->dsi_control_val, DSI_CONTROL);
986
987         val = DSI_PAD_CONTROL_PAD_PDIO(0) |
988                         DSI_PAD_CONTROL_PAD_PDIO_CLK(0) |
989                         DSI_PAD_CONTROL_PAD_PULLDN_ENAB(TEGRA_DSI_DISABLE);
990         tegra_dsi_writel(dsi, val, DSI_PAD_CONTROL);
991
992         val = DSI_POWER_CONTROL_LEG_DSI_ENABLE(TEGRA_DSI_ENABLE);
993         tegra_dsi_writel(dsi, val, DSI_POWER_CONTROL);
994
995         while (tegra_dsi_readl(dsi, DSI_POWER_CONTROL) != val) {
996                 tegra_dsi_writel(dsi, val, DSI_POWER_CONTROL);
997         }
998
999         dsi->status.init = DSI_MODULE_INIT;
1000         dsi->status.lphs = DSI_LPHS_NOT_INIT;
1001         dsi->status.vtype = DSI_VIDEO_TYPE_NOT_INIT;
1002         dsi->status.driven = DSI_DRIVEN_MODE_NOT_INIT;
1003         dsi->status.clk_out = DSI_PHYCLK_OUT_DIS;
1004         dsi->status.clk_mode = DSI_PHYCLK_NOT_INIT;
1005         dsi->status.clk_burst = DSI_CLK_BURST_NOT_INIT;
1006         dsi->status.dc_stream = DSI_DC_STREAM_DISABLE;
1007 fail:
1008         return err;
1009 }
1010
1011 static int tegra_dsi_set_to_lp_mode(struct tegra_dc *dc,
1012                                                 struct tegra_dc_dsi_data *dsi)
1013 {
1014         int     err;
1015
1016         if (dsi->status.init != DSI_MODULE_INIT) {
1017                 err = -EPERM;
1018                 goto fail;
1019         }
1020
1021         if (dsi->status.lphs == DSI_LPHS_IN_LP_MODE)
1022                 goto success;
1023
1024         if (dsi->status.dc_stream == DSI_DC_STREAM_ENABLE)
1025                 tegra_dsi_stop_dc_stream_at_frame_end(dc, dsi);
1026
1027         /* disable/enable hs clock according to enable_hs_clock_on_lp_cmd_mode */
1028         if ((dsi->status.clk_out == DSI_PHYCLK_OUT_EN) &&
1029                 (!dsi->info.enable_hs_clock_on_lp_cmd_mode))
1030                 tegra_dsi_hs_clk_out_disable(dc, dsi);
1031
1032         if (dsi->current_dsi_clk_khz != dsi->target_lp_clk_khz){
1033                 tegra_dsi_set_dsi_clk(dc, dsi, dsi->target_lp_clk_khz);
1034                 tegra_dsi_set_timeout(dsi);
1035         }
1036
1037         tegra_dsi_set_control_reg_lp(dsi);
1038
1039         if ((dsi->status.clk_out == DSI_PHYCLK_OUT_DIS) &&
1040                 (dsi->info.enable_hs_clock_on_lp_cmd_mode))
1041                 tegra_dsi_hs_clk_out_enable_in_lp(dsi);
1042
1043 success:
1044         dsi->status.lphs = DSI_LPHS_IN_LP_MODE;
1045         err = 0;
1046 fail:
1047         return err;
1048 }
1049
1050 static int tegra_dsi_set_to_hs_mode(struct tegra_dc *dc,
1051                                                 struct tegra_dc_dsi_data *dsi)
1052 {
1053         int err;
1054
1055         if (dsi->status.init != DSI_MODULE_INIT) {
1056                 err = -EPERM;
1057                 goto fail;
1058         }
1059
1060         if (dsi->status.dc_stream == DSI_DC_STREAM_ENABLE)
1061                 tegra_dsi_stop_dc_stream_at_frame_end(dc, dsi);
1062
1063         if ((dsi->status.clk_out == DSI_PHYCLK_OUT_EN) &&
1064                 (!dsi->info.enable_hs_clock_on_lp_cmd_mode))
1065                 tegra_dsi_hs_clk_out_disable(dc, dsi);
1066
1067         if (dsi->current_dsi_clk_khz != dsi->target_hs_clk_khz) {
1068                 tegra_dsi_set_dsi_clk(dc, dsi, dsi->target_hs_clk_khz);
1069                 tegra_dsi_set_timeout(dsi);
1070         }
1071
1072         tegra_dsi_set_phy_timing(dsi);
1073
1074         if (dsi->driven_mode == TEGRA_DSI_DRIVEN_BY_DC){
1075                 tegra_dsi_set_pkt_seq(dc, dsi);
1076                 tegra_dsi_set_pkt_length(dc, dsi);
1077                 tegra_dsi_set_sol_delay(dc, dsi);
1078                 tegra_dsi_set_dc_clk(dc, dsi);
1079         }
1080
1081         tegra_dsi_set_control_reg_hs(dsi);
1082
1083         if (dsi->status.clk_out == DSI_PHYCLK_OUT_DIS)
1084                 tegra_dsi_hs_clk_out_enable(dsi);
1085
1086         dsi->status.lphs = DSI_LPHS_IN_HS_MODE;
1087         err = 0;
1088 fail:
1089         return err;
1090 }
1091
1092 static bool tegra_dsi_is_controller_idle(struct tegra_dc_dsi_data *dsi)
1093 {
1094         u32 timeout = 0;
1095         bool retVal;
1096
1097         retVal = false;
1098         while (timeout <= DSI_MAX_COMMAND_DELAY_USEC) {
1099                 if (!tegra_dsi_readl(dsi, DSI_TRIGGER)) {
1100                         retVal = true;
1101                         break;
1102                 }
1103                 udelay(DSI_COMMAND_DELAY_STEPS_USEC);
1104                 timeout += DSI_COMMAND_DELAY_STEPS_USEC;
1105         }
1106
1107         return retVal;
1108 }
1109
1110 static bool tegra_dsi_host_trigger(struct tegra_dc_dsi_data *dsi)
1111 {
1112         bool status;
1113
1114         status = false;
1115         if (tegra_dsi_readl(dsi, DSI_TRIGGER))
1116                 goto fail;
1117
1118         tegra_dsi_writel(dsi, DSI_TRIGGER_HOST_TRIGGER(TEGRA_DSI_ENABLE),
1119                                                                 DSI_TRIGGER);
1120
1121 #if DSI_USE_SYNC_POINTS
1122         /* TODO: Implement sync point */
1123 #else
1124         status = tegra_dsi_is_controller_idle(dsi);
1125 #endif
1126
1127 fail:
1128         return status;
1129 }
1130
1131 static int _tegra_dsi_write_data(struct tegra_dc_dsi_data *dsi,
1132                                         u8* pdata, u8 data_id, u16 data_len)
1133 {
1134         u8 virtual_channel;
1135         u8 *pval;
1136         u32 val;
1137         int err;
1138
1139         err = 0;
1140
1141         virtual_channel = dsi->info.virtual_channel << DSI_VIR_CHANNEL_BIT_POSITION;
1142
1143         /* always use hw for ecc */
1144         val = (virtual_channel | data_id) << 0 |
1145                         data_len << 8;
1146         tegra_dsi_writel(dsi, val, DSI_WR_DATA);
1147
1148         /* if pdata != NULL, pkt type is long pkt */
1149         if (pdata != NULL) {
1150                 while (data_len) {
1151                         if (data_len >= 4) {
1152                                 val = ((u32*) pdata)[0];
1153                                 data_len -= 4;
1154                                 pdata += 4;
1155                         } else {
1156                                 val = 0;
1157                                 pval = (u8*) &val;
1158                                 do
1159                                         *pval++ = *pdata++;
1160                                 while(--data_len);
1161                         }
1162                         tegra_dsi_writel(dsi, val, DSI_WR_DATA);
1163                 }
1164         }
1165
1166         if (!tegra_dsi_host_trigger(dsi))
1167                 err = -EIO;
1168
1169         return err;
1170 }
1171
1172 static int tegra_dsi_write_data(struct tegra_dc *dc,
1173                                         struct tegra_dc_dsi_data *dsi,
1174                                         u8* pdata, u8 data_id, u16 data_len)
1175 {
1176         bool switch_back_to_hs_mode;
1177         bool switch_back_to_dc_mode;
1178         u32 val;
1179         int     err;
1180
1181         err = 0;
1182         switch_back_to_hs_mode = false;
1183         switch_back_to_dc_mode = false;
1184
1185         if ((dsi->status.init != DSI_MODULE_INIT) ||
1186                 (dsi->status.lphs == DSI_LPHS_NOT_INIT)) {
1187                 err = -EPERM;
1188                 goto fail;
1189         }
1190
1191         if (!tegra_dsi_is_controller_idle(dsi)) {
1192                 err = -EBUSY;
1193                 goto fail;
1194         }
1195
1196         err = 0;
1197
1198         if (dsi->status.lphs == DSI_LPHS_IN_HS_MODE) {
1199                 if (dsi->info.hs_cmd_mode_supported) {
1200                         if (dsi->status.driven == DSI_DRIVEN_MODE_DC) {
1201                                 dsi->driven_mode = TEGRA_DSI_DRIVEN_BY_HOST;
1202                                 tegra_dsi_set_to_hs_mode(dc, dsi);
1203                                 switch_back_to_dc_mode = true;
1204                         }
1205                 } else {
1206                         tegra_dsi_set_to_lp_mode(dc, dsi);
1207                         switch_back_to_hs_mode = true;
1208                 }
1209         }
1210
1211         err = _tegra_dsi_write_data(dsi, pdata, data_id, data_len);
1212
1213
1214         if (switch_back_to_dc_mode)
1215                 dsi->driven_mode = TEGRA_DSI_DRIVEN_BY_DC;
1216         if (switch_back_to_dc_mode || switch_back_to_hs_mode)
1217                 tegra_dsi_set_to_hs_mode(dc, dsi);
1218
1219 fail:
1220         return err;
1221 }
1222
1223 static int tegra_dsi_init_panel(struct tegra_dc *dc,
1224                                                 struct tegra_dc_dsi_data *dsi)
1225 {
1226         u32     i;
1227         int err;
1228
1229         err = 0;
1230         for (i = 0; i < dsi->info.n_init_cmd; i++) {
1231                 struct tegra_dsi_cmd *cur_cmd;
1232                 cur_cmd = &dsi->info.dsi_init_cmd[i];
1233
1234                 if (cur_cmd->cmd_type == TEGRA_DSI_DELAY_MS)
1235                         mdelay(cur_cmd->sp_len_dly.delay_ms);
1236                 else {
1237                         err = tegra_dsi_write_data(dc, dsi,
1238                                                 cur_cmd->pdata,
1239                                                 cur_cmd->data_id,
1240                                                 cur_cmd->sp_len_dly.data_len);
1241                         if (err < 0)
1242                                 break;
1243                 }
1244         }
1245         return err;
1246 }
1247
1248 static int tegra_dsi_bta(struct tegra_dc_dsi_data *dsi)
1249 {
1250         u32 val;
1251         u32 poll_time;
1252         int err;
1253
1254         poll_time = 0;
1255         err = 0;
1256
1257         val = tegra_dsi_readl(dsi, DSI_HOST_DSI_CONTROL);
1258         val |= DSI_HOST_DSI_CONTROL_IMM_BTA(TEGRA_DSI_ENABLE);
1259         tegra_dsi_writel(dsi, val, DSI_HOST_DSI_CONTROL);
1260
1261         while (poll_time <  DSI_STATUS_POLLING_DURATION_USEC) {
1262                 val = tegra_dsi_readl(dsi, DSI_HOST_DSI_CONTROL);
1263                 val &= DSI_HOST_DSI_CONTROL_IMM_BTA(TEGRA_DSI_ENABLE);
1264                 if (!val)
1265                         break;
1266                 udelay(DSI_STATUS_POLLING_DELAY_USEC);
1267                 poll_time += DSI_STATUS_POLLING_DELAY_USEC;
1268         }
1269         if (poll_time > DSI_STATUS_POLLING_DURATION_USEC)
1270                 err = -EBUSY;
1271
1272         return err;
1273 }
1274
1275 static void tegra_dsi_read_fifo(struct tegra_dc *dc,
1276                         struct tegra_dc_dsi_data *dsi,
1277                         u32 rd_fifo_cnt,
1278                         u8 *read_fifo)
1279 {
1280         u32 val;
1281         u32 i;
1282
1283         /* Read data from FIFO */
1284         for (i = 0; i < rd_fifo_cnt; i++) {
1285                 val = tegra_dsi_readl(dsi, DSI_RD_DATA);
1286                 printk(KERN_INFO "Read data[%d]: 0x%x\n", i, val);
1287                 memcpy(read_fifo, &val, 4);
1288                 read_fifo += 4;
1289         }
1290
1291         /* Make sure all the data is read from the FIFO */
1292         val = tegra_dsi_readl(dsi, DSI_STATUS);
1293         val &= DSI_STATUS_RD_FIFO_COUNT(0x1f);
1294         if (val)
1295                 dev_err(&dc->ndev->dev, "DSI FIFO_RD_CNT not zero"
1296                 " even after reading FIFO_RD_CNT words from read fifo\n");
1297 }
1298
1299 static int tegra_dsi_parse_read_response(struct tegra_dc *dc,
1300                                 u32 rd_fifo_cnt, u8 *read_fifo)
1301 {
1302         int err;
1303         u32 payload_size;
1304
1305         payload_size = 0;
1306         err = 0;
1307
1308         printk(KERN_INFO "escape sequence[0x%x]\n", read_fifo[0]);
1309         switch (read_fifo[4] & 0xff) {
1310         case GEN_LONG_RD_RES:
1311                 /* Fall through */
1312         case DCS_LONG_RD_RES:
1313                 payload_size = (read_fifo[5] |
1314                                 (read_fifo[6] << 8)) & 0xFFFF;
1315                 printk(KERN_INFO "Long read response Packet\n"
1316                                 "payload_size[0x%x]\n", payload_size);
1317                 break;
1318         case GEN_1_BYTE_SHORT_RD_RES:
1319                 /* Fall through */
1320         case DCS_1_BYTE_SHORT_RD_RES:
1321                 payload_size = 1;
1322                 printk(KERN_INFO "Short read response Packet\n"
1323                         "payload_size[0x%x]\n", payload_size);
1324                 break;
1325         case GEN_2_BYTE_SHORT_RD_RES:
1326                 /* Fall through */
1327         case DCS_2_BYTE_SHORT_RD_RES:
1328                 payload_size = 2;
1329                 printk(KERN_INFO "Short read response Packet\n"
1330                         "payload_size[0x%x]\n", payload_size);
1331                 break;
1332         case ACK_ERR_RES:
1333                 payload_size = 2;
1334                 printk(KERN_INFO "Acknowledge error report response\n"
1335                         "Packet payload_size[0x%x]\n", payload_size);
1336                 break;
1337         default:
1338                 /*reading from RD_FIFO_COUNT*/
1339                 printk(KERN_INFO "Invalid read response payload_size\n");
1340                 err = -EINVAL;
1341                 break;
1342         }
1343         return err;
1344 }
1345
1346 static int tegra_dsi_read_data(struct tegra_dc *dc,
1347                                 struct tegra_dc_dsi_data *dsi,
1348                                 u32 max_ret_payload_size,
1349                                 u32 panel_reg_addr, u8 *read_data)
1350 {
1351         u32 val;
1352         int err;
1353         u32 poll_time;
1354         u32 rd_fifo_cnt;
1355         bool switch_back_to_hs_mode;
1356         bool restart_dc_stream;
1357         bool switch_back_to_dc_mode;
1358
1359         err = 0;
1360         switch_back_to_hs_mode = false;
1361         restart_dc_stream = false;
1362         switch_back_to_dc_mode = false;
1363
1364         if ((dsi->status.init != DSI_MODULE_INIT) ||
1365                 (dsi->status.lphs == DSI_LPHS_NOT_INIT) ||
1366                 (dsi->status.driven == DSI_DRIVEN_MODE_NOT_INIT)) {
1367                 err = -EPERM;
1368                 goto fail;
1369         }
1370
1371         val = tegra_dsi_readl(dsi, DSI_STATUS);
1372         val &= DSI_STATUS_RD_FIFO_COUNT(0x1f);
1373         if (val) {
1374                 err = -EBUSY;
1375                 dev_err(&dc->ndev->dev, "DSI fifo count not zero\n");
1376                 goto fail;
1377         }
1378
1379         if (!tegra_dsi_is_controller_idle(dsi)) {
1380                 err = -EBUSY;
1381                 dev_err(&dc->ndev->dev, "DSI trigger bit is already set\n");
1382                 goto fail;
1383         }
1384
1385         if (dsi->status.lphs == DSI_LPHS_IN_HS_MODE) {
1386                 if (dsi->status.driven == DSI_DRIVEN_MODE_DC) {
1387                         if (dsi->status.dc_stream == DSI_DC_STREAM_ENABLE)
1388                                 restart_dc_stream = true;
1389                         dsi->driven_mode = TEGRA_DSI_DRIVEN_BY_HOST;
1390                         switch_back_to_dc_mode = true;
1391                         if (dsi->info.hs_cmd_mode_supported) {
1392                                 err = tegra_dsi_set_to_hs_mode(dc, dsi);
1393                                 if (err < 0) {
1394                                         dev_err(&dc->ndev->dev,
1395                                         "DSI failed to go to HS mode host driven\n");
1396                                         goto fail;
1397                                 }
1398                         }
1399                 }
1400                 if (!dsi->info.hs_cmd_mode_supported) {
1401                         err = tegra_dsi_set_to_lp_mode(dc, dsi);
1402                         if (err < 0) {
1403                                 dev_err(&dc->ndev->dev,
1404                                 "DSI failed to go to LP mode\n");
1405                                 goto fail;
1406                         }
1407                         switch_back_to_hs_mode = true;
1408                 }
1409         }
1410
1411         /* Set max return payload size in words */
1412         err = _tegra_dsi_write_data(dsi, NULL,
1413                 dsi_command_max_return_pkt_size,
1414                 max_ret_payload_size);
1415         if (err < 0) {
1416                 dev_err(&dc->ndev->dev,
1417                                 "DSI write failed\n");
1418                 goto fail;
1419         }
1420
1421         /* DCS to read given panel register */
1422         err = _tegra_dsi_write_data(dsi, NULL,
1423                 dsi_command_dcs_read_with_no_params,
1424                 panel_reg_addr);
1425         if (err < 0) {
1426                 dev_err(&dc->ndev->dev,
1427                                 "DSI write failed\n");
1428                 goto fail;
1429         }
1430
1431         err = tegra_dsi_bta(dsi);
1432         if (err < 0) {
1433                 dev_err(&dc->ndev->dev,
1434                         "DSI IMM BTA timeout\n");
1435                 goto fail;
1436         }
1437
1438         poll_time = 0;
1439         while (poll_time <  DSI_DELAY_FOR_READ_FIFO) {
1440                 mdelay(1);
1441                 val = tegra_dsi_readl(dsi, DSI_STATUS);
1442                 rd_fifo_cnt = val & DSI_STATUS_RD_FIFO_COUNT(0x1f);
1443                 if (rd_fifo_cnt << 2 > DSI_READ_FIFO_DEPTH)
1444                         dev_err(&dc->ndev->dev,
1445                         "DSI RD_FIFO_CNT is greater than RD_FIFO_DEPTH\n");
1446                         break;
1447                 poll_time++;
1448         }
1449
1450         if (rd_fifo_cnt == 0) {
1451                 dev_info(&dc->ndev->dev,
1452                         "DSI RD_FIFO_CNT is zero\n");
1453                 err = -EINVAL;
1454                 goto fail;
1455         }
1456
1457         if (val & DSI_STATUS_LB_UNDERFLOW(0x1) ||
1458                 val & DSI_STATUS_LB_OVERFLOW(0x1)) {
1459                 dev_err(&dc->ndev->dev,
1460                         "DSI overflow/underflow error\n");
1461                 err = -EINVAL;
1462                 goto fail;
1463         }
1464
1465         tegra_dsi_read_fifo(dc, dsi, rd_fifo_cnt, read_data);
1466
1467         err = tegra_dsi_parse_read_response(dc, rd_fifo_cnt, read_data);
1468 fail:
1469         if (switch_back_to_dc_mode)
1470                 dsi->driven_mode = TEGRA_DSI_DRIVEN_BY_DC;
1471         if (switch_back_to_dc_mode || switch_back_to_hs_mode)
1472                 tegra_dsi_set_to_hs_mode(dc, dsi);
1473         if (restart_dc_stream)
1474                 tegra_dsi_start_dc_stream(dc, dsi);
1475
1476         return err;
1477 }
1478
1479 static void tegra_dc_dsi_enable(struct tegra_dc *dc)
1480 {
1481         struct tegra_dc_dsi_data *dsi = tegra_dc_get_outdata(dc);
1482         int err;
1483
1484         tegra_dc_io_start(dc);
1485         mutex_lock(&dsi->lock);
1486
1487         err = tegra_dsi_init_hw(dc, dsi);
1488         if (err < 0) {
1489                 dev_err(&dc->ndev->dev, "dsi: not able to init dsi hardware\n");
1490                 return;
1491         }
1492
1493         err = tegra_dsi_set_to_lp_mode(dc, dsi);
1494         if (err < 0) {
1495                 dev_err(&dc->ndev->dev, "dsi: not able to set to lp mode\n");
1496                 return;
1497         }
1498
1499         err = tegra_dsi_init_panel(dc, dsi);
1500         if (err < 0) {
1501                 dev_err(&dc->ndev->dev, "dsi: error while sending dsi cmd\n");
1502                 return;
1503         }
1504
1505         err = tegra_dsi_set_to_hs_mode(dc, dsi);
1506         if (err < 0) {
1507                         dev_err(&dc->ndev->dev,
1508                                         "dsi: not able to set to hs mode\n");
1509                 return;
1510         }
1511
1512         if (dsi->status.driven == DSI_DRIVEN_MODE_DC) {
1513                 tegra_dsi_start_dc_stream(dc, dsi);
1514         }
1515
1516         mutex_unlock(&dsi->lock);
1517         tegra_dc_io_end(dc);
1518 }
1519
1520 static void _tegra_dc_dsi_init(struct tegra_dc *dc)
1521 {
1522         struct tegra_dc_dsi_data *dsi = tegra_dc_get_outdata(dc);
1523
1524         tegra_dsi_init_sw(dc, dsi);
1525         /* TODO: Configure the CSI pad configuration */
1526 }
1527
1528 static int tegra_dc_dsi_cp_init_cmd(struct tegra_dsi_cmd* src,
1529                                         struct tegra_dsi_cmd* dst, u16 n_cmd)
1530 {
1531         u16 i;
1532         u16 len;
1533
1534         memcpy(dst, src, sizeof(*dst) * n_cmd);
1535
1536         for (i = 0; i < n_cmd; i++)
1537                 if (src[i].pdata) {
1538                         len = sizeof(*src[i].pdata) * src[i].sp_len_dly.data_len;
1539                         dst[i].pdata = kzalloc(len, GFP_KERNEL);
1540                         if (!dst[i].pdata)
1541                                 goto free_cmd_pdata;
1542                         memcpy(dst[i].pdata, src[i].pdata, len);
1543                 }
1544
1545         return 0;
1546
1547 free_cmd_pdata:
1548         for (--i; i >=0; i--)
1549                 if (dst[i].pdata)
1550                         kfree(dst[i].pdata);
1551         return -ENOMEM;
1552 }
1553
1554 static int tegra_dc_dsi_cp_info(struct tegra_dc_dsi_data* dsi,
1555                                                 struct tegra_dsi_out* p_dsi)
1556 {
1557         struct tegra_dsi_cmd* pcmd;
1558         int err;
1559
1560         pcmd = kzalloc(sizeof(*pcmd) * p_dsi->n_init_cmd, GFP_KERNEL);
1561         if (!pcmd)
1562                 return -ENOMEM;
1563
1564         if (p_dsi->n_data_lanes > MAX_DSI_DATA_LANES) {
1565                 err = -EINVAL;
1566                 goto err_free_pcmd;
1567         }
1568
1569         memcpy(&dsi->info, p_dsi, sizeof(dsi->info));
1570
1571         err = tegra_dc_dsi_cp_init_cmd(p_dsi->dsi_init_cmd,
1572                                                 pcmd, p_dsi->n_init_cmd);
1573         if (err < 0)
1574                 goto err_free_pcmd;
1575
1576         dsi->info.dsi_init_cmd = pcmd;
1577
1578         if (!dsi->info.panel_reset_timeout_msec)
1579                 dsi->info.panel_reset_timeout_msec = DEFAULT_PANEL_RESET_TIMEOUT;
1580
1581         if (!dsi->info.panel_buffer_size_byte)
1582                 dsi->info.panel_buffer_size_byte = DEFAULT_PANEL_BUFFER_BYTE;
1583
1584         if (!dsi->info.max_panel_freq_khz)
1585                 dsi->info.max_panel_freq_khz = DEFAULT_MAX_DSI_PHY_CLK_KHZ;
1586
1587         if (!dsi->info.lp_cmd_mode_freq_khz)
1588                 dsi->info.lp_cmd_mode_freq_khz = DEFAULT_LP_CMD_MODE_CLK_KHZ;
1589
1590         /* host mode is for testing only*/
1591         dsi->driven_mode = TEGRA_DSI_DRIVEN_BY_DC;
1592
1593         return 0;
1594
1595 err_free_pcmd:
1596         kfree(pcmd);
1597         return err;
1598 }
1599
1600 static int tegra_dc_dsi_init(struct tegra_dc *dc)
1601 {
1602         struct tegra_dc_dsi_data *dsi;
1603         struct resource *res;
1604         struct resource *base_res;
1605         void __iomem *base;
1606         struct clk *dc_clk = NULL;
1607         struct clk *dsi_clk = NULL;
1608         struct tegra_dsi_out *dsi_pdata;
1609         int err;
1610
1611         err = 0;
1612
1613         dsi = kzalloc(sizeof(*dsi), GFP_KERNEL);
1614         if (!dsi)
1615                 return -ENOMEM;
1616
1617         res = nvhost_get_resource_byname(dc->ndev, IORESOURCE_MEM,
1618                                         "dsi_regs");
1619         if (!res) {
1620                 dev_err(&dc->ndev->dev, "dsi: no mem resource\n");
1621                 err = -ENOENT;
1622                 goto err_free_dsi;
1623         }
1624
1625         base_res = request_mem_region(res->start, resource_size(res),
1626                                 dc->ndev->name);
1627         if (!base_res) {
1628                 dev_err(&dc->ndev->dev, "dsi: request_mem_region failed\n");
1629                 err = -EBUSY;
1630                 goto err_free_dsi;
1631         }
1632
1633         base = ioremap(res->start, resource_size(res));
1634         if (!base) {
1635                 dev_err(&dc->ndev->dev, "dsi: registers can't be mapped\n");
1636                 err = -EBUSY;
1637                 goto err_release_regs;
1638         }
1639
1640         dsi_pdata = dc->pdata->default_out->dsi;
1641         if (!dsi_pdata) {
1642                 dev_err(&dc->ndev->dev, "dsi: dsi data not available\n");
1643                 goto err_release_regs;
1644         }
1645
1646         if (dsi_pdata->dsi_instance)
1647                 dsi_clk = clk_get(&dc->ndev->dev, "dsib");
1648         else
1649                 dsi_clk = clk_get(&dc->ndev->dev, "dsia");
1650
1651         if (IS_ERR_OR_NULL(dsi_clk)) {
1652                 dev_err(&dc->ndev->dev, "dsi: can't get clock\n");
1653                 err = -EBUSY;
1654                 goto err_release_regs;
1655         }
1656
1657         dc_clk = clk_get_sys(dev_name(&dc->ndev->dev), NULL);
1658         if (IS_ERR_OR_NULL(dc_clk)) {
1659                 dev_err(&dc->ndev->dev, "dsi: dc clock %s unavailable\n",
1660                         dev_name(&dc->ndev->dev));
1661                 err = -EBUSY;
1662                 goto err_clk_put;
1663         }
1664
1665         err = tegra_dc_dsi_cp_info(dsi, dsi_pdata);
1666         if (err < 0)
1667                 goto err_dsi_data;
1668
1669         mutex_init(&dsi->lock);
1670         dsi->dc = dc;
1671         dsi->base = base;
1672         dsi->base_res = base_res;
1673         dsi->dc_clk = dc_clk;
1674         dsi->dsi_clk = dsi_clk;
1675
1676         tegra_dc_set_outdata(dc, dsi);
1677         _tegra_dc_dsi_init(dc);
1678
1679         return 0;
1680
1681 err_dsi_data:
1682 err_clk_put:
1683         clk_put(dsi_clk);
1684 err_release_regs:
1685         release_resource(base_res);
1686 err_free_dsi:
1687         kfree(dsi);
1688
1689         return err;
1690 }
1691
1692 static void tegra_dc_dsi_destroy(struct tegra_dc *dc)
1693 {
1694         struct tegra_dc_dsi_data *dsi = tegra_dc_get_outdata(dc);
1695         u16 i;
1696         u32 val;
1697
1698         mutex_lock(&dsi->lock);
1699
1700         /* free up the pdata*/
1701         for(i = 0; i < dsi->info.n_init_cmd; i++){
1702                 if(dsi->info.dsi_init_cmd[i].pdata)
1703                         kfree(dsi->info.dsi_init_cmd[i].pdata);
1704         }
1705         kfree(dsi->info.dsi_init_cmd);
1706
1707         /* Disable dc stream*/
1708         if(dsi->status.dc_stream == DSI_DC_STREAM_ENABLE)
1709                 tegra_dsi_stop_dc_stream(dc, dsi);
1710
1711         /* Disable dsi phy clock*/
1712         if(dsi->status.clk_out == DSI_PHYCLK_OUT_EN)
1713                 tegra_dsi_hs_clk_out_disable(dc, dsi);
1714
1715         val = DSI_POWER_CONTROL_LEG_DSI_ENABLE(TEGRA_DSI_DISABLE);
1716         tegra_dsi_writel(dsi, val, DSI_POWER_CONTROL);
1717
1718         iounmap(dsi->base);
1719         release_resource(dsi->base_res);
1720
1721         clk_put(dsi->dc_clk);
1722         clk_put(dsi->dsi_clk);
1723
1724         mutex_unlock(&dsi->lock);
1725
1726         mutex_destroy(&dsi->lock);
1727         kfree(dsi);
1728 }
1729
1730 static void tegra_dc_dsi_disable(struct tegra_dc *dc)
1731 {
1732         struct tegra_dc_dsi_data *dsi = tegra_dc_get_outdata(dc);
1733
1734         mutex_lock(&dsi->lock);
1735
1736         if (dsi->status.dc_stream == DSI_DC_STREAM_ENABLE)
1737                 tegra_dsi_stop_dc_stream(dc, dsi);
1738
1739         if (dsi->status.clk_out == DSI_PHYCLK_OUT_EN)
1740                 tegra_dsi_hs_clk_out_disable(dc, dsi);
1741
1742         mutex_unlock(&dsi->lock);
1743
1744         dev_err(&dc->ndev->dev, "dsi: disable\n");
1745 }
1746
1747 struct tegra_dc_out_ops tegra_dc_dsi_ops = {
1748         .init = tegra_dc_dsi_init,
1749         .destroy = tegra_dc_dsi_destroy,
1750         .enable = tegra_dc_dsi_enable,
1751         .disable = tegra_dc_dsi_disable,
1752 };