video: tegra: dsi: Fix mipi continuous clk disable
[linux-2.6.git] / drivers / video / tegra / dc / dsi.c
1 /*
2  * drivers/video/tegra/dc/dsi.c
3  *
4  * Copyright (c) 2011, NVIDIA Corporation.
5  *
6  * This software is licensed under the terms of the GNU General Public
7  * License version 2, as published by the Free Software Foundation, and
8  * may be copied, distributed, and modified under those terms.
9  *
10  * This program is distributed in the hope that it will be useful,
11  * but WITHOUT ANY WARRANTY; without even the implied warranty of
12  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
13  * GNU General Public License for more details.
14  *
15  */
16
17 #include <linux/clk.h>
18 #include <linux/delay.h>
19 #include <linux/err.h>
20 #include <linux/fb.h>
21 #include <linux/gpio.h>
22 #include <linux/interrupt.h>
23 #include <linux/kernel.h>
24 #include <linux/slab.h>
25 #include <linux/spinlock.h>
26 #include <linux/workqueue.h>
27
28 #include <mach/clk.h>
29 #include <mach/dc.h>
30 #include <mach/fb.h>
31 #include <mach/csi.h>
32 #include <linux/nvhost.h>
33
34 #include "dc_reg.h"
35 #include "dc_priv.h"
36 #include "dsi_regs.h"
37 #include "dsi.h"
38
39 #define DSI_USE_SYNC_POINTS             1
40 #define S_TO_MS(x)                      (1000 * (x))
41
42 #define DSI_MODULE_NOT_INIT             0x0
43 #define DSI_MODULE_INIT                 0x1
44
45 #define DSI_LPHS_NOT_INIT               0x0
46 #define DSI_LPHS_IN_LP_MODE             0x1
47 #define DSI_LPHS_IN_HS_MODE             0x2
48
49 #define DSI_VIDEO_TYPE_NOT_INIT         0x0
50 #define DSI_VIDEO_TYPE_VIDEO_MODE       0x1
51 #define DSI_VIDEO_TYPE_CMD_MODE         0x2
52
53 #define DSI_DRIVEN_MODE_NOT_INIT        0x0
54 #define DSI_DRIVEN_MODE_DC              0x1
55 #define DSI_DRIVEN_MODE_HOST            0x2
56
57 #define DSI_PHYCLK_OUT_DIS              0x0
58 #define DSI_PHYCLK_OUT_EN               0x1
59
60 #define DSI_PHYCLK_NOT_INIT             0x0
61 #define DSI_PHYCLK_CONTINUOUS           0x1
62 #define DSI_PHYCLK_TX_ONLY              0x2
63
64 #define DSI_CLK_BURST_NOT_INIT          0x0
65 #define DSI_CLK_BURST_NONE_BURST        0x1
66 #define DSI_CLK_BURST_BURST_MODE        0x2
67
68 #define DSI_DC_STREAM_DISABLE           0x0
69 #define DSI_DC_STREAM_ENABLE            0x1
70
71 #define DSI_LP_OP_NOT_INIT              0x0
72 #define DSI_LP_OP_WRITE                 0x1
73 #define DSI_LP_OP_READ                  0x2
74
75 static bool enable_read_debug;
76 module_param(enable_read_debug, bool, 0644);
77 MODULE_PARM_DESC(enable_read_debug,
78                 "Enable to print read fifo and return packet type");
79
80 struct dsi_status {
81         unsigned init:2;
82
83         unsigned lphs:2;
84
85         unsigned vtype:2;
86         unsigned driven:2;
87
88         unsigned clk_out:2;
89         unsigned clk_mode:2;
90         unsigned clk_burst:2;
91
92         unsigned lp_op:2;
93
94         unsigned dc_stream:1;
95 };
96
97 /* source of video data */
98 enum {
99         TEGRA_DSI_DRIVEN_BY_DC,
100         TEGRA_DSI_DRIVEN_BY_HOST,
101 };
102
103 struct tegra_dc_dsi_data {
104         struct tegra_dc *dc;
105         void __iomem *base;
106         struct resource *base_res;
107
108         struct clk *dc_clk;
109         struct clk *dsi_clk;
110         bool clk_ref;
111
112         struct mutex lock;
113
114         /* data from board info */
115         struct tegra_dsi_out info;
116
117         struct dsi_status status;
118
119         u8 driven_mode;
120         u8 controller_index;
121
122         u8 pixel_scaler_mul;
123         u8 pixel_scaler_div;
124
125         u32 default_shift_clk_div;
126         u32 default_pixel_clk_khz;
127         u32 default_hs_clk_khz;
128
129         u32 shift_clk_div;
130         u32 target_hs_clk_khz;
131         u32 target_lp_clk_khz;
132
133         u32 syncpt_id;
134         u32 syncpt_val;
135
136         u16 current_bit_clk_ns;
137         u32 current_dsi_clk_khz;
138
139         u32 dsi_control_val;
140
141         bool ulpm;
142         bool enabled;
143 };
144
145 const u32 dsi_pkt_seq_reg[NUMOF_PKT_SEQ] = {
146         DSI_PKT_SEQ_0_LO,
147         DSI_PKT_SEQ_0_HI,
148         DSI_PKT_SEQ_1_LO,
149         DSI_PKT_SEQ_1_HI,
150         DSI_PKT_SEQ_2_LO,
151         DSI_PKT_SEQ_2_HI,
152         DSI_PKT_SEQ_3_LO,
153         DSI_PKT_SEQ_3_HI,
154         DSI_PKT_SEQ_4_LO,
155         DSI_PKT_SEQ_4_HI,
156         DSI_PKT_SEQ_5_LO,
157         DSI_PKT_SEQ_5_HI,
158 };
159
160 const u32 dsi_pkt_seq_video_non_burst_syne[NUMOF_PKT_SEQ] = {
161         PKT_ID0(CMD_VS) | PKT_LEN0(0) | PKT_ID1(CMD_EOT) | PKT_LEN1(0) | PKT_LP,
162         0,
163         PKT_ID0(CMD_VE) | PKT_LEN0(0) | PKT_ID1(CMD_EOT) | PKT_LEN1(0) | PKT_LP,
164         0,
165         PKT_ID0(CMD_HS) | PKT_LEN0(0) | PKT_ID1(CMD_EOT) | PKT_LEN1(0) | PKT_LP,
166         0,
167         PKT_ID0(CMD_HS) | PKT_LEN0(0) | PKT_ID1(CMD_BLNK) | PKT_LEN1(1) |
168         PKT_ID2(CMD_HE) | PKT_LEN2(0),
169         PKT_ID3(CMD_BLNK) | PKT_LEN3(2) | PKT_ID4(CMD_RGB) | PKT_LEN4(3) |
170         PKT_ID5(CMD_BLNK) | PKT_LEN5(4),
171         PKT_ID0(CMD_HS) | PKT_LEN0(0) | PKT_ID1(CMD_EOT) | PKT_LEN1(0) | PKT_LP,
172         0,
173         PKT_ID0(CMD_HS) | PKT_LEN0(0) | PKT_ID1(CMD_BLNK) | PKT_LEN1(1) |
174         PKT_ID2(CMD_HE) | PKT_LEN2(0),
175         PKT_ID3(CMD_BLNK) | PKT_LEN3(2) | PKT_ID4(CMD_RGB) | PKT_LEN4(3) |
176         PKT_ID5(CMD_BLNK) | PKT_LEN5(4),
177 };
178
179 const u32 dsi_pkt_seq_video_non_burst[NUMOF_PKT_SEQ] = {
180         PKT_ID0(CMD_VS) | PKT_LEN0(0) | PKT_ID1(CMD_EOT) | PKT_LEN1(0) | PKT_LP,
181         0,
182         PKT_ID0(CMD_HS) | PKT_LEN0(0) | PKT_ID1(CMD_EOT) | PKT_LEN1(0) | PKT_LP,
183         0,
184         PKT_ID0(CMD_HS) | PKT_LEN0(0) | PKT_ID1(CMD_EOT) | PKT_LEN1(0) | PKT_LP,
185         0,
186         PKT_ID0(CMD_HS) | PKT_LEN0(0) | PKT_ID1(CMD_BLNK) | PKT_LEN1(2) |
187         PKT_ID2(CMD_RGB) | PKT_LEN2(3),
188         PKT_ID3(CMD_BLNK) | PKT_LEN3(4),
189         PKT_ID0(CMD_HS) | PKT_LEN0(0) | PKT_ID1(CMD_EOT) | PKT_LEN1(0) | PKT_LP,
190         0,
191         PKT_ID0(CMD_HS) | PKT_LEN0(0) | PKT_ID1(CMD_BLNK) | PKT_LEN1(2) |
192         PKT_ID2(CMD_RGB) | PKT_LEN2(3),
193         PKT_ID3(CMD_BLNK) | PKT_LEN3(4),
194 };
195
196 static const u32 dsi_pkt_seq_video_burst[NUMOF_PKT_SEQ] = {
197         PKT_ID0(CMD_VS) | PKT_LEN0(0) | PKT_ID1(CMD_EOT) | PKT_LEN1(7) | PKT_LP,
198         0,
199         PKT_ID0(CMD_HS) | PKT_LEN0(0) | PKT_ID1(CMD_EOT) | PKT_LEN1(7) | PKT_LP,
200         0,
201         PKT_ID0(CMD_HS) | PKT_LEN0(0) | PKT_ID1(CMD_EOT) | PKT_LEN1(7) | PKT_LP,
202         0,
203         PKT_ID0(CMD_HS) | PKT_LEN0(0) | PKT_ID1(CMD_BLNK) | PKT_LEN1(2)|
204         PKT_ID2(CMD_RGB) | PKT_LEN2(3) | PKT_LP,
205         PKT_ID0(CMD_EOT) | PKT_LEN0(7),
206         PKT_ID0(CMD_HS) | PKT_LEN0(0) | PKT_ID1(CMD_EOT) | PKT_LEN1(7) | PKT_LP,
207         0,
208         PKT_ID0(CMD_HS) | PKT_LEN0(0) | PKT_ID1(CMD_BLNK) | PKT_LEN1(2)|
209         PKT_ID2(CMD_RGB) | PKT_LEN2(3) | PKT_LP,
210         PKT_ID0(CMD_EOT) | PKT_LEN0(7),
211 };
212
213 static const u32 dsi_pkt_seq_video_burst_no_eot[NUMOF_PKT_SEQ] = {
214         PKT_ID0(CMD_VS) | PKT_LEN0(0) | PKT_ID1(CMD_EOT) | PKT_LEN1(0) | PKT_LP,
215         0,
216         PKT_ID0(CMD_HS) | PKT_LEN0(0) | PKT_ID1(CMD_EOT) | PKT_LEN1(0) | PKT_LP,
217         0,
218         PKT_ID0(CMD_HS) | PKT_LEN0(0) | PKT_ID1(CMD_EOT) | PKT_LEN1(0) | PKT_LP,
219         0,
220         PKT_ID0(CMD_HS) | PKT_LEN0(0) | PKT_ID1(CMD_BLNK) | PKT_LEN1(2)|
221         PKT_ID2(CMD_RGB) | PKT_LEN2(3) | PKT_LP,
222         PKT_ID0(CMD_EOT) | PKT_LEN0(0),
223         PKT_ID0(CMD_HS) | PKT_LEN0(0) | PKT_ID1(CMD_EOT) | PKT_LEN1(0) | PKT_LP,
224         0,
225         PKT_ID0(CMD_HS) | PKT_LEN0(0) | PKT_ID1(CMD_BLNK) | PKT_LEN1(2)|
226         PKT_ID2(CMD_RGB) | PKT_LEN2(3) | PKT_LP,
227         PKT_ID0(CMD_EOT) | PKT_LEN0(0),
228 };
229
230 /* TODO: verify with hw about this format */
231 const u32 dsi_pkt_seq_cmd_mode[NUMOF_PKT_SEQ] = {
232         0,
233         0,
234         0,
235         0,
236         0,
237         0,
238         PKT_ID0(CMD_LONGW) | PKT_LEN0(3) | PKT_ID1(CMD_EOT) | PKT_LEN1(7),
239         0,
240         0,
241         0,
242         PKT_ID0(CMD_LONGW) | PKT_LEN0(3) | PKT_ID1(CMD_EOT) | PKT_LEN1(7),
243         0,
244 };
245
246 const u32 init_reg[] = {
247         DSI_INT_ENABLE,
248         DSI_INT_STATUS,
249         DSI_INT_MASK,
250         DSI_INIT_SEQ_DATA_0,
251         DSI_INIT_SEQ_DATA_1,
252         DSI_INIT_SEQ_DATA_2,
253         DSI_INIT_SEQ_DATA_3,
254         DSI_INIT_SEQ_DATA_4,
255         DSI_INIT_SEQ_DATA_5,
256         DSI_INIT_SEQ_DATA_6,
257         DSI_INIT_SEQ_DATA_7,
258         DSI_DCS_CMDS,
259         DSI_PKT_SEQ_0_LO,
260         DSI_PKT_SEQ_1_LO,
261         DSI_PKT_SEQ_2_LO,
262         DSI_PKT_SEQ_3_LO,
263         DSI_PKT_SEQ_4_LO,
264         DSI_PKT_SEQ_5_LO,
265         DSI_PKT_SEQ_0_HI,
266         DSI_PKT_SEQ_1_HI,
267         DSI_PKT_SEQ_2_HI,
268         DSI_PKT_SEQ_3_HI,
269         DSI_PKT_SEQ_4_HI,
270         DSI_PKT_SEQ_5_HI,
271         DSI_CONTROL,
272         DSI_HOST_DSI_CONTROL,
273         DSI_PAD_CONTROL,
274         DSI_PAD_CONTROL_CD,
275         DSI_SOL_DELAY,
276         DSI_MAX_THRESHOLD,
277         DSI_TRIGGER,
278         DSI_TX_CRC,
279         DSI_INIT_SEQ_CONTROL,
280         DSI_PKT_LEN_0_1,
281         DSI_PKT_LEN_2_3,
282         DSI_PKT_LEN_4_5,
283         DSI_PKT_LEN_6_7,
284 };
285
286 inline unsigned long tegra_dsi_readl(struct tegra_dc_dsi_data *dsi, u32 reg)
287 {
288         return readl(dsi->base + reg * 4);
289 }
290 EXPORT_SYMBOL(tegra_dsi_readl);
291
292 inline void tegra_dsi_writel(struct tegra_dc_dsi_data *dsi, u32 val, u32 reg)
293 {
294         writel(val, dsi->base + reg * 4);
295 }
296 EXPORT_SYMBOL(tegra_dsi_writel);
297
298 static int tegra_dsi_syncpt(struct tegra_dc_dsi_data *dsi)
299 {
300         u32 val;
301         int ret;
302
303         ret = 0;
304
305         dsi->syncpt_val = nvhost_syncpt_read(
306                         &dsi->dc->ndev->host->syncpt, dsi->syncpt_id);
307
308         val = DSI_INCR_SYNCPT_COND(OP_DONE) |
309                 DSI_INCR_SYNCPT_INDX(dsi->syncpt_id);
310         tegra_dsi_writel(dsi, val, DSI_INCR_SYNCPT);
311
312         /* TODO: Use interrupt rather than polling */
313         ret = nvhost_syncpt_wait(&dsi->dc->ndev->host->syncpt,
314                 dsi->syncpt_id, dsi->syncpt_val + 1);
315         if (ret < 0) {
316                 dev_err(&dsi->dc->ndev->dev, "DSI sync point failure\n");
317                 goto fail;
318         }
319
320         (dsi->syncpt_val)++;
321         return 0;
322 fail:
323         return ret;
324 }
325
326 static u32 tegra_dsi_get_hs_clk_rate(struct tegra_dc_dsi_data *dsi)
327 {
328         u32 dsi_clock_rate_khz;
329
330         switch (dsi->info.video_burst_mode) {
331         case TEGRA_DSI_VIDEO_BURST_MODE_LOW_SPEED:
332         case TEGRA_DSI_VIDEO_BURST_MODE_MEDIUM_SPEED:
333         case TEGRA_DSI_VIDEO_BURST_MODE_FAST_SPEED:
334         case TEGRA_DSI_VIDEO_BURST_MODE_FASTEST_SPEED:
335                 /* Calculate DSI HS clock rate for DSI burst mode */
336                 dsi_clock_rate_khz = dsi->default_pixel_clk_khz *
337                                                         dsi->shift_clk_div;
338                 break;
339         case TEGRA_DSI_VIDEO_NONE_BURST_MODE:
340         case TEGRA_DSI_VIDEO_NONE_BURST_MODE_WITH_SYNC_END:
341         case TEGRA_DSI_VIDEO_BURST_MODE_LOWEST_SPEED:
342         default:
343                 /* Clock rate is default DSI clock rate for non-burst mode */
344                 dsi_clock_rate_khz = dsi->default_hs_clk_khz;
345                 break;
346         }
347
348         return dsi_clock_rate_khz;
349 }
350
351 static u32 tegra_dsi_get_lp_clk_rate(struct tegra_dc_dsi_data *dsi, u8 lp_op)
352 {
353         u32 dsi_clock_rate_khz;
354
355         if (dsi->info.enable_hs_clock_on_lp_cmd_mode)
356                 if (dsi->info.hs_clk_in_lp_cmd_mode_freq_khz)
357                         dsi_clock_rate_khz =
358                                 dsi->info.hs_clk_in_lp_cmd_mode_freq_khz;
359                 else
360                         dsi_clock_rate_khz = tegra_dsi_get_hs_clk_rate(dsi);
361         else
362                 if (lp_op == DSI_LP_OP_READ)
363                         dsi_clock_rate_khz =
364                                 dsi->info.lp_read_cmd_mode_freq_khz;
365                 else
366                         dsi_clock_rate_khz =
367                                 dsi->info.lp_cmd_mode_freq_khz;
368
369         return dsi_clock_rate_khz;
370 }
371
372 static u32 tegra_dsi_get_shift_clk_div(struct tegra_dc_dsi_data *dsi)
373 {
374         u32 shift_clk_div;
375         u32 max_shift_clk_div;
376         u32 burst_width;
377         u32 burst_width_max;
378
379         /* Get the real value of default shift_clk_div. default_shift_clk_div
380          * holds the real value of shift_clk_div.
381          */
382         shift_clk_div = dsi->default_shift_clk_div;
383
384         /* Calculate shift_clk_div which can matche the video_burst_mode. */
385         if (dsi->info.video_burst_mode >=
386                         TEGRA_DSI_VIDEO_BURST_MODE_LOWEST_SPEED) {
387                 /* The max_shift_clk_div is multiplied by 10 to save the
388                  * fraction
389                  */
390                 if (dsi->info.max_panel_freq_khz >= dsi->default_hs_clk_khz)
391                         max_shift_clk_div = dsi->info.max_panel_freq_khz
392                                 * shift_clk_div * 10 / dsi->default_hs_clk_khz;
393                 else
394                         max_shift_clk_div = shift_clk_div * 10;
395
396                 burst_width = dsi->info.video_burst_mode
397                                 - TEGRA_DSI_VIDEO_BURST_MODE_LOWEST_SPEED;
398                 burst_width_max = TEGRA_DSI_VIDEO_BURST_MODE_FASTEST_SPEED
399                                 - TEGRA_DSI_VIDEO_BURST_MODE_LOWEST_SPEED;
400
401                 shift_clk_div = (max_shift_clk_div - shift_clk_div * 10) *
402                         burst_width / (burst_width_max * 10) + shift_clk_div;
403         }
404
405         return shift_clk_div;
406 }
407
408 static void tegra_dsi_init_sw(struct tegra_dc *dc,
409                         struct tegra_dc_dsi_data *dsi)
410 {
411         u32 h_width_pixels;
412         u32 v_width_lines;
413         u32 pixel_clk_hz;
414         u32 byte_clk_hz;
415         u32 plld_clk_mhz;
416
417         switch (dsi->info.pixel_format) {
418         case TEGRA_DSI_PIXEL_FORMAT_16BIT_P:
419                 /* 2 bytes per pixel */
420                 dsi->pixel_scaler_mul = 2;
421                 dsi->pixel_scaler_div = 1;
422                 break;
423         case TEGRA_DSI_PIXEL_FORMAT_18BIT_P:
424                 /* 2.25 bytes per pixel */
425                 dsi->pixel_scaler_mul = 9;
426                 dsi->pixel_scaler_div = 4;
427                 break;
428         case TEGRA_DSI_PIXEL_FORMAT_18BIT_NP:
429         case TEGRA_DSI_PIXEL_FORMAT_24BIT_P:
430                 /* 3 bytes per pixel */
431                 dsi->pixel_scaler_mul = 3;
432                 dsi->pixel_scaler_div = 1;
433                 break;
434         default:
435                 break;
436         }
437
438         dsi->controller_index = dc->ndev->id;
439         dsi->ulpm = false;
440         dsi->enabled = false;
441         dsi->clk_ref = false;
442
443         dsi->dsi_control_val =
444                         DSI_CONTROL_VIRTUAL_CHANNEL(dsi->info.virtual_channel) |
445                         DSI_CONTROL_NUM_DATA_LANES(dsi->info.n_data_lanes - 1) |
446                         DSI_CONTROL_VID_SOURCE(dsi->controller_index) |
447                         DSI_CONTROL_DATA_FORMAT(dsi->info.pixel_format);
448
449         /* Below we are going to calculate dsi and dc clock rate.
450          * Calcuate the horizontal and vertical width.
451          */
452         h_width_pixels = dc->mode.h_back_porch + dc->mode.h_front_porch +
453                         dc->mode.h_sync_width + dc->mode.h_active;
454         v_width_lines = dc->mode.v_back_porch + dc->mode.v_front_porch +
455                         dc->mode.v_sync_width + dc->mode.v_active;
456
457         /* Calculate minimum required pixel rate. */
458         pixel_clk_hz = h_width_pixels * v_width_lines * dsi->info.refresh_rate;
459
460         dc->pixel_clk = pixel_clk_hz;
461
462         /* Calculate minimum byte rate on DSI interface. */
463         byte_clk_hz = (pixel_clk_hz * dsi->pixel_scaler_mul) /
464                         (dsi->pixel_scaler_div * dsi->info.n_data_lanes);
465
466         /* Round up to multiple of mega hz. */
467         plld_clk_mhz = DIV_ROUND_UP((byte_clk_hz * NUMOF_BIT_PER_BYTE),
468                                                                 1000000);
469
470         /* Calculate default real shift_clk_div. */
471         dsi->default_shift_clk_div = (NUMOF_BIT_PER_BYTE / 2) *
472                 dsi->pixel_scaler_mul / (dsi->pixel_scaler_div *
473                 dsi->info.n_data_lanes);
474         /* Calculate default DSI hs clock. DSI interface is double data rate.
475          * Data is transferred on both rising and falling edge of clk, div by 2
476          * to get the actual clock rate.
477          */
478         dsi->default_hs_clk_khz = plld_clk_mhz * 1000 / 2;
479         dsi->default_pixel_clk_khz = plld_clk_mhz * 1000 / 2
480                                                 / dsi->default_shift_clk_div;
481
482         /* Get the actual shift_clk_div and clock rates. */
483         dsi->shift_clk_div = tegra_dsi_get_shift_clk_div(dsi);
484         dsi->target_lp_clk_khz =
485                         tegra_dsi_get_lp_clk_rate(dsi, DSI_LP_OP_WRITE);
486         dsi->target_hs_clk_khz = tegra_dsi_get_hs_clk_rate(dsi);
487
488         dev_info(&dc->ndev->dev, "DSI: HS clock rate is %d\n",
489                                                         dsi->target_hs_clk_khz);
490
491         dsi->controller_index = dc->ndev->id;
492
493 #if DSI_USE_SYNC_POINTS
494         dsi->syncpt_id = NVSYNCPT_DSI;
495 #endif
496
497         /*
498          * Force video clock to be continuous mode if
499          * enable_hs_clock_on_lp_cmd_mode is set
500          */
501         if (dsi->info.enable_hs_clock_on_lp_cmd_mode) {
502                 if (dsi->info.video_clock_mode !=
503                                         TEGRA_DSI_VIDEO_CLOCK_CONTINUOUS)
504                         dev_warn(&dc->ndev->dev,
505                                 "Force clock continuous mode\n");
506
507                 dsi->info.video_clock_mode = TEGRA_DSI_VIDEO_CLOCK_CONTINUOUS;
508         }
509
510 }
511
512 static void tegra_dsi_get_phy_timing(struct tegra_dc_dsi_data *dsi,
513                                 struct dsi_phy_timing_inclk *phy_timing_clk,
514                                 u32 clk_ns)
515 {
516
517         phy_timing_clk->t_hsdexit = dsi->info.phy_timing.t_hsdexit_ns ?
518                         (dsi->info.phy_timing.t_hsdexit_ns / clk_ns) :
519                         (T_HSEXIT_DEFAULT(clk_ns));
520
521         phy_timing_clk->t_hstrail = dsi->info.phy_timing.t_hstrail_ns ?
522                         (dsi->info.phy_timing.t_hstrail_ns / clk_ns) :
523                         (T_HSTRAIL_DEFAULT(clk_ns));
524
525         phy_timing_clk->t_datzero = dsi->info.phy_timing.t_datzero_ns ?
526                         (dsi->info.phy_timing.t_datzero_ns / clk_ns) :
527                         (T_DATZERO_DEFAULT(clk_ns));
528
529         phy_timing_clk->t_hsprepr = dsi->info.phy_timing.t_hsprepr_ns ?
530                         (dsi->info.phy_timing.t_hsprepr_ns / clk_ns) :
531                         (T_HSPREPR_DEFAULT(clk_ns));
532
533         phy_timing_clk->t_clktrail = dsi->info.phy_timing.t_clktrail_ns ?
534                                 (dsi->info.phy_timing.t_clktrail_ns / clk_ns) :
535                                 (T_CLKTRAIL_DEFAULT(clk_ns));
536
537         phy_timing_clk->t_clkpost = dsi->info.phy_timing.t_clkpost_ns ?
538                                 (dsi->info.phy_timing.t_clkpost_ns / clk_ns) :
539                                 (T_CLKPOST_DEFAULT(clk_ns));
540
541         phy_timing_clk->t_clkzero = dsi->info.phy_timing.t_clkzero_ns ?
542                                 (dsi->info.phy_timing.t_clkzero_ns / clk_ns) :
543                                 (T_CLKZERO_DEFAULT(clk_ns));
544
545         phy_timing_clk->t_tlpx = dsi->info.phy_timing.t_tlpx_ns ?
546                                 (dsi->info.phy_timing.t_tlpx_ns / clk_ns) :
547                                 (T_TLPX_DEFAULT(clk_ns));
548
549         phy_timing_clk->t_clkpre = T_CLKPRE_DEFAULT(clk_ns);
550         phy_timing_clk->t_clkprepare = T_CLKPREPARE_DEFAULT(clk_ns);
551         phy_timing_clk->t_wakeup = T_WAKEUP_DEFAULT(clk_ns);
552
553         phy_timing_clk->t_taget = 5 * phy_timing_clk->t_tlpx;
554         phy_timing_clk->t_tasure = 2 * phy_timing_clk->t_tlpx;
555         phy_timing_clk->t_tago = 4 * phy_timing_clk->t_tlpx;
556 }
557
558 static void tegra_dsi_set_phy_timing(struct tegra_dc_dsi_data *dsi)
559 {
560         u32 val;
561         struct dsi_phy_timing_inclk phy_timing;
562
563         tegra_dsi_get_phy_timing(dsi, &phy_timing, dsi->current_bit_clk_ns);
564
565         val = DSI_PHY_TIMING_0_THSDEXIT(phy_timing.t_hsdexit) |
566                         DSI_PHY_TIMING_0_THSTRAIL(phy_timing.t_hstrail) |
567                         DSI_PHY_TIMING_0_TDATZERO(phy_timing.t_datzero) |
568                         DSI_PHY_TIMING_0_THSPREPR(phy_timing.t_hsprepr);
569         tegra_dsi_writel(dsi, val, DSI_PHY_TIMING_0);
570
571         val = DSI_PHY_TIMING_1_TCLKTRAIL(phy_timing.t_clktrail) |
572                         DSI_PHY_TIMING_1_TCLKPOST(phy_timing.t_clkpost) |
573                         DSI_PHY_TIMING_1_TCLKZERO(phy_timing.t_clkzero) |
574                         DSI_PHY_TIMING_1_TTLPX(phy_timing.t_tlpx);
575         tegra_dsi_writel(dsi, val, DSI_PHY_TIMING_1);
576
577         val = DSI_PHY_TIMING_2_TCLKPREPARE(phy_timing.t_clkprepare) |
578                 DSI_PHY_TIMING_2_TCLKPRE(phy_timing.t_clkpre) |
579                         DSI_PHY_TIMING_2_TWAKEUP(phy_timing.t_wakeup);
580         tegra_dsi_writel(dsi, val, DSI_PHY_TIMING_2);
581
582         val = DSI_BTA_TIMING_TTAGET(phy_timing.t_taget) |
583                         DSI_BTA_TIMING_TTASURE(phy_timing.t_tasure) |
584                         DSI_BTA_TIMING_TTAGO(phy_timing.t_tago);
585         tegra_dsi_writel(dsi, val, DSI_BTA_TIMING);
586 }
587
588 static u32 tegra_dsi_sol_delay_burst(struct tegra_dc *dc,
589                                 struct tegra_dc_dsi_data *dsi)
590 {
591         u32 dsi_to_pixel_clk_ratio;
592         u32 temp;
593         u32 temp1;
594         u32 mipi_clk_adj_kHz;
595         u32 sol_delay;
596         struct tegra_dc_mode *dc_modes = &dc->mode;
597
598         /* Get Fdsi/Fpixel ration (note: Fdsi is in bit format) */
599         dsi_to_pixel_clk_ratio = (dsi->current_dsi_clk_khz * 2 +
600                 dsi->default_pixel_clk_khz - 1) / dsi->default_pixel_clk_khz;
601
602         /* Convert Fdsi to byte format */
603         dsi_to_pixel_clk_ratio *= 1000/8;
604
605         /* Multiplying by 1000 so that we don't loose the fraction part */
606         temp = dc_modes->h_active * 1000;
607         temp1 = dc_modes->h_active + dc_modes->h_back_porch +
608                         dc_modes->h_sync_width;
609
610         sol_delay = temp1 * dsi_to_pixel_clk_ratio -
611                         temp * dsi->pixel_scaler_mul /
612                         (dsi->pixel_scaler_div * dsi->info.n_data_lanes);
613
614         /* Do rounding on sol delay */
615         sol_delay = (sol_delay + 1000 - 1)/1000;
616
617         /* TODO:
618          * 1. find out the correct sol fifo depth to use
619          * 2. verify with hw about the clamping function
620          */
621         if (sol_delay > (480 * 4)) {
622                 sol_delay = (480 * 4);
623                 mipi_clk_adj_kHz = sol_delay +
624                         (dc_modes->h_active * dsi->pixel_scaler_mul) /
625                         (dsi->info.n_data_lanes * dsi->pixel_scaler_div);
626
627                 mipi_clk_adj_kHz *= (dsi->default_pixel_clk_khz / temp1);
628
629                 mipi_clk_adj_kHz *= 4;
630         }
631
632         dsi->target_hs_clk_khz = mipi_clk_adj_kHz;
633
634         return sol_delay;
635 }
636
637 static void tegra_dsi_set_sol_delay(struct tegra_dc *dc,
638                                 struct tegra_dc_dsi_data *dsi)
639 {
640         u32 sol_delay;
641
642         if (dsi->info.video_burst_mode == TEGRA_DSI_VIDEO_NONE_BURST_MODE ||
643                 dsi->info.video_burst_mode ==
644                                 TEGRA_DSI_VIDEO_NONE_BURST_MODE_WITH_SYNC_END) {
645                 sol_delay = NUMOF_BIT_PER_BYTE * dsi->pixel_scaler_mul /
646                         (dsi->pixel_scaler_div * dsi->info.n_data_lanes);
647                 dsi->status.clk_burst = DSI_CLK_BURST_NONE_BURST;
648         } else {
649                 sol_delay = tegra_dsi_sol_delay_burst(dc, dsi);
650                 dsi->status.clk_burst = DSI_CLK_BURST_BURST_MODE;
651         }
652
653         tegra_dsi_writel(dsi, DSI_SOL_DELAY_SOL_DELAY(sol_delay),
654                                                                 DSI_SOL_DELAY);
655 }
656
657 static void tegra_dsi_set_timeout(struct tegra_dc_dsi_data *dsi)
658 {
659         u32 val;
660         u32 bytes_per_frame;
661         u32 timeout = 0;
662
663         /* TODO: verify the following equation */
664         bytes_per_frame = dsi->current_dsi_clk_khz * 1000 * 2 /
665                                                 (dsi->info.refresh_rate * 8);
666         timeout = bytes_per_frame / DSI_CYCLE_COUNTER_VALUE;
667         timeout = (timeout + DSI_HTX_TO_MARGIN) & 0xffff;
668
669         val = DSI_TIMEOUT_0_LRXH_TO(DSI_LRXH_TO_VALUE) |
670                         DSI_TIMEOUT_0_HTX_TO(timeout);
671         tegra_dsi_writel(dsi, val, DSI_TIMEOUT_0);
672
673         if (dsi->info.panel_reset_timeout_msec)
674                 timeout = (dsi->info.panel_reset_timeout_msec * 1000*1000)
675                                         / dsi->current_bit_clk_ns;
676         else
677                 timeout = DSI_PR_TO_VALUE;
678
679         val = DSI_TIMEOUT_1_PR_TO(timeout) |
680                 DSI_TIMEOUT_1_TA_TO(DSI_TA_TO_VALUE);
681         tegra_dsi_writel(dsi, val, DSI_TIMEOUT_1);
682
683         val = DSI_TO_TALLY_P_RESET_STATUS(IN_RESET) |
684                 DSI_TO_TALLY_TA_TALLY(DSI_TA_TALLY_VALUE)|
685                 DSI_TO_TALLY_LRXH_TALLY(DSI_LRXH_TALLY_VALUE)|
686                 DSI_TO_TALLY_HTX_TALLY(DSI_HTX_TALLY_VALUE);
687         tegra_dsi_writel(dsi, val, DSI_TO_TALLY);
688 }
689
690 static void tegra_dsi_setup_video_mode_pkt_length(struct tegra_dc *dc,
691                                                 struct tegra_dc_dsi_data *dsi)
692 {
693         u32 val;
694         u32 hact_pkt_len;
695         u32 hsa_pkt_len;
696         u32 hbp_pkt_len;
697         u32 hfp_pkt_len;
698
699         hact_pkt_len = dc->mode.h_active * dsi->pixel_scaler_mul /
700                                                         dsi->pixel_scaler_div;
701         hsa_pkt_len = dc->mode.h_sync_width * dsi->pixel_scaler_mul /
702                                                         dsi->pixel_scaler_div;
703         hbp_pkt_len = dc->mode.h_back_porch * dsi->pixel_scaler_mul /
704                                                         dsi->pixel_scaler_div;
705         hfp_pkt_len = dc->mode.h_front_porch * dsi->pixel_scaler_mul /
706                                                         dsi->pixel_scaler_div;
707
708         if (dsi->info.video_burst_mode !=
709                                 TEGRA_DSI_VIDEO_NONE_BURST_MODE_WITH_SYNC_END)
710                 hbp_pkt_len += hsa_pkt_len;
711
712         hsa_pkt_len -= DSI_HSYNC_BLNK_PKT_OVERHEAD;
713         hbp_pkt_len -= DSI_HBACK_PORCH_PKT_OVERHEAD;
714         hfp_pkt_len -= DSI_HFRONT_PORCH_PKT_OVERHEAD;
715
716         val = DSI_PKT_LEN_0_1_LENGTH_0(0) |
717                         DSI_PKT_LEN_0_1_LENGTH_1(hsa_pkt_len);
718         tegra_dsi_writel(dsi, val, DSI_PKT_LEN_0_1);
719
720         val = DSI_PKT_LEN_2_3_LENGTH_2(hbp_pkt_len) |
721                         DSI_PKT_LEN_2_3_LENGTH_3(hact_pkt_len);
722         tegra_dsi_writel(dsi, val, DSI_PKT_LEN_2_3);
723
724         val = DSI_PKT_LEN_4_5_LENGTH_4(hfp_pkt_len) |
725                         DSI_PKT_LEN_4_5_LENGTH_5(0);
726         tegra_dsi_writel(dsi, val, DSI_PKT_LEN_4_5);
727
728         val = DSI_PKT_LEN_6_7_LENGTH_6(0) | DSI_PKT_LEN_6_7_LENGTH_7(0);
729         tegra_dsi_writel(dsi, val, DSI_PKT_LEN_6_7);
730 }
731
732 static void tegra_dsi_setup_cmd_mode_pkt_length(struct tegra_dc *dc,
733                                                 struct tegra_dc_dsi_data *dsi)
734 {
735         unsigned long   val;
736         unsigned long   act_bytes;
737
738         act_bytes = dc->mode.h_active * dsi->pixel_scaler_mul /
739                         dsi->pixel_scaler_div + 1;
740
741         val = DSI_PKT_LEN_0_1_LENGTH_0(0) | DSI_PKT_LEN_0_1_LENGTH_1(0);
742         tegra_dsi_writel(dsi, val, DSI_PKT_LEN_0_1);
743
744         val = DSI_PKT_LEN_2_3_LENGTH_2(0) | DSI_PKT_LEN_2_3_LENGTH_3(act_bytes);
745         tegra_dsi_writel(dsi, val, DSI_PKT_LEN_2_3);
746
747         val = DSI_PKT_LEN_4_5_LENGTH_4(0) | DSI_PKT_LEN_4_5_LENGTH_5(act_bytes);
748         tegra_dsi_writel(dsi, val, DSI_PKT_LEN_4_5);
749
750         val = DSI_PKT_LEN_6_7_LENGTH_6(0) | DSI_PKT_LEN_6_7_LENGTH_7(0x0f0f);
751         tegra_dsi_writel(dsi, val, DSI_PKT_LEN_6_7);
752 }
753
754 static void tegra_dsi_set_pkt_length(struct tegra_dc *dc,
755                                 struct tegra_dc_dsi_data *dsi)
756 {
757         if (dsi->driven_mode == TEGRA_DSI_DRIVEN_BY_HOST)
758                 return;
759
760         if (dsi->info.video_data_type == TEGRA_DSI_VIDEO_TYPE_VIDEO_MODE)
761                 tegra_dsi_setup_video_mode_pkt_length(dc, dsi);
762         else
763                 tegra_dsi_setup_cmd_mode_pkt_length(dc, dsi);
764 }
765
766 static void tegra_dsi_set_pkt_seq(struct tegra_dc *dc,
767                                 struct tegra_dc_dsi_data *dsi)
768 {
769         const u32 *pkt_seq;
770         u32 rgb_info;
771         u32 pkt_seq_3_5_rgb_lo;
772         u32 pkt_seq_3_5_rgb_hi;
773         u32     val;
774         u32 reg;
775         u8  i;
776
777         if (dsi->driven_mode == TEGRA_DSI_DRIVEN_BY_HOST)
778                 return;
779
780         switch (dsi->info.pixel_format) {
781         case TEGRA_DSI_PIXEL_FORMAT_16BIT_P:
782                 rgb_info = CMD_RGB_16BPP;
783                 break;
784         case TEGRA_DSI_PIXEL_FORMAT_18BIT_P:
785                 rgb_info = CMD_RGB_18BPP;
786                 break;
787         case TEGRA_DSI_PIXEL_FORMAT_18BIT_NP:
788                 rgb_info = CMD_RGB_18BPPNP;
789                 break;
790         case TEGRA_DSI_PIXEL_FORMAT_24BIT_P:
791         default:
792                 rgb_info = CMD_RGB_24BPP;
793                 break;
794         }
795
796         pkt_seq_3_5_rgb_lo = 0;
797         pkt_seq_3_5_rgb_hi = 0;
798         if (dsi->info.video_data_type == TEGRA_DSI_VIDEO_TYPE_COMMAND_MODE)
799                 pkt_seq = dsi_pkt_seq_cmd_mode;
800         else {
801                 switch (dsi->info.video_burst_mode) {
802                 case TEGRA_DSI_VIDEO_BURST_MODE_LOWEST_SPEED:
803                 case TEGRA_DSI_VIDEO_BURST_MODE_LOW_SPEED:
804                 case TEGRA_DSI_VIDEO_BURST_MODE_MEDIUM_SPEED:
805                 case TEGRA_DSI_VIDEO_BURST_MODE_FAST_SPEED:
806                 case TEGRA_DSI_VIDEO_BURST_MODE_FASTEST_SPEED:
807                         pkt_seq_3_5_rgb_lo =
808                                         DSI_PKT_SEQ_3_LO_PKT_32_ID(rgb_info);
809                         if (!dsi->info.no_pkt_seq_eot)
810                                 pkt_seq = dsi_pkt_seq_video_burst;
811                         else
812                                 pkt_seq = dsi_pkt_seq_video_burst_no_eot;
813                         break;
814                 case TEGRA_DSI_VIDEO_NONE_BURST_MODE_WITH_SYNC_END:
815                         pkt_seq_3_5_rgb_hi =
816                                         DSI_PKT_SEQ_3_HI_PKT_34_ID(rgb_info);
817                         pkt_seq = dsi_pkt_seq_video_non_burst_syne;
818                         break;
819                 case TEGRA_DSI_VIDEO_NONE_BURST_MODE:
820                 default:
821                         pkt_seq_3_5_rgb_lo =
822                                         DSI_PKT_SEQ_3_LO_PKT_32_ID(rgb_info);
823                         pkt_seq = dsi_pkt_seq_video_non_burst;
824                         break;
825                 }
826         }
827
828         for (i = 0; i < NUMOF_PKT_SEQ; i++) {
829                 val = pkt_seq[i];
830                 reg = dsi_pkt_seq_reg[i];
831                 if ((reg == DSI_PKT_SEQ_3_LO) || (reg == DSI_PKT_SEQ_5_LO))
832                         val |= pkt_seq_3_5_rgb_lo;
833                 if ((reg == DSI_PKT_SEQ_3_HI) || (reg == DSI_PKT_SEQ_5_HI))
834                         val |= pkt_seq_3_5_rgb_hi;
835                 tegra_dsi_writel(dsi, val, reg);
836         }
837 }
838
839 static void tegra_dsi_stop_dc_stream(struct tegra_dc *dc,
840                                         struct tegra_dc_dsi_data *dsi)
841 {
842         tegra_dc_writel(dc, DISP_CTRL_MODE_STOP, DC_CMD_DISPLAY_COMMAND);
843         tegra_dc_writel(dc, 0, DC_DISP_DISP_WIN_OPTIONS);
844         tegra_dc_writel(dc, GENERAL_UPDATE, DC_CMD_STATE_CONTROL);
845         tegra_dc_writel(dc, GENERAL_ACT_REQ , DC_CMD_STATE_CONTROL);
846
847         dsi->status.dc_stream = DSI_DC_STREAM_DISABLE;
848 }
849
850 static void tegra_dsi_stop_dc_stream_at_frame_end(struct tegra_dc *dc,
851                                                 struct tegra_dc_dsi_data *dsi)
852 {
853         int val;
854         long timeout;
855         u32 frame_period = DIV_ROUND_UP(S_TO_MS(1), dsi->info.refresh_rate);
856
857         /* stop dc */
858         tegra_dsi_stop_dc_stream(dc, dsi);
859
860         /* enable frame end interrupt */
861         val = tegra_dc_readl(dc, DC_CMD_INT_MASK);
862         val |= FRAME_END_INT;
863         tegra_dc_writel(dc, val, DC_CMD_INT_MASK);
864
865         /* wait for frame_end completion.
866          * timeout is 2 frame duration to accomodate for
867          * internal delay.
868          */
869         timeout = wait_for_completion_interruptible_timeout(
870                         &dc->frame_end_complete,
871                         msecs_to_jiffies(2 * frame_period));
872
873         /* disable frame end interrupt */
874         val = tegra_dc_readl(dc, DC_CMD_INT_MASK);
875         val &= ~FRAME_END_INT;
876         tegra_dc_writel(dc, val, DC_CMD_INT_MASK);
877
878         if (timeout == 0)
879                 dev_warn(&dc->ndev->dev,
880                         "DC doesn't stop at end of frame.\n");
881 }
882
883 static void tegra_dsi_start_dc_stream(struct tegra_dc *dc,
884                                         struct tegra_dc_dsi_data *dsi)
885 {
886         u32 val;
887
888         tegra_dc_writel(dc, DSI_ENABLE, DC_DISP_DISP_WIN_OPTIONS);
889
890         /* TODO: clean up */
891         tegra_dc_writel(dc, PW0_ENABLE | PW1_ENABLE | PW2_ENABLE | PW3_ENABLE |
892                         PW4_ENABLE | PM0_ENABLE | PM1_ENABLE,
893                         DC_CMD_DISPLAY_POWER_CONTROL);
894
895         /* Configure one-shot mode or continuous mode */
896         if (dc->out->flags & TEGRA_DC_OUT_ONE_SHOT_MODE) {
897                 /* disable LSPI/LCD_DE output */
898                 val = PIN_OUTPUT_LSPI_OUTPUT_DIS;
899                 tegra_dc_writel(dc, val, DC_COM_PIN_OUTPUT_ENABLE3);
900
901                 /* enable MSF & set MSF polarity */
902                 val = MSF_ENABLE | MSF_LSPI;
903                 if (!dsi->info.te_polarity_low)
904                         val |= MSF_POLARITY_HIGH;
905                 else
906                         val |= MSF_POLARITY_LOW;
907                 tegra_dc_writel(dc, val, DC_CMD_DISPLAY_COMMAND_OPTION0);
908
909                 /* set non-continuous mode */
910                 tegra_dc_writel(dc, DISP_CTRL_MODE_NC_DISPLAY,
911                                                 DC_CMD_DISPLAY_COMMAND);
912                 tegra_dc_writel(dc, GENERAL_UPDATE, DC_CMD_STATE_CONTROL);
913                 tegra_dc_writel(dc, GENERAL_ACT_REQ | NC_HOST_TRIG,
914                                                 DC_CMD_STATE_CONTROL);
915         } else {
916                 /* set continuous mode */
917                 tegra_dc_writel(dc, DISP_CTRL_MODE_C_DISPLAY,
918                                                 DC_CMD_DISPLAY_COMMAND);
919                 tegra_dc_writel(dc, GENERAL_UPDATE, DC_CMD_STATE_CONTROL);
920                 tegra_dc_writel(dc, GENERAL_ACT_REQ, DC_CMD_STATE_CONTROL);
921         }
922
923         dsi->status.dc_stream = DSI_DC_STREAM_ENABLE;
924 }
925
926 static void tegra_dsi_set_dc_clk(struct tegra_dc *dc,
927                                 struct tegra_dc_dsi_data *dsi)
928 {
929         u32 shift_clk_div_register;
930         u32 val;
931
932         /* Get the corresponding register value of shift_clk_div. */
933         shift_clk_div_register = dsi->shift_clk_div * 2 - 2;
934
935 #ifdef CONFIG_TEGRA_FPGA_PLATFORM
936         shift_clk_div_register = 1;
937 #endif
938
939         /* TODO: find out if PCD3 option is required */
940         val = PIXEL_CLK_DIVIDER_PCD1 |
941                 SHIFT_CLK_DIVIDER(shift_clk_div_register);
942         tegra_dc_writel(dc, val, DC_DISP_DISP_CLOCK_CONTROL);
943 }
944
945 static void tegra_dsi_set_dsi_clk(struct tegra_dc *dc,
946                         struct tegra_dc_dsi_data *dsi, u32 clk)
947 {
948         u32 rm;
949
950         rm = clk % 1000;
951         if (rm != 0)
952                 clk -= rm;
953
954         dc->mode.pclk = clk*1000;
955         tegra_dc_setup_clk(dc, dsi->dsi_clk);
956         if (dsi->clk_ref == true)
957                 clk_disable(dsi->dsi_clk);
958         else
959                 dsi->clk_ref = true;
960         clk_enable(dsi->dsi_clk);
961         tegra_periph_reset_deassert(dsi->dsi_clk);
962
963         dsi->current_dsi_clk_khz = clk_get_rate(dsi->dsi_clk) / 1000;
964
965         dsi->current_bit_clk_ns =  1000*1000 / (dsi->current_dsi_clk_khz * 2);
966 }
967
968 static void tegra_dsi_hs_clk_out_enable(struct tegra_dc_dsi_data *dsi)
969 {
970         u32 val;
971
972         val = tegra_dsi_readl(dsi, DSI_CONTROL);
973         val &= ~DSI_CONTROL_HS_CLK_CTRL(1);
974
975         if (dsi->info.video_clock_mode == TEGRA_DSI_VIDEO_CLOCK_CONTINUOUS) {
976                 val |= DSI_CONTROL_HS_CLK_CTRL(CONTINUOUS);
977                 dsi->status.clk_mode = DSI_PHYCLK_CONTINUOUS;
978         } else {
979                 val |= DSI_CONTROL_HS_CLK_CTRL(TX_ONLY);
980                 dsi->status.clk_mode = DSI_PHYCLK_TX_ONLY;
981         }
982         tegra_dsi_writel(dsi, val, DSI_CONTROL);
983
984         val = tegra_dsi_readl(dsi, DSI_HOST_DSI_CONTROL);
985         val &= ~DSI_HOST_DSI_CONTROL_HIGH_SPEED_TRANS(1);
986         val |= DSI_HOST_DSI_CONTROL_HIGH_SPEED_TRANS(TEGRA_DSI_HIGH);
987         tegra_dsi_writel(dsi, val, DSI_HOST_DSI_CONTROL);
988
989         dsi->status.clk_out = DSI_PHYCLK_OUT_EN;
990 }
991
992 static void tegra_dsi_hs_clk_out_enable_in_lp(struct tegra_dc_dsi_data *dsi)
993 {
994         u32 val;
995         tegra_dsi_hs_clk_out_enable(dsi);
996
997         val = tegra_dsi_readl(dsi, DSI_HOST_DSI_CONTROL);
998         val &= ~DSI_HOST_DSI_CONTROL_HIGH_SPEED_TRANS(1);
999         val |= DSI_HOST_DSI_CONTROL_HIGH_SPEED_TRANS(TEGRA_DSI_LOW);
1000         tegra_dsi_writel(dsi, val, DSI_HOST_DSI_CONTROL);
1001 }
1002
1003 static void tegra_dsi_hs_clk_out_disable(struct tegra_dc *dc,
1004                                                 struct tegra_dc_dsi_data *dsi)
1005 {
1006         u32 val;
1007
1008         if (dsi->status.dc_stream == DSI_DC_STREAM_ENABLE)
1009                 tegra_dsi_stop_dc_stream_at_frame_end(dc, dsi);
1010
1011         tegra_dsi_writel(dsi, TEGRA_DSI_DISABLE, DSI_POWER_CONTROL);
1012         /* stabilization delay */
1013         udelay(300);
1014
1015         val = tegra_dsi_readl(dsi, DSI_HOST_DSI_CONTROL);
1016         val &= ~DSI_HOST_DSI_CONTROL_HIGH_SPEED_TRANS(1);
1017         val |= DSI_HOST_DSI_CONTROL_HIGH_SPEED_TRANS(TEGRA_DSI_LOW);
1018         tegra_dsi_writel(dsi, val, DSI_HOST_DSI_CONTROL);
1019
1020         tegra_dsi_writel(dsi, TEGRA_DSI_ENABLE, DSI_POWER_CONTROL);
1021         /* stabilization delay */
1022         udelay(300);
1023
1024         dsi->status.clk_mode = DSI_PHYCLK_NOT_INIT;
1025         dsi->status.clk_out = DSI_PHYCLK_OUT_DIS;
1026 }
1027
1028 static void tegra_dsi_set_control_reg_lp(struct tegra_dc_dsi_data *dsi)
1029 {
1030         u32 dsi_control;
1031         u32 host_dsi_control;
1032         u32 max_threshold;
1033
1034         dsi_control = dsi->dsi_control_val | DSI_CTRL_HOST_DRIVEN;
1035         host_dsi_control = HOST_DSI_CTRL_COMMON |
1036                         HOST_DSI_CTRL_HOST_DRIVEN |
1037                         DSI_HOST_DSI_CONTROL_HIGH_SPEED_TRANS(TEGRA_DSI_LOW);
1038         max_threshold = DSI_MAX_THRESHOLD_MAX_THRESHOLD(DSI_HOST_FIFO_DEPTH);
1039
1040         tegra_dsi_writel(dsi, max_threshold, DSI_MAX_THRESHOLD);
1041         tegra_dsi_writel(dsi, dsi_control, DSI_CONTROL);
1042         tegra_dsi_writel(dsi, host_dsi_control, DSI_HOST_DSI_CONTROL);
1043
1044         dsi->status.driven = DSI_DRIVEN_MODE_HOST;
1045         dsi->status.clk_burst = DSI_CLK_BURST_NOT_INIT;
1046         dsi->status.vtype = DSI_VIDEO_TYPE_NOT_INIT;
1047 }
1048
1049 static void tegra_dsi_set_control_reg_hs(struct tegra_dc_dsi_data *dsi)
1050 {
1051         u32 dsi_control;
1052         u32 host_dsi_control;
1053         u32 max_threshold;
1054         u32 dcs_cmd;
1055
1056         dsi_control = dsi->dsi_control_val;
1057         host_dsi_control = HOST_DSI_CTRL_COMMON;
1058         max_threshold = 0;
1059         dcs_cmd = 0;
1060
1061         if (dsi->driven_mode == TEGRA_DSI_DRIVEN_BY_HOST) {
1062                 dsi_control |= DSI_CTRL_HOST_DRIVEN;
1063                 host_dsi_control |= HOST_DSI_CTRL_HOST_DRIVEN;
1064                 max_threshold =
1065                         DSI_MAX_THRESHOLD_MAX_THRESHOLD(DSI_HOST_FIFO_DEPTH);
1066                 dsi->status.driven = DSI_DRIVEN_MODE_HOST;
1067         } else {
1068                 dsi_control |= DSI_CTRL_DC_DRIVEN;
1069                 host_dsi_control |= HOST_DSI_CTRL_DC_DRIVEN;
1070                 max_threshold =
1071                         DSI_MAX_THRESHOLD_MAX_THRESHOLD(DSI_VIDEO_FIFO_DEPTH);
1072                 dsi->status.driven = DSI_DRIVEN_MODE_DC;
1073         }
1074
1075         if (dsi->info.video_data_type == TEGRA_DSI_VIDEO_TYPE_COMMAND_MODE) {
1076                 dsi_control |= DSI_CTRL_CMD_MODE;
1077                 dcs_cmd = DSI_DCS_CMDS_LT5_DCS_CMD(DSI_WRITE_MEMORY_START)|
1078                         DSI_DCS_CMDS_LT3_DCS_CMD(DSI_WRITE_MEMORY_CONTINUE);
1079                 dsi->status.vtype = DSI_VIDEO_TYPE_CMD_MODE;
1080
1081         } else {
1082                 dsi_control |= DSI_CTRL_VIDEO_MODE;
1083                 dsi->status.vtype = DSI_VIDEO_TYPE_VIDEO_MODE;
1084         }
1085
1086         tegra_dsi_writel(dsi, max_threshold, DSI_MAX_THRESHOLD);
1087         tegra_dsi_writel(dsi, dcs_cmd, DSI_DCS_CMDS);
1088         tegra_dsi_writel(dsi, dsi_control, DSI_CONTROL);
1089         tegra_dsi_writel(dsi, host_dsi_control, DSI_HOST_DSI_CONTROL);
1090 }
1091
1092 static void tegra_dsi_pad_calibration(struct tegra_dc_dsi_data *dsi)
1093 {
1094         u32 val;
1095
1096         val =   DSI_PAD_CONTROL_PAD_LPUPADJ(0x1) |
1097                 DSI_PAD_CONTROL_PAD_LPDNADJ(0x1) |
1098                 DSI_PAD_CONTROL_PAD_PREEMP_EN(0x1) |
1099                 DSI_PAD_CONTROL_PAD_SLEWDNADJ(0x6) |
1100                 DSI_PAD_CONTROL_PAD_SLEWUPADJ(0x6);
1101         if (!dsi->ulpm) {
1102                 val |=  DSI_PAD_CONTROL_PAD_PDIO(0) |
1103                         DSI_PAD_CONTROL_PAD_PDIO_CLK(0) |
1104                         DSI_PAD_CONTROL_PAD_PULLDN_ENAB(TEGRA_DSI_DISABLE);
1105         } else {
1106                 val |=  DSI_PAD_CONTROL_PAD_PDIO(0x3) |
1107                         DSI_PAD_CONTROL_PAD_PDIO_CLK(0x1) |
1108                         DSI_PAD_CONTROL_PAD_PULLDN_ENAB(TEGRA_DSI_ENABLE);
1109         }
1110         tegra_dsi_writel(dsi, val, DSI_PAD_CONTROL);
1111
1112         val = MIPI_CAL_TERMOSA(0x4);
1113         tegra_vi_csi_writel(val, CSI_CILA_MIPI_CAL_CONFIG_0);
1114
1115         val = MIPI_CAL_TERMOSB(0x4);
1116         tegra_vi_csi_writel(val, CSI_CILB_MIPI_CAL_CONFIG_0);
1117
1118         val = MIPI_CAL_HSPUOSD(0x3) | MIPI_CAL_HSPDOSD(0x4);
1119         tegra_vi_csi_writel(val, CSI_DSI_MIPI_CAL_CONFIG);
1120
1121         val = PAD_DRIV_DN_REF(0x5) | PAD_DRIV_UP_REF(0x7);
1122         tegra_vi_csi_writel(val, CSI_MIPIBIAS_PAD_CONFIG);
1123 }
1124
1125 static int tegra_dsi_init_hw(struct tegra_dc *dc,
1126                                                 struct tegra_dc_dsi_data *dsi)
1127 {
1128         u32 i;
1129
1130         tegra_dsi_writel(dsi,
1131                 DSI_POWER_CONTROL_LEG_DSI_ENABLE(TEGRA_DSI_DISABLE),
1132                 DSI_POWER_CONTROL);
1133         /* stabilization delay */
1134         udelay(300);
1135
1136         tegra_dsi_set_dsi_clk(dc, dsi, dsi->target_lp_clk_khz);
1137         if (dsi->info.dsi_instance) {
1138                 /* TODO:Set the misc register*/
1139         }
1140
1141         /* TODO: only need to change the timing for bta */
1142         tegra_dsi_set_phy_timing(dsi);
1143
1144         if (dsi->status.dc_stream == DSI_DC_STREAM_ENABLE)
1145                 tegra_dsi_stop_dc_stream_at_frame_end(dc, dsi);
1146
1147         /* Initializing DSI registers */
1148         for (i = 0; i < ARRAY_SIZE(init_reg); i++)
1149                 tegra_dsi_writel(dsi, 0, init_reg[i]);
1150
1151         tegra_dsi_writel(dsi, dsi->dsi_control_val, DSI_CONTROL);
1152
1153         tegra_dsi_pad_calibration(dsi);
1154
1155         tegra_dsi_writel(dsi,
1156                 DSI_POWER_CONTROL_LEG_DSI_ENABLE(TEGRA_DSI_ENABLE),
1157                 DSI_POWER_CONTROL);
1158         /* stabilization delay */
1159         udelay(300);
1160
1161         dsi->status.init = DSI_MODULE_INIT;
1162         dsi->status.lphs = DSI_LPHS_NOT_INIT;
1163         dsi->status.vtype = DSI_VIDEO_TYPE_NOT_INIT;
1164         dsi->status.driven = DSI_DRIVEN_MODE_NOT_INIT;
1165         dsi->status.clk_out = DSI_PHYCLK_OUT_DIS;
1166         dsi->status.clk_mode = DSI_PHYCLK_NOT_INIT;
1167         dsi->status.clk_burst = DSI_CLK_BURST_NOT_INIT;
1168         dsi->status.dc_stream = DSI_DC_STREAM_DISABLE;
1169         dsi->status.lp_op = DSI_LP_OP_NOT_INIT;
1170
1171         return 0;
1172 }
1173
1174 static int tegra_dsi_set_to_lp_mode(struct tegra_dc *dc,
1175                         struct tegra_dc_dsi_data *dsi, u8 lp_op)
1176 {
1177         int err;
1178
1179         if (dsi->status.init != DSI_MODULE_INIT) {
1180                 err = -EPERM;
1181                 goto fail;
1182         }
1183
1184         if (dsi->status.lphs == DSI_LPHS_IN_LP_MODE &&
1185                         dsi->status.lp_op == lp_op)
1186                 goto success;
1187
1188         if (dsi->status.dc_stream == DSI_DC_STREAM_ENABLE)
1189                 tegra_dsi_stop_dc_stream_at_frame_end(dc, dsi);
1190
1191         /* disable/enable hs clk according to enable_hs_clock_on_lp_cmd_mode */
1192         if ((dsi->status.clk_out == DSI_PHYCLK_OUT_EN) &&
1193                 (!dsi->info.enable_hs_clock_on_lp_cmd_mode))
1194                 tegra_dsi_hs_clk_out_disable(dc, dsi);
1195
1196         dsi->target_lp_clk_khz = tegra_dsi_get_lp_clk_rate(dsi, lp_op);
1197         if (dsi->current_dsi_clk_khz != dsi->target_lp_clk_khz) {
1198                 tegra_dsi_set_dsi_clk(dc, dsi, dsi->target_lp_clk_khz);
1199                 tegra_dsi_set_timeout(dsi);
1200         }
1201
1202         tegra_dsi_set_control_reg_lp(dsi);
1203
1204         if ((dsi->status.clk_out == DSI_PHYCLK_OUT_DIS) &&
1205                 (dsi->info.enable_hs_clock_on_lp_cmd_mode))
1206                 tegra_dsi_hs_clk_out_enable_in_lp(dsi);
1207
1208         dsi->status.lphs = DSI_LPHS_IN_LP_MODE;
1209         dsi->status.lp_op = lp_op;
1210 success:
1211         err = 0;
1212 fail:
1213         return err;
1214 }
1215
1216 static int tegra_dsi_set_to_hs_mode(struct tegra_dc *dc,
1217                                         struct tegra_dc_dsi_data *dsi)
1218 {
1219         int err;
1220
1221         if (dsi->status.init != DSI_MODULE_INIT) {
1222                 err = -EPERM;
1223                 goto fail;
1224         }
1225
1226         if (dsi->status.lphs == DSI_LPHS_IN_HS_MODE)
1227                 goto success;
1228
1229         if (dsi->status.dc_stream == DSI_DC_STREAM_ENABLE)
1230                 tegra_dsi_stop_dc_stream_at_frame_end(dc, dsi);
1231
1232         if ((dsi->status.clk_out == DSI_PHYCLK_OUT_EN) &&
1233                 (!dsi->info.enable_hs_clock_on_lp_cmd_mode))
1234                 tegra_dsi_hs_clk_out_disable(dc, dsi);
1235
1236         if (dsi->current_dsi_clk_khz != dsi->target_hs_clk_khz) {
1237                 tegra_dsi_set_dsi_clk(dc, dsi, dsi->target_hs_clk_khz);
1238                 tegra_dsi_set_timeout(dsi);
1239         }
1240
1241         tegra_dsi_set_phy_timing(dsi);
1242
1243         if (dsi->driven_mode == TEGRA_DSI_DRIVEN_BY_DC) {
1244                 tegra_dsi_set_pkt_seq(dc, dsi);
1245                 tegra_dsi_set_pkt_length(dc, dsi);
1246                 tegra_dsi_set_sol_delay(dc, dsi);
1247                 tegra_dsi_set_dc_clk(dc, dsi);
1248         }
1249
1250         tegra_dsi_set_control_reg_hs(dsi);
1251
1252         if (dsi->status.clk_out == DSI_PHYCLK_OUT_DIS ||
1253                 dsi->info.enable_hs_clock_on_lp_cmd_mode)
1254                 tegra_dsi_hs_clk_out_enable(dsi);
1255
1256         dsi->status.lphs = DSI_LPHS_IN_HS_MODE;
1257 success:
1258         dsi->status.lp_op = DSI_LP_OP_NOT_INIT;
1259         err = 0;
1260 fail:
1261         return err;
1262 }
1263
1264 static bool tegra_dsi_write_busy(struct tegra_dc_dsi_data *dsi)
1265 {
1266         u32 timeout = 0;
1267         bool retVal = true;
1268
1269         while (timeout <= DSI_MAX_COMMAND_DELAY_USEC) {
1270                 if (!(DSI_TRIGGER_HOST_TRIGGER(0x1) &
1271                         tegra_dsi_readl(dsi, DSI_TRIGGER))) {
1272                         retVal = false;
1273                         break;
1274                 }
1275                 udelay(DSI_COMMAND_DELAY_STEPS_USEC);
1276                 timeout += DSI_COMMAND_DELAY_STEPS_USEC;
1277         }
1278
1279         return retVal;
1280 }
1281
1282 static bool tegra_dsi_read_busy(struct tegra_dc_dsi_data *dsi)
1283 {
1284         u32 timeout = 0;
1285         bool retVal = true;
1286
1287         while (timeout <  DSI_STATUS_POLLING_DURATION_USEC) {
1288                 if (!(DSI_HOST_DSI_CONTROL_IMM_BTA(0x1) &
1289                         tegra_dsi_readl(dsi, DSI_HOST_DSI_CONTROL))) {
1290                         retVal = false;
1291                         break;
1292                 }
1293                 udelay(DSI_STATUS_POLLING_DELAY_USEC);
1294                 timeout += DSI_STATUS_POLLING_DELAY_USEC;
1295         }
1296
1297         return retVal;
1298 }
1299
1300 static bool tegra_dsi_host_busy(struct tegra_dc_dsi_data *dsi)
1301 {
1302         int err = 0;
1303
1304         if (tegra_dsi_write_busy(dsi)) {
1305                 err = -EBUSY;
1306                 dev_err(&dsi->dc->ndev->dev,
1307                         "DSI trigger bit already set\n");
1308                 goto fail;
1309         }
1310
1311         if (tegra_dsi_read_busy(dsi)) {
1312                 err = -EBUSY;
1313                 dev_err(&dsi->dc->ndev->dev,
1314                         "DSI immediate bta bit already set\n");
1315                 goto fail;
1316         }
1317 fail:
1318         return err;
1319 }
1320
1321 static void tegra_dsi_reset_underflow_overflow
1322                                 (struct tegra_dc_dsi_data *dsi)
1323 {
1324         u32 val;
1325
1326         val = tegra_dsi_readl(dsi, DSI_STATUS);
1327         val &= (DSI_STATUS_LB_OVERFLOW(0x1) | DSI_STATUS_LB_UNDERFLOW(0x1));
1328         if (val) {
1329                 dev_warn(&dsi->dc->ndev->dev, "Reset overflow/underflow\n");
1330                 val = tegra_dsi_readl(dsi, DSI_HOST_DSI_CONTROL);
1331                 val |= DSI_HOST_CONTROL_FIFO_STAT_RESET(0x1);
1332                 tegra_dsi_writel(dsi, val, DSI_HOST_DSI_CONTROL);
1333                 ndelay(200);
1334         }
1335 }
1336
1337 static void tegra_dsi_soft_reset(struct tegra_dc_dsi_data *dsi)
1338 {
1339         tegra_dsi_writel(dsi,
1340                 DSI_POWER_CONTROL_LEG_DSI_ENABLE(TEGRA_DSI_DISABLE),
1341                 DSI_POWER_CONTROL);
1342         /* stabilization delay */
1343         udelay(300);
1344
1345         tegra_dsi_writel(dsi,
1346                 DSI_POWER_CONTROL_LEG_DSI_ENABLE(TEGRA_DSI_ENABLE),
1347                 DSI_POWER_CONTROL);
1348         /* stabilization delay */
1349         udelay(300);
1350 }
1351
1352 static void tegra_dsi_reset_read_count(struct tegra_dc_dsi_data *dsi)
1353 {
1354         u32 val;
1355
1356         val = tegra_dsi_readl(dsi, DSI_STATUS);
1357         val &= DSI_STATUS_RD_FIFO_COUNT(0x1f);
1358         if (val) {
1359                 dev_warn(&dsi->dc->ndev->dev,
1360                         "DSI read count not zero, resetting\n");
1361                 tegra_dsi_soft_reset(dsi);
1362         }
1363 }
1364
1365 static struct dsi_status *tegra_dsi_save_state_switch_to_host_cmd_mode(
1366                                                 struct tegra_dc_dsi_data *dsi,
1367                                                 struct tegra_dc *dc,
1368                                                 u8 lp_op)
1369 {
1370         struct dsi_status *init_status;
1371         int err;
1372
1373         init_status = kzalloc(sizeof(*init_status), GFP_KERNEL);
1374         if (!init_status)
1375                 return ERR_PTR(-ENOMEM);
1376
1377         *init_status = dsi->status;
1378
1379         if (dsi->status.lphs == DSI_LPHS_IN_HS_MODE) {
1380                 if (dsi->status.driven == DSI_DRIVEN_MODE_DC) {
1381                         if (dsi->status.dc_stream == DSI_DC_STREAM_ENABLE)
1382                                 tegra_dsi_stop_dc_stream_at_frame_end(dc, dsi);
1383                         dsi->driven_mode = TEGRA_DSI_DRIVEN_BY_HOST;
1384                         if (dsi->info.hs_cmd_mode_supported) {
1385                                 err = tegra_dsi_set_to_hs_mode(dc, dsi);
1386                                 if (err < 0) {
1387                                         dev_err(&dc->ndev->dev,
1388                                         "Switch to HS host mode failed\n");
1389                                         goto fail;
1390                                 }
1391                         }
1392                 }
1393                 if (!dsi->info.hs_cmd_mode_supported) {
1394                         err =
1395                         tegra_dsi_set_to_lp_mode(dc, dsi, lp_op);
1396                         if (err < 0) {
1397                                 dev_err(&dc->ndev->dev,
1398                                 "DSI failed to go to LP mode\n");
1399                                 goto fail;
1400                         }
1401                 }
1402         } else if (dsi->status.lphs == DSI_LPHS_IN_LP_MODE) {
1403                 if (dsi->status.lp_op != lp_op) {
1404                         err = tegra_dsi_set_to_lp_mode(dc, dsi, lp_op);
1405                         if (err < 0) {
1406                                 dev_err(&dc->ndev->dev,
1407                                 "DSI failed to go to LP mode\n");
1408                                 goto fail;
1409                         }
1410                 }
1411         }
1412
1413         return init_status;
1414 fail:
1415         kfree(init_status);
1416         return ERR_PTR(err);
1417 }
1418
1419 static struct dsi_status *tegra_dsi_prepare_host_transmission(
1420                                 struct tegra_dc *dc,
1421                                 struct tegra_dc_dsi_data *dsi,
1422                                 u8 lp_op)
1423 {
1424         int err = 0;
1425         struct dsi_status *init_status;
1426
1427         if (dsi->status.init != DSI_MODULE_INIT ||
1428                 dsi->ulpm) {
1429                 err = -EPERM;
1430                 goto fail;
1431         }
1432
1433         if (tegra_dsi_host_busy(dsi)) {
1434                 err = -EBUSY;
1435                 dev_err(&dc->ndev->dev, "DSI host busy\n");
1436                 goto fail;
1437         }
1438
1439         tegra_dsi_reset_underflow_overflow(dsi);
1440
1441         if (lp_op == DSI_LP_OP_READ)
1442                 tegra_dsi_reset_read_count(dsi);
1443
1444         if (dsi->status.lphs == DSI_LPHS_NOT_INIT) {
1445                 err = tegra_dsi_set_to_lp_mode(dc, dsi, lp_op);
1446                 if (err < 0) {
1447                         dev_err(&dc->ndev->dev, "Failed to config LP write\n");
1448                         goto fail;
1449                 }
1450         }
1451
1452         init_status = tegra_dsi_save_state_switch_to_host_cmd_mode
1453                                         (dsi, dc, lp_op);
1454         if (IS_ERR_OR_NULL(init_status)) {
1455                 err = PTR_ERR(init_status);
1456                 dev_err(&dc->ndev->dev, "DSI state saving failed\n");
1457                 goto fail;
1458         }
1459
1460         return init_status;
1461 fail:
1462         return ERR_PTR(err);
1463 }
1464
1465 static int tegra_dsi_restore_state(struct tegra_dc *dc,
1466                                 struct tegra_dc_dsi_data *dsi,
1467                                 struct dsi_status *init_status)
1468 {
1469         bool switch_back_to_dc_mode = false;
1470         bool switch_back_to_hs_mode = false;
1471         bool restart_dc_stream;
1472         int err = 0;
1473
1474         switch_back_to_dc_mode = (dsi->status.driven ==
1475                                 DSI_DRIVEN_MODE_HOST &&
1476                                 init_status->driven ==
1477                                 DSI_DRIVEN_MODE_DC);
1478         switch_back_to_hs_mode = (dsi->status.lphs ==
1479                                 DSI_LPHS_IN_LP_MODE &&
1480                                 init_status->lphs ==
1481                                 DSI_LPHS_IN_HS_MODE);
1482         restart_dc_stream = (dsi->status.dc_stream ==
1483                                 DSI_DC_STREAM_DISABLE &&
1484                                 init_status->dc_stream ==
1485                                 DSI_DC_STREAM_ENABLE);
1486
1487         if (dsi->status.lphs == DSI_LPHS_IN_LP_MODE &&
1488                 init_status->lphs == DSI_LPHS_IN_LP_MODE) {
1489                 if (dsi->status.lp_op != init_status->lp_op) {
1490                         err =
1491                         tegra_dsi_set_to_lp_mode(dc, dsi, init_status->lp_op);
1492                         if (err < 0) {
1493                                 dev_err(&dc->ndev->dev,
1494                                         "Failed to config LP mode\n");
1495                                 goto fail;
1496                         }
1497                 }
1498                 goto success;
1499         }
1500
1501         if (switch_back_to_dc_mode)
1502                 dsi->driven_mode = TEGRA_DSI_DRIVEN_BY_DC;
1503         if (switch_back_to_dc_mode || switch_back_to_hs_mode) {
1504                 err = tegra_dsi_set_to_hs_mode(dc, dsi);
1505                 if (err < 0) {
1506                         dev_err(&dc->ndev->dev, "Failed to config HS mode\n");
1507                         goto fail;
1508                 }
1509         }
1510         if (restart_dc_stream)
1511                 tegra_dsi_start_dc_stream(dc, dsi);
1512
1513 success:
1514 fail:
1515         kfree(init_status);
1516         return err;
1517 }
1518
1519 static int tegra_dsi_host_trigger(struct tegra_dc_dsi_data *dsi)
1520 {
1521         int status = 0;
1522
1523         if (tegra_dsi_readl(dsi, DSI_TRIGGER)) {
1524                 status = -EBUSY;
1525                 goto fail;
1526         }
1527
1528         tegra_dsi_writel(dsi,
1529                 DSI_TRIGGER_HOST_TRIGGER(TEGRA_DSI_ENABLE), DSI_TRIGGER);
1530
1531 #if DSI_USE_SYNC_POINTS
1532         status = tegra_dsi_syncpt(dsi);
1533         if (status < 0) {
1534                 dev_err(&dsi->dc->ndev->dev,
1535                         "DSI syncpt for host trigger failed\n");
1536                 goto fail;
1537         }
1538 #else
1539         if (tegra_dsi_write_busy(dsi)) {
1540                 status = -EBUSY;
1541                 dev_err(&dsi->dc->ndev->dev,
1542                         "Timeout waiting on write completion\n");
1543         }
1544 #endif
1545
1546 fail:
1547         return status;
1548 }
1549
1550 static int _tegra_dsi_write_data(struct tegra_dc_dsi_data *dsi,
1551                                         u8 *pdata, u8 data_id, u16 data_len)
1552 {
1553         u8 virtual_channel;
1554         u8 *pval;
1555         u32 val;
1556         int err;
1557
1558         err = 0;
1559
1560         virtual_channel = dsi->info.virtual_channel <<
1561                                                 DSI_VIR_CHANNEL_BIT_POSITION;
1562
1563         /* always use hw for ecc */
1564         val = (virtual_channel | data_id) << 0 |
1565                         data_len << 8;
1566         tegra_dsi_writel(dsi, val, DSI_WR_DATA);
1567
1568         /* if pdata != NULL, pkt type is long pkt */
1569         if (pdata != NULL) {
1570                 while (data_len) {
1571                         if (data_len >= 4) {
1572                                 val = ((u32 *) pdata)[0];
1573                                 data_len -= 4;
1574                                 pdata += 4;
1575                         } else {
1576                                 val = 0;
1577                                 pval = (u8 *) &val;
1578                                 do
1579                                         *pval++ = *pdata++;
1580                                 while (--data_len);
1581                         }
1582                         tegra_dsi_writel(dsi, val, DSI_WR_DATA);
1583                 }
1584         }
1585
1586         err = tegra_dsi_host_trigger(dsi);
1587         if (err < 0)
1588                 dev_err(&dsi->dc->ndev->dev, "DSI host trigger failed\n");
1589
1590         return err;
1591 }
1592
1593 int tegra_dsi_write_data(struct tegra_dc *dc,
1594                         struct tegra_dc_dsi_data *dsi,
1595                         u8 *pdata, u8 data_id, u16 data_len)
1596 {
1597         int err = 0;
1598         struct dsi_status *init_status;
1599
1600         tegra_dc_io_start(dc);
1601
1602         init_status = tegra_dsi_prepare_host_transmission(
1603                                 dc, dsi, DSI_LP_OP_WRITE);
1604         if (IS_ERR_OR_NULL(init_status)) {
1605                 err = PTR_ERR(init_status);
1606                 dev_err(&dc->ndev->dev, "DSI host config failed\n");
1607                 goto fail;
1608         }
1609
1610         err = _tegra_dsi_write_data(dsi, pdata, data_id, data_len);
1611 fail:
1612         err = tegra_dsi_restore_state(dc, dsi, init_status);
1613         if (err < 0)
1614                 dev_err(&dc->ndev->dev, "Failed to restore prev state\n");
1615         tegra_dc_io_end(dc);
1616         return err;
1617 }
1618 EXPORT_SYMBOL(tegra_dsi_write_data);
1619
1620 static int tegra_dsi_send_panel_cmd(struct tegra_dc *dc,
1621                                         struct tegra_dc_dsi_data *dsi,
1622                                         struct tegra_dsi_cmd *cmd,
1623                                         u32 n_cmd)
1624 {
1625         u32 i;
1626         int err;
1627
1628         err = 0;
1629         for (i = 0; i < n_cmd; i++) {
1630                 struct tegra_dsi_cmd *cur_cmd;
1631                 cur_cmd = &cmd[i];
1632
1633                 if (cur_cmd->cmd_type == TEGRA_DSI_DELAY_MS)
1634                         mdelay(cur_cmd->sp_len_dly.delay_ms);
1635                 else {
1636                         err = tegra_dsi_write_data(dc, dsi,
1637                                                 cur_cmd->pdata,
1638                                                 cur_cmd->data_id,
1639                                                 cur_cmd->sp_len_dly.data_len);
1640                         if (err < 0)
1641                                 break;
1642                 }
1643         }
1644         return err;
1645 }
1646
1647 static u8 get_8bit_ecc(u32 header)
1648 {
1649         char ecc_parity[24] = {
1650                 0x07, 0x0b, 0x0d, 0x0e, 0x13, 0x15, 0x16, 0x19,
1651                 0x1a, 0x1c, 0x23, 0x25, 0x26, 0x29, 0x2a, 0x2c,
1652                 0x31, 0x32, 0x34, 0x38, 0x1f, 0x2f, 0x37, 0x3b
1653         };
1654         u8 ecc_byte;
1655         int i;
1656
1657         ecc_byte = 0;
1658         for (i = 0; i < 24; i++)
1659                 ecc_byte ^= ((header >> i) & 1) ? ecc_parity[i] : 0x00;
1660
1661         return ecc_byte;
1662 }
1663
1664 /* This function is written to send DCS short write (1 parameter) only.
1665  * This means the cmd will contain only 1 byte of index and 1 byte of value.
1666  * The data type ID is fixed at 0x15 and the ECC is calculated based on the
1667  * data in pdata.
1668  * The command will be sent by hardware every frame.
1669  * pdata should contain both the index + value for each cmd.
1670  * data_len will be the total number of bytes in pdata.
1671  */
1672 int tegra_dsi_send_panel_short_cmd(struct tegra_dc *dc, u8 *pdata, u8 data_len)
1673 {
1674         u8 ecc8bits = 0, data_len_orig = 0;
1675         u32 val = 0, pkthdr = 0;
1676         int err = 0, count = 0;
1677         struct tegra_dc_dsi_data *dsi = tegra_dc_get_outdata(dc);
1678
1679         data_len_orig = data_len;
1680         if (pdata != NULL) {
1681                 while (data_len) {
1682                         if (data_len >= 2) {
1683                                 pkthdr = (CMD_SHORTW |
1684                                         (((u16 *)pdata)[0]) << 8 | 0x00 << 24);
1685                                 ecc8bits = get_8bit_ecc(pkthdr);
1686                                 val = (pkthdr | (ecc8bits << 24));
1687                                 data_len -= 2;
1688                                 pdata += 2;
1689                                 count++;
1690                         }
1691                         switch (count) {
1692                         case 1:
1693                                 tegra_dsi_writel(dsi, val, DSI_INIT_SEQ_DATA_0);
1694                                 break;
1695                         case 2:
1696                                 tegra_dsi_writel(dsi, val, DSI_INIT_SEQ_DATA_1);
1697                                 break;
1698                         case 3:
1699                                 tegra_dsi_writel(dsi, val, DSI_INIT_SEQ_DATA_2);
1700                                 break;
1701                         case 4:
1702                                 tegra_dsi_writel(dsi, val, DSI_INIT_SEQ_DATA_3);
1703                                 break;
1704                         case 5:
1705                                 tegra_dsi_writel(dsi, val, DSI_INIT_SEQ_DATA_4);
1706                                 break;
1707                         case 6:
1708                                 tegra_dsi_writel(dsi, val, DSI_INIT_SEQ_DATA_5);
1709                                 break;
1710                         case 7:
1711                                 tegra_dsi_writel(dsi, val, DSI_INIT_SEQ_DATA_6);
1712                                 break;
1713                         case 8:
1714                                 tegra_dsi_writel(dsi, val, DSI_INIT_SEQ_DATA_7);
1715                                 break;
1716                         default:
1717                                 err = 1;
1718                                 break;
1719                         }
1720                 }
1721         }
1722
1723         val = DSI_INIT_SEQ_CONTROL_DSI_FRAME_INIT_BYTE_COUNT(data_len_orig * 2)
1724                 | DSI_INIT_SEQ_CONTROL_DSI_SEND_INIT_SEQUENCE(1);
1725         tegra_dsi_writel(dsi, val, DSI_INIT_SEQ_CONTROL);
1726
1727         return err;
1728 }
1729 EXPORT_SYMBOL(tegra_dsi_send_panel_short_cmd);
1730
1731 static int tegra_dsi_bta(struct tegra_dc_dsi_data *dsi)
1732 {
1733         u32 val;
1734         u32 poll_time;
1735         int err;
1736
1737         poll_time = 0;
1738         err = 0;
1739
1740         val = tegra_dsi_readl(dsi, DSI_HOST_DSI_CONTROL);
1741         val |= DSI_HOST_DSI_CONTROL_IMM_BTA(TEGRA_DSI_ENABLE);
1742         tegra_dsi_writel(dsi, val, DSI_HOST_DSI_CONTROL);
1743
1744 #if DSI_USE_SYNC_POINTS
1745         /* FIXME: Workaround for nvhost_syncpt_read */
1746         dsi->syncpt_val = nvhost_syncpt_update_min(
1747                         &dsi->dc->ndev->host->syncpt, dsi->syncpt_id);
1748
1749         val = DSI_INCR_SYNCPT_COND(OP_DONE) |
1750                 DSI_INCR_SYNCPT_INDX(dsi->syncpt_id);
1751         tegra_dsi_writel(dsi, val, DSI_INCR_SYNCPT);
1752
1753         /* TODO: Use interrupt rather than polling */
1754         err = nvhost_syncpt_wait(&dsi->dc->ndev->host->syncpt,
1755                 dsi->syncpt_id, dsi->syncpt_val + 1);
1756         if (err < 0)
1757                 dev_err(&dsi->dc->ndev->dev,
1758                         "DSI sync point failure\n");
1759         else
1760                 (dsi->syncpt_val)++;
1761 #else
1762         if (tegra_dsi_read_busy(dsi)) {
1763                 err = -EBUSY;
1764                 dev_err(&dsi->dc->ndev->dev,
1765                         "Timeout wating on read completion\n");
1766         }
1767 #endif
1768
1769         return err;
1770 }
1771
1772 static int tegra_dsi_parse_read_response(struct tegra_dc *dc,
1773                                         u32 rd_fifo_cnt, u8 *read_fifo)
1774 {
1775         int err;
1776         u32 payload_size;
1777
1778         payload_size = 0;
1779         err = 0;
1780
1781         switch (read_fifo[0]) {
1782         case DSI_ESCAPE_CMD:
1783                 dev_info(&dc->ndev->dev, "escape cmd[0x%x]\n", read_fifo[0]);
1784                 break;
1785         case DSI_ACK_NO_ERR:
1786                 dev_info(&dc->ndev->dev,
1787                         "Panel ack, no err[0x%x]\n", read_fifo[0]);
1788                 return err;
1789         default:
1790                 dev_info(&dc->ndev->dev, "Invalid read response\n");
1791                 break;
1792         }
1793
1794         switch (read_fifo[4] & 0xff) {
1795         case GEN_LONG_RD_RES:
1796                 /* Fall through */
1797         case DCS_LONG_RD_RES:
1798                 payload_size = (read_fifo[5] |
1799                                 (read_fifo[6] << 8)) & 0xFFFF;
1800                 dev_info(&dc->ndev->dev, "Long read response Packet\n"
1801                                 "payload_size[0x%x]\n", payload_size);
1802                 break;
1803         case GEN_1_BYTE_SHORT_RD_RES:
1804                 /* Fall through */
1805         case DCS_1_BYTE_SHORT_RD_RES:
1806                 payload_size = 1;
1807                 dev_info(&dc->ndev->dev, "Short read response Packet\n"
1808                         "payload_size[0x%x]\n", payload_size);
1809                 break;
1810         case GEN_2_BYTE_SHORT_RD_RES:
1811                 /* Fall through */
1812         case DCS_2_BYTE_SHORT_RD_RES:
1813                 payload_size = 2;
1814                 dev_info(&dc->ndev->dev, "Short read response Packet\n"
1815                         "payload_size[0x%x]\n", payload_size);
1816                 break;
1817         case ACK_ERR_RES:
1818                 payload_size = 2;
1819                 dev_info(&dc->ndev->dev, "Acknowledge error report response\n"
1820                         "Packet payload_size[0x%x]\n", payload_size);
1821                 break;
1822         default:
1823                 dev_info(&dc->ndev->dev, "Invalid response packet\n");
1824                 err = -EINVAL;
1825                 break;
1826         }
1827         return err;
1828 }
1829
1830 static int tegra_dsi_read_fifo(struct tegra_dc *dc,
1831                         struct tegra_dc_dsi_data *dsi,
1832                         u8 *read_fifo)
1833 {
1834         u32 val;
1835         u32 i;
1836         u32 poll_time = 0;
1837         u32 rd_fifo_cnt;
1838         int err = 0;
1839         u8 *read_fifo_cp = read_fifo;
1840
1841         while (poll_time <  DSI_DELAY_FOR_READ_FIFO) {
1842                 mdelay(1);
1843                 val = tegra_dsi_readl(dsi, DSI_STATUS);
1844                 rd_fifo_cnt = val & DSI_STATUS_RD_FIFO_COUNT(0x1f);
1845                 if (rd_fifo_cnt << 2 > DSI_READ_FIFO_DEPTH)
1846                         dev_err(&dc->ndev->dev,
1847                         "DSI RD_FIFO_CNT is greater than RD_FIFO_DEPTH\n");
1848                         break;
1849                 poll_time++;
1850         }
1851
1852         if (rd_fifo_cnt == 0) {
1853                 dev_info(&dc->ndev->dev,
1854                         "DSI RD_FIFO_CNT is zero\n");
1855                 err = -EINVAL;
1856                 goto fail;
1857         }
1858
1859         if (val & (DSI_STATUS_LB_UNDERFLOW(0x1) |
1860                 DSI_STATUS_LB_OVERFLOW(0x1))) {
1861                 dev_warn(&dc->ndev->dev,
1862                         "DSI overflow/underflow error\n");
1863         }
1864
1865         /* Read data from FIFO */
1866         for (i = 0; i < rd_fifo_cnt; i++) {
1867                 val = tegra_dsi_readl(dsi, DSI_RD_DATA);
1868                 if (enable_read_debug)
1869                         dev_info(&dc->ndev->dev,
1870                         "Read data[%d]: 0x%x\n", i, val);
1871                 memcpy(read_fifo, &val, 4);
1872                 read_fifo += 4;
1873         }
1874
1875         /* Make sure all the data is read from the FIFO */
1876         val = tegra_dsi_readl(dsi, DSI_STATUS);
1877         val &= DSI_STATUS_RD_FIFO_COUNT(0x1f);
1878         if (val)
1879                 dev_err(&dc->ndev->dev, "DSI FIFO_RD_CNT not zero"
1880                 " even after reading FIFO_RD_CNT words from read fifo\n");
1881
1882         if (enable_read_debug) {
1883                 err =
1884                 tegra_dsi_parse_read_response(dc, rd_fifo_cnt, read_fifo_cp);
1885                 if (err < 0)
1886                         dev_warn(&dc->ndev->dev, "Unexpected read data\n");
1887         }
1888 fail:
1889         return err;
1890 }
1891
1892 int tegra_dsi_read_data(struct tegra_dc *dc,
1893                                 struct tegra_dc_dsi_data *dsi,
1894                                 u32 max_ret_payload_size,
1895                                 u32 panel_reg_addr, u8 *read_data)
1896 {
1897         int err = 0;
1898         struct dsi_status *init_status;
1899
1900         tegra_dc_io_start(dc);
1901
1902         init_status = tegra_dsi_prepare_host_transmission(
1903                                 dc, dsi, DSI_LP_OP_WRITE);
1904         if (IS_ERR_OR_NULL(init_status)) {
1905                 err = PTR_ERR(init_status);
1906                 dev_err(&dc->ndev->dev, "DSI host config failed\n");
1907                 goto fail;
1908         }
1909
1910         /* Set max return payload size in words */
1911         err = _tegra_dsi_write_data(dsi, NULL,
1912                 dsi_command_max_return_pkt_size,
1913                 max_ret_payload_size);
1914         if (err < 0) {
1915                 dev_err(&dc->ndev->dev,
1916                                 "DSI write failed\n");
1917                 goto fail;
1918         }
1919
1920         /* DCS to read given panel register */
1921         err = _tegra_dsi_write_data(dsi, NULL,
1922                 dsi_command_dcs_read_with_no_params,
1923                 panel_reg_addr);
1924         if (err < 0) {
1925                 dev_err(&dc->ndev->dev,
1926                                 "DSI write failed\n");
1927                 goto fail;
1928         }
1929
1930         tegra_dsi_reset_read_count(dsi);
1931
1932         if (dsi->status.lp_op == DSI_LP_OP_WRITE) {
1933                 err = tegra_dsi_set_to_lp_mode(dc, dsi, DSI_LP_OP_READ);
1934                 if (err < 0) {
1935                         dev_err(&dc->ndev->dev,
1936                         "DSI failed to go to LP read mode\n");
1937                         goto fail;
1938                 }
1939         }
1940
1941         err = tegra_dsi_bta(dsi);
1942         if (err < 0) {
1943                 dev_err(&dc->ndev->dev,
1944                         "DSI IMM BTA timeout\n");
1945                 goto fail;
1946         }
1947
1948         err = tegra_dsi_read_fifo(dc, dsi, read_data);
1949         if (err < 0) {
1950                 dev_err(&dc->ndev->dev, "DSI read fifo failure\n");
1951                 goto fail;
1952         }
1953 fail:
1954         err = tegra_dsi_restore_state(dc, dsi, init_status);
1955         if (err < 0)
1956                 dev_err(&dc->ndev->dev, "Failed to restore prev state\n");
1957         tegra_dc_io_end(dc);
1958         return err;
1959 }
1960 EXPORT_SYMBOL(tegra_dsi_read_data);
1961
1962 int tegra_dsi_panel_sanity_check(struct tegra_dc *dc,
1963                                 struct tegra_dc_dsi_data *dsi)
1964 {
1965         int err = 0;
1966         u8 read_fifo[DSI_READ_FIFO_DEPTH];
1967         struct dsi_status *init_status;
1968         static struct tegra_dsi_cmd dsi_nop_cmd =
1969                         DSI_CMD_SHORT(0x05, 0x0, 0x0);
1970
1971         tegra_dc_io_start(dc);
1972
1973         init_status = tegra_dsi_prepare_host_transmission(
1974                                         dc, dsi, DSI_LP_OP_WRITE);
1975         if (IS_ERR_OR_NULL(init_status)) {
1976                 err = PTR_ERR(init_status);
1977                 dev_err(&dc->ndev->dev, "DSI host config failed\n");
1978                 goto fail;
1979         }
1980
1981         err = _tegra_dsi_write_data(dsi, NULL, dsi_nop_cmd.data_id, 0x0);
1982         if (err < 0) {
1983                 dev_err(&dc->ndev->dev, "DSI nop write failed\n");
1984                 goto fail;
1985         }
1986
1987         tegra_dsi_reset_read_count(dsi);
1988
1989         if (dsi->status.lp_op == DSI_LP_OP_WRITE) {
1990                 err = tegra_dsi_set_to_lp_mode(dc, dsi, DSI_LP_OP_READ);
1991                 if (err < 0) {
1992                         dev_err(&dc->ndev->dev,
1993                         "DSI failed to go to LP read mode\n");
1994                         goto fail;
1995                 }
1996         }
1997
1998         err = tegra_dsi_bta(dsi);
1999         if (err < 0) {
2000                 dev_err(&dc->ndev->dev, "DSI BTA failed\n");
2001                 goto fail;
2002         }
2003
2004         err = tegra_dsi_read_fifo(dc, dsi, read_fifo);
2005         if (err < 0) {
2006                 dev_err(&dc->ndev->dev, "DSI read fifo failure\n");
2007                 goto fail;
2008         }
2009
2010         if (read_fifo[0] != DSI_ACK_NO_ERR) {
2011                 dev_warn(&dc->ndev->dev,
2012                         "Ack no error trigger message not received\n");
2013                 err = -EAGAIN;
2014         }
2015 fail:
2016         err = tegra_dsi_restore_state(dc, dsi, init_status);
2017         if (err < 0)
2018                 dev_err(&dc->ndev->dev, "Failed to restore prev state\n");
2019         tegra_dc_io_end(dc);
2020         return err;
2021 }
2022 EXPORT_SYMBOL(tegra_dsi_panel_sanity_check);
2023
2024 static int tegra_dsi_enter_ulpm(struct tegra_dc_dsi_data *dsi)
2025 {
2026         u32 val;
2027         int ret;
2028
2029         ret = 0;
2030
2031         val = tegra_dsi_readl(dsi, DSI_HOST_DSI_CONTROL);
2032         val &= ~DSI_HOST_DSI_CONTROL_ULTRA_LOW_POWER(3);
2033         val |= DSI_HOST_DSI_CONTROL_ULTRA_LOW_POWER(ENTER_ULPM);
2034         tegra_dsi_writel(dsi, val, DSI_HOST_DSI_CONTROL);
2035
2036 #if DSI_USE_SYNC_POINTS
2037         ret = tegra_dsi_syncpt(dsi);
2038         if (ret < 0) {
2039                 dev_err(&dsi->dc->ndev->dev,
2040                         "DSI syncpt for ulpm enter failed\n");
2041                 goto fail;
2042         }
2043 #else
2044         /* TODO: Find exact delay required */
2045         mdelay(10);
2046 #endif
2047         dsi->ulpm = true;
2048 fail:
2049         return ret;
2050 }
2051
2052 static int tegra_dsi_exit_ulpm(struct tegra_dc_dsi_data *dsi)
2053 {
2054         u32 val;
2055         int ret;
2056
2057         ret = 0;
2058
2059         val = tegra_dsi_readl(dsi, DSI_HOST_DSI_CONTROL);
2060         val &= ~DSI_HOST_DSI_CONTROL_ULTRA_LOW_POWER(3);
2061         val |= DSI_HOST_DSI_CONTROL_ULTRA_LOW_POWER(EXIT_ULPM);
2062         tegra_dsi_writel(dsi, val, DSI_HOST_DSI_CONTROL);
2063
2064 #if DSI_USE_SYNC_POINTS
2065         ret = tegra_dsi_syncpt(dsi);
2066         if (ret < 0) {
2067                 dev_err(&dsi->dc->ndev->dev,
2068                         "DSI syncpt for ulpm exit failed\n");
2069                 goto fail;
2070         }
2071 #else
2072         /* TODO: Find exact delay required */
2073         mdelay(10);
2074 #endif
2075         dsi->ulpm = false;
2076
2077         val = tegra_dsi_readl(dsi, DSI_HOST_DSI_CONTROL);
2078         val &= ~DSI_HOST_DSI_CONTROL_ULTRA_LOW_POWER(0x3);
2079         val |= DSI_HOST_DSI_CONTROL_ULTRA_LOW_POWER(NORMAL);
2080         tegra_dsi_writel(dsi, val, DSI_HOST_DSI_CONTROL);
2081 fail:
2082         return ret;
2083
2084 }
2085
2086 static void tegra_dc_dsi_enable(struct tegra_dc *dc)
2087 {
2088         struct tegra_dc_dsi_data *dsi = tegra_dc_get_outdata(dc);
2089         int err;
2090         u32 val;
2091
2092         tegra_dc_io_start(dc);
2093         mutex_lock(&dsi->lock);
2094
2095         /* Stop DC stream before configuring DSI registers
2096          * to avoid visible glitches on panel during transition
2097          * from bootloader to kernel driver
2098          */
2099         tegra_dsi_stop_dc_stream(dc, dsi);
2100
2101         if (dsi->enabled) {
2102                 if (dsi->ulpm) {
2103                         if (tegra_dsi_exit_ulpm(dsi) < 0) {
2104                                 dev_err(&dc->ndev->dev,
2105                                         "DSI failed to exit ulpm\n");
2106                                 goto fail;
2107                         }
2108                 }
2109
2110                 if (dsi->info.panel_reset) {
2111                         err = tegra_dsi_send_panel_cmd(dc, dsi,
2112                                                         dsi->info.dsi_init_cmd,
2113                                                         dsi->info.n_init_cmd);
2114                         if (err < 0) {
2115                                 dev_err(&dc->ndev->dev,
2116                                 "dsi: error sending dsi init cmd\n");
2117                                 goto fail;
2118                         }
2119                 } else if (dsi->info.dsi_late_resume_cmd) {
2120                         err = tegra_dsi_send_panel_cmd(dc, dsi,
2121                                                 dsi->info.dsi_late_resume_cmd,
2122                                                 dsi->info.n_late_resume_cmd);
2123                         if (err < 0) {
2124                                 dev_err(&dc->ndev->dev,
2125                                 "dsi: error sending late resume cmd\n");
2126                                 goto fail;
2127                         }
2128                 }
2129         } else {
2130                 err = tegra_dsi_init_hw(dc, dsi);
2131                 if (err < 0) {
2132                         dev_err(&dc->ndev->dev,
2133                                 "dsi: not able to init dsi hardware\n");
2134                         goto fail;
2135                 }
2136
2137                 if (dsi->ulpm) {
2138                         if (tegra_dsi_enter_ulpm(dsi) < 0) {
2139                                 dev_err(&dc->ndev->dev,
2140                                         "DSI failed to enter ulpm\n");
2141                                 goto fail;
2142                         }
2143                         val = DSI_PAD_CONTROL_PAD_PDIO(0) |
2144                                 DSI_PAD_CONTROL_PAD_PDIO_CLK(0) |
2145                                 DSI_PAD_CONTROL_PAD_PULLDN_ENAB
2146                                                 (TEGRA_DSI_DISABLE);
2147                         tegra_dsi_writel(dsi, val, DSI_PAD_CONTROL);
2148                         if (tegra_dsi_exit_ulpm(dsi) < 0) {
2149                                 dev_err(&dc->ndev->dev,
2150                                         "DSI failed to exit ulpm\n");
2151                                 goto fail;
2152                         }
2153                 }
2154
2155                 err = tegra_dsi_set_to_lp_mode(dc, dsi, DSI_LP_OP_WRITE);
2156                 if (err < 0) {
2157                         dev_err(&dc->ndev->dev,
2158                                 "dsi: not able to set to lp mode\n");
2159                         goto fail;
2160                 }
2161
2162                 err = tegra_dsi_send_panel_cmd(dc, dsi, dsi->info.dsi_init_cmd,
2163                                                 dsi->info.n_init_cmd);
2164                 if (err < 0) {
2165                         dev_err(&dc->ndev->dev,
2166                                 "dsi: error while sending dsi init cmd\n");
2167                         goto fail;
2168                 }
2169
2170                 err = tegra_dsi_set_to_hs_mode(dc, dsi);
2171                 if (err < 0) {
2172                         dev_err(&dc->ndev->dev,
2173                                 "dsi: not able to set to hs mode\n");
2174                         goto fail;
2175                 }
2176
2177                 dsi->enabled = true;
2178         }
2179
2180         if (dsi->status.driven == DSI_DRIVEN_MODE_DC)
2181                 tegra_dsi_start_dc_stream(dc, dsi);
2182 fail:
2183         mutex_unlock(&dsi->lock);
2184         tegra_dc_io_end(dc);
2185 }
2186
2187 static void _tegra_dc_dsi_init(struct tegra_dc *dc)
2188 {
2189         struct tegra_dc_dsi_data *dsi = tegra_dc_get_outdata(dc);
2190
2191         tegra_dsi_init_sw(dc, dsi);
2192         /* TODO: Configure the CSI pad configuration */
2193 }
2194
2195 static int tegra_dc_dsi_cp_p_cmd(struct tegra_dsi_cmd *src,
2196                                         struct tegra_dsi_cmd *dst, u16 n_cmd)
2197 {
2198         u16 i;
2199         u16 len;
2200
2201         memcpy(dst, src, sizeof(*dst) * n_cmd);
2202
2203         for (i = 0; i < n_cmd; i++)
2204                 if (src[i].pdata) {
2205                         len = sizeof(*src[i].pdata) *
2206                                         src[i].sp_len_dly.data_len;
2207                         dst[i].pdata = kzalloc(len, GFP_KERNEL);
2208                         if (!dst[i].pdata)
2209                                 goto free_cmd_pdata;
2210                         memcpy(dst[i].pdata, src[i].pdata, len);
2211                 }
2212
2213         return 0;
2214
2215 free_cmd_pdata:
2216         for (--i; i >= 0; i--)
2217                 if (dst[i].pdata)
2218                         kfree(dst[i].pdata);
2219         return -ENOMEM;
2220 }
2221
2222 static int tegra_dc_dsi_cp_info(struct tegra_dc_dsi_data *dsi,
2223                                         struct tegra_dsi_out *p_dsi)
2224 {
2225         struct tegra_dsi_cmd *p_init_cmd;
2226         struct tegra_dsi_cmd *p_early_suspend_cmd;
2227         struct tegra_dsi_cmd *p_late_resume_cmd;
2228         struct tegra_dsi_cmd *p_suspend_cmd;
2229         int err;
2230
2231         if (p_dsi->n_data_lanes > MAX_DSI_DATA_LANES)
2232                 return -EINVAL;
2233
2234         p_init_cmd = kzalloc(sizeof(*p_init_cmd) *
2235                                 p_dsi->n_init_cmd, GFP_KERNEL);
2236         if (!p_init_cmd)
2237                 return -ENOMEM;
2238
2239         if (p_dsi->dsi_early_suspend_cmd) {
2240                 p_early_suspend_cmd = kzalloc(sizeof(*p_early_suspend_cmd) *
2241                                         p_dsi->n_early_suspend_cmd,
2242                                         GFP_KERNEL);
2243                 if (!p_early_suspend_cmd) {
2244                         err = -ENOMEM;
2245                         goto err_free_init_cmd;
2246                 }
2247         }
2248
2249         if (p_dsi->dsi_late_resume_cmd) {
2250                 p_late_resume_cmd = kzalloc(sizeof(*p_late_resume_cmd) *
2251                                         p_dsi->n_late_resume_cmd,
2252                                         GFP_KERNEL);
2253                 if (!p_late_resume_cmd) {
2254                         err = -ENOMEM;
2255                         goto err_free_p_early_suspend_cmd;
2256                 }
2257         }
2258
2259         p_suspend_cmd = kzalloc(sizeof(*p_suspend_cmd) * p_dsi->n_suspend_cmd,
2260                                 GFP_KERNEL);
2261         if (!p_suspend_cmd) {
2262                 err = -ENOMEM;
2263                 goto err_free_p_late_resume_cmd;
2264         }
2265
2266         memcpy(&dsi->info, p_dsi, sizeof(dsi->info));
2267
2268         /* Copy panel init cmd */
2269         err = tegra_dc_dsi_cp_p_cmd(p_dsi->dsi_init_cmd,
2270                                                 p_init_cmd, p_dsi->n_init_cmd);
2271         if (err < 0)
2272                 goto err_free;
2273         dsi->info.dsi_init_cmd = p_init_cmd;
2274
2275         /* Copy panel early suspend cmd */
2276         if (p_dsi->dsi_early_suspend_cmd) {
2277                 err = tegra_dc_dsi_cp_p_cmd(p_dsi->dsi_early_suspend_cmd,
2278                                         p_early_suspend_cmd,
2279                                         p_dsi->n_early_suspend_cmd);
2280                 if (err < 0)
2281                         goto err_free;
2282                 dsi->info.dsi_early_suspend_cmd = p_early_suspend_cmd;
2283         }
2284
2285         /* Copy panel late resume cmd */
2286         if (p_dsi->dsi_late_resume_cmd) {
2287                 err = tegra_dc_dsi_cp_p_cmd(p_dsi->dsi_late_resume_cmd,
2288                                                 p_late_resume_cmd,
2289                                                 p_dsi->n_late_resume_cmd);
2290                 if (err < 0)
2291                         goto err_free;
2292                 dsi->info.dsi_late_resume_cmd = p_late_resume_cmd;
2293         }
2294
2295         /* Copy panel suspend cmd */
2296         err = tegra_dc_dsi_cp_p_cmd(p_dsi->dsi_suspend_cmd, p_suspend_cmd,
2297                                         p_dsi->n_suspend_cmd);
2298         if (err < 0)
2299                 goto err_free;
2300         dsi->info.dsi_suspend_cmd = p_suspend_cmd;
2301
2302         if (!dsi->info.panel_reset_timeout_msec)
2303                 dsi->info.panel_reset_timeout_msec =
2304                                                 DEFAULT_PANEL_RESET_TIMEOUT;
2305
2306         if (!dsi->info.panel_buffer_size_byte)
2307                 dsi->info.panel_buffer_size_byte = DEFAULT_PANEL_BUFFER_BYTE;
2308
2309         if (!dsi->info.max_panel_freq_khz) {
2310                 dsi->info.max_panel_freq_khz = DEFAULT_MAX_DSI_PHY_CLK_KHZ;
2311
2312                 if (dsi->info.video_burst_mode >
2313                                 TEGRA_DSI_VIDEO_NONE_BURST_MODE_WITH_SYNC_END){
2314                         dev_err(&dsi->dc->ndev->dev, "DSI: max_panel_freq_khz"
2315                                         "is not set for DSI burst mode.\n");
2316                         dsi->info.video_burst_mode =
2317                                 TEGRA_DSI_VIDEO_BURST_MODE_LOWEST_SPEED;
2318                 }
2319         }
2320
2321         if (!dsi->info.lp_cmd_mode_freq_khz)
2322                 dsi->info.lp_cmd_mode_freq_khz = DEFAULT_LP_CMD_MODE_CLK_KHZ;
2323
2324         if (!dsi->info.chip_id || !dsi->info.chip_rev)
2325                 dev_warn(&dsi->dc->ndev->dev,
2326                         "DSI: Failed to get chip info\n");
2327
2328         if (!dsi->info.lp_read_cmd_mode_freq_khz)
2329                 dsi->info.lp_read_cmd_mode_freq_khz =
2330                         dsi->info.lp_cmd_mode_freq_khz;
2331
2332         /* host mode is for testing only */
2333         dsi->driven_mode = TEGRA_DSI_DRIVEN_BY_DC;
2334         return 0;
2335
2336 err_free:
2337         kfree(p_suspend_cmd);
2338 err_free_p_late_resume_cmd:
2339         kfree(p_late_resume_cmd);
2340 err_free_p_early_suspend_cmd:
2341         kfree(p_early_suspend_cmd);
2342 err_free_init_cmd:
2343         kfree(p_init_cmd);
2344         return err;
2345 }
2346
2347 static int tegra_dc_dsi_init(struct tegra_dc *dc)
2348 {
2349         struct tegra_dc_dsi_data *dsi;
2350         struct resource *res;
2351         struct resource *base_res;
2352         void __iomem *base;
2353         struct clk *dc_clk = NULL;
2354         struct clk *dsi_clk = NULL;
2355         struct tegra_dsi_out *dsi_pdata;
2356         int err;
2357
2358         err = 0;
2359
2360         dsi = kzalloc(sizeof(*dsi), GFP_KERNEL);
2361         if (!dsi)
2362                 return -ENOMEM;
2363
2364         res = nvhost_get_resource_byname(dc->ndev, IORESOURCE_MEM,
2365                                         "dsi_regs");
2366         if (!res) {
2367                 dev_err(&dc->ndev->dev, "dsi: no mem resource\n");
2368                 err = -ENOENT;
2369                 goto err_free_dsi;
2370         }
2371
2372         base_res = request_mem_region(res->start, resource_size(res),
2373                                 dc->ndev->name);
2374         if (!base_res) {
2375                 dev_err(&dc->ndev->dev, "dsi: request_mem_region failed\n");
2376                 err = -EBUSY;
2377                 goto err_free_dsi;
2378         }
2379
2380         base = ioremap(res->start, resource_size(res));
2381         if (!base) {
2382                 dev_err(&dc->ndev->dev, "dsi: registers can't be mapped\n");
2383                 err = -EBUSY;
2384                 goto err_release_regs;
2385         }
2386
2387         dsi_pdata = dc->pdata->default_out->dsi;
2388         if (!dsi_pdata) {
2389                 dev_err(&dc->ndev->dev, "dsi: dsi data not available\n");
2390                 goto err_release_regs;
2391         }
2392
2393         if (dsi_pdata->dsi_instance)
2394                 dsi_clk = clk_get(&dc->ndev->dev, "dsib");
2395         else
2396                 dsi_clk = clk_get(&dc->ndev->dev, "dsia");
2397
2398         if (IS_ERR_OR_NULL(dsi_clk)) {
2399                 dev_err(&dc->ndev->dev, "dsi: can't get clock\n");
2400                 err = -EBUSY;
2401                 goto err_release_regs;
2402         }
2403
2404         dc_clk = clk_get_sys(dev_name(&dc->ndev->dev), NULL);
2405         if (IS_ERR_OR_NULL(dc_clk)) {
2406                 dev_err(&dc->ndev->dev, "dsi: dc clock %s unavailable\n",
2407                         dev_name(&dc->ndev->dev));
2408                 err = -EBUSY;
2409                 goto err_clk_put;
2410         }
2411
2412         mutex_init(&dsi->lock);
2413         dsi->dc = dc;
2414         dsi->base = base;
2415         dsi->base_res = base_res;
2416         dsi->dc_clk = dc_clk;
2417         dsi->dsi_clk = dsi_clk;
2418
2419         err = tegra_dc_dsi_cp_info(dsi, dsi_pdata);
2420         if (err < 0)
2421                 goto err_dsi_data;
2422
2423         tegra_dc_set_outdata(dc, dsi);
2424         _tegra_dc_dsi_init(dc);
2425
2426         return 0;
2427
2428 err_dsi_data:
2429 err_clk_put:
2430         clk_put(dsi_clk);
2431 err_release_regs:
2432         release_resource(base_res);
2433 err_free_dsi:
2434         kfree(dsi);
2435
2436         return err;
2437 }
2438
2439 static void tegra_dc_dsi_destroy(struct tegra_dc *dc)
2440 {
2441         struct tegra_dc_dsi_data *dsi = tegra_dc_get_outdata(dc);
2442         u16 i;
2443         u32 val;
2444
2445         mutex_lock(&dsi->lock);
2446
2447         /* free up the pdata */
2448         for (i = 0; i < dsi->info.n_init_cmd; i++) {
2449                 if (dsi->info.dsi_init_cmd[i].pdata)
2450                         kfree(dsi->info.dsi_init_cmd[i].pdata);
2451         }
2452         kfree(dsi->info.dsi_init_cmd);
2453
2454         /* Disable dc stream */
2455         if (dsi->status.dc_stream == DSI_DC_STREAM_ENABLE)
2456                 tegra_dsi_stop_dc_stream_at_frame_end(dc, dsi);
2457
2458         /* Disable dsi phy clock */
2459         if (dsi->status.clk_out == DSI_PHYCLK_OUT_EN)
2460                 tegra_dsi_hs_clk_out_disable(dc, dsi);
2461
2462         val = DSI_POWER_CONTROL_LEG_DSI_ENABLE(TEGRA_DSI_DISABLE);
2463         tegra_dsi_writel(dsi, val, DSI_POWER_CONTROL);
2464
2465         iounmap(dsi->base);
2466         release_resource(dsi->base_res);
2467
2468         clk_put(dsi->dc_clk);
2469         clk_put(dsi->dsi_clk);
2470
2471         mutex_unlock(&dsi->lock);
2472
2473         mutex_destroy(&dsi->lock);
2474         kfree(dsi);
2475 }
2476
2477 static int tegra_dsi_deep_sleep(struct tegra_dc *dc,
2478                                 struct tegra_dc_dsi_data *dsi)
2479 {
2480         int err = 0;
2481         int val;
2482         struct clk *parent_clk = NULL;
2483         struct clk *base_clk = NULL;
2484
2485         if (!dsi->enabled) {
2486                 err = -EPERM;
2487                 goto fail;
2488         }
2489
2490         err = tegra_dsi_set_to_lp_mode(dc, dsi, DSI_LP_OP_WRITE);
2491         if (err < 0) {
2492                 dev_err(&dc->ndev->dev,
2493                 "DSI failed to go to LP mode\n");
2494                 goto fail;
2495         }
2496
2497         /* Suspend panel */
2498         err = tegra_dsi_send_panel_cmd(dc, dsi,
2499                         dsi->info.dsi_suspend_cmd,
2500                         dsi->info.n_suspend_cmd);
2501         if (err < 0) {
2502                 dev_err(&dc->ndev->dev,
2503                         "dsi: Error sending suspend cmd\n");
2504                 goto fail;
2505         }
2506
2507         if (!dsi->ulpm) {
2508                 err = tegra_dsi_enter_ulpm(dsi);
2509                 if (err < 0) {
2510                         dev_err(&dc->ndev->dev,
2511                                 "DSI failed to enter ulpm\n");
2512                         goto fail;
2513                 }
2514         }
2515
2516         /* Suspend pad */
2517         val = tegra_dsi_readl(dsi, DSI_PAD_CONTROL);
2518         val = DSI_PAD_CONTROL_PAD_PDIO(0x3) |
2519                 DSI_PAD_CONTROL_PAD_PDIO_CLK(0x1) |
2520                 DSI_PAD_CONTROL_PAD_PULLDN_ENAB(TEGRA_DSI_ENABLE);
2521         tegra_dsi_writel(dsi, val, DSI_PAD_CONTROL);
2522
2523         /* Suspend core-logic */
2524         val = DSI_POWER_CONTROL_LEG_DSI_ENABLE(TEGRA_DSI_DISABLE);
2525         tegra_dsi_writel(dsi, val, DSI_POWER_CONTROL);
2526
2527         /* Disable dsi fast and slow clock */
2528         parent_clk = clk_get_parent(dsi->dsi_clk);
2529         base_clk = clk_get_parent(parent_clk);
2530         if (dsi->info.dsi_instance)
2531                 tegra_clk_cfg_ex(base_clk,
2532                                 TEGRA_CLK_PLLD_CSI_OUT_ENB,
2533                                 0);
2534         else
2535                 tegra_clk_cfg_ex(base_clk,
2536                                 TEGRA_CLK_PLLD_DSI_OUT_ENB,
2537                                 0);
2538
2539         /* Disable dsi source clock */
2540         clk_disable(dsi->dsi_clk);
2541
2542         dsi->clk_ref = false;
2543         dsi->enabled = false;
2544
2545         return 0;
2546 fail:
2547         return err;
2548 }
2549
2550 static void tegra_dc_dsi_disable(struct tegra_dc *dc)
2551 {
2552         int err;
2553         struct tegra_dc_dsi_data *dsi = tegra_dc_get_outdata(dc);
2554
2555         tegra_dc_io_start(dc);
2556         mutex_lock(&dsi->lock);
2557
2558         if (dsi->status.dc_stream == DSI_DC_STREAM_ENABLE)
2559                 tegra_dsi_stop_dc_stream_at_frame_end(dc, dsi);
2560
2561         if (dsi->info.power_saving_suspend) {
2562                 if (tegra_dsi_deep_sleep(dc, dsi) < 0) {
2563                         dev_err(&dc->ndev->dev,
2564                                 "DSI failed to enter deep sleep\n");
2565                         goto fail;
2566                 }
2567         } else {
2568                 if (dsi->info.dsi_early_suspend_cmd) {
2569                         err = tegra_dsi_send_panel_cmd(dc, dsi,
2570                                 dsi->info.dsi_early_suspend_cmd,
2571                                 dsi->info.n_early_suspend_cmd);
2572                         if (err < 0) {
2573                                 dev_err(&dc->ndev->dev,
2574                                 "dsi: Error sending early suspend cmd\n");
2575                                 goto fail;
2576                         }
2577                 }
2578
2579                 if (!dsi->ulpm) {
2580                         if (tegra_dsi_enter_ulpm(dsi) < 0) {
2581                                 dev_err(&dc->ndev->dev,
2582                                         "DSI failed to enter ulpm\n");
2583                                 goto fail;
2584                         }
2585                 }
2586         }
2587
2588 fail:
2589         mutex_unlock(&dsi->lock);
2590         tegra_dc_io_end(dc);
2591 }
2592
2593 #ifdef CONFIG_PM
2594 static void tegra_dc_dsi_suspend(struct tegra_dc *dc)
2595 {
2596         struct tegra_dc_dsi_data *dsi;
2597
2598         dsi = tegra_dc_get_outdata(dc);
2599
2600         tegra_dc_io_start(dc);
2601         mutex_lock(&dsi->lock);
2602
2603         if (!dsi->enabled)
2604                 goto fail;
2605
2606         if (!dsi->info.power_saving_suspend) {
2607                 if (dsi->ulpm) {
2608                         if (tegra_dsi_exit_ulpm(dsi) < 0) {
2609                                 dev_err(&dc->ndev->dev,
2610                                         "DSI failed to exit ulpm");
2611                                 goto fail;
2612                         }
2613                 }
2614
2615                 if (tegra_dsi_deep_sleep(dc, dsi) < 0) {
2616                         dev_err(&dc->ndev->dev,
2617                                 "DSI failed to enter deep sleep\n");
2618                         goto fail;
2619                 }
2620         }
2621 fail:
2622         mutex_unlock(&dsi->lock);
2623         tegra_dc_io_end(dc);
2624 }
2625
2626 static void tegra_dc_dsi_resume(struct tegra_dc *dc)
2627 {
2628         /* Not required since tegra_dc_dsi_enable
2629          * will reconfigure the controller from scratch
2630          */
2631 }
2632 #endif
2633
2634 struct tegra_dc_out_ops tegra_dc_dsi_ops = {
2635         .init = tegra_dc_dsi_init,
2636         .destroy = tegra_dc_dsi_destroy,
2637         .enable = tegra_dc_dsi_enable,
2638         .disable = tegra_dc_dsi_disable,
2639 #ifdef CONFIG_PM
2640         .suspend = tegra_dc_dsi_suspend,
2641         .resume = tegra_dc_dsi_resume,
2642 #endif
2643 };