video: tegra: dsi: Fix DC & DSI clock issue.
[linux-2.6.git] / drivers / video / tegra / dc / dsi.c
1 /*
2  * drivers/video/tegra/dc/dsi.c
3  *
4  * Copyright (c) 2011, NVIDIA Corporation.
5  *
6  * This software is licensed under the terms of the GNU General Public
7  * License version 2, as published by the Free Software Foundation, and
8  * may be copied, distributed, and modified under those terms.
9  *
10  * This program is distributed in the hope that it will be useful,
11  * but WITHOUT ANY WARRANTY; without even the implied warranty of
12  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
13  * GNU General Public License for more details.
14  *
15  */
16
17 #include <linux/clk.h>
18 #include <linux/delay.h>
19 #include <linux/err.h>
20 #include <linux/fb.h>
21 #include <linux/gpio.h>
22 #include <linux/interrupt.h>
23 #include <linux/kernel.h>
24 #include <linux/slab.h>
25 #include <linux/spinlock.h>
26 #include <linux/workqueue.h>
27
28 #include <mach/clk.h>
29 #include <mach/dc.h>
30 #include <mach/fb.h>
31 #include <mach/nvhost.h>
32 #include <../gpio-names.h>
33
34 #include "dc_reg.h"
35 #include "dc_priv.h"
36 #include "dsi_regs.h"
37 #include "dsi.h"
38
39 #define DSI_USE_SYNC_POINTS 1
40
41 #define DSI_STOP_DC_DURATION_MSEC 1000
42
43 #define DSI_MODULE_NOT_INIT             0x0
44 #define DSI_MODULE_INIT                 0x1
45
46 #define DSI_LPHS_NOT_INIT               0x0
47 #define DSI_LPHS_IN_LP_MODE             0x1
48 #define DSI_LPHS_IN_HS_MODE             0x2
49
50 #define DSI_VIDEO_TYPE_NOT_INIT         0x0
51 #define DSI_VIDEO_TYPE_VIDEO_MODE       0x1
52 #define DSI_VIDEO_TYPE_CMD_MODE         0x2
53
54 #define DSI_DRIVEN_MODE_NOT_INIT        0x0
55 #define DSI_DRIVEN_MODE_DC              0x1
56 #define DSI_DRIVEN_MODE_HOST            0x2
57
58 #define DSI_PHYCLK_OUT_DIS              0x0
59 #define DSI_PHYCLK_OUT_EN               0x1
60
61 #define DSI_PHYCLK_NOT_INIT             0x0
62 #define DSI_PHYCLK_CONTINUOUS           0x1
63 #define DSI_PHYCLK_TX_ONLY              0x2
64
65 #define DSI_CLK_BURST_NOT_INIT          0x0
66 #define DSI_CLK_BURST_NONE_BURST        0x1
67 #define DSI_CLK_BURST_BURST_MODE        0x2
68
69 #define DSI_DC_STREAM_DISABLE           0x0
70 #define DSI_DC_STREAM_ENABLE            0x1
71
72 struct dsi_status {
73         unsigned        init:2;
74
75         unsigned        lphs:2;
76
77         unsigned        vtype:2;
78         unsigned        driven:2;
79
80         unsigned        clk_out:2;
81         unsigned        clk_mode:2;
82         unsigned        clk_burst:2;
83
84         unsigned        dc_stream:1;
85 };
86
87 /* source of video data */
88 enum{
89         TEGRA_DSI_DRIVEN_BY_DC,
90         TEGRA_DSI_DRIVEN_BY_HOST,
91 };
92
93 struct tegra_dc_dsi_data {
94         struct tegra_dc *dc;
95         void __iomem    *base;
96         struct resource *base_res;
97
98         struct clk              *dc_clk;
99         struct clk              *dsi_clk;
100         bool                    clk_ref;
101
102         struct mutex    lock;
103
104         /* data from board info */
105         struct tegra_dsi_out info;
106
107         struct dsi_status       status;
108
109         u8              driven_mode;
110         u8              controller_index;
111
112         u8              pixel_scaler_mul;
113         u8              pixel_scaler_div;
114
115         u32             default_shift_clk_div;
116         u32             default_pixel_clk_khz;
117         u32             default_hs_clk_khz;
118
119         u32             shift_clk_div;
120         u32             target_hs_clk_khz;
121         u32             target_lp_clk_khz;
122
123         u32             syncpt_id;
124         u32             syncpt_val;
125
126         u16             current_bit_clk_ns;
127         u32             current_dsi_clk_khz;
128
129         u32             dsi_control_val;
130
131         bool            ulpm;
132         bool            enabled;
133 };
134
135 const u32 dsi_pkt_seq_reg[NUMOF_PKT_SEQ] = {
136         DSI_PKT_SEQ_0_LO,
137         DSI_PKT_SEQ_0_HI,
138         DSI_PKT_SEQ_1_LO,
139         DSI_PKT_SEQ_1_HI,
140         DSI_PKT_SEQ_2_LO,
141         DSI_PKT_SEQ_2_HI,
142         DSI_PKT_SEQ_3_LO,
143         DSI_PKT_SEQ_3_HI,
144         DSI_PKT_SEQ_4_LO,
145         DSI_PKT_SEQ_4_HI,
146         DSI_PKT_SEQ_5_LO,
147         DSI_PKT_SEQ_5_HI,
148 };
149
150 const u32 dsi_pkt_seq_video_non_burst_syne[NUMOF_PKT_SEQ] = {
151         PKT_ID0(CMD_VS) | PKT_LEN0(0) | PKT_ID1(CMD_EOT) | PKT_LEN1(0) | PKT_LP,
152         0,
153         PKT_ID0(CMD_VE) | PKT_LEN0(0) | PKT_ID1(CMD_EOT) | PKT_LEN1(0) | PKT_LP,
154         0,
155         PKT_ID0(CMD_HS) | PKT_LEN0(0) | PKT_ID1(CMD_EOT) | PKT_LEN1(0) | PKT_LP,
156         0,
157         PKT_ID0(CMD_HS) | PKT_LEN0(0) | PKT_ID1(CMD_BLNK) | PKT_LEN1(1) |
158                 PKT_ID2(CMD_HE) | PKT_LEN2(0),
159         PKT_ID3(CMD_BLNK) | PKT_LEN3(2) | PKT_ID4(CMD_RGB) | PKT_LEN4(3) |
160                 PKT_ID5(CMD_BLNK) | PKT_LEN5(4),
161         PKT_ID0(CMD_HS) | PKT_LEN0(0) | PKT_ID1(CMD_EOT) | PKT_LEN1(0) | PKT_LP,
162         0,
163         PKT_ID0(CMD_HS) | PKT_LEN0(0) | PKT_ID1(CMD_BLNK) | PKT_LEN1(1) |
164                 PKT_ID2(CMD_HE) | PKT_LEN2(0),
165         PKT_ID3(CMD_BLNK) | PKT_LEN3(2) | PKT_ID4(CMD_RGB) | PKT_LEN4(3) |
166                 PKT_ID5(CMD_BLNK) | PKT_LEN5(4),
167 };
168
169 const u32 dsi_pkt_seq_video_non_burst[NUMOF_PKT_SEQ] = {
170         PKT_ID0(CMD_VS) | PKT_LEN0(0) | PKT_ID1(CMD_EOT) | PKT_LEN1(0) | PKT_LP,
171         0,
172         PKT_ID0(CMD_HS) | PKT_LEN0(0) | PKT_ID1(CMD_EOT) | PKT_LEN1(0) | PKT_LP,
173         0,
174         PKT_ID0(CMD_HS) | PKT_LEN0(0) | PKT_ID1(CMD_EOT) | PKT_LEN1(0) | PKT_LP,
175         0,
176         PKT_ID0(CMD_HS) | PKT_LEN0(0) | PKT_ID1(CMD_BLNK) | PKT_LEN1(2) |
177                 PKT_ID2(CMD_RGB) | PKT_LEN2(3),
178         PKT_ID3(CMD_BLNK) | PKT_LEN3(4),
179         PKT_ID0(CMD_HS) | PKT_LEN0(0) | PKT_ID1(CMD_EOT) | PKT_LEN1(0) | PKT_LP,
180         0,
181         PKT_ID0(CMD_HS) | PKT_LEN0(0) | PKT_ID1(CMD_BLNK) | PKT_LEN1(2) |
182                 PKT_ID2(CMD_RGB) | PKT_LEN2(3),
183         PKT_ID3(CMD_BLNK) | PKT_LEN3(4),
184 };
185
186 static const u32 dsi_pkt_seq_video_burst[NUMOF_PKT_SEQ] = {
187         PKT_ID0(CMD_VS) | PKT_LEN0(0) | PKT_ID1(CMD_EOT) | PKT_LEN1(7) | PKT_LP,
188         0,
189         PKT_ID0(CMD_HS) | PKT_LEN0(0) | PKT_ID1(CMD_EOT) | PKT_LEN1(7) | PKT_LP,
190         0,
191         PKT_ID0(CMD_HS) | PKT_LEN0(0) | PKT_ID1(CMD_EOT) | PKT_LEN1(7) | PKT_LP,
192         0,
193         PKT_ID0(CMD_HS) | PKT_LEN0(0) | PKT_ID1(CMD_BLNK) | PKT_LEN1(2)|
194         PKT_ID2(CMD_RGB) | PKT_LEN2(3) | PKT_LP,
195         PKT_ID0(CMD_EOT) | PKT_LEN0(7),
196         PKT_ID0(CMD_HS) | PKT_LEN0(0) | PKT_ID1(CMD_EOT) | PKT_LEN1(7) | PKT_LP,
197         0,
198         PKT_ID0(CMD_HS) | PKT_LEN0(0) | PKT_ID1(CMD_BLNK) | PKT_LEN1(2)|
199         PKT_ID2(CMD_RGB) | PKT_LEN2(3) | PKT_LP,
200         PKT_ID0(CMD_EOT) | PKT_LEN0(7),
201 };
202
203 static const u32 dsi_pkt_seq_video_burst_no_eot[NUMOF_PKT_SEQ] = {
204         PKT_ID0(CMD_VS) | PKT_LEN0(0) | PKT_ID1(CMD_EOT) | PKT_LEN1(0) | PKT_LP,
205         0,
206         PKT_ID0(CMD_HS) | PKT_LEN0(0) | PKT_ID1(CMD_EOT) | PKT_LEN1(0) | PKT_LP,
207         0,
208         PKT_ID0(CMD_HS) | PKT_LEN0(0) | PKT_ID1(CMD_EOT) | PKT_LEN1(0) | PKT_LP,
209         0,
210         PKT_ID0(CMD_HS) | PKT_LEN0(0) | PKT_ID1(CMD_BLNK) | PKT_LEN1(2)|
211         PKT_ID2(CMD_RGB) | PKT_LEN2(3) | PKT_LP,
212         PKT_ID0(CMD_EOT) | PKT_LEN0(0),
213         PKT_ID0(CMD_HS) | PKT_LEN0(0) | PKT_ID1(CMD_EOT) | PKT_LEN1(0) | PKT_LP,
214         0,
215         PKT_ID0(CMD_HS) | PKT_LEN0(0) | PKT_ID1(CMD_BLNK) | PKT_LEN1(2)|
216         PKT_ID2(CMD_RGB) | PKT_LEN2(3) | PKT_LP,
217         PKT_ID0(CMD_EOT) | PKT_LEN0(0),
218 };
219
220 /* TODO: verify with hw about this format */
221 const u32 dsi_pkt_seq_cmd_mode [NUMOF_PKT_SEQ] = {
222         0,
223         0,
224         0,
225         0,
226         0,
227         0,
228         PKT_ID0(CMD_LONGW) | PKT_LEN0(3) | PKT_ID1(CMD_EOT) | PKT_LEN1(7),
229         0,
230         0,
231         0,
232         PKT_ID0(CMD_LONGW) | PKT_LEN0(3) | PKT_ID1(CMD_EOT) | PKT_LEN1(7),
233         0,
234 };
235
236 const u32 init_reg[] = {
237         DSI_WR_DATA,
238         DSI_INT_ENABLE,
239         DSI_INT_STATUS,
240         DSI_INT_MASK,
241         DSI_INIT_SEQ_DATA_0,
242         DSI_INIT_SEQ_DATA_1,
243         DSI_INIT_SEQ_DATA_2,
244         DSI_INIT_SEQ_DATA_3,
245         DSI_DCS_CMDS,
246         DSI_PKT_SEQ_0_LO,
247         DSI_PKT_SEQ_1_LO,
248         DSI_PKT_SEQ_2_LO,
249         DSI_PKT_SEQ_3_LO,
250         DSI_PKT_SEQ_4_LO,
251         DSI_PKT_SEQ_5_LO,
252         DSI_PKT_SEQ_0_HI,
253         DSI_PKT_SEQ_1_HI,
254         DSI_PKT_SEQ_2_HI,
255         DSI_PKT_SEQ_3_HI,
256         DSI_PKT_SEQ_4_HI,
257         DSI_PKT_SEQ_5_HI,
258         DSI_CONTROL,
259         DSI_HOST_DSI_CONTROL,
260         DSI_PAD_CONTROL,
261         DSI_PAD_CONTROL_CD,
262         DSI_SOL_DELAY,
263         DSI_MAX_THRESHOLD,
264         DSI_TRIGGER,
265         DSI_TX_CRC,
266         DSI_INIT_SEQ_CONTROL,
267         DSI_PKT_LEN_0_1,
268         DSI_PKT_LEN_2_3,
269         DSI_PKT_LEN_4_5,
270         DSI_PKT_LEN_6_7,
271 };
272
273 static inline unsigned long tegra_dsi_readl(struct tegra_dc_dsi_data *dsi,
274                                                                         u32 reg)
275 {
276         return readl(dsi->base + reg * 4);
277 }
278
279 static inline void tegra_dsi_writel(struct tegra_dc_dsi_data *dsi,u32 val,
280                                                                         u32 reg)
281 {
282         writel(val, dsi->base + reg * 4);
283 }
284
285 static int tegra_dsi_syncpt(struct tegra_dc_dsi_data *dsi)
286 {
287         u32 val;
288         int ret;
289
290         ret = 0;
291
292         dsi->syncpt_val = nvhost_syncpt_read(
293                         &dsi->dc->ndev->host->syncpt, dsi->syncpt_id);
294
295         val = DSI_INCR_SYNCPT_COND(OP_DONE) |
296                 DSI_INCR_SYNCPT_INDX(dsi->syncpt_id);
297         tegra_dsi_writel(dsi, val, DSI_INCR_SYNCPT);
298
299         /* TODO: Use interrupt rather than polling */
300         ret = nvhost_syncpt_wait(&dsi->dc->ndev->host->syncpt,
301                 dsi->syncpt_id, dsi->syncpt_val + 1);
302         if (ret < 0) {
303                 printk(KERN_ERR "DSI sync point failure\n");
304                 goto fail;
305         }
306
307         (dsi->syncpt_val)++;
308         return 0;
309 fail:
310         return ret;
311 }
312
313 static u32 tegra_dsi_get_hs_clk_rate(struct tegra_dc_dsi_data *dsi)
314 {
315         u32 dsi_clock_rate_khz;
316
317         switch (dsi->info.video_burst_mode) {
318         case TEGRA_DSI_VIDEO_BURST_MODE_LOW_SPEED:
319         case TEGRA_DSI_VIDEO_BURST_MODE_MEDIUM_SPEED:
320         case TEGRA_DSI_VIDEO_BURST_MODE_FAST_SPEED:
321         case TEGRA_DSI_VIDEO_BURST_MODE_FASTEST_SPEED:
322                 /* Calculate DSI HS clock rate for DSI burst mode */
323                 dsi_clock_rate_khz = dsi->default_pixel_clk_khz *
324                                                         dsi->shift_clk_div;
325                 break;
326         case TEGRA_DSI_VIDEO_NONE_BURST_MODE:
327         case TEGRA_DSI_VIDEO_NONE_BURST_MODE_WITH_SYNC_END:
328         case TEGRA_DSI_VIDEO_BURST_MODE_LOWEST_SPEED:
329         default:
330                 /* Clock rate is default DSI clock rate for non-burst mode */
331                 dsi_clock_rate_khz = dsi->default_hs_clk_khz;
332                 break;
333         }
334
335         return dsi_clock_rate_khz;
336 }
337
338 static u32 tegra_dsi_get_lp_clk_rate(struct tegra_dc_dsi_data *dsi)
339 {
340         u32 dsi_clock_rate_khz;
341
342         if (dsi->info.enable_hs_clock_on_lp_cmd_mode)
343                 if (dsi->info.hs_clk_in_lp_cmd_mode_freq_khz)
344                         dsi_clock_rate_khz =
345                                 dsi->info.hs_clk_in_lp_cmd_mode_freq_khz;
346                 else
347                         dsi_clock_rate_khz = tegra_dsi_get_hs_clk_rate(dsi);
348         else
349                 dsi_clock_rate_khz = dsi->info.lp_cmd_mode_freq_khz;
350
351         return dsi_clock_rate_khz;
352 }
353
354 static u32 tegra_dsi_get_shift_clk_div(struct tegra_dc_dsi_data *dsi)
355 {
356         u32 shift_clk_div;
357         u32 max_shift_clk_div;
358         u32 burst_width;
359         u32 burst_width_max;
360
361         /* Get the real value of default shift_clk_div. default_shift_clk_div
362          * holds the real value of shift_clk_div. */
363         shift_clk_div = dsi->default_shift_clk_div;
364
365         /* Calculate shift_clk_div which can matche the video_burst_mode.*/
366         if (dsi->info.video_burst_mode >=
367                         TEGRA_DSI_VIDEO_BURST_MODE_LOWEST_SPEED) {
368                 /* The max_shift_clk_div is multiplied by 10 to save the
369                  * fraction */
370                 if (dsi->info.max_panel_freq_khz >= dsi->default_hs_clk_khz)
371                         max_shift_clk_div = dsi->info.max_panel_freq_khz
372                                 * shift_clk_div * 10 / dsi->default_hs_clk_khz;
373                 else
374                         max_shift_clk_div = shift_clk_div * 10;
375
376                 burst_width = dsi->info.video_burst_mode
377                                 - TEGRA_DSI_VIDEO_BURST_MODE_LOWEST_SPEED;
378                 burst_width_max = TEGRA_DSI_VIDEO_BURST_MODE_FASTEST_SPEED
379                                 - TEGRA_DSI_VIDEO_BURST_MODE_LOWEST_SPEED;
380
381                 shift_clk_div = (max_shift_clk_div - shift_clk_div * 10) *
382                         burst_width / (burst_width_max * 10) + shift_clk_div;
383         }
384
385         return shift_clk_div;
386 }
387
388 static void tegra_dsi_init_sw(struct tegra_dc *dc,
389                                                 struct tegra_dc_dsi_data *dsi)
390 {
391         u32 h_width_pixels;
392         u32 v_width_lines;
393         u32 pixel_clk_hz;
394         u32 byte_clk_hz;
395         u32 plld_clk_mhz;
396
397         switch (dsi->info.pixel_format) {
398                 case TEGRA_DSI_PIXEL_FORMAT_16BIT_P:
399                         /* 2 bytes per pixel */
400                         dsi->pixel_scaler_mul = 2;
401                         dsi->pixel_scaler_div = 1;
402                         break;
403                 case TEGRA_DSI_PIXEL_FORMAT_18BIT_P:
404                         /* 2.25 bytes per pixel */
405                         dsi->pixel_scaler_mul = 9;
406                         dsi->pixel_scaler_div = 4;
407                         break;
408                 case TEGRA_DSI_PIXEL_FORMAT_18BIT_NP:
409                 case TEGRA_DSI_PIXEL_FORMAT_24BIT_P:
410                         /* 3 bytes per pixel */
411                         dsi->pixel_scaler_mul = 3;
412                         dsi->pixel_scaler_div = 1;
413                         break;
414                 default:
415                         break;
416         }
417
418         dsi->controller_index = dc->ndev->id;
419         dsi->ulpm = false;
420         dsi->enabled = false;
421         dsi->clk_ref = false;
422
423         dsi->dsi_control_val =
424                         DSI_CONTROL_VIRTUAL_CHANNEL(dsi->info.virtual_channel) |
425                         DSI_CONTROL_NUM_DATA_LANES(dsi->info.n_data_lanes - 1) |
426                         DSI_CONTROL_VID_SOURCE(dsi->controller_index) |
427                         DSI_CONTROL_DATA_FORMAT(dsi->info.pixel_format);
428
429         /* Below we are going to calculate dsi and dc clock rate.
430          * Calcuate the horizontal and vertical width. */
431         h_width_pixels = dc->mode.h_back_porch + dc->mode.h_front_porch +
432                         dc->mode.h_sync_width + dc->mode.h_active;
433         v_width_lines = dc->mode.v_back_porch + dc->mode.v_front_porch +
434                         dc->mode.v_sync_width + dc->mode.v_active;
435
436         /* Calculate minimum required pixel rate. */
437         pixel_clk_hz = h_width_pixels * v_width_lines * dsi->info.refresh_rate;
438
439         dc->pixel_clk = pixel_clk_hz;
440
441         /* Calculate minimum byte rate on DSI interface. */
442         byte_clk_hz = (pixel_clk_hz * dsi->pixel_scaler_mul) /
443                         (dsi->pixel_scaler_div * dsi->info.n_data_lanes);
444
445         /* Round up to multiple of mega hz. */
446         plld_clk_mhz = DIV_ROUND_UP((byte_clk_hz * NUMOF_BIT_PER_BYTE),
447                                                                 1000000);
448
449         /* Calculate default real shift_clk_div. */
450         dsi->default_shift_clk_div = (NUMOF_BIT_PER_BYTE / 2) *
451                 dsi->pixel_scaler_mul / (dsi->pixel_scaler_div *
452                 dsi->info.n_data_lanes);
453         /* Calculate default DSI hs clock. DSI interface is double data rate.
454          * Data is transferred on both rising and falling edge of clk, div by 2
455          * to get the actual clock rate.
456          * */
457         dsi->default_hs_clk_khz = plld_clk_mhz * 1000 / 2;
458         dsi->default_pixel_clk_khz = plld_clk_mhz * 1000 / 2
459                                                 / dsi->default_shift_clk_div;
460
461         /* Get the actual shift_clk_div and clock rates. */
462         dsi->shift_clk_div = tegra_dsi_get_shift_clk_div(dsi);
463         dsi->target_lp_clk_khz = tegra_dsi_get_lp_clk_rate(dsi);
464         dsi->target_hs_clk_khz = tegra_dsi_get_hs_clk_rate(dsi);
465
466         dev_info(&dc->ndev->dev, "DSI: HS clock rate is %d\n",
467                                                         dsi->target_hs_clk_khz);
468
469         dsi->controller_index = dc->ndev->id;
470
471 #if DSI_USE_SYNC_POINTS
472         dsi->syncpt_id = NVSYNCPT_DSI;
473 #endif
474
475         /*
476          * Force video clock to be continuous mode if
477          * enable_hs_clock_on_lp_cmd_mode is set
478          */
479         if (dsi->info.enable_hs_clock_on_lp_cmd_mode) {
480                 if (dsi->info.video_clock_mode != TEGRA_DSI_VIDEO_CLOCK_CONTINUOUS)
481                         printk("Force to clock continuous mode\n");
482
483                 dsi->info.video_clock_mode = TEGRA_DSI_VIDEO_CLOCK_CONTINUOUS;
484         }
485
486 }
487
488 static void tegra_dsi_get_phy_timing(struct tegra_dc_dsi_data *dsi,
489                                 struct dsi_phy_timing_inclk *phy_timing_clk,
490                                 u32 clk_ns)
491 {
492
493         phy_timing_clk->t_hsdexit = dsi->info.phy_timing.t_hsdexit_ns ?
494                         (dsi->info.phy_timing.t_hsdexit_ns / clk_ns) :
495                         (T_HSEXIT_DEFAULT(clk_ns));
496
497         phy_timing_clk->t_hstrail = dsi->info.phy_timing.t_hstrail_ns ?
498                         (dsi->info.phy_timing.t_hstrail_ns / clk_ns) :
499                         (T_HSTRAIL_DEFAULT(clk_ns));
500
501         phy_timing_clk->t_datzero = dsi->info.phy_timing.t_datzero_ns ?
502                         (dsi->info.phy_timing.t_datzero_ns / clk_ns) :
503                         (T_DATZERO_DEFAULT(clk_ns));
504
505         phy_timing_clk->t_hsprepr = dsi->info.phy_timing.t_hsprepr_ns ?
506                         (dsi->info.phy_timing.t_hsprepr_ns / clk_ns) :
507                         (T_HSPREPR_DEFAULT(clk_ns));
508
509         phy_timing_clk->t_clktrail = dsi->info.phy_timing.t_clktrail_ns ?
510                                 (dsi->info.phy_timing.t_clktrail_ns / clk_ns) :
511                                 (T_CLKTRAIL_DEFAULT(clk_ns));
512
513         phy_timing_clk->t_clkpost = dsi->info.phy_timing.t_clkpost_ns ?
514                                 (dsi->info.phy_timing.t_clkpost_ns / clk_ns) :
515                                 (T_CLKPOST_DEFAULT(clk_ns));
516
517         phy_timing_clk->t_clkzero = dsi->info.phy_timing.t_clkzero_ns ?
518                                 (dsi->info.phy_timing.t_clkzero_ns / clk_ns) :
519                                 (T_CLKZERO_DEFAULT(clk_ns));
520
521         phy_timing_clk->t_tlpx = dsi->info.phy_timing.t_tlpx_ns ?
522                                 (dsi->info.phy_timing.t_tlpx_ns / clk_ns) :
523                                 (T_TLPX_DEFAULT(clk_ns));
524
525         phy_timing_clk->t_clkpre = T_CLKPRE_DEFAULT(clk_ns);
526         phy_timing_clk->t_clkprepare = T_CLKPREPARE_DEFAULT(clk_ns);
527         phy_timing_clk->t_wakeup = T_WAKEUP_DEFAULT(clk_ns);
528
529         phy_timing_clk->t_taget = 5 * phy_timing_clk->t_tlpx;
530         phy_timing_clk->t_tasure = 2 * phy_timing_clk->t_tlpx;
531         phy_timing_clk->t_tago = 4 * phy_timing_clk->t_tlpx;
532 }
533
534 static void tegra_dsi_set_phy_timing(struct tegra_dc_dsi_data *dsi)
535 {
536         u32 val;
537         struct dsi_phy_timing_inclk     phy_timing;
538
539         tegra_dsi_get_phy_timing(dsi, &phy_timing, dsi->current_bit_clk_ns);
540
541         val = DSI_PHY_TIMING_0_THSDEXIT(phy_timing.t_hsdexit) |
542                         DSI_PHY_TIMING_0_THSTRAIL(phy_timing.t_hstrail) |
543                         DSI_PHY_TIMING_0_TDATZERO(phy_timing.t_datzero) |
544                         DSI_PHY_TIMING_0_THSPREPR(phy_timing.t_hsprepr);
545         tegra_dsi_writel(dsi, val, DSI_PHY_TIMING_0);
546
547         val = DSI_PHY_TIMING_1_TCLKTRAIL(phy_timing.t_clktrail) |
548                         DSI_PHY_TIMING_1_TCLKPOST(phy_timing.t_clkpost) |
549                         DSI_PHY_TIMING_1_TCLKZERO(phy_timing.t_clkzero) |
550                         DSI_PHY_TIMING_1_TTLPX(phy_timing.t_tlpx);
551         tegra_dsi_writel(dsi, val, DSI_PHY_TIMING_1);
552
553         val = DSI_PHY_TIMING_2_TCLKPREPARE(phy_timing.t_clkprepare) |
554                 DSI_PHY_TIMING_2_TCLKPRE(phy_timing.t_clkpre) |
555                         DSI_PHY_TIMING_2_TWAKEUP(phy_timing.t_wakeup);
556         tegra_dsi_writel(dsi, val, DSI_PHY_TIMING_2);
557
558         val = DSI_BTA_TIMING_TTAGET(phy_timing.t_taget) |
559                         DSI_BTA_TIMING_TTASURE(phy_timing.t_tasure) |
560                         DSI_BTA_TIMING_TTAGO(phy_timing.t_tago);
561         tegra_dsi_writel(dsi, val, DSI_BTA_TIMING);
562 }
563
564 static u32 tegra_dsi_sol_delay_burst(struct tegra_dc *dc,
565                                                 struct tegra_dc_dsi_data *dsi)
566 {
567         u32 dsi_to_pixel_clk_ratio;
568         u32 temp;
569         u32 temp1;
570         u32 mipi_clk_adj_kHz;
571         u32 sol_delay;
572         struct tegra_dc_mode *dc_modes = &dc->mode;
573
574         /* Get Fdsi/Fpixel ration (note: Fdsi si in bit format) */
575         dsi_to_pixel_clk_ratio = (dsi->current_dsi_clk_khz * 2 +
576                 dsi->default_pixel_clk_khz - 1) / dsi->default_pixel_clk_khz;
577
578         /* Convert Fdsi to byte format */
579         dsi_to_pixel_clk_ratio *= 1000/8;
580
581         /* Multiplying by 1000 so that we don't loose the fraction part */
582         temp = dc_modes->h_active * 1000;
583         temp1 = dc_modes->h_active + dc_modes->h_back_porch +
584                         dc_modes->h_sync_width;
585
586         sol_delay = temp1 * dsi_to_pixel_clk_ratio -
587                         temp * dsi->pixel_scaler_mul /
588                         (dsi->pixel_scaler_div * dsi->info.n_data_lanes);
589
590         /* Do rounding on sol delay */
591         sol_delay = (sol_delay + 1000 - 1)/1000;
592
593         /* TODO:
594          * 1. find out the correct sol fifo depth to use
595          * 2. verify with hw about the clamping function
596          */
597         if (sol_delay > (480 * 4)) {
598                 sol_delay = (480 * 4);
599                 mipi_clk_adj_kHz = sol_delay +
600                         (dc_modes->h_active * dsi->pixel_scaler_mul) /
601                         (dsi->info.n_data_lanes * dsi->pixel_scaler_div);
602
603                 mipi_clk_adj_kHz *= (dsi->default_pixel_clk_khz / temp1);
604
605                 mipi_clk_adj_kHz *= 4;
606         }
607
608         dsi->target_hs_clk_khz = mipi_clk_adj_kHz;
609
610         return sol_delay;
611 }
612
613 static void tegra_dsi_set_sol_delay(struct tegra_dc *dc,
614                                                 struct tegra_dc_dsi_data *dsi)
615 {
616         u32 sol_delay;
617
618         if (dsi->info.video_burst_mode == TEGRA_DSI_VIDEO_NONE_BURST_MODE ||
619                 dsi->info.video_burst_mode ==
620                                 TEGRA_DSI_VIDEO_NONE_BURST_MODE_WITH_SYNC_END) {
621                 sol_delay = NUMOF_BIT_PER_BYTE * dsi->pixel_scaler_mul /
622                         (dsi->pixel_scaler_div * dsi->info.n_data_lanes);
623                 dsi->status.clk_burst = DSI_CLK_BURST_NONE_BURST;
624         } else {
625                 sol_delay = tegra_dsi_sol_delay_burst(dc, dsi);
626                 dsi->status.clk_burst = DSI_CLK_BURST_BURST_MODE;
627         }
628
629         tegra_dsi_writel(dsi, DSI_SOL_DELAY_SOL_DELAY(sol_delay),
630                                                                 DSI_SOL_DELAY);
631 }
632
633 static void tegra_dsi_set_timeout(struct tegra_dc_dsi_data *dsi)
634 {
635         u32 val;
636         u32 bytes_per_frame;
637         u32 timeout = 0;
638
639         /* TODO: verify the following eq */
640         bytes_per_frame = dsi->current_dsi_clk_khz * 1000 * 2 /
641                                                 (dsi->info.refresh_rate * 8);
642         timeout = bytes_per_frame / DSI_CYCLE_COUNTER_VALUE;
643         timeout = (timeout + DSI_HTX_TO_MARGIN) & 0xffff;
644
645         val = DSI_TIMEOUT_0_LRXH_TO(DSI_LRXH_TO_VALUE) |
646                         DSI_TIMEOUT_0_HTX_TO(timeout);
647         tegra_dsi_writel(dsi, val, DSI_TIMEOUT_0);
648
649         if (dsi->info.panel_reset_timeout_msec)
650                 timeout = (dsi->info.panel_reset_timeout_msec * 1000*1000)
651                                         / dsi->current_bit_clk_ns;
652         else
653                 timeout = DSI_PR_TO_VALUE;
654
655         val = DSI_TIMEOUT_1_PR_TO(timeout) |
656                 DSI_TIMEOUT_1_TA_TO(DSI_TA_TO_VALUE);
657         tegra_dsi_writel(dsi, val, DSI_TIMEOUT_1);
658
659         val = DSI_TO_TALLY_P_RESET_STATUS(IN_RESET) |
660                 DSI_TO_TALLY_TA_TALLY(DSI_TA_TALLY_VALUE)|
661                 DSI_TO_TALLY_LRXH_TALLY(DSI_LRXH_TALLY_VALUE)|
662                 DSI_TO_TALLY_HTX_TALLY(DSI_HTX_TALLY_VALUE);
663         tegra_dsi_writel(dsi, val, DSI_TO_TALLY);
664 }
665
666 static void tegra_dsi_setup_video_mode_pkt_length(struct tegra_dc *dc,
667                                                 struct tegra_dc_dsi_data *dsi)
668 {
669         u32 val;
670         u32 hact_pkt_len;
671         u32 hsa_pkt_len;
672         u32 hbp_pkt_len;
673         u32 hfp_pkt_len;
674
675         hact_pkt_len = dc->mode.h_active * dsi->pixel_scaler_mul /
676                                                         dsi->pixel_scaler_div;
677         hsa_pkt_len = dc->mode.h_sync_width * dsi->pixel_scaler_mul /
678                                                         dsi->pixel_scaler_div;
679         hbp_pkt_len = dc->mode.h_back_porch * dsi->pixel_scaler_mul /
680                                                         dsi->pixel_scaler_div;
681         hfp_pkt_len = dc->mode.h_front_porch * dsi->pixel_scaler_mul /
682                                                         dsi->pixel_scaler_div;
683
684         if (dsi->info.video_burst_mode !=
685                                 TEGRA_DSI_VIDEO_NONE_BURST_MODE_WITH_SYNC_END)
686                 hbp_pkt_len += hsa_pkt_len;
687
688         hsa_pkt_len -= DSI_HSYNC_BLNK_PKT_OVERHEAD;
689         hbp_pkt_len -= DSI_HBACK_PORCH_PKT_OVERHEAD;
690         hfp_pkt_len -= DSI_HFRONT_PORCH_PKT_OVERHEAD;
691
692         val = DSI_PKT_LEN_0_1_LENGTH_0(0) | DSI_PKT_LEN_0_1_LENGTH_1(hsa_pkt_len);
693         tegra_dsi_writel(dsi, val, DSI_PKT_LEN_0_1);
694
695         val = DSI_PKT_LEN_2_3_LENGTH_2(hbp_pkt_len) |
696                         DSI_PKT_LEN_2_3_LENGTH_3(hact_pkt_len);
697         tegra_dsi_writel(dsi, val, DSI_PKT_LEN_2_3);
698
699         val = DSI_PKT_LEN_4_5_LENGTH_4(hfp_pkt_len) | DSI_PKT_LEN_4_5_LENGTH_5(0);
700         tegra_dsi_writel(dsi, val, DSI_PKT_LEN_4_5);
701
702         val = DSI_PKT_LEN_6_7_LENGTH_6(0) | DSI_PKT_LEN_6_7_LENGTH_7(0);
703         tegra_dsi_writel(dsi, val, DSI_PKT_LEN_6_7);
704 }
705
706 static void tegra_dsi_setup_cmd_mode_pkt_length(struct tegra_dc *dc,
707                                                 struct tegra_dc_dsi_data *dsi)
708 {
709         unsigned long   val;
710         unsigned long   act_bytes;
711
712         act_bytes = dc->mode.h_active * dsi->pixel_scaler_mul /
713                         dsi->pixel_scaler_div + 1;
714
715         val = DSI_PKT_LEN_0_1_LENGTH_0(0) | DSI_PKT_LEN_0_1_LENGTH_1(0);
716         tegra_dsi_writel(dsi, val, DSI_PKT_LEN_0_1);
717
718         val = DSI_PKT_LEN_2_3_LENGTH_2(0) | DSI_PKT_LEN_2_3_LENGTH_3(act_bytes);
719         tegra_dsi_writel(dsi, val, DSI_PKT_LEN_2_3);
720
721         val = DSI_PKT_LEN_4_5_LENGTH_4(0) | DSI_PKT_LEN_4_5_LENGTH_5(act_bytes);
722         tegra_dsi_writel(dsi, val, DSI_PKT_LEN_4_5);
723
724         val = DSI_PKT_LEN_6_7_LENGTH_6(0) | DSI_PKT_LEN_6_7_LENGTH_7(0x0f0f);
725         tegra_dsi_writel(dsi, val, DSI_PKT_LEN_6_7);
726 }
727
728 static void tegra_dsi_set_pkt_length(struct tegra_dc *dc,
729                                                 struct tegra_dc_dsi_data *dsi)
730 {
731         if (dsi->driven_mode == TEGRA_DSI_DRIVEN_BY_HOST)
732                 return;
733
734         if (dsi->info.video_data_type == TEGRA_DSI_VIDEO_TYPE_VIDEO_MODE)
735                 tegra_dsi_setup_video_mode_pkt_length(dc, dsi);
736         else
737                 tegra_dsi_setup_cmd_mode_pkt_length(dc, dsi);
738 }
739
740 static void tegra_dsi_set_pkt_seq(struct tegra_dc *dc,
741                                                 struct tegra_dc_dsi_data *dsi)
742 {
743         const u32 *pkt_seq;
744         u32 rgb_info;
745         u32 pkt_seq_3_5_rgb_lo;
746         u32 pkt_seq_3_5_rgb_hi;
747         u32     val;
748         u32 reg;
749         u8  i;
750
751         if (dsi->driven_mode == TEGRA_DSI_DRIVEN_BY_HOST)
752                 return;
753
754         switch(dsi->info.pixel_format) {
755         case TEGRA_DSI_PIXEL_FORMAT_16BIT_P:
756                 rgb_info = CMD_RGB_16BPP;
757                 break;
758         case TEGRA_DSI_PIXEL_FORMAT_18BIT_P:
759                 rgb_info = CMD_RGB_18BPP;
760                 break;
761         case TEGRA_DSI_PIXEL_FORMAT_18BIT_NP:
762                 rgb_info = CMD_RGB_18BPPNP;
763                 break;
764         case TEGRA_DSI_PIXEL_FORMAT_24BIT_P:
765         default:
766                 rgb_info = CMD_RGB_24BPP;
767                 break;
768         }
769
770         pkt_seq_3_5_rgb_lo = 0;
771         pkt_seq_3_5_rgb_hi = 0;
772         if (dsi->info.video_data_type == TEGRA_DSI_VIDEO_TYPE_COMMAND_MODE)
773                 pkt_seq = dsi_pkt_seq_cmd_mode;
774         else {
775                 switch (dsi->info.video_burst_mode) {
776                 case TEGRA_DSI_VIDEO_BURST_MODE_LOWEST_SPEED:
777                 case TEGRA_DSI_VIDEO_BURST_MODE_LOW_SPEED:
778                 case TEGRA_DSI_VIDEO_BURST_MODE_MEDIUM_SPEED:
779                 case TEGRA_DSI_VIDEO_BURST_MODE_FAST_SPEED:
780                 case TEGRA_DSI_VIDEO_BURST_MODE_FASTEST_SPEED:
781                         pkt_seq_3_5_rgb_lo = DSI_PKT_SEQ_3_LO_PKT_32_ID(rgb_info);
782                         if(!dsi->info.no_pkt_seq_eot)
783                                 pkt_seq = dsi_pkt_seq_video_burst;
784                         else
785                                 pkt_seq = dsi_pkt_seq_video_burst_no_eot;
786                         break;
787                 case TEGRA_DSI_VIDEO_NONE_BURST_MODE_WITH_SYNC_END:
788                         pkt_seq_3_5_rgb_hi = DSI_PKT_SEQ_3_HI_PKT_34_ID(rgb_info);
789                         pkt_seq = dsi_pkt_seq_video_non_burst_syne;
790                         break;
791                 case TEGRA_DSI_VIDEO_NONE_BURST_MODE:
792                 default:
793                         pkt_seq_3_5_rgb_lo = DSI_PKT_SEQ_3_LO_PKT_32_ID(rgb_info);
794                         pkt_seq = dsi_pkt_seq_video_non_burst;
795                         break;
796                 }
797         }
798
799         for (i = 0; i < NUMOF_PKT_SEQ; i++) {
800                 val = pkt_seq[i];
801                 reg = dsi_pkt_seq_reg[i];
802                 if ((reg == DSI_PKT_SEQ_3_LO) || (reg == DSI_PKT_SEQ_5_LO))
803                         val |= pkt_seq_3_5_rgb_lo;
804                 if ((reg == DSI_PKT_SEQ_3_HI) || (reg == DSI_PKT_SEQ_5_HI))
805                         val |= pkt_seq_3_5_rgb_hi;
806                 tegra_dsi_writel(dsi, val, reg);
807         }
808 }
809
810 static void tegra_dsi_stop_dc_stream(struct tegra_dc *dc,
811                                                 struct tegra_dc_dsi_data *dsi)
812 {
813         tegra_dc_writel(dc, 0, DC_DISP_DISP_WIN_OPTIONS);
814         tegra_dc_writel(dc, GENERAL_ACT_REQ << 8, DC_CMD_STATE_CONTROL);
815         tegra_dc_writel(dc, GENERAL_ACT_REQ, DC_CMD_STATE_CONTROL);
816
817         dsi->status.dc_stream = DSI_DC_STREAM_DISABLE;
818 }
819
820 void tegra_dsi_stop_dc_stream_at_frame_end(struct tegra_dc *dc, struct tegra_dc_dsi_data *dsi)
821 {
822         int val;
823         long timeout;
824
825         /* stop dc */
826         tegra_dsi_stop_dc_stream(dc, dsi);
827
828         /* enable vblank interrupt */
829         val = tegra_dc_readl(dc, DC_CMD_INT_ENABLE);
830         val |= V_BLANK_INT;
831         tegra_dc_writel(dc, val, DC_CMD_INT_ENABLE);
832
833         val = tegra_dc_readl(dc, DC_CMD_INT_MASK);
834         val |= V_BLANK_INT;
835         tegra_dc_writel(dc, val, DC_CMD_INT_MASK);
836
837         /* wait for vblank completion */
838         timeout = wait_for_completion_interruptible_timeout(
839                 &dc->vblank_complete, DSI_STOP_DC_DURATION_MSEC);
840
841         /* disable vblank interrupt */
842         val = tegra_dc_readl(dc, DC_CMD_INT_ENABLE);
843         val &= ~V_BLANK_INT;
844         tegra_dc_writel(dc, val, DC_CMD_INT_ENABLE);
845
846         if(timeout == 0)
847                 printk("Warning: dc dosen't stop at the end of the frame.\n");
848 }
849
850 static void tegra_dsi_start_dc_stream(struct tegra_dc *dc,
851                                                 struct tegra_dc_dsi_data *dsi)
852 {
853         u32 val;
854
855         tegra_dc_writel(dc, DSI_ENABLE, DC_DISP_DISP_WIN_OPTIONS);
856
857         /* TODO: clean up */
858         val = PIN_INPUT_LSPI_INPUT_EN;
859         tegra_dc_writel(dc, val, DC_COM_PIN_INPUT_ENABLE3);
860
861         val = PIN_OUTPUT_LSPI_OUTPUT_DIS;
862         tegra_dc_writel(dc, val, DC_COM_PIN_OUTPUT_ENABLE3);
863
864         tegra_dc_writel(dc, PW0_ENABLE | PW1_ENABLE | PW2_ENABLE | PW3_ENABLE |
865                         PW4_ENABLE | PM0_ENABLE | PM1_ENABLE,
866                         DC_CMD_DISPLAY_POWER_CONTROL);
867
868         val = MSF_POLARITY_HIGH | MSF_ENABLE | MSF_LSPI;
869         tegra_dc_writel(dc, val, DC_CMD_DISPLAY_COMMAND_OPTION0);
870
871
872         /* TODO: using continuous video mode for now */
873         /* if (dsi->info.panel_has_frame_buffer) {*/
874         if (0) {
875                 tegra_dc_writel(dc, DISP_CTRL_MODE_NC_DISPLAY, DC_CMD_DISPLAY_COMMAND);
876                 tegra_dc_writel(dc, GENERAL_UPDATE, DC_CMD_STATE_CONTROL);
877                 val = GENERAL_ACT_REQ | NC_HOST_TRIG;
878                 tegra_dc_writel(dc, val, DC_CMD_STATE_CONTROL);
879         } else {
880                 tegra_dc_writel(dc, DISP_CTRL_MODE_C_DISPLAY, DC_CMD_DISPLAY_COMMAND);
881                 tegra_dc_writel(dc, GENERAL_ACT_REQ << 8, DC_CMD_STATE_CONTROL);
882                 tegra_dc_writel(dc, GENERAL_ACT_REQ, DC_CMD_STATE_CONTROL);
883         }
884
885         dsi->status.dc_stream = DSI_DC_STREAM_ENABLE;
886 }
887
888 static void tegra_dsi_set_dc_clk(struct tegra_dc *dc,
889                                                 struct tegra_dc_dsi_data *dsi)
890 {
891         u32 shift_clk_div_register;
892         u32 val;
893
894         /* Get the corresponding register value of shift_clk_div. */
895         shift_clk_div_register = dsi->shift_clk_div * 2 - 2;
896
897 #ifdef CONFIG_TEGRA_FPGA_PLATFORM
898         shift_clk_div_register = 1;
899 #endif
900
901         /* TODO: find out if PCD3 option is required */
902         val = PIXEL_CLK_DIVIDER_PCD1 |
903                                 SHIFT_CLK_DIVIDER(shift_clk_div_register);
904         tegra_dc_writel(dc, val, DC_DISP_DISP_CLOCK_CONTROL);
905 }
906
907 static void tegra_dsi_set_dsi_clk(struct tegra_dc *dc,
908                                         struct tegra_dc_dsi_data *dsi, u32 clk)
909 {
910         u32 rm;
911
912         rm = clk % 1000;
913         if (rm != 0)
914                 clk -= rm;
915
916         clk *= 2;       /* Value for PLLD routine is required to be twice as */
917                         /* the desired clock rate */
918
919         dc->mode.pclk = clk*1000;
920         tegra_dc_setup_clk(dc, dsi->dsi_clk);
921         if (dsi->clk_ref == true)
922                 clk_disable(dsi->dsi_clk);
923         else
924                 dsi->clk_ref = true;
925         clk_enable(dsi->dsi_clk);
926         tegra_periph_reset_deassert(dsi->dsi_clk);
927
928         dsi->current_dsi_clk_khz = clk_get_rate(dsi->dsi_clk) / 1000;
929
930         dsi->current_bit_clk_ns =  1000*1000 / (dsi->current_dsi_clk_khz * 2);
931 }
932
933 static void tegra_dsi_hs_clk_out_enable(struct tegra_dc_dsi_data *dsi)
934 {
935         u32 val;
936
937         val = tegra_dsi_readl(dsi, DSI_CONTROL);
938         val &= ~DSI_CONTROL_HS_CLK_CTRL(1);
939
940         if (dsi->info.video_clock_mode == TEGRA_DSI_VIDEO_CLOCK_CONTINUOUS) {
941                 val |= DSI_CONTROL_HS_CLK_CTRL(CONTINUOUS);
942                 dsi->status.clk_mode = DSI_PHYCLK_CONTINUOUS;
943         } else {
944                 val |= DSI_CONTROL_HS_CLK_CTRL(TX_ONLY);
945                 dsi->status.clk_mode = DSI_PHYCLK_TX_ONLY;
946         }
947         tegra_dsi_writel(dsi, val, DSI_CONTROL);
948
949         val = tegra_dsi_readl(dsi, DSI_HOST_DSI_CONTROL);
950         val &= ~DSI_HOST_DSI_CONTROL_HIGH_SPEED_TRANS(1);
951         val |= DSI_HOST_DSI_CONTROL_HIGH_SPEED_TRANS(TEGRA_DSI_HIGH);
952         tegra_dsi_writel(dsi, val, DSI_HOST_DSI_CONTROL);
953
954         dsi->status.clk_out = DSI_PHYCLK_OUT_EN;
955 }
956
957 static void tegra_dsi_hs_clk_out_enable_in_lp(struct tegra_dc_dsi_data *dsi)
958 {
959         u32 val;
960         tegra_dsi_hs_clk_out_enable(dsi);
961
962         val = tegra_dsi_readl(dsi, DSI_HOST_DSI_CONTROL);
963         val &= ~DSI_HOST_DSI_CONTROL_HIGH_SPEED_TRANS(1);
964         val |= DSI_HOST_DSI_CONTROL_HIGH_SPEED_TRANS(TEGRA_DSI_LOW);
965         tegra_dsi_writel(dsi, val, DSI_HOST_DSI_CONTROL);
966 }
967
968 static void tegra_dsi_hs_clk_out_disable(struct tegra_dc *dc,
969                                                 struct tegra_dc_dsi_data *dsi)
970 {
971         u32 val;
972
973         if (dsi->status.dc_stream == DSI_DC_STREAM_ENABLE)
974                 tegra_dsi_stop_dc_stream(dc, dsi);
975
976         val = tegra_dsi_readl(dsi, DSI_CONTROL);
977         val &= ~DSI_CONTROL_HS_CLK_CTRL(1);
978         val |= DSI_CONTROL_HS_CLK_CTRL(TX_ONLY);
979         tegra_dsi_writel(dsi, val, DSI_CONTROL);
980
981         /* TODO: issue a cmd */
982
983         val = tegra_dsi_readl(dsi, DSI_HOST_DSI_CONTROL);
984         val &= ~DSI_HOST_DSI_CONTROL_HIGH_SPEED_TRANS(1);
985         val |= DSI_HOST_DSI_CONTROL_HIGH_SPEED_TRANS(TEGRA_DSI_LOW);
986         tegra_dsi_writel(dsi, val, DSI_HOST_DSI_CONTROL);
987
988         dsi->status.clk_mode = DSI_PHYCLK_NOT_INIT;
989         dsi->status.clk_out = DSI_PHYCLK_OUT_DIS;
990 }
991
992 static void tegra_dsi_set_control_reg_lp(struct tegra_dc_dsi_data *dsi)
993 {
994         u32 dsi_control;
995         u32 host_dsi_control;
996         u32 max_threshold;
997
998         dsi_control = dsi->dsi_control_val | DSI_CTRL_HOST_DRIVEN;
999         host_dsi_control = HOST_DSI_CTRL_COMMON |
1000                         HOST_DSI_CTRL_HOST_DRIVEN |
1001                         DSI_HOST_DSI_CONTROL_HIGH_SPEED_TRANS(TEGRA_DSI_LOW);
1002         max_threshold = DSI_MAX_THRESHOLD_MAX_THRESHOLD(DSI_HOST_FIFO_DEPTH);
1003
1004         tegra_dsi_writel(dsi, max_threshold, DSI_MAX_THRESHOLD);
1005         tegra_dsi_writel(dsi, dsi_control, DSI_CONTROL);
1006         tegra_dsi_writel(dsi, host_dsi_control, DSI_HOST_DSI_CONTROL);
1007
1008         dsi->status.driven = DSI_DRIVEN_MODE_HOST;
1009         dsi->status.clk_burst = DSI_CLK_BURST_NOT_INIT;
1010         dsi->status.vtype = DSI_VIDEO_TYPE_NOT_INIT;
1011 }
1012
1013 static void tegra_dsi_set_control_reg_hs(struct tegra_dc_dsi_data *dsi)
1014 {
1015         u32 dsi_control;
1016         u32 host_dsi_control;
1017         u32 max_threshold;
1018         u32 dcs_cmd;
1019
1020         dsi_control = dsi->dsi_control_val;
1021         host_dsi_control = HOST_DSI_CTRL_COMMON;
1022         max_threshold = 0;
1023         dcs_cmd = 0;
1024
1025         if (dsi->driven_mode == TEGRA_DSI_DRIVEN_BY_HOST) {
1026                 dsi_control |= DSI_CTRL_HOST_DRIVEN;
1027                 host_dsi_control |= HOST_DSI_CTRL_HOST_DRIVEN;
1028                 max_threshold = DSI_MAX_THRESHOLD_MAX_THRESHOLD(DSI_HOST_FIFO_DEPTH);
1029                 dsi->status.driven = DSI_DRIVEN_MODE_HOST;
1030         } else {
1031                 dsi_control |= DSI_CTRL_DC_DRIVEN;
1032                 host_dsi_control |= HOST_DSI_CTRL_DC_DRIVEN;
1033                 max_threshold = DSI_MAX_THRESHOLD_MAX_THRESHOLD(DSI_VIDEO_FIFO_DEPTH);
1034                 dsi->status.driven = DSI_DRIVEN_MODE_DC;
1035         }
1036
1037         if (dsi->info.video_data_type == TEGRA_DSI_VIDEO_TYPE_COMMAND_MODE) {
1038                 dsi_control |= DSI_CTRL_CMD_MODE;
1039                 host_dsi_control |= HOST_DSI_CTRL_CMD_MODE;
1040                 dcs_cmd = DSI_DCS_CMDS_LT5_DCS_CMD(DSI_WRITE_MEMORY_START)|
1041                                 DSI_DCS_CMDS_LT3_DCS_CMD(DSI_WRITE_MEMORY_CONTINUE);
1042                 dsi->status.vtype = DSI_VIDEO_TYPE_CMD_MODE;
1043
1044         } else {
1045                 dsi_control |= DSI_CTRL_VIDEO_MODE;
1046                 host_dsi_control |= HOST_DSI_CTRL_VIDEO_MODE;
1047                 dsi->status.vtype = DSI_VIDEO_TYPE_VIDEO_MODE;
1048         }
1049
1050         tegra_dsi_writel(dsi, max_threshold, DSI_MAX_THRESHOLD);
1051         tegra_dsi_writel(dsi, dcs_cmd, DSI_DCS_CMDS);
1052         tegra_dsi_writel(dsi, dsi_control, DSI_CONTROL);
1053         tegra_dsi_writel(dsi, host_dsi_control, DSI_HOST_DSI_CONTROL);
1054 }
1055
1056 static int tegra_dsi_init_hw(struct tegra_dc *dc,
1057                                                 struct tegra_dc_dsi_data *dsi)
1058 {
1059         u32 val;
1060         u32 i;
1061
1062         tegra_dsi_set_dsi_clk(dc, dsi, dsi->target_lp_clk_khz);
1063         if (dsi->info.dsi_instance) {
1064                 /* TODO:Set the misc register*/
1065         }
1066
1067         /* TODO: only need to change the timing for bta */
1068         tegra_dsi_set_phy_timing(dsi);
1069
1070         if (dsi->status.dc_stream == DSI_DC_STREAM_ENABLE)
1071                 tegra_dsi_stop_dc_stream(dc, dsi);
1072
1073         /* Initializing DSI registers */
1074         for (i = 0; i < ARRAY_SIZE(init_reg); i++) {
1075                 tegra_dsi_writel(dsi, 0, init_reg[i]);
1076         }
1077         tegra_dsi_writel(dsi, dsi->dsi_control_val, DSI_CONTROL);
1078
1079         /* Initialize DSI_PAD_CONTROL register. */
1080         val =   DSI_PAD_CONTROL_PAD_LPUPADJ(0x1) |
1081                 DSI_PAD_CONTROL_PAD_LPDNADJ(0x1) |
1082                 DSI_PAD_CONTROL_PAD_PREEMP_EN(0x1) |
1083                 DSI_PAD_CONTROL_PAD_SLEWDNADJ(0x6) |
1084                 DSI_PAD_CONTROL_PAD_SLEWUPADJ(0x6);
1085         if (!dsi->ulpm) {
1086                 val |=  DSI_PAD_CONTROL_PAD_PDIO(0) |
1087                         DSI_PAD_CONTROL_PAD_PDIO_CLK(0) |
1088                         DSI_PAD_CONTROL_PAD_PULLDN_ENAB(TEGRA_DSI_DISABLE);
1089         } else {
1090                 val |=  DSI_PAD_CONTROL_PAD_PDIO(0x3) |
1091                         DSI_PAD_CONTROL_PAD_PDIO_CLK(0x1) |
1092                         DSI_PAD_CONTROL_PAD_PULLDN_ENAB(TEGRA_DSI_ENABLE);
1093         }
1094         tegra_dsi_writel(dsi, val, DSI_PAD_CONTROL);
1095
1096         val = DSI_POWER_CONTROL_LEG_DSI_ENABLE(TEGRA_DSI_ENABLE);
1097         tegra_dsi_writel(dsi, val, DSI_POWER_CONTROL);
1098
1099         while (tegra_dsi_readl(dsi, DSI_POWER_CONTROL) != val) {
1100                 tegra_dsi_writel(dsi, val, DSI_POWER_CONTROL);
1101         }
1102
1103         dsi->status.init = DSI_MODULE_INIT;
1104         dsi->status.lphs = DSI_LPHS_NOT_INIT;
1105         dsi->status.vtype = DSI_VIDEO_TYPE_NOT_INIT;
1106         dsi->status.driven = DSI_DRIVEN_MODE_NOT_INIT;
1107         dsi->status.clk_out = DSI_PHYCLK_OUT_DIS;
1108         dsi->status.clk_mode = DSI_PHYCLK_NOT_INIT;
1109         dsi->status.clk_burst = DSI_CLK_BURST_NOT_INIT;
1110         dsi->status.dc_stream = DSI_DC_STREAM_DISABLE;
1111
1112         return 0;
1113 }
1114
1115 static int tegra_dsi_set_to_lp_mode(struct tegra_dc *dc,
1116                                                 struct tegra_dc_dsi_data *dsi)
1117 {
1118         int     err;
1119
1120         if (dsi->status.init != DSI_MODULE_INIT) {
1121                 err = -EPERM;
1122                 goto fail;
1123         }
1124
1125         if (dsi->status.lphs == DSI_LPHS_IN_LP_MODE)
1126                 goto success;
1127
1128         if (dsi->status.dc_stream == DSI_DC_STREAM_ENABLE)
1129                 tegra_dsi_stop_dc_stream_at_frame_end(dc, dsi);
1130
1131         /* disable/enable hs clock according to enable_hs_clock_on_lp_cmd_mode */
1132         if ((dsi->status.clk_out == DSI_PHYCLK_OUT_EN) &&
1133                 (!dsi->info.enable_hs_clock_on_lp_cmd_mode))
1134                 tegra_dsi_hs_clk_out_disable(dc, dsi);
1135
1136         if (dsi->current_dsi_clk_khz != dsi->target_lp_clk_khz){
1137                 tegra_dsi_set_dsi_clk(dc, dsi, dsi->target_lp_clk_khz);
1138                 tegra_dsi_set_timeout(dsi);
1139         }
1140
1141         tegra_dsi_set_control_reg_lp(dsi);
1142
1143         if ((dsi->status.clk_out == DSI_PHYCLK_OUT_DIS) &&
1144                 (dsi->info.enable_hs_clock_on_lp_cmd_mode))
1145                 tegra_dsi_hs_clk_out_enable_in_lp(dsi);
1146
1147 success:
1148         dsi->status.lphs = DSI_LPHS_IN_LP_MODE;
1149         err = 0;
1150 fail:
1151         return err;
1152 }
1153
1154 static int tegra_dsi_set_to_hs_mode(struct tegra_dc *dc,
1155                                                 struct tegra_dc_dsi_data *dsi)
1156 {
1157         int err;
1158
1159         if (dsi->status.init != DSI_MODULE_INIT) {
1160                 err = -EPERM;
1161                 goto fail;
1162         }
1163
1164         if (dsi->status.dc_stream == DSI_DC_STREAM_ENABLE)
1165                 tegra_dsi_stop_dc_stream_at_frame_end(dc, dsi);
1166
1167         if ((dsi->status.clk_out == DSI_PHYCLK_OUT_EN) &&
1168                 (!dsi->info.enable_hs_clock_on_lp_cmd_mode))
1169                 tegra_dsi_hs_clk_out_disable(dc, dsi);
1170
1171         if (dsi->current_dsi_clk_khz != dsi->target_hs_clk_khz) {
1172                 tegra_dsi_set_dsi_clk(dc, dsi, dsi->target_hs_clk_khz);
1173                 tegra_dsi_set_timeout(dsi);
1174         }
1175
1176         tegra_dsi_set_phy_timing(dsi);
1177
1178         if (dsi->driven_mode == TEGRA_DSI_DRIVEN_BY_DC){
1179                 tegra_dsi_set_pkt_seq(dc, dsi);
1180                 tegra_dsi_set_pkt_length(dc, dsi);
1181                 tegra_dsi_set_sol_delay(dc, dsi);
1182                 tegra_dsi_set_dc_clk(dc, dsi);
1183         }
1184
1185         tegra_dsi_set_control_reg_hs(dsi);
1186
1187         if (dsi->status.clk_out == DSI_PHYCLK_OUT_DIS)
1188                 tegra_dsi_hs_clk_out_enable(dsi);
1189
1190         dsi->status.lphs = DSI_LPHS_IN_HS_MODE;
1191         err = 0;
1192 fail:
1193         return err;
1194 }
1195
1196 static bool tegra_dsi_is_controller_idle(struct tegra_dc_dsi_data *dsi)
1197 {
1198         u32 timeout = 0;
1199         bool retVal;
1200
1201         retVal = false;
1202         while (timeout <= DSI_MAX_COMMAND_DELAY_USEC) {
1203                 if (!tegra_dsi_readl(dsi, DSI_TRIGGER)) {
1204                         retVal = true;
1205                         break;
1206                 }
1207                 udelay(DSI_COMMAND_DELAY_STEPS_USEC);
1208                 timeout += DSI_COMMAND_DELAY_STEPS_USEC;
1209         }
1210
1211         return retVal;
1212 }
1213
1214 static int tegra_dsi_host_trigger(struct tegra_dc_dsi_data *dsi)
1215 {
1216         int status = 0;
1217
1218         if (tegra_dsi_readl(dsi, DSI_TRIGGER)) {
1219                 status = -EBUSY;
1220                 goto fail;
1221         }
1222
1223         tegra_dsi_writel(dsi,
1224                 DSI_TRIGGER_HOST_TRIGGER(TEGRA_DSI_ENABLE), DSI_TRIGGER);
1225
1226 #if DSI_USE_SYNC_POINTS
1227         status = tegra_dsi_syncpt(dsi);
1228         if (status < 0) {
1229                 printk(KERN_ERR "DSI syncpt for host trigger failed\n");
1230                 goto fail;
1231         }
1232 #else
1233         if (!tegra_dsi_is_controller_idle(dsi))
1234                 status = -EIO;
1235 #endif
1236
1237 fail:
1238         return status;
1239 }
1240
1241 static int _tegra_dsi_write_data(struct tegra_dc_dsi_data *dsi,
1242                                         u8* pdata, u8 data_id, u16 data_len)
1243 {
1244         u8 virtual_channel;
1245         u8 *pval;
1246         u32 val;
1247         int err;
1248
1249         err = 0;
1250
1251         virtual_channel = dsi->info.virtual_channel << DSI_VIR_CHANNEL_BIT_POSITION;
1252
1253         /* always use hw for ecc */
1254         val = (virtual_channel | data_id) << 0 |
1255                         data_len << 8;
1256         tegra_dsi_writel(dsi, val, DSI_WR_DATA);
1257
1258         /* if pdata != NULL, pkt type is long pkt */
1259         if (pdata != NULL) {
1260                 while (data_len) {
1261                         if (data_len >= 4) {
1262                                 val = ((u32*) pdata)[0];
1263                                 data_len -= 4;
1264                                 pdata += 4;
1265                         } else {
1266                                 val = 0;
1267                                 pval = (u8*) &val;
1268                                 do
1269                                         *pval++ = *pdata++;
1270                                 while(--data_len);
1271                         }
1272                         tegra_dsi_writel(dsi, val, DSI_WR_DATA);
1273                 }
1274         }
1275
1276         err = tegra_dsi_host_trigger(dsi);
1277         if (err < 0)
1278                 printk(KERN_ERR "DSI host trigger failed\n");
1279
1280         return err;
1281 }
1282
1283 static int tegra_dsi_write_data(struct tegra_dc *dc,
1284                                         struct tegra_dc_dsi_data *dsi,
1285                                         u8* pdata, u8 data_id, u16 data_len)
1286 {
1287         bool switch_back_to_hs_mode;
1288         bool switch_back_to_dc_mode;
1289         int err;
1290
1291         err = 0;
1292         switch_back_to_hs_mode = false;
1293         switch_back_to_dc_mode = false;
1294
1295         if ((dsi->status.init != DSI_MODULE_INIT) ||
1296                 (dsi->status.lphs == DSI_LPHS_NOT_INIT)) {
1297                 err = -EPERM;
1298                 goto fail;
1299         }
1300
1301         if (!tegra_dsi_is_controller_idle(dsi)) {
1302                 err = -EBUSY;
1303                 goto fail;
1304         }
1305
1306         err = 0;
1307
1308         if (dsi->status.lphs == DSI_LPHS_IN_HS_MODE) {
1309                 if (dsi->info.hs_cmd_mode_supported) {
1310                         if (dsi->status.driven == DSI_DRIVEN_MODE_DC) {
1311                                 dsi->driven_mode = TEGRA_DSI_DRIVEN_BY_HOST;
1312                                 tegra_dsi_set_to_hs_mode(dc, dsi);
1313                                 switch_back_to_dc_mode = true;
1314                         }
1315                 } else {
1316                         tegra_dsi_set_to_lp_mode(dc, dsi);
1317                         switch_back_to_hs_mode = true;
1318                 }
1319         }
1320
1321         err = _tegra_dsi_write_data(dsi, pdata, data_id, data_len);
1322
1323
1324         if (switch_back_to_dc_mode)
1325                 dsi->driven_mode = TEGRA_DSI_DRIVEN_BY_DC;
1326         if (switch_back_to_dc_mode || switch_back_to_hs_mode)
1327                 tegra_dsi_set_to_hs_mode(dc, dsi);
1328
1329 fail:
1330         return err;
1331 }
1332
1333 static int tegra_dsi_send_panel_cmd(struct tegra_dc *dc,
1334                                                 struct tegra_dc_dsi_data *dsi,
1335                                                 struct tegra_dsi_cmd *cmd,
1336                                                 u32 n_cmd)
1337 {
1338         u32 i;
1339         int err;
1340
1341         err = 0;
1342         for (i = 0; i < n_cmd; i++) {
1343                 struct tegra_dsi_cmd *cur_cmd;
1344                 cur_cmd = &cmd[i];
1345
1346                 if (cur_cmd->cmd_type == TEGRA_DSI_DELAY_MS)
1347                         mdelay(cur_cmd->sp_len_dly.delay_ms);
1348                 else {
1349                         err = tegra_dsi_write_data(dc, dsi,
1350                                                 cur_cmd->pdata,
1351                                                 cur_cmd->data_id,
1352                                                 cur_cmd->sp_len_dly.data_len);
1353                         if (err < 0)
1354                                 break;
1355                 }
1356         }
1357         return err;
1358 }
1359
1360 static int tegra_dsi_bta(struct tegra_dc_dsi_data *dsi)
1361 {
1362         u32 val;
1363         u32 poll_time;
1364         int err;
1365
1366         poll_time = 0;
1367         err = 0;
1368
1369         val = tegra_dsi_readl(dsi, DSI_HOST_DSI_CONTROL);
1370         val |= DSI_HOST_DSI_CONTROL_IMM_BTA(TEGRA_DSI_ENABLE);
1371         tegra_dsi_writel(dsi, val, DSI_HOST_DSI_CONTROL);
1372
1373 #if DSI_USE_SYNC_POINTS
1374         /* FIXME: Workaround for nvhost_syncpt_read */
1375         dsi->syncpt_val = nvhost_syncpt_update_min(
1376                         &dsi->dc->ndev->host->syncpt, dsi->syncpt_id);
1377
1378         val = DSI_INCR_SYNCPT_COND(OP_DONE) |
1379                 DSI_INCR_SYNCPT_INDX(dsi->syncpt_id);
1380         tegra_dsi_writel(dsi, val, DSI_INCR_SYNCPT);
1381
1382         /* TODO: Use interrupt rather than polling */
1383         err = nvhost_syncpt_wait(&dsi->dc->ndev->host->syncpt,
1384                 dsi->syncpt_id, dsi->syncpt_val + 1);
1385         if (err < 0)
1386                 printk(KERN_ERR "DSI sync point failure\n");
1387         else
1388                 (dsi->syncpt_val)++;
1389 #else
1390         while (poll_time <  DSI_STATUS_POLLING_DURATION_USEC) {
1391                 val = tegra_dsi_readl(dsi, DSI_HOST_DSI_CONTROL);
1392                 val &= DSI_HOST_DSI_CONTROL_IMM_BTA(TEGRA_DSI_ENABLE);
1393                 if (!val)
1394                         break;
1395                 udelay(DSI_STATUS_POLLING_DELAY_USEC);
1396                 poll_time += DSI_STATUS_POLLING_DELAY_USEC;
1397         }
1398         if (poll_time > DSI_STATUS_POLLING_DURATION_USEC)
1399                 err = -EBUSY;
1400 #endif
1401
1402         return err;
1403 }
1404
1405 static void tegra_dsi_read_fifo(struct tegra_dc *dc,
1406                         struct tegra_dc_dsi_data *dsi,
1407                         u32 rd_fifo_cnt,
1408                         u8 *read_fifo)
1409 {
1410         u32 val;
1411         u32 i;
1412
1413         /* Read data from FIFO */
1414         for (i = 0; i < rd_fifo_cnt; i++) {
1415                 val = tegra_dsi_readl(dsi, DSI_RD_DATA);
1416                 printk(KERN_INFO "Read data[%d]: 0x%x\n", i, val);
1417                 memcpy(read_fifo, &val, 4);
1418                 read_fifo += 4;
1419         }
1420
1421         /* Make sure all the data is read from the FIFO */
1422         val = tegra_dsi_readl(dsi, DSI_STATUS);
1423         val &= DSI_STATUS_RD_FIFO_COUNT(0x1f);
1424         if (val)
1425                 dev_err(&dc->ndev->dev, "DSI FIFO_RD_CNT not zero"
1426                 " even after reading FIFO_RD_CNT words from read fifo\n");
1427 }
1428
1429 static int tegra_dsi_parse_read_response(struct tegra_dc *dc,
1430                                 u32 rd_fifo_cnt, u8 *read_fifo)
1431 {
1432         int err;
1433         u32 payload_size;
1434
1435         payload_size = 0;
1436         err = 0;
1437
1438         printk(KERN_INFO "escape sequence[0x%x]\n", read_fifo[0]);
1439         switch (read_fifo[4] & 0xff) {
1440         case GEN_LONG_RD_RES:
1441                 /* Fall through */
1442         case DCS_LONG_RD_RES:
1443                 payload_size = (read_fifo[5] |
1444                                 (read_fifo[6] << 8)) & 0xFFFF;
1445                 printk(KERN_INFO "Long read response Packet\n"
1446                                 "payload_size[0x%x]\n", payload_size);
1447                 break;
1448         case GEN_1_BYTE_SHORT_RD_RES:
1449                 /* Fall through */
1450         case DCS_1_BYTE_SHORT_RD_RES:
1451                 payload_size = 1;
1452                 printk(KERN_INFO "Short read response Packet\n"
1453                         "payload_size[0x%x]\n", payload_size);
1454                 break;
1455         case GEN_2_BYTE_SHORT_RD_RES:
1456                 /* Fall through */
1457         case DCS_2_BYTE_SHORT_RD_RES:
1458                 payload_size = 2;
1459                 printk(KERN_INFO "Short read response Packet\n"
1460                         "payload_size[0x%x]\n", payload_size);
1461                 break;
1462         case ACK_ERR_RES:
1463                 payload_size = 2;
1464                 printk(KERN_INFO "Acknowledge error report response\n"
1465                         "Packet payload_size[0x%x]\n", payload_size);
1466                 break;
1467         default:
1468                 /*reading from RD_FIFO_COUNT*/
1469                 printk(KERN_INFO "Invalid read response payload_size\n");
1470                 err = -EINVAL;
1471                 break;
1472         }
1473         return err;
1474 }
1475
1476 static int tegra_dsi_read_data(struct tegra_dc *dc,
1477                                 struct tegra_dc_dsi_data *dsi,
1478                                 u32 max_ret_payload_size,
1479                                 u32 panel_reg_addr, u8 *read_data)
1480 {
1481         u32 val;
1482         int err;
1483         u32 poll_time;
1484         u32 rd_fifo_cnt;
1485         bool switch_back_to_hs_mode;
1486         bool restart_dc_stream;
1487         bool switch_back_to_dc_mode;
1488
1489         err = 0;
1490         switch_back_to_hs_mode = false;
1491         restart_dc_stream = false;
1492         switch_back_to_dc_mode = false;
1493
1494         if ((dsi->status.init != DSI_MODULE_INIT) ||
1495                 (dsi->status.lphs == DSI_LPHS_NOT_INIT) ||
1496                 (dsi->status.driven == DSI_DRIVEN_MODE_NOT_INIT)) {
1497                 err = -EPERM;
1498                 goto fail;
1499         }
1500
1501         val = tegra_dsi_readl(dsi, DSI_STATUS);
1502         val &= DSI_STATUS_RD_FIFO_COUNT(0x1f);
1503         if (val) {
1504                 err = -EBUSY;
1505                 dev_err(&dc->ndev->dev, "DSI fifo count not zero\n");
1506                 goto fail;
1507         }
1508
1509         if (!tegra_dsi_is_controller_idle(dsi)) {
1510                 err = -EBUSY;
1511                 dev_err(&dc->ndev->dev, "DSI trigger bit is already set\n");
1512                 goto fail;
1513         }
1514
1515         if (dsi->status.lphs == DSI_LPHS_IN_HS_MODE) {
1516                 if (dsi->status.driven == DSI_DRIVEN_MODE_DC) {
1517                         if (dsi->status.dc_stream == DSI_DC_STREAM_ENABLE)
1518                                 restart_dc_stream = true;
1519                         dsi->driven_mode = TEGRA_DSI_DRIVEN_BY_HOST;
1520                         switch_back_to_dc_mode = true;
1521                         if (dsi->info.hs_cmd_mode_supported) {
1522                                 err = tegra_dsi_set_to_hs_mode(dc, dsi);
1523                                 if (err < 0) {
1524                                         dev_err(&dc->ndev->dev,
1525                                         "DSI failed to go to HS mode host driven\n");
1526                                         goto fail;
1527                                 }
1528                         }
1529                 }
1530                 if (!dsi->info.hs_cmd_mode_supported) {
1531                         err = tegra_dsi_set_to_lp_mode(dc, dsi);
1532                         if (err < 0) {
1533                                 dev_err(&dc->ndev->dev,
1534                                 "DSI failed to go to LP mode\n");
1535                                 goto fail;
1536                         }
1537                         switch_back_to_hs_mode = true;
1538                 }
1539         }
1540
1541         /* Set max return payload size in words */
1542         err = _tegra_dsi_write_data(dsi, NULL,
1543                 dsi_command_max_return_pkt_size,
1544                 max_ret_payload_size);
1545         if (err < 0) {
1546                 dev_err(&dc->ndev->dev,
1547                                 "DSI write failed\n");
1548                 goto fail;
1549         }
1550
1551         /* DCS to read given panel register */
1552         err = _tegra_dsi_write_data(dsi, NULL,
1553                 dsi_command_dcs_read_with_no_params,
1554                 panel_reg_addr);
1555         if (err < 0) {
1556                 dev_err(&dc->ndev->dev,
1557                                 "DSI write failed\n");
1558                 goto fail;
1559         }
1560
1561         err = tegra_dsi_bta(dsi);
1562         if (err < 0) {
1563                 dev_err(&dc->ndev->dev,
1564                         "DSI IMM BTA timeout\n");
1565                 goto fail;
1566         }
1567
1568         poll_time = 0;
1569         while (poll_time <  DSI_DELAY_FOR_READ_FIFO) {
1570                 mdelay(1);
1571                 val = tegra_dsi_readl(dsi, DSI_STATUS);
1572                 rd_fifo_cnt = val & DSI_STATUS_RD_FIFO_COUNT(0x1f);
1573                 if (rd_fifo_cnt << 2 > DSI_READ_FIFO_DEPTH)
1574                         dev_err(&dc->ndev->dev,
1575                         "DSI RD_FIFO_CNT is greater than RD_FIFO_DEPTH\n");
1576                         break;
1577                 poll_time++;
1578         }
1579
1580         if (rd_fifo_cnt == 0) {
1581                 dev_info(&dc->ndev->dev,
1582                         "DSI RD_FIFO_CNT is zero\n");
1583                 err = -EINVAL;
1584                 goto fail;
1585         }
1586
1587         if (val & DSI_STATUS_LB_UNDERFLOW(0x1) ||
1588                 val & DSI_STATUS_LB_OVERFLOW(0x1)) {
1589                 dev_err(&dc->ndev->dev,
1590                         "DSI overflow/underflow error\n");
1591                 err = -EINVAL;
1592                 goto fail;
1593         }
1594
1595         tegra_dsi_read_fifo(dc, dsi, rd_fifo_cnt, read_data);
1596
1597         err = tegra_dsi_parse_read_response(dc, rd_fifo_cnt, read_data);
1598 fail:
1599         if (switch_back_to_dc_mode)
1600                 dsi->driven_mode = TEGRA_DSI_DRIVEN_BY_DC;
1601         if (switch_back_to_dc_mode || switch_back_to_hs_mode)
1602                 tegra_dsi_set_to_hs_mode(dc, dsi);
1603         if (restart_dc_stream)
1604                 tegra_dsi_start_dc_stream(dc, dsi);
1605
1606         return err;
1607 }
1608
1609 static int tegra_dsi_enter_ulpm(struct tegra_dc_dsi_data *dsi)
1610 {
1611         u32 val;
1612         int ret;
1613
1614         ret = 0;
1615
1616         val = tegra_dsi_readl(dsi, DSI_HOST_DSI_CONTROL);
1617         val &= ~DSI_HOST_DSI_CONTROL_ULTRA_LOW_POWER(3);
1618         val |= DSI_HOST_DSI_CONTROL_ULTRA_LOW_POWER(ENTER_ULPM);
1619         tegra_dsi_writel(dsi, val, DSI_HOST_DSI_CONTROL);
1620
1621 #if DSI_USE_SYNC_POINTS
1622         ret = tegra_dsi_syncpt(dsi);
1623         if (ret < 0) {
1624                 printk(KERN_ERR "DSI syncpt for ulpm enter failed\n");
1625                 goto fail;
1626         }
1627 #else
1628         /* TODO: Find exact delay required */
1629         mdelay(10);
1630 #endif
1631         dsi->ulpm = true;
1632 fail:
1633         return ret;
1634 }
1635
1636 static int tegra_dsi_exit_ulpm(struct tegra_dc_dsi_data *dsi)
1637 {
1638         u32 val;
1639         int ret;
1640
1641         ret = 0;
1642
1643         val = tegra_dsi_readl(dsi, DSI_HOST_DSI_CONTROL);
1644         val &= ~DSI_HOST_DSI_CONTROL_ULTRA_LOW_POWER(3);
1645         val |= DSI_HOST_DSI_CONTROL_ULTRA_LOW_POWER(EXIT_ULPM);
1646         tegra_dsi_writel(dsi, val, DSI_HOST_DSI_CONTROL);
1647
1648 #if DSI_USE_SYNC_POINTS
1649         ret = tegra_dsi_syncpt(dsi);
1650         if (ret < 0) {
1651                 printk(KERN_ERR "DSI syncpt for ulpm exit failed\n");
1652                 goto fail;
1653         }
1654 #else
1655         /* TODO: Find exact delay required */
1656         mdelay(10);
1657 #endif
1658         dsi->ulpm = false;
1659
1660         val = tegra_dsi_readl(dsi, DSI_HOST_DSI_CONTROL);
1661         val &= ~DSI_HOST_DSI_CONTROL_ULTRA_LOW_POWER(0x3);
1662         val |= DSI_HOST_DSI_CONTROL_ULTRA_LOW_POWER(NORMAL);
1663         tegra_dsi_writel(dsi, val, DSI_HOST_DSI_CONTROL);
1664 fail:
1665         return ret;
1666
1667 }
1668
1669 static void tegra_dc_dsi_enable(struct tegra_dc *dc)
1670 {
1671         struct tegra_dc_dsi_data *dsi = tegra_dc_get_outdata(dc);
1672         int err;
1673         u32 val;
1674
1675         tegra_dc_io_start(dc);
1676         mutex_lock(&dsi->lock);
1677
1678         /* Stop DC stream before configuring DSI registers
1679          * to avoid visible glitches on panel during transition
1680          * from bootloader to kernel driver
1681          */
1682         tegra_dsi_stop_dc_stream_at_frame_end(dc, dsi);
1683
1684         if (dsi->enabled) {
1685                 if (dsi->ulpm) {
1686                         if (tegra_dsi_exit_ulpm(dsi) < 0) {
1687                                 printk(KERN_ERR "DSI failed to exit ulpm\n");
1688                                 goto fail;
1689                         }
1690                 }
1691                 if (dsi->info.panel_reset) {
1692                         err = tegra_dsi_send_panel_cmd(dc, dsi,
1693                                                         dsi->info.dsi_init_cmd,
1694                                                         dsi->info.n_init_cmd);
1695                         if (err < 0) {
1696                                 dev_err(&dc->ndev->dev,
1697                                 "dsi: error sending dsi init cmd\n");
1698                                 goto fail;
1699                         }
1700                 } else if (dsi->info.dsi_late_resume_cmd) {
1701                         err = tegra_dsi_send_panel_cmd(dc, dsi,
1702                                                 dsi->info.dsi_late_resume_cmd,
1703                                                 dsi->info.n_late_resume_cmd);
1704                         if (err < 0) {
1705                                 dev_err(&dc->ndev->dev,
1706                                 "dsi: error sending late resume cmd\n");
1707                                 goto fail;
1708                         }
1709                 }
1710         } else {
1711                 err = tegra_dsi_init_hw(dc, dsi);
1712                 if (err < 0) {
1713                         dev_err(&dc->ndev->dev,
1714                                 "dsi: not able to init dsi hardware\n");
1715                         goto fail;
1716                 }
1717
1718                 if (dsi->ulpm) {
1719                         if (tegra_dsi_enter_ulpm(dsi) < 0) {
1720                                 printk(KERN_ERR "DSI failed to enter ulpm\n");
1721                                 goto fail;
1722                         }
1723                         val = DSI_PAD_CONTROL_PAD_PDIO(0) |
1724                                 DSI_PAD_CONTROL_PAD_PDIO_CLK(0) |
1725                                 DSI_PAD_CONTROL_PAD_PULLDN_ENAB(TEGRA_DSI_DISABLE);
1726                         tegra_dsi_writel(dsi, val, DSI_PAD_CONTROL);
1727                         if (tegra_dsi_exit_ulpm(dsi) < 0) {
1728                                 printk(KERN_ERR "DSI failed to exit ulpm\n");
1729                                 goto fail;
1730                         }
1731                 }
1732
1733                 err = tegra_dsi_set_to_lp_mode(dc, dsi);
1734                 if (err < 0) {
1735                         dev_err(&dc->ndev->dev,
1736                                 "dsi: not able to set to lp mode\n");
1737                         goto fail;
1738                 }
1739
1740                 err = tegra_dsi_send_panel_cmd(dc, dsi, dsi->info.dsi_init_cmd,
1741                                                 dsi->info.n_init_cmd);
1742                 if (err < 0) {
1743                         dev_err(&dc->ndev->dev,
1744                                 "dsi: error while sending dsi init cmd\n");
1745                         goto fail;
1746                 }
1747
1748                 err = tegra_dsi_set_to_hs_mode(dc, dsi);
1749                 if (err < 0) {
1750                         dev_err(&dc->ndev->dev,
1751                                 "dsi: not able to set to hs mode\n");
1752                         goto fail;
1753                 }
1754
1755                 dsi->enabled = true;
1756         }
1757
1758         if (dsi->status.driven == DSI_DRIVEN_MODE_DC)
1759                 tegra_dsi_start_dc_stream(dc, dsi);
1760 fail:
1761         mutex_unlock(&dsi->lock);
1762         tegra_dc_io_end(dc);
1763 }
1764
1765 static void _tegra_dc_dsi_init(struct tegra_dc *dc)
1766 {
1767         struct tegra_dc_dsi_data *dsi = tegra_dc_get_outdata(dc);
1768
1769         tegra_dsi_init_sw(dc, dsi);
1770         /* TODO: Configure the CSI pad configuration */
1771 }
1772
1773 static int tegra_dc_dsi_cp_p_cmd(struct tegra_dsi_cmd* src,
1774                                         struct tegra_dsi_cmd* dst, u16 n_cmd)
1775 {
1776         u16 i;
1777         u16 len;
1778
1779         memcpy(dst, src, sizeof(*dst) * n_cmd);
1780
1781         for (i = 0; i < n_cmd; i++)
1782                 if (src[i].pdata) {
1783                         len = sizeof(*src[i].pdata) * src[i].sp_len_dly.data_len;
1784                         dst[i].pdata = kzalloc(len, GFP_KERNEL);
1785                         if (!dst[i].pdata)
1786                                 goto free_cmd_pdata;
1787                         memcpy(dst[i].pdata, src[i].pdata, len);
1788                 }
1789
1790         return 0;
1791
1792 free_cmd_pdata:
1793         for (--i; i >=0; i--)
1794                 if (dst[i].pdata)
1795                         kfree(dst[i].pdata);
1796         return -ENOMEM;
1797 }
1798
1799 static int tegra_dc_dsi_cp_info(struct tegra_dc_dsi_data* dsi,
1800                                                 struct tegra_dsi_out* p_dsi)
1801 {
1802         struct tegra_dsi_cmd *p_init_cmd;
1803         struct tegra_dsi_cmd *p_early_suspend_cmd;
1804         struct tegra_dsi_cmd *p_late_resume_cmd;
1805         struct tegra_dsi_cmd *p_suspend_cmd;
1806         int err;
1807
1808         if (p_dsi->n_data_lanes > MAX_DSI_DATA_LANES)
1809                 return -EINVAL;
1810
1811         p_init_cmd = kzalloc(sizeof(*p_init_cmd) *
1812                                 p_dsi->n_init_cmd, GFP_KERNEL);
1813         if (!p_init_cmd)
1814                 return -ENOMEM;
1815
1816         if (p_dsi->dsi_early_suspend_cmd) {
1817                 p_early_suspend_cmd = kzalloc(sizeof(*p_early_suspend_cmd) *
1818                                         p_dsi->n_early_suspend_cmd,
1819                                         GFP_KERNEL);
1820                 if (!p_early_suspend_cmd) {
1821                         err = -ENOMEM;
1822                         goto err_free_init_cmd;
1823                 }
1824         }
1825
1826         if (p_dsi->dsi_late_resume_cmd) {
1827                 p_late_resume_cmd = kzalloc(sizeof(*p_late_resume_cmd) *
1828                                         p_dsi->n_late_resume_cmd,
1829                                         GFP_KERNEL);
1830                 if (!p_late_resume_cmd) {
1831                         err = -ENOMEM;
1832                         goto err_free_p_early_suspend_cmd;
1833                 }
1834         }
1835
1836         p_suspend_cmd = kzalloc(sizeof(*p_suspend_cmd) * p_dsi->n_suspend_cmd,
1837                                 GFP_KERNEL);
1838         if (!p_suspend_cmd) {
1839                 err = -ENOMEM;
1840                 goto err_free_p_late_resume_cmd;
1841         }
1842
1843         memcpy(&dsi->info, p_dsi, sizeof(dsi->info));
1844
1845         /* Copy panel init cmd */
1846         err = tegra_dc_dsi_cp_p_cmd(p_dsi->dsi_init_cmd,
1847                                                 p_init_cmd, p_dsi->n_init_cmd);
1848         if (err < 0)
1849                 goto err_free;
1850         dsi->info.dsi_init_cmd = p_init_cmd;
1851
1852         /* Copy panel early suspend cmd */
1853         if (p_dsi->dsi_early_suspend_cmd) {
1854                 err = tegra_dc_dsi_cp_p_cmd(p_dsi->dsi_early_suspend_cmd,
1855                                         p_early_suspend_cmd,
1856                                         p_dsi->n_early_suspend_cmd);
1857                 if (err < 0)
1858                         goto err_free;
1859                 dsi->info.dsi_early_suspend_cmd = p_early_suspend_cmd;
1860         }
1861
1862         /* Copy panel late resume cmd */
1863         if (p_dsi->dsi_late_resume_cmd) {
1864                 err = tegra_dc_dsi_cp_p_cmd(p_dsi->dsi_late_resume_cmd,
1865                                                 p_late_resume_cmd,
1866                                                 p_dsi->n_late_resume_cmd);
1867                 if (err < 0)
1868                         goto err_free;
1869                 dsi->info.dsi_late_resume_cmd = p_late_resume_cmd;
1870         }
1871
1872         /* Copy panel suspend cmd */
1873         err = tegra_dc_dsi_cp_p_cmd(p_dsi->dsi_suspend_cmd, p_suspend_cmd,
1874                                         p_dsi->n_suspend_cmd);
1875         if (err < 0)
1876                 goto err_free;
1877         dsi->info.dsi_suspend_cmd = p_suspend_cmd;
1878
1879         if (!dsi->info.panel_reset_timeout_msec)
1880                 dsi->info.panel_reset_timeout_msec = DEFAULT_PANEL_RESET_TIMEOUT;
1881
1882         if (!dsi->info.panel_buffer_size_byte)
1883                 dsi->info.panel_buffer_size_byte = DEFAULT_PANEL_BUFFER_BYTE;
1884
1885         if (!dsi->info.max_panel_freq_khz) {
1886                 dsi->info.max_panel_freq_khz = DEFAULT_MAX_DSI_PHY_CLK_KHZ;
1887
1888                 if (dsi->info.video_burst_mode >
1889                                 TEGRA_DSI_VIDEO_NONE_BURST_MODE_WITH_SYNC_END){
1890                         dev_err(&dsi->dc->ndev->dev, "DSI: max_panel_freq_khz"
1891                                         "is not set for DSI burst mode.\n");
1892                         dsi->info.video_burst_mode =
1893                                 TEGRA_DSI_VIDEO_BURST_MODE_LOWEST_SPEED;
1894                 }
1895         }
1896
1897         if (!dsi->info.lp_cmd_mode_freq_khz)
1898                 dsi->info.lp_cmd_mode_freq_khz = DEFAULT_LP_CMD_MODE_CLK_KHZ;
1899
1900         /* host mode is for testing only*/
1901         dsi->driven_mode = TEGRA_DSI_DRIVEN_BY_DC;
1902
1903         return 0;
1904
1905 err_free:
1906         kfree(p_suspend_cmd);
1907 err_free_p_late_resume_cmd:
1908         kfree(p_late_resume_cmd);
1909 err_free_p_early_suspend_cmd:
1910         kfree(p_early_suspend_cmd);
1911 err_free_init_cmd:
1912         kfree(p_init_cmd);
1913         return err;
1914 }
1915
1916 static int tegra_dc_dsi_init(struct tegra_dc *dc)
1917 {
1918         struct tegra_dc_dsi_data *dsi;
1919         struct resource *res;
1920         struct resource *base_res;
1921         void __iomem *base;
1922         struct clk *dc_clk = NULL;
1923         struct clk *dsi_clk = NULL;
1924         struct tegra_dsi_out *dsi_pdata;
1925         int err;
1926
1927         err = 0;
1928
1929         dsi = kzalloc(sizeof(*dsi), GFP_KERNEL);
1930         if (!dsi)
1931                 return -ENOMEM;
1932
1933         res = nvhost_get_resource_byname(dc->ndev, IORESOURCE_MEM,
1934                                         "dsi_regs");
1935         if (!res) {
1936                 dev_err(&dc->ndev->dev, "dsi: no mem resource\n");
1937                 err = -ENOENT;
1938                 goto err_free_dsi;
1939         }
1940
1941         base_res = request_mem_region(res->start, resource_size(res),
1942                                 dc->ndev->name);
1943         if (!base_res) {
1944                 dev_err(&dc->ndev->dev, "dsi: request_mem_region failed\n");
1945                 err = -EBUSY;
1946                 goto err_free_dsi;
1947         }
1948
1949         base = ioremap(res->start, resource_size(res));
1950         if (!base) {
1951                 dev_err(&dc->ndev->dev, "dsi: registers can't be mapped\n");
1952                 err = -EBUSY;
1953                 goto err_release_regs;
1954         }
1955
1956         dsi_pdata = dc->pdata->default_out->dsi;
1957         if (!dsi_pdata) {
1958                 dev_err(&dc->ndev->dev, "dsi: dsi data not available\n");
1959                 goto err_release_regs;
1960         }
1961
1962         if (dsi_pdata->dsi_instance)
1963                 dsi_clk = clk_get(&dc->ndev->dev, "dsib");
1964         else
1965                 dsi_clk = clk_get(&dc->ndev->dev, "dsia");
1966
1967         if (IS_ERR_OR_NULL(dsi_clk)) {
1968                 dev_err(&dc->ndev->dev, "dsi: can't get clock\n");
1969                 err = -EBUSY;
1970                 goto err_release_regs;
1971         }
1972
1973         dc_clk = clk_get_sys(dev_name(&dc->ndev->dev), NULL);
1974         if (IS_ERR_OR_NULL(dc_clk)) {
1975                 dev_err(&dc->ndev->dev, "dsi: dc clock %s unavailable\n",
1976                         dev_name(&dc->ndev->dev));
1977                 err = -EBUSY;
1978                 goto err_clk_put;
1979         }
1980
1981         err = tegra_dc_dsi_cp_info(dsi, dsi_pdata);
1982         if (err < 0)
1983                 goto err_dsi_data;
1984
1985         mutex_init(&dsi->lock);
1986         dsi->dc = dc;
1987         dsi->base = base;
1988         dsi->base_res = base_res;
1989         dsi->dc_clk = dc_clk;
1990         dsi->dsi_clk = dsi_clk;
1991
1992         tegra_dc_set_outdata(dc, dsi);
1993         _tegra_dc_dsi_init(dc);
1994
1995         return 0;
1996
1997 err_dsi_data:
1998 err_clk_put:
1999         clk_put(dsi_clk);
2000 err_release_regs:
2001         release_resource(base_res);
2002 err_free_dsi:
2003         kfree(dsi);
2004
2005         return err;
2006 }
2007
2008 static void tegra_dc_dsi_destroy(struct tegra_dc *dc)
2009 {
2010         struct tegra_dc_dsi_data *dsi = tegra_dc_get_outdata(dc);
2011         u16 i;
2012         u32 val;
2013
2014         mutex_lock(&dsi->lock);
2015
2016         /* free up the pdata*/
2017         for(i = 0; i < dsi->info.n_init_cmd; i++){
2018                 if(dsi->info.dsi_init_cmd[i].pdata)
2019                         kfree(dsi->info.dsi_init_cmd[i].pdata);
2020         }
2021         kfree(dsi->info.dsi_init_cmd);
2022
2023         /* Disable dc stream*/
2024         if(dsi->status.dc_stream == DSI_DC_STREAM_ENABLE)
2025                 tegra_dsi_stop_dc_stream(dc, dsi);
2026
2027         /* Disable dsi phy clock*/
2028         if(dsi->status.clk_out == DSI_PHYCLK_OUT_EN)
2029                 tegra_dsi_hs_clk_out_disable(dc, dsi);
2030
2031         val = DSI_POWER_CONTROL_LEG_DSI_ENABLE(TEGRA_DSI_DISABLE);
2032         tegra_dsi_writel(dsi, val, DSI_POWER_CONTROL);
2033
2034         iounmap(dsi->base);
2035         release_resource(dsi->base_res);
2036
2037         clk_put(dsi->dc_clk);
2038         clk_put(dsi->dsi_clk);
2039
2040         mutex_unlock(&dsi->lock);
2041
2042         mutex_destroy(&dsi->lock);
2043         kfree(dsi);
2044 }
2045
2046 static void tegra_dc_dsi_disable(struct tegra_dc *dc)
2047 {
2048         struct tegra_dc_dsi_data *dsi = tegra_dc_get_outdata(dc);
2049         int err;
2050
2051         tegra_dc_io_start(dc);
2052         mutex_lock(&dsi->lock);
2053
2054         if (dsi->status.dc_stream == DSI_DC_STREAM_ENABLE)
2055                 tegra_dsi_stop_dc_stream(dc, dsi);
2056
2057         if (dsi->info.dsi_early_suspend_cmd) {
2058                 err = tegra_dsi_send_panel_cmd(dc, dsi,
2059                         dsi->info.dsi_early_suspend_cmd,
2060                         dsi->info.n_early_suspend_cmd);
2061                 if (err < 0) {
2062                         dev_err(&dc->ndev->dev,
2063                                 "dsi: Error sending early suspend cmd\n");
2064                         goto fail;
2065                 }
2066         }
2067
2068         if (!dsi->ulpm) {
2069                 if (tegra_dsi_enter_ulpm(dsi) < 0)
2070                         printk(KERN_ERR "DSI failed to enter ulpm\n");
2071         }
2072 fail:
2073         mutex_unlock(&dsi->lock);
2074         tegra_dc_io_end(dc);
2075 }
2076
2077 #ifdef CONFIG_PM
2078 static void tegra_dc_dsi_suspend(struct tegra_dc *dc)
2079 {
2080         struct tegra_dc_dsi_data *dsi;
2081         int err;
2082         u32 val;
2083
2084         dsi = tegra_dc_get_outdata(dc);
2085
2086         tegra_dc_io_start(dc);
2087         mutex_lock(&dsi->lock);
2088
2089         if (!dsi->enabled)
2090                 goto fail;
2091
2092         if (dsi->ulpm) {
2093                 if (tegra_dsi_exit_ulpm(dsi) < 0) {
2094                         printk(KERN_ERR "DSI failed to exit ulpm");
2095                         goto fail;
2096                 }
2097         }
2098
2099         /* Suspend Panel */
2100         err = tegra_dsi_send_panel_cmd(dc, dsi,
2101                         dsi->info.dsi_suspend_cmd,
2102                         dsi->info.n_suspend_cmd);
2103         if (err < 0) {
2104                 dev_err(&dc->ndev->dev,
2105                         "dsi: Error sending suspend cmd\n");
2106                 goto fail;
2107         }
2108         if (!dsi->ulpm) {
2109                 if (tegra_dsi_enter_ulpm(dsi) < 0) {
2110                         printk(KERN_ERR "DSI failed to enter ulpm\n");
2111                         goto fail;
2112                 }
2113         }
2114
2115         /* Suspend pad */
2116         val = tegra_dsi_readl(dsi, DSI_PAD_CONTROL);
2117         val = DSI_PAD_CONTROL_PAD_PDIO(0x3) |
2118                 DSI_PAD_CONTROL_PAD_PDIO_CLK(0x1) |
2119                 DSI_PAD_CONTROL_PAD_PULLDN_ENAB(TEGRA_DSI_ENABLE);
2120         tegra_dsi_writel(dsi, val, DSI_PAD_CONTROL);
2121
2122         /* Suspend core-logic */
2123         val = DSI_POWER_CONTROL_LEG_DSI_ENABLE(TEGRA_DSI_DISABLE);
2124         tegra_dsi_writel(dsi, val, DSI_POWER_CONTROL);
2125
2126         dsi->enabled = false;
2127
2128         clk_disable(dsi->dsi_clk);
2129         dsi->clk_ref = false;
2130 fail:
2131         mutex_unlock(&dsi->lock);
2132         tegra_dc_io_end(dc);
2133 }
2134
2135 static void tegra_dc_dsi_resume(struct tegra_dc *dc)
2136 {
2137         /* Not required since tegra_dc_dsi_enable
2138          * will reconfigure the controller from scratch
2139          */
2140 }
2141 #endif
2142
2143 struct tegra_dc_out_ops tegra_dc_dsi_ops = {
2144         .init = tegra_dc_dsi_init,
2145         .destroy = tegra_dc_dsi_destroy,
2146         .enable = tegra_dc_dsi_enable,
2147         .disable = tegra_dc_dsi_disable,
2148 #ifdef CONFIG_PM
2149         .suspend = tegra_dc_dsi_suspend,
2150         .resume = tegra_dc_dsi_resume,
2151 #endif
2152 };