video: tegra: dsi: Fix dsi phy timing
[linux-2.6.git] / drivers / video / tegra / dc / dsi.c
1 /*
2  * drivers/video/tegra/dc/dsi.c
3  *
4  * Copyright (c) 2011, NVIDIA Corporation.
5  *
6  * This software is licensed under the terms of the GNU General Public
7  * License version 2, as published by the Free Software Foundation, and
8  * may be copied, distributed, and modified under those terms.
9  *
10  * This program is distributed in the hope that it will be useful,
11  * but WITHOUT ANY WARRANTY; without even the implied warranty of
12  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
13  * GNU General Public License for more details.
14  *
15  */
16
17 #include <linux/clk.h>
18 #include <linux/delay.h>
19 #include <linux/err.h>
20 #include <linux/fb.h>
21 #include <linux/gpio.h>
22 #include <linux/interrupt.h>
23 #include <linux/kernel.h>
24 #include <linux/slab.h>
25 #include <linux/spinlock.h>
26 #include <linux/workqueue.h>
27
28 #include <mach/clk.h>
29 #include <mach/dc.h>
30 #include <mach/fb.h>
31 #include <mach/csi.h>
32 #include <linux/nvhost.h>
33
34 #include "dc_reg.h"
35 #include "dc_priv.h"
36 #include "dsi_regs.h"
37 #include "dsi.h"
38
39 #define DSI_USE_SYNC_POINTS             1
40 #define S_TO_MS(x)                      (1000 * (x))
41
42 #define DSI_MODULE_NOT_INIT             0x0
43 #define DSI_MODULE_INIT                 0x1
44
45 #define DSI_LPHS_NOT_INIT               0x0
46 #define DSI_LPHS_IN_LP_MODE             0x1
47 #define DSI_LPHS_IN_HS_MODE             0x2
48
49 #define DSI_VIDEO_TYPE_NOT_INIT         0x0
50 #define DSI_VIDEO_TYPE_VIDEO_MODE       0x1
51 #define DSI_VIDEO_TYPE_CMD_MODE         0x2
52
53 #define DSI_DRIVEN_MODE_NOT_INIT        0x0
54 #define DSI_DRIVEN_MODE_DC              0x1
55 #define DSI_DRIVEN_MODE_HOST            0x2
56
57 #define DSI_PHYCLK_OUT_DIS              0x0
58 #define DSI_PHYCLK_OUT_EN               0x1
59
60 #define DSI_PHYCLK_NOT_INIT             0x0
61 #define DSI_PHYCLK_CONTINUOUS           0x1
62 #define DSI_PHYCLK_TX_ONLY              0x2
63
64 #define DSI_CLK_BURST_NOT_INIT          0x0
65 #define DSI_CLK_BURST_NONE_BURST        0x1
66 #define DSI_CLK_BURST_BURST_MODE        0x2
67
68 #define DSI_DC_STREAM_DISABLE           0x0
69 #define DSI_DC_STREAM_ENABLE            0x1
70
71 #define DSI_LP_OP_NOT_INIT              0x0
72 #define DSI_LP_OP_WRITE                 0x1
73 #define DSI_LP_OP_READ                  0x2
74
75 static bool enable_read_debug;
76 module_param(enable_read_debug, bool, 0644);
77 MODULE_PARM_DESC(enable_read_debug,
78                 "Enable to print read fifo and return packet type");
79
80 struct dsi_status {
81         unsigned init:2;
82
83         unsigned lphs:2;
84
85         unsigned vtype:2;
86         unsigned driven:2;
87
88         unsigned clk_out:2;
89         unsigned clk_mode:2;
90         unsigned clk_burst:2;
91
92         unsigned lp_op:2;
93
94         unsigned dc_stream:1;
95 };
96
97 /* source of video data */
98 enum {
99         TEGRA_DSI_DRIVEN_BY_DC,
100         TEGRA_DSI_DRIVEN_BY_HOST,
101 };
102
103 struct tegra_dc_dsi_data {
104         struct tegra_dc *dc;
105         void __iomem *base;
106         struct resource *base_res;
107
108         struct clk *dc_clk;
109         struct clk *dsi_clk;
110         bool clk_ref;
111
112         struct mutex lock;
113
114         /* data from board info */
115         struct tegra_dsi_out info;
116
117         struct dsi_status status;
118
119         struct dsi_phy_timing_inclk phy_timing;
120
121         u8 driven_mode;
122         u8 controller_index;
123
124         u8 pixel_scaler_mul;
125         u8 pixel_scaler_div;
126
127         u32 default_shift_clk_div;
128         u32 default_pixel_clk_khz;
129         u32 default_hs_clk_khz;
130
131         u32 shift_clk_div;
132         u32 target_hs_clk_khz;
133         u32 target_lp_clk_khz;
134
135         u32 syncpt_id;
136         u32 syncpt_val;
137
138         u16 current_bit_clk_ns;
139         u32 current_dsi_clk_khz;
140
141         u32 dsi_control_val;
142
143         bool ulpm;
144         bool enabled;
145 };
146
147 const u32 dsi_pkt_seq_reg[NUMOF_PKT_SEQ] = {
148         DSI_PKT_SEQ_0_LO,
149         DSI_PKT_SEQ_0_HI,
150         DSI_PKT_SEQ_1_LO,
151         DSI_PKT_SEQ_1_HI,
152         DSI_PKT_SEQ_2_LO,
153         DSI_PKT_SEQ_2_HI,
154         DSI_PKT_SEQ_3_LO,
155         DSI_PKT_SEQ_3_HI,
156         DSI_PKT_SEQ_4_LO,
157         DSI_PKT_SEQ_4_HI,
158         DSI_PKT_SEQ_5_LO,
159         DSI_PKT_SEQ_5_HI,
160 };
161
162 const u32 dsi_pkt_seq_video_non_burst_syne[NUMOF_PKT_SEQ] = {
163         PKT_ID0(CMD_VS) | PKT_LEN0(0) | PKT_ID1(CMD_EOT) | PKT_LEN1(0) | PKT_LP,
164         0,
165         PKT_ID0(CMD_VE) | PKT_LEN0(0) | PKT_ID1(CMD_EOT) | PKT_LEN1(0) | PKT_LP,
166         0,
167         PKT_ID0(CMD_HS) | PKT_LEN0(0) | PKT_ID1(CMD_EOT) | PKT_LEN1(0) | PKT_LP,
168         0,
169         PKT_ID0(CMD_HS) | PKT_LEN0(0) | PKT_ID1(CMD_BLNK) | PKT_LEN1(1) |
170         PKT_ID2(CMD_HE) | PKT_LEN2(0),
171         PKT_ID3(CMD_BLNK) | PKT_LEN3(2) | PKT_ID4(CMD_RGB) | PKT_LEN4(3) |
172         PKT_ID5(CMD_BLNK) | PKT_LEN5(4),
173         PKT_ID0(CMD_HS) | PKT_LEN0(0) | PKT_ID1(CMD_EOT) | PKT_LEN1(0) | PKT_LP,
174         0,
175         PKT_ID0(CMD_HS) | PKT_LEN0(0) | PKT_ID1(CMD_BLNK) | PKT_LEN1(1) |
176         PKT_ID2(CMD_HE) | PKT_LEN2(0),
177         PKT_ID3(CMD_BLNK) | PKT_LEN3(2) | PKT_ID4(CMD_RGB) | PKT_LEN4(3) |
178         PKT_ID5(CMD_BLNK) | PKT_LEN5(4),
179 };
180
181 const u32 dsi_pkt_seq_video_non_burst[NUMOF_PKT_SEQ] = {
182         PKT_ID0(CMD_VS) | PKT_LEN0(0) | PKT_ID1(CMD_EOT) | PKT_LEN1(0) | PKT_LP,
183         0,
184         PKT_ID0(CMD_HS) | PKT_LEN0(0) | PKT_ID1(CMD_EOT) | PKT_LEN1(0) | PKT_LP,
185         0,
186         PKT_ID0(CMD_HS) | PKT_LEN0(0) | PKT_ID1(CMD_EOT) | PKT_LEN1(0) | PKT_LP,
187         0,
188         PKT_ID0(CMD_HS) | PKT_LEN0(0) | PKT_ID1(CMD_BLNK) | PKT_LEN1(2) |
189         PKT_ID2(CMD_RGB) | PKT_LEN2(3),
190         PKT_ID3(CMD_BLNK) | PKT_LEN3(4),
191         PKT_ID0(CMD_HS) | PKT_LEN0(0) | PKT_ID1(CMD_EOT) | PKT_LEN1(0) | PKT_LP,
192         0,
193         PKT_ID0(CMD_HS) | PKT_LEN0(0) | PKT_ID1(CMD_BLNK) | PKT_LEN1(2) |
194         PKT_ID2(CMD_RGB) | PKT_LEN2(3),
195         PKT_ID3(CMD_BLNK) | PKT_LEN3(4),
196 };
197
198 static const u32 dsi_pkt_seq_video_burst[NUMOF_PKT_SEQ] = {
199         PKT_ID0(CMD_VS) | PKT_LEN0(0) | PKT_ID1(CMD_EOT) | PKT_LEN1(7) | PKT_LP,
200         0,
201         PKT_ID0(CMD_HS) | PKT_LEN0(0) | PKT_ID1(CMD_EOT) | PKT_LEN1(7) | PKT_LP,
202         0,
203         PKT_ID0(CMD_HS) | PKT_LEN0(0) | PKT_ID1(CMD_EOT) | PKT_LEN1(7) | PKT_LP,
204         0,
205         PKT_ID0(CMD_HS) | PKT_LEN0(0) | PKT_ID1(CMD_BLNK) | PKT_LEN1(2)|
206         PKT_ID2(CMD_RGB) | PKT_LEN2(3) | PKT_LP,
207         PKT_ID0(CMD_EOT) | PKT_LEN0(7),
208         PKT_ID0(CMD_HS) | PKT_LEN0(0) | PKT_ID1(CMD_EOT) | PKT_LEN1(7) | PKT_LP,
209         0,
210         PKT_ID0(CMD_HS) | PKT_LEN0(0) | PKT_ID1(CMD_BLNK) | PKT_LEN1(2)|
211         PKT_ID2(CMD_RGB) | PKT_LEN2(3) | PKT_LP,
212         PKT_ID0(CMD_EOT) | PKT_LEN0(7),
213 };
214
215 static const u32 dsi_pkt_seq_video_burst_no_eot[NUMOF_PKT_SEQ] = {
216         PKT_ID0(CMD_VS) | PKT_LEN0(0) | PKT_ID1(CMD_EOT) | PKT_LEN1(0) | PKT_LP,
217         0,
218         PKT_ID0(CMD_HS) | PKT_LEN0(0) | PKT_ID1(CMD_EOT) | PKT_LEN1(0) | PKT_LP,
219         0,
220         PKT_ID0(CMD_HS) | PKT_LEN0(0) | PKT_ID1(CMD_EOT) | PKT_LEN1(0) | PKT_LP,
221         0,
222         PKT_ID0(CMD_HS) | PKT_LEN0(0) | PKT_ID1(CMD_BLNK) | PKT_LEN1(2)|
223         PKT_ID2(CMD_RGB) | PKT_LEN2(3) | PKT_LP,
224         PKT_ID0(CMD_EOT) | PKT_LEN0(0),
225         PKT_ID0(CMD_HS) | PKT_LEN0(0) | PKT_ID1(CMD_EOT) | PKT_LEN1(0) | PKT_LP,
226         0,
227         PKT_ID0(CMD_HS) | PKT_LEN0(0) | PKT_ID1(CMD_BLNK) | PKT_LEN1(2)|
228         PKT_ID2(CMD_RGB) | PKT_LEN2(3) | PKT_LP,
229         PKT_ID0(CMD_EOT) | PKT_LEN0(0),
230 };
231
232 /* TODO: verify with hw about this format */
233 const u32 dsi_pkt_seq_cmd_mode[NUMOF_PKT_SEQ] = {
234         0,
235         0,
236         0,
237         0,
238         0,
239         0,
240         PKT_ID0(CMD_LONGW) | PKT_LEN0(3) | PKT_ID1(CMD_EOT) | PKT_LEN1(7),
241         0,
242         0,
243         0,
244         PKT_ID0(CMD_LONGW) | PKT_LEN0(3) | PKT_ID1(CMD_EOT) | PKT_LEN1(7),
245         0,
246 };
247
248 const u32 init_reg[] = {
249         DSI_INT_ENABLE,
250         DSI_INT_STATUS,
251         DSI_INT_MASK,
252         DSI_INIT_SEQ_DATA_0,
253         DSI_INIT_SEQ_DATA_1,
254         DSI_INIT_SEQ_DATA_2,
255         DSI_INIT_SEQ_DATA_3,
256         DSI_INIT_SEQ_DATA_4,
257         DSI_INIT_SEQ_DATA_5,
258         DSI_INIT_SEQ_DATA_6,
259         DSI_INIT_SEQ_DATA_7,
260         DSI_DCS_CMDS,
261         DSI_PKT_SEQ_0_LO,
262         DSI_PKT_SEQ_1_LO,
263         DSI_PKT_SEQ_2_LO,
264         DSI_PKT_SEQ_3_LO,
265         DSI_PKT_SEQ_4_LO,
266         DSI_PKT_SEQ_5_LO,
267         DSI_PKT_SEQ_0_HI,
268         DSI_PKT_SEQ_1_HI,
269         DSI_PKT_SEQ_2_HI,
270         DSI_PKT_SEQ_3_HI,
271         DSI_PKT_SEQ_4_HI,
272         DSI_PKT_SEQ_5_HI,
273         DSI_CONTROL,
274         DSI_HOST_DSI_CONTROL,
275         DSI_PAD_CONTROL,
276         DSI_PAD_CONTROL_CD,
277         DSI_SOL_DELAY,
278         DSI_MAX_THRESHOLD,
279         DSI_TRIGGER,
280         DSI_TX_CRC,
281         DSI_INIT_SEQ_CONTROL,
282         DSI_PKT_LEN_0_1,
283         DSI_PKT_LEN_2_3,
284         DSI_PKT_LEN_4_5,
285         DSI_PKT_LEN_6_7,
286 };
287
288 inline unsigned long tegra_dsi_readl(struct tegra_dc_dsi_data *dsi, u32 reg)
289 {
290         return readl(dsi->base + reg * 4);
291 }
292 EXPORT_SYMBOL(tegra_dsi_readl);
293
294 inline void tegra_dsi_writel(struct tegra_dc_dsi_data *dsi, u32 val, u32 reg)
295 {
296         writel(val, dsi->base + reg * 4);
297 }
298 EXPORT_SYMBOL(tegra_dsi_writel);
299
300 static int tegra_dsi_syncpt(struct tegra_dc_dsi_data *dsi)
301 {
302         u32 val;
303         int ret;
304
305         ret = 0;
306
307         dsi->syncpt_val = nvhost_syncpt_read(
308                         &nvhost_get_host(dsi->dc->ndev)->syncpt,
309                         dsi->syncpt_id);
310
311         val = DSI_INCR_SYNCPT_COND(OP_DONE) |
312                 DSI_INCR_SYNCPT_INDX(dsi->syncpt_id);
313         tegra_dsi_writel(dsi, val, DSI_INCR_SYNCPT);
314
315         /* TODO: Use interrupt rather than polling */
316         ret = nvhost_syncpt_wait(&nvhost_get_host(dsi->dc->ndev)->syncpt,
317                 dsi->syncpt_id, dsi->syncpt_val + 1);
318         if (ret < 0) {
319                 dev_err(&dsi->dc->ndev->dev, "DSI sync point failure\n");
320                 goto fail;
321         }
322
323         (dsi->syncpt_val)++;
324         return 0;
325 fail:
326         return ret;
327 }
328
329 static u32 tegra_dsi_get_hs_clk_rate(struct tegra_dc_dsi_data *dsi)
330 {
331         u32 dsi_clock_rate_khz;
332
333         switch (dsi->info.video_burst_mode) {
334         case TEGRA_DSI_VIDEO_BURST_MODE_LOW_SPEED:
335         case TEGRA_DSI_VIDEO_BURST_MODE_MEDIUM_SPEED:
336         case TEGRA_DSI_VIDEO_BURST_MODE_FAST_SPEED:
337         case TEGRA_DSI_VIDEO_BURST_MODE_FASTEST_SPEED:
338                 /* Calculate DSI HS clock rate for DSI burst mode */
339                 dsi_clock_rate_khz = dsi->default_pixel_clk_khz *
340                                                         dsi->shift_clk_div;
341                 break;
342         case TEGRA_DSI_VIDEO_NONE_BURST_MODE:
343         case TEGRA_DSI_VIDEO_NONE_BURST_MODE_WITH_SYNC_END:
344         case TEGRA_DSI_VIDEO_BURST_MODE_LOWEST_SPEED:
345         default:
346                 /* Clock rate is default DSI clock rate for non-burst mode */
347                 dsi_clock_rate_khz = dsi->default_hs_clk_khz;
348                 break;
349         }
350
351         return dsi_clock_rate_khz;
352 }
353
354 static u32 tegra_dsi_get_lp_clk_rate(struct tegra_dc_dsi_data *dsi, u8 lp_op)
355 {
356         u32 dsi_clock_rate_khz;
357
358         if (dsi->info.enable_hs_clock_on_lp_cmd_mode)
359                 if (dsi->info.hs_clk_in_lp_cmd_mode_freq_khz)
360                         dsi_clock_rate_khz =
361                                 dsi->info.hs_clk_in_lp_cmd_mode_freq_khz;
362                 else
363                         dsi_clock_rate_khz = tegra_dsi_get_hs_clk_rate(dsi);
364         else
365                 if (lp_op == DSI_LP_OP_READ)
366                         dsi_clock_rate_khz =
367                                 dsi->info.lp_read_cmd_mode_freq_khz;
368                 else
369                         dsi_clock_rate_khz =
370                                 dsi->info.lp_cmd_mode_freq_khz;
371
372         return dsi_clock_rate_khz;
373 }
374
375 static u32 tegra_dsi_get_shift_clk_div(struct tegra_dc_dsi_data *dsi)
376 {
377         u32 shift_clk_div;
378         u32 max_shift_clk_div;
379         u32 burst_width;
380         u32 burst_width_max;
381
382         /* Get the real value of default shift_clk_div. default_shift_clk_div
383          * holds the real value of shift_clk_div.
384          */
385         shift_clk_div = dsi->default_shift_clk_div;
386
387         /* Calculate shift_clk_div which can matche the video_burst_mode. */
388         if (dsi->info.video_burst_mode >=
389                         TEGRA_DSI_VIDEO_BURST_MODE_LOWEST_SPEED) {
390                 /* The max_shift_clk_div is multiplied by 10 to save the
391                  * fraction
392                  */
393                 if (dsi->info.max_panel_freq_khz >= dsi->default_hs_clk_khz)
394                         max_shift_clk_div = dsi->info.max_panel_freq_khz
395                                 * shift_clk_div * 10 / dsi->default_hs_clk_khz;
396                 else
397                         max_shift_clk_div = shift_clk_div * 10;
398
399                 burst_width = dsi->info.video_burst_mode
400                                 - TEGRA_DSI_VIDEO_BURST_MODE_LOWEST_SPEED;
401                 burst_width_max = TEGRA_DSI_VIDEO_BURST_MODE_FASTEST_SPEED
402                                 - TEGRA_DSI_VIDEO_BURST_MODE_LOWEST_SPEED;
403
404                 shift_clk_div = (max_shift_clk_div - shift_clk_div * 10) *
405                         burst_width / (burst_width_max * 10) + shift_clk_div;
406         }
407
408         return shift_clk_div;
409 }
410
411 static void tegra_dsi_init_sw(struct tegra_dc *dc,
412                         struct tegra_dc_dsi_data *dsi)
413 {
414         u32 h_width_pixels;
415         u32 v_width_lines;
416         u32 pixel_clk_hz;
417         u32 byte_clk_hz;
418         u32 plld_clk_mhz;
419
420         switch (dsi->info.pixel_format) {
421         case TEGRA_DSI_PIXEL_FORMAT_16BIT_P:
422                 /* 2 bytes per pixel */
423                 dsi->pixel_scaler_mul = 2;
424                 dsi->pixel_scaler_div = 1;
425                 break;
426         case TEGRA_DSI_PIXEL_FORMAT_18BIT_P:
427                 /* 2.25 bytes per pixel */
428                 dsi->pixel_scaler_mul = 9;
429                 dsi->pixel_scaler_div = 4;
430                 break;
431         case TEGRA_DSI_PIXEL_FORMAT_18BIT_NP:
432         case TEGRA_DSI_PIXEL_FORMAT_24BIT_P:
433                 /* 3 bytes per pixel */
434                 dsi->pixel_scaler_mul = 3;
435                 dsi->pixel_scaler_div = 1;
436                 break;
437         default:
438                 break;
439         }
440
441         dsi->controller_index = dc->ndev->id;
442         dsi->ulpm = false;
443         dsi->enabled = false;
444         dsi->clk_ref = false;
445
446         dsi->dsi_control_val =
447                         DSI_CONTROL_VIRTUAL_CHANNEL(dsi->info.virtual_channel) |
448                         DSI_CONTROL_NUM_DATA_LANES(dsi->info.n_data_lanes - 1) |
449                         DSI_CONTROL_VID_SOURCE(dsi->controller_index) |
450                         DSI_CONTROL_DATA_FORMAT(dsi->info.pixel_format);
451
452         /* Below we are going to calculate dsi and dc clock rate.
453          * Calcuate the horizontal and vertical width.
454          */
455         h_width_pixels = dc->mode.h_back_porch + dc->mode.h_front_porch +
456                         dc->mode.h_sync_width + dc->mode.h_active;
457         v_width_lines = dc->mode.v_back_porch + dc->mode.v_front_porch +
458                         dc->mode.v_sync_width + dc->mode.v_active;
459
460         /* Calculate minimum required pixel rate. */
461         pixel_clk_hz = h_width_pixels * v_width_lines * dsi->info.refresh_rate;
462
463         /* Calculate minimum byte rate on DSI interface. */
464         byte_clk_hz = (pixel_clk_hz * dsi->pixel_scaler_mul) /
465                         (dsi->pixel_scaler_div * dsi->info.n_data_lanes);
466
467         /* Round up to multiple of mega hz. */
468         plld_clk_mhz = DIV_ROUND_UP((byte_clk_hz * NUMOF_BIT_PER_BYTE),
469                                                                 1000000);
470
471         /* Calculate default real shift_clk_div. */
472         dsi->default_shift_clk_div = (NUMOF_BIT_PER_BYTE / 2) *
473                 dsi->pixel_scaler_mul / (dsi->pixel_scaler_div *
474                 dsi->info.n_data_lanes);
475         /* Calculate default DSI hs clock. DSI interface is double data rate.
476          * Data is transferred on both rising and falling edge of clk, div by 2
477          * to get the actual clock rate.
478          */
479         dsi->default_hs_clk_khz = plld_clk_mhz * 1000 / 2;
480         dsi->default_pixel_clk_khz = plld_clk_mhz * 1000 / 2
481                                                 / dsi->default_shift_clk_div;
482
483         /* Get the actual shift_clk_div and clock rates. */
484         dsi->shift_clk_div = tegra_dsi_get_shift_clk_div(dsi);
485         dsi->target_lp_clk_khz =
486                         tegra_dsi_get_lp_clk_rate(dsi, DSI_LP_OP_WRITE);
487         dsi->target_hs_clk_khz = tegra_dsi_get_hs_clk_rate(dsi);
488
489         dev_info(&dc->ndev->dev, "DSI: HS clock rate is %d\n",
490                                                         dsi->target_hs_clk_khz);
491
492         dsi->controller_index = dc->ndev->id;
493
494 #if DSI_USE_SYNC_POINTS
495         dsi->syncpt_id = NVSYNCPT_DSI;
496 #endif
497
498         /*
499          * Force video clock to be continuous mode if
500          * enable_hs_clock_on_lp_cmd_mode is set
501          */
502         if (dsi->info.enable_hs_clock_on_lp_cmd_mode) {
503                 if (dsi->info.video_clock_mode !=
504                                         TEGRA_DSI_VIDEO_CLOCK_CONTINUOUS)
505                         dev_warn(&dc->ndev->dev,
506                                 "Force clock continuous mode\n");
507
508                 dsi->info.video_clock_mode = TEGRA_DSI_VIDEO_CLOCK_CONTINUOUS;
509         }
510
511 }
512
513 #define SELECT_T_PHY(platform_t_phy_ns, default_phy, clk_ns) ( \
514         (platform_t_phy_ns) ? ( \
515         ((DSI_CONVERT_T_PHY_NS_TO_T_PHY(platform_t_phy_ns, clk_ns)) < 0 ? 0 : \
516         (DSI_CONVERT_T_PHY_NS_TO_T_PHY(platform_t_phy_ns, clk_ns)))) : \
517         ((default_phy) < 0 ? 0 : (default_phy)))
518
519 static void tegra_dsi_get_clk_phy_timing(struct tegra_dc_dsi_data *dsi,
520                 struct dsi_phy_timing_inclk *phy_timing_clk, u32 clk_ns)
521 {
522         phy_timing_clk->t_tlpx = SELECT_T_PHY(
523                 dsi->info.phy_timing.t_tlpx_ns,
524                 T_TLPX_DEFAULT(clk_ns), clk_ns);
525
526         phy_timing_clk->t_clktrail = SELECT_T_PHY(
527                 dsi->info.phy_timing.t_clktrail_ns,
528                 T_CLKTRAIL_DEFAULT(clk_ns), clk_ns);
529
530         phy_timing_clk->t_clkpost = SELECT_T_PHY(
531                 dsi->info.phy_timing.t_clkpost_ns,
532                 T_CLKPOST_DEFAULT(clk_ns), clk_ns);
533
534         phy_timing_clk->t_clkzero = SELECT_T_PHY(
535                 dsi->info.phy_timing.t_clkzero_ns,
536                 T_CLKZERO_DEFAULT(clk_ns), clk_ns);
537
538         phy_timing_clk->t_clkprepare = SELECT_T_PHY(
539                 dsi->info.phy_timing.t_clkprepare_ns,
540                 T_CLKPREPARE_DEFAULT(clk_ns), clk_ns);
541
542         phy_timing_clk->t_clkpre = SELECT_T_PHY(
543                 dsi->info.phy_timing.t_clkpre_ns,
544                 T_CLKPRE_DEFAULT, clk_ns);
545 }
546
547 static void tegra_dsi_get_hs_phy_timing(struct tegra_dc_dsi_data *dsi,
548                 struct dsi_phy_timing_inclk *phy_timing_clk, u32 clk_ns)
549 {
550         phy_timing_clk->t_tlpx = SELECT_T_PHY(
551                 dsi->info.phy_timing.t_tlpx_ns,
552                 T_TLPX_DEFAULT(clk_ns), clk_ns);
553
554         phy_timing_clk->t_hsdexit = SELECT_T_PHY(
555                 dsi->info.phy_timing.t_hsdexit_ns,
556                 T_HSEXIT_DEFAULT(clk_ns), clk_ns);
557
558         phy_timing_clk->t_hstrail = SELECT_T_PHY(
559                 dsi->info.phy_timing.t_hstrail_ns,
560                 T_HSTRAIL_DEFAULT(clk_ns), clk_ns);
561
562         phy_timing_clk->t_datzero = SELECT_T_PHY(
563                 dsi->info.phy_timing.t_datzero_ns,
564                 T_DATZERO_DEFAULT(clk_ns), clk_ns);
565
566         phy_timing_clk->t_hsprepare = SELECT_T_PHY(
567                 dsi->info.phy_timing.t_hsprepare_ns,
568                 T_HSPREPARE_DEFAULT(clk_ns), clk_ns);
569 }
570
571 static void tegra_dsi_get_escape_phy_timing(struct tegra_dc_dsi_data *dsi,
572                 struct dsi_phy_timing_inclk *phy_timing_clk, u32 clk_ns)
573 {
574         phy_timing_clk->t_tlpx = SELECT_T_PHY(
575                 dsi->info.phy_timing.t_tlpx_ns,
576                 T_TLPX_DEFAULT(clk_ns), clk_ns);
577 }
578
579 static void tegra_dsi_get_bta_phy_timing(struct tegra_dc_dsi_data *dsi,
580                 struct dsi_phy_timing_inclk *phy_timing_clk, u32 clk_ns)
581 {
582         phy_timing_clk->t_tlpx = SELECT_T_PHY(
583                 dsi->info.phy_timing.t_tlpx_ns,
584                 T_TLPX_DEFAULT(clk_ns), clk_ns);
585
586         phy_timing_clk->t_taget = SELECT_T_PHY(
587                 dsi->info.phy_timing.t_taget_ns,
588                 T_TAGET_DEFAULT(clk_ns), clk_ns);
589
590         phy_timing_clk->t_tasure = SELECT_T_PHY(
591                 dsi->info.phy_timing.t_tasure_ns,
592                 T_TASURE_DEFAULT(clk_ns), clk_ns);
593
594         phy_timing_clk->t_tago = SELECT_T_PHY(
595                 dsi->info.phy_timing.t_tago_ns,
596                 T_TAGO_DEFAULT(clk_ns), clk_ns);
597 }
598
599 static void tegra_dsi_get_ulps_phy_timing(struct tegra_dc_dsi_data *dsi,
600                 struct dsi_phy_timing_inclk *phy_timing_clk, u32 clk_ns)
601 {
602         phy_timing_clk->t_tlpx = SELECT_T_PHY(
603                 dsi->info.phy_timing.t_tlpx_ns,
604                 T_TLPX_DEFAULT(clk_ns), clk_ns);
605
606         phy_timing_clk->t_wakeup = SELECT_T_PHY(
607                 dsi->info.phy_timing.t_wakeup_ns,
608                 T_WAKEUP_DEFAULT, clk_ns);
609 }
610
611 #undef SELECT_T_PHY
612
613 static void tegra_dsi_get_phy_timing(struct tegra_dc_dsi_data *dsi,
614                                 struct dsi_phy_timing_inclk *phy_timing_clk,
615                                 u32 clk_ns, u8 lphs)
616 {
617         if (lphs == DSI_LPHS_IN_HS_MODE) {
618                 tegra_dsi_get_clk_phy_timing(dsi, phy_timing_clk, clk_ns);
619                 tegra_dsi_get_hs_phy_timing(dsi, phy_timing_clk, clk_ns);
620         } else {
621                 /* default is LP mode */
622                 tegra_dsi_get_escape_phy_timing(dsi, phy_timing_clk, clk_ns);
623                 tegra_dsi_get_bta_phy_timing(dsi, phy_timing_clk, clk_ns);
624                 tegra_dsi_get_ulps_phy_timing(dsi, phy_timing_clk, clk_ns);
625                 if (dsi->info.enable_hs_clock_on_lp_cmd_mode)
626                         tegra_dsi_get_clk_phy_timing
627                                 (dsi, phy_timing_clk, clk_ns);
628         }
629 }
630
631 static int tegra_dsi_mipi_phy_timing_range(struct tegra_dc_dsi_data *dsi,
632                                 struct dsi_phy_timing_inclk *phy_timing,
633                                 u32 clk_ns, u8 lphs)
634 {
635 #define CHECK_RANGE(val, min, max) ( \
636                 ((min) == NOT_DEFINED ? 0 : (val) < (min)) || \
637                 ((max) == NOT_DEFINED ? 0 : (val) > (max)) ? -EINVAL : 0)
638
639         int err = 0;
640
641         err = CHECK_RANGE(
642         DSI_CONVERT_T_PHY_TO_T_PHY_NS(phy_timing->t_tlpx, clk_ns),
643                         MIPI_T_TLPX_NS_MIN, MIPI_T_TLPX_NS_MAX);
644         if (err < 0) {
645                 dev_warn(&dsi->dc->ndev->dev,
646                         "dsi: Tlpx mipi range violated\n");
647                 goto fail;
648         }
649
650         if (lphs == DSI_LPHS_IN_HS_MODE) {
651                 err = CHECK_RANGE(
652                 DSI_CONVERT_T_PHY_TO_T_PHY_NS(phy_timing->t_hsdexit, clk_ns),
653                                 MIPI_T_HSEXIT_NS_MIN, MIPI_T_HSEXIT_NS_MAX);
654                 if (err < 0) {
655                         dev_warn(&dsi->dc->ndev->dev,
656                                 "dsi: HsExit mipi range violated\n");
657                         goto fail;
658                 }
659
660                 err = CHECK_RANGE(
661                 DSI_CONVERT_T_PHY_TO_T_PHY_NS(phy_timing->t_hstrail, clk_ns),
662                         MIPI_T_HSTRAIL_NS_MIN(clk_ns), MIPI_T_HSTRAIL_NS_MAX);
663                 if (err < 0) {
664                         dev_warn(&dsi->dc->ndev->dev,
665                                 "dsi: HsTrail mipi range violated\n");
666                         goto fail;
667                 }
668
669                 err = CHECK_RANGE(
670                 DSI_CONVERT_T_PHY_TO_T_PHY_NS(phy_timing->t_datzero, clk_ns),
671                                 MIPI_T_HSZERO_NS_MIN, MIPI_T_HSZERO_NS_MAX);
672                 if (err < 0) {
673                         dev_warn(&dsi->dc->ndev->dev,
674                                 "dsi: HsZero mipi range violated\n");
675                         goto fail;
676                 }
677
678                 err = CHECK_RANGE(
679                 DSI_CONVERT_T_PHY_TO_T_PHY_NS(phy_timing->t_hsprepare, clk_ns),
680                                         MIPI_T_HSPREPARE_NS_MIN(clk_ns),
681                                         MIPI_T_HSPREPARE_NS_MAX(clk_ns));
682                 if (err < 0) {
683                         dev_warn(&dsi->dc->ndev->dev,
684                                 "dsi: HsPrepare mipi range violated\n");
685                         goto fail;
686                 }
687
688                 err = CHECK_RANGE(
689                 DSI_CONVERT_T_PHY_TO_T_PHY_NS(
690                 phy_timing->t_hsprepare, clk_ns) +
691                 DSI_CONVERT_T_PHY_TO_T_PHY_NS(phy_timing->t_datzero, clk_ns),
692                         MIPI_T_HSPREPARE_ADD_HSZERO_NS_MIN(clk_ns),
693                         MIPI_T_HSPREPARE_ADD_HSZERO_NS_MAX);
694                 if (err < 0) {
695                         dev_warn(&dsi->dc->ndev->dev,
696                         "dsi: HsPrepare + HsZero mipi range violated\n");
697                         goto fail;
698                 }
699         } else {
700                 /* default is LP mode */
701                 err = CHECK_RANGE(
702                 DSI_CONVERT_T_PHY_TO_T_PHY_NS(phy_timing->t_wakeup, clk_ns),
703                         MIPI_T_WAKEUP_NS_MIN, MIPI_T_WAKEUP_NS_MAX);
704                 if (err < 0) {
705                         dev_warn(&dsi->dc->ndev->dev,
706                                 "dsi: WakeUp mipi range violated\n");
707                         goto fail;
708                 }
709
710                 err = CHECK_RANGE(
711                 DSI_CONVERT_T_PHY_TO_T_PHY_NS(phy_timing->t_tasure, clk_ns),
712                         MIPI_T_TASURE_NS_MIN(DSI_CONVERT_T_PHY_TO_T_PHY_NS(
713                         phy_timing->t_tlpx, clk_ns)),
714                         MIPI_T_TASURE_NS_MAX(DSI_CONVERT_T_PHY_TO_T_PHY_NS(
715                         phy_timing->t_tlpx, clk_ns)));
716                 if (err < 0) {
717                         dev_warn(&dsi->dc->ndev->dev,
718                                 "dsi: TaSure mipi range violated\n");
719                         goto fail;
720                 }
721         }
722
723         if (lphs == DSI_LPHS_IN_HS_MODE ||
724                 dsi->info.enable_hs_clock_on_lp_cmd_mode) {
725                 err = CHECK_RANGE(
726                 DSI_CONVERT_T_PHY_TO_T_PHY_NS(phy_timing->t_clktrail, clk_ns),
727                         MIPI_T_CLKTRAIL_NS_MIN, MIPI_T_CLKTRAIL_NS_MAX);
728                 if (err < 0) {
729                         dev_warn(&dsi->dc->ndev->dev,
730                                 "dsi: ClkTrail mipi range violated\n");
731                         goto fail;
732                 }
733
734                 err = CHECK_RANGE(
735                 DSI_CONVERT_T_PHY_TO_T_PHY_NS(phy_timing->t_clkpost, clk_ns),
736                         MIPI_T_CLKPOST_NS_MIN(clk_ns), MIPI_T_CLKPOST_NS_MAX);
737                 if (err < 0) {
738                         dev_warn(&dsi->dc->ndev->dev,
739                                 "dsi: ClkPost mipi range violated\n");
740                         goto fail;
741                 }
742
743                 err = CHECK_RANGE(
744                 DSI_CONVERT_T_PHY_TO_T_PHY_NS(phy_timing->t_clkzero, clk_ns),
745                                 MIPI_T_CLKZERO_NS_MIN, MIPI_T_CLKZERO_NS_MAX);
746                 if (err < 0) {
747                         dev_warn(&dsi->dc->ndev->dev,
748                                 "dsi: ClkZero mipi range violated\n");
749                         goto fail;
750                 }
751
752                 err = CHECK_RANGE(
753                 DSI_CONVERT_T_PHY_TO_T_PHY_NS
754                         (phy_timing->t_clkprepare, clk_ns),
755                         MIPI_T_CLKPREPARE_NS_MIN, MIPI_T_CLKPREPARE_NS_MAX);
756                 if (err < 0) {
757                         dev_warn(&dsi->dc->ndev->dev,
758                                 "dsi: ClkPrepare mipi range violated\n");
759                         goto fail;
760                 }
761
762                 err = CHECK_RANGE(
763                 DSI_CONVERT_T_PHY_TO_T_PHY_NS(phy_timing->t_clkpre, clk_ns),
764                         MIPI_T_CLKPRE_NS_MIN, MIPI_T_CLKPRE_NS_MAX);
765                 if (err < 0) {
766                         dev_warn(&dsi->dc->ndev->dev,
767                                 "dsi: ClkPre mipi range violated\n");
768                         goto fail;
769                 }
770
771                 err = CHECK_RANGE(
772                 DSI_CONVERT_T_PHY_TO_T_PHY_NS(
773                 phy_timing->t_clkprepare, clk_ns) +
774                 DSI_CONVERT_T_PHY_TO_T_PHY_NS(phy_timing->t_clkzero, clk_ns),
775                         MIPI_T_CLKPREPARE_ADD_CLKZERO_NS_MIN,
776                         MIPI_T_CLKPREPARE_ADD_CLKZERO_NS_MAX);
777                 if (err < 0) {
778                         dev_warn(&dsi->dc->ndev->dev,
779                         "dsi: ClkPrepare + ClkZero mipi range violated\n");
780                         goto fail;
781                 }
782         }
783 fail:
784 #undef CHECK_RANGE
785         return err;
786 }
787
788 static int tegra_dsi_constraint_phy_timing(struct tegra_dc_dsi_data *dsi,
789                                 struct dsi_phy_timing_inclk *phy_timing,
790                                 u32 clk_ns, u8 lphs)
791 {
792         int err = 0;
793
794         err = tegra_dsi_mipi_phy_timing_range(dsi, phy_timing, clk_ns, lphs);
795         if (err < 0) {
796                 dev_warn(&dsi->dc->ndev->dev, "dsi: mipi range violated\n");
797                 goto fail;
798         }
799
800         /* TODO: add more contraints */
801 fail:
802         return err;
803 }
804
805 static void tegra_dsi_set_phy_timing(struct tegra_dc_dsi_data *dsi, u8 lphs)
806 {
807         u32 val;
808         struct dsi_phy_timing_inclk phy_timing = dsi->phy_timing;
809
810         tegra_dsi_get_phy_timing
811                 (dsi, &phy_timing, dsi->current_bit_clk_ns, lphs);
812
813         tegra_dsi_constraint_phy_timing(dsi, &phy_timing,
814                                         dsi->current_bit_clk_ns, lphs);
815
816         val = DSI_PHY_TIMING_0_THSDEXIT(phy_timing.t_hsdexit) |
817                         DSI_PHY_TIMING_0_THSTRAIL(phy_timing.t_hstrail) |
818                         DSI_PHY_TIMING_0_TDATZERO(phy_timing.t_datzero) |
819                         DSI_PHY_TIMING_0_THSPREPR(phy_timing.t_hsprepare);
820         tegra_dsi_writel(dsi, val, DSI_PHY_TIMING_0);
821
822         val = DSI_PHY_TIMING_1_TCLKTRAIL(phy_timing.t_clktrail) |
823                         DSI_PHY_TIMING_1_TCLKPOST(phy_timing.t_clkpost) |
824                         DSI_PHY_TIMING_1_TCLKZERO(phy_timing.t_clkzero) |
825                         DSI_PHY_TIMING_1_TTLPX(phy_timing.t_tlpx);
826         tegra_dsi_writel(dsi, val, DSI_PHY_TIMING_1);
827
828         val = DSI_PHY_TIMING_2_TCLKPREPARE(phy_timing.t_clkprepare) |
829                 DSI_PHY_TIMING_2_TCLKPRE(phy_timing.t_clkpre) |
830                         DSI_PHY_TIMING_2_TWAKEUP(phy_timing.t_wakeup);
831         tegra_dsi_writel(dsi, val, DSI_PHY_TIMING_2);
832
833         val = DSI_BTA_TIMING_TTAGET(phy_timing.t_taget) |
834                         DSI_BTA_TIMING_TTASURE(phy_timing.t_tasure) |
835                         DSI_BTA_TIMING_TTAGO(phy_timing.t_tago);
836         tegra_dsi_writel(dsi, val, DSI_BTA_TIMING);
837
838         dsi->phy_timing = phy_timing;
839 }
840
841 static u32 tegra_dsi_sol_delay_burst(struct tegra_dc *dc,
842                                 struct tegra_dc_dsi_data *dsi)
843 {
844         u32 dsi_to_pixel_clk_ratio;
845         u32 temp;
846         u32 temp1;
847         u32 mipi_clk_adj_kHz;
848         u32 sol_delay;
849         struct tegra_dc_mode *dc_modes = &dc->mode;
850
851         /* Get Fdsi/Fpixel ration (note: Fdsi is in bit format) */
852         dsi_to_pixel_clk_ratio = (dsi->current_dsi_clk_khz * 2 +
853                 dsi->default_pixel_clk_khz - 1) / dsi->default_pixel_clk_khz;
854
855         /* Convert Fdsi to byte format */
856         dsi_to_pixel_clk_ratio *= 1000/8;
857
858         /* Multiplying by 1000 so that we don't loose the fraction part */
859         temp = dc_modes->h_active * 1000;
860         temp1 = dc_modes->h_active + dc_modes->h_back_porch +
861                         dc_modes->h_sync_width;
862
863         sol_delay = temp1 * dsi_to_pixel_clk_ratio -
864                         temp * dsi->pixel_scaler_mul /
865                         (dsi->pixel_scaler_div * dsi->info.n_data_lanes);
866
867         /* Do rounding on sol delay */
868         sol_delay = (sol_delay + 1000 - 1)/1000;
869
870         /* TODO:
871          * 1. find out the correct sol fifo depth to use
872          * 2. verify with hw about the clamping function
873          */
874         if (sol_delay > (480 * 4)) {
875                 sol_delay = (480 * 4);
876                 mipi_clk_adj_kHz = sol_delay +
877                         (dc_modes->h_active * dsi->pixel_scaler_mul) /
878                         (dsi->info.n_data_lanes * dsi->pixel_scaler_div);
879
880                 mipi_clk_adj_kHz *= (dsi->default_pixel_clk_khz / temp1);
881
882                 mipi_clk_adj_kHz *= 4;
883         }
884
885         dsi->target_hs_clk_khz = mipi_clk_adj_kHz;
886
887         return sol_delay;
888 }
889
890 static void tegra_dsi_set_sol_delay(struct tegra_dc *dc,
891                                 struct tegra_dc_dsi_data *dsi)
892 {
893         u32 sol_delay;
894
895         if (dsi->info.video_burst_mode == TEGRA_DSI_VIDEO_NONE_BURST_MODE ||
896                 dsi->info.video_burst_mode ==
897                                 TEGRA_DSI_VIDEO_NONE_BURST_MODE_WITH_SYNC_END) {
898                 sol_delay = NUMOF_BIT_PER_BYTE * dsi->pixel_scaler_mul /
899                         (dsi->pixel_scaler_div * dsi->info.n_data_lanes);
900                 dsi->status.clk_burst = DSI_CLK_BURST_NONE_BURST;
901         } else {
902                 sol_delay = tegra_dsi_sol_delay_burst(dc, dsi);
903                 dsi->status.clk_burst = DSI_CLK_BURST_BURST_MODE;
904         }
905
906         tegra_dsi_writel(dsi, DSI_SOL_DELAY_SOL_DELAY(sol_delay),
907                                                                 DSI_SOL_DELAY);
908 }
909
910 static void tegra_dsi_set_timeout(struct tegra_dc_dsi_data *dsi)
911 {
912         u32 val;
913         u32 bytes_per_frame;
914         u32 timeout = 0;
915
916         /* TODO: verify the following equation */
917         bytes_per_frame = dsi->current_dsi_clk_khz * 1000 * 2 /
918                                                 (dsi->info.refresh_rate * 8);
919         timeout = bytes_per_frame / DSI_CYCLE_COUNTER_VALUE;
920         timeout = (timeout + DSI_HTX_TO_MARGIN) & 0xffff;
921
922         val = DSI_TIMEOUT_0_LRXH_TO(DSI_LRXH_TO_VALUE) |
923                         DSI_TIMEOUT_0_HTX_TO(timeout);
924         tegra_dsi_writel(dsi, val, DSI_TIMEOUT_0);
925
926         if (dsi->info.panel_reset_timeout_msec)
927                 timeout = (dsi->info.panel_reset_timeout_msec * 1000*1000)
928                                         / dsi->current_bit_clk_ns;
929         else
930                 timeout = DSI_PR_TO_VALUE;
931
932         val = DSI_TIMEOUT_1_PR_TO(timeout) |
933                 DSI_TIMEOUT_1_TA_TO(DSI_TA_TO_VALUE);
934         tegra_dsi_writel(dsi, val, DSI_TIMEOUT_1);
935
936         val = DSI_TO_TALLY_P_RESET_STATUS(IN_RESET) |
937                 DSI_TO_TALLY_TA_TALLY(DSI_TA_TALLY_VALUE)|
938                 DSI_TO_TALLY_LRXH_TALLY(DSI_LRXH_TALLY_VALUE)|
939                 DSI_TO_TALLY_HTX_TALLY(DSI_HTX_TALLY_VALUE);
940         tegra_dsi_writel(dsi, val, DSI_TO_TALLY);
941 }
942
943 static void tegra_dsi_setup_video_mode_pkt_length(struct tegra_dc *dc,
944                                                 struct tegra_dc_dsi_data *dsi)
945 {
946         u32 val;
947         u32 hact_pkt_len;
948         u32 hsa_pkt_len;
949         u32 hbp_pkt_len;
950         u32 hfp_pkt_len;
951
952         hact_pkt_len = dc->mode.h_active * dsi->pixel_scaler_mul /
953                                                         dsi->pixel_scaler_div;
954         hsa_pkt_len = dc->mode.h_sync_width * dsi->pixel_scaler_mul /
955                                                         dsi->pixel_scaler_div;
956         hbp_pkt_len = dc->mode.h_back_porch * dsi->pixel_scaler_mul /
957                                                         dsi->pixel_scaler_div;
958         hfp_pkt_len = dc->mode.h_front_porch * dsi->pixel_scaler_mul /
959                                                         dsi->pixel_scaler_div;
960
961         if (dsi->info.video_burst_mode !=
962                                 TEGRA_DSI_VIDEO_NONE_BURST_MODE_WITH_SYNC_END)
963                 hbp_pkt_len += hsa_pkt_len;
964
965         hsa_pkt_len -= DSI_HSYNC_BLNK_PKT_OVERHEAD;
966         hbp_pkt_len -= DSI_HBACK_PORCH_PKT_OVERHEAD;
967         hfp_pkt_len -= DSI_HFRONT_PORCH_PKT_OVERHEAD;
968
969         val = DSI_PKT_LEN_0_1_LENGTH_0(0) |
970                         DSI_PKT_LEN_0_1_LENGTH_1(hsa_pkt_len);
971         tegra_dsi_writel(dsi, val, DSI_PKT_LEN_0_1);
972
973         val = DSI_PKT_LEN_2_3_LENGTH_2(hbp_pkt_len) |
974                         DSI_PKT_LEN_2_3_LENGTH_3(hact_pkt_len);
975         tegra_dsi_writel(dsi, val, DSI_PKT_LEN_2_3);
976
977         val = DSI_PKT_LEN_4_5_LENGTH_4(hfp_pkt_len) |
978                         DSI_PKT_LEN_4_5_LENGTH_5(0);
979         tegra_dsi_writel(dsi, val, DSI_PKT_LEN_4_5);
980
981         val = DSI_PKT_LEN_6_7_LENGTH_6(0) | DSI_PKT_LEN_6_7_LENGTH_7(0);
982         tegra_dsi_writel(dsi, val, DSI_PKT_LEN_6_7);
983 }
984
985 static void tegra_dsi_setup_cmd_mode_pkt_length(struct tegra_dc *dc,
986                                                 struct tegra_dc_dsi_data *dsi)
987 {
988         unsigned long   val;
989         unsigned long   act_bytes;
990
991         act_bytes = dc->mode.h_active * dsi->pixel_scaler_mul /
992                         dsi->pixel_scaler_div + 1;
993
994         val = DSI_PKT_LEN_0_1_LENGTH_0(0) | DSI_PKT_LEN_0_1_LENGTH_1(0);
995         tegra_dsi_writel(dsi, val, DSI_PKT_LEN_0_1);
996
997         val = DSI_PKT_LEN_2_3_LENGTH_2(0) | DSI_PKT_LEN_2_3_LENGTH_3(act_bytes);
998         tegra_dsi_writel(dsi, val, DSI_PKT_LEN_2_3);
999
1000         val = DSI_PKT_LEN_4_5_LENGTH_4(0) | DSI_PKT_LEN_4_5_LENGTH_5(act_bytes);
1001         tegra_dsi_writel(dsi, val, DSI_PKT_LEN_4_5);
1002
1003         val = DSI_PKT_LEN_6_7_LENGTH_6(0) | DSI_PKT_LEN_6_7_LENGTH_7(0x0f0f);
1004         tegra_dsi_writel(dsi, val, DSI_PKT_LEN_6_7);
1005 }
1006
1007 static void tegra_dsi_set_pkt_length(struct tegra_dc *dc,
1008                                 struct tegra_dc_dsi_data *dsi)
1009 {
1010         if (dsi->driven_mode == TEGRA_DSI_DRIVEN_BY_HOST)
1011                 return;
1012
1013         if (dsi->info.video_data_type == TEGRA_DSI_VIDEO_TYPE_VIDEO_MODE)
1014                 tegra_dsi_setup_video_mode_pkt_length(dc, dsi);
1015         else
1016                 tegra_dsi_setup_cmd_mode_pkt_length(dc, dsi);
1017 }
1018
1019 static void tegra_dsi_set_pkt_seq(struct tegra_dc *dc,
1020                                 struct tegra_dc_dsi_data *dsi)
1021 {
1022         const u32 *pkt_seq;
1023         u32 rgb_info;
1024         u32 pkt_seq_3_5_rgb_lo;
1025         u32 pkt_seq_3_5_rgb_hi;
1026         u32     val;
1027         u32 reg;
1028         u8  i;
1029
1030         if (dsi->driven_mode == TEGRA_DSI_DRIVEN_BY_HOST)
1031                 return;
1032
1033         switch (dsi->info.pixel_format) {
1034         case TEGRA_DSI_PIXEL_FORMAT_16BIT_P:
1035                 rgb_info = CMD_RGB_16BPP;
1036                 break;
1037         case TEGRA_DSI_PIXEL_FORMAT_18BIT_P:
1038                 rgb_info = CMD_RGB_18BPP;
1039                 break;
1040         case TEGRA_DSI_PIXEL_FORMAT_18BIT_NP:
1041                 rgb_info = CMD_RGB_18BPPNP;
1042                 break;
1043         case TEGRA_DSI_PIXEL_FORMAT_24BIT_P:
1044         default:
1045                 rgb_info = CMD_RGB_24BPP;
1046                 break;
1047         }
1048
1049         pkt_seq_3_5_rgb_lo = 0;
1050         pkt_seq_3_5_rgb_hi = 0;
1051         if (dsi->info.video_data_type == TEGRA_DSI_VIDEO_TYPE_COMMAND_MODE)
1052                 pkt_seq = dsi_pkt_seq_cmd_mode;
1053         else {
1054                 switch (dsi->info.video_burst_mode) {
1055                 case TEGRA_DSI_VIDEO_BURST_MODE_LOWEST_SPEED:
1056                 case TEGRA_DSI_VIDEO_BURST_MODE_LOW_SPEED:
1057                 case TEGRA_DSI_VIDEO_BURST_MODE_MEDIUM_SPEED:
1058                 case TEGRA_DSI_VIDEO_BURST_MODE_FAST_SPEED:
1059                 case TEGRA_DSI_VIDEO_BURST_MODE_FASTEST_SPEED:
1060                         pkt_seq_3_5_rgb_lo =
1061                                         DSI_PKT_SEQ_3_LO_PKT_32_ID(rgb_info);
1062                         if (!dsi->info.no_pkt_seq_eot)
1063                                 pkt_seq = dsi_pkt_seq_video_burst;
1064                         else
1065                                 pkt_seq = dsi_pkt_seq_video_burst_no_eot;
1066                         break;
1067                 case TEGRA_DSI_VIDEO_NONE_BURST_MODE_WITH_SYNC_END:
1068                         pkt_seq_3_5_rgb_hi =
1069                                         DSI_PKT_SEQ_3_HI_PKT_34_ID(rgb_info);
1070                         pkt_seq = dsi_pkt_seq_video_non_burst_syne;
1071                         break;
1072                 case TEGRA_DSI_VIDEO_NONE_BURST_MODE:
1073                 default:
1074                         pkt_seq_3_5_rgb_lo =
1075                                         DSI_PKT_SEQ_3_LO_PKT_32_ID(rgb_info);
1076                         pkt_seq = dsi_pkt_seq_video_non_burst;
1077                         break;
1078                 }
1079         }
1080
1081         for (i = 0; i < NUMOF_PKT_SEQ; i++) {
1082                 val = pkt_seq[i];
1083                 reg = dsi_pkt_seq_reg[i];
1084                 if ((reg == DSI_PKT_SEQ_3_LO) || (reg == DSI_PKT_SEQ_5_LO))
1085                         val |= pkt_seq_3_5_rgb_lo;
1086                 if ((reg == DSI_PKT_SEQ_3_HI) || (reg == DSI_PKT_SEQ_5_HI))
1087                         val |= pkt_seq_3_5_rgb_hi;
1088                 tegra_dsi_writel(dsi, val, reg);
1089         }
1090 }
1091
1092 static void tegra_dsi_stop_dc_stream(struct tegra_dc *dc,
1093                                         struct tegra_dc_dsi_data *dsi)
1094 {
1095         tegra_dc_writel(dc, DISP_CTRL_MODE_STOP, DC_CMD_DISPLAY_COMMAND);
1096         tegra_dc_writel(dc, 0, DC_DISP_DISP_WIN_OPTIONS);
1097         tegra_dc_writel(dc, GENERAL_UPDATE, DC_CMD_STATE_CONTROL);
1098         tegra_dc_writel(dc, GENERAL_ACT_REQ , DC_CMD_STATE_CONTROL);
1099
1100         dsi->status.dc_stream = DSI_DC_STREAM_DISABLE;
1101 }
1102
1103 static void tegra_dsi_stop_dc_stream_at_frame_end(struct tegra_dc *dc,
1104                                                 struct tegra_dc_dsi_data *dsi)
1105 {
1106         int val;
1107         long timeout;
1108         u32 frame_period = DIV_ROUND_UP(S_TO_MS(1), dsi->info.refresh_rate);
1109
1110         /* stop dc */
1111         tegra_dsi_stop_dc_stream(dc, dsi);
1112
1113         /* enable frame end interrupt */
1114         val = tegra_dc_readl(dc, DC_CMD_INT_MASK);
1115         val |= FRAME_END_INT;
1116         tegra_dc_writel(dc, val, DC_CMD_INT_MASK);
1117
1118         /* wait for frame_end completion.
1119          * timeout is 2 frame duration to accomodate for
1120          * internal delay.
1121          */
1122         timeout = wait_for_completion_interruptible_timeout(
1123                         &dc->frame_end_complete,
1124                         msecs_to_jiffies(2 * frame_period));
1125
1126         /* disable frame end interrupt */
1127         val = tegra_dc_readl(dc, DC_CMD_INT_MASK);
1128         val &= ~FRAME_END_INT;
1129         tegra_dc_writel(dc, val, DC_CMD_INT_MASK);
1130
1131         if (timeout == 0)
1132                 dev_warn(&dc->ndev->dev,
1133                         "DC doesn't stop at end of frame.\n");
1134 }
1135
1136 static void tegra_dsi_start_dc_stream(struct tegra_dc *dc,
1137                                         struct tegra_dc_dsi_data *dsi)
1138 {
1139         u32 val;
1140
1141         tegra_dc_writel(dc, DSI_ENABLE, DC_DISP_DISP_WIN_OPTIONS);
1142
1143         /* TODO: clean up */
1144         tegra_dc_writel(dc, PW0_ENABLE | PW1_ENABLE | PW2_ENABLE | PW3_ENABLE |
1145                         PW4_ENABLE | PM0_ENABLE | PM1_ENABLE,
1146                         DC_CMD_DISPLAY_POWER_CONTROL);
1147
1148         /* Configure one-shot mode or continuous mode */
1149         if (dc->out->flags & TEGRA_DC_OUT_ONE_SHOT_MODE) {
1150                 /* disable LSPI/LCD_DE output */
1151                 val = PIN_OUTPUT_LSPI_OUTPUT_DIS;
1152                 tegra_dc_writel(dc, val, DC_COM_PIN_OUTPUT_ENABLE3);
1153
1154                 /* enable MSF & set MSF polarity */
1155                 val = MSF_ENABLE | MSF_LSPI;
1156                 if (!dsi->info.te_polarity_low)
1157                         val |= MSF_POLARITY_HIGH;
1158                 else
1159                         val |= MSF_POLARITY_LOW;
1160                 tegra_dc_writel(dc, val, DC_CMD_DISPLAY_COMMAND_OPTION0);
1161
1162                 /* set non-continuous mode */
1163                 tegra_dc_writel(dc, DISP_CTRL_MODE_NC_DISPLAY,
1164                                                 DC_CMD_DISPLAY_COMMAND);
1165                 tegra_dc_writel(dc, GENERAL_UPDATE, DC_CMD_STATE_CONTROL);
1166                 tegra_dc_writel(dc, GENERAL_ACT_REQ | NC_HOST_TRIG,
1167                                                 DC_CMD_STATE_CONTROL);
1168         } else {
1169                 /* set continuous mode */
1170                 tegra_dc_writel(dc, DISP_CTRL_MODE_C_DISPLAY,
1171                                                 DC_CMD_DISPLAY_COMMAND);
1172                 tegra_dc_writel(dc, GENERAL_UPDATE, DC_CMD_STATE_CONTROL);
1173                 tegra_dc_writel(dc, GENERAL_ACT_REQ, DC_CMD_STATE_CONTROL);
1174         }
1175
1176         dsi->status.dc_stream = DSI_DC_STREAM_ENABLE;
1177 }
1178
1179 static void tegra_dsi_set_dc_clk(struct tegra_dc *dc,
1180                                 struct tegra_dc_dsi_data *dsi)
1181 {
1182         u32 shift_clk_div_register;
1183         u32 val;
1184
1185         /* Get the corresponding register value of shift_clk_div. */
1186         shift_clk_div_register = dsi->shift_clk_div * 2 - 2;
1187
1188 #ifdef CONFIG_TEGRA_FPGA_PLATFORM
1189         shift_clk_div_register = 1;
1190 #endif
1191
1192         /* TODO: find out if PCD3 option is required */
1193         val = PIXEL_CLK_DIVIDER_PCD1 |
1194                 SHIFT_CLK_DIVIDER(shift_clk_div_register);
1195         tegra_dc_writel(dc, val, DC_DISP_DISP_CLOCK_CONTROL);
1196 }
1197
1198 static void tegra_dsi_set_dsi_clk(struct tegra_dc *dc,
1199                         struct tegra_dc_dsi_data *dsi, u32 clk)
1200 {
1201         u32 rm;
1202
1203         /* Round up to MHz */
1204         rm = clk % 1000;
1205         if (rm != 0)
1206                 clk -= rm;
1207
1208         /* Set up pixel clock */
1209         dc->shift_clk_div = dsi->shift_clk_div;
1210         dc->mode.pclk = (clk * 1000) / dsi->shift_clk_div;
1211         /* TODO: Define one shot work delay in board file. */
1212         /* Since for one-shot mode, refresh rate is usually set larger than
1213          * expected refresh rate, it needs at least 3 frame period. Less
1214          * delay one shot work is, more powering saving we have. */
1215         dc->one_shot_delay_ms = 4 *
1216                         DIV_ROUND_UP(S_TO_MS(1), dsi->info.refresh_rate);
1217
1218         /* Enable DSI clock */
1219         tegra_dc_setup_clk(dc, dsi->dsi_clk);
1220         if (!dsi->clk_ref) {
1221                 dsi->clk_ref = true;
1222                 clk_enable(dsi->dsi_clk);
1223                 tegra_periph_reset_deassert(dsi->dsi_clk);
1224         }
1225         dsi->current_dsi_clk_khz = clk_get_rate(dsi->dsi_clk) / 1000;
1226         dsi->current_bit_clk_ns =  1000*1000 / (dsi->current_dsi_clk_khz * 2);
1227 }
1228
1229 static void tegra_dsi_hs_clk_out_enable(struct tegra_dc_dsi_data *dsi)
1230 {
1231         u32 val;
1232
1233         val = tegra_dsi_readl(dsi, DSI_CONTROL);
1234         val &= ~DSI_CONTROL_HS_CLK_CTRL(1);
1235
1236         if (dsi->info.video_clock_mode == TEGRA_DSI_VIDEO_CLOCK_CONTINUOUS) {
1237                 val |= DSI_CONTROL_HS_CLK_CTRL(CONTINUOUS);
1238                 dsi->status.clk_mode = DSI_PHYCLK_CONTINUOUS;
1239         } else {
1240                 val |= DSI_CONTROL_HS_CLK_CTRL(TX_ONLY);
1241                 dsi->status.clk_mode = DSI_PHYCLK_TX_ONLY;
1242         }
1243         tegra_dsi_writel(dsi, val, DSI_CONTROL);
1244
1245         val = tegra_dsi_readl(dsi, DSI_HOST_DSI_CONTROL);
1246         val &= ~DSI_HOST_DSI_CONTROL_HIGH_SPEED_TRANS(1);
1247         val |= DSI_HOST_DSI_CONTROL_HIGH_SPEED_TRANS(TEGRA_DSI_HIGH);
1248         tegra_dsi_writel(dsi, val, DSI_HOST_DSI_CONTROL);
1249
1250         dsi->status.clk_out = DSI_PHYCLK_OUT_EN;
1251 }
1252
1253 static void tegra_dsi_hs_clk_out_enable_in_lp(struct tegra_dc_dsi_data *dsi)
1254 {
1255         u32 val;
1256         tegra_dsi_hs_clk_out_enable(dsi);
1257
1258         val = tegra_dsi_readl(dsi, DSI_HOST_DSI_CONTROL);
1259         val &= ~DSI_HOST_DSI_CONTROL_HIGH_SPEED_TRANS(1);
1260         val |= DSI_HOST_DSI_CONTROL_HIGH_SPEED_TRANS(TEGRA_DSI_LOW);
1261         tegra_dsi_writel(dsi, val, DSI_HOST_DSI_CONTROL);
1262 }
1263
1264 static void tegra_dsi_hs_clk_out_disable(struct tegra_dc *dc,
1265                                                 struct tegra_dc_dsi_data *dsi)
1266 {
1267         u32 val;
1268
1269         if (dsi->status.dc_stream == DSI_DC_STREAM_ENABLE)
1270                 tegra_dsi_stop_dc_stream_at_frame_end(dc, dsi);
1271
1272         tegra_dsi_writel(dsi, TEGRA_DSI_DISABLE, DSI_POWER_CONTROL);
1273         /* stabilization delay */
1274         udelay(300);
1275
1276         val = tegra_dsi_readl(dsi, DSI_HOST_DSI_CONTROL);
1277         val &= ~DSI_HOST_DSI_CONTROL_HIGH_SPEED_TRANS(1);
1278         val |= DSI_HOST_DSI_CONTROL_HIGH_SPEED_TRANS(TEGRA_DSI_LOW);
1279         tegra_dsi_writel(dsi, val, DSI_HOST_DSI_CONTROL);
1280
1281         tegra_dsi_writel(dsi, TEGRA_DSI_ENABLE, DSI_POWER_CONTROL);
1282         /* stabilization delay */
1283         udelay(300);
1284
1285         dsi->status.clk_mode = DSI_PHYCLK_NOT_INIT;
1286         dsi->status.clk_out = DSI_PHYCLK_OUT_DIS;
1287 }
1288
1289 static void tegra_dsi_set_control_reg_lp(struct tegra_dc_dsi_data *dsi)
1290 {
1291         u32 dsi_control;
1292         u32 host_dsi_control;
1293         u32 max_threshold;
1294
1295         dsi_control = dsi->dsi_control_val | DSI_CTRL_HOST_DRIVEN;
1296         host_dsi_control = HOST_DSI_CTRL_COMMON |
1297                         HOST_DSI_CTRL_HOST_DRIVEN |
1298                         DSI_HOST_DSI_CONTROL_HIGH_SPEED_TRANS(TEGRA_DSI_LOW);
1299         max_threshold = DSI_MAX_THRESHOLD_MAX_THRESHOLD(DSI_HOST_FIFO_DEPTH);
1300
1301         tegra_dsi_writel(dsi, max_threshold, DSI_MAX_THRESHOLD);
1302         tegra_dsi_writel(dsi, dsi_control, DSI_CONTROL);
1303         tegra_dsi_writel(dsi, host_dsi_control, DSI_HOST_DSI_CONTROL);
1304
1305         dsi->status.driven = DSI_DRIVEN_MODE_HOST;
1306         dsi->status.clk_burst = DSI_CLK_BURST_NOT_INIT;
1307         dsi->status.vtype = DSI_VIDEO_TYPE_NOT_INIT;
1308 }
1309
1310 static void tegra_dsi_set_control_reg_hs(struct tegra_dc_dsi_data *dsi)
1311 {
1312         u32 dsi_control;
1313         u32 host_dsi_control;
1314         u32 max_threshold;
1315         u32 dcs_cmd;
1316
1317         dsi_control = dsi->dsi_control_val;
1318         host_dsi_control = HOST_DSI_CTRL_COMMON;
1319         max_threshold = 0;
1320         dcs_cmd = 0;
1321
1322         if (dsi->driven_mode == TEGRA_DSI_DRIVEN_BY_HOST) {
1323                 dsi_control |= DSI_CTRL_HOST_DRIVEN;
1324                 host_dsi_control |= HOST_DSI_CTRL_HOST_DRIVEN;
1325                 max_threshold =
1326                         DSI_MAX_THRESHOLD_MAX_THRESHOLD(DSI_HOST_FIFO_DEPTH);
1327                 dsi->status.driven = DSI_DRIVEN_MODE_HOST;
1328         } else {
1329                 dsi_control |= DSI_CTRL_DC_DRIVEN;
1330                 host_dsi_control |= HOST_DSI_CTRL_DC_DRIVEN;
1331                 max_threshold =
1332                         DSI_MAX_THRESHOLD_MAX_THRESHOLD(DSI_VIDEO_FIFO_DEPTH);
1333                 dsi->status.driven = DSI_DRIVEN_MODE_DC;
1334         }
1335
1336         if (dsi->info.video_data_type == TEGRA_DSI_VIDEO_TYPE_COMMAND_MODE) {
1337                 dsi_control |= DSI_CTRL_CMD_MODE;
1338                 dcs_cmd = DSI_DCS_CMDS_LT5_DCS_CMD(DSI_WRITE_MEMORY_START)|
1339                         DSI_DCS_CMDS_LT3_DCS_CMD(DSI_WRITE_MEMORY_CONTINUE);
1340                 dsi->status.vtype = DSI_VIDEO_TYPE_CMD_MODE;
1341
1342         } else {
1343                 dsi_control |= DSI_CTRL_VIDEO_MODE;
1344                 dsi->status.vtype = DSI_VIDEO_TYPE_VIDEO_MODE;
1345         }
1346
1347         tegra_dsi_writel(dsi, max_threshold, DSI_MAX_THRESHOLD);
1348         tegra_dsi_writel(dsi, dcs_cmd, DSI_DCS_CMDS);
1349         tegra_dsi_writel(dsi, dsi_control, DSI_CONTROL);
1350         tegra_dsi_writel(dsi, host_dsi_control, DSI_HOST_DSI_CONTROL);
1351 }
1352
1353 static void tegra_dsi_pad_calibration(struct tegra_dc_dsi_data *dsi)
1354 {
1355         u32 val;
1356
1357         val =   DSI_PAD_CONTROL_PAD_LPUPADJ(0x1) |
1358                 DSI_PAD_CONTROL_PAD_LPDNADJ(0x1) |
1359                 DSI_PAD_CONTROL_PAD_PREEMP_EN(0x1) |
1360                 DSI_PAD_CONTROL_PAD_SLEWDNADJ(0x6) |
1361                 DSI_PAD_CONTROL_PAD_SLEWUPADJ(0x6);
1362         if (!dsi->ulpm) {
1363                 val |=  DSI_PAD_CONTROL_PAD_PDIO(0) |
1364                         DSI_PAD_CONTROL_PAD_PDIO_CLK(0) |
1365                         DSI_PAD_CONTROL_PAD_PULLDN_ENAB(TEGRA_DSI_DISABLE);
1366         } else {
1367                 val |=  DSI_PAD_CONTROL_PAD_PDIO(0x3) |
1368                         DSI_PAD_CONTROL_PAD_PDIO_CLK(0x1) |
1369                         DSI_PAD_CONTROL_PAD_PULLDN_ENAB(TEGRA_DSI_ENABLE);
1370         }
1371         tegra_dsi_writel(dsi, val, DSI_PAD_CONTROL);
1372
1373         val = MIPI_CAL_TERMOSA(0x4);
1374         tegra_vi_csi_writel(val, CSI_CILA_MIPI_CAL_CONFIG_0);
1375
1376         val = MIPI_CAL_TERMOSB(0x4);
1377         tegra_vi_csi_writel(val, CSI_CILB_MIPI_CAL_CONFIG_0);
1378
1379         val = MIPI_CAL_HSPUOSD(0x3) | MIPI_CAL_HSPDOSD(0x4);
1380         tegra_vi_csi_writel(val, CSI_DSI_MIPI_CAL_CONFIG);
1381
1382         val = PAD_DRIV_DN_REF(0x5) | PAD_DRIV_UP_REF(0x7);
1383         tegra_vi_csi_writel(val, CSI_MIPIBIAS_PAD_CONFIG);
1384
1385         val = PAD_CIL_PDVREG(0x0);
1386         tegra_vi_csi_writel(val, CSI_CIL_PAD_CONFIG);
1387 }
1388
1389 static int tegra_dsi_init_hw(struct tegra_dc *dc,
1390                                                 struct tegra_dc_dsi_data *dsi)
1391 {
1392         u32 i;
1393
1394         tegra_dsi_writel(dsi,
1395                 DSI_POWER_CONTROL_LEG_DSI_ENABLE(TEGRA_DSI_DISABLE),
1396                 DSI_POWER_CONTROL);
1397         /* stabilization delay */
1398         udelay(300);
1399
1400         tegra_dsi_set_dsi_clk(dc, dsi, dsi->target_lp_clk_khz);
1401         if (dsi->info.dsi_instance) {
1402                 /* TODO:Set the misc register*/
1403         }
1404
1405         /* TODO: only need to change the timing for bta */
1406         tegra_dsi_set_phy_timing(dsi, DSI_LPHS_IN_LP_MODE);
1407
1408         if (dsi->status.dc_stream == DSI_DC_STREAM_ENABLE)
1409                 tegra_dsi_stop_dc_stream_at_frame_end(dc, dsi);
1410
1411         /* Initializing DSI registers */
1412         for (i = 0; i < ARRAY_SIZE(init_reg); i++)
1413                 tegra_dsi_writel(dsi, 0, init_reg[i]);
1414
1415         tegra_dsi_writel(dsi, dsi->dsi_control_val, DSI_CONTROL);
1416
1417         tegra_dsi_pad_calibration(dsi);
1418
1419         tegra_dsi_writel(dsi,
1420                 DSI_POWER_CONTROL_LEG_DSI_ENABLE(TEGRA_DSI_ENABLE),
1421                 DSI_POWER_CONTROL);
1422         /* stabilization delay */
1423         udelay(300);
1424
1425         dsi->status.init = DSI_MODULE_INIT;
1426         dsi->status.lphs = DSI_LPHS_NOT_INIT;
1427         dsi->status.vtype = DSI_VIDEO_TYPE_NOT_INIT;
1428         dsi->status.driven = DSI_DRIVEN_MODE_NOT_INIT;
1429         dsi->status.clk_out = DSI_PHYCLK_OUT_DIS;
1430         dsi->status.clk_mode = DSI_PHYCLK_NOT_INIT;
1431         dsi->status.clk_burst = DSI_CLK_BURST_NOT_INIT;
1432         dsi->status.dc_stream = DSI_DC_STREAM_DISABLE;
1433         dsi->status.lp_op = DSI_LP_OP_NOT_INIT;
1434
1435         return 0;
1436 }
1437
1438 static int tegra_dsi_set_to_lp_mode(struct tegra_dc *dc,
1439                         struct tegra_dc_dsi_data *dsi, u8 lp_op)
1440 {
1441         int err;
1442
1443         if (dsi->status.init != DSI_MODULE_INIT) {
1444                 err = -EPERM;
1445                 goto fail;
1446         }
1447
1448         if (dsi->status.lphs == DSI_LPHS_IN_LP_MODE &&
1449                         dsi->status.lp_op == lp_op)
1450                 goto success;
1451
1452         if (dsi->status.dc_stream == DSI_DC_STREAM_ENABLE)
1453                 tegra_dsi_stop_dc_stream_at_frame_end(dc, dsi);
1454
1455         /* disable/enable hs clk according to enable_hs_clock_on_lp_cmd_mode */
1456         if ((dsi->status.clk_out == DSI_PHYCLK_OUT_EN) &&
1457                 (!dsi->info.enable_hs_clock_on_lp_cmd_mode))
1458                 tegra_dsi_hs_clk_out_disable(dc, dsi);
1459
1460         dsi->target_lp_clk_khz = tegra_dsi_get_lp_clk_rate(dsi, lp_op);
1461         if (dsi->current_dsi_clk_khz != dsi->target_lp_clk_khz) {
1462                 tegra_dsi_set_dsi_clk(dc, dsi, dsi->target_lp_clk_khz);
1463                 tegra_dsi_set_timeout(dsi);
1464         }
1465
1466         tegra_dsi_set_phy_timing(dsi, DSI_LPHS_IN_LP_MODE);
1467
1468         tegra_dsi_set_control_reg_lp(dsi);
1469
1470         if ((dsi->status.clk_out == DSI_PHYCLK_OUT_DIS) &&
1471                 (dsi->info.enable_hs_clock_on_lp_cmd_mode))
1472                 tegra_dsi_hs_clk_out_enable_in_lp(dsi);
1473
1474         dsi->status.lphs = DSI_LPHS_IN_LP_MODE;
1475         dsi->status.lp_op = lp_op;
1476 success:
1477         err = 0;
1478 fail:
1479         return err;
1480 }
1481
1482 static int tegra_dsi_set_to_hs_mode(struct tegra_dc *dc,
1483                                         struct tegra_dc_dsi_data *dsi)
1484 {
1485         int err;
1486
1487         if (dsi->status.init != DSI_MODULE_INIT) {
1488                 err = -EPERM;
1489                 goto fail;
1490         }
1491
1492         if (dsi->status.lphs == DSI_LPHS_IN_HS_MODE)
1493                 goto success;
1494
1495         if (dsi->status.dc_stream == DSI_DC_STREAM_ENABLE)
1496                 tegra_dsi_stop_dc_stream_at_frame_end(dc, dsi);
1497
1498         if ((dsi->status.clk_out == DSI_PHYCLK_OUT_EN) &&
1499                 (!dsi->info.enable_hs_clock_on_lp_cmd_mode))
1500                 tegra_dsi_hs_clk_out_disable(dc, dsi);
1501
1502         if (dsi->current_dsi_clk_khz != dsi->target_hs_clk_khz) {
1503                 tegra_dsi_set_dsi_clk(dc, dsi, dsi->target_hs_clk_khz);
1504                 tegra_dsi_set_timeout(dsi);
1505         }
1506
1507         tegra_dsi_set_phy_timing(dsi, DSI_LPHS_IN_HS_MODE);
1508
1509         if (dsi->driven_mode == TEGRA_DSI_DRIVEN_BY_DC) {
1510                 tegra_dsi_set_pkt_seq(dc, dsi);
1511                 tegra_dsi_set_pkt_length(dc, dsi);
1512                 tegra_dsi_set_sol_delay(dc, dsi);
1513                 tegra_dsi_set_dc_clk(dc, dsi);
1514         }
1515
1516         tegra_dsi_set_control_reg_hs(dsi);
1517
1518         if (dsi->status.clk_out == DSI_PHYCLK_OUT_DIS ||
1519                 dsi->info.enable_hs_clock_on_lp_cmd_mode)
1520                 tegra_dsi_hs_clk_out_enable(dsi);
1521
1522         dsi->status.lphs = DSI_LPHS_IN_HS_MODE;
1523 success:
1524         dsi->status.lp_op = DSI_LP_OP_NOT_INIT;
1525         err = 0;
1526 fail:
1527         return err;
1528 }
1529
1530 static bool tegra_dsi_write_busy(struct tegra_dc_dsi_data *dsi)
1531 {
1532         u32 timeout = 0;
1533         bool retVal = true;
1534
1535         while (timeout <= DSI_MAX_COMMAND_DELAY_USEC) {
1536                 if (!(DSI_TRIGGER_HOST_TRIGGER(0x1) &
1537                         tegra_dsi_readl(dsi, DSI_TRIGGER))) {
1538                         retVal = false;
1539                         break;
1540                 }
1541                 udelay(DSI_COMMAND_DELAY_STEPS_USEC);
1542                 timeout += DSI_COMMAND_DELAY_STEPS_USEC;
1543         }
1544
1545         return retVal;
1546 }
1547
1548 static bool tegra_dsi_read_busy(struct tegra_dc_dsi_data *dsi)
1549 {
1550         u32 timeout = 0;
1551         bool retVal = true;
1552
1553         while (timeout <  DSI_STATUS_POLLING_DURATION_USEC) {
1554                 if (!(DSI_HOST_DSI_CONTROL_IMM_BTA(0x1) &
1555                         tegra_dsi_readl(dsi, DSI_HOST_DSI_CONTROL))) {
1556                         retVal = false;
1557                         break;
1558                 }
1559                 udelay(DSI_STATUS_POLLING_DELAY_USEC);
1560                 timeout += DSI_STATUS_POLLING_DELAY_USEC;
1561         }
1562
1563         return retVal;
1564 }
1565
1566 static bool tegra_dsi_host_busy(struct tegra_dc_dsi_data *dsi)
1567 {
1568         int err = 0;
1569
1570         if (tegra_dsi_write_busy(dsi)) {
1571                 err = -EBUSY;
1572                 dev_err(&dsi->dc->ndev->dev,
1573                         "DSI trigger bit already set\n");
1574                 goto fail;
1575         }
1576
1577         if (tegra_dsi_read_busy(dsi)) {
1578                 err = -EBUSY;
1579                 dev_err(&dsi->dc->ndev->dev,
1580                         "DSI immediate bta bit already set\n");
1581                 goto fail;
1582         }
1583 fail:
1584         return (err < 0 ? true : false);
1585 }
1586
1587 static void tegra_dsi_reset_underflow_overflow
1588                                 (struct tegra_dc_dsi_data *dsi)
1589 {
1590         u32 val;
1591
1592         val = tegra_dsi_readl(dsi, DSI_STATUS);
1593         val &= (DSI_STATUS_LB_OVERFLOW(0x1) | DSI_STATUS_LB_UNDERFLOW(0x1));
1594         if (val) {
1595                 dev_warn(&dsi->dc->ndev->dev, "Reset overflow/underflow\n");
1596                 val = tegra_dsi_readl(dsi, DSI_HOST_DSI_CONTROL);
1597                 val |= DSI_HOST_CONTROL_FIFO_STAT_RESET(0x1);
1598                 tegra_dsi_writel(dsi, val, DSI_HOST_DSI_CONTROL);
1599                 ndelay(200);
1600         }
1601 }
1602
1603 static void tegra_dsi_soft_reset(struct tegra_dc_dsi_data *dsi)
1604 {
1605         tegra_dsi_writel(dsi,
1606                 DSI_POWER_CONTROL_LEG_DSI_ENABLE(TEGRA_DSI_DISABLE),
1607                 DSI_POWER_CONTROL);
1608         /* stabilization delay */
1609         udelay(300);
1610
1611         tegra_dsi_writel(dsi,
1612                 DSI_POWER_CONTROL_LEG_DSI_ENABLE(TEGRA_DSI_ENABLE),
1613                 DSI_POWER_CONTROL);
1614         /* stabilization delay */
1615         udelay(300);
1616 }
1617
1618 static void tegra_dsi_reset_read_count(struct tegra_dc_dsi_data *dsi)
1619 {
1620         u32 val;
1621
1622         val = tegra_dsi_readl(dsi, DSI_STATUS);
1623         val &= DSI_STATUS_RD_FIFO_COUNT(0x1f);
1624         if (val) {
1625                 dev_warn(&dsi->dc->ndev->dev,
1626                         "DSI read count not zero, resetting\n");
1627                 tegra_dsi_soft_reset(dsi);
1628         }
1629 }
1630
1631 static struct dsi_status *tegra_dsi_save_state_switch_to_host_cmd_mode(
1632                                                 struct tegra_dc_dsi_data *dsi,
1633                                                 struct tegra_dc *dc,
1634                                                 u8 lp_op)
1635 {
1636         struct dsi_status *init_status;
1637         int err;
1638
1639         init_status = kzalloc(sizeof(*init_status), GFP_KERNEL);
1640         if (!init_status)
1641                 return ERR_PTR(-ENOMEM);
1642
1643         *init_status = dsi->status;
1644
1645         if (dsi->status.lphs == DSI_LPHS_IN_HS_MODE) {
1646                 if (dsi->status.driven == DSI_DRIVEN_MODE_DC) {
1647                         if (dsi->status.dc_stream == DSI_DC_STREAM_ENABLE)
1648                                 tegra_dsi_stop_dc_stream_at_frame_end(dc, dsi);
1649                         dsi->driven_mode = TEGRA_DSI_DRIVEN_BY_HOST;
1650                         if (dsi->info.hs_cmd_mode_supported) {
1651                                 err = tegra_dsi_set_to_hs_mode(dc, dsi);
1652                                 if (err < 0) {
1653                                         dev_err(&dc->ndev->dev,
1654                                         "Switch to HS host mode failed\n");
1655                                         goto fail;
1656                                 }
1657                         }
1658                 }
1659                 if (!dsi->info.hs_cmd_mode_supported) {
1660                         err =
1661                         tegra_dsi_set_to_lp_mode(dc, dsi, lp_op);
1662                         if (err < 0) {
1663                                 dev_err(&dc->ndev->dev,
1664                                 "DSI failed to go to LP mode\n");
1665                                 goto fail;
1666                         }
1667                 }
1668         } else if (dsi->status.lphs == DSI_LPHS_IN_LP_MODE) {
1669                 if (dsi->status.lp_op != lp_op) {
1670                         err = tegra_dsi_set_to_lp_mode(dc, dsi, lp_op);
1671                         if (err < 0) {
1672                                 dev_err(&dc->ndev->dev,
1673                                 "DSI failed to go to LP mode\n");
1674                                 goto fail;
1675                         }
1676                 }
1677         }
1678
1679         return init_status;
1680 fail:
1681         kfree(init_status);
1682         return ERR_PTR(err);
1683 }
1684
1685 static struct dsi_status *tegra_dsi_prepare_host_transmission(
1686                                 struct tegra_dc *dc,
1687                                 struct tegra_dc_dsi_data *dsi,
1688                                 u8 lp_op)
1689 {
1690         int err = 0;
1691         struct dsi_status *init_status;
1692
1693         if (dsi->status.init != DSI_MODULE_INIT ||
1694                 dsi->ulpm) {
1695                 err = -EPERM;
1696                 goto fail;
1697         }
1698
1699         if (tegra_dsi_host_busy(dsi)) {
1700                 tegra_dsi_soft_reset(dsi);
1701                 if (tegra_dsi_host_busy(dsi)) {
1702                         err = -EBUSY;
1703                         dev_err(&dc->ndev->dev, "DSI host busy\n");
1704                         goto fail;
1705                 }
1706         }
1707
1708         tegra_dsi_reset_underflow_overflow(dsi);
1709
1710         if (lp_op == DSI_LP_OP_READ)
1711                 tegra_dsi_reset_read_count(dsi);
1712
1713         if (dsi->status.lphs == DSI_LPHS_NOT_INIT) {
1714                 err = tegra_dsi_set_to_lp_mode(dc, dsi, lp_op);
1715                 if (err < 0) {
1716                         dev_err(&dc->ndev->dev, "Failed to config LP write\n");
1717                         goto fail;
1718                 }
1719         }
1720
1721         init_status = tegra_dsi_save_state_switch_to_host_cmd_mode
1722                                         (dsi, dc, lp_op);
1723         if (IS_ERR_OR_NULL(init_status)) {
1724                 err = PTR_ERR(init_status);
1725                 dev_err(&dc->ndev->dev, "DSI state saving failed\n");
1726                 goto fail;
1727         }
1728
1729         return init_status;
1730 fail:
1731         return ERR_PTR(err);
1732 }
1733
1734 static int tegra_dsi_restore_state(struct tegra_dc *dc,
1735                                 struct tegra_dc_dsi_data *dsi,
1736                                 struct dsi_status *init_status)
1737 {
1738         bool switch_back_to_dc_mode = false;
1739         bool switch_back_to_hs_mode = false;
1740         bool restart_dc_stream;
1741         int err = 0;
1742
1743         switch_back_to_dc_mode = (dsi->status.driven ==
1744                                 DSI_DRIVEN_MODE_HOST &&
1745                                 init_status->driven ==
1746                                 DSI_DRIVEN_MODE_DC);
1747         switch_back_to_hs_mode = (dsi->status.lphs ==
1748                                 DSI_LPHS_IN_LP_MODE &&
1749                                 init_status->lphs ==
1750                                 DSI_LPHS_IN_HS_MODE);
1751         restart_dc_stream = (dsi->status.dc_stream ==
1752                                 DSI_DC_STREAM_DISABLE &&
1753                                 init_status->dc_stream ==
1754                                 DSI_DC_STREAM_ENABLE);
1755
1756         if (dsi->status.lphs == DSI_LPHS_IN_LP_MODE &&
1757                 init_status->lphs == DSI_LPHS_IN_LP_MODE) {
1758                 if (dsi->status.lp_op != init_status->lp_op) {
1759                         err =
1760                         tegra_dsi_set_to_lp_mode(dc, dsi, init_status->lp_op);
1761                         if (err < 0) {
1762                                 dev_err(&dc->ndev->dev,
1763                                         "Failed to config LP mode\n");
1764                                 goto fail;
1765                         }
1766                 }
1767                 goto success;
1768         }
1769
1770         if (switch_back_to_dc_mode)
1771                 dsi->driven_mode = TEGRA_DSI_DRIVEN_BY_DC;
1772         if (switch_back_to_dc_mode || switch_back_to_hs_mode) {
1773                 err = tegra_dsi_set_to_hs_mode(dc, dsi);
1774                 if (err < 0) {
1775                         dev_err(&dc->ndev->dev, "Failed to config HS mode\n");
1776                         goto fail;
1777                 }
1778         }
1779         if (restart_dc_stream)
1780                 tegra_dsi_start_dc_stream(dc, dsi);
1781
1782 success:
1783 fail:
1784         kfree(init_status);
1785         return err;
1786 }
1787
1788 static int tegra_dsi_host_trigger(struct tegra_dc_dsi_data *dsi)
1789 {
1790         int status = 0;
1791
1792         if (tegra_dsi_readl(dsi, DSI_TRIGGER)) {
1793                 status = -EBUSY;
1794                 goto fail;
1795         }
1796
1797         tegra_dsi_writel(dsi,
1798                 DSI_TRIGGER_HOST_TRIGGER(TEGRA_DSI_ENABLE), DSI_TRIGGER);
1799
1800 #if DSI_USE_SYNC_POINTS
1801         status = tegra_dsi_syncpt(dsi);
1802         if (status < 0) {
1803                 dev_err(&dsi->dc->ndev->dev,
1804                         "DSI syncpt for host trigger failed\n");
1805                 goto fail;
1806         }
1807 #else
1808         if (tegra_dsi_write_busy(dsi)) {
1809                 status = -EBUSY;
1810                 dev_err(&dsi->dc->ndev->dev,
1811                         "Timeout waiting on write completion\n");
1812         }
1813 #endif
1814
1815 fail:
1816         return status;
1817 }
1818
1819 static int _tegra_dsi_write_data(struct tegra_dc_dsi_data *dsi,
1820                                         u8 *pdata, u8 data_id, u16 data_len)
1821 {
1822         u8 virtual_channel;
1823         u8 *pval;
1824         u32 val;
1825         int err;
1826
1827         err = 0;
1828
1829         virtual_channel = dsi->info.virtual_channel <<
1830                                                 DSI_VIR_CHANNEL_BIT_POSITION;
1831
1832         /* always use hw for ecc */
1833         val = (virtual_channel | data_id) << 0 |
1834                         data_len << 8;
1835         tegra_dsi_writel(dsi, val, DSI_WR_DATA);
1836
1837         /* if pdata != NULL, pkt type is long pkt */
1838         if (pdata != NULL) {
1839                 while (data_len) {
1840                         if (data_len >= 4) {
1841                                 val = ((u32 *) pdata)[0];
1842                                 data_len -= 4;
1843                                 pdata += 4;
1844                         } else {
1845                                 val = 0;
1846                                 pval = (u8 *) &val;
1847                                 do
1848                                         *pval++ = *pdata++;
1849                                 while (--data_len);
1850                         }
1851                         tegra_dsi_writel(dsi, val, DSI_WR_DATA);
1852                 }
1853         }
1854
1855         err = tegra_dsi_host_trigger(dsi);
1856         if (err < 0)
1857                 dev_err(&dsi->dc->ndev->dev, "DSI host trigger failed\n");
1858
1859         return err;
1860 }
1861
1862 int tegra_dsi_write_data(struct tegra_dc *dc,
1863                         struct tegra_dc_dsi_data *dsi,
1864                         u8 *pdata, u8 data_id, u16 data_len)
1865 {
1866         int err = 0;
1867         struct dsi_status *init_status;
1868
1869         tegra_dc_io_start(dc);
1870
1871         init_status = tegra_dsi_prepare_host_transmission(
1872                                 dc, dsi, DSI_LP_OP_WRITE);
1873         if (IS_ERR_OR_NULL(init_status)) {
1874                 err = PTR_ERR(init_status);
1875                 dev_err(&dc->ndev->dev, "DSI host config failed\n");
1876                 goto fail;
1877         }
1878
1879         err = _tegra_dsi_write_data(dsi, pdata, data_id, data_len);
1880 fail:
1881         err = tegra_dsi_restore_state(dc, dsi, init_status);
1882         if (err < 0)
1883                 dev_err(&dc->ndev->dev, "Failed to restore prev state\n");
1884         tegra_dc_io_end(dc);
1885         return err;
1886 }
1887 EXPORT_SYMBOL(tegra_dsi_write_data);
1888
1889 static int tegra_dsi_send_panel_cmd(struct tegra_dc *dc,
1890                                         struct tegra_dc_dsi_data *dsi,
1891                                         struct tegra_dsi_cmd *cmd,
1892                                         u32 n_cmd)
1893 {
1894         u32 i;
1895         int err;
1896
1897         err = 0;
1898         for (i = 0; i < n_cmd; i++) {
1899                 struct tegra_dsi_cmd *cur_cmd;
1900                 cur_cmd = &cmd[i];
1901
1902                 if (cur_cmd->cmd_type == TEGRA_DSI_DELAY_MS)
1903                         mdelay(cur_cmd->sp_len_dly.delay_ms);
1904                 else {
1905                         err = tegra_dsi_write_data(dc, dsi,
1906                                                 cur_cmd->pdata,
1907                                                 cur_cmd->data_id,
1908                                                 cur_cmd->sp_len_dly.data_len);
1909                         if (err < 0)
1910                                 break;
1911                 }
1912         }
1913         return err;
1914 }
1915
1916 static u8 get_8bit_ecc(u32 header)
1917 {
1918         char ecc_parity[24] = {
1919                 0x07, 0x0b, 0x0d, 0x0e, 0x13, 0x15, 0x16, 0x19,
1920                 0x1a, 0x1c, 0x23, 0x25, 0x26, 0x29, 0x2a, 0x2c,
1921                 0x31, 0x32, 0x34, 0x38, 0x1f, 0x2f, 0x37, 0x3b
1922         };
1923         u8 ecc_byte;
1924         int i;
1925
1926         ecc_byte = 0;
1927         for (i = 0; i < 24; i++)
1928                 ecc_byte ^= ((header >> i) & 1) ? ecc_parity[i] : 0x00;
1929
1930         return ecc_byte;
1931 }
1932
1933 /* This function is written to send DCS short write (1 parameter) only.
1934  * This means the cmd will contain only 1 byte of index and 1 byte of value.
1935  * The data type ID is fixed at 0x15 and the ECC is calculated based on the
1936  * data in pdata.
1937  * The command will be sent by hardware every frame.
1938  * pdata should contain both the index + value for each cmd.
1939  * data_len will be the total number of bytes in pdata.
1940  */
1941 int tegra_dsi_send_panel_short_cmd(struct tegra_dc *dc, u8 *pdata, u8 data_len)
1942 {
1943         u8 ecc8bits = 0, data_len_orig = 0;
1944         u32 val = 0, pkthdr = 0;
1945         int err = 0, count = 0;
1946         struct tegra_dc_dsi_data *dsi = tegra_dc_get_outdata(dc);
1947
1948         data_len_orig = data_len;
1949         if (pdata != NULL) {
1950                 while (data_len) {
1951                         if (data_len >= 2) {
1952                                 pkthdr = (CMD_SHORTW |
1953                                         (((u16 *)pdata)[0]) << 8 | 0x00 << 24);
1954                                 ecc8bits = get_8bit_ecc(pkthdr);
1955                                 val = (pkthdr | (ecc8bits << 24));
1956                                 data_len -= 2;
1957                                 pdata += 2;
1958                                 count++;
1959                         }
1960                         switch (count) {
1961                         case 1:
1962                                 tegra_dsi_writel(dsi, val, DSI_INIT_SEQ_DATA_0);
1963                                 break;
1964                         case 2:
1965                                 tegra_dsi_writel(dsi, val, DSI_INIT_SEQ_DATA_1);
1966                                 break;
1967                         case 3:
1968                                 tegra_dsi_writel(dsi, val, DSI_INIT_SEQ_DATA_2);
1969                                 break;
1970                         case 4:
1971                                 tegra_dsi_writel(dsi, val, DSI_INIT_SEQ_DATA_3);
1972                                 break;
1973                         case 5:
1974                                 tegra_dsi_writel(dsi, val, DSI_INIT_SEQ_DATA_4);
1975                                 break;
1976                         case 6:
1977                                 tegra_dsi_writel(dsi, val, DSI_INIT_SEQ_DATA_5);
1978                                 break;
1979                         case 7:
1980                                 tegra_dsi_writel(dsi, val, DSI_INIT_SEQ_DATA_6);
1981                                 break;
1982                         case 8:
1983                                 tegra_dsi_writel(dsi, val, DSI_INIT_SEQ_DATA_7);
1984                                 break;
1985                         default:
1986                                 err = 1;
1987                                 break;
1988                         }
1989                 }
1990         }
1991
1992         val = DSI_INIT_SEQ_CONTROL_DSI_FRAME_INIT_BYTE_COUNT(data_len_orig * 2)
1993                 | DSI_INIT_SEQ_CONTROL_DSI_SEND_INIT_SEQUENCE(1);
1994         tegra_dsi_writel(dsi, val, DSI_INIT_SEQ_CONTROL);
1995
1996         return err;
1997 }
1998 EXPORT_SYMBOL(tegra_dsi_send_panel_short_cmd);
1999
2000 static int tegra_dsi_bta(struct tegra_dc_dsi_data *dsi)
2001 {
2002         u32 val;
2003         u32 poll_time;
2004         int err;
2005
2006         poll_time = 0;
2007         err = 0;
2008
2009         val = tegra_dsi_readl(dsi, DSI_HOST_DSI_CONTROL);
2010         val |= DSI_HOST_DSI_CONTROL_IMM_BTA(TEGRA_DSI_ENABLE);
2011         tegra_dsi_writel(dsi, val, DSI_HOST_DSI_CONTROL);
2012
2013 #if DSI_USE_SYNC_POINTS
2014         /* FIXME: Workaround for nvhost_syncpt_read */
2015         dsi->syncpt_val = nvhost_syncpt_update_min(
2016                         &nvhost_get_host(dsi->dc->ndev)->syncpt,
2017                         dsi->syncpt_id);
2018
2019         val = DSI_INCR_SYNCPT_COND(OP_DONE) |
2020                 DSI_INCR_SYNCPT_INDX(dsi->syncpt_id);
2021         tegra_dsi_writel(dsi, val, DSI_INCR_SYNCPT);
2022
2023         /* TODO: Use interrupt rather than polling */
2024         err = nvhost_syncpt_wait(&nvhost_get_host(dsi->dc->ndev)->syncpt,
2025                 dsi->syncpt_id, dsi->syncpt_val + 1);
2026         if (err < 0)
2027                 dev_err(&dsi->dc->ndev->dev,
2028                         "DSI sync point failure\n");
2029         else
2030                 (dsi->syncpt_val)++;
2031 #else
2032         if (tegra_dsi_read_busy(dsi)) {
2033                 err = -EBUSY;
2034                 dev_err(&dsi->dc->ndev->dev,
2035                         "Timeout wating on read completion\n");
2036         }
2037 #endif
2038
2039         return err;
2040 }
2041
2042 static int tegra_dsi_parse_read_response(struct tegra_dc *dc,
2043                                         u32 rd_fifo_cnt, u8 *read_fifo)
2044 {
2045         int err;
2046         u32 payload_size;
2047
2048         payload_size = 0;
2049         err = 0;
2050
2051         switch (read_fifo[0]) {
2052         case DSI_ESCAPE_CMD:
2053                 dev_info(&dc->ndev->dev, "escape cmd[0x%x]\n", read_fifo[0]);
2054                 break;
2055         case DSI_ACK_NO_ERR:
2056                 dev_info(&dc->ndev->dev,
2057                         "Panel ack, no err[0x%x]\n", read_fifo[0]);
2058                 return err;
2059         default:
2060                 dev_info(&dc->ndev->dev, "Invalid read response\n");
2061                 break;
2062         }
2063
2064         switch (read_fifo[4] & 0xff) {
2065         case GEN_LONG_RD_RES:
2066                 /* Fall through */
2067         case DCS_LONG_RD_RES:
2068                 payload_size = (read_fifo[5] |
2069                                 (read_fifo[6] << 8)) & 0xFFFF;
2070                 dev_info(&dc->ndev->dev, "Long read response Packet\n"
2071                                 "payload_size[0x%x]\n", payload_size);
2072                 break;
2073         case GEN_1_BYTE_SHORT_RD_RES:
2074                 /* Fall through */
2075         case DCS_1_BYTE_SHORT_RD_RES:
2076                 payload_size = 1;
2077                 dev_info(&dc->ndev->dev, "Short read response Packet\n"
2078                         "payload_size[0x%x]\n", payload_size);
2079                 break;
2080         case GEN_2_BYTE_SHORT_RD_RES:
2081                 /* Fall through */
2082         case DCS_2_BYTE_SHORT_RD_RES:
2083                 payload_size = 2;
2084                 dev_info(&dc->ndev->dev, "Short read response Packet\n"
2085                         "payload_size[0x%x]\n", payload_size);
2086                 break;
2087         case ACK_ERR_RES:
2088                 payload_size = 2;
2089                 dev_info(&dc->ndev->dev, "Acknowledge error report response\n"
2090                         "Packet payload_size[0x%x]\n", payload_size);
2091                 break;
2092         default:
2093                 dev_info(&dc->ndev->dev, "Invalid response packet\n");
2094                 err = -EINVAL;
2095                 break;
2096         }
2097         return err;
2098 }
2099
2100 static int tegra_dsi_read_fifo(struct tegra_dc *dc,
2101                         struct tegra_dc_dsi_data *dsi,
2102                         u8 *read_fifo)
2103 {
2104         u32 val;
2105         u32 i;
2106         u32 poll_time = 0;
2107         u32 rd_fifo_cnt;
2108         int err = 0;
2109         u8 *read_fifo_cp = read_fifo;
2110
2111         while (poll_time <  DSI_DELAY_FOR_READ_FIFO) {
2112                 mdelay(1);
2113                 val = tegra_dsi_readl(dsi, DSI_STATUS);
2114                 rd_fifo_cnt = val & DSI_STATUS_RD_FIFO_COUNT(0x1f);
2115                 if (rd_fifo_cnt << 2 > DSI_READ_FIFO_DEPTH)
2116                         dev_err(&dc->ndev->dev,
2117                         "DSI RD_FIFO_CNT is greater than RD_FIFO_DEPTH\n");
2118                         break;
2119                 poll_time++;
2120         }
2121
2122         if (rd_fifo_cnt == 0) {
2123                 dev_info(&dc->ndev->dev,
2124                         "DSI RD_FIFO_CNT is zero\n");
2125                 err = -EINVAL;
2126                 goto fail;
2127         }
2128
2129         if (val & (DSI_STATUS_LB_UNDERFLOW(0x1) |
2130                 DSI_STATUS_LB_OVERFLOW(0x1))) {
2131                 dev_warn(&dc->ndev->dev,
2132                         "DSI overflow/underflow error\n");
2133         }
2134
2135         /* Read data from FIFO */
2136         for (i = 0; i < rd_fifo_cnt; i++) {
2137                 val = tegra_dsi_readl(dsi, DSI_RD_DATA);
2138                 if (enable_read_debug)
2139                         dev_info(&dc->ndev->dev,
2140                         "Read data[%d]: 0x%x\n", i, val);
2141                 memcpy(read_fifo, &val, 4);
2142                 read_fifo += 4;
2143         }
2144
2145         /* Make sure all the data is read from the FIFO */
2146         val = tegra_dsi_readl(dsi, DSI_STATUS);
2147         val &= DSI_STATUS_RD_FIFO_COUNT(0x1f);
2148         if (val)
2149                 dev_err(&dc->ndev->dev, "DSI FIFO_RD_CNT not zero"
2150                 " even after reading FIFO_RD_CNT words from read fifo\n");
2151
2152         if (enable_read_debug) {
2153                 err =
2154                 tegra_dsi_parse_read_response(dc, rd_fifo_cnt, read_fifo_cp);
2155                 if (err < 0)
2156                         dev_warn(&dc->ndev->dev, "Unexpected read data\n");
2157         }
2158 fail:
2159         return err;
2160 }
2161
2162 int tegra_dsi_read_data(struct tegra_dc *dc,
2163                                 struct tegra_dc_dsi_data *dsi,
2164                                 u32 max_ret_payload_size,
2165                                 u32 panel_reg_addr, u8 *read_data)
2166 {
2167         int err = 0;
2168         struct dsi_status *init_status;
2169
2170         tegra_dc_io_start(dc);
2171
2172         init_status = tegra_dsi_prepare_host_transmission(
2173                                 dc, dsi, DSI_LP_OP_WRITE);
2174         if (IS_ERR_OR_NULL(init_status)) {
2175                 err = PTR_ERR(init_status);
2176                 dev_err(&dc->ndev->dev, "DSI host config failed\n");
2177                 goto fail;
2178         }
2179
2180         /* Set max return payload size in words */
2181         err = _tegra_dsi_write_data(dsi, NULL,
2182                 dsi_command_max_return_pkt_size,
2183                 max_ret_payload_size);
2184         if (err < 0) {
2185                 dev_err(&dc->ndev->dev,
2186                                 "DSI write failed\n");
2187                 goto fail;
2188         }
2189
2190         /* DCS to read given panel register */
2191         err = _tegra_dsi_write_data(dsi, NULL,
2192                 dsi_command_dcs_read_with_no_params,
2193                 panel_reg_addr);
2194         if (err < 0) {
2195                 dev_err(&dc->ndev->dev,
2196                                 "DSI write failed\n");
2197                 goto fail;
2198         }
2199
2200         tegra_dsi_reset_read_count(dsi);
2201
2202         if (dsi->status.lp_op == DSI_LP_OP_WRITE) {
2203                 err = tegra_dsi_set_to_lp_mode(dc, dsi, DSI_LP_OP_READ);
2204                 if (err < 0) {
2205                         dev_err(&dc->ndev->dev,
2206                         "DSI failed to go to LP read mode\n");
2207                         goto fail;
2208                 }
2209         }
2210
2211         err = tegra_dsi_bta(dsi);
2212         if (err < 0) {
2213                 dev_err(&dc->ndev->dev,
2214                         "DSI IMM BTA timeout\n");
2215                 goto fail;
2216         }
2217
2218         err = tegra_dsi_read_fifo(dc, dsi, read_data);
2219         if (err < 0) {
2220                 dev_err(&dc->ndev->dev, "DSI read fifo failure\n");
2221                 goto fail;
2222         }
2223 fail:
2224         err = tegra_dsi_restore_state(dc, dsi, init_status);
2225         if (err < 0)
2226                 dev_err(&dc->ndev->dev, "Failed to restore prev state\n");
2227         tegra_dc_io_end(dc);
2228         return err;
2229 }
2230 EXPORT_SYMBOL(tegra_dsi_read_data);
2231
2232 int tegra_dsi_panel_sanity_check(struct tegra_dc *dc,
2233                                 struct tegra_dc_dsi_data *dsi)
2234 {
2235         int err = 0;
2236         u8 read_fifo[DSI_READ_FIFO_DEPTH];
2237         struct dsi_status *init_status;
2238         static struct tegra_dsi_cmd dsi_nop_cmd =
2239                         DSI_CMD_SHORT(0x05, 0x0, 0x0);
2240
2241         tegra_dc_io_start(dc);
2242
2243         init_status = tegra_dsi_prepare_host_transmission(
2244                                         dc, dsi, DSI_LP_OP_WRITE);
2245         if (IS_ERR_OR_NULL(init_status)) {
2246                 err = PTR_ERR(init_status);
2247                 dev_err(&dc->ndev->dev, "DSI host config failed\n");
2248                 goto fail;
2249         }
2250
2251         err = _tegra_dsi_write_data(dsi, NULL, dsi_nop_cmd.data_id, 0x0);
2252         if (err < 0) {
2253                 dev_err(&dc->ndev->dev, "DSI nop write failed\n");
2254                 goto fail;
2255         }
2256
2257         tegra_dsi_reset_read_count(dsi);
2258
2259         if (dsi->status.lp_op == DSI_LP_OP_WRITE) {
2260                 err = tegra_dsi_set_to_lp_mode(dc, dsi, DSI_LP_OP_READ);
2261                 if (err < 0) {
2262                         dev_err(&dc->ndev->dev,
2263                         "DSI failed to go to LP read mode\n");
2264                         goto fail;
2265                 }
2266         }
2267
2268         err = tegra_dsi_bta(dsi);
2269         if (err < 0) {
2270                 dev_err(&dc->ndev->dev, "DSI BTA failed\n");
2271                 goto fail;
2272         }
2273
2274         err = tegra_dsi_read_fifo(dc, dsi, read_fifo);
2275         if (err < 0) {
2276                 dev_err(&dc->ndev->dev, "DSI read fifo failure\n");
2277                 goto fail;
2278         }
2279
2280         if (read_fifo[0] != DSI_ACK_NO_ERR) {
2281                 dev_warn(&dc->ndev->dev,
2282                         "Ack no error trigger message not received\n");
2283                 err = -EAGAIN;
2284         }
2285 fail:
2286         err = tegra_dsi_restore_state(dc, dsi, init_status);
2287         if (err < 0)
2288                 dev_err(&dc->ndev->dev, "Failed to restore prev state\n");
2289         tegra_dc_io_end(dc);
2290         return err;
2291 }
2292 EXPORT_SYMBOL(tegra_dsi_panel_sanity_check);
2293
2294 static int tegra_dsi_enter_ulpm(struct tegra_dc_dsi_data *dsi)
2295 {
2296         u32 val;
2297         int ret;
2298
2299         ret = 0;
2300
2301         val = tegra_dsi_readl(dsi, DSI_HOST_DSI_CONTROL);
2302         val &= ~DSI_HOST_DSI_CONTROL_ULTRA_LOW_POWER(3);
2303         val |= DSI_HOST_DSI_CONTROL_ULTRA_LOW_POWER(ENTER_ULPM);
2304         tegra_dsi_writel(dsi, val, DSI_HOST_DSI_CONTROL);
2305
2306 #if DSI_USE_SYNC_POINTS
2307         ret = tegra_dsi_syncpt(dsi);
2308         if (ret < 0) {
2309                 dev_err(&dsi->dc->ndev->dev,
2310                         "DSI syncpt for ulpm enter failed\n");
2311                 goto fail;
2312         }
2313 #else
2314         /* TODO: Find exact delay required */
2315         mdelay(10);
2316 #endif
2317         dsi->ulpm = true;
2318 fail:
2319         return ret;
2320 }
2321
2322 static int tegra_dsi_exit_ulpm(struct tegra_dc_dsi_data *dsi)
2323 {
2324         u32 val;
2325         int ret;
2326
2327         ret = 0;
2328
2329         val = tegra_dsi_readl(dsi, DSI_HOST_DSI_CONTROL);
2330         val &= ~DSI_HOST_DSI_CONTROL_ULTRA_LOW_POWER(3);
2331         val |= DSI_HOST_DSI_CONTROL_ULTRA_LOW_POWER(EXIT_ULPM);
2332         tegra_dsi_writel(dsi, val, DSI_HOST_DSI_CONTROL);
2333
2334 #if DSI_USE_SYNC_POINTS
2335         ret = tegra_dsi_syncpt(dsi);
2336         if (ret < 0) {
2337                 dev_err(&dsi->dc->ndev->dev,
2338                         "DSI syncpt for ulpm exit failed\n");
2339                 goto fail;
2340         }
2341 #else
2342         /* TODO: Find exact delay required */
2343         mdelay(10);
2344 #endif
2345         dsi->ulpm = false;
2346
2347         val = tegra_dsi_readl(dsi, DSI_HOST_DSI_CONTROL);
2348         val &= ~DSI_HOST_DSI_CONTROL_ULTRA_LOW_POWER(0x3);
2349         val |= DSI_HOST_DSI_CONTROL_ULTRA_LOW_POWER(NORMAL);
2350         tegra_dsi_writel(dsi, val, DSI_HOST_DSI_CONTROL);
2351 fail:
2352         return ret;
2353
2354 }
2355
2356 static void tegra_dc_dsi_enable(struct tegra_dc *dc)
2357 {
2358         struct tegra_dc_dsi_data *dsi = tegra_dc_get_outdata(dc);
2359         int err;
2360         u32 val;
2361
2362         tegra_dc_io_start(dc);
2363         mutex_lock(&dsi->lock);
2364
2365         /* Stop DC stream before configuring DSI registers
2366          * to avoid visible glitches on panel during transition
2367          * from bootloader to kernel driver
2368          */
2369         tegra_dsi_stop_dc_stream(dc, dsi);
2370
2371         if (dsi->enabled) {
2372                 if (dsi->ulpm) {
2373                         if (tegra_dsi_exit_ulpm(dsi) < 0) {
2374                                 dev_err(&dc->ndev->dev,
2375                                         "DSI failed to exit ulpm\n");
2376                                 goto fail;
2377                         }
2378                 }
2379
2380                 if (dsi->info.panel_reset) {
2381                         err = tegra_dsi_send_panel_cmd(dc, dsi,
2382                                                         dsi->info.dsi_init_cmd,
2383                                                         dsi->info.n_init_cmd);
2384                         if (err < 0) {
2385                                 dev_err(&dc->ndev->dev,
2386                                 "dsi: error sending dsi init cmd\n");
2387                                 goto fail;
2388                         }
2389                 } else if (dsi->info.dsi_late_resume_cmd) {
2390                         err = tegra_dsi_send_panel_cmd(dc, dsi,
2391                                                 dsi->info.dsi_late_resume_cmd,
2392                                                 dsi->info.n_late_resume_cmd);
2393                         if (err < 0) {
2394                                 dev_err(&dc->ndev->dev,
2395                                 "dsi: error sending late resume cmd\n");
2396                                 goto fail;
2397                         }
2398                 }
2399         } else {
2400                 err = tegra_dsi_init_hw(dc, dsi);
2401                 if (err < 0) {
2402                         dev_err(&dc->ndev->dev,
2403                                 "dsi: not able to init dsi hardware\n");
2404                         goto fail;
2405                 }
2406
2407                 if (dsi->ulpm) {
2408                         if (tegra_dsi_enter_ulpm(dsi) < 0) {
2409                                 dev_err(&dc->ndev->dev,
2410                                         "DSI failed to enter ulpm\n");
2411                                 goto fail;
2412                         }
2413                         val = DSI_PAD_CONTROL_PAD_PDIO(0) |
2414                                 DSI_PAD_CONTROL_PAD_PDIO_CLK(0) |
2415                                 DSI_PAD_CONTROL_PAD_PULLDN_ENAB
2416                                                 (TEGRA_DSI_DISABLE);
2417                         tegra_dsi_writel(dsi, val, DSI_PAD_CONTROL);
2418                         if (tegra_dsi_exit_ulpm(dsi) < 0) {
2419                                 dev_err(&dc->ndev->dev,
2420                                         "DSI failed to exit ulpm\n");
2421                                 goto fail;
2422                         }
2423                 }
2424
2425                 err = tegra_dsi_set_to_lp_mode(dc, dsi, DSI_LP_OP_WRITE);
2426                 if (err < 0) {
2427                         dev_err(&dc->ndev->dev,
2428                                 "dsi: not able to set to lp mode\n");
2429                         goto fail;
2430                 }
2431
2432                 err = tegra_dsi_send_panel_cmd(dc, dsi, dsi->info.dsi_init_cmd,
2433                                                 dsi->info.n_init_cmd);
2434                 if (err < 0) {
2435                         dev_err(&dc->ndev->dev,
2436                                 "dsi: error while sending dsi init cmd\n");
2437                         goto fail;
2438                 }
2439
2440                 err = tegra_dsi_set_to_hs_mode(dc, dsi);
2441                 if (err < 0) {
2442                         dev_err(&dc->ndev->dev,
2443                                 "dsi: not able to set to hs mode\n");
2444                         goto fail;
2445                 }
2446
2447                 dsi->enabled = true;
2448         }
2449
2450         if (dsi->status.driven == DSI_DRIVEN_MODE_DC)
2451                 tegra_dsi_start_dc_stream(dc, dsi);
2452 fail:
2453         mutex_unlock(&dsi->lock);
2454         tegra_dc_io_end(dc);
2455 }
2456
2457 static void _tegra_dc_dsi_init(struct tegra_dc *dc)
2458 {
2459         struct tegra_dc_dsi_data *dsi = tegra_dc_get_outdata(dc);
2460
2461         tegra_dsi_init_sw(dc, dsi);
2462         /* TODO: Configure the CSI pad configuration */
2463 }
2464
2465 static int tegra_dc_dsi_cp_p_cmd(struct tegra_dsi_cmd *src,
2466                                         struct tegra_dsi_cmd *dst, u16 n_cmd)
2467 {
2468         u16 i;
2469         u16 len;
2470
2471         memcpy(dst, src, sizeof(*dst) * n_cmd);
2472
2473         for (i = 0; i < n_cmd; i++)
2474                 if (src[i].pdata) {
2475                         len = sizeof(*src[i].pdata) *
2476                                         src[i].sp_len_dly.data_len;
2477                         dst[i].pdata = kzalloc(len, GFP_KERNEL);
2478                         if (!dst[i].pdata)
2479                                 goto free_cmd_pdata;
2480                         memcpy(dst[i].pdata, src[i].pdata, len);
2481                 }
2482
2483         return 0;
2484
2485 free_cmd_pdata:
2486         for (--i; i >= 0; i--)
2487                 if (dst[i].pdata)
2488                         kfree(dst[i].pdata);
2489         return -ENOMEM;
2490 }
2491
2492 static int tegra_dc_dsi_cp_info(struct tegra_dc_dsi_data *dsi,
2493                                         struct tegra_dsi_out *p_dsi)
2494 {
2495         struct tegra_dsi_cmd *p_init_cmd;
2496         struct tegra_dsi_cmd *p_early_suspend_cmd;
2497         struct tegra_dsi_cmd *p_late_resume_cmd;
2498         struct tegra_dsi_cmd *p_suspend_cmd;
2499         int err;
2500
2501         if (p_dsi->n_data_lanes > MAX_DSI_DATA_LANES)
2502                 return -EINVAL;
2503
2504         p_init_cmd = kzalloc(sizeof(*p_init_cmd) *
2505                                 p_dsi->n_init_cmd, GFP_KERNEL);
2506         if (!p_init_cmd)
2507                 return -ENOMEM;
2508
2509         if (p_dsi->dsi_early_suspend_cmd) {
2510                 p_early_suspend_cmd = kzalloc(sizeof(*p_early_suspend_cmd) *
2511                                         p_dsi->n_early_suspend_cmd,
2512                                         GFP_KERNEL);
2513                 if (!p_early_suspend_cmd) {
2514                         err = -ENOMEM;
2515                         goto err_free_init_cmd;
2516                 }
2517         }
2518
2519         if (p_dsi->dsi_late_resume_cmd) {
2520                 p_late_resume_cmd = kzalloc(sizeof(*p_late_resume_cmd) *
2521                                         p_dsi->n_late_resume_cmd,
2522                                         GFP_KERNEL);
2523                 if (!p_late_resume_cmd) {
2524                         err = -ENOMEM;
2525                         goto err_free_p_early_suspend_cmd;
2526                 }
2527         }
2528
2529         p_suspend_cmd = kzalloc(sizeof(*p_suspend_cmd) * p_dsi->n_suspend_cmd,
2530                                 GFP_KERNEL);
2531         if (!p_suspend_cmd) {
2532                 err = -ENOMEM;
2533                 goto err_free_p_late_resume_cmd;
2534         }
2535
2536         memcpy(&dsi->info, p_dsi, sizeof(dsi->info));
2537
2538         /* Copy panel init cmd */
2539         err = tegra_dc_dsi_cp_p_cmd(p_dsi->dsi_init_cmd,
2540                                                 p_init_cmd, p_dsi->n_init_cmd);
2541         if (err < 0)
2542                 goto err_free;
2543         dsi->info.dsi_init_cmd = p_init_cmd;
2544
2545         /* Copy panel early suspend cmd */
2546         if (p_dsi->dsi_early_suspend_cmd) {
2547                 err = tegra_dc_dsi_cp_p_cmd(p_dsi->dsi_early_suspend_cmd,
2548                                         p_early_suspend_cmd,
2549                                         p_dsi->n_early_suspend_cmd);
2550                 if (err < 0)
2551                         goto err_free;
2552                 dsi->info.dsi_early_suspend_cmd = p_early_suspend_cmd;
2553         }
2554
2555         /* Copy panel late resume cmd */
2556         if (p_dsi->dsi_late_resume_cmd) {
2557                 err = tegra_dc_dsi_cp_p_cmd(p_dsi->dsi_late_resume_cmd,
2558                                                 p_late_resume_cmd,
2559                                                 p_dsi->n_late_resume_cmd);
2560                 if (err < 0)
2561                         goto err_free;
2562                 dsi->info.dsi_late_resume_cmd = p_late_resume_cmd;
2563         }
2564
2565         /* Copy panel suspend cmd */
2566         err = tegra_dc_dsi_cp_p_cmd(p_dsi->dsi_suspend_cmd, p_suspend_cmd,
2567                                         p_dsi->n_suspend_cmd);
2568         if (err < 0)
2569                 goto err_free;
2570         dsi->info.dsi_suspend_cmd = p_suspend_cmd;
2571
2572         if (!dsi->info.panel_reset_timeout_msec)
2573                 dsi->info.panel_reset_timeout_msec =
2574                                                 DEFAULT_PANEL_RESET_TIMEOUT;
2575
2576         if (!dsi->info.panel_buffer_size_byte)
2577                 dsi->info.panel_buffer_size_byte = DEFAULT_PANEL_BUFFER_BYTE;
2578
2579         if (!dsi->info.max_panel_freq_khz) {
2580                 dsi->info.max_panel_freq_khz = DEFAULT_MAX_DSI_PHY_CLK_KHZ;
2581
2582                 if (dsi->info.video_burst_mode >
2583                                 TEGRA_DSI_VIDEO_NONE_BURST_MODE_WITH_SYNC_END){
2584                         dev_err(&dsi->dc->ndev->dev, "DSI: max_panel_freq_khz"
2585                                         "is not set for DSI burst mode.\n");
2586                         dsi->info.video_burst_mode =
2587                                 TEGRA_DSI_VIDEO_BURST_MODE_LOWEST_SPEED;
2588                 }
2589         }
2590
2591         if (!dsi->info.lp_cmd_mode_freq_khz)
2592                 dsi->info.lp_cmd_mode_freq_khz = DEFAULT_LP_CMD_MODE_CLK_KHZ;
2593
2594         if (!dsi->info.chip_id || !dsi->info.chip_rev)
2595                 dev_warn(&dsi->dc->ndev->dev,
2596                         "DSI: Failed to get chip info\n");
2597
2598         if (!dsi->info.lp_read_cmd_mode_freq_khz)
2599                 dsi->info.lp_read_cmd_mode_freq_khz =
2600                         dsi->info.lp_cmd_mode_freq_khz;
2601
2602         /* host mode is for testing only */
2603         dsi->driven_mode = TEGRA_DSI_DRIVEN_BY_DC;
2604         return 0;
2605
2606 err_free:
2607         kfree(p_suspend_cmd);
2608 err_free_p_late_resume_cmd:
2609         kfree(p_late_resume_cmd);
2610 err_free_p_early_suspend_cmd:
2611         kfree(p_early_suspend_cmd);
2612 err_free_init_cmd:
2613         kfree(p_init_cmd);
2614         return err;
2615 }
2616
2617 static int tegra_dc_dsi_init(struct tegra_dc *dc)
2618 {
2619         struct tegra_dc_dsi_data *dsi;
2620         struct resource *res;
2621         struct resource *base_res;
2622         void __iomem *base;
2623         struct clk *dc_clk = NULL;
2624         struct clk *dsi_clk = NULL;
2625         struct tegra_dsi_out *dsi_pdata;
2626         int err;
2627
2628         err = 0;
2629
2630         dsi = kzalloc(sizeof(*dsi), GFP_KERNEL);
2631         if (!dsi)
2632                 return -ENOMEM;
2633
2634         res = nvhost_get_resource_byname(dc->ndev, IORESOURCE_MEM,
2635                                         "dsi_regs");
2636         if (!res) {
2637                 dev_err(&dc->ndev->dev, "dsi: no mem resource\n");
2638                 err = -ENOENT;
2639                 goto err_free_dsi;
2640         }
2641
2642         base_res = request_mem_region(res->start, resource_size(res),
2643                                 dc->ndev->name);
2644         if (!base_res) {
2645                 dev_err(&dc->ndev->dev, "dsi: request_mem_region failed\n");
2646                 err = -EBUSY;
2647                 goto err_free_dsi;
2648         }
2649
2650         base = ioremap(res->start, resource_size(res));
2651         if (!base) {
2652                 dev_err(&dc->ndev->dev, "dsi: registers can't be mapped\n");
2653                 err = -EBUSY;
2654                 goto err_release_regs;
2655         }
2656
2657         dsi_pdata = dc->pdata->default_out->dsi;
2658         if (!dsi_pdata) {
2659                 dev_err(&dc->ndev->dev, "dsi: dsi data not available\n");
2660                 goto err_release_regs;
2661         }
2662
2663         if (dsi_pdata->dsi_instance)
2664                 dsi_clk = clk_get(&dc->ndev->dev, "dsib");
2665         else
2666                 dsi_clk = clk_get(&dc->ndev->dev, "dsia");
2667
2668         if (IS_ERR_OR_NULL(dsi_clk)) {
2669                 dev_err(&dc->ndev->dev, "dsi: can't get clock\n");
2670                 err = -EBUSY;
2671                 goto err_release_regs;
2672         }
2673
2674         dc_clk = clk_get_sys(dev_name(&dc->ndev->dev), NULL);
2675         if (IS_ERR_OR_NULL(dc_clk)) {
2676                 dev_err(&dc->ndev->dev, "dsi: dc clock %s unavailable\n",
2677                         dev_name(&dc->ndev->dev));
2678                 err = -EBUSY;
2679                 goto err_clk_put;
2680         }
2681
2682         mutex_init(&dsi->lock);
2683         dsi->dc = dc;
2684         dsi->base = base;
2685         dsi->base_res = base_res;
2686         dsi->dc_clk = dc_clk;
2687         dsi->dsi_clk = dsi_clk;
2688
2689         err = tegra_dc_dsi_cp_info(dsi, dsi_pdata);
2690         if (err < 0)
2691                 goto err_dsi_data;
2692
2693         tegra_dc_set_outdata(dc, dsi);
2694         _tegra_dc_dsi_init(dc);
2695
2696         return 0;
2697
2698 err_dsi_data:
2699 err_clk_put:
2700         clk_put(dsi_clk);
2701 err_release_regs:
2702         release_resource(base_res);
2703 err_free_dsi:
2704         kfree(dsi);
2705
2706         return err;
2707 }
2708
2709 static void tegra_dc_dsi_destroy(struct tegra_dc *dc)
2710 {
2711         struct tegra_dc_dsi_data *dsi = tegra_dc_get_outdata(dc);
2712         u16 i;
2713         u32 val;
2714
2715         mutex_lock(&dsi->lock);
2716
2717         /* free up the pdata */
2718         for (i = 0; i < dsi->info.n_init_cmd; i++) {
2719                 if (dsi->info.dsi_init_cmd[i].pdata)
2720                         kfree(dsi->info.dsi_init_cmd[i].pdata);
2721         }
2722         kfree(dsi->info.dsi_init_cmd);
2723
2724         /* Disable dc stream */
2725         if (dsi->status.dc_stream == DSI_DC_STREAM_ENABLE)
2726                 tegra_dsi_stop_dc_stream_at_frame_end(dc, dsi);
2727
2728         /* Disable dsi phy clock */
2729         if (dsi->status.clk_out == DSI_PHYCLK_OUT_EN)
2730                 tegra_dsi_hs_clk_out_disable(dc, dsi);
2731
2732         val = DSI_POWER_CONTROL_LEG_DSI_ENABLE(TEGRA_DSI_DISABLE);
2733         tegra_dsi_writel(dsi, val, DSI_POWER_CONTROL);
2734
2735         iounmap(dsi->base);
2736         release_resource(dsi->base_res);
2737
2738         clk_put(dsi->dc_clk);
2739         clk_put(dsi->dsi_clk);
2740
2741         mutex_unlock(&dsi->lock);
2742
2743         mutex_destroy(&dsi->lock);
2744         kfree(dsi);
2745 }
2746
2747 static int tegra_dsi_deep_sleep(struct tegra_dc *dc,
2748                                 struct tegra_dc_dsi_data *dsi)
2749 {
2750         int err = 0;
2751         int val;
2752         struct clk *parent_clk = NULL;
2753         struct clk *base_clk = NULL;
2754
2755         if (!dsi->enabled) {
2756                 err = -EPERM;
2757                 goto fail;
2758         }
2759
2760         err = tegra_dsi_set_to_lp_mode(dc, dsi, DSI_LP_OP_WRITE);
2761         if (err < 0) {
2762                 dev_err(&dc->ndev->dev,
2763                 "DSI failed to go to LP mode\n");
2764                 goto fail;
2765         }
2766
2767         /* Suspend panel */
2768         err = tegra_dsi_send_panel_cmd(dc, dsi,
2769                         dsi->info.dsi_suspend_cmd,
2770                         dsi->info.n_suspend_cmd);
2771         if (err < 0) {
2772                 dev_err(&dc->ndev->dev,
2773                         "dsi: Error sending suspend cmd\n");
2774                 goto fail;
2775         }
2776
2777         if (!dsi->ulpm) {
2778                 err = tegra_dsi_enter_ulpm(dsi);
2779                 if (err < 0) {
2780                         dev_err(&dc->ndev->dev,
2781                                 "DSI failed to enter ulpm\n");
2782                         goto fail;
2783                 }
2784         }
2785
2786         /* Suspend pad */
2787         val = tegra_dsi_readl(dsi, DSI_PAD_CONTROL);
2788         val = DSI_PAD_CONTROL_PAD_PDIO(0x3) |
2789                 DSI_PAD_CONTROL_PAD_PDIO_CLK(0x1) |
2790                 DSI_PAD_CONTROL_PAD_PULLDN_ENAB(TEGRA_DSI_ENABLE);
2791         tegra_dsi_writel(dsi, val, DSI_PAD_CONTROL);
2792
2793         /* Suspend core-logic */
2794         val = DSI_POWER_CONTROL_LEG_DSI_ENABLE(TEGRA_DSI_DISABLE);
2795         tegra_dsi_writel(dsi, val, DSI_POWER_CONTROL);
2796
2797         /* Disable dsi fast and slow clock */
2798         parent_clk = clk_get_parent(dsi->dsi_clk);
2799         base_clk = clk_get_parent(parent_clk);
2800         if (dsi->info.dsi_instance)
2801                 tegra_clk_cfg_ex(base_clk,
2802                                 TEGRA_CLK_PLLD_CSI_OUT_ENB,
2803                                 0);
2804         else
2805                 tegra_clk_cfg_ex(base_clk,
2806                                 TEGRA_CLK_PLLD_DSI_OUT_ENB,
2807                                 0);
2808
2809         /* Disable dsi source clock */
2810         clk_disable(dsi->dsi_clk);
2811
2812         dsi->clk_ref = false;
2813         dsi->enabled = false;
2814
2815         return 0;
2816 fail:
2817         return err;
2818 }
2819
2820 static void tegra_dc_dsi_disable(struct tegra_dc *dc)
2821 {
2822         int err;
2823         struct tegra_dc_dsi_data *dsi = tegra_dc_get_outdata(dc);
2824
2825         tegra_dc_io_start(dc);
2826         mutex_lock(&dsi->lock);
2827
2828         if (dsi->status.dc_stream == DSI_DC_STREAM_ENABLE)
2829                 tegra_dsi_stop_dc_stream_at_frame_end(dc, dsi);
2830
2831         if (dsi->info.power_saving_suspend) {
2832                 if (tegra_dsi_deep_sleep(dc, dsi) < 0) {
2833                         dev_err(&dc->ndev->dev,
2834                                 "DSI failed to enter deep sleep\n");
2835                         goto fail;
2836                 }
2837         } else {
2838                 if (dsi->info.dsi_early_suspend_cmd) {
2839                         err = tegra_dsi_send_panel_cmd(dc, dsi,
2840                                 dsi->info.dsi_early_suspend_cmd,
2841                                 dsi->info.n_early_suspend_cmd);
2842                         if (err < 0) {
2843                                 dev_err(&dc->ndev->dev,
2844                                 "dsi: Error sending early suspend cmd\n");
2845                                 goto fail;
2846                         }
2847                 }
2848
2849                 if (!dsi->ulpm) {
2850                         if (tegra_dsi_enter_ulpm(dsi) < 0) {
2851                                 dev_err(&dc->ndev->dev,
2852                                         "DSI failed to enter ulpm\n");
2853                                 goto fail;
2854                         }
2855                 }
2856         }
2857
2858 fail:
2859         mutex_unlock(&dsi->lock);
2860         tegra_dc_io_end(dc);
2861 }
2862
2863 #ifdef CONFIG_PM
2864 static void tegra_dc_dsi_suspend(struct tegra_dc *dc)
2865 {
2866         struct tegra_dc_dsi_data *dsi;
2867
2868         dsi = tegra_dc_get_outdata(dc);
2869
2870         if (!dsi->enabled)
2871                 return;
2872
2873         tegra_dc_io_start(dc);
2874         mutex_lock(&dsi->lock);
2875
2876         if (!dsi->info.power_saving_suspend) {
2877                 if (dsi->ulpm) {
2878                         if (tegra_dsi_exit_ulpm(dsi) < 0) {
2879                                 dev_err(&dc->ndev->dev,
2880                                         "DSI failed to exit ulpm");
2881                                 goto fail;
2882                         }
2883                 }
2884
2885                 if (tegra_dsi_deep_sleep(dc, dsi) < 0) {
2886                         dev_err(&dc->ndev->dev,
2887                                 "DSI failed to enter deep sleep\n");
2888                         goto fail;
2889                 }
2890         }
2891 fail:
2892         mutex_unlock(&dsi->lock);
2893         tegra_dc_io_end(dc);
2894 }
2895
2896 static void tegra_dc_dsi_resume(struct tegra_dc *dc)
2897 {
2898         /* Not required since tegra_dc_dsi_enable
2899          * will reconfigure the controller from scratch
2900          */
2901 }
2902 #endif
2903
2904 struct tegra_dc_out_ops tegra_dc_dsi_ops = {
2905         .init = tegra_dc_dsi_init,
2906         .destroy = tegra_dc_dsi_destroy,
2907         .enable = tegra_dc_dsi_enable,
2908         .disable = tegra_dc_dsi_disable,
2909 #ifdef CONFIG_PM
2910         .suspend = tegra_dc_dsi_suspend,
2911         .resume = tegra_dc_dsi_resume,
2912 #endif
2913 };