video: dsi: tegra: Fix init sequence for burst mode
[linux-2.6.git] / drivers / video / tegra / dc / dsi.c
1 /*
2  * drivers/video/tegra/dc/dsi.c
3  *
4  * Copyright (c) 2011, NVIDIA Corporation.
5  *
6  * This software is licensed under the terms of the GNU General Public
7  * License version 2, as published by the Free Software Foundation, and
8  * may be copied, distributed, and modified under those terms.
9  *
10  * This program is distributed in the hope that it will be useful,
11  * but WITHOUT ANY WARRANTY; without even the implied warranty of
12  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
13  * GNU General Public License for more details.
14  *
15  */
16
17 #include <linux/clk.h>
18 #include <linux/delay.h>
19 #include <linux/err.h>
20 #include <linux/fb.h>
21 #include <linux/gpio.h>
22 #include <linux/interrupt.h>
23 #include <linux/kernel.h>
24 #include <linux/slab.h>
25 #include <linux/spinlock.h>
26 #include <linux/workqueue.h>
27
28 #include <mach/clk.h>
29 #include <mach/dc.h>
30 #include <mach/fb.h>
31 #include <mach/nvhost.h>
32 #include <../gpio-names.h>
33
34 #include "dc_reg.h"
35 #include "dc_priv.h"
36 #include "dsi_regs.h"
37 #include "dsi.h"
38
39 #define DSI_USE_SYNC_POINTS 1
40
41 #define DSI_STOP_DC_DURATION_MSEC 1000
42
43 #define DSI_MODULE_NOT_INIT             0x0
44 #define DSI_MODULE_INIT                 0x1
45
46 #define DSI_LPHS_NOT_INIT               0x0
47 #define DSI_LPHS_IN_LP_MODE             0x1
48 #define DSI_LPHS_IN_HS_MODE             0x2
49
50 #define DSI_VIDEO_TYPE_NOT_INIT         0x0
51 #define DSI_VIDEO_TYPE_VIDEO_MODE       0x1
52 #define DSI_VIDEO_TYPE_CMD_MODE         0x2
53
54 #define DSI_DRIVEN_MODE_NOT_INIT        0x0
55 #define DSI_DRIVEN_MODE_DC              0x1
56 #define DSI_DRIVEN_MODE_HOST            0x2
57
58 #define DSI_PHYCLK_OUT_DIS              0x0
59 #define DSI_PHYCLK_OUT_EN               0x1
60
61 #define DSI_PHYCLK_NOT_INIT             0x0
62 #define DSI_PHYCLK_CONTINUOUS           0x1
63 #define DSI_PHYCLK_TX_ONLY              0x2
64
65 #define DSI_CLK_BURST_NOT_INIT          0x0
66 #define DSI_CLK_BURST_NONE_BURST        0x1
67 #define DSI_CLK_BURST_BURST_MODE        0x2
68
69 #define DSI_DC_STREAM_DISABLE           0x0
70 #define DSI_DC_STREAM_ENABLE            0x1
71
72 struct dsi_status {
73         unsigned        init:2;
74
75         unsigned        lphs:2;
76
77         unsigned        vtype:2;
78         unsigned        driven:2;
79
80         unsigned        clk_out:2;
81         unsigned        clk_mode:2;
82         unsigned        clk_burst:2;
83
84         unsigned        dc_stream:1;
85 };
86
87 /* source of video data */
88 enum{
89         TEGRA_DSI_DRIVEN_BY_DC,
90         TEGRA_DSI_DRIVEN_BY_HOST,
91 };
92
93 struct tegra_dc_dsi_data {
94         struct tegra_dc *dc;
95         void __iomem    *base;
96         struct resource *base_res;
97
98         struct clk              *dc_clk;
99         struct clk              *dsi_clk;
100         bool                    clk_ref;
101
102         struct mutex    lock;
103
104         /* data from board info */
105         struct tegra_dsi_out info;
106
107         struct dsi_status       status;
108
109         u8              driven_mode;
110         u8              controller_index;
111
112         u8              pixel_scaler_mul;
113         u8              pixel_scaler_div;
114
115         u32             default_shift_clk_div;
116         u32             default_pixel_clk_khz;
117         u32             default_hs_clk_khz;
118
119         u32             shift_clk_div;
120         u32             target_hs_clk_khz;
121         u32             target_lp_clk_khz;
122
123         u32             syncpt_id;
124         u32             syncpt_val;
125
126         u16             current_bit_clk_ns;
127         u32             current_dsi_clk_khz;
128
129         u32             dsi_control_val;
130
131         bool            ulpm;
132         bool            enabled;
133 };
134
135 const u32 dsi_pkt_seq_reg[NUMOF_PKT_SEQ] = {
136         DSI_PKT_SEQ_0_LO,
137         DSI_PKT_SEQ_0_HI,
138         DSI_PKT_SEQ_1_LO,
139         DSI_PKT_SEQ_1_HI,
140         DSI_PKT_SEQ_2_LO,
141         DSI_PKT_SEQ_2_HI,
142         DSI_PKT_SEQ_3_LO,
143         DSI_PKT_SEQ_3_HI,
144         DSI_PKT_SEQ_4_LO,
145         DSI_PKT_SEQ_4_HI,
146         DSI_PKT_SEQ_5_LO,
147         DSI_PKT_SEQ_5_HI,
148 };
149
150 const u32 dsi_pkt_seq_video_non_burst_syne[NUMOF_PKT_SEQ] = {
151         PKT_ID0(CMD_VS) | PKT_LEN0(0) | PKT_ID1(CMD_EOT) | PKT_LEN1(0) | PKT_LP,
152         0,
153         PKT_ID0(CMD_VE) | PKT_LEN0(0) | PKT_ID1(CMD_EOT) | PKT_LEN1(0) | PKT_LP,
154         0,
155         PKT_ID0(CMD_HS) | PKT_LEN0(0) | PKT_ID1(CMD_EOT) | PKT_LEN1(0) | PKT_LP,
156         0,
157         PKT_ID0(CMD_HS) | PKT_LEN0(0) | PKT_ID1(CMD_BLNK) | PKT_LEN1(1) |
158                 PKT_ID2(CMD_HE) | PKT_LEN2(0),
159         PKT_ID3(CMD_BLNK) | PKT_LEN3(2) | PKT_ID4(CMD_RGB) | PKT_LEN4(3) |
160                 PKT_ID5(CMD_BLNK) | PKT_LEN5(4),
161         PKT_ID0(CMD_HS) | PKT_LEN0(0) | PKT_ID1(CMD_EOT) | PKT_LEN1(0) | PKT_LP,
162         0,
163         PKT_ID0(CMD_HS) | PKT_LEN0(0) | PKT_ID1(CMD_BLNK) | PKT_LEN1(1) |
164                 PKT_ID2(CMD_HE) | PKT_LEN2(0),
165         PKT_ID3(CMD_BLNK) | PKT_LEN3(2) | PKT_ID4(CMD_RGB) | PKT_LEN4(3) |
166                 PKT_ID5(CMD_BLNK) | PKT_LEN5(4),
167 };
168
169 const u32 dsi_pkt_seq_video_non_burst[NUMOF_PKT_SEQ] = {
170         PKT_ID0(CMD_VS) | PKT_LEN0(0) | PKT_ID1(CMD_EOT) | PKT_LEN1(0) | PKT_LP,
171         0,
172         PKT_ID0(CMD_HS) | PKT_LEN0(0) | PKT_ID1(CMD_EOT) | PKT_LEN1(0) | PKT_LP,
173         0,
174         PKT_ID0(CMD_HS) | PKT_LEN0(0) | PKT_ID1(CMD_EOT) | PKT_LEN1(0) | PKT_LP,
175         0,
176         PKT_ID0(CMD_HS) | PKT_LEN0(0) | PKT_ID1(CMD_BLNK) | PKT_LEN1(2) |
177                 PKT_ID2(CMD_RGB) | PKT_LEN2(3),
178         PKT_ID3(CMD_BLNK) | PKT_LEN3(4),
179         PKT_ID0(CMD_HS) | PKT_LEN0(0) | PKT_ID1(CMD_EOT) | PKT_LEN1(0) | PKT_LP,
180         0,
181         PKT_ID0(CMD_HS) | PKT_LEN0(0) | PKT_ID1(CMD_BLNK) | PKT_LEN1(2) |
182                 PKT_ID2(CMD_RGB) | PKT_LEN2(3),
183         PKT_ID3(CMD_BLNK) | PKT_LEN3(4),
184 };
185
186 static const u32 dsi_pkt_seq_video_burst[NUMOF_PKT_SEQ] = {
187         PKT_ID0(CMD_VS) | PKT_LEN0(0) | PKT_ID1(CMD_EOT) | PKT_LEN1(7) | PKT_LP,
188         0,
189         PKT_ID0(CMD_HS) | PKT_LEN0(0) | PKT_ID1(CMD_EOT) | PKT_LEN1(7) | PKT_LP,
190         0,
191         PKT_ID0(CMD_HS) | PKT_LEN0(0) | PKT_ID1(CMD_EOT) | PKT_LEN1(7) | PKT_LP,
192         0,
193         PKT_ID0(CMD_HS) | PKT_LEN0(0) | PKT_ID1(CMD_BLNK) | PKT_LEN1(2)|
194         PKT_ID2(CMD_RGB) | PKT_LEN2(3) | PKT_LP,
195         PKT_ID0(CMD_EOT) | PKT_LEN0(7),
196         PKT_ID0(CMD_HS) | PKT_LEN0(0) | PKT_ID1(CMD_EOT) | PKT_LEN1(7) | PKT_LP,
197         0,
198         PKT_ID0(CMD_HS) | PKT_LEN0(0) | PKT_ID1(CMD_BLNK) | PKT_LEN1(2)|
199         PKT_ID2(CMD_RGB) | PKT_LEN2(3) | PKT_LP,
200         PKT_ID0(CMD_EOT) | PKT_LEN0(7),
201 };
202
203 static const u32 dsi_pkt_seq_video_burst_no_eot[NUMOF_PKT_SEQ] = {
204         PKT_ID0(CMD_VS) | PKT_LEN0(0) | PKT_ID1(CMD_EOT) | PKT_LEN1(0) | PKT_LP,
205         0,
206         PKT_ID0(CMD_HS) | PKT_LEN0(0) | PKT_ID1(CMD_EOT) | PKT_LEN1(0) | PKT_LP,
207         0,
208         PKT_ID0(CMD_HS) | PKT_LEN0(0) | PKT_ID1(CMD_EOT) | PKT_LEN1(0) | PKT_LP,
209         0,
210         PKT_ID0(CMD_HS) | PKT_LEN0(0) | PKT_ID1(CMD_BLNK) | PKT_LEN1(2)|
211         PKT_ID2(CMD_RGB) | PKT_LEN2(3) | PKT_LP,
212         PKT_ID0(CMD_EOT) | PKT_LEN0(0),
213         PKT_ID0(CMD_HS) | PKT_LEN0(0) | PKT_ID1(CMD_EOT) | PKT_LEN1(0) | PKT_LP,
214         0,
215         PKT_ID0(CMD_HS) | PKT_LEN0(0) | PKT_ID1(CMD_BLNK) | PKT_LEN1(2)|
216         PKT_ID2(CMD_RGB) | PKT_LEN2(3) | PKT_LP,
217         PKT_ID0(CMD_EOT) | PKT_LEN0(0),
218 };
219
220 /* TODO: verify with hw about this format */
221 const u32 dsi_pkt_seq_cmd_mode [NUMOF_PKT_SEQ] = {
222         0,
223         0,
224         0,
225         0,
226         0,
227         0,
228         PKT_ID0(CMD_LONGW) | PKT_LEN0(3) | PKT_ID1(CMD_EOT) | PKT_LEN1(7),
229         0,
230         0,
231         0,
232         PKT_ID0(CMD_LONGW) | PKT_LEN0(3) | PKT_ID1(CMD_EOT) | PKT_LEN1(7),
233         0,
234 };
235
236 const u32 init_reg[] = {
237         DSI_WR_DATA,
238         DSI_INT_ENABLE,
239         DSI_INT_STATUS,
240         DSI_INT_MASK,
241         DSI_INIT_SEQ_DATA_0,
242         DSI_INIT_SEQ_DATA_1,
243         DSI_INIT_SEQ_DATA_2,
244         DSI_INIT_SEQ_DATA_3,
245         DSI_DCS_CMDS,
246         DSI_PKT_SEQ_0_LO,
247         DSI_PKT_SEQ_1_LO,
248         DSI_PKT_SEQ_2_LO,
249         DSI_PKT_SEQ_3_LO,
250         DSI_PKT_SEQ_4_LO,
251         DSI_PKT_SEQ_5_LO,
252         DSI_PKT_SEQ_0_HI,
253         DSI_PKT_SEQ_1_HI,
254         DSI_PKT_SEQ_2_HI,
255         DSI_PKT_SEQ_3_HI,
256         DSI_PKT_SEQ_4_HI,
257         DSI_PKT_SEQ_5_HI,
258         DSI_CONTROL,
259         DSI_HOST_DSI_CONTROL,
260         DSI_PAD_CONTROL,
261         DSI_PAD_CONTROL_CD,
262         DSI_SOL_DELAY,
263         DSI_MAX_THRESHOLD,
264         DSI_TRIGGER,
265         DSI_TX_CRC,
266         DSI_INIT_SEQ_CONTROL,
267         DSI_PKT_LEN_0_1,
268         DSI_PKT_LEN_2_3,
269         DSI_PKT_LEN_4_5,
270         DSI_PKT_LEN_6_7,
271 };
272
273 static inline unsigned long tegra_dsi_readl(struct tegra_dc_dsi_data *dsi,
274                                                                         u32 reg)
275 {
276         return readl(dsi->base + reg * 4);
277 }
278
279 static inline void tegra_dsi_writel(struct tegra_dc_dsi_data *dsi,u32 val,
280                                                                         u32 reg)
281 {
282         writel(val, dsi->base + reg * 4);
283 }
284
285 static int tegra_dsi_syncpt(struct tegra_dc_dsi_data *dsi)
286 {
287         u32 val;
288         int ret;
289
290         ret = 0;
291
292         dsi->syncpt_val = nvhost_syncpt_read(
293                         &dsi->dc->ndev->host->syncpt, dsi->syncpt_id);
294
295         val = DSI_INCR_SYNCPT_COND(OP_DONE) |
296                 DSI_INCR_SYNCPT_INDX(dsi->syncpt_id);
297         tegra_dsi_writel(dsi, val, DSI_INCR_SYNCPT);
298
299         /* TODO: Use interrupt rather than polling */
300         ret = nvhost_syncpt_wait(&dsi->dc->ndev->host->syncpt,
301                 dsi->syncpt_id, dsi->syncpt_val + 1);
302         if (ret < 0) {
303                 printk(KERN_ERR "DSI sync point failure\n");
304                 goto fail;
305         }
306
307         (dsi->syncpt_val)++;
308         return 0;
309 fail:
310         return ret;
311 }
312
313 static u32 tegra_dsi_get_hs_clk_rate(struct tegra_dc_dsi_data *dsi)
314 {
315         u32 dsi_clock_rate_khz;
316
317         switch (dsi->info.video_burst_mode) {
318         case TEGRA_DSI_VIDEO_BURST_MODE_LOW_SPEED:
319         case TEGRA_DSI_VIDEO_BURST_MODE_MEDIUM_SPEED:
320         case TEGRA_DSI_VIDEO_BURST_MODE_FAST_SPEED:
321         case TEGRA_DSI_VIDEO_BURST_MODE_FASTEST_SPEED:
322                 /* Calculate DSI HS clock rate for DSI burst mode */
323                 dsi_clock_rate_khz = dsi->default_pixel_clk_khz *
324                                                         dsi->shift_clk_div;
325                 break;
326         case TEGRA_DSI_VIDEO_NONE_BURST_MODE:
327         case TEGRA_DSI_VIDEO_NONE_BURST_MODE_WITH_SYNC_END:
328         case TEGRA_DSI_VIDEO_BURST_MODE_LOWEST_SPEED:
329         default:
330                 /* Clock rate is default DSI clock rate for non-burst mode */
331                 dsi_clock_rate_khz = dsi->default_hs_clk_khz;
332                 break;
333         }
334
335         return dsi_clock_rate_khz;
336 }
337
338 static u32 tegra_dsi_get_lp_clk_rate(struct tegra_dc_dsi_data *dsi)
339 {
340         u32 dsi_clock_rate_khz;
341
342         if (dsi->info.enable_hs_clock_on_lp_cmd_mode)
343                 if (dsi->info.hs_clk_in_lp_cmd_mode_freq_khz)
344                         dsi_clock_rate_khz =
345                                 dsi->info.hs_clk_in_lp_cmd_mode_freq_khz;
346                 else
347                         dsi_clock_rate_khz = tegra_dsi_get_hs_clk_rate(dsi);
348         else
349                 dsi_clock_rate_khz = dsi->info.lp_cmd_mode_freq_khz;
350
351         return dsi_clock_rate_khz;
352 }
353
354 static u32 tegra_dsi_get_shift_clk_div(struct tegra_dc_dsi_data *dsi)
355 {
356         u32 shift_clk_div;
357         u32 max_shift_clk_div;
358         u32 burst_width;
359         u32 burst_width_max;
360
361         /* Get the real value of default shift_clk_div. default_shift_clk_div
362          * holds the real value of shift_clk_div. */
363         shift_clk_div = dsi->default_shift_clk_div;
364
365         /* Calculate shift_clk_div which can matche the video_burst_mode.*/
366         if (dsi->info.video_burst_mode >=
367                         TEGRA_DSI_VIDEO_BURST_MODE_LOWEST_SPEED) {
368                 /* The max_shift_clk_div is multiplied by 10 to save the
369                  * fraction */
370                 if (dsi->info.max_panel_freq_khz >= dsi->default_hs_clk_khz)
371                         max_shift_clk_div = dsi->info.max_panel_freq_khz
372                                 * shift_clk_div * 10 / dsi->default_hs_clk_khz;
373                 else
374                         max_shift_clk_div = shift_clk_div * 10;
375
376                 burst_width = dsi->info.video_burst_mode
377                                 - TEGRA_DSI_VIDEO_BURST_MODE_LOWEST_SPEED;
378                 burst_width_max = TEGRA_DSI_VIDEO_BURST_MODE_FASTEST_SPEED
379                                 - TEGRA_DSI_VIDEO_BURST_MODE_LOWEST_SPEED;
380
381                 shift_clk_div = (max_shift_clk_div - shift_clk_div * 10) *
382                         burst_width / (burst_width_max * 10) + shift_clk_div;
383         }
384
385         return shift_clk_div;
386 }
387
388 static void tegra_dsi_init_sw(struct tegra_dc *dc,
389                                                 struct tegra_dc_dsi_data *dsi)
390 {
391         u32 h_width_pixels;
392         u32 v_width_lines;
393         u32 pixel_clk_hz;
394         u32 byte_clk_hz;
395         u32 plld_clk_mhz;
396
397         switch (dsi->info.pixel_format) {
398                 case TEGRA_DSI_PIXEL_FORMAT_16BIT_P:
399                         /* 2 bytes per pixel */
400                         dsi->pixel_scaler_mul = 2;
401                         dsi->pixel_scaler_div = 1;
402                         break;
403                 case TEGRA_DSI_PIXEL_FORMAT_18BIT_P:
404                         /* 2.25 bytes per pixel */
405                         dsi->pixel_scaler_mul = 9;
406                         dsi->pixel_scaler_div = 4;
407                         break;
408                 case TEGRA_DSI_PIXEL_FORMAT_18BIT_NP:
409                 case TEGRA_DSI_PIXEL_FORMAT_24BIT_P:
410                         /* 3 bytes per pixel */
411                         dsi->pixel_scaler_mul = 3;
412                         dsi->pixel_scaler_div = 1;
413                         break;
414                 default:
415                         break;
416         }
417
418         dsi->controller_index = dc->ndev->id;
419         dsi->ulpm = false;
420         dsi->enabled = false;
421         dsi->clk_ref = false;
422
423         dsi->dsi_control_val =
424                         DSI_CONTROL_VIRTUAL_CHANNEL(dsi->info.virtual_channel) |
425                         DSI_CONTROL_NUM_DATA_LANES(dsi->info.n_data_lanes - 1) |
426                         DSI_CONTROL_VID_SOURCE(dsi->controller_index) |
427                         DSI_CONTROL_DATA_FORMAT(dsi->info.pixel_format);
428
429         /* Below we are going to calculate dsi and dc clock rate.
430          * Calcuate the horizontal and vertical width. */
431         h_width_pixels = dc->mode.h_back_porch + dc->mode.h_front_porch +
432                         dc->mode.h_sync_width + dc->mode.h_active;
433         v_width_lines = dc->mode.v_back_porch + dc->mode.v_front_porch +
434                         dc->mode.v_sync_width + dc->mode.v_active;
435
436         /* Calculate minimum required pixel rate. */
437         pixel_clk_hz = h_width_pixels * v_width_lines * dsi->info.refresh_rate;
438
439         dc->pixel_clk = pixel_clk_hz;
440
441         /* Calculate minimum byte rate on DSI interface. */
442         byte_clk_hz = (pixel_clk_hz * dsi->pixel_scaler_mul) /
443                         (dsi->pixel_scaler_div * dsi->info.n_data_lanes);
444
445         /* Round up to multiple of mega hz. */
446         plld_clk_mhz = DIV_ROUND_UP((byte_clk_hz * NUMOF_BIT_PER_BYTE),
447                                                                 1000000);
448
449         /* Calculate default real shift_clk_div. */
450         dsi->default_shift_clk_div = (NUMOF_BIT_PER_BYTE / 2) *
451                 dsi->pixel_scaler_mul / (dsi->pixel_scaler_div *
452                 dsi->info.n_data_lanes);
453         /* Calculate default DSI hs clock. DSI interface is double data rate.
454          * Data is transferred on both rising and falling edge of clk, div by 2
455          * to get the actual clock rate.
456          * */
457         dsi->default_hs_clk_khz = plld_clk_mhz * 1000 / 2;
458         dsi->default_pixel_clk_khz = plld_clk_mhz * 1000 / 2
459                                                 / dsi->default_shift_clk_div;
460
461         /* Get the actual shift_clk_div and clock rates. */
462         dsi->shift_clk_div = tegra_dsi_get_shift_clk_div(dsi);
463         dsi->target_lp_clk_khz = tegra_dsi_get_lp_clk_rate(dsi);
464         dsi->target_hs_clk_khz = tegra_dsi_get_hs_clk_rate(dsi);
465
466         dev_info(&dc->ndev->dev, "DSI: HS clock rate is %d\n",
467                                                         dsi->target_hs_clk_khz);
468
469         dsi->controller_index = dc->ndev->id;
470
471 #if DSI_USE_SYNC_POINTS
472         dsi->syncpt_id = NVSYNCPT_DSI;
473 #endif
474
475         /*
476          * Force video clock to be continuous mode if
477          * enable_hs_clock_on_lp_cmd_mode is set
478          */
479         if (dsi->info.enable_hs_clock_on_lp_cmd_mode) {
480                 if (dsi->info.video_clock_mode != TEGRA_DSI_VIDEO_CLOCK_CONTINUOUS)
481                         printk("Force to clock continuous mode\n");
482
483                 dsi->info.video_clock_mode = TEGRA_DSI_VIDEO_CLOCK_CONTINUOUS;
484         }
485
486 }
487
488 static void tegra_dsi_get_phy_timing(struct tegra_dc_dsi_data *dsi,
489                                 struct dsi_phy_timing_inclk *phy_timing_clk,
490                                 u32 clk_ns)
491 {
492
493         phy_timing_clk->t_hsdexit = dsi->info.phy_timing.t_hsdexit_ns ?
494                         (dsi->info.phy_timing.t_hsdexit_ns / clk_ns) :
495                         (T_HSEXIT_DEFAULT(clk_ns));
496
497         phy_timing_clk->t_hstrail = dsi->info.phy_timing.t_hstrail_ns ?
498                         (dsi->info.phy_timing.t_hstrail_ns / clk_ns) :
499                         (T_HSTRAIL_DEFAULT(clk_ns));
500
501         phy_timing_clk->t_datzero = dsi->info.phy_timing.t_datzero_ns ?
502                         (dsi->info.phy_timing.t_datzero_ns / clk_ns) :
503                         (T_DATZERO_DEFAULT(clk_ns));
504
505         phy_timing_clk->t_hsprepr = dsi->info.phy_timing.t_hsprepr_ns ?
506                         (dsi->info.phy_timing.t_hsprepr_ns / clk_ns) :
507                         (T_HSPREPR_DEFAULT(clk_ns));
508
509         phy_timing_clk->t_clktrail = dsi->info.phy_timing.t_clktrail_ns ?
510                                 (dsi->info.phy_timing.t_clktrail_ns / clk_ns) :
511                                 (T_CLKTRAIL_DEFAULT(clk_ns));
512
513         phy_timing_clk->t_clkpost = dsi->info.phy_timing.t_clkpost_ns ?
514                                 (dsi->info.phy_timing.t_clkpost_ns / clk_ns) :
515                                 (T_CLKPOST_DEFAULT(clk_ns));
516
517         phy_timing_clk->t_clkzero = dsi->info.phy_timing.t_clkzero_ns ?
518                                 (dsi->info.phy_timing.t_clkzero_ns / clk_ns) :
519                                 (T_CLKZERO_DEFAULT(clk_ns));
520
521         phy_timing_clk->t_tlpx = dsi->info.phy_timing.t_tlpx_ns ?
522                                 (dsi->info.phy_timing.t_tlpx_ns / clk_ns) :
523                                 (T_TLPX_DEFAULT(clk_ns));
524
525         phy_timing_clk->t_clkpre = T_CLKPRE_DEFAULT(clk_ns);
526         phy_timing_clk->t_clkprepare = T_CLKPREPARE_DEFAULT(clk_ns);
527         phy_timing_clk->t_wakeup = T_WAKEUP_DEFAULT(clk_ns);
528
529         phy_timing_clk->t_taget = 5 * phy_timing_clk->t_tlpx;
530         phy_timing_clk->t_tasure = 2 * phy_timing_clk->t_tlpx;
531         phy_timing_clk->t_tago = 4 * phy_timing_clk->t_tlpx;
532 }
533
534 static void tegra_dsi_set_phy_timing(struct tegra_dc_dsi_data *dsi)
535 {
536         u32 val;
537         struct dsi_phy_timing_inclk     phy_timing;
538
539         tegra_dsi_get_phy_timing(dsi, &phy_timing, dsi->current_bit_clk_ns);
540
541         val = DSI_PHY_TIMING_0_THSDEXIT(phy_timing.t_hsdexit) |
542                         DSI_PHY_TIMING_0_THSTRAIL(phy_timing.t_hstrail) |
543                         DSI_PHY_TIMING_0_TDATZERO(phy_timing.t_datzero) |
544                         DSI_PHY_TIMING_0_THSPREPR(phy_timing.t_hsprepr);
545         tegra_dsi_writel(dsi, val, DSI_PHY_TIMING_0);
546
547         val = DSI_PHY_TIMING_1_TCLKTRAIL(phy_timing.t_clktrail) |
548                         DSI_PHY_TIMING_1_TCLKPOST(phy_timing.t_clkpost) |
549                         DSI_PHY_TIMING_1_TCLKZERO(phy_timing.t_clkzero) |
550                         DSI_PHY_TIMING_1_TTLPX(phy_timing.t_tlpx);
551         tegra_dsi_writel(dsi, val, DSI_PHY_TIMING_1);
552
553         val = DSI_PHY_TIMING_2_TCLKPREPARE(phy_timing.t_clkprepare) |
554                 DSI_PHY_TIMING_2_TCLKPRE(phy_timing.t_clkpre) |
555                         DSI_PHY_TIMING_2_TWAKEUP(phy_timing.t_wakeup);
556         tegra_dsi_writel(dsi, val, DSI_PHY_TIMING_2);
557
558         val = DSI_BTA_TIMING_TTAGET(phy_timing.t_taget) |
559                         DSI_BTA_TIMING_TTASURE(phy_timing.t_tasure) |
560                         DSI_BTA_TIMING_TTAGO(phy_timing.t_tago);
561         tegra_dsi_writel(dsi, val, DSI_BTA_TIMING);
562 }
563
564 static u32 tegra_dsi_sol_delay_burst(struct tegra_dc *dc,
565                                                 struct tegra_dc_dsi_data *dsi)
566 {
567         u32 dsi_to_pixel_clk_ratio;
568         u32 temp;
569         u32 temp1;
570         u32 mipi_clk_adj_kHz;
571         u32 sol_delay;
572         struct tegra_dc_mode *dc_modes = &dc->mode;
573
574         /* Get Fdsi/Fpixel ration (note: Fdsi si in bit format) */
575         dsi_to_pixel_clk_ratio = (dsi->current_dsi_clk_khz * 2 +
576                 dsi->default_pixel_clk_khz - 1) / dsi->default_pixel_clk_khz;
577
578         /* Convert Fdsi to byte format */
579         dsi_to_pixel_clk_ratio *= 1000/8;
580
581         /* Multiplying by 1000 so that we don't loose the fraction part */
582         temp = dc_modes->h_active * 1000;
583         temp1 = dc_modes->h_active + dc_modes->h_back_porch +
584                         dc_modes->h_sync_width;
585
586         sol_delay = temp1 * dsi_to_pixel_clk_ratio -
587                         temp * dsi->pixel_scaler_mul /
588                         (dsi->pixel_scaler_div * dsi->info.n_data_lanes);
589
590         /* Do rounding on sol delay */
591         sol_delay = (sol_delay + 1000 - 1)/1000;
592
593         /* TODO:
594          * 1. find out the correct sol fifo depth to use
595          * 2. verify with hw about the clamping function
596          */
597         if (sol_delay > (480 * 4)) {
598                 sol_delay = (480 * 4);
599                 mipi_clk_adj_kHz = sol_delay +
600                         (dc_modes->h_active * dsi->pixel_scaler_mul) /
601                         (dsi->info.n_data_lanes * dsi->pixel_scaler_div);
602
603                 mipi_clk_adj_kHz *= (dsi->default_pixel_clk_khz / temp1);
604
605                 mipi_clk_adj_kHz *= 4;
606         }
607
608         dsi->target_hs_clk_khz = mipi_clk_adj_kHz;
609
610         return sol_delay;
611 }
612
613 static void tegra_dsi_set_sol_delay(struct tegra_dc *dc,
614                                                 struct tegra_dc_dsi_data *dsi)
615 {
616         u32 sol_delay;
617
618         if (dsi->info.video_burst_mode == TEGRA_DSI_VIDEO_NONE_BURST_MODE ||
619                 dsi->info.video_burst_mode ==
620                                 TEGRA_DSI_VIDEO_NONE_BURST_MODE_WITH_SYNC_END) {
621                 sol_delay = NUMOF_BIT_PER_BYTE * dsi->pixel_scaler_mul /
622                         (dsi->pixel_scaler_div * dsi->info.n_data_lanes);
623                 dsi->status.clk_burst = DSI_CLK_BURST_NONE_BURST;
624         } else {
625                 sol_delay = tegra_dsi_sol_delay_burst(dc, dsi);
626                 dsi->status.clk_burst = DSI_CLK_BURST_BURST_MODE;
627         }
628
629         tegra_dsi_writel(dsi, DSI_SOL_DELAY_SOL_DELAY(sol_delay),
630                                                                 DSI_SOL_DELAY);
631 }
632
633 static void tegra_dsi_set_timeout(struct tegra_dc_dsi_data *dsi)
634 {
635         u32 val;
636         u32 bytes_per_frame;
637         u32 timeout = 0;
638
639         /* TODO: verify the following eq */
640         bytes_per_frame = dsi->current_dsi_clk_khz * 1000 * 2 /
641                                                 (dsi->info.refresh_rate * 8);
642         timeout = bytes_per_frame / DSI_CYCLE_COUNTER_VALUE;
643         timeout = (timeout + DSI_HTX_TO_MARGIN) & 0xffff;
644
645         val = DSI_TIMEOUT_0_LRXH_TO(DSI_LRXH_TO_VALUE) |
646                         DSI_TIMEOUT_0_HTX_TO(timeout);
647         tegra_dsi_writel(dsi, val, DSI_TIMEOUT_0);
648
649         if (dsi->info.panel_reset_timeout_msec)
650                 timeout = (dsi->info.panel_reset_timeout_msec * 1000*1000)
651                                         / dsi->current_bit_clk_ns;
652         else
653                 timeout = DSI_PR_TO_VALUE;
654
655         val = DSI_TIMEOUT_1_PR_TO(timeout) |
656                 DSI_TIMEOUT_1_TA_TO(DSI_TA_TO_VALUE);
657         tegra_dsi_writel(dsi, val, DSI_TIMEOUT_1);
658
659         val = DSI_TO_TALLY_P_RESET_STATUS(IN_RESET) |
660                 DSI_TO_TALLY_TA_TALLY(DSI_TA_TALLY_VALUE)|
661                 DSI_TO_TALLY_LRXH_TALLY(DSI_LRXH_TALLY_VALUE)|
662                 DSI_TO_TALLY_HTX_TALLY(DSI_HTX_TALLY_VALUE);
663         tegra_dsi_writel(dsi, val, DSI_TO_TALLY);
664 }
665
666 static void tegra_dsi_setup_video_mode_pkt_length(struct tegra_dc *dc,
667                                                 struct tegra_dc_dsi_data *dsi)
668 {
669         u32 val;
670         u32 hact_pkt_len;
671         u32 hsa_pkt_len;
672         u32 hbp_pkt_len;
673         u32 hfp_pkt_len;
674
675         hact_pkt_len = dc->mode.h_active * dsi->pixel_scaler_mul /
676                                                         dsi->pixel_scaler_div;
677         hsa_pkt_len = dc->mode.h_sync_width * dsi->pixel_scaler_mul /
678                                                         dsi->pixel_scaler_div;
679         hbp_pkt_len = dc->mode.h_back_porch * dsi->pixel_scaler_mul /
680                                                         dsi->pixel_scaler_div;
681         hfp_pkt_len = dc->mode.h_front_porch * dsi->pixel_scaler_mul /
682                                                         dsi->pixel_scaler_div;
683
684         if (dsi->info.video_burst_mode !=
685                                 TEGRA_DSI_VIDEO_NONE_BURST_MODE_WITH_SYNC_END)
686                 hbp_pkt_len += hsa_pkt_len;
687
688         hsa_pkt_len -= DSI_HSYNC_BLNK_PKT_OVERHEAD;
689         hbp_pkt_len -= DSI_HBACK_PORCH_PKT_OVERHEAD;
690         hfp_pkt_len -= DSI_HFRONT_PORCH_PKT_OVERHEAD;
691
692         val = DSI_PKT_LEN_0_1_LENGTH_0(0) | DSI_PKT_LEN_0_1_LENGTH_1(hsa_pkt_len);
693         tegra_dsi_writel(dsi, val, DSI_PKT_LEN_0_1);
694
695         val = DSI_PKT_LEN_2_3_LENGTH_2(hbp_pkt_len) |
696                         DSI_PKT_LEN_2_3_LENGTH_3(hact_pkt_len);
697         tegra_dsi_writel(dsi, val, DSI_PKT_LEN_2_3);
698
699         val = DSI_PKT_LEN_4_5_LENGTH_4(hfp_pkt_len) | DSI_PKT_LEN_4_5_LENGTH_5(0);
700         tegra_dsi_writel(dsi, val, DSI_PKT_LEN_4_5);
701
702         val = DSI_PKT_LEN_6_7_LENGTH_6(0) | DSI_PKT_LEN_6_7_LENGTH_7(0);
703         tegra_dsi_writel(dsi, val, DSI_PKT_LEN_6_7);
704 }
705
706 static void tegra_dsi_setup_cmd_mode_pkt_length(struct tegra_dc *dc,
707                                                 struct tegra_dc_dsi_data *dsi)
708 {
709         unsigned long   val;
710         unsigned long   act_bytes;
711
712         act_bytes = dc->mode.h_active * dsi->pixel_scaler_mul /
713                         dsi->pixel_scaler_div + 1;
714
715         val = DSI_PKT_LEN_0_1_LENGTH_0(0) | DSI_PKT_LEN_0_1_LENGTH_1(0);
716         tegra_dsi_writel(dsi, val, DSI_PKT_LEN_0_1);
717
718         val = DSI_PKT_LEN_2_3_LENGTH_2(0) | DSI_PKT_LEN_2_3_LENGTH_3(act_bytes);
719         tegra_dsi_writel(dsi, val, DSI_PKT_LEN_2_3);
720
721         val = DSI_PKT_LEN_4_5_LENGTH_4(0) | DSI_PKT_LEN_4_5_LENGTH_5(act_bytes);
722         tegra_dsi_writel(dsi, val, DSI_PKT_LEN_4_5);
723
724         val = DSI_PKT_LEN_6_7_LENGTH_6(0) | DSI_PKT_LEN_6_7_LENGTH_7(0x0f0f);
725         tegra_dsi_writel(dsi, val, DSI_PKT_LEN_6_7);
726 }
727
728 static void tegra_dsi_set_pkt_length(struct tegra_dc *dc,
729                                                 struct tegra_dc_dsi_data *dsi)
730 {
731         if (dsi->driven_mode == TEGRA_DSI_DRIVEN_BY_HOST)
732                 return;
733
734         if (dsi->info.video_data_type == TEGRA_DSI_VIDEO_TYPE_VIDEO_MODE)
735                 tegra_dsi_setup_video_mode_pkt_length(dc, dsi);
736         else
737                 tegra_dsi_setup_cmd_mode_pkt_length(dc, dsi);
738 }
739
740 static void tegra_dsi_set_pkt_seq(struct tegra_dc *dc,
741                                                 struct tegra_dc_dsi_data *dsi)
742 {
743         const u32 *pkt_seq;
744         u32 rgb_info;
745         u32 pkt_seq_3_5_rgb_lo;
746         u32 pkt_seq_3_5_rgb_hi;
747         u32     val;
748         u32 reg;
749         u8  i;
750
751         if (dsi->driven_mode == TEGRA_DSI_DRIVEN_BY_HOST)
752                 return;
753
754         switch(dsi->info.pixel_format) {
755         case TEGRA_DSI_PIXEL_FORMAT_16BIT_P:
756                 rgb_info = CMD_RGB_16BPP;
757                 break;
758         case TEGRA_DSI_PIXEL_FORMAT_18BIT_P:
759                 rgb_info = CMD_RGB_18BPP;
760                 break;
761         case TEGRA_DSI_PIXEL_FORMAT_18BIT_NP:
762                 rgb_info = CMD_RGB_18BPPNP;
763                 break;
764         case TEGRA_DSI_PIXEL_FORMAT_24BIT_P:
765         default:
766                 rgb_info = CMD_RGB_24BPP;
767                 break;
768         }
769
770         pkt_seq_3_5_rgb_lo = 0;
771         pkt_seq_3_5_rgb_hi = 0;
772         if (dsi->info.video_data_type == TEGRA_DSI_VIDEO_TYPE_COMMAND_MODE)
773                 pkt_seq = dsi_pkt_seq_cmd_mode;
774         else {
775                 switch (dsi->info.video_burst_mode) {
776                 case TEGRA_DSI_VIDEO_BURST_MODE_LOWEST_SPEED:
777                 case TEGRA_DSI_VIDEO_BURST_MODE_LOW_SPEED:
778                 case TEGRA_DSI_VIDEO_BURST_MODE_MEDIUM_SPEED:
779                 case TEGRA_DSI_VIDEO_BURST_MODE_FAST_SPEED:
780                 case TEGRA_DSI_VIDEO_BURST_MODE_FASTEST_SPEED:
781                         pkt_seq_3_5_rgb_lo = DSI_PKT_SEQ_3_LO_PKT_32_ID(rgb_info);
782                         if(!dsi->info.no_pkt_seq_eot)
783                                 pkt_seq = dsi_pkt_seq_video_burst;
784                         else
785                                 pkt_seq = dsi_pkt_seq_video_burst_no_eot;
786                         break;
787                 case TEGRA_DSI_VIDEO_NONE_BURST_MODE_WITH_SYNC_END:
788                         pkt_seq_3_5_rgb_hi = DSI_PKT_SEQ_3_HI_PKT_34_ID(rgb_info);
789                         pkt_seq = dsi_pkt_seq_video_non_burst_syne;
790                         break;
791                 case TEGRA_DSI_VIDEO_NONE_BURST_MODE:
792                 default:
793                         pkt_seq_3_5_rgb_lo = DSI_PKT_SEQ_3_LO_PKT_32_ID(rgb_info);
794                         pkt_seq = dsi_pkt_seq_video_non_burst;
795                         break;
796                 }
797         }
798
799         for (i = 0; i < NUMOF_PKT_SEQ; i++) {
800                 val = pkt_seq[i];
801                 reg = dsi_pkt_seq_reg[i];
802                 if ((reg == DSI_PKT_SEQ_3_LO) || (reg == DSI_PKT_SEQ_5_LO))
803                         val |= pkt_seq_3_5_rgb_lo;
804                 if ((reg == DSI_PKT_SEQ_3_HI) || (reg == DSI_PKT_SEQ_5_HI))
805                         val |= pkt_seq_3_5_rgb_hi;
806                 tegra_dsi_writel(dsi, val, reg);
807         }
808 }
809
810 static void tegra_dsi_stop_dc_stream(struct tegra_dc *dc,
811                                                 struct tegra_dc_dsi_data *dsi)
812 {
813         tegra_dc_writel(dc, 0, DC_DISP_DISP_WIN_OPTIONS);
814         tegra_dc_writel(dc, GENERAL_ACT_REQ << 8, DC_CMD_STATE_CONTROL);
815         tegra_dc_writel(dc, GENERAL_ACT_REQ, DC_CMD_STATE_CONTROL);
816
817         dsi->status.dc_stream = DSI_DC_STREAM_DISABLE;
818 }
819
820 void tegra_dsi_stop_dc_stream_at_frame_end(struct tegra_dc *dc, struct tegra_dc_dsi_data *dsi)
821 {
822         int val;
823         long timeout;
824
825         /* stop dc */
826         tegra_dsi_stop_dc_stream(dc, dsi);
827
828         /* enable vblank interrupt */
829         val = tegra_dc_readl(dc, DC_CMD_INT_ENABLE);
830         val |= V_BLANK_INT;
831         tegra_dc_writel(dc, val, DC_CMD_INT_ENABLE);
832
833         val = tegra_dc_readl(dc, DC_CMD_INT_MASK);
834         val |= V_BLANK_INT;
835         tegra_dc_writel(dc, val, DC_CMD_INT_MASK);
836
837         /* wait for vblank completion */
838         timeout = wait_for_completion_interruptible_timeout(
839                 &dc->vblank_complete, DSI_STOP_DC_DURATION_MSEC);
840
841         /* disable vblank interrupt */
842         val = tegra_dc_readl(dc, DC_CMD_INT_ENABLE);
843         val &= ~V_BLANK_INT;
844         tegra_dc_writel(dc, val, DC_CMD_INT_ENABLE);
845
846         if(timeout == 0)
847                 printk("Warning: dc dosen't stop at the end of the frame.\n");
848 }
849
850 static void tegra_dsi_start_dc_stream(struct tegra_dc *dc,
851                                                 struct tegra_dc_dsi_data *dsi)
852 {
853         u32 val;
854
855         tegra_dc_writel(dc, DSI_ENABLE, DC_DISP_DISP_WIN_OPTIONS);
856
857         /* TODO: clean up */
858         tegra_dc_writel(dc, PW0_ENABLE | PW1_ENABLE | PW2_ENABLE | PW3_ENABLE |
859                         PW4_ENABLE | PM0_ENABLE | PM1_ENABLE,
860                         DC_CMD_DISPLAY_POWER_CONTROL);
861
862         /* Configure one-shot mode or continuous mode */
863         if (dc->out->flags & TEGRA_DC_OUT_ONE_SHOT_MODE) {
864                 /* disable LSPI/LCD_DE output */
865                 val = PIN_OUTPUT_LSPI_OUTPUT_DIS;
866                 tegra_dc_writel(dc, val, DC_COM_PIN_OUTPUT_ENABLE3);
867
868                 /* enable MSF & set MSF polarity */
869                 val = MSF_ENABLE | MSF_LSPI;
870                 if (!dsi->info.te_polarity_low)
871                         val |= MSF_POLARITY_HIGH;
872                 else
873                         val |= MSF_POLARITY_LOW;
874                 tegra_dc_writel(dc, val, DC_CMD_DISPLAY_COMMAND_OPTION0);
875
876                 /* set non-continuous mode */
877                 tegra_dc_writel(dc, DISP_CTRL_MODE_NC_DISPLAY,
878                                                 DC_CMD_DISPLAY_COMMAND);
879                 tegra_dc_writel(dc, GENERAL_UPDATE, DC_CMD_STATE_CONTROL);
880                 tegra_dc_writel(dc, GENERAL_ACT_REQ | NC_HOST_TRIG,
881                                                 DC_CMD_STATE_CONTROL);
882         } else {
883                 /* set continuous mode */
884                 tegra_dc_writel(dc, DISP_CTRL_MODE_C_DISPLAY,
885                                                 DC_CMD_DISPLAY_COMMAND);
886                 tegra_dc_writel(dc, GENERAL_UPDATE, DC_CMD_STATE_CONTROL);
887                 tegra_dc_writel(dc, GENERAL_ACT_REQ, DC_CMD_STATE_CONTROL);
888         }
889
890         dsi->status.dc_stream = DSI_DC_STREAM_ENABLE;
891 }
892
893 static void tegra_dsi_set_dc_clk(struct tegra_dc *dc,
894                                                 struct tegra_dc_dsi_data *dsi)
895 {
896         u32 shift_clk_div_register;
897         u32 val;
898
899         /* Get the corresponding register value of shift_clk_div. */
900         shift_clk_div_register = dsi->shift_clk_div * 2 - 2;
901
902 #ifdef CONFIG_TEGRA_FPGA_PLATFORM
903         shift_clk_div_register = 1;
904 #endif
905
906         /* TODO: find out if PCD3 option is required */
907         val = PIXEL_CLK_DIVIDER_PCD1 |
908                                 SHIFT_CLK_DIVIDER(shift_clk_div_register);
909         tegra_dc_writel(dc, val, DC_DISP_DISP_CLOCK_CONTROL);
910 }
911
912 static void tegra_dsi_set_dsi_clk(struct tegra_dc *dc,
913                                         struct tegra_dc_dsi_data *dsi, u32 clk)
914 {
915         u32 rm;
916
917         rm = clk % 1000;
918         if (rm != 0)
919                 clk -= rm;
920
921         clk *= 2;       /* Value for PLLD routine is required to be twice as */
922                         /* the desired clock rate */
923
924         dc->mode.pclk = clk*1000;
925         tegra_dc_setup_clk(dc, dsi->dsi_clk);
926         if (dsi->clk_ref == true)
927                 clk_disable(dsi->dsi_clk);
928         else
929                 dsi->clk_ref = true;
930         clk_enable(dsi->dsi_clk);
931         tegra_periph_reset_deassert(dsi->dsi_clk);
932
933         dsi->current_dsi_clk_khz = clk_get_rate(dsi->dsi_clk) / 1000;
934
935         dsi->current_bit_clk_ns =  1000*1000 / (dsi->current_dsi_clk_khz * 2);
936 }
937
938 static void tegra_dsi_hs_clk_out_enable(struct tegra_dc_dsi_data *dsi)
939 {
940         u32 val;
941         struct clk *base_clk;
942
943         /* Enable PHY clock */
944         base_clk = clk_get_parent(dsi->dsi_clk);
945         tegra_clk_cfg_ex(base_clk, TEGRA_CLK_PLLD_DSI_OUT_ENB, 1);
946         if (dsi->info.dsi_instance)
947                 tegra_clk_cfg_ex(base_clk, TEGRA_CLK_PLLD_CSI_OUT_ENB, 1);
948
949         val = tegra_dsi_readl(dsi, DSI_CONTROL);
950         val &= ~DSI_CONTROL_HS_CLK_CTRL(1);
951
952         if (dsi->info.video_clock_mode == TEGRA_DSI_VIDEO_CLOCK_CONTINUOUS) {
953                 val |= DSI_CONTROL_HS_CLK_CTRL(CONTINUOUS);
954                 dsi->status.clk_mode = DSI_PHYCLK_CONTINUOUS;
955         } else {
956                 val |= DSI_CONTROL_HS_CLK_CTRL(TX_ONLY);
957                 dsi->status.clk_mode = DSI_PHYCLK_TX_ONLY;
958         }
959         tegra_dsi_writel(dsi, val, DSI_CONTROL);
960
961         val = tegra_dsi_readl(dsi, DSI_HOST_DSI_CONTROL);
962         val &= ~DSI_HOST_DSI_CONTROL_HIGH_SPEED_TRANS(1);
963         val |= DSI_HOST_DSI_CONTROL_HIGH_SPEED_TRANS(TEGRA_DSI_HIGH);
964         tegra_dsi_writel(dsi, val, DSI_HOST_DSI_CONTROL);
965
966         dsi->status.clk_out = DSI_PHYCLK_OUT_EN;
967 }
968
969 static void tegra_dsi_hs_clk_out_enable_in_lp(struct tegra_dc_dsi_data *dsi)
970 {
971         u32 val;
972         tegra_dsi_hs_clk_out_enable(dsi);
973
974         val = tegra_dsi_readl(dsi, DSI_HOST_DSI_CONTROL);
975         val &= ~DSI_HOST_DSI_CONTROL_HIGH_SPEED_TRANS(1);
976         val |= DSI_HOST_DSI_CONTROL_HIGH_SPEED_TRANS(TEGRA_DSI_LOW);
977         tegra_dsi_writel(dsi, val, DSI_HOST_DSI_CONTROL);
978 }
979
980 static void tegra_dsi_hs_clk_out_disable(struct tegra_dc *dc,
981                                                 struct tegra_dc_dsi_data *dsi)
982 {
983         u32 val;
984         struct clk *base_clk;
985
986         if (dsi->status.dc_stream == DSI_DC_STREAM_ENABLE)
987                 tegra_dsi_stop_dc_stream(dc, dsi);
988
989         val = tegra_dsi_readl(dsi, DSI_CONTROL);
990         val &= ~DSI_CONTROL_HS_CLK_CTRL(1);
991         val |= DSI_CONTROL_HS_CLK_CTRL(TX_ONLY);
992         tegra_dsi_writel(dsi, val, DSI_CONTROL);
993
994         /* TODO: issue a cmd */
995
996         val = tegra_dsi_readl(dsi, DSI_HOST_DSI_CONTROL);
997         val &= ~DSI_HOST_DSI_CONTROL_HIGH_SPEED_TRANS(1);
998         val |= DSI_HOST_DSI_CONTROL_HIGH_SPEED_TRANS(TEGRA_DSI_LOW);
999         tegra_dsi_writel(dsi, val, DSI_HOST_DSI_CONTROL);
1000
1001         /* Disable PHY clock */
1002         base_clk = clk_get_parent(dsi->dsi_clk);
1003         tegra_clk_cfg_ex(base_clk, TEGRA_CLK_PLLD_DSI_OUT_ENB, 0);
1004         if (dsi->info.dsi_instance)
1005                 tegra_clk_cfg_ex(base_clk, TEGRA_CLK_PLLD_CSI_OUT_ENB, 0);
1006
1007         dsi->status.clk_mode = DSI_PHYCLK_NOT_INIT;
1008         dsi->status.clk_out = DSI_PHYCLK_OUT_DIS;
1009 }
1010
1011 static void tegra_dsi_set_control_reg_lp(struct tegra_dc_dsi_data *dsi)
1012 {
1013         u32 dsi_control;
1014         u32 host_dsi_control;
1015         u32 max_threshold;
1016
1017         dsi_control = dsi->dsi_control_val | DSI_CTRL_HOST_DRIVEN;
1018         host_dsi_control = HOST_DSI_CTRL_COMMON |
1019                         HOST_DSI_CTRL_HOST_DRIVEN |
1020                         DSI_HOST_DSI_CONTROL_HIGH_SPEED_TRANS(TEGRA_DSI_LOW);
1021         max_threshold = DSI_MAX_THRESHOLD_MAX_THRESHOLD(DSI_HOST_FIFO_DEPTH);
1022
1023         tegra_dsi_writel(dsi, max_threshold, DSI_MAX_THRESHOLD);
1024         tegra_dsi_writel(dsi, dsi_control, DSI_CONTROL);
1025         tegra_dsi_writel(dsi, host_dsi_control, DSI_HOST_DSI_CONTROL);
1026
1027         dsi->status.driven = DSI_DRIVEN_MODE_HOST;
1028         dsi->status.clk_burst = DSI_CLK_BURST_NOT_INIT;
1029         dsi->status.vtype = DSI_VIDEO_TYPE_NOT_INIT;
1030 }
1031
1032 static void tegra_dsi_set_control_reg_hs(struct tegra_dc_dsi_data *dsi)
1033 {
1034         u32 dsi_control;
1035         u32 host_dsi_control;
1036         u32 max_threshold;
1037         u32 dcs_cmd;
1038
1039         dsi_control = dsi->dsi_control_val;
1040         host_dsi_control = HOST_DSI_CTRL_COMMON;
1041         max_threshold = 0;
1042         dcs_cmd = 0;
1043
1044         if (dsi->driven_mode == TEGRA_DSI_DRIVEN_BY_HOST) {
1045                 dsi_control |= DSI_CTRL_HOST_DRIVEN;
1046                 host_dsi_control |= HOST_DSI_CTRL_HOST_DRIVEN;
1047                 max_threshold = DSI_MAX_THRESHOLD_MAX_THRESHOLD(DSI_HOST_FIFO_DEPTH);
1048                 dsi->status.driven = DSI_DRIVEN_MODE_HOST;
1049         } else {
1050                 dsi_control |= DSI_CTRL_DC_DRIVEN;
1051                 host_dsi_control |= HOST_DSI_CTRL_DC_DRIVEN;
1052                 max_threshold = DSI_MAX_THRESHOLD_MAX_THRESHOLD(DSI_VIDEO_FIFO_DEPTH);
1053                 dsi->status.driven = DSI_DRIVEN_MODE_DC;
1054         }
1055
1056         if (dsi->info.video_data_type == TEGRA_DSI_VIDEO_TYPE_COMMAND_MODE) {
1057                 dsi_control |= DSI_CTRL_CMD_MODE;
1058                 host_dsi_control |= HOST_DSI_CTRL_CMD_MODE;
1059                 dcs_cmd = DSI_DCS_CMDS_LT5_DCS_CMD(DSI_WRITE_MEMORY_START)|
1060                                 DSI_DCS_CMDS_LT3_DCS_CMD(DSI_WRITE_MEMORY_CONTINUE);
1061                 dsi->status.vtype = DSI_VIDEO_TYPE_CMD_MODE;
1062
1063         } else {
1064                 dsi_control |= DSI_CTRL_VIDEO_MODE;
1065                 host_dsi_control |= HOST_DSI_CTRL_VIDEO_MODE;
1066                 dsi->status.vtype = DSI_VIDEO_TYPE_VIDEO_MODE;
1067         }
1068
1069         tegra_dsi_writel(dsi, max_threshold, DSI_MAX_THRESHOLD);
1070         tegra_dsi_writel(dsi, dcs_cmd, DSI_DCS_CMDS);
1071         tegra_dsi_writel(dsi, dsi_control, DSI_CONTROL);
1072         tegra_dsi_writel(dsi, host_dsi_control, DSI_HOST_DSI_CONTROL);
1073 }
1074
1075 static int tegra_dsi_init_hw(struct tegra_dc *dc,
1076                                                 struct tegra_dc_dsi_data *dsi)
1077 {
1078         u32 val;
1079         u32 i;
1080
1081         tegra_dsi_set_dsi_clk(dc, dsi, dsi->target_lp_clk_khz);
1082         if (dsi->info.dsi_instance) {
1083                 /* TODO:Set the misc register*/
1084         }
1085
1086         /* TODO: only need to change the timing for bta */
1087         tegra_dsi_set_phy_timing(dsi);
1088
1089         if (dsi->status.dc_stream == DSI_DC_STREAM_ENABLE)
1090                 tegra_dsi_stop_dc_stream(dc, dsi);
1091
1092         /* Initializing DSI registers */
1093         for (i = 0; i < ARRAY_SIZE(init_reg); i++) {
1094                 tegra_dsi_writel(dsi, 0, init_reg[i]);
1095         }
1096         tegra_dsi_writel(dsi, dsi->dsi_control_val, DSI_CONTROL);
1097
1098         /* Initialize DSI_PAD_CONTROL register. */
1099         val =   DSI_PAD_CONTROL_PAD_LPUPADJ(0x1) |
1100                 DSI_PAD_CONTROL_PAD_LPDNADJ(0x1) |
1101                 DSI_PAD_CONTROL_PAD_PREEMP_EN(0x1) |
1102                 DSI_PAD_CONTROL_PAD_SLEWDNADJ(0x6) |
1103                 DSI_PAD_CONTROL_PAD_SLEWUPADJ(0x6);
1104         if (!dsi->ulpm) {
1105                 val |=  DSI_PAD_CONTROL_PAD_PDIO(0) |
1106                         DSI_PAD_CONTROL_PAD_PDIO_CLK(0) |
1107                         DSI_PAD_CONTROL_PAD_PULLDN_ENAB(TEGRA_DSI_DISABLE);
1108         } else {
1109                 val |=  DSI_PAD_CONTROL_PAD_PDIO(0x3) |
1110                         DSI_PAD_CONTROL_PAD_PDIO_CLK(0x1) |
1111                         DSI_PAD_CONTROL_PAD_PULLDN_ENAB(TEGRA_DSI_ENABLE);
1112         }
1113         tegra_dsi_writel(dsi, val, DSI_PAD_CONTROL);
1114
1115         val = DSI_POWER_CONTROL_LEG_DSI_ENABLE(TEGRA_DSI_ENABLE);
1116         tegra_dsi_writel(dsi, val, DSI_POWER_CONTROL);
1117
1118         while (tegra_dsi_readl(dsi, DSI_POWER_CONTROL) != val) {
1119                 tegra_dsi_writel(dsi, val, DSI_POWER_CONTROL);
1120         }
1121
1122         dsi->status.init = DSI_MODULE_INIT;
1123         dsi->status.lphs = DSI_LPHS_NOT_INIT;
1124         dsi->status.vtype = DSI_VIDEO_TYPE_NOT_INIT;
1125         dsi->status.driven = DSI_DRIVEN_MODE_NOT_INIT;
1126         dsi->status.clk_out = DSI_PHYCLK_OUT_DIS;
1127         dsi->status.clk_mode = DSI_PHYCLK_NOT_INIT;
1128         dsi->status.clk_burst = DSI_CLK_BURST_NOT_INIT;
1129         dsi->status.dc_stream = DSI_DC_STREAM_DISABLE;
1130
1131         return 0;
1132 }
1133
1134 static int tegra_dsi_set_to_lp_mode(struct tegra_dc *dc,
1135                                                 struct tegra_dc_dsi_data *dsi)
1136 {
1137         int     err;
1138
1139         if (dsi->status.init != DSI_MODULE_INIT) {
1140                 err = -EPERM;
1141                 goto fail;
1142         }
1143
1144         if (dsi->status.lphs == DSI_LPHS_IN_LP_MODE)
1145                 goto success;
1146
1147         if (dsi->status.dc_stream == DSI_DC_STREAM_ENABLE)
1148                 tegra_dsi_stop_dc_stream_at_frame_end(dc, dsi);
1149
1150         /* disable/enable hs clock according to enable_hs_clock_on_lp_cmd_mode */
1151         if ((dsi->status.clk_out == DSI_PHYCLK_OUT_EN) &&
1152                 (!dsi->info.enable_hs_clock_on_lp_cmd_mode))
1153                 tegra_dsi_hs_clk_out_disable(dc, dsi);
1154
1155         if (dsi->current_dsi_clk_khz != dsi->target_lp_clk_khz){
1156                 tegra_dsi_set_dsi_clk(dc, dsi, dsi->target_lp_clk_khz);
1157                 tegra_dsi_set_timeout(dsi);
1158         }
1159
1160         tegra_dsi_set_control_reg_lp(dsi);
1161
1162         if ((dsi->status.clk_out == DSI_PHYCLK_OUT_DIS) &&
1163                 (dsi->info.enable_hs_clock_on_lp_cmd_mode))
1164                 tegra_dsi_hs_clk_out_enable_in_lp(dsi);
1165
1166 success:
1167         dsi->status.lphs = DSI_LPHS_IN_LP_MODE;
1168         err = 0;
1169 fail:
1170         return err;
1171 }
1172
1173 static int tegra_dsi_set_to_hs_mode(struct tegra_dc *dc,
1174                                                 struct tegra_dc_dsi_data *dsi)
1175 {
1176         int err;
1177
1178         if (dsi->status.init != DSI_MODULE_INIT) {
1179                 err = -EPERM;
1180                 goto fail;
1181         }
1182
1183         if (dsi->status.dc_stream == DSI_DC_STREAM_ENABLE)
1184                 tegra_dsi_stop_dc_stream_at_frame_end(dc, dsi);
1185
1186         if ((dsi->status.clk_out == DSI_PHYCLK_OUT_EN) &&
1187                 (!dsi->info.enable_hs_clock_on_lp_cmd_mode))
1188                 tegra_dsi_hs_clk_out_disable(dc, dsi);
1189
1190         if (dsi->current_dsi_clk_khz != dsi->target_hs_clk_khz) {
1191                 tegra_dsi_set_dsi_clk(dc, dsi, dsi->target_hs_clk_khz);
1192                 tegra_dsi_set_timeout(dsi);
1193         }
1194
1195         tegra_dsi_set_phy_timing(dsi);
1196
1197         if (dsi->driven_mode == TEGRA_DSI_DRIVEN_BY_DC){
1198                 tegra_dsi_set_pkt_seq(dc, dsi);
1199                 tegra_dsi_set_pkt_length(dc, dsi);
1200                 tegra_dsi_set_sol_delay(dc, dsi);
1201                 tegra_dsi_set_dc_clk(dc, dsi);
1202         }
1203
1204         tegra_dsi_set_control_reg_hs(dsi);
1205
1206         if (dsi->status.clk_out == DSI_PHYCLK_OUT_DIS)
1207                 tegra_dsi_hs_clk_out_enable(dsi);
1208
1209         dsi->status.lphs = DSI_LPHS_IN_HS_MODE;
1210         err = 0;
1211 fail:
1212         return err;
1213 }
1214
1215 static bool tegra_dsi_is_controller_idle(struct tegra_dc_dsi_data *dsi)
1216 {
1217         u32 timeout = 0;
1218         bool retVal;
1219
1220         retVal = false;
1221         while (timeout <= DSI_MAX_COMMAND_DELAY_USEC) {
1222                 if (!tegra_dsi_readl(dsi, DSI_TRIGGER)) {
1223                         retVal = true;
1224                         break;
1225                 }
1226                 udelay(DSI_COMMAND_DELAY_STEPS_USEC);
1227                 timeout += DSI_COMMAND_DELAY_STEPS_USEC;
1228         }
1229
1230         return retVal;
1231 }
1232
1233 static int tegra_dsi_host_trigger(struct tegra_dc_dsi_data *dsi)
1234 {
1235         int status = 0;
1236
1237         if (tegra_dsi_readl(dsi, DSI_TRIGGER)) {
1238                 status = -EBUSY;
1239                 goto fail;
1240         }
1241
1242         tegra_dsi_writel(dsi,
1243                 DSI_TRIGGER_HOST_TRIGGER(TEGRA_DSI_ENABLE), DSI_TRIGGER);
1244
1245 #if DSI_USE_SYNC_POINTS
1246         status = tegra_dsi_syncpt(dsi);
1247         if (status < 0) {
1248                 printk(KERN_ERR "DSI syncpt for host trigger failed\n");
1249                 goto fail;
1250         }
1251 #else
1252         if (!tegra_dsi_is_controller_idle(dsi))
1253                 status = -EIO;
1254 #endif
1255
1256 fail:
1257         return status;
1258 }
1259
1260 static int _tegra_dsi_write_data(struct tegra_dc_dsi_data *dsi,
1261                                         u8* pdata, u8 data_id, u16 data_len)
1262 {
1263         u8 virtual_channel;
1264         u8 *pval;
1265         u32 val;
1266         int err;
1267
1268         err = 0;
1269
1270         virtual_channel = dsi->info.virtual_channel << DSI_VIR_CHANNEL_BIT_POSITION;
1271
1272         /* always use hw for ecc */
1273         val = (virtual_channel | data_id) << 0 |
1274                         data_len << 8;
1275         tegra_dsi_writel(dsi, val, DSI_WR_DATA);
1276
1277         /* if pdata != NULL, pkt type is long pkt */
1278         if (pdata != NULL) {
1279                 while (data_len) {
1280                         if (data_len >= 4) {
1281                                 val = ((u32*) pdata)[0];
1282                                 data_len -= 4;
1283                                 pdata += 4;
1284                         } else {
1285                                 val = 0;
1286                                 pval = (u8*) &val;
1287                                 do
1288                                         *pval++ = *pdata++;
1289                                 while(--data_len);
1290                         }
1291                         tegra_dsi_writel(dsi, val, DSI_WR_DATA);
1292                 }
1293         }
1294
1295         err = tegra_dsi_host_trigger(dsi);
1296         if (err < 0)
1297                 printk(KERN_ERR "DSI host trigger failed\n");
1298
1299         return err;
1300 }
1301
1302 static int tegra_dsi_write_data(struct tegra_dc *dc,
1303                                         struct tegra_dc_dsi_data *dsi,
1304                                         u8* pdata, u8 data_id, u16 data_len)
1305 {
1306         bool switch_back_to_hs_mode;
1307         bool switch_back_to_dc_mode;
1308         int err;
1309
1310         err = 0;
1311         switch_back_to_hs_mode = false;
1312         switch_back_to_dc_mode = false;
1313
1314         if ((dsi->status.init != DSI_MODULE_INIT) ||
1315                 (dsi->status.lphs == DSI_LPHS_NOT_INIT)) {
1316                 err = -EPERM;
1317                 goto fail;
1318         }
1319
1320         if (!tegra_dsi_is_controller_idle(dsi)) {
1321                 err = -EBUSY;
1322                 goto fail;
1323         }
1324
1325         err = 0;
1326
1327         if (dsi->status.lphs == DSI_LPHS_IN_HS_MODE) {
1328                 if (dsi->info.hs_cmd_mode_supported) {
1329                         if (dsi->status.driven == DSI_DRIVEN_MODE_DC) {
1330                                 dsi->driven_mode = TEGRA_DSI_DRIVEN_BY_HOST;
1331                                 tegra_dsi_set_to_hs_mode(dc, dsi);
1332                                 switch_back_to_dc_mode = true;
1333                         }
1334                 } else {
1335                         tegra_dsi_set_to_lp_mode(dc, dsi);
1336                         switch_back_to_hs_mode = true;
1337                 }
1338         }
1339
1340         err = _tegra_dsi_write_data(dsi, pdata, data_id, data_len);
1341
1342
1343         if (switch_back_to_dc_mode)
1344                 dsi->driven_mode = TEGRA_DSI_DRIVEN_BY_DC;
1345         if (switch_back_to_dc_mode || switch_back_to_hs_mode)
1346                 tegra_dsi_set_to_hs_mode(dc, dsi);
1347
1348 fail:
1349         return err;
1350 }
1351
1352 static int tegra_dsi_send_panel_cmd(struct tegra_dc *dc,
1353                                                 struct tegra_dc_dsi_data *dsi,
1354                                                 struct tegra_dsi_cmd *cmd,
1355                                                 u32 n_cmd)
1356 {
1357         u32 i;
1358         int err;
1359
1360         err = 0;
1361         for (i = 0; i < n_cmd; i++) {
1362                 struct tegra_dsi_cmd *cur_cmd;
1363                 cur_cmd = &cmd[i];
1364
1365                 if (cur_cmd->cmd_type == TEGRA_DSI_DELAY_MS)
1366                         mdelay(cur_cmd->sp_len_dly.delay_ms);
1367                 else {
1368                         err = tegra_dsi_write_data(dc, dsi,
1369                                                 cur_cmd->pdata,
1370                                                 cur_cmd->data_id,
1371                                                 cur_cmd->sp_len_dly.data_len);
1372                         if (err < 0)
1373                                 break;
1374                 }
1375         }
1376         return err;
1377 }
1378
1379 static int tegra_dsi_bta(struct tegra_dc_dsi_data *dsi)
1380 {
1381         u32 val;
1382         u32 poll_time;
1383         int err;
1384
1385         poll_time = 0;
1386         err = 0;
1387
1388         val = tegra_dsi_readl(dsi, DSI_HOST_DSI_CONTROL);
1389         val |= DSI_HOST_DSI_CONTROL_IMM_BTA(TEGRA_DSI_ENABLE);
1390         tegra_dsi_writel(dsi, val, DSI_HOST_DSI_CONTROL);
1391
1392 #if DSI_USE_SYNC_POINTS
1393         /* FIXME: Workaround for nvhost_syncpt_read */
1394         dsi->syncpt_val = nvhost_syncpt_update_min(
1395                         &dsi->dc->ndev->host->syncpt, dsi->syncpt_id);
1396
1397         val = DSI_INCR_SYNCPT_COND(OP_DONE) |
1398                 DSI_INCR_SYNCPT_INDX(dsi->syncpt_id);
1399         tegra_dsi_writel(dsi, val, DSI_INCR_SYNCPT);
1400
1401         /* TODO: Use interrupt rather than polling */
1402         err = nvhost_syncpt_wait(&dsi->dc->ndev->host->syncpt,
1403                 dsi->syncpt_id, dsi->syncpt_val + 1);
1404         if (err < 0)
1405                 printk(KERN_ERR "DSI sync point failure\n");
1406         else
1407                 (dsi->syncpt_val)++;
1408 #else
1409         while (poll_time <  DSI_STATUS_POLLING_DURATION_USEC) {
1410                 val = tegra_dsi_readl(dsi, DSI_HOST_DSI_CONTROL);
1411                 val &= DSI_HOST_DSI_CONTROL_IMM_BTA(TEGRA_DSI_ENABLE);
1412                 if (!val)
1413                         break;
1414                 udelay(DSI_STATUS_POLLING_DELAY_USEC);
1415                 poll_time += DSI_STATUS_POLLING_DELAY_USEC;
1416         }
1417         if (poll_time > DSI_STATUS_POLLING_DURATION_USEC)
1418                 err = -EBUSY;
1419 #endif
1420
1421         return err;
1422 }
1423
1424 static void tegra_dsi_read_fifo(struct tegra_dc *dc,
1425                         struct tegra_dc_dsi_data *dsi,
1426                         u32 rd_fifo_cnt,
1427                         u8 *read_fifo)
1428 {
1429         u32 val;
1430         u32 i;
1431
1432         /* Read data from FIFO */
1433         for (i = 0; i < rd_fifo_cnt; i++) {
1434                 val = tegra_dsi_readl(dsi, DSI_RD_DATA);
1435                 printk(KERN_INFO "Read data[%d]: 0x%x\n", i, val);
1436                 memcpy(read_fifo, &val, 4);
1437                 read_fifo += 4;
1438         }
1439
1440         /* Make sure all the data is read from the FIFO */
1441         val = tegra_dsi_readl(dsi, DSI_STATUS);
1442         val &= DSI_STATUS_RD_FIFO_COUNT(0x1f);
1443         if (val)
1444                 dev_err(&dc->ndev->dev, "DSI FIFO_RD_CNT not zero"
1445                 " even after reading FIFO_RD_CNT words from read fifo\n");
1446 }
1447
1448 static int tegra_dsi_parse_read_response(struct tegra_dc *dc,
1449                                 u32 rd_fifo_cnt, u8 *read_fifo)
1450 {
1451         int err;
1452         u32 payload_size;
1453
1454         payload_size = 0;
1455         err = 0;
1456
1457         printk(KERN_INFO "escape sequence[0x%x]\n", read_fifo[0]);
1458         switch (read_fifo[4] & 0xff) {
1459         case GEN_LONG_RD_RES:
1460                 /* Fall through */
1461         case DCS_LONG_RD_RES:
1462                 payload_size = (read_fifo[5] |
1463                                 (read_fifo[6] << 8)) & 0xFFFF;
1464                 printk(KERN_INFO "Long read response Packet\n"
1465                                 "payload_size[0x%x]\n", payload_size);
1466                 break;
1467         case GEN_1_BYTE_SHORT_RD_RES:
1468                 /* Fall through */
1469         case DCS_1_BYTE_SHORT_RD_RES:
1470                 payload_size = 1;
1471                 printk(KERN_INFO "Short read response Packet\n"
1472                         "payload_size[0x%x]\n", payload_size);
1473                 break;
1474         case GEN_2_BYTE_SHORT_RD_RES:
1475                 /* Fall through */
1476         case DCS_2_BYTE_SHORT_RD_RES:
1477                 payload_size = 2;
1478                 printk(KERN_INFO "Short read response Packet\n"
1479                         "payload_size[0x%x]\n", payload_size);
1480                 break;
1481         case ACK_ERR_RES:
1482                 payload_size = 2;
1483                 printk(KERN_INFO "Acknowledge error report response\n"
1484                         "Packet payload_size[0x%x]\n", payload_size);
1485                 break;
1486         default:
1487                 /*reading from RD_FIFO_COUNT*/
1488                 printk(KERN_INFO "Invalid read response payload_size\n");
1489                 err = -EINVAL;
1490                 break;
1491         }
1492         return err;
1493 }
1494
1495 static int tegra_dsi_read_data(struct tegra_dc *dc,
1496                                 struct tegra_dc_dsi_data *dsi,
1497                                 u32 max_ret_payload_size,
1498                                 u32 panel_reg_addr, u8 *read_data)
1499 {
1500         u32 val;
1501         int err;
1502         u32 poll_time;
1503         u32 rd_fifo_cnt;
1504         bool switch_back_to_hs_mode;
1505         bool restart_dc_stream;
1506         bool switch_back_to_dc_mode;
1507
1508         err = 0;
1509         switch_back_to_hs_mode = false;
1510         restart_dc_stream = false;
1511         switch_back_to_dc_mode = false;
1512
1513         if ((dsi->status.init != DSI_MODULE_INIT) ||
1514                 (dsi->status.lphs == DSI_LPHS_NOT_INIT) ||
1515                 (dsi->status.driven == DSI_DRIVEN_MODE_NOT_INIT)) {
1516                 err = -EPERM;
1517                 goto fail;
1518         }
1519
1520         val = tegra_dsi_readl(dsi, DSI_STATUS);
1521         val &= DSI_STATUS_RD_FIFO_COUNT(0x1f);
1522         if (val) {
1523                 err = -EBUSY;
1524                 dev_err(&dc->ndev->dev, "DSI fifo count not zero\n");
1525                 goto fail;
1526         }
1527
1528         if (!tegra_dsi_is_controller_idle(dsi)) {
1529                 err = -EBUSY;
1530                 dev_err(&dc->ndev->dev, "DSI trigger bit is already set\n");
1531                 goto fail;
1532         }
1533
1534         if (dsi->status.lphs == DSI_LPHS_IN_HS_MODE) {
1535                 if (dsi->status.driven == DSI_DRIVEN_MODE_DC) {
1536                         if (dsi->status.dc_stream == DSI_DC_STREAM_ENABLE)
1537                                 restart_dc_stream = true;
1538                         dsi->driven_mode = TEGRA_DSI_DRIVEN_BY_HOST;
1539                         switch_back_to_dc_mode = true;
1540                         if (dsi->info.hs_cmd_mode_supported) {
1541                                 err = tegra_dsi_set_to_hs_mode(dc, dsi);
1542                                 if (err < 0) {
1543                                         dev_err(&dc->ndev->dev,
1544                                         "DSI failed to go to HS mode host driven\n");
1545                                         goto fail;
1546                                 }
1547                         }
1548                 }
1549                 if (!dsi->info.hs_cmd_mode_supported) {
1550                         err = tegra_dsi_set_to_lp_mode(dc, dsi);
1551                         if (err < 0) {
1552                                 dev_err(&dc->ndev->dev,
1553                                 "DSI failed to go to LP mode\n");
1554                                 goto fail;
1555                         }
1556                         switch_back_to_hs_mode = true;
1557                 }
1558         }
1559
1560         /* Set max return payload size in words */
1561         err = _tegra_dsi_write_data(dsi, NULL,
1562                 dsi_command_max_return_pkt_size,
1563                 max_ret_payload_size);
1564         if (err < 0) {
1565                 dev_err(&dc->ndev->dev,
1566                                 "DSI write failed\n");
1567                 goto fail;
1568         }
1569
1570         /* DCS to read given panel register */
1571         err = _tegra_dsi_write_data(dsi, NULL,
1572                 dsi_command_dcs_read_with_no_params,
1573                 panel_reg_addr);
1574         if (err < 0) {
1575                 dev_err(&dc->ndev->dev,
1576                                 "DSI write failed\n");
1577                 goto fail;
1578         }
1579
1580         err = tegra_dsi_bta(dsi);
1581         if (err < 0) {
1582                 dev_err(&dc->ndev->dev,
1583                         "DSI IMM BTA timeout\n");
1584                 goto fail;
1585         }
1586
1587         poll_time = 0;
1588         while (poll_time <  DSI_DELAY_FOR_READ_FIFO) {
1589                 mdelay(1);
1590                 val = tegra_dsi_readl(dsi, DSI_STATUS);
1591                 rd_fifo_cnt = val & DSI_STATUS_RD_FIFO_COUNT(0x1f);
1592                 if (rd_fifo_cnt << 2 > DSI_READ_FIFO_DEPTH)
1593                         dev_err(&dc->ndev->dev,
1594                         "DSI RD_FIFO_CNT is greater than RD_FIFO_DEPTH\n");
1595                         break;
1596                 poll_time++;
1597         }
1598
1599         if (rd_fifo_cnt == 0) {
1600                 dev_info(&dc->ndev->dev,
1601                         "DSI RD_FIFO_CNT is zero\n");
1602                 err = -EINVAL;
1603                 goto fail;
1604         }
1605
1606         if (val & DSI_STATUS_LB_UNDERFLOW(0x1) ||
1607                 val & DSI_STATUS_LB_OVERFLOW(0x1)) {
1608                 dev_err(&dc->ndev->dev,
1609                         "DSI overflow/underflow error\n");
1610                 err = -EINVAL;
1611                 goto fail;
1612         }
1613
1614         tegra_dsi_read_fifo(dc, dsi, rd_fifo_cnt, read_data);
1615
1616         err = tegra_dsi_parse_read_response(dc, rd_fifo_cnt, read_data);
1617 fail:
1618         if (switch_back_to_dc_mode)
1619                 dsi->driven_mode = TEGRA_DSI_DRIVEN_BY_DC;
1620         if (switch_back_to_dc_mode || switch_back_to_hs_mode)
1621                 tegra_dsi_set_to_hs_mode(dc, dsi);
1622         if (restart_dc_stream)
1623                 tegra_dsi_start_dc_stream(dc, dsi);
1624
1625         return err;
1626 }
1627
1628 static int tegra_dsi_enter_ulpm(struct tegra_dc_dsi_data *dsi)
1629 {
1630         u32 val;
1631         int ret;
1632
1633         ret = 0;
1634
1635         val = tegra_dsi_readl(dsi, DSI_HOST_DSI_CONTROL);
1636         val &= ~DSI_HOST_DSI_CONTROL_ULTRA_LOW_POWER(3);
1637         val |= DSI_HOST_DSI_CONTROL_ULTRA_LOW_POWER(ENTER_ULPM);
1638         tegra_dsi_writel(dsi, val, DSI_HOST_DSI_CONTROL);
1639
1640 #if DSI_USE_SYNC_POINTS
1641         ret = tegra_dsi_syncpt(dsi);
1642         if (ret < 0) {
1643                 printk(KERN_ERR "DSI syncpt for ulpm enter failed\n");
1644                 goto fail;
1645         }
1646 #else
1647         /* TODO: Find exact delay required */
1648         mdelay(10);
1649 #endif
1650         dsi->ulpm = true;
1651 fail:
1652         return ret;
1653 }
1654
1655 static int tegra_dsi_exit_ulpm(struct tegra_dc_dsi_data *dsi)
1656 {
1657         u32 val;
1658         int ret;
1659
1660         ret = 0;
1661
1662         val = tegra_dsi_readl(dsi, DSI_HOST_DSI_CONTROL);
1663         val &= ~DSI_HOST_DSI_CONTROL_ULTRA_LOW_POWER(3);
1664         val |= DSI_HOST_DSI_CONTROL_ULTRA_LOW_POWER(EXIT_ULPM);
1665         tegra_dsi_writel(dsi, val, DSI_HOST_DSI_CONTROL);
1666
1667 #if DSI_USE_SYNC_POINTS
1668         ret = tegra_dsi_syncpt(dsi);
1669         if (ret < 0) {
1670                 printk(KERN_ERR "DSI syncpt for ulpm exit failed\n");
1671                 goto fail;
1672         }
1673 #else
1674         /* TODO: Find exact delay required */
1675         mdelay(10);
1676 #endif
1677         dsi->ulpm = false;
1678
1679         val = tegra_dsi_readl(dsi, DSI_HOST_DSI_CONTROL);
1680         val &= ~DSI_HOST_DSI_CONTROL_ULTRA_LOW_POWER(0x3);
1681         val |= DSI_HOST_DSI_CONTROL_ULTRA_LOW_POWER(NORMAL);
1682         tegra_dsi_writel(dsi, val, DSI_HOST_DSI_CONTROL);
1683 fail:
1684         return ret;
1685
1686 }
1687
1688 static void tegra_dc_dsi_enable(struct tegra_dc *dc)
1689 {
1690         struct tegra_dc_dsi_data *dsi = tegra_dc_get_outdata(dc);
1691         int err;
1692         u32 val;
1693
1694         tegra_dc_io_start(dc);
1695         mutex_lock(&dsi->lock);
1696
1697         /* Stop DC stream before configuring DSI registers
1698          * to avoid visible glitches on panel during transition
1699          * from bootloader to kernel driver
1700          */
1701         tegra_dsi_stop_dc_stream_at_frame_end(dc, dsi);
1702
1703         if (dsi->enabled) {
1704                 if (dsi->ulpm) {
1705                         if (tegra_dsi_exit_ulpm(dsi) < 0) {
1706                                 printk(KERN_ERR "DSI failed to exit ulpm\n");
1707                                 goto fail;
1708                         }
1709                 }
1710
1711                 if (dsi->info.panel_reset) {
1712                         err = tegra_dsi_send_panel_cmd(dc, dsi,
1713                                                         dsi->info.dsi_init_cmd,
1714                                                         dsi->info.n_init_cmd);
1715                         if (err < 0) {
1716                                 dev_err(&dc->ndev->dev,
1717                                 "dsi: error sending dsi init cmd\n");
1718                                 goto fail;
1719                         }
1720                 } else if (dsi->info.dsi_late_resume_cmd) {
1721                         err = tegra_dsi_send_panel_cmd(dc, dsi,
1722                                                 dsi->info.dsi_late_resume_cmd,
1723                                                 dsi->info.n_late_resume_cmd);
1724                         if (err < 0) {
1725                                 dev_err(&dc->ndev->dev,
1726                                 "dsi: error sending late resume cmd\n");
1727                                 goto fail;
1728                         }
1729                 }
1730
1731                 err = tegra_dsi_set_to_hs_mode(dc, dsi);
1732                 if (err < 0) {
1733                         dev_err(&dc->ndev->dev,
1734                                 "dsi: not able to set to hs mode\n");
1735                         goto fail;
1736                 }
1737         } else {
1738                 err = tegra_dsi_init_hw(dc, dsi);
1739                 if (err < 0) {
1740                         dev_err(&dc->ndev->dev,
1741                                 "dsi: not able to init dsi hardware\n");
1742                         goto fail;
1743                 }
1744
1745                 if (dsi->ulpm) {
1746                         if (tegra_dsi_enter_ulpm(dsi) < 0) {
1747                                 printk(KERN_ERR "DSI failed to enter ulpm\n");
1748                                 goto fail;
1749                         }
1750                         val = DSI_PAD_CONTROL_PAD_PDIO(0) |
1751                                 DSI_PAD_CONTROL_PAD_PDIO_CLK(0) |
1752                                 DSI_PAD_CONTROL_PAD_PULLDN_ENAB(TEGRA_DSI_DISABLE);
1753                         tegra_dsi_writel(dsi, val, DSI_PAD_CONTROL);
1754                         if (tegra_dsi_exit_ulpm(dsi) < 0) {
1755                                 printk(KERN_ERR "DSI failed to exit ulpm\n");
1756                                 goto fail;
1757                         }
1758                 }
1759
1760                 err = tegra_dsi_set_to_lp_mode(dc, dsi);
1761                 if (err < 0) {
1762                         dev_err(&dc->ndev->dev,
1763                                 "dsi: not able to set to lp mode\n");
1764                         goto fail;
1765                 }
1766
1767                 err = tegra_dsi_send_panel_cmd(dc, dsi, dsi->info.dsi_init_cmd,
1768                                                 dsi->info.n_init_cmd);
1769                 if (err < 0) {
1770                         dev_err(&dc->ndev->dev,
1771                                 "dsi: error while sending dsi init cmd\n");
1772                         goto fail;
1773                 }
1774
1775                 err = tegra_dsi_set_to_hs_mode(dc, dsi);
1776                 if (err < 0) {
1777                         dev_err(&dc->ndev->dev,
1778                                 "dsi: not able to set to hs mode\n");
1779                         goto fail;
1780                 }
1781
1782                 dsi->enabled = true;
1783         }
1784
1785         if (dsi->status.driven == DSI_DRIVEN_MODE_DC)
1786                 tegra_dsi_start_dc_stream(dc, dsi);
1787 fail:
1788         mutex_unlock(&dsi->lock);
1789         tegra_dc_io_end(dc);
1790 }
1791
1792 static void _tegra_dc_dsi_init(struct tegra_dc *dc)
1793 {
1794         struct tegra_dc_dsi_data *dsi = tegra_dc_get_outdata(dc);
1795
1796         tegra_dsi_init_sw(dc, dsi);
1797         /* TODO: Configure the CSI pad configuration */
1798 }
1799
1800 static int tegra_dc_dsi_cp_p_cmd(struct tegra_dsi_cmd* src,
1801                                         struct tegra_dsi_cmd* dst, u16 n_cmd)
1802 {
1803         u16 i;
1804         u16 len;
1805
1806         memcpy(dst, src, sizeof(*dst) * n_cmd);
1807
1808         for (i = 0; i < n_cmd; i++)
1809                 if (src[i].pdata) {
1810                         len = sizeof(*src[i].pdata) * src[i].sp_len_dly.data_len;
1811                         dst[i].pdata = kzalloc(len, GFP_KERNEL);
1812                         if (!dst[i].pdata)
1813                                 goto free_cmd_pdata;
1814                         memcpy(dst[i].pdata, src[i].pdata, len);
1815                 }
1816
1817         return 0;
1818
1819 free_cmd_pdata:
1820         for (--i; i >=0; i--)
1821                 if (dst[i].pdata)
1822                         kfree(dst[i].pdata);
1823         return -ENOMEM;
1824 }
1825
1826 static int tegra_dc_dsi_cp_info(struct tegra_dc_dsi_data* dsi,
1827                                                 struct tegra_dsi_out* p_dsi)
1828 {
1829         struct tegra_dsi_cmd *p_init_cmd;
1830         struct tegra_dsi_cmd *p_early_suspend_cmd;
1831         struct tegra_dsi_cmd *p_late_resume_cmd;
1832         struct tegra_dsi_cmd *p_suspend_cmd;
1833         int err;
1834
1835         if (p_dsi->n_data_lanes > MAX_DSI_DATA_LANES)
1836                 return -EINVAL;
1837
1838         p_init_cmd = kzalloc(sizeof(*p_init_cmd) *
1839                                 p_dsi->n_init_cmd, GFP_KERNEL);
1840         if (!p_init_cmd)
1841                 return -ENOMEM;
1842
1843         if (p_dsi->dsi_early_suspend_cmd) {
1844                 p_early_suspend_cmd = kzalloc(sizeof(*p_early_suspend_cmd) *
1845                                         p_dsi->n_early_suspend_cmd,
1846                                         GFP_KERNEL);
1847                 if (!p_early_suspend_cmd) {
1848                         err = -ENOMEM;
1849                         goto err_free_init_cmd;
1850                 }
1851         }
1852
1853         if (p_dsi->dsi_late_resume_cmd) {
1854                 p_late_resume_cmd = kzalloc(sizeof(*p_late_resume_cmd) *
1855                                         p_dsi->n_late_resume_cmd,
1856                                         GFP_KERNEL);
1857                 if (!p_late_resume_cmd) {
1858                         err = -ENOMEM;
1859                         goto err_free_p_early_suspend_cmd;
1860                 }
1861         }
1862
1863         p_suspend_cmd = kzalloc(sizeof(*p_suspend_cmd) * p_dsi->n_suspend_cmd,
1864                                 GFP_KERNEL);
1865         if (!p_suspend_cmd) {
1866                 err = -ENOMEM;
1867                 goto err_free_p_late_resume_cmd;
1868         }
1869
1870         memcpy(&dsi->info, p_dsi, sizeof(dsi->info));
1871
1872         /* Copy panel init cmd */
1873         err = tegra_dc_dsi_cp_p_cmd(p_dsi->dsi_init_cmd,
1874                                                 p_init_cmd, p_dsi->n_init_cmd);
1875         if (err < 0)
1876                 goto err_free;
1877         dsi->info.dsi_init_cmd = p_init_cmd;
1878
1879         /* Copy panel early suspend cmd */
1880         if (p_dsi->dsi_early_suspend_cmd) {
1881                 err = tegra_dc_dsi_cp_p_cmd(p_dsi->dsi_early_suspend_cmd,
1882                                         p_early_suspend_cmd,
1883                                         p_dsi->n_early_suspend_cmd);
1884                 if (err < 0)
1885                         goto err_free;
1886                 dsi->info.dsi_early_suspend_cmd = p_early_suspend_cmd;
1887         }
1888
1889         /* Copy panel late resume cmd */
1890         if (p_dsi->dsi_late_resume_cmd) {
1891                 err = tegra_dc_dsi_cp_p_cmd(p_dsi->dsi_late_resume_cmd,
1892                                                 p_late_resume_cmd,
1893                                                 p_dsi->n_late_resume_cmd);
1894                 if (err < 0)
1895                         goto err_free;
1896                 dsi->info.dsi_late_resume_cmd = p_late_resume_cmd;
1897         }
1898
1899         /* Copy panel suspend cmd */
1900         err = tegra_dc_dsi_cp_p_cmd(p_dsi->dsi_suspend_cmd, p_suspend_cmd,
1901                                         p_dsi->n_suspend_cmd);
1902         if (err < 0)
1903                 goto err_free;
1904         dsi->info.dsi_suspend_cmd = p_suspend_cmd;
1905
1906         if (!dsi->info.panel_reset_timeout_msec)
1907                 dsi->info.panel_reset_timeout_msec = DEFAULT_PANEL_RESET_TIMEOUT;
1908
1909         if (!dsi->info.panel_buffer_size_byte)
1910                 dsi->info.panel_buffer_size_byte = DEFAULT_PANEL_BUFFER_BYTE;
1911
1912         if (!dsi->info.max_panel_freq_khz) {
1913                 dsi->info.max_panel_freq_khz = DEFAULT_MAX_DSI_PHY_CLK_KHZ;
1914
1915                 if (dsi->info.video_burst_mode >
1916                                 TEGRA_DSI_VIDEO_NONE_BURST_MODE_WITH_SYNC_END){
1917                         dev_err(&dsi->dc->ndev->dev, "DSI: max_panel_freq_khz"
1918                                         "is not set for DSI burst mode.\n");
1919                         dsi->info.video_burst_mode =
1920                                 TEGRA_DSI_VIDEO_BURST_MODE_LOWEST_SPEED;
1921                 }
1922         }
1923
1924         if (!dsi->info.lp_cmd_mode_freq_khz)
1925                 dsi->info.lp_cmd_mode_freq_khz = DEFAULT_LP_CMD_MODE_CLK_KHZ;
1926
1927         /* host mode is for testing only*/
1928         dsi->driven_mode = TEGRA_DSI_DRIVEN_BY_DC;
1929
1930         return 0;
1931
1932 err_free:
1933         kfree(p_suspend_cmd);
1934 err_free_p_late_resume_cmd:
1935         kfree(p_late_resume_cmd);
1936 err_free_p_early_suspend_cmd:
1937         kfree(p_early_suspend_cmd);
1938 err_free_init_cmd:
1939         kfree(p_init_cmd);
1940         return err;
1941 }
1942
1943 static int tegra_dc_dsi_init(struct tegra_dc *dc)
1944 {
1945         struct tegra_dc_dsi_data *dsi;
1946         struct resource *res;
1947         struct resource *base_res;
1948         void __iomem *base;
1949         struct clk *dc_clk = NULL;
1950         struct clk *dsi_clk = NULL;
1951         struct tegra_dsi_out *dsi_pdata;
1952         int err;
1953
1954         err = 0;
1955
1956         dsi = kzalloc(sizeof(*dsi), GFP_KERNEL);
1957         if (!dsi)
1958                 return -ENOMEM;
1959
1960         res = nvhost_get_resource_byname(dc->ndev, IORESOURCE_MEM,
1961                                         "dsi_regs");
1962         if (!res) {
1963                 dev_err(&dc->ndev->dev, "dsi: no mem resource\n");
1964                 err = -ENOENT;
1965                 goto err_free_dsi;
1966         }
1967
1968         base_res = request_mem_region(res->start, resource_size(res),
1969                                 dc->ndev->name);
1970         if (!base_res) {
1971                 dev_err(&dc->ndev->dev, "dsi: request_mem_region failed\n");
1972                 err = -EBUSY;
1973                 goto err_free_dsi;
1974         }
1975
1976         base = ioremap(res->start, resource_size(res));
1977         if (!base) {
1978                 dev_err(&dc->ndev->dev, "dsi: registers can't be mapped\n");
1979                 err = -EBUSY;
1980                 goto err_release_regs;
1981         }
1982
1983         dsi_pdata = dc->pdata->default_out->dsi;
1984         if (!dsi_pdata) {
1985                 dev_err(&dc->ndev->dev, "dsi: dsi data not available\n");
1986                 goto err_release_regs;
1987         }
1988
1989         if (dsi_pdata->dsi_instance)
1990                 dsi_clk = clk_get(&dc->ndev->dev, "dsib");
1991         else
1992                 dsi_clk = clk_get(&dc->ndev->dev, "dsia");
1993
1994         if (IS_ERR_OR_NULL(dsi_clk)) {
1995                 dev_err(&dc->ndev->dev, "dsi: can't get clock\n");
1996                 err = -EBUSY;
1997                 goto err_release_regs;
1998         }
1999
2000         dc_clk = clk_get_sys(dev_name(&dc->ndev->dev), NULL);
2001         if (IS_ERR_OR_NULL(dc_clk)) {
2002                 dev_err(&dc->ndev->dev, "dsi: dc clock %s unavailable\n",
2003                         dev_name(&dc->ndev->dev));
2004                 err = -EBUSY;
2005                 goto err_clk_put;
2006         }
2007
2008         mutex_init(&dsi->lock);
2009         dsi->dc = dc;
2010         dsi->base = base;
2011         dsi->base_res = base_res;
2012         dsi->dc_clk = dc_clk;
2013         dsi->dsi_clk = dsi_clk;
2014
2015         err = tegra_dc_dsi_cp_info(dsi, dsi_pdata);
2016         if (err < 0)
2017                 goto err_dsi_data;
2018
2019         tegra_dc_set_outdata(dc, dsi);
2020         _tegra_dc_dsi_init(dc);
2021
2022         return 0;
2023
2024 err_dsi_data:
2025 err_clk_put:
2026         clk_put(dsi_clk);
2027 err_release_regs:
2028         release_resource(base_res);
2029 err_free_dsi:
2030         kfree(dsi);
2031
2032         return err;
2033 }
2034
2035 static void tegra_dc_dsi_destroy(struct tegra_dc *dc)
2036 {
2037         struct tegra_dc_dsi_data *dsi = tegra_dc_get_outdata(dc);
2038         u16 i;
2039         u32 val;
2040
2041         mutex_lock(&dsi->lock);
2042
2043         /* free up the pdata*/
2044         for(i = 0; i < dsi->info.n_init_cmd; i++){
2045                 if(dsi->info.dsi_init_cmd[i].pdata)
2046                         kfree(dsi->info.dsi_init_cmd[i].pdata);
2047         }
2048         kfree(dsi->info.dsi_init_cmd);
2049
2050         /* Disable dc stream*/
2051         if(dsi->status.dc_stream == DSI_DC_STREAM_ENABLE)
2052                 tegra_dsi_stop_dc_stream(dc, dsi);
2053
2054         /* Disable dsi phy clock*/
2055         if(dsi->status.clk_out == DSI_PHYCLK_OUT_EN)
2056                 tegra_dsi_hs_clk_out_disable(dc, dsi);
2057
2058         val = DSI_POWER_CONTROL_LEG_DSI_ENABLE(TEGRA_DSI_DISABLE);
2059         tegra_dsi_writel(dsi, val, DSI_POWER_CONTROL);
2060
2061         iounmap(dsi->base);
2062         release_resource(dsi->base_res);
2063
2064         clk_put(dsi->dc_clk);
2065         clk_put(dsi->dsi_clk);
2066
2067         mutex_unlock(&dsi->lock);
2068
2069         mutex_destroy(&dsi->lock);
2070         kfree(dsi);
2071 }
2072
2073 static void tegra_dc_dsi_disable(struct tegra_dc *dc)
2074 {
2075         int err;
2076         struct tegra_dc_dsi_data *dsi = tegra_dc_get_outdata(dc);
2077
2078         tegra_dc_io_start(dc);
2079         mutex_lock(&dsi->lock);
2080
2081         if (dsi->status.dc_stream == DSI_DC_STREAM_ENABLE)
2082                 tegra_dsi_stop_dc_stream(dc, dsi);
2083
2084         if (dsi->info.dsi_early_suspend_cmd) {
2085                 err = tegra_dsi_send_panel_cmd(dc, dsi,
2086                         dsi->info.dsi_early_suspend_cmd,
2087                         dsi->info.n_early_suspend_cmd);
2088                 if (err < 0) {
2089                         dev_err(&dc->ndev->dev,
2090                                 "dsi: Error sending early suspend cmd\n");
2091                         goto fail;
2092                 }
2093         }
2094
2095         err = tegra_dsi_set_to_lp_mode(dc, dsi);
2096         if (err < 0) {
2097                 dev_err(&dc->ndev->dev,
2098                         "dsi: not able to set to lp mode\n");
2099                 goto fail;
2100         }
2101
2102         if (!dsi->ulpm) {
2103                 if (tegra_dsi_enter_ulpm(dsi) < 0)
2104                         printk(KERN_ERR "DSI failed to enter ulpm\n");
2105         }
2106 fail:
2107         mutex_unlock(&dsi->lock);
2108         tegra_dc_io_end(dc);
2109 }
2110
2111 #ifdef CONFIG_PM
2112 static void tegra_dc_dsi_suspend(struct tegra_dc *dc)
2113 {
2114         struct tegra_dc_dsi_data *dsi;
2115         int err;
2116         u32 val;
2117
2118         dsi = tegra_dc_get_outdata(dc);
2119
2120         tegra_dc_io_start(dc);
2121         mutex_lock(&dsi->lock);
2122
2123         if (!dsi->enabled)
2124                 goto fail;
2125
2126         if (dsi->ulpm) {
2127                 if (tegra_dsi_exit_ulpm(dsi) < 0) {
2128                         printk(KERN_ERR "DSI failed to exit ulpm");
2129                         goto fail;
2130                 }
2131         }
2132
2133         /* Suspend Panel */
2134         err = tegra_dsi_send_panel_cmd(dc, dsi,
2135                         dsi->info.dsi_suspend_cmd,
2136                         dsi->info.n_suspend_cmd);
2137         if (err < 0) {
2138                 dev_err(&dc->ndev->dev,
2139                         "dsi: Error sending suspend cmd\n");
2140                 goto fail;
2141         }
2142         if (!dsi->ulpm) {
2143                 if (tegra_dsi_enter_ulpm(dsi) < 0) {
2144                         printk(KERN_ERR "DSI failed to enter ulpm\n");
2145                         goto fail;
2146                 }
2147         }
2148
2149         /* Suspend pad */
2150         val = tegra_dsi_readl(dsi, DSI_PAD_CONTROL);
2151         val = DSI_PAD_CONTROL_PAD_PDIO(0x3) |
2152                 DSI_PAD_CONTROL_PAD_PDIO_CLK(0x1) |
2153                 DSI_PAD_CONTROL_PAD_PULLDN_ENAB(TEGRA_DSI_ENABLE);
2154         tegra_dsi_writel(dsi, val, DSI_PAD_CONTROL);
2155
2156         /* Suspend core-logic */
2157         val = DSI_POWER_CONTROL_LEG_DSI_ENABLE(TEGRA_DSI_DISABLE);
2158         tegra_dsi_writel(dsi, val, DSI_POWER_CONTROL);
2159
2160         dsi->enabled = false;
2161
2162         clk_disable(dsi->dsi_clk);
2163         dsi->clk_ref = false;
2164 fail:
2165         mutex_unlock(&dsi->lock);
2166         tegra_dc_io_end(dc);
2167 }
2168
2169 static void tegra_dc_dsi_resume(struct tegra_dc *dc)
2170 {
2171         /* Not required since tegra_dc_dsi_enable
2172          * will reconfigure the controller from scratch
2173          */
2174 }
2175 #endif
2176
2177 struct tegra_dc_out_ops tegra_dc_dsi_ops = {
2178         .init = tegra_dc_dsi_init,
2179         .destroy = tegra_dc_dsi_destroy,
2180         .enable = tegra_dc_dsi_enable,
2181         .disable = tegra_dc_dsi_disable,
2182 #ifdef CONFIG_PM
2183         .suspend = tegra_dc_dsi_suspend,
2184         .resume = tegra_dc_dsi_resume,
2185 #endif
2186 };