video: tegra: dsi: Add phy timing check for hblank
[linux-2.6.git] / drivers / video / tegra / dc / dsi.c
1 /*
2  * drivers/video/tegra/dc/dsi.c
3  *
4  * Copyright (c) 2011, NVIDIA Corporation.
5  *
6  * This software is licensed under the terms of the GNU General Public
7  * License version 2, as published by the Free Software Foundation, and
8  * may be copied, distributed, and modified under those terms.
9  *
10  * This program is distributed in the hope that it will be useful,
11  * but WITHOUT ANY WARRANTY; without even the implied warranty of
12  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
13  * GNU General Public License for more details.
14  *
15  */
16
17 #include <linux/clk.h>
18 #include <linux/delay.h>
19 #include <linux/err.h>
20 #include <linux/fb.h>
21 #include <linux/gpio.h>
22 #include <linux/interrupt.h>
23 #include <linux/kernel.h>
24 #include <linux/slab.h>
25 #include <linux/spinlock.h>
26 #include <linux/workqueue.h>
27
28 #include <mach/clk.h>
29 #include <mach/dc.h>
30 #include <mach/fb.h>
31 #include <mach/csi.h>
32 #include <linux/nvhost.h>
33
34 #include "dc_reg.h"
35 #include "dc_priv.h"
36 #include "dsi_regs.h"
37 #include "dsi.h"
38
39 #define DSI_USE_SYNC_POINTS             1
40 #define S_TO_MS(x)                      (1000 * (x))
41
42 #define DSI_MODULE_NOT_INIT             0x0
43 #define DSI_MODULE_INIT                 0x1
44
45 #define DSI_LPHS_NOT_INIT               0x0
46 #define DSI_LPHS_IN_LP_MODE             0x1
47 #define DSI_LPHS_IN_HS_MODE             0x2
48
49 #define DSI_VIDEO_TYPE_NOT_INIT         0x0
50 #define DSI_VIDEO_TYPE_VIDEO_MODE       0x1
51 #define DSI_VIDEO_TYPE_CMD_MODE         0x2
52
53 #define DSI_DRIVEN_MODE_NOT_INIT        0x0
54 #define DSI_DRIVEN_MODE_DC              0x1
55 #define DSI_DRIVEN_MODE_HOST            0x2
56
57 #define DSI_PHYCLK_OUT_DIS              0x0
58 #define DSI_PHYCLK_OUT_EN               0x1
59
60 #define DSI_PHYCLK_NOT_INIT             0x0
61 #define DSI_PHYCLK_CONTINUOUS           0x1
62 #define DSI_PHYCLK_TX_ONLY              0x2
63
64 #define DSI_CLK_BURST_NOT_INIT          0x0
65 #define DSI_CLK_BURST_NONE_BURST        0x1
66 #define DSI_CLK_BURST_BURST_MODE        0x2
67
68 #define DSI_DC_STREAM_DISABLE           0x0
69 #define DSI_DC_STREAM_ENABLE            0x1
70
71 #define DSI_LP_OP_NOT_INIT              0x0
72 #define DSI_LP_OP_WRITE                 0x1
73 #define DSI_LP_OP_READ                  0x2
74
75 static bool enable_read_debug;
76 module_param(enable_read_debug, bool, 0644);
77 MODULE_PARM_DESC(enable_read_debug,
78                 "Enable to print read fifo and return packet type");
79
80 struct dsi_status {
81         unsigned init:2;
82
83         unsigned lphs:2;
84
85         unsigned vtype:2;
86         unsigned driven:2;
87
88         unsigned clk_out:2;
89         unsigned clk_mode:2;
90         unsigned clk_burst:2;
91
92         unsigned lp_op:2;
93
94         unsigned dc_stream:1;
95 };
96
97 /* source of video data */
98 enum {
99         TEGRA_DSI_DRIVEN_BY_DC,
100         TEGRA_DSI_DRIVEN_BY_HOST,
101 };
102
103 struct tegra_dc_dsi_data {
104         struct tegra_dc *dc;
105         void __iomem *base;
106         struct resource *base_res;
107
108         struct clk *dc_clk;
109         struct clk *dsi_clk;
110         bool clk_ref;
111
112         struct mutex lock;
113
114         /* data from board info */
115         struct tegra_dsi_out info;
116
117         struct dsi_status status;
118
119         struct dsi_phy_timing_inclk phy_timing;
120
121         u8 driven_mode;
122         u8 controller_index;
123
124         u8 pixel_scaler_mul;
125         u8 pixel_scaler_div;
126
127         u32 default_shift_clk_div;
128         u32 default_pixel_clk_khz;
129         u32 default_hs_clk_khz;
130
131         u32 shift_clk_div;
132         u32 target_hs_clk_khz;
133         u32 target_lp_clk_khz;
134
135         u32 syncpt_id;
136         u32 syncpt_val;
137
138         u16 current_bit_clk_ns;
139         u32 current_dsi_clk_khz;
140
141         u32 dsi_control_val;
142
143         bool ulpm;
144         bool enabled;
145 };
146
147 const u32 dsi_pkt_seq_reg[NUMOF_PKT_SEQ] = {
148         DSI_PKT_SEQ_0_LO,
149         DSI_PKT_SEQ_0_HI,
150         DSI_PKT_SEQ_1_LO,
151         DSI_PKT_SEQ_1_HI,
152         DSI_PKT_SEQ_2_LO,
153         DSI_PKT_SEQ_2_HI,
154         DSI_PKT_SEQ_3_LO,
155         DSI_PKT_SEQ_3_HI,
156         DSI_PKT_SEQ_4_LO,
157         DSI_PKT_SEQ_4_HI,
158         DSI_PKT_SEQ_5_LO,
159         DSI_PKT_SEQ_5_HI,
160 };
161
162 const u32 dsi_pkt_seq_video_non_burst_syne[NUMOF_PKT_SEQ] = {
163         PKT_ID0(CMD_VS) | PKT_LEN0(0) | PKT_ID1(CMD_EOT) | PKT_LEN1(0) | PKT_LP,
164         0,
165         PKT_ID0(CMD_VE) | PKT_LEN0(0) | PKT_ID1(CMD_EOT) | PKT_LEN1(0) | PKT_LP,
166         0,
167         PKT_ID0(CMD_HS) | PKT_LEN0(0) | PKT_ID1(CMD_EOT) | PKT_LEN1(0) | PKT_LP,
168         0,
169         PKT_ID0(CMD_HS) | PKT_LEN0(0) | PKT_ID1(CMD_BLNK) | PKT_LEN1(1) |
170         PKT_ID2(CMD_HE) | PKT_LEN2(0),
171         PKT_ID3(CMD_BLNK) | PKT_LEN3(2) | PKT_ID4(CMD_RGB) | PKT_LEN4(3) |
172         PKT_ID5(CMD_BLNK) | PKT_LEN5(4),
173         PKT_ID0(CMD_HS) | PKT_LEN0(0) | PKT_ID1(CMD_EOT) | PKT_LEN1(0) | PKT_LP,
174         0,
175         PKT_ID0(CMD_HS) | PKT_LEN0(0) | PKT_ID1(CMD_BLNK) | PKT_LEN1(1) |
176         PKT_ID2(CMD_HE) | PKT_LEN2(0),
177         PKT_ID3(CMD_BLNK) | PKT_LEN3(2) | PKT_ID4(CMD_RGB) | PKT_LEN4(3) |
178         PKT_ID5(CMD_BLNK) | PKT_LEN5(4),
179 };
180
181 const u32 dsi_pkt_seq_video_non_burst[NUMOF_PKT_SEQ] = {
182         PKT_ID0(CMD_VS) | PKT_LEN0(0) | PKT_ID1(CMD_EOT) | PKT_LEN1(0) | PKT_LP,
183         0,
184         PKT_ID0(CMD_HS) | PKT_LEN0(0) | PKT_ID1(CMD_EOT) | PKT_LEN1(0) | PKT_LP,
185         0,
186         PKT_ID0(CMD_HS) | PKT_LEN0(0) | PKT_ID1(CMD_EOT) | PKT_LEN1(0) | PKT_LP,
187         0,
188         PKT_ID0(CMD_HS) | PKT_LEN0(0) | PKT_ID1(CMD_BLNK) | PKT_LEN1(2) |
189         PKT_ID2(CMD_RGB) | PKT_LEN2(3),
190         PKT_ID3(CMD_BLNK) | PKT_LEN3(4),
191         PKT_ID0(CMD_HS) | PKT_LEN0(0) | PKT_ID1(CMD_EOT) | PKT_LEN1(0) | PKT_LP,
192         0,
193         PKT_ID0(CMD_HS) | PKT_LEN0(0) | PKT_ID1(CMD_BLNK) | PKT_LEN1(2) |
194         PKT_ID2(CMD_RGB) | PKT_LEN2(3),
195         PKT_ID3(CMD_BLNK) | PKT_LEN3(4),
196 };
197
198 static const u32 dsi_pkt_seq_video_burst[NUMOF_PKT_SEQ] = {
199         PKT_ID0(CMD_VS) | PKT_LEN0(0) | PKT_ID1(CMD_EOT) | PKT_LEN1(7) | PKT_LP,
200         0,
201         PKT_ID0(CMD_HS) | PKT_LEN0(0) | PKT_ID1(CMD_EOT) | PKT_LEN1(7) | PKT_LP,
202         0,
203         PKT_ID0(CMD_HS) | PKT_LEN0(0) | PKT_ID1(CMD_EOT) | PKT_LEN1(7) | PKT_LP,
204         0,
205         PKT_ID0(CMD_HS) | PKT_LEN0(0) | PKT_ID1(CMD_BLNK) | PKT_LEN1(2)|
206         PKT_ID2(CMD_RGB) | PKT_LEN2(3) | PKT_LP,
207         PKT_ID0(CMD_EOT) | PKT_LEN0(7),
208         PKT_ID0(CMD_HS) | PKT_LEN0(0) | PKT_ID1(CMD_EOT) | PKT_LEN1(7) | PKT_LP,
209         0,
210         PKT_ID0(CMD_HS) | PKT_LEN0(0) | PKT_ID1(CMD_BLNK) | PKT_LEN1(2)|
211         PKT_ID2(CMD_RGB) | PKT_LEN2(3) | PKT_LP,
212         PKT_ID0(CMD_EOT) | PKT_LEN0(7),
213 };
214
215 static const u32 dsi_pkt_seq_video_burst_no_eot[NUMOF_PKT_SEQ] = {
216         PKT_ID0(CMD_VS) | PKT_LEN0(0) | PKT_ID1(CMD_EOT) | PKT_LEN1(0) | PKT_LP,
217         0,
218         PKT_ID0(CMD_HS) | PKT_LEN0(0) | PKT_ID1(CMD_EOT) | PKT_LEN1(0) | PKT_LP,
219         0,
220         PKT_ID0(CMD_HS) | PKT_LEN0(0) | PKT_ID1(CMD_EOT) | PKT_LEN1(0) | PKT_LP,
221         0,
222         PKT_ID0(CMD_HS) | PKT_LEN0(0) | PKT_ID1(CMD_BLNK) | PKT_LEN1(2)|
223         PKT_ID2(CMD_RGB) | PKT_LEN2(3) | PKT_LP,
224         PKT_ID0(CMD_EOT) | PKT_LEN0(0),
225         PKT_ID0(CMD_HS) | PKT_LEN0(0) | PKT_ID1(CMD_EOT) | PKT_LEN1(0) | PKT_LP,
226         0,
227         PKT_ID0(CMD_HS) | PKT_LEN0(0) | PKT_ID1(CMD_BLNK) | PKT_LEN1(2)|
228         PKT_ID2(CMD_RGB) | PKT_LEN2(3) | PKT_LP,
229         PKT_ID0(CMD_EOT) | PKT_LEN0(0),
230 };
231
232 /* TODO: verify with hw about this format */
233 const u32 dsi_pkt_seq_cmd_mode[NUMOF_PKT_SEQ] = {
234         0,
235         0,
236         0,
237         0,
238         0,
239         0,
240         PKT_ID0(CMD_LONGW) | PKT_LEN0(3) | PKT_ID1(CMD_EOT) | PKT_LEN1(7),
241         0,
242         0,
243         0,
244         PKT_ID0(CMD_LONGW) | PKT_LEN0(3) | PKT_ID1(CMD_EOT) | PKT_LEN1(7),
245         0,
246 };
247
248 const u32 init_reg[] = {
249         DSI_INT_ENABLE,
250         DSI_INT_STATUS,
251         DSI_INT_MASK,
252         DSI_INIT_SEQ_DATA_0,
253         DSI_INIT_SEQ_DATA_1,
254         DSI_INIT_SEQ_DATA_2,
255         DSI_INIT_SEQ_DATA_3,
256         DSI_INIT_SEQ_DATA_4,
257         DSI_INIT_SEQ_DATA_5,
258         DSI_INIT_SEQ_DATA_6,
259         DSI_INIT_SEQ_DATA_7,
260         DSI_DCS_CMDS,
261         DSI_PKT_SEQ_0_LO,
262         DSI_PKT_SEQ_1_LO,
263         DSI_PKT_SEQ_2_LO,
264         DSI_PKT_SEQ_3_LO,
265         DSI_PKT_SEQ_4_LO,
266         DSI_PKT_SEQ_5_LO,
267         DSI_PKT_SEQ_0_HI,
268         DSI_PKT_SEQ_1_HI,
269         DSI_PKT_SEQ_2_HI,
270         DSI_PKT_SEQ_3_HI,
271         DSI_PKT_SEQ_4_HI,
272         DSI_PKT_SEQ_5_HI,
273         DSI_CONTROL,
274         DSI_HOST_DSI_CONTROL,
275         DSI_PAD_CONTROL,
276         DSI_PAD_CONTROL_CD,
277         DSI_SOL_DELAY,
278         DSI_MAX_THRESHOLD,
279         DSI_TRIGGER,
280         DSI_TX_CRC,
281         DSI_INIT_SEQ_CONTROL,
282         DSI_PKT_LEN_0_1,
283         DSI_PKT_LEN_2_3,
284         DSI_PKT_LEN_4_5,
285         DSI_PKT_LEN_6_7,
286 };
287
288 inline unsigned long tegra_dsi_readl(struct tegra_dc_dsi_data *dsi, u32 reg)
289 {
290         return readl(dsi->base + reg * 4);
291 }
292 EXPORT_SYMBOL(tegra_dsi_readl);
293
294 inline void tegra_dsi_writel(struct tegra_dc_dsi_data *dsi, u32 val, u32 reg)
295 {
296         writel(val, dsi->base + reg * 4);
297 }
298 EXPORT_SYMBOL(tegra_dsi_writel);
299
300 static int tegra_dsi_syncpt(struct tegra_dc_dsi_data *dsi)
301 {
302         u32 val;
303         int ret;
304
305         ret = 0;
306
307         dsi->syncpt_val = nvhost_syncpt_read(
308                         &nvhost_get_host(dsi->dc->ndev)->syncpt,
309                         dsi->syncpt_id);
310
311         val = DSI_INCR_SYNCPT_COND(OP_DONE) |
312                 DSI_INCR_SYNCPT_INDX(dsi->syncpt_id);
313         tegra_dsi_writel(dsi, val, DSI_INCR_SYNCPT);
314
315         /* TODO: Use interrupt rather than polling */
316         ret = nvhost_syncpt_wait(&nvhost_get_host(dsi->dc->ndev)->syncpt,
317                 dsi->syncpt_id, dsi->syncpt_val + 1);
318         if (ret < 0) {
319                 dev_err(&dsi->dc->ndev->dev, "DSI sync point failure\n");
320                 goto fail;
321         }
322
323         (dsi->syncpt_val)++;
324         return 0;
325 fail:
326         return ret;
327 }
328
329 static u32 tegra_dsi_get_hs_clk_rate(struct tegra_dc_dsi_data *dsi)
330 {
331         u32 dsi_clock_rate_khz;
332
333         switch (dsi->info.video_burst_mode) {
334         case TEGRA_DSI_VIDEO_BURST_MODE_LOW_SPEED:
335         case TEGRA_DSI_VIDEO_BURST_MODE_MEDIUM_SPEED:
336         case TEGRA_DSI_VIDEO_BURST_MODE_FAST_SPEED:
337         case TEGRA_DSI_VIDEO_BURST_MODE_FASTEST_SPEED:
338                 /* Calculate DSI HS clock rate for DSI burst mode */
339                 dsi_clock_rate_khz = dsi->default_pixel_clk_khz *
340                                                         dsi->shift_clk_div;
341                 break;
342         case TEGRA_DSI_VIDEO_NONE_BURST_MODE:
343         case TEGRA_DSI_VIDEO_NONE_BURST_MODE_WITH_SYNC_END:
344         case TEGRA_DSI_VIDEO_BURST_MODE_LOWEST_SPEED:
345         default:
346                 /* Clock rate is default DSI clock rate for non-burst mode */
347                 dsi_clock_rate_khz = dsi->default_hs_clk_khz;
348                 break;
349         }
350
351         return dsi_clock_rate_khz;
352 }
353
354 static u32 tegra_dsi_get_lp_clk_rate(struct tegra_dc_dsi_data *dsi, u8 lp_op)
355 {
356         u32 dsi_clock_rate_khz;
357
358         if (dsi->info.enable_hs_clock_on_lp_cmd_mode)
359                 if (dsi->info.hs_clk_in_lp_cmd_mode_freq_khz)
360                         dsi_clock_rate_khz =
361                                 dsi->info.hs_clk_in_lp_cmd_mode_freq_khz;
362                 else
363                         dsi_clock_rate_khz = tegra_dsi_get_hs_clk_rate(dsi);
364         else
365                 if (lp_op == DSI_LP_OP_READ)
366                         dsi_clock_rate_khz =
367                                 dsi->info.lp_read_cmd_mode_freq_khz;
368                 else
369                         dsi_clock_rate_khz =
370                                 dsi->info.lp_cmd_mode_freq_khz;
371
372         return dsi_clock_rate_khz;
373 }
374
375 static u32 tegra_dsi_get_shift_clk_div(struct tegra_dc_dsi_data *dsi)
376 {
377         u32 shift_clk_div;
378         u32 max_shift_clk_div;
379         u32 burst_width;
380         u32 burst_width_max;
381
382         /* Get the real value of default shift_clk_div. default_shift_clk_div
383          * holds the real value of shift_clk_div.
384          */
385         shift_clk_div = dsi->default_shift_clk_div;
386
387         /* Calculate shift_clk_div which can matche the video_burst_mode. */
388         if (dsi->info.video_burst_mode >=
389                         TEGRA_DSI_VIDEO_BURST_MODE_LOWEST_SPEED) {
390                 /* The max_shift_clk_div is multiplied by 10 to save the
391                  * fraction
392                  */
393                 if (dsi->info.max_panel_freq_khz >= dsi->default_hs_clk_khz)
394                         max_shift_clk_div = dsi->info.max_panel_freq_khz
395                                 * shift_clk_div * 10 / dsi->default_hs_clk_khz;
396                 else
397                         max_shift_clk_div = shift_clk_div * 10;
398
399                 burst_width = dsi->info.video_burst_mode
400                                 - TEGRA_DSI_VIDEO_BURST_MODE_LOWEST_SPEED;
401                 burst_width_max = TEGRA_DSI_VIDEO_BURST_MODE_FASTEST_SPEED
402                                 - TEGRA_DSI_VIDEO_BURST_MODE_LOWEST_SPEED;
403
404                 shift_clk_div = (max_shift_clk_div - shift_clk_div * 10) *
405                         burst_width / (burst_width_max * 10) + shift_clk_div;
406         }
407
408         return shift_clk_div;
409 }
410
411 static void tegra_dsi_init_sw(struct tegra_dc *dc,
412                         struct tegra_dc_dsi_data *dsi)
413 {
414         u32 h_width_pixels;
415         u32 v_width_lines;
416         u32 pixel_clk_hz;
417         u32 byte_clk_hz;
418         u32 plld_clk_mhz;
419
420         switch (dsi->info.pixel_format) {
421         case TEGRA_DSI_PIXEL_FORMAT_16BIT_P:
422                 /* 2 bytes per pixel */
423                 dsi->pixel_scaler_mul = 2;
424                 dsi->pixel_scaler_div = 1;
425                 break;
426         case TEGRA_DSI_PIXEL_FORMAT_18BIT_P:
427                 /* 2.25 bytes per pixel */
428                 dsi->pixel_scaler_mul = 9;
429                 dsi->pixel_scaler_div = 4;
430                 break;
431         case TEGRA_DSI_PIXEL_FORMAT_18BIT_NP:
432         case TEGRA_DSI_PIXEL_FORMAT_24BIT_P:
433                 /* 3 bytes per pixel */
434                 dsi->pixel_scaler_mul = 3;
435                 dsi->pixel_scaler_div = 1;
436                 break;
437         default:
438                 break;
439         }
440
441         dsi->controller_index = dc->ndev->id;
442         dsi->ulpm = false;
443         dsi->enabled = false;
444         dsi->clk_ref = false;
445
446         dsi->dsi_control_val =
447                         DSI_CONTROL_VIRTUAL_CHANNEL(dsi->info.virtual_channel) |
448                         DSI_CONTROL_NUM_DATA_LANES(dsi->info.n_data_lanes - 1) |
449                         DSI_CONTROL_VID_SOURCE(dsi->controller_index) |
450                         DSI_CONTROL_DATA_FORMAT(dsi->info.pixel_format);
451
452         /* Below we are going to calculate dsi and dc clock rate.
453          * Calcuate the horizontal and vertical width.
454          */
455         h_width_pixels = dc->mode.h_back_porch + dc->mode.h_front_porch +
456                         dc->mode.h_sync_width + dc->mode.h_active;
457         v_width_lines = dc->mode.v_back_porch + dc->mode.v_front_porch +
458                         dc->mode.v_sync_width + dc->mode.v_active;
459
460         /* Calculate minimum required pixel rate. */
461         pixel_clk_hz = h_width_pixels * v_width_lines * dsi->info.refresh_rate;
462
463         /* Calculate minimum byte rate on DSI interface. */
464         byte_clk_hz = (pixel_clk_hz * dsi->pixel_scaler_mul) /
465                         (dsi->pixel_scaler_div * dsi->info.n_data_lanes);
466
467         /* Round up to multiple of mega hz. */
468         plld_clk_mhz = DIV_ROUND_UP((byte_clk_hz * NUMOF_BIT_PER_BYTE),
469                                                                 1000000);
470
471         /* Calculate default real shift_clk_div. */
472         dsi->default_shift_clk_div = (NUMOF_BIT_PER_BYTE / 2) *
473                 dsi->pixel_scaler_mul / (dsi->pixel_scaler_div *
474                 dsi->info.n_data_lanes);
475         /* Calculate default DSI hs clock. DSI interface is double data rate.
476          * Data is transferred on both rising and falling edge of clk, div by 2
477          * to get the actual clock rate.
478          */
479         dsi->default_hs_clk_khz = plld_clk_mhz * 1000 / 2;
480         dsi->default_pixel_clk_khz = plld_clk_mhz * 1000 / 2
481                                                 / dsi->default_shift_clk_div;
482
483         /* Get the actual shift_clk_div and clock rates. */
484         dsi->shift_clk_div = tegra_dsi_get_shift_clk_div(dsi);
485         dsi->target_lp_clk_khz =
486                         tegra_dsi_get_lp_clk_rate(dsi, DSI_LP_OP_WRITE);
487         dsi->target_hs_clk_khz = tegra_dsi_get_hs_clk_rate(dsi);
488
489         dev_info(&dc->ndev->dev, "DSI: HS clock rate is %d\n",
490                                                         dsi->target_hs_clk_khz);
491
492         dsi->controller_index = dc->ndev->id;
493
494 #if DSI_USE_SYNC_POINTS
495         dsi->syncpt_id = NVSYNCPT_DSI;
496 #endif
497
498         /*
499          * Force video clock to be continuous mode if
500          * enable_hs_clock_on_lp_cmd_mode is set
501          */
502         if (dsi->info.enable_hs_clock_on_lp_cmd_mode) {
503                 if (dsi->info.video_clock_mode !=
504                                         TEGRA_DSI_VIDEO_CLOCK_CONTINUOUS)
505                         dev_warn(&dc->ndev->dev,
506                                 "Force clock continuous mode\n");
507
508                 dsi->info.video_clock_mode = TEGRA_DSI_VIDEO_CLOCK_CONTINUOUS;
509         }
510
511 }
512
513 #define SELECT_T_PHY(platform_t_phy_ns, default_phy, clk_ns, hw_inc) ( \
514 (platform_t_phy_ns) ? ( \
515 ((DSI_CONVERT_T_PHY_NS_TO_T_PHY(platform_t_phy_ns, clk_ns, hw_inc)) < 0 ? 0 : \
516 (DSI_CONVERT_T_PHY_NS_TO_T_PHY(platform_t_phy_ns, clk_ns, hw_inc)))) : \
517 ((default_phy) < 0 ? 0 : (default_phy)))
518
519 static void tegra_dsi_get_clk_phy_timing(struct tegra_dc_dsi_data *dsi,
520                 struct dsi_phy_timing_inclk *phy_timing_clk, u32 clk_ns)
521 {
522         phy_timing_clk->t_tlpx = SELECT_T_PHY(
523                 dsi->info.phy_timing.t_tlpx_ns,
524                 T_TLPX_DEFAULT(clk_ns), clk_ns, T_TLPX_HW_INC);
525
526         phy_timing_clk->t_clktrail = SELECT_T_PHY(
527                 dsi->info.phy_timing.t_clktrail_ns,
528                 T_CLKTRAIL_DEFAULT(clk_ns), clk_ns, T_CLKTRAIL_HW_INC);
529
530         phy_timing_clk->t_clkpost = SELECT_T_PHY(
531                 dsi->info.phy_timing.t_clkpost_ns,
532                 T_CLKPOST_DEFAULT(clk_ns), clk_ns, T_CLKPOST_HW_INC);
533
534         phy_timing_clk->t_clkzero = SELECT_T_PHY(
535                 dsi->info.phy_timing.t_clkzero_ns,
536                 T_CLKZERO_DEFAULT(clk_ns), clk_ns, T_CLKZERO_HW_INC);
537
538         phy_timing_clk->t_clkprepare = SELECT_T_PHY(
539                 dsi->info.phy_timing.t_clkprepare_ns,
540                 T_CLKPREPARE_DEFAULT(clk_ns), clk_ns, T_CLKPREPARE_HW_INC);
541
542         phy_timing_clk->t_clkpre = SELECT_T_PHY(
543                 dsi->info.phy_timing.t_clkpre_ns,
544                 T_CLKPRE_DEFAULT, clk_ns, T_CLKPRE_HW_INC);
545 }
546
547 static void tegra_dsi_get_hs_phy_timing(struct tegra_dc_dsi_data *dsi,
548                 struct dsi_phy_timing_inclk *phy_timing_clk, u32 clk_ns)
549 {
550         phy_timing_clk->t_tlpx = SELECT_T_PHY(
551                 dsi->info.phy_timing.t_tlpx_ns,
552                 T_TLPX_DEFAULT(clk_ns), clk_ns, T_TLPX_HW_INC);
553
554         phy_timing_clk->t_hsdexit = SELECT_T_PHY(
555                 dsi->info.phy_timing.t_hsdexit_ns,
556                 T_HSEXIT_DEFAULT(clk_ns), clk_ns, T_HSEXIT_HW_INC);
557
558         phy_timing_clk->t_hstrail = SELECT_T_PHY(
559                 dsi->info.phy_timing.t_hstrail_ns,
560                 T_HSTRAIL_DEFAULT(clk_ns), clk_ns, T_HSTRAIL_HW_INC);
561
562         phy_timing_clk->t_datzero = SELECT_T_PHY(
563                 dsi->info.phy_timing.t_datzero_ns,
564                 T_DATZERO_DEFAULT(clk_ns), clk_ns, T_DATZERO_HW_INC);
565
566         phy_timing_clk->t_hsprepare = SELECT_T_PHY(
567                 dsi->info.phy_timing.t_hsprepare_ns,
568                 T_HSPREPARE_DEFAULT(clk_ns), clk_ns, T_HSPREPARE_HW_INC);
569 }
570
571 static void tegra_dsi_get_escape_phy_timing(struct tegra_dc_dsi_data *dsi,
572                 struct dsi_phy_timing_inclk *phy_timing_clk, u32 clk_ns)
573 {
574         phy_timing_clk->t_tlpx = SELECT_T_PHY(
575                 dsi->info.phy_timing.t_tlpx_ns,
576                 T_TLPX_DEFAULT(clk_ns), clk_ns, T_TLPX_HW_INC);
577 }
578
579 static void tegra_dsi_get_bta_phy_timing(struct tegra_dc_dsi_data *dsi,
580                 struct dsi_phy_timing_inclk *phy_timing_clk, u32 clk_ns)
581 {
582         phy_timing_clk->t_tlpx = SELECT_T_PHY(
583                 dsi->info.phy_timing.t_tlpx_ns,
584                 T_TLPX_DEFAULT(clk_ns), clk_ns, T_TLPX_HW_INC);
585
586         phy_timing_clk->t_taget = SELECT_T_PHY(
587                 dsi->info.phy_timing.t_taget_ns,
588                 T_TAGET_DEFAULT(clk_ns), clk_ns, T_TAGET_HW_INC);
589
590         phy_timing_clk->t_tasure = SELECT_T_PHY(
591                 dsi->info.phy_timing.t_tasure_ns,
592                 T_TASURE_DEFAULT(clk_ns), clk_ns, T_TASURE_HW_INC);
593
594         phy_timing_clk->t_tago = SELECT_T_PHY(
595                 dsi->info.phy_timing.t_tago_ns,
596                 T_TAGO_DEFAULT(clk_ns), clk_ns, T_TAGO_HW_INC);
597 }
598
599 static void tegra_dsi_get_ulps_phy_timing(struct tegra_dc_dsi_data *dsi,
600                 struct dsi_phy_timing_inclk *phy_timing_clk, u32 clk_ns)
601 {
602         phy_timing_clk->t_tlpx = SELECT_T_PHY(
603                 dsi->info.phy_timing.t_tlpx_ns,
604                 T_TLPX_DEFAULT(clk_ns), clk_ns, T_TLPX_HW_INC);
605
606         phy_timing_clk->t_wakeup = SELECT_T_PHY(
607                 dsi->info.phy_timing.t_wakeup_ns,
608                 T_WAKEUP_DEFAULT, clk_ns, T_WAKEUP_HW_INC);
609 }
610
611 #undef SELECT_T_PHY
612
613 static void tegra_dsi_get_phy_timing(struct tegra_dc_dsi_data *dsi,
614                                 struct dsi_phy_timing_inclk *phy_timing_clk,
615                                 u32 clk_ns, u8 lphs)
616 {
617         if (lphs == DSI_LPHS_IN_HS_MODE) {
618                 tegra_dsi_get_clk_phy_timing(dsi, phy_timing_clk, clk_ns);
619                 tegra_dsi_get_hs_phy_timing(dsi, phy_timing_clk, clk_ns);
620         } else {
621                 /* default is LP mode */
622                 tegra_dsi_get_escape_phy_timing(dsi, phy_timing_clk, clk_ns);
623                 tegra_dsi_get_bta_phy_timing(dsi, phy_timing_clk, clk_ns);
624                 tegra_dsi_get_ulps_phy_timing(dsi, phy_timing_clk, clk_ns);
625                 if (dsi->info.enable_hs_clock_on_lp_cmd_mode)
626                         tegra_dsi_get_clk_phy_timing
627                                 (dsi, phy_timing_clk, clk_ns);
628         }
629 }
630
631 static int tegra_dsi_mipi_phy_timing_range(struct tegra_dc_dsi_data *dsi,
632                                 struct dsi_phy_timing_inclk *phy_timing,
633                                 u32 clk_ns, u8 lphs)
634 {
635 #define CHECK_RANGE(val, min, max) ( \
636                 ((min) == NOT_DEFINED ? 0 : (val) < (min)) || \
637                 ((max) == NOT_DEFINED ? 0 : (val) > (max)) ? -EINVAL : 0)
638
639         int err = 0;
640
641         err = CHECK_RANGE(
642         DSI_CONVERT_T_PHY_TO_T_PHY_NS(
643                         phy_timing->t_tlpx, clk_ns, T_TLPX_HW_INC),
644                         MIPI_T_TLPX_NS_MIN, MIPI_T_TLPX_NS_MAX);
645         if (err < 0) {
646                 dev_warn(&dsi->dc->ndev->dev,
647                         "dsi: Tlpx mipi range violated\n");
648                 goto fail;
649         }
650
651         if (lphs == DSI_LPHS_IN_HS_MODE) {
652                 err = CHECK_RANGE(
653                 DSI_CONVERT_T_PHY_TO_T_PHY_NS(
654                         phy_timing->t_hsdexit, clk_ns, T_HSEXIT_HW_INC),
655                         MIPI_T_HSEXIT_NS_MIN, MIPI_T_HSEXIT_NS_MAX);
656                 if (err < 0) {
657                         dev_warn(&dsi->dc->ndev->dev,
658                                 "dsi: HsExit mipi range violated\n");
659                         goto fail;
660                 }
661
662                 err = CHECK_RANGE(
663                 DSI_CONVERT_T_PHY_TO_T_PHY_NS(
664                         phy_timing->t_hstrail, clk_ns, T_HSTRAIL_HW_INC),
665                         MIPI_T_HSTRAIL_NS_MIN(clk_ns), MIPI_T_HSTRAIL_NS_MAX);
666                 if (err < 0) {
667                         dev_warn(&dsi->dc->ndev->dev,
668                                 "dsi: HsTrail mipi range violated\n");
669                         goto fail;
670                 }
671
672                 err = CHECK_RANGE(
673                 DSI_CONVERT_T_PHY_TO_T_PHY_NS(
674                         phy_timing->t_datzero, clk_ns, T_DATZERO_HW_INC),
675                         MIPI_T_HSZERO_NS_MIN, MIPI_T_HSZERO_NS_MAX);
676                 if (err < 0) {
677                         dev_warn(&dsi->dc->ndev->dev,
678                                 "dsi: HsZero mipi range violated\n");
679                         goto fail;
680                 }
681
682                 err = CHECK_RANGE(
683                 DSI_CONVERT_T_PHY_TO_T_PHY_NS(
684                         phy_timing->t_hsprepare, clk_ns, T_HSPREPARE_HW_INC),
685                         MIPI_T_HSPREPARE_NS_MIN(clk_ns),
686                         MIPI_T_HSPREPARE_NS_MAX(clk_ns));
687                 if (err < 0) {
688                         dev_warn(&dsi->dc->ndev->dev,
689                                 "dsi: HsPrepare mipi range violated\n");
690                         goto fail;
691                 }
692
693                 err = CHECK_RANGE(
694                 DSI_CONVERT_T_PHY_TO_T_PHY_NS(
695                 phy_timing->t_hsprepare, clk_ns, T_HSPREPARE_HW_INC) +
696                 DSI_CONVERT_T_PHY_TO_T_PHY_NS(
697                         phy_timing->t_datzero, clk_ns, T_DATZERO_HW_INC),
698                         MIPI_T_HSPREPARE_ADD_HSZERO_NS_MIN(clk_ns),
699                         MIPI_T_HSPREPARE_ADD_HSZERO_NS_MAX);
700                 if (err < 0) {
701                         dev_warn(&dsi->dc->ndev->dev,
702                         "dsi: HsPrepare + HsZero mipi range violated\n");
703                         goto fail;
704                 }
705         } else {
706                 /* default is LP mode */
707                 err = CHECK_RANGE(
708                 DSI_CONVERT_T_PHY_TO_T_PHY_NS(
709                         phy_timing->t_wakeup, clk_ns, T_WAKEUP_HW_INC),
710                         MIPI_T_WAKEUP_NS_MIN, MIPI_T_WAKEUP_NS_MAX);
711                 if (err < 0) {
712                         dev_warn(&dsi->dc->ndev->dev,
713                                 "dsi: WakeUp mipi range violated\n");
714                         goto fail;
715                 }
716
717                 err = CHECK_RANGE(
718                 DSI_CONVERT_T_PHY_TO_T_PHY_NS(
719                         phy_timing->t_tasure, clk_ns, T_TASURE_HW_INC),
720                         MIPI_T_TASURE_NS_MIN(DSI_CONVERT_T_PHY_TO_T_PHY_NS(
721                         phy_timing->t_tlpx, clk_ns, T_TLPX_HW_INC)),
722                         MIPI_T_TASURE_NS_MAX(DSI_CONVERT_T_PHY_TO_T_PHY_NS(
723                         phy_timing->t_tlpx, clk_ns, T_TLPX_HW_INC)));
724                 if (err < 0) {
725                         dev_warn(&dsi->dc->ndev->dev,
726                                 "dsi: TaSure mipi range violated\n");
727                         goto fail;
728                 }
729         }
730
731         if (lphs == DSI_LPHS_IN_HS_MODE ||
732                 dsi->info.enable_hs_clock_on_lp_cmd_mode) {
733                 err = CHECK_RANGE(
734                 DSI_CONVERT_T_PHY_TO_T_PHY_NS(
735                         phy_timing->t_clktrail, clk_ns, T_CLKTRAIL_HW_INC),
736                         MIPI_T_CLKTRAIL_NS_MIN, MIPI_T_CLKTRAIL_NS_MAX);
737                 if (err < 0) {
738                         dev_warn(&dsi->dc->ndev->dev,
739                                 "dsi: ClkTrail mipi range violated\n");
740                         goto fail;
741                 }
742
743                 err = CHECK_RANGE(
744                 DSI_CONVERT_T_PHY_TO_T_PHY_NS(
745                         phy_timing->t_clkpost, clk_ns, T_CLKPOST_HW_INC),
746                         MIPI_T_CLKPOST_NS_MIN(clk_ns), MIPI_T_CLKPOST_NS_MAX);
747                 if (err < 0) {
748                         dev_warn(&dsi->dc->ndev->dev,
749                                 "dsi: ClkPost mipi range violated\n");
750                         goto fail;
751                 }
752
753                 err = CHECK_RANGE(
754                 DSI_CONVERT_T_PHY_TO_T_PHY_NS(
755                         phy_timing->t_clkzero, clk_ns, T_CLKZERO_HW_INC),
756                         MIPI_T_CLKZERO_NS_MIN, MIPI_T_CLKZERO_NS_MAX);
757                 if (err < 0) {
758                         dev_warn(&dsi->dc->ndev->dev,
759                                 "dsi: ClkZero mipi range violated\n");
760                         goto fail;
761                 }
762
763                 err = CHECK_RANGE(
764                 DSI_CONVERT_T_PHY_TO_T_PHY_NS(
765                         phy_timing->t_clkprepare, clk_ns, T_CLKPREPARE_HW_INC),
766                         MIPI_T_CLKPREPARE_NS_MIN, MIPI_T_CLKPREPARE_NS_MAX);
767                 if (err < 0) {
768                         dev_warn(&dsi->dc->ndev->dev,
769                                 "dsi: ClkPrepare mipi range violated\n");
770                         goto fail;
771                 }
772
773                 err = CHECK_RANGE(
774                 DSI_CONVERT_T_PHY_TO_T_PHY_NS(
775                         phy_timing->t_clkpre, clk_ns, T_CLKPRE_HW_INC),
776                         MIPI_T_CLKPRE_NS_MIN, MIPI_T_CLKPRE_NS_MAX);
777                 if (err < 0) {
778                         dev_warn(&dsi->dc->ndev->dev,
779                                 "dsi: ClkPre mipi range violated\n");
780                         goto fail;
781                 }
782
783                 err = CHECK_RANGE(
784                 DSI_CONVERT_T_PHY_TO_T_PHY_NS(
785                 phy_timing->t_clkprepare, clk_ns, T_CLKPREPARE_HW_INC) +
786                 DSI_CONVERT_T_PHY_TO_T_PHY_NS(
787                         phy_timing->t_clkzero, clk_ns, T_CLKZERO_HW_INC),
788                         MIPI_T_CLKPREPARE_ADD_CLKZERO_NS_MIN,
789                         MIPI_T_CLKPREPARE_ADD_CLKZERO_NS_MAX);
790                 if (err < 0) {
791                         dev_warn(&dsi->dc->ndev->dev,
792                         "dsi: ClkPrepare + ClkZero mipi range violated\n");
793                         goto fail;
794                 }
795         }
796 fail:
797 #undef CHECK_RANGE
798         return err;
799 }
800
801 static int tegra_dsi_hs_phy_len(struct tegra_dc_dsi_data *dsi,
802                                 struct dsi_phy_timing_inclk *phy_timing,
803                                 u32 clk_ns, u8 lphs)
804 {
805         u32 hs_t_phy_ns;
806         u32 clk_t_phy_ns;
807         u32 t_phy_ns;
808         u32 h_blank_ns;
809         struct tegra_dc_mode *modes;
810         u32 t_pix_ns;
811         int err = 0;
812
813         if (!(lphs == DSI_LPHS_IN_HS_MODE))
814                 goto fail;
815
816         modes = dsi->dc->out->modes;
817         t_pix_ns = clk_ns * BITS_PER_BYTE *
818                 dsi->pixel_scaler_mul / dsi->pixel_scaler_div;
819
820         hs_t_phy_ns =
821                 DSI_CONVERT_T_PHY_TO_T_PHY_NS(
822                 phy_timing->t_tlpx, clk_ns, T_TLPX_HW_INC) +
823                 DSI_CONVERT_T_PHY_TO_T_PHY_NS(
824                 phy_timing->t_hsprepare, clk_ns, T_HSPREPARE_HW_INC) +
825                 DSI_CONVERT_T_PHY_TO_T_PHY_NS(
826                 phy_timing->t_datzero, clk_ns, T_DATZERO_HW_INC) +
827                 DSI_CONVERT_T_PHY_TO_T_PHY_NS(
828                 phy_timing->t_hstrail, clk_ns, T_HSTRAIL_HW_INC) +
829                 DSI_CONVERT_T_PHY_TO_T_PHY_NS(
830                 phy_timing->t_hsdexit, clk_ns, T_HSEXIT_HW_INC);
831
832         clk_t_phy_ns =
833                 DSI_CONVERT_T_PHY_TO_T_PHY_NS(
834                 phy_timing->t_clkpost, clk_ns, T_CLKPOST_HW_INC) +
835                 DSI_CONVERT_T_PHY_TO_T_PHY_NS(
836                 phy_timing->t_clktrail, clk_ns, T_CLKTRAIL_HW_INC) +
837                 DSI_CONVERT_T_PHY_TO_T_PHY_NS(
838                 phy_timing->t_hsdexit, clk_ns, T_HSEXIT_HW_INC) +
839                 DSI_CONVERT_T_PHY_TO_T_PHY_NS(
840                 phy_timing->t_tlpx, clk_ns, T_TLPX_HW_INC) +
841                 DSI_CONVERT_T_PHY_TO_T_PHY_NS(
842                 phy_timing->t_clkprepare, clk_ns, T_CLKPREPARE_HW_INC) +
843                 DSI_CONVERT_T_PHY_TO_T_PHY_NS(
844                 phy_timing->t_clkzero, clk_ns, T_CLKZERO_HW_INC) +
845                 DSI_CONVERT_T_PHY_TO_T_PHY_NS(
846                 phy_timing->t_clkpre, clk_ns, T_CLKPRE_HW_INC);
847
848         h_blank_ns = t_pix_ns * (modes->h_sync_width + modes->h_back_porch +
849                                                 modes->h_front_porch);
850
851         /* Extra tlpx and byte cycle required by dsi HW */
852         t_phy_ns = dsi->info.n_data_lanes * (hs_t_phy_ns + clk_t_phy_ns +
853                 DSI_CONVERT_T_PHY_TO_T_PHY_NS(
854                 phy_timing->t_tlpx, clk_ns, T_TLPX_HW_INC) +
855                 clk_ns * BITS_PER_BYTE);
856
857         if (h_blank_ns < t_phy_ns) {
858                 err = -EINVAL;
859                 dev_err(&dsi->dc->ndev->dev,
860                         "dsi: Hblank is smaller than HS trans phy timing\n");
861                 goto fail;
862         }
863
864         return 0;
865 fail:
866         return err;
867 }
868
869 static int tegra_dsi_constraint_phy_timing(struct tegra_dc_dsi_data *dsi,
870                                 struct dsi_phy_timing_inclk *phy_timing,
871                                 u32 clk_ns, u8 lphs)
872 {
873         int err = 0;
874
875         err = tegra_dsi_mipi_phy_timing_range(dsi, phy_timing, clk_ns, lphs);
876         if (err < 0) {
877                 dev_warn(&dsi->dc->ndev->dev, "dsi: mipi range violated\n");
878                 goto fail;
879         }
880
881         err = tegra_dsi_hs_phy_len(dsi, phy_timing, clk_ns, lphs);
882         if (err < 0) {
883                 dev_err(&dsi->dc->ndev->dev, "dsi: Hblank too short\n");
884                 goto fail;
885         }
886
887         /* TODO: add more contraints */
888 fail:
889         return err;
890 }
891
892 static void tegra_dsi_set_phy_timing(struct tegra_dc_dsi_data *dsi, u8 lphs)
893 {
894         u32 val;
895         struct dsi_phy_timing_inclk phy_timing = dsi->phy_timing;
896
897         tegra_dsi_get_phy_timing
898                 (dsi, &phy_timing, dsi->current_bit_clk_ns, lphs);
899
900         tegra_dsi_constraint_phy_timing(dsi, &phy_timing,
901                                         dsi->current_bit_clk_ns, lphs);
902
903         val = DSI_PHY_TIMING_0_THSDEXIT(phy_timing.t_hsdexit) |
904                         DSI_PHY_TIMING_0_THSTRAIL(phy_timing.t_hstrail) |
905                         DSI_PHY_TIMING_0_TDATZERO(phy_timing.t_datzero) |
906                         DSI_PHY_TIMING_0_THSPREPR(phy_timing.t_hsprepare);
907         tegra_dsi_writel(dsi, val, DSI_PHY_TIMING_0);
908
909         val = DSI_PHY_TIMING_1_TCLKTRAIL(phy_timing.t_clktrail) |
910                         DSI_PHY_TIMING_1_TCLKPOST(phy_timing.t_clkpost) |
911                         DSI_PHY_TIMING_1_TCLKZERO(phy_timing.t_clkzero) |
912                         DSI_PHY_TIMING_1_TTLPX(phy_timing.t_tlpx);
913         tegra_dsi_writel(dsi, val, DSI_PHY_TIMING_1);
914
915         val = DSI_PHY_TIMING_2_TCLKPREPARE(phy_timing.t_clkprepare) |
916                 DSI_PHY_TIMING_2_TCLKPRE(phy_timing.t_clkpre) |
917                         DSI_PHY_TIMING_2_TWAKEUP(phy_timing.t_wakeup);
918         tegra_dsi_writel(dsi, val, DSI_PHY_TIMING_2);
919
920         val = DSI_BTA_TIMING_TTAGET(phy_timing.t_taget) |
921                         DSI_BTA_TIMING_TTASURE(phy_timing.t_tasure) |
922                         DSI_BTA_TIMING_TTAGO(phy_timing.t_tago);
923         tegra_dsi_writel(dsi, val, DSI_BTA_TIMING);
924
925         dsi->phy_timing = phy_timing;
926 }
927
928 static u32 tegra_dsi_sol_delay_burst(struct tegra_dc *dc,
929                                 struct tegra_dc_dsi_data *dsi)
930 {
931         u32 dsi_to_pixel_clk_ratio;
932         u32 temp;
933         u32 temp1;
934         u32 mipi_clk_adj_kHz;
935         u32 sol_delay;
936         struct tegra_dc_mode *dc_modes = &dc->mode;
937
938         /* Get Fdsi/Fpixel ration (note: Fdsi is in bit format) */
939         dsi_to_pixel_clk_ratio = (dsi->current_dsi_clk_khz * 2 +
940                 dsi->default_pixel_clk_khz - 1) / dsi->default_pixel_clk_khz;
941
942         /* Convert Fdsi to byte format */
943         dsi_to_pixel_clk_ratio *= 1000/8;
944
945         /* Multiplying by 1000 so that we don't loose the fraction part */
946         temp = dc_modes->h_active * 1000;
947         temp1 = dc_modes->h_active + dc_modes->h_back_porch +
948                         dc_modes->h_sync_width;
949
950         sol_delay = temp1 * dsi_to_pixel_clk_ratio -
951                         temp * dsi->pixel_scaler_mul /
952                         (dsi->pixel_scaler_div * dsi->info.n_data_lanes);
953
954         /* Do rounding on sol delay */
955         sol_delay = (sol_delay + 1000 - 1)/1000;
956
957         /* TODO:
958          * 1. find out the correct sol fifo depth to use
959          * 2. verify with hw about the clamping function
960          */
961         if (sol_delay > (480 * 4)) {
962                 sol_delay = (480 * 4);
963                 mipi_clk_adj_kHz = sol_delay +
964                         (dc_modes->h_active * dsi->pixel_scaler_mul) /
965                         (dsi->info.n_data_lanes * dsi->pixel_scaler_div);
966
967                 mipi_clk_adj_kHz *= (dsi->default_pixel_clk_khz / temp1);
968
969                 mipi_clk_adj_kHz *= 4;
970         }
971
972         dsi->target_hs_clk_khz = mipi_clk_adj_kHz;
973
974         return sol_delay;
975 }
976
977 static void tegra_dsi_set_sol_delay(struct tegra_dc *dc,
978                                 struct tegra_dc_dsi_data *dsi)
979 {
980         u32 sol_delay;
981
982         if (dsi->info.video_burst_mode == TEGRA_DSI_VIDEO_NONE_BURST_MODE ||
983                 dsi->info.video_burst_mode ==
984                                 TEGRA_DSI_VIDEO_NONE_BURST_MODE_WITH_SYNC_END) {
985 #define VIDEO_FIFO_LATENCY_PIXEL_CLK 8
986                 sol_delay = VIDEO_FIFO_LATENCY_PIXEL_CLK *
987                         dsi->pixel_scaler_mul / dsi->pixel_scaler_div;
988 #undef VIDEO_FIFO_LATENCY_PIXEL_CLK
989                 dsi->status.clk_burst = DSI_CLK_BURST_NONE_BURST;
990         } else {
991                 sol_delay = tegra_dsi_sol_delay_burst(dc, dsi);
992                 dsi->status.clk_burst = DSI_CLK_BURST_BURST_MODE;
993         }
994
995         tegra_dsi_writel(dsi, DSI_SOL_DELAY_SOL_DELAY(sol_delay),
996                                                                 DSI_SOL_DELAY);
997 }
998
999 static void tegra_dsi_set_timeout(struct tegra_dc_dsi_data *dsi)
1000 {
1001         u32 val;
1002         u32 bytes_per_frame;
1003         u32 timeout = 0;
1004
1005         /* TODO: verify the following equation */
1006         bytes_per_frame = dsi->current_dsi_clk_khz * 1000 * 2 /
1007                                                 (dsi->info.refresh_rate * 8);
1008         timeout = bytes_per_frame / DSI_CYCLE_COUNTER_VALUE;
1009         timeout = (timeout + DSI_HTX_TO_MARGIN) & 0xffff;
1010
1011         val = DSI_TIMEOUT_0_LRXH_TO(DSI_LRXH_TO_VALUE) |
1012                         DSI_TIMEOUT_0_HTX_TO(timeout);
1013         tegra_dsi_writel(dsi, val, DSI_TIMEOUT_0);
1014
1015         if (dsi->info.panel_reset_timeout_msec)
1016                 timeout = (dsi->info.panel_reset_timeout_msec * 1000*1000)
1017                                         / dsi->current_bit_clk_ns;
1018         else
1019                 timeout = DSI_PR_TO_VALUE;
1020
1021         val = DSI_TIMEOUT_1_PR_TO(timeout) |
1022                 DSI_TIMEOUT_1_TA_TO(DSI_TA_TO_VALUE);
1023         tegra_dsi_writel(dsi, val, DSI_TIMEOUT_1);
1024
1025         val = DSI_TO_TALLY_P_RESET_STATUS(IN_RESET) |
1026                 DSI_TO_TALLY_TA_TALLY(DSI_TA_TALLY_VALUE)|
1027                 DSI_TO_TALLY_LRXH_TALLY(DSI_LRXH_TALLY_VALUE)|
1028                 DSI_TO_TALLY_HTX_TALLY(DSI_HTX_TALLY_VALUE);
1029         tegra_dsi_writel(dsi, val, DSI_TO_TALLY);
1030 }
1031
1032 static void tegra_dsi_setup_video_mode_pkt_length(struct tegra_dc *dc,
1033                                                 struct tegra_dc_dsi_data *dsi)
1034 {
1035         u32 val;
1036         u32 hact_pkt_len;
1037         u32 hsa_pkt_len;
1038         u32 hbp_pkt_len;
1039         u32 hfp_pkt_len;
1040
1041         hact_pkt_len = dc->mode.h_active * dsi->pixel_scaler_mul /
1042                                                         dsi->pixel_scaler_div;
1043         hsa_pkt_len = dc->mode.h_sync_width * dsi->pixel_scaler_mul /
1044                                                         dsi->pixel_scaler_div;
1045         hbp_pkt_len = dc->mode.h_back_porch * dsi->pixel_scaler_mul /
1046                                                         dsi->pixel_scaler_div;
1047         hfp_pkt_len = dc->mode.h_front_porch * dsi->pixel_scaler_mul /
1048                                                         dsi->pixel_scaler_div;
1049
1050         if (dsi->info.video_burst_mode !=
1051                                 TEGRA_DSI_VIDEO_NONE_BURST_MODE_WITH_SYNC_END)
1052                 hbp_pkt_len += hsa_pkt_len;
1053
1054         hsa_pkt_len -= DSI_HSYNC_BLNK_PKT_OVERHEAD;
1055         hbp_pkt_len -= DSI_HBACK_PORCH_PKT_OVERHEAD;
1056         hfp_pkt_len -= DSI_HFRONT_PORCH_PKT_OVERHEAD;
1057
1058         val = DSI_PKT_LEN_0_1_LENGTH_0(0) |
1059                         DSI_PKT_LEN_0_1_LENGTH_1(hsa_pkt_len);
1060         tegra_dsi_writel(dsi, val, DSI_PKT_LEN_0_1);
1061
1062         val = DSI_PKT_LEN_2_3_LENGTH_2(hbp_pkt_len) |
1063                         DSI_PKT_LEN_2_3_LENGTH_3(hact_pkt_len);
1064         tegra_dsi_writel(dsi, val, DSI_PKT_LEN_2_3);
1065
1066         val = DSI_PKT_LEN_4_5_LENGTH_4(hfp_pkt_len) |
1067                         DSI_PKT_LEN_4_5_LENGTH_5(0);
1068         tegra_dsi_writel(dsi, val, DSI_PKT_LEN_4_5);
1069
1070         val = DSI_PKT_LEN_6_7_LENGTH_6(0) | DSI_PKT_LEN_6_7_LENGTH_7(0);
1071         tegra_dsi_writel(dsi, val, DSI_PKT_LEN_6_7);
1072 }
1073
1074 static void tegra_dsi_setup_cmd_mode_pkt_length(struct tegra_dc *dc,
1075                                                 struct tegra_dc_dsi_data *dsi)
1076 {
1077         unsigned long   val;
1078         unsigned long   act_bytes;
1079
1080         act_bytes = dc->mode.h_active * dsi->pixel_scaler_mul /
1081                         dsi->pixel_scaler_div + 1;
1082
1083         val = DSI_PKT_LEN_0_1_LENGTH_0(0) | DSI_PKT_LEN_0_1_LENGTH_1(0);
1084         tegra_dsi_writel(dsi, val, DSI_PKT_LEN_0_1);
1085
1086         val = DSI_PKT_LEN_2_3_LENGTH_2(0) | DSI_PKT_LEN_2_3_LENGTH_3(act_bytes);
1087         tegra_dsi_writel(dsi, val, DSI_PKT_LEN_2_3);
1088
1089         val = DSI_PKT_LEN_4_5_LENGTH_4(0) | DSI_PKT_LEN_4_5_LENGTH_5(act_bytes);
1090         tegra_dsi_writel(dsi, val, DSI_PKT_LEN_4_5);
1091
1092         val = DSI_PKT_LEN_6_7_LENGTH_6(0) | DSI_PKT_LEN_6_7_LENGTH_7(0x0f0f);
1093         tegra_dsi_writel(dsi, val, DSI_PKT_LEN_6_7);
1094 }
1095
1096 static void tegra_dsi_set_pkt_length(struct tegra_dc *dc,
1097                                 struct tegra_dc_dsi_data *dsi)
1098 {
1099         if (dsi->driven_mode == TEGRA_DSI_DRIVEN_BY_HOST)
1100                 return;
1101
1102         if (dsi->info.video_data_type == TEGRA_DSI_VIDEO_TYPE_VIDEO_MODE)
1103                 tegra_dsi_setup_video_mode_pkt_length(dc, dsi);
1104         else
1105                 tegra_dsi_setup_cmd_mode_pkt_length(dc, dsi);
1106 }
1107
1108 static void tegra_dsi_set_pkt_seq(struct tegra_dc *dc,
1109                                 struct tegra_dc_dsi_data *dsi)
1110 {
1111         const u32 *pkt_seq;
1112         u32 rgb_info;
1113         u32 pkt_seq_3_5_rgb_lo;
1114         u32 pkt_seq_3_5_rgb_hi;
1115         u32     val;
1116         u32 reg;
1117         u8  i;
1118
1119         if (dsi->driven_mode == TEGRA_DSI_DRIVEN_BY_HOST)
1120                 return;
1121
1122         switch (dsi->info.pixel_format) {
1123         case TEGRA_DSI_PIXEL_FORMAT_16BIT_P:
1124                 rgb_info = CMD_RGB_16BPP;
1125                 break;
1126         case TEGRA_DSI_PIXEL_FORMAT_18BIT_P:
1127                 rgb_info = CMD_RGB_18BPP;
1128                 break;
1129         case TEGRA_DSI_PIXEL_FORMAT_18BIT_NP:
1130                 rgb_info = CMD_RGB_18BPPNP;
1131                 break;
1132         case TEGRA_DSI_PIXEL_FORMAT_24BIT_P:
1133         default:
1134                 rgb_info = CMD_RGB_24BPP;
1135                 break;
1136         }
1137
1138         pkt_seq_3_5_rgb_lo = 0;
1139         pkt_seq_3_5_rgb_hi = 0;
1140         if (dsi->info.video_data_type == TEGRA_DSI_VIDEO_TYPE_COMMAND_MODE)
1141                 pkt_seq = dsi_pkt_seq_cmd_mode;
1142         else {
1143                 switch (dsi->info.video_burst_mode) {
1144                 case TEGRA_DSI_VIDEO_BURST_MODE_LOWEST_SPEED:
1145                 case TEGRA_DSI_VIDEO_BURST_MODE_LOW_SPEED:
1146                 case TEGRA_DSI_VIDEO_BURST_MODE_MEDIUM_SPEED:
1147                 case TEGRA_DSI_VIDEO_BURST_MODE_FAST_SPEED:
1148                 case TEGRA_DSI_VIDEO_BURST_MODE_FASTEST_SPEED:
1149                         pkt_seq_3_5_rgb_lo =
1150                                         DSI_PKT_SEQ_3_LO_PKT_32_ID(rgb_info);
1151                         if (!dsi->info.no_pkt_seq_eot)
1152                                 pkt_seq = dsi_pkt_seq_video_burst;
1153                         else
1154                                 pkt_seq = dsi_pkt_seq_video_burst_no_eot;
1155                         break;
1156                 case TEGRA_DSI_VIDEO_NONE_BURST_MODE_WITH_SYNC_END:
1157                         pkt_seq_3_5_rgb_hi =
1158                                         DSI_PKT_SEQ_3_HI_PKT_34_ID(rgb_info);
1159                         pkt_seq = dsi_pkt_seq_video_non_burst_syne;
1160                         break;
1161                 case TEGRA_DSI_VIDEO_NONE_BURST_MODE:
1162                 default:
1163                         pkt_seq_3_5_rgb_lo =
1164                                         DSI_PKT_SEQ_3_LO_PKT_32_ID(rgb_info);
1165                         pkt_seq = dsi_pkt_seq_video_non_burst;
1166                         break;
1167                 }
1168         }
1169
1170         for (i = 0; i < NUMOF_PKT_SEQ; i++) {
1171                 val = pkt_seq[i];
1172                 reg = dsi_pkt_seq_reg[i];
1173                 if ((reg == DSI_PKT_SEQ_3_LO) || (reg == DSI_PKT_SEQ_5_LO))
1174                         val |= pkt_seq_3_5_rgb_lo;
1175                 if ((reg == DSI_PKT_SEQ_3_HI) || (reg == DSI_PKT_SEQ_5_HI))
1176                         val |= pkt_seq_3_5_rgb_hi;
1177                 tegra_dsi_writel(dsi, val, reg);
1178         }
1179 }
1180
1181 static void tegra_dsi_reset_underflow_overflow
1182                                 (struct tegra_dc_dsi_data *dsi)
1183 {
1184         u32 val;
1185
1186         val = tegra_dsi_readl(dsi, DSI_STATUS);
1187         val &= (DSI_STATUS_LB_OVERFLOW(0x1) | DSI_STATUS_LB_UNDERFLOW(0x1));
1188         if (val) {
1189                 if (val & DSI_STATUS_LB_OVERFLOW(0x1))
1190                         dev_warn(&dsi->dc->ndev->dev,
1191                                 "dsi: video fifo overflow. Resetting flag\n");
1192                 if (val & DSI_STATUS_LB_UNDERFLOW(0x1))
1193                         dev_warn(&dsi->dc->ndev->dev,
1194                                 "dsi: video fifo underflow. Resetting flag\n");
1195                 val = tegra_dsi_readl(dsi, DSI_HOST_DSI_CONTROL);
1196                 val |= DSI_HOST_CONTROL_FIFO_STAT_RESET(0x1);
1197                 tegra_dsi_writel(dsi, val, DSI_HOST_DSI_CONTROL);
1198                 udelay(5);
1199         }
1200 }
1201
1202 static void tegra_dsi_stop_dc_stream(struct tegra_dc *dc,
1203                                         struct tegra_dc_dsi_data *dsi)
1204 {
1205         tegra_dc_writel(dc, DISP_CTRL_MODE_STOP, DC_CMD_DISPLAY_COMMAND);
1206         tegra_dc_writel(dc, 0, DC_DISP_DISP_WIN_OPTIONS);
1207         tegra_dc_writel(dc, GENERAL_UPDATE, DC_CMD_STATE_CONTROL);
1208         tegra_dc_writel(dc, GENERAL_ACT_REQ , DC_CMD_STATE_CONTROL);
1209
1210         dsi->status.dc_stream = DSI_DC_STREAM_DISABLE;
1211 }
1212
1213 static void tegra_dsi_stop_dc_stream_at_frame_end(struct tegra_dc *dc,
1214                                                 struct tegra_dc_dsi_data *dsi)
1215 {
1216         int val;
1217         long timeout;
1218         u32 frame_period = DIV_ROUND_UP(S_TO_MS(1), dsi->info.refresh_rate);
1219
1220         /* stop dc */
1221         tegra_dsi_stop_dc_stream(dc, dsi);
1222
1223         /* enable frame end interrupt */
1224         val = tegra_dc_readl(dc, DC_CMD_INT_MASK);
1225         val |= FRAME_END_INT;
1226         tegra_dc_writel(dc, val, DC_CMD_INT_MASK);
1227
1228         /* wait for frame_end completion.
1229          * timeout is 2 frame duration to accomodate for
1230          * internal delay.
1231          */
1232         timeout = wait_for_completion_interruptible_timeout(
1233                         &dc->frame_end_complete,
1234                         msecs_to_jiffies(2 * frame_period));
1235
1236         /* disable frame end interrupt */
1237         val = tegra_dc_readl(dc, DC_CMD_INT_MASK);
1238         val &= ~FRAME_END_INT;
1239         tegra_dc_writel(dc, val, DC_CMD_INT_MASK);
1240
1241         if (timeout == 0)
1242                 dev_warn(&dc->ndev->dev,
1243                         "DC doesn't stop at end of frame.\n");
1244
1245         tegra_dsi_reset_underflow_overflow(dsi);
1246 }
1247
1248 static void tegra_dsi_start_dc_stream(struct tegra_dc *dc,
1249                                         struct tegra_dc_dsi_data *dsi)
1250 {
1251         u32 val;
1252
1253         tegra_dc_writel(dc, DSI_ENABLE, DC_DISP_DISP_WIN_OPTIONS);
1254
1255         /* TODO: clean up */
1256         tegra_dc_writel(dc, PW0_ENABLE | PW1_ENABLE | PW2_ENABLE | PW3_ENABLE |
1257                         PW4_ENABLE | PM0_ENABLE | PM1_ENABLE,
1258                         DC_CMD_DISPLAY_POWER_CONTROL);
1259
1260         /* Configure one-shot mode or continuous mode */
1261         if (dc->out->flags & TEGRA_DC_OUT_ONE_SHOT_MODE) {
1262                 /* disable LSPI/LCD_DE output */
1263                 val = PIN_OUTPUT_LSPI_OUTPUT_DIS;
1264                 tegra_dc_writel(dc, val, DC_COM_PIN_OUTPUT_ENABLE3);
1265
1266                 /* enable MSF & set MSF polarity */
1267                 val = MSF_ENABLE | MSF_LSPI;
1268                 if (!dsi->info.te_polarity_low)
1269                         val |= MSF_POLARITY_HIGH;
1270                 else
1271                         val |= MSF_POLARITY_LOW;
1272                 tegra_dc_writel(dc, val, DC_CMD_DISPLAY_COMMAND_OPTION0);
1273
1274                 /* set non-continuous mode */
1275                 tegra_dc_writel(dc, DISP_CTRL_MODE_NC_DISPLAY,
1276                                                 DC_CMD_DISPLAY_COMMAND);
1277                 tegra_dc_writel(dc, GENERAL_UPDATE, DC_CMD_STATE_CONTROL);
1278                 tegra_dc_writel(dc, GENERAL_ACT_REQ | NC_HOST_TRIG,
1279                                                 DC_CMD_STATE_CONTROL);
1280         } else {
1281                 /* set continuous mode */
1282                 tegra_dc_writel(dc, DISP_CTRL_MODE_C_DISPLAY,
1283                                                 DC_CMD_DISPLAY_COMMAND);
1284                 tegra_dc_writel(dc, GENERAL_UPDATE, DC_CMD_STATE_CONTROL);
1285                 tegra_dc_writel(dc, GENERAL_ACT_REQ, DC_CMD_STATE_CONTROL);
1286         }
1287
1288         dsi->status.dc_stream = DSI_DC_STREAM_ENABLE;
1289 }
1290
1291 static void tegra_dsi_set_dc_clk(struct tegra_dc *dc,
1292                                 struct tegra_dc_dsi_data *dsi)
1293 {
1294         u32 shift_clk_div_register;
1295         u32 val;
1296
1297         /* Get the corresponding register value of shift_clk_div. */
1298         shift_clk_div_register = dsi->shift_clk_div * 2 - 2;
1299
1300 #ifdef CONFIG_TEGRA_FPGA_PLATFORM
1301         shift_clk_div_register = 1;
1302 #endif
1303
1304         /* TODO: find out if PCD3 option is required */
1305         val = PIXEL_CLK_DIVIDER_PCD1 |
1306                 SHIFT_CLK_DIVIDER(shift_clk_div_register);
1307         tegra_dc_writel(dc, val, DC_DISP_DISP_CLOCK_CONTROL);
1308 }
1309
1310 static void tegra_dsi_set_dsi_clk(struct tegra_dc *dc,
1311                         struct tegra_dc_dsi_data *dsi, u32 clk)
1312 {
1313         u32 rm;
1314
1315         /* Round up to MHz */
1316         rm = clk % 1000;
1317         if (rm != 0)
1318                 clk -= rm;
1319
1320         /* Set up pixel clock */
1321         dc->shift_clk_div = dsi->shift_clk_div;
1322         dc->mode.pclk = (clk * 1000) / dsi->shift_clk_div;
1323         /* TODO: Define one shot work delay in board file. */
1324         /* Since for one-shot mode, refresh rate is usually set larger than
1325          * expected refresh rate, it needs at least 3 frame period. Less
1326          * delay one shot work is, more powering saving we have. */
1327         dc->one_shot_delay_ms = 4 *
1328                         DIV_ROUND_UP(S_TO_MS(1), dsi->info.refresh_rate);
1329
1330         /* Enable DSI clock */
1331         tegra_dc_setup_clk(dc, dsi->dsi_clk);
1332         if (!dsi->clk_ref) {
1333                 dsi->clk_ref = true;
1334                 clk_enable(dsi->dsi_clk);
1335                 tegra_periph_reset_deassert(dsi->dsi_clk);
1336         }
1337         dsi->current_dsi_clk_khz = clk_get_rate(dsi->dsi_clk) / 1000;
1338         dsi->current_bit_clk_ns =  1000*1000 / (dsi->current_dsi_clk_khz * 2);
1339 }
1340
1341 static void tegra_dsi_hs_clk_out_enable(struct tegra_dc_dsi_data *dsi)
1342 {
1343         u32 val;
1344
1345         val = tegra_dsi_readl(dsi, DSI_CONTROL);
1346         val &= ~DSI_CONTROL_HS_CLK_CTRL(1);
1347
1348         if (dsi->info.video_clock_mode == TEGRA_DSI_VIDEO_CLOCK_CONTINUOUS) {
1349                 val |= DSI_CONTROL_HS_CLK_CTRL(CONTINUOUS);
1350                 dsi->status.clk_mode = DSI_PHYCLK_CONTINUOUS;
1351         } else {
1352                 val |= DSI_CONTROL_HS_CLK_CTRL(TX_ONLY);
1353                 dsi->status.clk_mode = DSI_PHYCLK_TX_ONLY;
1354         }
1355         tegra_dsi_writel(dsi, val, DSI_CONTROL);
1356
1357         val = tegra_dsi_readl(dsi, DSI_HOST_DSI_CONTROL);
1358         val &= ~DSI_HOST_DSI_CONTROL_HIGH_SPEED_TRANS(1);
1359         val |= DSI_HOST_DSI_CONTROL_HIGH_SPEED_TRANS(TEGRA_DSI_HIGH);
1360         tegra_dsi_writel(dsi, val, DSI_HOST_DSI_CONTROL);
1361
1362         dsi->status.clk_out = DSI_PHYCLK_OUT_EN;
1363 }
1364
1365 static void tegra_dsi_hs_clk_out_enable_in_lp(struct tegra_dc_dsi_data *dsi)
1366 {
1367         u32 val;
1368         tegra_dsi_hs_clk_out_enable(dsi);
1369
1370         val = tegra_dsi_readl(dsi, DSI_HOST_DSI_CONTROL);
1371         val &= ~DSI_HOST_DSI_CONTROL_HIGH_SPEED_TRANS(1);
1372         val |= DSI_HOST_DSI_CONTROL_HIGH_SPEED_TRANS(TEGRA_DSI_LOW);
1373         tegra_dsi_writel(dsi, val, DSI_HOST_DSI_CONTROL);
1374 }
1375
1376 static void tegra_dsi_hs_clk_out_disable(struct tegra_dc *dc,
1377                                                 struct tegra_dc_dsi_data *dsi)
1378 {
1379         u32 val;
1380
1381         if (dsi->status.dc_stream == DSI_DC_STREAM_ENABLE)
1382                 tegra_dsi_stop_dc_stream_at_frame_end(dc, dsi);
1383
1384         tegra_dsi_writel(dsi, TEGRA_DSI_DISABLE, DSI_POWER_CONTROL);
1385         /* stabilization delay */
1386         udelay(300);
1387
1388         val = tegra_dsi_readl(dsi, DSI_HOST_DSI_CONTROL);
1389         val &= ~DSI_HOST_DSI_CONTROL_HIGH_SPEED_TRANS(1);
1390         val |= DSI_HOST_DSI_CONTROL_HIGH_SPEED_TRANS(TEGRA_DSI_LOW);
1391         tegra_dsi_writel(dsi, val, DSI_HOST_DSI_CONTROL);
1392
1393         tegra_dsi_writel(dsi, TEGRA_DSI_ENABLE, DSI_POWER_CONTROL);
1394         /* stabilization delay */
1395         udelay(300);
1396
1397         dsi->status.clk_mode = DSI_PHYCLK_NOT_INIT;
1398         dsi->status.clk_out = DSI_PHYCLK_OUT_DIS;
1399 }
1400
1401 static void tegra_dsi_set_control_reg_lp(struct tegra_dc_dsi_data *dsi)
1402 {
1403         u32 dsi_control;
1404         u32 host_dsi_control;
1405         u32 max_threshold;
1406
1407         dsi_control = dsi->dsi_control_val | DSI_CTRL_HOST_DRIVEN;
1408         host_dsi_control = HOST_DSI_CTRL_COMMON |
1409                         HOST_DSI_CTRL_HOST_DRIVEN |
1410                         DSI_HOST_DSI_CONTROL_HIGH_SPEED_TRANS(TEGRA_DSI_LOW);
1411         max_threshold = DSI_MAX_THRESHOLD_MAX_THRESHOLD(DSI_HOST_FIFO_DEPTH);
1412
1413         tegra_dsi_writel(dsi, max_threshold, DSI_MAX_THRESHOLD);
1414         tegra_dsi_writel(dsi, dsi_control, DSI_CONTROL);
1415         tegra_dsi_writel(dsi, host_dsi_control, DSI_HOST_DSI_CONTROL);
1416
1417         dsi->status.driven = DSI_DRIVEN_MODE_HOST;
1418         dsi->status.clk_burst = DSI_CLK_BURST_NOT_INIT;
1419         dsi->status.vtype = DSI_VIDEO_TYPE_NOT_INIT;
1420 }
1421
1422 static void tegra_dsi_set_control_reg_hs(struct tegra_dc_dsi_data *dsi)
1423 {
1424         u32 dsi_control;
1425         u32 host_dsi_control;
1426         u32 max_threshold;
1427         u32 dcs_cmd;
1428
1429         dsi_control = dsi->dsi_control_val;
1430         host_dsi_control = HOST_DSI_CTRL_COMMON;
1431         max_threshold = 0;
1432         dcs_cmd = 0;
1433
1434         if (dsi->driven_mode == TEGRA_DSI_DRIVEN_BY_HOST) {
1435                 dsi_control |= DSI_CTRL_HOST_DRIVEN;
1436                 host_dsi_control |= HOST_DSI_CTRL_HOST_DRIVEN;
1437                 max_threshold =
1438                         DSI_MAX_THRESHOLD_MAX_THRESHOLD(DSI_HOST_FIFO_DEPTH);
1439                 dsi->status.driven = DSI_DRIVEN_MODE_HOST;
1440         } else {
1441                 dsi_control |= DSI_CTRL_DC_DRIVEN;
1442                 host_dsi_control |= HOST_DSI_CTRL_DC_DRIVEN;
1443                 max_threshold =
1444                         DSI_MAX_THRESHOLD_MAX_THRESHOLD(DSI_VIDEO_FIFO_DEPTH);
1445                 dsi->status.driven = DSI_DRIVEN_MODE_DC;
1446         }
1447
1448         if (dsi->info.video_data_type == TEGRA_DSI_VIDEO_TYPE_COMMAND_MODE) {
1449                 dsi_control |= DSI_CTRL_CMD_MODE;
1450                 dcs_cmd = DSI_DCS_CMDS_LT5_DCS_CMD(DSI_WRITE_MEMORY_START)|
1451                         DSI_DCS_CMDS_LT3_DCS_CMD(DSI_WRITE_MEMORY_CONTINUE);
1452                 dsi->status.vtype = DSI_VIDEO_TYPE_CMD_MODE;
1453
1454         } else {
1455                 dsi_control |= DSI_CTRL_VIDEO_MODE;
1456                 dsi->status.vtype = DSI_VIDEO_TYPE_VIDEO_MODE;
1457         }
1458
1459         tegra_dsi_writel(dsi, max_threshold, DSI_MAX_THRESHOLD);
1460         tegra_dsi_writel(dsi, dcs_cmd, DSI_DCS_CMDS);
1461         tegra_dsi_writel(dsi, dsi_control, DSI_CONTROL);
1462         tegra_dsi_writel(dsi, host_dsi_control, DSI_HOST_DSI_CONTROL);
1463 }
1464
1465 static void tegra_dsi_pad_calibration(struct tegra_dc_dsi_data *dsi)
1466 {
1467         u32 val;
1468
1469         val =   DSI_PAD_CONTROL_PAD_LPUPADJ(0x1) |
1470                 DSI_PAD_CONTROL_PAD_LPDNADJ(0x1) |
1471                 DSI_PAD_CONTROL_PAD_PREEMP_EN(0x1) |
1472                 DSI_PAD_CONTROL_PAD_SLEWDNADJ(0x6) |
1473                 DSI_PAD_CONTROL_PAD_SLEWUPADJ(0x6);
1474         if (!dsi->ulpm) {
1475                 val |=  DSI_PAD_CONTROL_PAD_PDIO(0) |
1476                         DSI_PAD_CONTROL_PAD_PDIO_CLK(0) |
1477                         DSI_PAD_CONTROL_PAD_PULLDN_ENAB(TEGRA_DSI_DISABLE);
1478         } else {
1479                 val |=  DSI_PAD_CONTROL_PAD_PDIO(0x3) |
1480                         DSI_PAD_CONTROL_PAD_PDIO_CLK(0x1) |
1481                         DSI_PAD_CONTROL_PAD_PULLDN_ENAB(TEGRA_DSI_ENABLE);
1482         }
1483         tegra_dsi_writel(dsi, val, DSI_PAD_CONTROL);
1484
1485         val = MIPI_CAL_TERMOSA(0x4);
1486         tegra_vi_csi_writel(val, CSI_CILA_MIPI_CAL_CONFIG_0);
1487
1488         val = MIPI_CAL_TERMOSB(0x4);
1489         tegra_vi_csi_writel(val, CSI_CILB_MIPI_CAL_CONFIG_0);
1490
1491         val = MIPI_CAL_HSPUOSD(0x3) | MIPI_CAL_HSPDOSD(0x4);
1492         tegra_vi_csi_writel(val, CSI_DSI_MIPI_CAL_CONFIG);
1493
1494         val = PAD_DRIV_DN_REF(0x5) | PAD_DRIV_UP_REF(0x7);
1495         tegra_vi_csi_writel(val, CSI_MIPIBIAS_PAD_CONFIG);
1496
1497         val = PAD_CIL_PDVREG(0x0);
1498         tegra_vi_csi_writel(val, CSI_CIL_PAD_CONFIG);
1499 }
1500
1501 static int tegra_dsi_init_hw(struct tegra_dc *dc,
1502                                                 struct tegra_dc_dsi_data *dsi)
1503 {
1504         u32 i;
1505
1506         tegra_dsi_writel(dsi,
1507                 DSI_POWER_CONTROL_LEG_DSI_ENABLE(TEGRA_DSI_DISABLE),
1508                 DSI_POWER_CONTROL);
1509         /* stabilization delay */
1510         udelay(300);
1511
1512         tegra_dsi_set_dsi_clk(dc, dsi, dsi->target_lp_clk_khz);
1513         if (dsi->info.dsi_instance) {
1514                 /* TODO:Set the misc register*/
1515         }
1516
1517         /* TODO: only need to change the timing for bta */
1518         tegra_dsi_set_phy_timing(dsi, DSI_LPHS_IN_LP_MODE);
1519
1520         if (dsi->status.dc_stream == DSI_DC_STREAM_ENABLE)
1521                 tegra_dsi_stop_dc_stream_at_frame_end(dc, dsi);
1522
1523         /* Initializing DSI registers */
1524         for (i = 0; i < ARRAY_SIZE(init_reg); i++)
1525                 tegra_dsi_writel(dsi, 0, init_reg[i]);
1526
1527         tegra_dsi_writel(dsi, dsi->dsi_control_val, DSI_CONTROL);
1528
1529         tegra_dsi_pad_calibration(dsi);
1530
1531         tegra_dsi_writel(dsi,
1532                 DSI_POWER_CONTROL_LEG_DSI_ENABLE(TEGRA_DSI_ENABLE),
1533                 DSI_POWER_CONTROL);
1534         /* stabilization delay */
1535         udelay(300);
1536
1537         dsi->status.init = DSI_MODULE_INIT;
1538         dsi->status.lphs = DSI_LPHS_NOT_INIT;
1539         dsi->status.vtype = DSI_VIDEO_TYPE_NOT_INIT;
1540         dsi->status.driven = DSI_DRIVEN_MODE_NOT_INIT;
1541         dsi->status.clk_out = DSI_PHYCLK_OUT_DIS;
1542         dsi->status.clk_mode = DSI_PHYCLK_NOT_INIT;
1543         dsi->status.clk_burst = DSI_CLK_BURST_NOT_INIT;
1544         dsi->status.dc_stream = DSI_DC_STREAM_DISABLE;
1545         dsi->status.lp_op = DSI_LP_OP_NOT_INIT;
1546
1547         return 0;
1548 }
1549
1550 static int tegra_dsi_set_to_lp_mode(struct tegra_dc *dc,
1551                         struct tegra_dc_dsi_data *dsi, u8 lp_op)
1552 {
1553         int err;
1554
1555         if (dsi->status.init != DSI_MODULE_INIT) {
1556                 err = -EPERM;
1557                 goto fail;
1558         }
1559
1560         if (dsi->status.lphs == DSI_LPHS_IN_LP_MODE &&
1561                         dsi->status.lp_op == lp_op)
1562                 goto success;
1563
1564         if (dsi->status.dc_stream == DSI_DC_STREAM_ENABLE)
1565                 tegra_dsi_stop_dc_stream_at_frame_end(dc, dsi);
1566
1567         /* disable/enable hs clk according to enable_hs_clock_on_lp_cmd_mode */
1568         if ((dsi->status.clk_out == DSI_PHYCLK_OUT_EN) &&
1569                 (!dsi->info.enable_hs_clock_on_lp_cmd_mode))
1570                 tegra_dsi_hs_clk_out_disable(dc, dsi);
1571
1572         dsi->target_lp_clk_khz = tegra_dsi_get_lp_clk_rate(dsi, lp_op);
1573         if (dsi->current_dsi_clk_khz != dsi->target_lp_clk_khz) {
1574                 tegra_dsi_set_dsi_clk(dc, dsi, dsi->target_lp_clk_khz);
1575                 tegra_dsi_set_timeout(dsi);
1576         }
1577
1578         tegra_dsi_set_phy_timing(dsi, DSI_LPHS_IN_LP_MODE);
1579
1580         tegra_dsi_set_control_reg_lp(dsi);
1581
1582         if ((dsi->status.clk_out == DSI_PHYCLK_OUT_DIS) &&
1583                 (dsi->info.enable_hs_clock_on_lp_cmd_mode))
1584                 tegra_dsi_hs_clk_out_enable_in_lp(dsi);
1585
1586         dsi->status.lphs = DSI_LPHS_IN_LP_MODE;
1587         dsi->status.lp_op = lp_op;
1588 success:
1589         err = 0;
1590 fail:
1591         return err;
1592 }
1593
1594 static int tegra_dsi_set_to_hs_mode(struct tegra_dc *dc,
1595                                         struct tegra_dc_dsi_data *dsi)
1596 {
1597         int err;
1598
1599         if (dsi->status.init != DSI_MODULE_INIT) {
1600                 err = -EPERM;
1601                 goto fail;
1602         }
1603
1604         if (dsi->status.lphs == DSI_LPHS_IN_HS_MODE)
1605                 goto success;
1606
1607         if (dsi->status.dc_stream == DSI_DC_STREAM_ENABLE)
1608                 tegra_dsi_stop_dc_stream_at_frame_end(dc, dsi);
1609
1610         if ((dsi->status.clk_out == DSI_PHYCLK_OUT_EN) &&
1611                 (!dsi->info.enable_hs_clock_on_lp_cmd_mode))
1612                 tegra_dsi_hs_clk_out_disable(dc, dsi);
1613
1614         if (dsi->current_dsi_clk_khz != dsi->target_hs_clk_khz) {
1615                 tegra_dsi_set_dsi_clk(dc, dsi, dsi->target_hs_clk_khz);
1616                 tegra_dsi_set_timeout(dsi);
1617         }
1618
1619         tegra_dsi_set_phy_timing(dsi, DSI_LPHS_IN_HS_MODE);
1620
1621         if (dsi->driven_mode == TEGRA_DSI_DRIVEN_BY_DC) {
1622                 tegra_dsi_set_pkt_seq(dc, dsi);
1623                 tegra_dsi_set_pkt_length(dc, dsi);
1624                 tegra_dsi_set_sol_delay(dc, dsi);
1625                 tegra_dsi_set_dc_clk(dc, dsi);
1626         }
1627
1628         tegra_dsi_set_control_reg_hs(dsi);
1629
1630         if (dsi->status.clk_out == DSI_PHYCLK_OUT_DIS ||
1631                 dsi->info.enable_hs_clock_on_lp_cmd_mode)
1632                 tegra_dsi_hs_clk_out_enable(dsi);
1633
1634         dsi->status.lphs = DSI_LPHS_IN_HS_MODE;
1635 success:
1636         dsi->status.lp_op = DSI_LP_OP_NOT_INIT;
1637         err = 0;
1638 fail:
1639         return err;
1640 }
1641
1642 static bool tegra_dsi_write_busy(struct tegra_dc_dsi_data *dsi)
1643 {
1644         u32 timeout = 0;
1645         bool retVal = true;
1646
1647         while (timeout <= DSI_MAX_COMMAND_DELAY_USEC) {
1648                 if (!(DSI_TRIGGER_HOST_TRIGGER(0x1) &
1649                         tegra_dsi_readl(dsi, DSI_TRIGGER))) {
1650                         retVal = false;
1651                         break;
1652                 }
1653                 udelay(DSI_COMMAND_DELAY_STEPS_USEC);
1654                 timeout += DSI_COMMAND_DELAY_STEPS_USEC;
1655         }
1656
1657         return retVal;
1658 }
1659
1660 static bool tegra_dsi_read_busy(struct tegra_dc_dsi_data *dsi)
1661 {
1662         u32 timeout = 0;
1663         bool retVal = true;
1664
1665         while (timeout <  DSI_STATUS_POLLING_DURATION_USEC) {
1666                 if (!(DSI_HOST_DSI_CONTROL_IMM_BTA(0x1) &
1667                         tegra_dsi_readl(dsi, DSI_HOST_DSI_CONTROL))) {
1668                         retVal = false;
1669                         break;
1670                 }
1671                 udelay(DSI_STATUS_POLLING_DELAY_USEC);
1672                 timeout += DSI_STATUS_POLLING_DELAY_USEC;
1673         }
1674
1675         return retVal;
1676 }
1677
1678 static bool tegra_dsi_host_busy(struct tegra_dc_dsi_data *dsi)
1679 {
1680         int err = 0;
1681
1682         if (tegra_dsi_write_busy(dsi)) {
1683                 err = -EBUSY;
1684                 dev_err(&dsi->dc->ndev->dev,
1685                         "DSI trigger bit already set\n");
1686                 goto fail;
1687         }
1688
1689         if (tegra_dsi_read_busy(dsi)) {
1690                 err = -EBUSY;
1691                 dev_err(&dsi->dc->ndev->dev,
1692                         "DSI immediate bta bit already set\n");
1693                 goto fail;
1694         }
1695 fail:
1696         return (err < 0 ? true : false);
1697 }
1698
1699 static void tegra_dsi_soft_reset(struct tegra_dc_dsi_data *dsi)
1700 {
1701         tegra_dsi_writel(dsi,
1702                 DSI_POWER_CONTROL_LEG_DSI_ENABLE(TEGRA_DSI_DISABLE),
1703                 DSI_POWER_CONTROL);
1704         /* stabilization delay */
1705         udelay(300);
1706
1707         tegra_dsi_writel(dsi,
1708                 DSI_POWER_CONTROL_LEG_DSI_ENABLE(TEGRA_DSI_ENABLE),
1709                 DSI_POWER_CONTROL);
1710         /* stabilization delay */
1711         udelay(300);
1712 }
1713
1714 static void tegra_dsi_reset_read_count(struct tegra_dc_dsi_data *dsi)
1715 {
1716         u32 val;
1717
1718         val = tegra_dsi_readl(dsi, DSI_STATUS);
1719         val &= DSI_STATUS_RD_FIFO_COUNT(0x1f);
1720         if (val) {
1721                 dev_warn(&dsi->dc->ndev->dev,
1722                         "DSI read count not zero, resetting\n");
1723                 tegra_dsi_soft_reset(dsi);
1724         }
1725 }
1726
1727 static struct dsi_status *tegra_dsi_save_state_switch_to_host_cmd_mode(
1728                                                 struct tegra_dc_dsi_data *dsi,
1729                                                 struct tegra_dc *dc,
1730                                                 u8 lp_op)
1731 {
1732         struct dsi_status *init_status;
1733         int err;
1734
1735         init_status = kzalloc(sizeof(*init_status), GFP_KERNEL);
1736         if (!init_status)
1737                 return ERR_PTR(-ENOMEM);
1738
1739         *init_status = dsi->status;
1740
1741         if (dsi->status.lphs == DSI_LPHS_IN_HS_MODE) {
1742                 if (dsi->status.driven == DSI_DRIVEN_MODE_DC) {
1743                         if (dsi->status.dc_stream == DSI_DC_STREAM_ENABLE)
1744                                 tegra_dsi_stop_dc_stream_at_frame_end(dc, dsi);
1745                         dsi->driven_mode = TEGRA_DSI_DRIVEN_BY_HOST;
1746                         if (dsi->info.hs_cmd_mode_supported) {
1747                                 err = tegra_dsi_set_to_hs_mode(dc, dsi);
1748                                 if (err < 0) {
1749                                         dev_err(&dc->ndev->dev,
1750                                         "Switch to HS host mode failed\n");
1751                                         goto fail;
1752                                 }
1753                         }
1754                 }
1755                 if (!dsi->info.hs_cmd_mode_supported) {
1756                         err =
1757                         tegra_dsi_set_to_lp_mode(dc, dsi, lp_op);
1758                         if (err < 0) {
1759                                 dev_err(&dc->ndev->dev,
1760                                 "DSI failed to go to LP mode\n");
1761                                 goto fail;
1762                         }
1763                 }
1764         } else if (dsi->status.lphs == DSI_LPHS_IN_LP_MODE) {
1765                 if (dsi->status.lp_op != lp_op) {
1766                         err = tegra_dsi_set_to_lp_mode(dc, dsi, lp_op);
1767                         if (err < 0) {
1768                                 dev_err(&dc->ndev->dev,
1769                                 "DSI failed to go to LP mode\n");
1770                                 goto fail;
1771                         }
1772                 }
1773         }
1774
1775         return init_status;
1776 fail:
1777         kfree(init_status);
1778         return ERR_PTR(err);
1779 }
1780
1781 static struct dsi_status *tegra_dsi_prepare_host_transmission(
1782                                 struct tegra_dc *dc,
1783                                 struct tegra_dc_dsi_data *dsi,
1784                                 u8 lp_op)
1785 {
1786         int err = 0;
1787         struct dsi_status *init_status;
1788
1789         if (dsi->status.init != DSI_MODULE_INIT ||
1790                 dsi->ulpm) {
1791                 err = -EPERM;
1792                 goto fail;
1793         }
1794
1795         if (tegra_dsi_host_busy(dsi)) {
1796                 tegra_dsi_soft_reset(dsi);
1797                 if (tegra_dsi_host_busy(dsi)) {
1798                         err = -EBUSY;
1799                         dev_err(&dc->ndev->dev, "DSI host busy\n");
1800                         goto fail;
1801                 }
1802         }
1803
1804         if (lp_op == DSI_LP_OP_READ)
1805                 tegra_dsi_reset_read_count(dsi);
1806
1807         if (dsi->status.lphs == DSI_LPHS_NOT_INIT) {
1808                 err = tegra_dsi_set_to_lp_mode(dc, dsi, lp_op);
1809                 if (err < 0) {
1810                         dev_err(&dc->ndev->dev, "Failed to config LP write\n");
1811                         goto fail;
1812                 }
1813         }
1814
1815         init_status = tegra_dsi_save_state_switch_to_host_cmd_mode
1816                                         (dsi, dc, lp_op);
1817         if (IS_ERR_OR_NULL(init_status)) {
1818                 err = PTR_ERR(init_status);
1819                 dev_err(&dc->ndev->dev, "DSI state saving failed\n");
1820                 goto fail;
1821         }
1822
1823         return init_status;
1824 fail:
1825         return ERR_PTR(err);
1826 }
1827
1828 static int tegra_dsi_restore_state(struct tegra_dc *dc,
1829                                 struct tegra_dc_dsi_data *dsi,
1830                                 struct dsi_status *init_status)
1831 {
1832         bool switch_back_to_dc_mode = false;
1833         bool switch_back_to_hs_mode = false;
1834         bool restart_dc_stream;
1835         int err = 0;
1836
1837         switch_back_to_dc_mode = (dsi->status.driven ==
1838                                 DSI_DRIVEN_MODE_HOST &&
1839                                 init_status->driven ==
1840                                 DSI_DRIVEN_MODE_DC);
1841         switch_back_to_hs_mode = (dsi->status.lphs ==
1842                                 DSI_LPHS_IN_LP_MODE &&
1843                                 init_status->lphs ==
1844                                 DSI_LPHS_IN_HS_MODE);
1845         restart_dc_stream = (dsi->status.dc_stream ==
1846                                 DSI_DC_STREAM_DISABLE &&
1847                                 init_status->dc_stream ==
1848                                 DSI_DC_STREAM_ENABLE);
1849
1850         if (dsi->status.lphs == DSI_LPHS_IN_LP_MODE &&
1851                 init_status->lphs == DSI_LPHS_IN_LP_MODE) {
1852                 if (dsi->status.lp_op != init_status->lp_op) {
1853                         err =
1854                         tegra_dsi_set_to_lp_mode(dc, dsi, init_status->lp_op);
1855                         if (err < 0) {
1856                                 dev_err(&dc->ndev->dev,
1857                                         "Failed to config LP mode\n");
1858                                 goto fail;
1859                         }
1860                 }
1861                 goto success;
1862         }
1863
1864         if (switch_back_to_dc_mode)
1865                 dsi->driven_mode = TEGRA_DSI_DRIVEN_BY_DC;
1866         if (switch_back_to_dc_mode || switch_back_to_hs_mode) {
1867                 err = tegra_dsi_set_to_hs_mode(dc, dsi);
1868                 if (err < 0) {
1869                         dev_err(&dc->ndev->dev, "Failed to config HS mode\n");
1870                         goto fail;
1871                 }
1872         }
1873         if (restart_dc_stream)
1874                 tegra_dsi_start_dc_stream(dc, dsi);
1875
1876 success:
1877 fail:
1878         kfree(init_status);
1879         return err;
1880 }
1881
1882 static int tegra_dsi_host_trigger(struct tegra_dc_dsi_data *dsi)
1883 {
1884         int status = 0;
1885
1886         if (tegra_dsi_readl(dsi, DSI_TRIGGER)) {
1887                 status = -EBUSY;
1888                 goto fail;
1889         }
1890
1891         tegra_dsi_writel(dsi,
1892                 DSI_TRIGGER_HOST_TRIGGER(TEGRA_DSI_ENABLE), DSI_TRIGGER);
1893
1894 #if DSI_USE_SYNC_POINTS
1895         status = tegra_dsi_syncpt(dsi);
1896         if (status < 0) {
1897                 dev_err(&dsi->dc->ndev->dev,
1898                         "DSI syncpt for host trigger failed\n");
1899                 goto fail;
1900         }
1901 #else
1902         if (tegra_dsi_write_busy(dsi)) {
1903                 status = -EBUSY;
1904                 dev_err(&dsi->dc->ndev->dev,
1905                         "Timeout waiting on write completion\n");
1906         }
1907 #endif
1908
1909 fail:
1910         return status;
1911 }
1912
1913 static int _tegra_dsi_write_data(struct tegra_dc_dsi_data *dsi,
1914                                         u8 *pdata, u8 data_id, u16 data_len)
1915 {
1916         u8 virtual_channel;
1917         u8 *pval;
1918         u32 val;
1919         int err;
1920
1921         err = 0;
1922
1923         virtual_channel = dsi->info.virtual_channel <<
1924                                                 DSI_VIR_CHANNEL_BIT_POSITION;
1925
1926         /* always use hw for ecc */
1927         val = (virtual_channel | data_id) << 0 |
1928                         data_len << 8;
1929         tegra_dsi_writel(dsi, val, DSI_WR_DATA);
1930
1931         /* if pdata != NULL, pkt type is long pkt */
1932         if (pdata != NULL) {
1933                 while (data_len) {
1934                         if (data_len >= 4) {
1935                                 val = ((u32 *) pdata)[0];
1936                                 data_len -= 4;
1937                                 pdata += 4;
1938                         } else {
1939                                 val = 0;
1940                                 pval = (u8 *) &val;
1941                                 do
1942                                         *pval++ = *pdata++;
1943                                 while (--data_len);
1944                         }
1945                         tegra_dsi_writel(dsi, val, DSI_WR_DATA);
1946                 }
1947         }
1948
1949         err = tegra_dsi_host_trigger(dsi);
1950         if (err < 0)
1951                 dev_err(&dsi->dc->ndev->dev, "DSI host trigger failed\n");
1952
1953         return err;
1954 }
1955
1956 int tegra_dsi_write_data(struct tegra_dc *dc,
1957                         struct tegra_dc_dsi_data *dsi,
1958                         u8 *pdata, u8 data_id, u16 data_len)
1959 {
1960         int err = 0;
1961         struct dsi_status *init_status;
1962
1963         tegra_dc_io_start(dc);
1964
1965         init_status = tegra_dsi_prepare_host_transmission(
1966                                 dc, dsi, DSI_LP_OP_WRITE);
1967         if (IS_ERR_OR_NULL(init_status)) {
1968                 err = PTR_ERR(init_status);
1969                 dev_err(&dc->ndev->dev, "DSI host config failed\n");
1970                 goto fail;
1971         }
1972
1973         err = _tegra_dsi_write_data(dsi, pdata, data_id, data_len);
1974 fail:
1975         err = tegra_dsi_restore_state(dc, dsi, init_status);
1976         if (err < 0)
1977                 dev_err(&dc->ndev->dev, "Failed to restore prev state\n");
1978         tegra_dc_io_end(dc);
1979         return err;
1980 }
1981 EXPORT_SYMBOL(tegra_dsi_write_data);
1982
1983 static int tegra_dsi_send_panel_cmd(struct tegra_dc *dc,
1984                                         struct tegra_dc_dsi_data *dsi,
1985                                         struct tegra_dsi_cmd *cmd,
1986                                         u32 n_cmd)
1987 {
1988         u32 i;
1989         int err;
1990
1991         err = 0;
1992         for (i = 0; i < n_cmd; i++) {
1993                 struct tegra_dsi_cmd *cur_cmd;
1994                 cur_cmd = &cmd[i];
1995
1996                 if (cur_cmd->cmd_type == TEGRA_DSI_DELAY_MS)
1997                         mdelay(cur_cmd->sp_len_dly.delay_ms);
1998                 else {
1999                         err = tegra_dsi_write_data(dc, dsi,
2000                                                 cur_cmd->pdata,
2001                                                 cur_cmd->data_id,
2002                                                 cur_cmd->sp_len_dly.data_len);
2003                         if (err < 0)
2004                                 break;
2005                 }
2006         }
2007         return err;
2008 }
2009
2010 static u8 get_8bit_ecc(u32 header)
2011 {
2012         char ecc_parity[24] = {
2013                 0x07, 0x0b, 0x0d, 0x0e, 0x13, 0x15, 0x16, 0x19,
2014                 0x1a, 0x1c, 0x23, 0x25, 0x26, 0x29, 0x2a, 0x2c,
2015                 0x31, 0x32, 0x34, 0x38, 0x1f, 0x2f, 0x37, 0x3b
2016         };
2017         u8 ecc_byte;
2018         int i;
2019
2020         ecc_byte = 0;
2021         for (i = 0; i < 24; i++)
2022                 ecc_byte ^= ((header >> i) & 1) ? ecc_parity[i] : 0x00;
2023
2024         return ecc_byte;
2025 }
2026
2027 /* This function is written to send DCS short write (1 parameter) only.
2028  * This means the cmd will contain only 1 byte of index and 1 byte of value.
2029  * The data type ID is fixed at 0x15 and the ECC is calculated based on the
2030  * data in pdata.
2031  * The command will be sent by hardware every frame.
2032  * pdata should contain both the index + value for each cmd.
2033  * data_len will be the total number of bytes in pdata.
2034  */
2035 int tegra_dsi_send_panel_short_cmd(struct tegra_dc *dc, u8 *pdata, u8 data_len)
2036 {
2037         u8 ecc8bits = 0, data_len_orig = 0;
2038         u32 val = 0, pkthdr = 0;
2039         int err = 0, count = 0;
2040         struct tegra_dc_dsi_data *dsi = tegra_dc_get_outdata(dc);
2041
2042         data_len_orig = data_len;
2043         if (pdata != NULL) {
2044                 while (data_len) {
2045                         if (data_len >= 2) {
2046                                 pkthdr = (CMD_SHORTW |
2047                                         (((u16 *)pdata)[0]) << 8 | 0x00 << 24);
2048                                 ecc8bits = get_8bit_ecc(pkthdr);
2049                                 val = (pkthdr | (ecc8bits << 24));
2050                                 data_len -= 2;
2051                                 pdata += 2;
2052                                 count++;
2053                         }
2054                         switch (count) {
2055                         case 1:
2056                                 tegra_dsi_writel(dsi, val, DSI_INIT_SEQ_DATA_0);
2057                                 break;
2058                         case 2:
2059                                 tegra_dsi_writel(dsi, val, DSI_INIT_SEQ_DATA_1);
2060                                 break;
2061                         case 3:
2062                                 tegra_dsi_writel(dsi, val, DSI_INIT_SEQ_DATA_2);
2063                                 break;
2064                         case 4:
2065                                 tegra_dsi_writel(dsi, val, DSI_INIT_SEQ_DATA_3);
2066                                 break;
2067                         case 5:
2068                                 tegra_dsi_writel(dsi, val, DSI_INIT_SEQ_DATA_4);
2069                                 break;
2070                         case 6:
2071                                 tegra_dsi_writel(dsi, val, DSI_INIT_SEQ_DATA_5);
2072                                 break;
2073                         case 7:
2074                                 tegra_dsi_writel(dsi, val, DSI_INIT_SEQ_DATA_6);
2075                                 break;
2076                         case 8:
2077                                 tegra_dsi_writel(dsi, val, DSI_INIT_SEQ_DATA_7);
2078                                 break;
2079                         default:
2080                                 err = 1;
2081                                 break;
2082                         }
2083                 }
2084         }
2085
2086         val = DSI_INIT_SEQ_CONTROL_DSI_FRAME_INIT_BYTE_COUNT(data_len_orig * 2)
2087                 | DSI_INIT_SEQ_CONTROL_DSI_SEND_INIT_SEQUENCE(1);
2088         tegra_dsi_writel(dsi, val, DSI_INIT_SEQ_CONTROL);
2089
2090         return err;
2091 }
2092 EXPORT_SYMBOL(tegra_dsi_send_panel_short_cmd);
2093
2094 static int tegra_dsi_bta(struct tegra_dc_dsi_data *dsi)
2095 {
2096         u32 val;
2097         u32 poll_time;
2098         int err;
2099
2100         poll_time = 0;
2101         err = 0;
2102
2103         val = tegra_dsi_readl(dsi, DSI_HOST_DSI_CONTROL);
2104         val |= DSI_HOST_DSI_CONTROL_IMM_BTA(TEGRA_DSI_ENABLE);
2105         tegra_dsi_writel(dsi, val, DSI_HOST_DSI_CONTROL);
2106
2107 #if DSI_USE_SYNC_POINTS
2108         /* FIXME: Workaround for nvhost_syncpt_read */
2109         dsi->syncpt_val = nvhost_syncpt_update_min(
2110                         &nvhost_get_host(dsi->dc->ndev)->syncpt,
2111                         dsi->syncpt_id);
2112
2113         val = DSI_INCR_SYNCPT_COND(OP_DONE) |
2114                 DSI_INCR_SYNCPT_INDX(dsi->syncpt_id);
2115         tegra_dsi_writel(dsi, val, DSI_INCR_SYNCPT);
2116
2117         /* TODO: Use interrupt rather than polling */
2118         err = nvhost_syncpt_wait(&nvhost_get_host(dsi->dc->ndev)->syncpt,
2119                 dsi->syncpt_id, dsi->syncpt_val + 1);
2120         if (err < 0)
2121                 dev_err(&dsi->dc->ndev->dev,
2122                         "DSI sync point failure\n");
2123         else
2124                 (dsi->syncpt_val)++;
2125 #else
2126         if (tegra_dsi_read_busy(dsi)) {
2127                 err = -EBUSY;
2128                 dev_err(&dsi->dc->ndev->dev,
2129                         "Timeout wating on read completion\n");
2130         }
2131 #endif
2132
2133         return err;
2134 }
2135
2136 static int tegra_dsi_parse_read_response(struct tegra_dc *dc,
2137                                         u32 rd_fifo_cnt, u8 *read_fifo)
2138 {
2139         int err;
2140         u32 payload_size;
2141
2142         payload_size = 0;
2143         err = 0;
2144
2145         switch (read_fifo[0]) {
2146         case DSI_ESCAPE_CMD:
2147                 dev_info(&dc->ndev->dev, "escape cmd[0x%x]\n", read_fifo[0]);
2148                 break;
2149         case DSI_ACK_NO_ERR:
2150                 dev_info(&dc->ndev->dev,
2151                         "Panel ack, no err[0x%x]\n", read_fifo[0]);
2152                 return err;
2153         default:
2154                 dev_info(&dc->ndev->dev, "Invalid read response\n");
2155                 break;
2156         }
2157
2158         switch (read_fifo[4] & 0xff) {
2159         case GEN_LONG_RD_RES:
2160                 /* Fall through */
2161         case DCS_LONG_RD_RES:
2162                 payload_size = (read_fifo[5] |
2163                                 (read_fifo[6] << 8)) & 0xFFFF;
2164                 dev_info(&dc->ndev->dev, "Long read response Packet\n"
2165                                 "payload_size[0x%x]\n", payload_size);
2166                 break;
2167         case GEN_1_BYTE_SHORT_RD_RES:
2168                 /* Fall through */
2169         case DCS_1_BYTE_SHORT_RD_RES:
2170                 payload_size = 1;
2171                 dev_info(&dc->ndev->dev, "Short read response Packet\n"
2172                         "payload_size[0x%x]\n", payload_size);
2173                 break;
2174         case GEN_2_BYTE_SHORT_RD_RES:
2175                 /* Fall through */
2176         case DCS_2_BYTE_SHORT_RD_RES:
2177                 payload_size = 2;
2178                 dev_info(&dc->ndev->dev, "Short read response Packet\n"
2179                         "payload_size[0x%x]\n", payload_size);
2180                 break;
2181         case ACK_ERR_RES:
2182                 payload_size = 2;
2183                 dev_info(&dc->ndev->dev, "Acknowledge error report response\n"
2184                         "Packet payload_size[0x%x]\n", payload_size);
2185                 break;
2186         default:
2187                 dev_info(&dc->ndev->dev, "Invalid response packet\n");
2188                 err = -EINVAL;
2189                 break;
2190         }
2191         return err;
2192 }
2193
2194 static int tegra_dsi_read_fifo(struct tegra_dc *dc,
2195                         struct tegra_dc_dsi_data *dsi,
2196                         u8 *read_fifo)
2197 {
2198         u32 val;
2199         u32 i;
2200         u32 poll_time = 0;
2201         u32 rd_fifo_cnt;
2202         int err = 0;
2203         u8 *read_fifo_cp = read_fifo;
2204
2205         while (poll_time <  DSI_DELAY_FOR_READ_FIFO) {
2206                 mdelay(1);
2207                 val = tegra_dsi_readl(dsi, DSI_STATUS);
2208                 rd_fifo_cnt = val & DSI_STATUS_RD_FIFO_COUNT(0x1f);
2209                 if (rd_fifo_cnt << 2 > DSI_READ_FIFO_DEPTH)
2210                         dev_err(&dc->ndev->dev,
2211                         "DSI RD_FIFO_CNT is greater than RD_FIFO_DEPTH\n");
2212                         break;
2213                 poll_time++;
2214         }
2215
2216         if (rd_fifo_cnt == 0) {
2217                 dev_info(&dc->ndev->dev,
2218                         "DSI RD_FIFO_CNT is zero\n");
2219                 err = -EINVAL;
2220                 goto fail;
2221         }
2222
2223         if (val & (DSI_STATUS_LB_UNDERFLOW(0x1) |
2224                 DSI_STATUS_LB_OVERFLOW(0x1))) {
2225                 dev_warn(&dc->ndev->dev,
2226                         "DSI overflow/underflow error\n");
2227         }
2228
2229         /* Read data from FIFO */
2230         for (i = 0; i < rd_fifo_cnt; i++) {
2231                 val = tegra_dsi_readl(dsi, DSI_RD_DATA);
2232                 if (enable_read_debug)
2233                         dev_info(&dc->ndev->dev,
2234                         "Read data[%d]: 0x%x\n", i, val);
2235                 memcpy(read_fifo, &val, 4);
2236                 read_fifo += 4;
2237         }
2238
2239         /* Make sure all the data is read from the FIFO */
2240         val = tegra_dsi_readl(dsi, DSI_STATUS);
2241         val &= DSI_STATUS_RD_FIFO_COUNT(0x1f);
2242         if (val)
2243                 dev_err(&dc->ndev->dev, "DSI FIFO_RD_CNT not zero"
2244                 " even after reading FIFO_RD_CNT words from read fifo\n");
2245
2246         if (enable_read_debug) {
2247                 err =
2248                 tegra_dsi_parse_read_response(dc, rd_fifo_cnt, read_fifo_cp);
2249                 if (err < 0)
2250                         dev_warn(&dc->ndev->dev, "Unexpected read data\n");
2251         }
2252 fail:
2253         return err;
2254 }
2255
2256 int tegra_dsi_read_data(struct tegra_dc *dc,
2257                                 struct tegra_dc_dsi_data *dsi,
2258                                 u32 max_ret_payload_size,
2259                                 u32 panel_reg_addr, u8 *read_data)
2260 {
2261         int err = 0;
2262         struct dsi_status *init_status;
2263
2264         tegra_dc_io_start(dc);
2265
2266         init_status = tegra_dsi_prepare_host_transmission(
2267                                 dc, dsi, DSI_LP_OP_WRITE);
2268         if (IS_ERR_OR_NULL(init_status)) {
2269                 err = PTR_ERR(init_status);
2270                 dev_err(&dc->ndev->dev, "DSI host config failed\n");
2271                 goto fail;
2272         }
2273
2274         /* Set max return payload size in words */
2275         err = _tegra_dsi_write_data(dsi, NULL,
2276                 dsi_command_max_return_pkt_size,
2277                 max_ret_payload_size);
2278         if (err < 0) {
2279                 dev_err(&dc->ndev->dev,
2280                                 "DSI write failed\n");
2281                 goto fail;
2282         }
2283
2284         /* DCS to read given panel register */
2285         err = _tegra_dsi_write_data(dsi, NULL,
2286                 dsi_command_dcs_read_with_no_params,
2287                 panel_reg_addr);
2288         if (err < 0) {
2289                 dev_err(&dc->ndev->dev,
2290                                 "DSI write failed\n");
2291                 goto fail;
2292         }
2293
2294         tegra_dsi_reset_read_count(dsi);
2295
2296         if (dsi->status.lp_op == DSI_LP_OP_WRITE) {
2297                 err = tegra_dsi_set_to_lp_mode(dc, dsi, DSI_LP_OP_READ);
2298                 if (err < 0) {
2299                         dev_err(&dc->ndev->dev,
2300                         "DSI failed to go to LP read mode\n");
2301                         goto fail;
2302                 }
2303         }
2304
2305         err = tegra_dsi_bta(dsi);
2306         if (err < 0) {
2307                 dev_err(&dc->ndev->dev,
2308                         "DSI IMM BTA timeout\n");
2309                 goto fail;
2310         }
2311
2312         err = tegra_dsi_read_fifo(dc, dsi, read_data);
2313         if (err < 0) {
2314                 dev_err(&dc->ndev->dev, "DSI read fifo failure\n");
2315                 goto fail;
2316         }
2317 fail:
2318         err = tegra_dsi_restore_state(dc, dsi, init_status);
2319         if (err < 0)
2320                 dev_err(&dc->ndev->dev, "Failed to restore prev state\n");
2321         tegra_dc_io_end(dc);
2322         return err;
2323 }
2324 EXPORT_SYMBOL(tegra_dsi_read_data);
2325
2326 int tegra_dsi_panel_sanity_check(struct tegra_dc *dc,
2327                                 struct tegra_dc_dsi_data *dsi)
2328 {
2329         int err = 0;
2330         u8 read_fifo[DSI_READ_FIFO_DEPTH];
2331         struct dsi_status *init_status;
2332         static struct tegra_dsi_cmd dsi_nop_cmd =
2333                         DSI_CMD_SHORT(0x05, 0x0, 0x0);
2334
2335         tegra_dc_io_start(dc);
2336
2337         init_status = tegra_dsi_prepare_host_transmission(
2338                                         dc, dsi, DSI_LP_OP_WRITE);
2339         if (IS_ERR_OR_NULL(init_status)) {
2340                 err = PTR_ERR(init_status);
2341                 dev_err(&dc->ndev->dev, "DSI host config failed\n");
2342                 goto fail;
2343         }
2344
2345         err = _tegra_dsi_write_data(dsi, NULL, dsi_nop_cmd.data_id, 0x0);
2346         if (err < 0) {
2347                 dev_err(&dc->ndev->dev, "DSI nop write failed\n");
2348                 goto fail;
2349         }
2350
2351         tegra_dsi_reset_read_count(dsi);
2352
2353         if (dsi->status.lp_op == DSI_LP_OP_WRITE) {
2354                 err = tegra_dsi_set_to_lp_mode(dc, dsi, DSI_LP_OP_READ);
2355                 if (err < 0) {
2356                         dev_err(&dc->ndev->dev,
2357                         "DSI failed to go to LP read mode\n");
2358                         goto fail;
2359                 }
2360         }
2361
2362         err = tegra_dsi_bta(dsi);
2363         if (err < 0) {
2364                 dev_err(&dc->ndev->dev, "DSI BTA failed\n");
2365                 goto fail;
2366         }
2367
2368         err = tegra_dsi_read_fifo(dc, dsi, read_fifo);
2369         if (err < 0) {
2370                 dev_err(&dc->ndev->dev, "DSI read fifo failure\n");
2371                 goto fail;
2372         }
2373
2374         if (read_fifo[0] != DSI_ACK_NO_ERR) {
2375                 dev_warn(&dc->ndev->dev,
2376                         "Ack no error trigger message not received\n");
2377                 err = -EAGAIN;
2378         }
2379 fail:
2380         err = tegra_dsi_restore_state(dc, dsi, init_status);
2381         if (err < 0)
2382                 dev_err(&dc->ndev->dev, "Failed to restore prev state\n");
2383         tegra_dc_io_end(dc);
2384         return err;
2385 }
2386 EXPORT_SYMBOL(tegra_dsi_panel_sanity_check);
2387
2388 static int tegra_dsi_enter_ulpm(struct tegra_dc_dsi_data *dsi)
2389 {
2390         u32 val;
2391         int ret;
2392
2393         ret = 0;
2394
2395         val = tegra_dsi_readl(dsi, DSI_HOST_DSI_CONTROL);
2396         val &= ~DSI_HOST_DSI_CONTROL_ULTRA_LOW_POWER(3);
2397         val |= DSI_HOST_DSI_CONTROL_ULTRA_LOW_POWER(ENTER_ULPM);
2398         tegra_dsi_writel(dsi, val, DSI_HOST_DSI_CONTROL);
2399
2400 #if DSI_USE_SYNC_POINTS
2401         ret = tegra_dsi_syncpt(dsi);
2402         if (ret < 0) {
2403                 dev_err(&dsi->dc->ndev->dev,
2404                         "DSI syncpt for ulpm enter failed\n");
2405                 goto fail;
2406         }
2407 #else
2408         /* TODO: Find exact delay required */
2409         mdelay(10);
2410 #endif
2411         dsi->ulpm = true;
2412 fail:
2413         return ret;
2414 }
2415
2416 static int tegra_dsi_exit_ulpm(struct tegra_dc_dsi_data *dsi)
2417 {
2418         u32 val;
2419         int ret;
2420
2421         ret = 0;
2422
2423         val = tegra_dsi_readl(dsi, DSI_HOST_DSI_CONTROL);
2424         val &= ~DSI_HOST_DSI_CONTROL_ULTRA_LOW_POWER(3);
2425         val |= DSI_HOST_DSI_CONTROL_ULTRA_LOW_POWER(EXIT_ULPM);
2426         tegra_dsi_writel(dsi, val, DSI_HOST_DSI_CONTROL);
2427
2428 #if DSI_USE_SYNC_POINTS
2429         ret = tegra_dsi_syncpt(dsi);
2430         if (ret < 0) {
2431                 dev_err(&dsi->dc->ndev->dev,
2432                         "DSI syncpt for ulpm exit failed\n");
2433                 goto fail;
2434         }
2435 #else
2436         /* TODO: Find exact delay required */
2437         mdelay(10);
2438 #endif
2439         dsi->ulpm = false;
2440
2441         val = tegra_dsi_readl(dsi, DSI_HOST_DSI_CONTROL);
2442         val &= ~DSI_HOST_DSI_CONTROL_ULTRA_LOW_POWER(0x3);
2443         val |= DSI_HOST_DSI_CONTROL_ULTRA_LOW_POWER(NORMAL);
2444         tegra_dsi_writel(dsi, val, DSI_HOST_DSI_CONTROL);
2445 fail:
2446         return ret;
2447
2448 }
2449
2450 static void tegra_dc_dsi_enable(struct tegra_dc *dc)
2451 {
2452         struct tegra_dc_dsi_data *dsi = tegra_dc_get_outdata(dc);
2453         int err;
2454         u32 val;
2455
2456         tegra_dc_io_start(dc);
2457         mutex_lock(&dsi->lock);
2458
2459         /* Stop DC stream before configuring DSI registers
2460          * to avoid visible glitches on panel during transition
2461          * from bootloader to kernel driver
2462          */
2463         tegra_dsi_stop_dc_stream(dc, dsi);
2464
2465         if (dsi->enabled) {
2466                 if (dsi->ulpm) {
2467                         if (tegra_dsi_exit_ulpm(dsi) < 0) {
2468                                 dev_err(&dc->ndev->dev,
2469                                         "DSI failed to exit ulpm\n");
2470                                 goto fail;
2471                         }
2472                 }
2473
2474                 if (dsi->info.panel_reset) {
2475                         err = tegra_dsi_send_panel_cmd(dc, dsi,
2476                                                         dsi->info.dsi_init_cmd,
2477                                                         dsi->info.n_init_cmd);
2478                         if (err < 0) {
2479                                 dev_err(&dc->ndev->dev,
2480                                 "dsi: error sending dsi init cmd\n");
2481                                 goto fail;
2482                         }
2483                 } else if (dsi->info.dsi_late_resume_cmd) {
2484                         err = tegra_dsi_send_panel_cmd(dc, dsi,
2485                                                 dsi->info.dsi_late_resume_cmd,
2486                                                 dsi->info.n_late_resume_cmd);
2487                         if (err < 0) {
2488                                 dev_err(&dc->ndev->dev,
2489                                 "dsi: error sending late resume cmd\n");
2490                                 goto fail;
2491                         }
2492                 }
2493         } else {
2494                 err = tegra_dsi_init_hw(dc, dsi);
2495                 if (err < 0) {
2496                         dev_err(&dc->ndev->dev,
2497                                 "dsi: not able to init dsi hardware\n");
2498                         goto fail;
2499                 }
2500
2501                 if (dsi->ulpm) {
2502                         if (tegra_dsi_enter_ulpm(dsi) < 0) {
2503                                 dev_err(&dc->ndev->dev,
2504                                         "DSI failed to enter ulpm\n");
2505                                 goto fail;
2506                         }
2507
2508                         val = tegra_dsi_readl(dsi, DSI_PAD_CONTROL);
2509
2510                         /* erase bits we're about to set */
2511                         val &= ~(DSI_PAD_CONTROL_PAD_PDIO(0x3) |
2512                                 DSI_PAD_CONTROL_PAD_PDIO_CLK(0x1) |
2513                                 DSI_PAD_CONTROL_PAD_PULLDN_ENAB(0x1));
2514
2515                         val |= (DSI_PAD_CONTROL_PAD_PDIO(0) |
2516                                 DSI_PAD_CONTROL_PAD_PDIO_CLK(0) |
2517                                 DSI_PAD_CONTROL_PAD_PULLDN_ENAB
2518                                                 (TEGRA_DSI_DISABLE));
2519
2520                         tegra_dsi_writel(dsi, val, DSI_PAD_CONTROL);
2521                         if (tegra_dsi_exit_ulpm(dsi) < 0) {
2522                                 dev_err(&dc->ndev->dev,
2523                                         "DSI failed to exit ulpm\n");
2524                                 goto fail;
2525                         }
2526                 }
2527
2528                 err = tegra_dsi_set_to_lp_mode(dc, dsi, DSI_LP_OP_WRITE);
2529                 if (err < 0) {
2530                         dev_err(&dc->ndev->dev,
2531                                 "dsi: not able to set to lp mode\n");
2532                         goto fail;
2533                 }
2534
2535                 err = tegra_dsi_send_panel_cmd(dc, dsi, dsi->info.dsi_init_cmd,
2536                                                 dsi->info.n_init_cmd);
2537                 if (err < 0) {
2538                         dev_err(&dc->ndev->dev,
2539                                 "dsi: error while sending dsi init cmd\n");
2540                         goto fail;
2541                 }
2542
2543                 err = tegra_dsi_set_to_hs_mode(dc, dsi);
2544                 if (err < 0) {
2545                         dev_err(&dc->ndev->dev,
2546                                 "dsi: not able to set to hs mode\n");
2547                         goto fail;
2548                 }
2549
2550                 dsi->enabled = true;
2551         }
2552
2553         if (dsi->status.driven == DSI_DRIVEN_MODE_DC)
2554                 tegra_dsi_start_dc_stream(dc, dsi);
2555 fail:
2556         mutex_unlock(&dsi->lock);
2557         tegra_dc_io_end(dc);
2558 }
2559
2560 static void _tegra_dc_dsi_init(struct tegra_dc *dc)
2561 {
2562         struct tegra_dc_dsi_data *dsi = tegra_dc_get_outdata(dc);
2563
2564         tegra_dsi_init_sw(dc, dsi);
2565         /* TODO: Configure the CSI pad configuration */
2566 }
2567
2568 static int tegra_dc_dsi_cp_p_cmd(struct tegra_dsi_cmd *src,
2569                                         struct tegra_dsi_cmd *dst, u16 n_cmd)
2570 {
2571         u16 i;
2572         u16 len;
2573
2574         memcpy(dst, src, sizeof(*dst) * n_cmd);
2575
2576         for (i = 0; i < n_cmd; i++)
2577                 if (src[i].pdata) {
2578                         len = sizeof(*src[i].pdata) *
2579                                         src[i].sp_len_dly.data_len;
2580                         dst[i].pdata = kzalloc(len, GFP_KERNEL);
2581                         if (!dst[i].pdata)
2582                                 goto free_cmd_pdata;
2583                         memcpy(dst[i].pdata, src[i].pdata, len);
2584                 }
2585
2586         return 0;
2587
2588 free_cmd_pdata:
2589         for (--i; i >= 0; i--)
2590                 if (dst[i].pdata)
2591                         kfree(dst[i].pdata);
2592         return -ENOMEM;
2593 }
2594
2595 static int tegra_dc_dsi_cp_info(struct tegra_dc_dsi_data *dsi,
2596                                         struct tegra_dsi_out *p_dsi)
2597 {
2598         struct tegra_dsi_cmd *p_init_cmd;
2599         struct tegra_dsi_cmd *p_early_suspend_cmd;
2600         struct tegra_dsi_cmd *p_late_resume_cmd;
2601         struct tegra_dsi_cmd *p_suspend_cmd;
2602         int err;
2603
2604         if (p_dsi->n_data_lanes > MAX_DSI_DATA_LANES)
2605                 return -EINVAL;
2606
2607         p_init_cmd = kzalloc(sizeof(*p_init_cmd) *
2608                                 p_dsi->n_init_cmd, GFP_KERNEL);
2609         if (!p_init_cmd)
2610                 return -ENOMEM;
2611
2612         if (p_dsi->dsi_early_suspend_cmd) {
2613                 p_early_suspend_cmd = kzalloc(sizeof(*p_early_suspend_cmd) *
2614                                         p_dsi->n_early_suspend_cmd,
2615                                         GFP_KERNEL);
2616                 if (!p_early_suspend_cmd) {
2617                         err = -ENOMEM;
2618                         goto err_free_init_cmd;
2619                 }
2620         }
2621
2622         if (p_dsi->dsi_late_resume_cmd) {
2623                 p_late_resume_cmd = kzalloc(sizeof(*p_late_resume_cmd) *
2624                                         p_dsi->n_late_resume_cmd,
2625                                         GFP_KERNEL);
2626                 if (!p_late_resume_cmd) {
2627                         err = -ENOMEM;
2628                         goto err_free_p_early_suspend_cmd;
2629                 }
2630         }
2631
2632         p_suspend_cmd = kzalloc(sizeof(*p_suspend_cmd) * p_dsi->n_suspend_cmd,
2633                                 GFP_KERNEL);
2634         if (!p_suspend_cmd) {
2635                 err = -ENOMEM;
2636                 goto err_free_p_late_resume_cmd;
2637         }
2638
2639         memcpy(&dsi->info, p_dsi, sizeof(dsi->info));
2640
2641         /* Copy panel init cmd */
2642         err = tegra_dc_dsi_cp_p_cmd(p_dsi->dsi_init_cmd,
2643                                                 p_init_cmd, p_dsi->n_init_cmd);
2644         if (err < 0)
2645                 goto err_free;
2646         dsi->info.dsi_init_cmd = p_init_cmd;
2647
2648         /* Copy panel early suspend cmd */
2649         if (p_dsi->dsi_early_suspend_cmd) {
2650                 err = tegra_dc_dsi_cp_p_cmd(p_dsi->dsi_early_suspend_cmd,
2651                                         p_early_suspend_cmd,
2652                                         p_dsi->n_early_suspend_cmd);
2653                 if (err < 0)
2654                         goto err_free;
2655                 dsi->info.dsi_early_suspend_cmd = p_early_suspend_cmd;
2656         }
2657
2658         /* Copy panel late resume cmd */
2659         if (p_dsi->dsi_late_resume_cmd) {
2660                 err = tegra_dc_dsi_cp_p_cmd(p_dsi->dsi_late_resume_cmd,
2661                                                 p_late_resume_cmd,
2662                                                 p_dsi->n_late_resume_cmd);
2663                 if (err < 0)
2664                         goto err_free;
2665                 dsi->info.dsi_late_resume_cmd = p_late_resume_cmd;
2666         }
2667
2668         /* Copy panel suspend cmd */
2669         err = tegra_dc_dsi_cp_p_cmd(p_dsi->dsi_suspend_cmd, p_suspend_cmd,
2670                                         p_dsi->n_suspend_cmd);
2671         if (err < 0)
2672                 goto err_free;
2673         dsi->info.dsi_suspend_cmd = p_suspend_cmd;
2674
2675         if (!dsi->info.panel_reset_timeout_msec)
2676                 dsi->info.panel_reset_timeout_msec =
2677                                                 DEFAULT_PANEL_RESET_TIMEOUT;
2678
2679         if (!dsi->info.panel_buffer_size_byte)
2680                 dsi->info.panel_buffer_size_byte = DEFAULT_PANEL_BUFFER_BYTE;
2681
2682         if (!dsi->info.max_panel_freq_khz) {
2683                 dsi->info.max_panel_freq_khz = DEFAULT_MAX_DSI_PHY_CLK_KHZ;
2684
2685                 if (dsi->info.video_burst_mode >
2686                                 TEGRA_DSI_VIDEO_NONE_BURST_MODE_WITH_SYNC_END){
2687                         dev_err(&dsi->dc->ndev->dev, "DSI: max_panel_freq_khz"
2688                                         "is not set for DSI burst mode.\n");
2689                         dsi->info.video_burst_mode =
2690                                 TEGRA_DSI_VIDEO_BURST_MODE_LOWEST_SPEED;
2691                 }
2692         }
2693
2694         if (!dsi->info.lp_cmd_mode_freq_khz)
2695                 dsi->info.lp_cmd_mode_freq_khz = DEFAULT_LP_CMD_MODE_CLK_KHZ;
2696
2697         if (!dsi->info.chip_id || !dsi->info.chip_rev)
2698                 dev_warn(&dsi->dc->ndev->dev,
2699                         "DSI: Failed to get chip info\n");
2700
2701         if (!dsi->info.lp_read_cmd_mode_freq_khz)
2702                 dsi->info.lp_read_cmd_mode_freq_khz =
2703                         dsi->info.lp_cmd_mode_freq_khz;
2704
2705         /* host mode is for testing only */
2706         dsi->driven_mode = TEGRA_DSI_DRIVEN_BY_DC;
2707         return 0;
2708
2709 err_free:
2710         kfree(p_suspend_cmd);
2711 err_free_p_late_resume_cmd:
2712         kfree(p_late_resume_cmd);
2713 err_free_p_early_suspend_cmd:
2714         kfree(p_early_suspend_cmd);
2715 err_free_init_cmd:
2716         kfree(p_init_cmd);
2717         return err;
2718 }
2719
2720 static int tegra_dc_dsi_init(struct tegra_dc *dc)
2721 {
2722         struct tegra_dc_dsi_data *dsi;
2723         struct resource *res;
2724         struct resource *base_res;
2725         void __iomem *base;
2726         struct clk *dc_clk = NULL;
2727         struct clk *dsi_clk = NULL;
2728         struct tegra_dsi_out *dsi_pdata;
2729         int err;
2730
2731         err = 0;
2732
2733         dsi = kzalloc(sizeof(*dsi), GFP_KERNEL);
2734         if (!dsi)
2735                 return -ENOMEM;
2736
2737         res = nvhost_get_resource_byname(dc->ndev, IORESOURCE_MEM,
2738                                         "dsi_regs");
2739         if (!res) {
2740                 dev_err(&dc->ndev->dev, "dsi: no mem resource\n");
2741                 err = -ENOENT;
2742                 goto err_free_dsi;
2743         }
2744
2745         base_res = request_mem_region(res->start, resource_size(res),
2746                                 dc->ndev->name);
2747         if (!base_res) {
2748                 dev_err(&dc->ndev->dev, "dsi: request_mem_region failed\n");
2749                 err = -EBUSY;
2750                 goto err_free_dsi;
2751         }
2752
2753         base = ioremap(res->start, resource_size(res));
2754         if (!base) {
2755                 dev_err(&dc->ndev->dev, "dsi: registers can't be mapped\n");
2756                 err = -EBUSY;
2757                 goto err_release_regs;
2758         }
2759
2760         dsi_pdata = dc->pdata->default_out->dsi;
2761         if (!dsi_pdata) {
2762                 dev_err(&dc->ndev->dev, "dsi: dsi data not available\n");
2763                 goto err_release_regs;
2764         }
2765
2766         if (dsi_pdata->dsi_instance)
2767                 dsi_clk = clk_get(&dc->ndev->dev, "dsib");
2768         else
2769                 dsi_clk = clk_get(&dc->ndev->dev, "dsia");
2770
2771         if (IS_ERR_OR_NULL(dsi_clk)) {
2772                 dev_err(&dc->ndev->dev, "dsi: can't get clock\n");
2773                 err = -EBUSY;
2774                 goto err_release_regs;
2775         }
2776
2777         dc_clk = clk_get_sys(dev_name(&dc->ndev->dev), NULL);
2778         if (IS_ERR_OR_NULL(dc_clk)) {
2779                 dev_err(&dc->ndev->dev, "dsi: dc clock %s unavailable\n",
2780                         dev_name(&dc->ndev->dev));
2781                 err = -EBUSY;
2782                 goto err_clk_put;
2783         }
2784
2785         mutex_init(&dsi->lock);
2786         dsi->dc = dc;
2787         dsi->base = base;
2788         dsi->base_res = base_res;
2789         dsi->dc_clk = dc_clk;
2790         dsi->dsi_clk = dsi_clk;
2791
2792         err = tegra_dc_dsi_cp_info(dsi, dsi_pdata);
2793         if (err < 0)
2794                 goto err_dsi_data;
2795
2796         tegra_dc_set_outdata(dc, dsi);
2797         _tegra_dc_dsi_init(dc);
2798
2799         return 0;
2800
2801 err_dsi_data:
2802 err_clk_put:
2803         clk_put(dsi_clk);
2804 err_release_regs:
2805         release_resource(base_res);
2806 err_free_dsi:
2807         kfree(dsi);
2808
2809         return err;
2810 }
2811
2812 static void tegra_dc_dsi_destroy(struct tegra_dc *dc)
2813 {
2814         struct tegra_dc_dsi_data *dsi = tegra_dc_get_outdata(dc);
2815         u16 i;
2816         u32 val;
2817
2818         mutex_lock(&dsi->lock);
2819
2820         /* free up the pdata */
2821         for (i = 0; i < dsi->info.n_init_cmd; i++) {
2822                 if (dsi->info.dsi_init_cmd[i].pdata)
2823                         kfree(dsi->info.dsi_init_cmd[i].pdata);
2824         }
2825         kfree(dsi->info.dsi_init_cmd);
2826
2827         /* Disable dc stream */
2828         if (dsi->status.dc_stream == DSI_DC_STREAM_ENABLE)
2829                 tegra_dsi_stop_dc_stream_at_frame_end(dc, dsi);
2830
2831         /* Disable dsi phy clock */
2832         if (dsi->status.clk_out == DSI_PHYCLK_OUT_EN)
2833                 tegra_dsi_hs_clk_out_disable(dc, dsi);
2834
2835         val = DSI_POWER_CONTROL_LEG_DSI_ENABLE(TEGRA_DSI_DISABLE);
2836         tegra_dsi_writel(dsi, val, DSI_POWER_CONTROL);
2837
2838         iounmap(dsi->base);
2839         release_resource(dsi->base_res);
2840
2841         clk_put(dsi->dc_clk);
2842         clk_put(dsi->dsi_clk);
2843
2844         mutex_unlock(&dsi->lock);
2845
2846         mutex_destroy(&dsi->lock);
2847         kfree(dsi);
2848 }
2849
2850 static int tegra_dsi_deep_sleep(struct tegra_dc *dc,
2851                                 struct tegra_dc_dsi_data *dsi)
2852 {
2853         int err = 0;
2854         int val;
2855         struct clk *parent_clk = NULL;
2856         struct clk *base_clk = NULL;
2857
2858         if (!dsi->enabled) {
2859                 err = -EPERM;
2860                 goto fail;
2861         }
2862
2863         err = tegra_dsi_set_to_lp_mode(dc, dsi, DSI_LP_OP_WRITE);
2864         if (err < 0) {
2865                 dev_err(&dc->ndev->dev,
2866                 "DSI failed to go to LP mode\n");
2867                 goto fail;
2868         }
2869
2870         /* Suspend panel */
2871         err = tegra_dsi_send_panel_cmd(dc, dsi,
2872                         dsi->info.dsi_suspend_cmd,
2873                         dsi->info.n_suspend_cmd);
2874         if (err < 0) {
2875                 dev_err(&dc->ndev->dev,
2876                         "dsi: Error sending suspend cmd\n");
2877                 goto fail;
2878         }
2879
2880         if (!dsi->ulpm) {
2881                 err = tegra_dsi_enter_ulpm(dsi);
2882                 if (err < 0) {
2883                         dev_err(&dc->ndev->dev,
2884                                 "DSI failed to enter ulpm\n");
2885                         goto fail;
2886                 }
2887         }
2888
2889         /*
2890          * Suspend pad
2891          * It is ok to overwrite previous value of DSI_PAD_CONTROL reg
2892          * because it will be restored properly in resume sequence
2893          */
2894         val = DSI_PAD_CONTROL_PAD_PDIO(0x3) |
2895                 DSI_PAD_CONTROL_PAD_PDIO_CLK(0x1) |
2896                 DSI_PAD_CONTROL_PAD_PULLDN_ENAB(TEGRA_DSI_ENABLE);
2897         tegra_dsi_writel(dsi, val, DSI_PAD_CONTROL);
2898
2899         /* Suspend core-logic */
2900         val = DSI_POWER_CONTROL_LEG_DSI_ENABLE(TEGRA_DSI_DISABLE);
2901         tegra_dsi_writel(dsi, val, DSI_POWER_CONTROL);
2902
2903         /* Disable dsi fast and slow clock */
2904         parent_clk = clk_get_parent(dsi->dsi_clk);
2905         base_clk = clk_get_parent(parent_clk);
2906         if (dsi->info.dsi_instance)
2907                 tegra_clk_cfg_ex(base_clk,
2908                                 TEGRA_CLK_PLLD_CSI_OUT_ENB,
2909                                 0);
2910         else
2911                 tegra_clk_cfg_ex(base_clk,
2912                                 TEGRA_CLK_PLLD_DSI_OUT_ENB,
2913                                 0);
2914
2915         /* Disable dsi source clock */
2916         clk_disable(dsi->dsi_clk);
2917
2918         dsi->clk_ref = false;
2919         dsi->enabled = false;
2920
2921         return 0;
2922 fail:
2923         return err;
2924 }
2925
2926 static void tegra_dc_dsi_disable(struct tegra_dc *dc)
2927 {
2928         int err;
2929         struct tegra_dc_dsi_data *dsi = tegra_dc_get_outdata(dc);
2930
2931         tegra_dc_io_start(dc);
2932         mutex_lock(&dsi->lock);
2933
2934         if (dsi->status.dc_stream == DSI_DC_STREAM_ENABLE)
2935                 tegra_dsi_stop_dc_stream_at_frame_end(dc, dsi);
2936
2937         if (dsi->info.power_saving_suspend) {
2938                 if (tegra_dsi_deep_sleep(dc, dsi) < 0) {
2939                         dev_err(&dc->ndev->dev,
2940                                 "DSI failed to enter deep sleep\n");
2941                         goto fail;
2942                 }
2943         } else {
2944                 if (dsi->info.dsi_early_suspend_cmd) {
2945                         err = tegra_dsi_send_panel_cmd(dc, dsi,
2946                                 dsi->info.dsi_early_suspend_cmd,
2947                                 dsi->info.n_early_suspend_cmd);
2948                         if (err < 0) {
2949                                 dev_err(&dc->ndev->dev,
2950                                 "dsi: Error sending early suspend cmd\n");
2951                                 goto fail;
2952                         }
2953                 }
2954
2955                 if (!dsi->ulpm) {
2956                         if (tegra_dsi_enter_ulpm(dsi) < 0) {
2957                                 dev_err(&dc->ndev->dev,
2958                                         "DSI failed to enter ulpm\n");
2959                                 goto fail;
2960                         }
2961                 }
2962         }
2963
2964 fail:
2965         mutex_unlock(&dsi->lock);
2966         tegra_dc_io_end(dc);
2967 }
2968
2969 #ifdef CONFIG_PM
2970 static void tegra_dc_dsi_suspend(struct tegra_dc *dc)
2971 {
2972         struct tegra_dc_dsi_data *dsi;
2973
2974         dsi = tegra_dc_get_outdata(dc);
2975
2976         if (!dsi->enabled)
2977                 return;
2978
2979         tegra_dc_io_start(dc);
2980         mutex_lock(&dsi->lock);
2981
2982         if (!dsi->info.power_saving_suspend) {
2983                 if (dsi->ulpm) {
2984                         if (tegra_dsi_exit_ulpm(dsi) < 0) {
2985                                 dev_err(&dc->ndev->dev,
2986                                         "DSI failed to exit ulpm");
2987                                 goto fail;
2988                         }
2989                 }
2990
2991                 if (tegra_dsi_deep_sleep(dc, dsi) < 0) {
2992                         dev_err(&dc->ndev->dev,
2993                                 "DSI failed to enter deep sleep\n");
2994                         goto fail;
2995                 }
2996         }
2997 fail:
2998         mutex_unlock(&dsi->lock);
2999         tegra_dc_io_end(dc);
3000 }
3001
3002 static void tegra_dc_dsi_resume(struct tegra_dc *dc)
3003 {
3004         /* Not required since tegra_dc_dsi_enable
3005          * will reconfigure the controller from scratch
3006          */
3007 }
3008 #endif
3009
3010 struct tegra_dc_out_ops tegra_dc_dsi_ops = {
3011         .init = tegra_dc_dsi_init,
3012         .destroy = tegra_dc_dsi_destroy,
3013         .enable = tegra_dc_dsi_enable,
3014         .disable = tegra_dc_dsi_disable,
3015 #ifdef CONFIG_PM
3016         .suspend = tegra_dc_dsi_suspend,
3017         .resume = tegra_dc_dsi_resume,
3018 #endif
3019 };