video: tegra: dc: Ignore suspend if DSI is disabled
[linux-2.6.git] / drivers / video / tegra / dc / dsi.c
1 /*
2  * drivers/video/tegra/dc/dsi.c
3  *
4  * Copyright (c) 2011, NVIDIA Corporation.
5  *
6  * This software is licensed under the terms of the GNU General Public
7  * License version 2, as published by the Free Software Foundation, and
8  * may be copied, distributed, and modified under those terms.
9  *
10  * This program is distributed in the hope that it will be useful,
11  * but WITHOUT ANY WARRANTY; without even the implied warranty of
12  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
13  * GNU General Public License for more details.
14  *
15  */
16
17 #include <linux/clk.h>
18 #include <linux/delay.h>
19 #include <linux/err.h>
20 #include <linux/fb.h>
21 #include <linux/gpio.h>
22 #include <linux/interrupt.h>
23 #include <linux/kernel.h>
24 #include <linux/slab.h>
25 #include <linux/spinlock.h>
26 #include <linux/workqueue.h>
27
28 #include <mach/clk.h>
29 #include <mach/dc.h>
30 #include <mach/fb.h>
31 #include <mach/csi.h>
32 #include <linux/nvhost.h>
33
34 #include "dc_reg.h"
35 #include "dc_priv.h"
36 #include "dsi_regs.h"
37 #include "dsi.h"
38
39 #define DSI_USE_SYNC_POINTS             1
40 #define S_TO_MS(x)                      (1000 * (x))
41
42 #define DSI_MODULE_NOT_INIT             0x0
43 #define DSI_MODULE_INIT                 0x1
44
45 #define DSI_LPHS_NOT_INIT               0x0
46 #define DSI_LPHS_IN_LP_MODE             0x1
47 #define DSI_LPHS_IN_HS_MODE             0x2
48
49 #define DSI_VIDEO_TYPE_NOT_INIT         0x0
50 #define DSI_VIDEO_TYPE_VIDEO_MODE       0x1
51 #define DSI_VIDEO_TYPE_CMD_MODE         0x2
52
53 #define DSI_DRIVEN_MODE_NOT_INIT        0x0
54 #define DSI_DRIVEN_MODE_DC              0x1
55 #define DSI_DRIVEN_MODE_HOST            0x2
56
57 #define DSI_PHYCLK_OUT_DIS              0x0
58 #define DSI_PHYCLK_OUT_EN               0x1
59
60 #define DSI_PHYCLK_NOT_INIT             0x0
61 #define DSI_PHYCLK_CONTINUOUS           0x1
62 #define DSI_PHYCLK_TX_ONLY              0x2
63
64 #define DSI_CLK_BURST_NOT_INIT          0x0
65 #define DSI_CLK_BURST_NONE_BURST        0x1
66 #define DSI_CLK_BURST_BURST_MODE        0x2
67
68 #define DSI_DC_STREAM_DISABLE           0x0
69 #define DSI_DC_STREAM_ENABLE            0x1
70
71 #define DSI_LP_OP_NOT_INIT              0x0
72 #define DSI_LP_OP_WRITE                 0x1
73 #define DSI_LP_OP_READ                  0x2
74
75 static bool enable_read_debug;
76 module_param(enable_read_debug, bool, 0644);
77 MODULE_PARM_DESC(enable_read_debug,
78                 "Enable to print read fifo and return packet type");
79
80 struct dsi_status {
81         unsigned init:2;
82
83         unsigned lphs:2;
84
85         unsigned vtype:2;
86         unsigned driven:2;
87
88         unsigned clk_out:2;
89         unsigned clk_mode:2;
90         unsigned clk_burst:2;
91
92         unsigned lp_op:2;
93
94         unsigned dc_stream:1;
95 };
96
97 /* source of video data */
98 enum {
99         TEGRA_DSI_DRIVEN_BY_DC,
100         TEGRA_DSI_DRIVEN_BY_HOST,
101 };
102
103 struct tegra_dc_dsi_data {
104         struct tegra_dc *dc;
105         void __iomem *base;
106         struct resource *base_res;
107
108         struct clk *dc_clk;
109         struct clk *dsi_clk;
110         bool clk_ref;
111
112         struct mutex lock;
113
114         /* data from board info */
115         struct tegra_dsi_out info;
116
117         struct dsi_status status;
118
119         u8 driven_mode;
120         u8 controller_index;
121
122         u8 pixel_scaler_mul;
123         u8 pixel_scaler_div;
124
125         u32 default_shift_clk_div;
126         u32 default_pixel_clk_khz;
127         u32 default_hs_clk_khz;
128
129         u32 shift_clk_div;
130         u32 target_hs_clk_khz;
131         u32 target_lp_clk_khz;
132
133         u32 syncpt_id;
134         u32 syncpt_val;
135
136         u16 current_bit_clk_ns;
137         u32 current_dsi_clk_khz;
138
139         u32 dsi_control_val;
140
141         bool ulpm;
142         bool enabled;
143 };
144
145 const u32 dsi_pkt_seq_reg[NUMOF_PKT_SEQ] = {
146         DSI_PKT_SEQ_0_LO,
147         DSI_PKT_SEQ_0_HI,
148         DSI_PKT_SEQ_1_LO,
149         DSI_PKT_SEQ_1_HI,
150         DSI_PKT_SEQ_2_LO,
151         DSI_PKT_SEQ_2_HI,
152         DSI_PKT_SEQ_3_LO,
153         DSI_PKT_SEQ_3_HI,
154         DSI_PKT_SEQ_4_LO,
155         DSI_PKT_SEQ_4_HI,
156         DSI_PKT_SEQ_5_LO,
157         DSI_PKT_SEQ_5_HI,
158 };
159
160 const u32 dsi_pkt_seq_video_non_burst_syne[NUMOF_PKT_SEQ] = {
161         PKT_ID0(CMD_VS) | PKT_LEN0(0) | PKT_ID1(CMD_EOT) | PKT_LEN1(0) | PKT_LP,
162         0,
163         PKT_ID0(CMD_VE) | PKT_LEN0(0) | PKT_ID1(CMD_EOT) | PKT_LEN1(0) | PKT_LP,
164         0,
165         PKT_ID0(CMD_HS) | PKT_LEN0(0) | PKT_ID1(CMD_EOT) | PKT_LEN1(0) | PKT_LP,
166         0,
167         PKT_ID0(CMD_HS) | PKT_LEN0(0) | PKT_ID1(CMD_BLNK) | PKT_LEN1(1) |
168         PKT_ID2(CMD_HE) | PKT_LEN2(0),
169         PKT_ID3(CMD_BLNK) | PKT_LEN3(2) | PKT_ID4(CMD_RGB) | PKT_LEN4(3) |
170         PKT_ID5(CMD_BLNK) | PKT_LEN5(4),
171         PKT_ID0(CMD_HS) | PKT_LEN0(0) | PKT_ID1(CMD_EOT) | PKT_LEN1(0) | PKT_LP,
172         0,
173         PKT_ID0(CMD_HS) | PKT_LEN0(0) | PKT_ID1(CMD_BLNK) | PKT_LEN1(1) |
174         PKT_ID2(CMD_HE) | PKT_LEN2(0),
175         PKT_ID3(CMD_BLNK) | PKT_LEN3(2) | PKT_ID4(CMD_RGB) | PKT_LEN4(3) |
176         PKT_ID5(CMD_BLNK) | PKT_LEN5(4),
177 };
178
179 const u32 dsi_pkt_seq_video_non_burst[NUMOF_PKT_SEQ] = {
180         PKT_ID0(CMD_VS) | PKT_LEN0(0) | PKT_ID1(CMD_EOT) | PKT_LEN1(0) | PKT_LP,
181         0,
182         PKT_ID0(CMD_HS) | PKT_LEN0(0) | PKT_ID1(CMD_EOT) | PKT_LEN1(0) | PKT_LP,
183         0,
184         PKT_ID0(CMD_HS) | PKT_LEN0(0) | PKT_ID1(CMD_EOT) | PKT_LEN1(0) | PKT_LP,
185         0,
186         PKT_ID0(CMD_HS) | PKT_LEN0(0) | PKT_ID1(CMD_BLNK) | PKT_LEN1(2) |
187         PKT_ID2(CMD_RGB) | PKT_LEN2(3),
188         PKT_ID3(CMD_BLNK) | PKT_LEN3(4),
189         PKT_ID0(CMD_HS) | PKT_LEN0(0) | PKT_ID1(CMD_EOT) | PKT_LEN1(0) | PKT_LP,
190         0,
191         PKT_ID0(CMD_HS) | PKT_LEN0(0) | PKT_ID1(CMD_BLNK) | PKT_LEN1(2) |
192         PKT_ID2(CMD_RGB) | PKT_LEN2(3),
193         PKT_ID3(CMD_BLNK) | PKT_LEN3(4),
194 };
195
196 static const u32 dsi_pkt_seq_video_burst[NUMOF_PKT_SEQ] = {
197         PKT_ID0(CMD_VS) | PKT_LEN0(0) | PKT_ID1(CMD_EOT) | PKT_LEN1(7) | PKT_LP,
198         0,
199         PKT_ID0(CMD_HS) | PKT_LEN0(0) | PKT_ID1(CMD_EOT) | PKT_LEN1(7) | PKT_LP,
200         0,
201         PKT_ID0(CMD_HS) | PKT_LEN0(0) | PKT_ID1(CMD_EOT) | PKT_LEN1(7) | PKT_LP,
202         0,
203         PKT_ID0(CMD_HS) | PKT_LEN0(0) | PKT_ID1(CMD_BLNK) | PKT_LEN1(2)|
204         PKT_ID2(CMD_RGB) | PKT_LEN2(3) | PKT_LP,
205         PKT_ID0(CMD_EOT) | PKT_LEN0(7),
206         PKT_ID0(CMD_HS) | PKT_LEN0(0) | PKT_ID1(CMD_EOT) | PKT_LEN1(7) | PKT_LP,
207         0,
208         PKT_ID0(CMD_HS) | PKT_LEN0(0) | PKT_ID1(CMD_BLNK) | PKT_LEN1(2)|
209         PKT_ID2(CMD_RGB) | PKT_LEN2(3) | PKT_LP,
210         PKT_ID0(CMD_EOT) | PKT_LEN0(7),
211 };
212
213 static const u32 dsi_pkt_seq_video_burst_no_eot[NUMOF_PKT_SEQ] = {
214         PKT_ID0(CMD_VS) | PKT_LEN0(0) | PKT_ID1(CMD_EOT) | PKT_LEN1(0) | PKT_LP,
215         0,
216         PKT_ID0(CMD_HS) | PKT_LEN0(0) | PKT_ID1(CMD_EOT) | PKT_LEN1(0) | PKT_LP,
217         0,
218         PKT_ID0(CMD_HS) | PKT_LEN0(0) | PKT_ID1(CMD_EOT) | PKT_LEN1(0) | PKT_LP,
219         0,
220         PKT_ID0(CMD_HS) | PKT_LEN0(0) | PKT_ID1(CMD_BLNK) | PKT_LEN1(2)|
221         PKT_ID2(CMD_RGB) | PKT_LEN2(3) | PKT_LP,
222         PKT_ID0(CMD_EOT) | PKT_LEN0(0),
223         PKT_ID0(CMD_HS) | PKT_LEN0(0) | PKT_ID1(CMD_EOT) | PKT_LEN1(0) | PKT_LP,
224         0,
225         PKT_ID0(CMD_HS) | PKT_LEN0(0) | PKT_ID1(CMD_BLNK) | PKT_LEN1(2)|
226         PKT_ID2(CMD_RGB) | PKT_LEN2(3) | PKT_LP,
227         PKT_ID0(CMD_EOT) | PKT_LEN0(0),
228 };
229
230 /* TODO: verify with hw about this format */
231 const u32 dsi_pkt_seq_cmd_mode[NUMOF_PKT_SEQ] = {
232         0,
233         0,
234         0,
235         0,
236         0,
237         0,
238         PKT_ID0(CMD_LONGW) | PKT_LEN0(3) | PKT_ID1(CMD_EOT) | PKT_LEN1(7),
239         0,
240         0,
241         0,
242         PKT_ID0(CMD_LONGW) | PKT_LEN0(3) | PKT_ID1(CMD_EOT) | PKT_LEN1(7),
243         0,
244 };
245
246 const u32 init_reg[] = {
247         DSI_INT_ENABLE,
248         DSI_INT_STATUS,
249         DSI_INT_MASK,
250         DSI_INIT_SEQ_DATA_0,
251         DSI_INIT_SEQ_DATA_1,
252         DSI_INIT_SEQ_DATA_2,
253         DSI_INIT_SEQ_DATA_3,
254         DSI_INIT_SEQ_DATA_4,
255         DSI_INIT_SEQ_DATA_5,
256         DSI_INIT_SEQ_DATA_6,
257         DSI_INIT_SEQ_DATA_7,
258         DSI_DCS_CMDS,
259         DSI_PKT_SEQ_0_LO,
260         DSI_PKT_SEQ_1_LO,
261         DSI_PKT_SEQ_2_LO,
262         DSI_PKT_SEQ_3_LO,
263         DSI_PKT_SEQ_4_LO,
264         DSI_PKT_SEQ_5_LO,
265         DSI_PKT_SEQ_0_HI,
266         DSI_PKT_SEQ_1_HI,
267         DSI_PKT_SEQ_2_HI,
268         DSI_PKT_SEQ_3_HI,
269         DSI_PKT_SEQ_4_HI,
270         DSI_PKT_SEQ_5_HI,
271         DSI_CONTROL,
272         DSI_HOST_DSI_CONTROL,
273         DSI_PAD_CONTROL,
274         DSI_PAD_CONTROL_CD,
275         DSI_SOL_DELAY,
276         DSI_MAX_THRESHOLD,
277         DSI_TRIGGER,
278         DSI_TX_CRC,
279         DSI_INIT_SEQ_CONTROL,
280         DSI_PKT_LEN_0_1,
281         DSI_PKT_LEN_2_3,
282         DSI_PKT_LEN_4_5,
283         DSI_PKT_LEN_6_7,
284 };
285
286 inline unsigned long tegra_dsi_readl(struct tegra_dc_dsi_data *dsi, u32 reg)
287 {
288         return readl(dsi->base + reg * 4);
289 }
290 EXPORT_SYMBOL(tegra_dsi_readl);
291
292 inline void tegra_dsi_writel(struct tegra_dc_dsi_data *dsi, u32 val, u32 reg)
293 {
294         writel(val, dsi->base + reg * 4);
295 }
296 EXPORT_SYMBOL(tegra_dsi_writel);
297
298 static int tegra_dsi_syncpt(struct tegra_dc_dsi_data *dsi)
299 {
300         u32 val;
301         int ret;
302
303         ret = 0;
304
305         dsi->syncpt_val = nvhost_syncpt_read(
306                         &nvhost_get_host(dsi->dc->ndev)->syncpt,
307                         dsi->syncpt_id);
308
309         val = DSI_INCR_SYNCPT_COND(OP_DONE) |
310                 DSI_INCR_SYNCPT_INDX(dsi->syncpt_id);
311         tegra_dsi_writel(dsi, val, DSI_INCR_SYNCPT);
312
313         /* TODO: Use interrupt rather than polling */
314         ret = nvhost_syncpt_wait(&nvhost_get_host(dsi->dc->ndev)->syncpt,
315                 dsi->syncpt_id, dsi->syncpt_val + 1);
316         if (ret < 0) {
317                 dev_err(&dsi->dc->ndev->dev, "DSI sync point failure\n");
318                 goto fail;
319         }
320
321         (dsi->syncpt_val)++;
322         return 0;
323 fail:
324         return ret;
325 }
326
327 static u32 tegra_dsi_get_hs_clk_rate(struct tegra_dc_dsi_data *dsi)
328 {
329         u32 dsi_clock_rate_khz;
330
331         switch (dsi->info.video_burst_mode) {
332         case TEGRA_DSI_VIDEO_BURST_MODE_LOW_SPEED:
333         case TEGRA_DSI_VIDEO_BURST_MODE_MEDIUM_SPEED:
334         case TEGRA_DSI_VIDEO_BURST_MODE_FAST_SPEED:
335         case TEGRA_DSI_VIDEO_BURST_MODE_FASTEST_SPEED:
336                 /* Calculate DSI HS clock rate for DSI burst mode */
337                 dsi_clock_rate_khz = dsi->default_pixel_clk_khz *
338                                                         dsi->shift_clk_div;
339                 break;
340         case TEGRA_DSI_VIDEO_NONE_BURST_MODE:
341         case TEGRA_DSI_VIDEO_NONE_BURST_MODE_WITH_SYNC_END:
342         case TEGRA_DSI_VIDEO_BURST_MODE_LOWEST_SPEED:
343         default:
344                 /* Clock rate is default DSI clock rate for non-burst mode */
345                 dsi_clock_rate_khz = dsi->default_hs_clk_khz;
346                 break;
347         }
348
349         return dsi_clock_rate_khz;
350 }
351
352 static u32 tegra_dsi_get_lp_clk_rate(struct tegra_dc_dsi_data *dsi, u8 lp_op)
353 {
354         u32 dsi_clock_rate_khz;
355
356         if (dsi->info.enable_hs_clock_on_lp_cmd_mode)
357                 if (dsi->info.hs_clk_in_lp_cmd_mode_freq_khz)
358                         dsi_clock_rate_khz =
359                                 dsi->info.hs_clk_in_lp_cmd_mode_freq_khz;
360                 else
361                         dsi_clock_rate_khz = tegra_dsi_get_hs_clk_rate(dsi);
362         else
363                 if (lp_op == DSI_LP_OP_READ)
364                         dsi_clock_rate_khz =
365                                 dsi->info.lp_read_cmd_mode_freq_khz;
366                 else
367                         dsi_clock_rate_khz =
368                                 dsi->info.lp_cmd_mode_freq_khz;
369
370         return dsi_clock_rate_khz;
371 }
372
373 static u32 tegra_dsi_get_shift_clk_div(struct tegra_dc_dsi_data *dsi)
374 {
375         u32 shift_clk_div;
376         u32 max_shift_clk_div;
377         u32 burst_width;
378         u32 burst_width_max;
379
380         /* Get the real value of default shift_clk_div. default_shift_clk_div
381          * holds the real value of shift_clk_div.
382          */
383         shift_clk_div = dsi->default_shift_clk_div;
384
385         /* Calculate shift_clk_div which can matche the video_burst_mode. */
386         if (dsi->info.video_burst_mode >=
387                         TEGRA_DSI_VIDEO_BURST_MODE_LOWEST_SPEED) {
388                 /* The max_shift_clk_div is multiplied by 10 to save the
389                  * fraction
390                  */
391                 if (dsi->info.max_panel_freq_khz >= dsi->default_hs_clk_khz)
392                         max_shift_clk_div = dsi->info.max_panel_freq_khz
393                                 * shift_clk_div * 10 / dsi->default_hs_clk_khz;
394                 else
395                         max_shift_clk_div = shift_clk_div * 10;
396
397                 burst_width = dsi->info.video_burst_mode
398                                 - TEGRA_DSI_VIDEO_BURST_MODE_LOWEST_SPEED;
399                 burst_width_max = TEGRA_DSI_VIDEO_BURST_MODE_FASTEST_SPEED
400                                 - TEGRA_DSI_VIDEO_BURST_MODE_LOWEST_SPEED;
401
402                 shift_clk_div = (max_shift_clk_div - shift_clk_div * 10) *
403                         burst_width / (burst_width_max * 10) + shift_clk_div;
404         }
405
406         return shift_clk_div;
407 }
408
409 static void tegra_dsi_init_sw(struct tegra_dc *dc,
410                         struct tegra_dc_dsi_data *dsi)
411 {
412         u32 h_width_pixels;
413         u32 v_width_lines;
414         u32 pixel_clk_hz;
415         u32 byte_clk_hz;
416         u32 plld_clk_mhz;
417
418         switch (dsi->info.pixel_format) {
419         case TEGRA_DSI_PIXEL_FORMAT_16BIT_P:
420                 /* 2 bytes per pixel */
421                 dsi->pixel_scaler_mul = 2;
422                 dsi->pixel_scaler_div = 1;
423                 break;
424         case TEGRA_DSI_PIXEL_FORMAT_18BIT_P:
425                 /* 2.25 bytes per pixel */
426                 dsi->pixel_scaler_mul = 9;
427                 dsi->pixel_scaler_div = 4;
428                 break;
429         case TEGRA_DSI_PIXEL_FORMAT_18BIT_NP:
430         case TEGRA_DSI_PIXEL_FORMAT_24BIT_P:
431                 /* 3 bytes per pixel */
432                 dsi->pixel_scaler_mul = 3;
433                 dsi->pixel_scaler_div = 1;
434                 break;
435         default:
436                 break;
437         }
438
439         dsi->controller_index = dc->ndev->id;
440         dsi->ulpm = false;
441         dsi->enabled = false;
442         dsi->clk_ref = false;
443
444         dsi->dsi_control_val =
445                         DSI_CONTROL_VIRTUAL_CHANNEL(dsi->info.virtual_channel) |
446                         DSI_CONTROL_NUM_DATA_LANES(dsi->info.n_data_lanes - 1) |
447                         DSI_CONTROL_VID_SOURCE(dsi->controller_index) |
448                         DSI_CONTROL_DATA_FORMAT(dsi->info.pixel_format);
449
450         /* Below we are going to calculate dsi and dc clock rate.
451          * Calcuate the horizontal and vertical width.
452          */
453         h_width_pixels = dc->mode.h_back_porch + dc->mode.h_front_porch +
454                         dc->mode.h_sync_width + dc->mode.h_active;
455         v_width_lines = dc->mode.v_back_porch + dc->mode.v_front_porch +
456                         dc->mode.v_sync_width + dc->mode.v_active;
457
458         /* Calculate minimum required pixel rate. */
459         pixel_clk_hz = h_width_pixels * v_width_lines * dsi->info.refresh_rate;
460
461         /* Calculate minimum byte rate on DSI interface. */
462         byte_clk_hz = (pixel_clk_hz * dsi->pixel_scaler_mul) /
463                         (dsi->pixel_scaler_div * dsi->info.n_data_lanes);
464
465         /* Round up to multiple of mega hz. */
466         plld_clk_mhz = DIV_ROUND_UP((byte_clk_hz * NUMOF_BIT_PER_BYTE),
467                                                                 1000000);
468
469         /* Calculate default real shift_clk_div. */
470         dsi->default_shift_clk_div = (NUMOF_BIT_PER_BYTE / 2) *
471                 dsi->pixel_scaler_mul / (dsi->pixel_scaler_div *
472                 dsi->info.n_data_lanes);
473         /* Calculate default DSI hs clock. DSI interface is double data rate.
474          * Data is transferred on both rising and falling edge of clk, div by 2
475          * to get the actual clock rate.
476          */
477         dsi->default_hs_clk_khz = plld_clk_mhz * 1000 / 2;
478         dsi->default_pixel_clk_khz = plld_clk_mhz * 1000 / 2
479                                                 / dsi->default_shift_clk_div;
480
481         /* Get the actual shift_clk_div and clock rates. */
482         dsi->shift_clk_div = tegra_dsi_get_shift_clk_div(dsi);
483         dsi->target_lp_clk_khz =
484                         tegra_dsi_get_lp_clk_rate(dsi, DSI_LP_OP_WRITE);
485         dsi->target_hs_clk_khz = tegra_dsi_get_hs_clk_rate(dsi);
486
487         dev_info(&dc->ndev->dev, "DSI: HS clock rate is %d\n",
488                                                         dsi->target_hs_clk_khz);
489
490         dsi->controller_index = dc->ndev->id;
491
492 #if DSI_USE_SYNC_POINTS
493         dsi->syncpt_id = NVSYNCPT_DSI;
494 #endif
495
496         /*
497          * Force video clock to be continuous mode if
498          * enable_hs_clock_on_lp_cmd_mode is set
499          */
500         if (dsi->info.enable_hs_clock_on_lp_cmd_mode) {
501                 if (dsi->info.video_clock_mode !=
502                                         TEGRA_DSI_VIDEO_CLOCK_CONTINUOUS)
503                         dev_warn(&dc->ndev->dev,
504                                 "Force clock continuous mode\n");
505
506                 dsi->info.video_clock_mode = TEGRA_DSI_VIDEO_CLOCK_CONTINUOUS;
507         }
508
509 }
510
511 static void tegra_dsi_get_phy_timing(struct tegra_dc_dsi_data *dsi,
512                                 struct dsi_phy_timing_inclk *phy_timing_clk,
513                                 u32 clk_ns)
514 {
515
516         phy_timing_clk->t_hsdexit = dsi->info.phy_timing.t_hsdexit_ns ?
517                         (dsi->info.phy_timing.t_hsdexit_ns / clk_ns) :
518                         (T_HSEXIT_DEFAULT(clk_ns));
519
520         phy_timing_clk->t_hstrail = dsi->info.phy_timing.t_hstrail_ns ?
521                         (dsi->info.phy_timing.t_hstrail_ns / clk_ns) :
522                         (T_HSTRAIL_DEFAULT(clk_ns));
523
524         phy_timing_clk->t_datzero = dsi->info.phy_timing.t_datzero_ns ?
525                         (dsi->info.phy_timing.t_datzero_ns / clk_ns) :
526                         (T_DATZERO_DEFAULT(clk_ns));
527
528         phy_timing_clk->t_hsprepr = dsi->info.phy_timing.t_hsprepr_ns ?
529                         (dsi->info.phy_timing.t_hsprepr_ns / clk_ns) :
530                         (T_HSPREPR_DEFAULT(clk_ns));
531
532         phy_timing_clk->t_clktrail = dsi->info.phy_timing.t_clktrail_ns ?
533                                 (dsi->info.phy_timing.t_clktrail_ns / clk_ns) :
534                                 (T_CLKTRAIL_DEFAULT(clk_ns));
535
536         phy_timing_clk->t_clkpost = dsi->info.phy_timing.t_clkpost_ns ?
537                                 (dsi->info.phy_timing.t_clkpost_ns / clk_ns) :
538                                 (T_CLKPOST_DEFAULT(clk_ns));
539
540         phy_timing_clk->t_clkzero = dsi->info.phy_timing.t_clkzero_ns ?
541                                 (dsi->info.phy_timing.t_clkzero_ns / clk_ns) :
542                                 (T_CLKZERO_DEFAULT(clk_ns));
543
544         phy_timing_clk->t_tlpx = dsi->info.phy_timing.t_tlpx_ns ?
545                                 (dsi->info.phy_timing.t_tlpx_ns / clk_ns) :
546                                 (T_TLPX_DEFAULT(clk_ns));
547
548         phy_timing_clk->t_clkpre = T_CLKPRE_DEFAULT(clk_ns);
549         phy_timing_clk->t_clkprepare = T_CLKPREPARE_DEFAULT(clk_ns);
550         phy_timing_clk->t_wakeup = T_WAKEUP_DEFAULT(clk_ns);
551
552         phy_timing_clk->t_taget = 5 * phy_timing_clk->t_tlpx;
553         phy_timing_clk->t_tasure = 2 * phy_timing_clk->t_tlpx;
554         phy_timing_clk->t_tago = 4 * phy_timing_clk->t_tlpx;
555 }
556
557 static void tegra_dsi_set_phy_timing(struct tegra_dc_dsi_data *dsi)
558 {
559         u32 val;
560         struct dsi_phy_timing_inclk phy_timing;
561
562         tegra_dsi_get_phy_timing(dsi, &phy_timing, dsi->current_bit_clk_ns);
563
564         val = DSI_PHY_TIMING_0_THSDEXIT(phy_timing.t_hsdexit) |
565                         DSI_PHY_TIMING_0_THSTRAIL(phy_timing.t_hstrail) |
566                         DSI_PHY_TIMING_0_TDATZERO(phy_timing.t_datzero) |
567                         DSI_PHY_TIMING_0_THSPREPR(phy_timing.t_hsprepr);
568         tegra_dsi_writel(dsi, val, DSI_PHY_TIMING_0);
569
570         val = DSI_PHY_TIMING_1_TCLKTRAIL(phy_timing.t_clktrail) |
571                         DSI_PHY_TIMING_1_TCLKPOST(phy_timing.t_clkpost) |
572                         DSI_PHY_TIMING_1_TCLKZERO(phy_timing.t_clkzero) |
573                         DSI_PHY_TIMING_1_TTLPX(phy_timing.t_tlpx);
574         tegra_dsi_writel(dsi, val, DSI_PHY_TIMING_1);
575
576         val = DSI_PHY_TIMING_2_TCLKPREPARE(phy_timing.t_clkprepare) |
577                 DSI_PHY_TIMING_2_TCLKPRE(phy_timing.t_clkpre) |
578                         DSI_PHY_TIMING_2_TWAKEUP(phy_timing.t_wakeup);
579         tegra_dsi_writel(dsi, val, DSI_PHY_TIMING_2);
580
581         val = DSI_BTA_TIMING_TTAGET(phy_timing.t_taget) |
582                         DSI_BTA_TIMING_TTASURE(phy_timing.t_tasure) |
583                         DSI_BTA_TIMING_TTAGO(phy_timing.t_tago);
584         tegra_dsi_writel(dsi, val, DSI_BTA_TIMING);
585 }
586
587 static u32 tegra_dsi_sol_delay_burst(struct tegra_dc *dc,
588                                 struct tegra_dc_dsi_data *dsi)
589 {
590         u32 dsi_to_pixel_clk_ratio;
591         u32 temp;
592         u32 temp1;
593         u32 mipi_clk_adj_kHz;
594         u32 sol_delay;
595         struct tegra_dc_mode *dc_modes = &dc->mode;
596
597         /* Get Fdsi/Fpixel ration (note: Fdsi is in bit format) */
598         dsi_to_pixel_clk_ratio = (dsi->current_dsi_clk_khz * 2 +
599                 dsi->default_pixel_clk_khz - 1) / dsi->default_pixel_clk_khz;
600
601         /* Convert Fdsi to byte format */
602         dsi_to_pixel_clk_ratio *= 1000/8;
603
604         /* Multiplying by 1000 so that we don't loose the fraction part */
605         temp = dc_modes->h_active * 1000;
606         temp1 = dc_modes->h_active + dc_modes->h_back_porch +
607                         dc_modes->h_sync_width;
608
609         sol_delay = temp1 * dsi_to_pixel_clk_ratio -
610                         temp * dsi->pixel_scaler_mul /
611                         (dsi->pixel_scaler_div * dsi->info.n_data_lanes);
612
613         /* Do rounding on sol delay */
614         sol_delay = (sol_delay + 1000 - 1)/1000;
615
616         /* TODO:
617          * 1. find out the correct sol fifo depth to use
618          * 2. verify with hw about the clamping function
619          */
620         if (sol_delay > (480 * 4)) {
621                 sol_delay = (480 * 4);
622                 mipi_clk_adj_kHz = sol_delay +
623                         (dc_modes->h_active * dsi->pixel_scaler_mul) /
624                         (dsi->info.n_data_lanes * dsi->pixel_scaler_div);
625
626                 mipi_clk_adj_kHz *= (dsi->default_pixel_clk_khz / temp1);
627
628                 mipi_clk_adj_kHz *= 4;
629         }
630
631         dsi->target_hs_clk_khz = mipi_clk_adj_kHz;
632
633         return sol_delay;
634 }
635
636 static void tegra_dsi_set_sol_delay(struct tegra_dc *dc,
637                                 struct tegra_dc_dsi_data *dsi)
638 {
639         u32 sol_delay;
640
641         if (dsi->info.video_burst_mode == TEGRA_DSI_VIDEO_NONE_BURST_MODE ||
642                 dsi->info.video_burst_mode ==
643                                 TEGRA_DSI_VIDEO_NONE_BURST_MODE_WITH_SYNC_END) {
644                 sol_delay = NUMOF_BIT_PER_BYTE * dsi->pixel_scaler_mul /
645                         (dsi->pixel_scaler_div * dsi->info.n_data_lanes);
646                 dsi->status.clk_burst = DSI_CLK_BURST_NONE_BURST;
647         } else {
648                 sol_delay = tegra_dsi_sol_delay_burst(dc, dsi);
649                 dsi->status.clk_burst = DSI_CLK_BURST_BURST_MODE;
650         }
651
652         tegra_dsi_writel(dsi, DSI_SOL_DELAY_SOL_DELAY(sol_delay),
653                                                                 DSI_SOL_DELAY);
654 }
655
656 static void tegra_dsi_set_timeout(struct tegra_dc_dsi_data *dsi)
657 {
658         u32 val;
659         u32 bytes_per_frame;
660         u32 timeout = 0;
661
662         /* TODO: verify the following equation */
663         bytes_per_frame = dsi->current_dsi_clk_khz * 1000 * 2 /
664                                                 (dsi->info.refresh_rate * 8);
665         timeout = bytes_per_frame / DSI_CYCLE_COUNTER_VALUE;
666         timeout = (timeout + DSI_HTX_TO_MARGIN) & 0xffff;
667
668         val = DSI_TIMEOUT_0_LRXH_TO(DSI_LRXH_TO_VALUE) |
669                         DSI_TIMEOUT_0_HTX_TO(timeout);
670         tegra_dsi_writel(dsi, val, DSI_TIMEOUT_0);
671
672         if (dsi->info.panel_reset_timeout_msec)
673                 timeout = (dsi->info.panel_reset_timeout_msec * 1000*1000)
674                                         / dsi->current_bit_clk_ns;
675         else
676                 timeout = DSI_PR_TO_VALUE;
677
678         val = DSI_TIMEOUT_1_PR_TO(timeout) |
679                 DSI_TIMEOUT_1_TA_TO(DSI_TA_TO_VALUE);
680         tegra_dsi_writel(dsi, val, DSI_TIMEOUT_1);
681
682         val = DSI_TO_TALLY_P_RESET_STATUS(IN_RESET) |
683                 DSI_TO_TALLY_TA_TALLY(DSI_TA_TALLY_VALUE)|
684                 DSI_TO_TALLY_LRXH_TALLY(DSI_LRXH_TALLY_VALUE)|
685                 DSI_TO_TALLY_HTX_TALLY(DSI_HTX_TALLY_VALUE);
686         tegra_dsi_writel(dsi, val, DSI_TO_TALLY);
687 }
688
689 static void tegra_dsi_setup_video_mode_pkt_length(struct tegra_dc *dc,
690                                                 struct tegra_dc_dsi_data *dsi)
691 {
692         u32 val;
693         u32 hact_pkt_len;
694         u32 hsa_pkt_len;
695         u32 hbp_pkt_len;
696         u32 hfp_pkt_len;
697
698         hact_pkt_len = dc->mode.h_active * dsi->pixel_scaler_mul /
699                                                         dsi->pixel_scaler_div;
700         hsa_pkt_len = dc->mode.h_sync_width * dsi->pixel_scaler_mul /
701                                                         dsi->pixel_scaler_div;
702         hbp_pkt_len = dc->mode.h_back_porch * dsi->pixel_scaler_mul /
703                                                         dsi->pixel_scaler_div;
704         hfp_pkt_len = dc->mode.h_front_porch * dsi->pixel_scaler_mul /
705                                                         dsi->pixel_scaler_div;
706
707         if (dsi->info.video_burst_mode !=
708                                 TEGRA_DSI_VIDEO_NONE_BURST_MODE_WITH_SYNC_END)
709                 hbp_pkt_len += hsa_pkt_len;
710
711         hsa_pkt_len -= DSI_HSYNC_BLNK_PKT_OVERHEAD;
712         hbp_pkt_len -= DSI_HBACK_PORCH_PKT_OVERHEAD;
713         hfp_pkt_len -= DSI_HFRONT_PORCH_PKT_OVERHEAD;
714
715         val = DSI_PKT_LEN_0_1_LENGTH_0(0) |
716                         DSI_PKT_LEN_0_1_LENGTH_1(hsa_pkt_len);
717         tegra_dsi_writel(dsi, val, DSI_PKT_LEN_0_1);
718
719         val = DSI_PKT_LEN_2_3_LENGTH_2(hbp_pkt_len) |
720                         DSI_PKT_LEN_2_3_LENGTH_3(hact_pkt_len);
721         tegra_dsi_writel(dsi, val, DSI_PKT_LEN_2_3);
722
723         val = DSI_PKT_LEN_4_5_LENGTH_4(hfp_pkt_len) |
724                         DSI_PKT_LEN_4_5_LENGTH_5(0);
725         tegra_dsi_writel(dsi, val, DSI_PKT_LEN_4_5);
726
727         val = DSI_PKT_LEN_6_7_LENGTH_6(0) | DSI_PKT_LEN_6_7_LENGTH_7(0);
728         tegra_dsi_writel(dsi, val, DSI_PKT_LEN_6_7);
729 }
730
731 static void tegra_dsi_setup_cmd_mode_pkt_length(struct tegra_dc *dc,
732                                                 struct tegra_dc_dsi_data *dsi)
733 {
734         unsigned long   val;
735         unsigned long   act_bytes;
736
737         act_bytes = dc->mode.h_active * dsi->pixel_scaler_mul /
738                         dsi->pixel_scaler_div + 1;
739
740         val = DSI_PKT_LEN_0_1_LENGTH_0(0) | DSI_PKT_LEN_0_1_LENGTH_1(0);
741         tegra_dsi_writel(dsi, val, DSI_PKT_LEN_0_1);
742
743         val = DSI_PKT_LEN_2_3_LENGTH_2(0) | DSI_PKT_LEN_2_3_LENGTH_3(act_bytes);
744         tegra_dsi_writel(dsi, val, DSI_PKT_LEN_2_3);
745
746         val = DSI_PKT_LEN_4_5_LENGTH_4(0) | DSI_PKT_LEN_4_5_LENGTH_5(act_bytes);
747         tegra_dsi_writel(dsi, val, DSI_PKT_LEN_4_5);
748
749         val = DSI_PKT_LEN_6_7_LENGTH_6(0) | DSI_PKT_LEN_6_7_LENGTH_7(0x0f0f);
750         tegra_dsi_writel(dsi, val, DSI_PKT_LEN_6_7);
751 }
752
753 static void tegra_dsi_set_pkt_length(struct tegra_dc *dc,
754                                 struct tegra_dc_dsi_data *dsi)
755 {
756         if (dsi->driven_mode == TEGRA_DSI_DRIVEN_BY_HOST)
757                 return;
758
759         if (dsi->info.video_data_type == TEGRA_DSI_VIDEO_TYPE_VIDEO_MODE)
760                 tegra_dsi_setup_video_mode_pkt_length(dc, dsi);
761         else
762                 tegra_dsi_setup_cmd_mode_pkt_length(dc, dsi);
763 }
764
765 static void tegra_dsi_set_pkt_seq(struct tegra_dc *dc,
766                                 struct tegra_dc_dsi_data *dsi)
767 {
768         const u32 *pkt_seq;
769         u32 rgb_info;
770         u32 pkt_seq_3_5_rgb_lo;
771         u32 pkt_seq_3_5_rgb_hi;
772         u32     val;
773         u32 reg;
774         u8  i;
775
776         if (dsi->driven_mode == TEGRA_DSI_DRIVEN_BY_HOST)
777                 return;
778
779         switch (dsi->info.pixel_format) {
780         case TEGRA_DSI_PIXEL_FORMAT_16BIT_P:
781                 rgb_info = CMD_RGB_16BPP;
782                 break;
783         case TEGRA_DSI_PIXEL_FORMAT_18BIT_P:
784                 rgb_info = CMD_RGB_18BPP;
785                 break;
786         case TEGRA_DSI_PIXEL_FORMAT_18BIT_NP:
787                 rgb_info = CMD_RGB_18BPPNP;
788                 break;
789         case TEGRA_DSI_PIXEL_FORMAT_24BIT_P:
790         default:
791                 rgb_info = CMD_RGB_24BPP;
792                 break;
793         }
794
795         pkt_seq_3_5_rgb_lo = 0;
796         pkt_seq_3_5_rgb_hi = 0;
797         if (dsi->info.video_data_type == TEGRA_DSI_VIDEO_TYPE_COMMAND_MODE)
798                 pkt_seq = dsi_pkt_seq_cmd_mode;
799         else {
800                 switch (dsi->info.video_burst_mode) {
801                 case TEGRA_DSI_VIDEO_BURST_MODE_LOWEST_SPEED:
802                 case TEGRA_DSI_VIDEO_BURST_MODE_LOW_SPEED:
803                 case TEGRA_DSI_VIDEO_BURST_MODE_MEDIUM_SPEED:
804                 case TEGRA_DSI_VIDEO_BURST_MODE_FAST_SPEED:
805                 case TEGRA_DSI_VIDEO_BURST_MODE_FASTEST_SPEED:
806                         pkt_seq_3_5_rgb_lo =
807                                         DSI_PKT_SEQ_3_LO_PKT_32_ID(rgb_info);
808                         if (!dsi->info.no_pkt_seq_eot)
809                                 pkt_seq = dsi_pkt_seq_video_burst;
810                         else
811                                 pkt_seq = dsi_pkt_seq_video_burst_no_eot;
812                         break;
813                 case TEGRA_DSI_VIDEO_NONE_BURST_MODE_WITH_SYNC_END:
814                         pkt_seq_3_5_rgb_hi =
815                                         DSI_PKT_SEQ_3_HI_PKT_34_ID(rgb_info);
816                         pkt_seq = dsi_pkt_seq_video_non_burst_syne;
817                         break;
818                 case TEGRA_DSI_VIDEO_NONE_BURST_MODE:
819                 default:
820                         pkt_seq_3_5_rgb_lo =
821                                         DSI_PKT_SEQ_3_LO_PKT_32_ID(rgb_info);
822                         pkt_seq = dsi_pkt_seq_video_non_burst;
823                         break;
824                 }
825         }
826
827         for (i = 0; i < NUMOF_PKT_SEQ; i++) {
828                 val = pkt_seq[i];
829                 reg = dsi_pkt_seq_reg[i];
830                 if ((reg == DSI_PKT_SEQ_3_LO) || (reg == DSI_PKT_SEQ_5_LO))
831                         val |= pkt_seq_3_5_rgb_lo;
832                 if ((reg == DSI_PKT_SEQ_3_HI) || (reg == DSI_PKT_SEQ_5_HI))
833                         val |= pkt_seq_3_5_rgb_hi;
834                 tegra_dsi_writel(dsi, val, reg);
835         }
836 }
837
838 static void tegra_dsi_stop_dc_stream(struct tegra_dc *dc,
839                                         struct tegra_dc_dsi_data *dsi)
840 {
841         tegra_dc_writel(dc, DISP_CTRL_MODE_STOP, DC_CMD_DISPLAY_COMMAND);
842         tegra_dc_writel(dc, 0, DC_DISP_DISP_WIN_OPTIONS);
843         tegra_dc_writel(dc, GENERAL_UPDATE, DC_CMD_STATE_CONTROL);
844         tegra_dc_writel(dc, GENERAL_ACT_REQ , DC_CMD_STATE_CONTROL);
845
846         dsi->status.dc_stream = DSI_DC_STREAM_DISABLE;
847 }
848
849 static void tegra_dsi_stop_dc_stream_at_frame_end(struct tegra_dc *dc,
850                                                 struct tegra_dc_dsi_data *dsi)
851 {
852         int val;
853         long timeout;
854         u32 frame_period = DIV_ROUND_UP(S_TO_MS(1), dsi->info.refresh_rate);
855
856         /* stop dc */
857         tegra_dsi_stop_dc_stream(dc, dsi);
858
859         /* enable frame end interrupt */
860         val = tegra_dc_readl(dc, DC_CMD_INT_MASK);
861         val |= FRAME_END_INT;
862         tegra_dc_writel(dc, val, DC_CMD_INT_MASK);
863
864         /* wait for frame_end completion.
865          * timeout is 2 frame duration to accomodate for
866          * internal delay.
867          */
868         timeout = wait_for_completion_interruptible_timeout(
869                         &dc->frame_end_complete,
870                         msecs_to_jiffies(2 * frame_period));
871
872         /* disable frame end interrupt */
873         val = tegra_dc_readl(dc, DC_CMD_INT_MASK);
874         val &= ~FRAME_END_INT;
875         tegra_dc_writel(dc, val, DC_CMD_INT_MASK);
876
877         if (timeout == 0)
878                 dev_warn(&dc->ndev->dev,
879                         "DC doesn't stop at end of frame.\n");
880 }
881
882 static void tegra_dsi_start_dc_stream(struct tegra_dc *dc,
883                                         struct tegra_dc_dsi_data *dsi)
884 {
885         u32 val;
886
887         tegra_dc_writel(dc, DSI_ENABLE, DC_DISP_DISP_WIN_OPTIONS);
888
889         /* TODO: clean up */
890         tegra_dc_writel(dc, PW0_ENABLE | PW1_ENABLE | PW2_ENABLE | PW3_ENABLE |
891                         PW4_ENABLE | PM0_ENABLE | PM1_ENABLE,
892                         DC_CMD_DISPLAY_POWER_CONTROL);
893
894         /* Configure one-shot mode or continuous mode */
895         if (dc->out->flags & TEGRA_DC_OUT_ONE_SHOT_MODE) {
896                 /* disable LSPI/LCD_DE output */
897                 val = PIN_OUTPUT_LSPI_OUTPUT_DIS;
898                 tegra_dc_writel(dc, val, DC_COM_PIN_OUTPUT_ENABLE3);
899
900                 /* enable MSF & set MSF polarity */
901                 val = MSF_ENABLE | MSF_LSPI;
902                 if (!dsi->info.te_polarity_low)
903                         val |= MSF_POLARITY_HIGH;
904                 else
905                         val |= MSF_POLARITY_LOW;
906                 tegra_dc_writel(dc, val, DC_CMD_DISPLAY_COMMAND_OPTION0);
907
908                 /* set non-continuous mode */
909                 tegra_dc_writel(dc, DISP_CTRL_MODE_NC_DISPLAY,
910                                                 DC_CMD_DISPLAY_COMMAND);
911                 tegra_dc_writel(dc, GENERAL_UPDATE, DC_CMD_STATE_CONTROL);
912                 tegra_dc_writel(dc, GENERAL_ACT_REQ | NC_HOST_TRIG,
913                                                 DC_CMD_STATE_CONTROL);
914         } else {
915                 /* set continuous mode */
916                 tegra_dc_writel(dc, DISP_CTRL_MODE_C_DISPLAY,
917                                                 DC_CMD_DISPLAY_COMMAND);
918                 tegra_dc_writel(dc, GENERAL_UPDATE, DC_CMD_STATE_CONTROL);
919                 tegra_dc_writel(dc, GENERAL_ACT_REQ, DC_CMD_STATE_CONTROL);
920         }
921
922         dsi->status.dc_stream = DSI_DC_STREAM_ENABLE;
923 }
924
925 static void tegra_dsi_set_dc_clk(struct tegra_dc *dc,
926                                 struct tegra_dc_dsi_data *dsi)
927 {
928         u32 shift_clk_div_register;
929         u32 val;
930
931         /* Get the corresponding register value of shift_clk_div. */
932         shift_clk_div_register = dsi->shift_clk_div * 2 - 2;
933
934 #ifdef CONFIG_TEGRA_FPGA_PLATFORM
935         shift_clk_div_register = 1;
936 #endif
937
938         /* TODO: find out if PCD3 option is required */
939         val = PIXEL_CLK_DIVIDER_PCD1 |
940                 SHIFT_CLK_DIVIDER(shift_clk_div_register);
941         tegra_dc_writel(dc, val, DC_DISP_DISP_CLOCK_CONTROL);
942 }
943
944 static void tegra_dsi_set_dsi_clk(struct tegra_dc *dc,
945                         struct tegra_dc_dsi_data *dsi, u32 clk)
946 {
947         u32 rm;
948
949         /* Round up to MHz */
950         rm = clk % 1000;
951         if (rm != 0)
952                 clk -= rm;
953
954         /* Set up pixel clock */
955         dc->shift_clk_div = dsi->shift_clk_div;
956         dc->mode.pclk = (clk * 1000) / dsi->shift_clk_div;
957
958         /* Enable DSI clock */
959         tegra_dc_setup_clk(dc, dsi->dsi_clk);
960         if (!dsi->clk_ref) {
961                 dsi->clk_ref = true;
962                 clk_enable(dsi->dsi_clk);
963                 tegra_periph_reset_deassert(dsi->dsi_clk);
964         }
965         dsi->current_dsi_clk_khz = clk_get_rate(dsi->dsi_clk) / 1000;
966         dsi->current_bit_clk_ns =  1000*1000 / (dsi->current_dsi_clk_khz * 2);
967 }
968
969 static void tegra_dsi_hs_clk_out_enable(struct tegra_dc_dsi_data *dsi)
970 {
971         u32 val;
972
973         val = tegra_dsi_readl(dsi, DSI_CONTROL);
974         val &= ~DSI_CONTROL_HS_CLK_CTRL(1);
975
976         if (dsi->info.video_clock_mode == TEGRA_DSI_VIDEO_CLOCK_CONTINUOUS) {
977                 val |= DSI_CONTROL_HS_CLK_CTRL(CONTINUOUS);
978                 dsi->status.clk_mode = DSI_PHYCLK_CONTINUOUS;
979         } else {
980                 val |= DSI_CONTROL_HS_CLK_CTRL(TX_ONLY);
981                 dsi->status.clk_mode = DSI_PHYCLK_TX_ONLY;
982         }
983         tegra_dsi_writel(dsi, val, DSI_CONTROL);
984
985         val = tegra_dsi_readl(dsi, DSI_HOST_DSI_CONTROL);
986         val &= ~DSI_HOST_DSI_CONTROL_HIGH_SPEED_TRANS(1);
987         val |= DSI_HOST_DSI_CONTROL_HIGH_SPEED_TRANS(TEGRA_DSI_HIGH);
988         tegra_dsi_writel(dsi, val, DSI_HOST_DSI_CONTROL);
989
990         dsi->status.clk_out = DSI_PHYCLK_OUT_EN;
991 }
992
993 static void tegra_dsi_hs_clk_out_enable_in_lp(struct tegra_dc_dsi_data *dsi)
994 {
995         u32 val;
996         tegra_dsi_hs_clk_out_enable(dsi);
997
998         val = tegra_dsi_readl(dsi, DSI_HOST_DSI_CONTROL);
999         val &= ~DSI_HOST_DSI_CONTROL_HIGH_SPEED_TRANS(1);
1000         val |= DSI_HOST_DSI_CONTROL_HIGH_SPEED_TRANS(TEGRA_DSI_LOW);
1001         tegra_dsi_writel(dsi, val, DSI_HOST_DSI_CONTROL);
1002 }
1003
1004 static void tegra_dsi_hs_clk_out_disable(struct tegra_dc *dc,
1005                                                 struct tegra_dc_dsi_data *dsi)
1006 {
1007         u32 val;
1008
1009         if (dsi->status.dc_stream == DSI_DC_STREAM_ENABLE)
1010                 tegra_dsi_stop_dc_stream_at_frame_end(dc, dsi);
1011
1012         tegra_dsi_writel(dsi, TEGRA_DSI_DISABLE, DSI_POWER_CONTROL);
1013         /* stabilization delay */
1014         udelay(300);
1015
1016         val = tegra_dsi_readl(dsi, DSI_HOST_DSI_CONTROL);
1017         val &= ~DSI_HOST_DSI_CONTROL_HIGH_SPEED_TRANS(1);
1018         val |= DSI_HOST_DSI_CONTROL_HIGH_SPEED_TRANS(TEGRA_DSI_LOW);
1019         tegra_dsi_writel(dsi, val, DSI_HOST_DSI_CONTROL);
1020
1021         tegra_dsi_writel(dsi, TEGRA_DSI_ENABLE, DSI_POWER_CONTROL);
1022         /* stabilization delay */
1023         udelay(300);
1024
1025         dsi->status.clk_mode = DSI_PHYCLK_NOT_INIT;
1026         dsi->status.clk_out = DSI_PHYCLK_OUT_DIS;
1027 }
1028
1029 static void tegra_dsi_set_control_reg_lp(struct tegra_dc_dsi_data *dsi)
1030 {
1031         u32 dsi_control;
1032         u32 host_dsi_control;
1033         u32 max_threshold;
1034
1035         dsi_control = dsi->dsi_control_val | DSI_CTRL_HOST_DRIVEN;
1036         host_dsi_control = HOST_DSI_CTRL_COMMON |
1037                         HOST_DSI_CTRL_HOST_DRIVEN |
1038                         DSI_HOST_DSI_CONTROL_HIGH_SPEED_TRANS(TEGRA_DSI_LOW);
1039         max_threshold = DSI_MAX_THRESHOLD_MAX_THRESHOLD(DSI_HOST_FIFO_DEPTH);
1040
1041         tegra_dsi_writel(dsi, max_threshold, DSI_MAX_THRESHOLD);
1042         tegra_dsi_writel(dsi, dsi_control, DSI_CONTROL);
1043         tegra_dsi_writel(dsi, host_dsi_control, DSI_HOST_DSI_CONTROL);
1044
1045         dsi->status.driven = DSI_DRIVEN_MODE_HOST;
1046         dsi->status.clk_burst = DSI_CLK_BURST_NOT_INIT;
1047         dsi->status.vtype = DSI_VIDEO_TYPE_NOT_INIT;
1048 }
1049
1050 static void tegra_dsi_set_control_reg_hs(struct tegra_dc_dsi_data *dsi)
1051 {
1052         u32 dsi_control;
1053         u32 host_dsi_control;
1054         u32 max_threshold;
1055         u32 dcs_cmd;
1056
1057         dsi_control = dsi->dsi_control_val;
1058         host_dsi_control = HOST_DSI_CTRL_COMMON;
1059         max_threshold = 0;
1060         dcs_cmd = 0;
1061
1062         if (dsi->driven_mode == TEGRA_DSI_DRIVEN_BY_HOST) {
1063                 dsi_control |= DSI_CTRL_HOST_DRIVEN;
1064                 host_dsi_control |= HOST_DSI_CTRL_HOST_DRIVEN;
1065                 max_threshold =
1066                         DSI_MAX_THRESHOLD_MAX_THRESHOLD(DSI_HOST_FIFO_DEPTH);
1067                 dsi->status.driven = DSI_DRIVEN_MODE_HOST;
1068         } else {
1069                 dsi_control |= DSI_CTRL_DC_DRIVEN;
1070                 host_dsi_control |= HOST_DSI_CTRL_DC_DRIVEN;
1071                 max_threshold =
1072                         DSI_MAX_THRESHOLD_MAX_THRESHOLD(DSI_VIDEO_FIFO_DEPTH);
1073                 dsi->status.driven = DSI_DRIVEN_MODE_DC;
1074         }
1075
1076         if (dsi->info.video_data_type == TEGRA_DSI_VIDEO_TYPE_COMMAND_MODE) {
1077                 dsi_control |= DSI_CTRL_CMD_MODE;
1078                 dcs_cmd = DSI_DCS_CMDS_LT5_DCS_CMD(DSI_WRITE_MEMORY_START)|
1079                         DSI_DCS_CMDS_LT3_DCS_CMD(DSI_WRITE_MEMORY_CONTINUE);
1080                 dsi->status.vtype = DSI_VIDEO_TYPE_CMD_MODE;
1081
1082         } else {
1083                 dsi_control |= DSI_CTRL_VIDEO_MODE;
1084                 dsi->status.vtype = DSI_VIDEO_TYPE_VIDEO_MODE;
1085         }
1086
1087         tegra_dsi_writel(dsi, max_threshold, DSI_MAX_THRESHOLD);
1088         tegra_dsi_writel(dsi, dcs_cmd, DSI_DCS_CMDS);
1089         tegra_dsi_writel(dsi, dsi_control, DSI_CONTROL);
1090         tegra_dsi_writel(dsi, host_dsi_control, DSI_HOST_DSI_CONTROL);
1091 }
1092
1093 static void tegra_dsi_pad_calibration(struct tegra_dc_dsi_data *dsi)
1094 {
1095         u32 val;
1096
1097         val =   DSI_PAD_CONTROL_PAD_LPUPADJ(0x1) |
1098                 DSI_PAD_CONTROL_PAD_LPDNADJ(0x1) |
1099                 DSI_PAD_CONTROL_PAD_PREEMP_EN(0x1) |
1100                 DSI_PAD_CONTROL_PAD_SLEWDNADJ(0x6) |
1101                 DSI_PAD_CONTROL_PAD_SLEWUPADJ(0x6);
1102         if (!dsi->ulpm) {
1103                 val |=  DSI_PAD_CONTROL_PAD_PDIO(0) |
1104                         DSI_PAD_CONTROL_PAD_PDIO_CLK(0) |
1105                         DSI_PAD_CONTROL_PAD_PULLDN_ENAB(TEGRA_DSI_DISABLE);
1106         } else {
1107                 val |=  DSI_PAD_CONTROL_PAD_PDIO(0x3) |
1108                         DSI_PAD_CONTROL_PAD_PDIO_CLK(0x1) |
1109                         DSI_PAD_CONTROL_PAD_PULLDN_ENAB(TEGRA_DSI_ENABLE);
1110         }
1111         tegra_dsi_writel(dsi, val, DSI_PAD_CONTROL);
1112
1113         val = MIPI_CAL_TERMOSA(0x4);
1114         tegra_vi_csi_writel(val, CSI_CILA_MIPI_CAL_CONFIG_0);
1115
1116         val = MIPI_CAL_TERMOSB(0x4);
1117         tegra_vi_csi_writel(val, CSI_CILB_MIPI_CAL_CONFIG_0);
1118
1119         val = MIPI_CAL_HSPUOSD(0x3) | MIPI_CAL_HSPDOSD(0x4);
1120         tegra_vi_csi_writel(val, CSI_DSI_MIPI_CAL_CONFIG);
1121
1122         val = PAD_DRIV_DN_REF(0x5) | PAD_DRIV_UP_REF(0x7);
1123         tegra_vi_csi_writel(val, CSI_MIPIBIAS_PAD_CONFIG);
1124 }
1125
1126 static int tegra_dsi_init_hw(struct tegra_dc *dc,
1127                                                 struct tegra_dc_dsi_data *dsi)
1128 {
1129         u32 i;
1130
1131         tegra_dsi_writel(dsi,
1132                 DSI_POWER_CONTROL_LEG_DSI_ENABLE(TEGRA_DSI_DISABLE),
1133                 DSI_POWER_CONTROL);
1134         /* stabilization delay */
1135         udelay(300);
1136
1137         tegra_dsi_set_dsi_clk(dc, dsi, dsi->target_lp_clk_khz);
1138         if (dsi->info.dsi_instance) {
1139                 /* TODO:Set the misc register*/
1140         }
1141
1142         /* TODO: only need to change the timing for bta */
1143         tegra_dsi_set_phy_timing(dsi);
1144
1145         if (dsi->status.dc_stream == DSI_DC_STREAM_ENABLE)
1146                 tegra_dsi_stop_dc_stream_at_frame_end(dc, dsi);
1147
1148         /* Initializing DSI registers */
1149         for (i = 0; i < ARRAY_SIZE(init_reg); i++)
1150                 tegra_dsi_writel(dsi, 0, init_reg[i]);
1151
1152         tegra_dsi_writel(dsi, dsi->dsi_control_val, DSI_CONTROL);
1153
1154         tegra_dsi_pad_calibration(dsi);
1155
1156         tegra_dsi_writel(dsi,
1157                 DSI_POWER_CONTROL_LEG_DSI_ENABLE(TEGRA_DSI_ENABLE),
1158                 DSI_POWER_CONTROL);
1159         /* stabilization delay */
1160         udelay(300);
1161
1162         dsi->status.init = DSI_MODULE_INIT;
1163         dsi->status.lphs = DSI_LPHS_NOT_INIT;
1164         dsi->status.vtype = DSI_VIDEO_TYPE_NOT_INIT;
1165         dsi->status.driven = DSI_DRIVEN_MODE_NOT_INIT;
1166         dsi->status.clk_out = DSI_PHYCLK_OUT_DIS;
1167         dsi->status.clk_mode = DSI_PHYCLK_NOT_INIT;
1168         dsi->status.clk_burst = DSI_CLK_BURST_NOT_INIT;
1169         dsi->status.dc_stream = DSI_DC_STREAM_DISABLE;
1170         dsi->status.lp_op = DSI_LP_OP_NOT_INIT;
1171
1172         return 0;
1173 }
1174
1175 static int tegra_dsi_set_to_lp_mode(struct tegra_dc *dc,
1176                         struct tegra_dc_dsi_data *dsi, u8 lp_op)
1177 {
1178         int err;
1179
1180         if (dsi->status.init != DSI_MODULE_INIT) {
1181                 err = -EPERM;
1182                 goto fail;
1183         }
1184
1185         if (dsi->status.lphs == DSI_LPHS_IN_LP_MODE &&
1186                         dsi->status.lp_op == lp_op)
1187                 goto success;
1188
1189         if (dsi->status.dc_stream == DSI_DC_STREAM_ENABLE)
1190                 tegra_dsi_stop_dc_stream_at_frame_end(dc, dsi);
1191
1192         /* disable/enable hs clk according to enable_hs_clock_on_lp_cmd_mode */
1193         if ((dsi->status.clk_out == DSI_PHYCLK_OUT_EN) &&
1194                 (!dsi->info.enable_hs_clock_on_lp_cmd_mode))
1195                 tegra_dsi_hs_clk_out_disable(dc, dsi);
1196
1197         dsi->target_lp_clk_khz = tegra_dsi_get_lp_clk_rate(dsi, lp_op);
1198         if (dsi->current_dsi_clk_khz != dsi->target_lp_clk_khz) {
1199                 tegra_dsi_set_dsi_clk(dc, dsi, dsi->target_lp_clk_khz);
1200                 tegra_dsi_set_timeout(dsi);
1201         }
1202
1203         tegra_dsi_set_control_reg_lp(dsi);
1204
1205         if ((dsi->status.clk_out == DSI_PHYCLK_OUT_DIS) &&
1206                 (dsi->info.enable_hs_clock_on_lp_cmd_mode))
1207                 tegra_dsi_hs_clk_out_enable_in_lp(dsi);
1208
1209         dsi->status.lphs = DSI_LPHS_IN_LP_MODE;
1210         dsi->status.lp_op = lp_op;
1211 success:
1212         err = 0;
1213 fail:
1214         return err;
1215 }
1216
1217 static int tegra_dsi_set_to_hs_mode(struct tegra_dc *dc,
1218                                         struct tegra_dc_dsi_data *dsi)
1219 {
1220         int err;
1221
1222         if (dsi->status.init != DSI_MODULE_INIT) {
1223                 err = -EPERM;
1224                 goto fail;
1225         }
1226
1227         if (dsi->status.lphs == DSI_LPHS_IN_HS_MODE)
1228                 goto success;
1229
1230         if (dsi->status.dc_stream == DSI_DC_STREAM_ENABLE)
1231                 tegra_dsi_stop_dc_stream_at_frame_end(dc, dsi);
1232
1233         if ((dsi->status.clk_out == DSI_PHYCLK_OUT_EN) &&
1234                 (!dsi->info.enable_hs_clock_on_lp_cmd_mode))
1235                 tegra_dsi_hs_clk_out_disable(dc, dsi);
1236
1237         if (dsi->current_dsi_clk_khz != dsi->target_hs_clk_khz) {
1238                 tegra_dsi_set_dsi_clk(dc, dsi, dsi->target_hs_clk_khz);
1239                 tegra_dsi_set_timeout(dsi);
1240         }
1241
1242         tegra_dsi_set_phy_timing(dsi);
1243
1244         if (dsi->driven_mode == TEGRA_DSI_DRIVEN_BY_DC) {
1245                 tegra_dsi_set_pkt_seq(dc, dsi);
1246                 tegra_dsi_set_pkt_length(dc, dsi);
1247                 tegra_dsi_set_sol_delay(dc, dsi);
1248                 tegra_dsi_set_dc_clk(dc, dsi);
1249         }
1250
1251         tegra_dsi_set_control_reg_hs(dsi);
1252
1253         if (dsi->status.clk_out == DSI_PHYCLK_OUT_DIS ||
1254                 dsi->info.enable_hs_clock_on_lp_cmd_mode)
1255                 tegra_dsi_hs_clk_out_enable(dsi);
1256
1257         dsi->status.lphs = DSI_LPHS_IN_HS_MODE;
1258 success:
1259         dsi->status.lp_op = DSI_LP_OP_NOT_INIT;
1260         err = 0;
1261 fail:
1262         return err;
1263 }
1264
1265 static bool tegra_dsi_write_busy(struct tegra_dc_dsi_data *dsi)
1266 {
1267         u32 timeout = 0;
1268         bool retVal = true;
1269
1270         while (timeout <= DSI_MAX_COMMAND_DELAY_USEC) {
1271                 if (!(DSI_TRIGGER_HOST_TRIGGER(0x1) &
1272                         tegra_dsi_readl(dsi, DSI_TRIGGER))) {
1273                         retVal = false;
1274                         break;
1275                 }
1276                 udelay(DSI_COMMAND_DELAY_STEPS_USEC);
1277                 timeout += DSI_COMMAND_DELAY_STEPS_USEC;
1278         }
1279
1280         return retVal;
1281 }
1282
1283 static bool tegra_dsi_read_busy(struct tegra_dc_dsi_data *dsi)
1284 {
1285         u32 timeout = 0;
1286         bool retVal = true;
1287
1288         while (timeout <  DSI_STATUS_POLLING_DURATION_USEC) {
1289                 if (!(DSI_HOST_DSI_CONTROL_IMM_BTA(0x1) &
1290                         tegra_dsi_readl(dsi, DSI_HOST_DSI_CONTROL))) {
1291                         retVal = false;
1292                         break;
1293                 }
1294                 udelay(DSI_STATUS_POLLING_DELAY_USEC);
1295                 timeout += DSI_STATUS_POLLING_DELAY_USEC;
1296         }
1297
1298         return retVal;
1299 }
1300
1301 static bool tegra_dsi_host_busy(struct tegra_dc_dsi_data *dsi)
1302 {
1303         int err = 0;
1304
1305         if (tegra_dsi_write_busy(dsi)) {
1306                 err = -EBUSY;
1307                 dev_err(&dsi->dc->ndev->dev,
1308                         "DSI trigger bit already set\n");
1309                 goto fail;
1310         }
1311
1312         if (tegra_dsi_read_busy(dsi)) {
1313                 err = -EBUSY;
1314                 dev_err(&dsi->dc->ndev->dev,
1315                         "DSI immediate bta bit already set\n");
1316                 goto fail;
1317         }
1318 fail:
1319         return err;
1320 }
1321
1322 static void tegra_dsi_reset_underflow_overflow
1323                                 (struct tegra_dc_dsi_data *dsi)
1324 {
1325         u32 val;
1326
1327         val = tegra_dsi_readl(dsi, DSI_STATUS);
1328         val &= (DSI_STATUS_LB_OVERFLOW(0x1) | DSI_STATUS_LB_UNDERFLOW(0x1));
1329         if (val) {
1330                 dev_warn(&dsi->dc->ndev->dev, "Reset overflow/underflow\n");
1331                 val = tegra_dsi_readl(dsi, DSI_HOST_DSI_CONTROL);
1332                 val |= DSI_HOST_CONTROL_FIFO_STAT_RESET(0x1);
1333                 tegra_dsi_writel(dsi, val, DSI_HOST_DSI_CONTROL);
1334                 ndelay(200);
1335         }
1336 }
1337
1338 static void tegra_dsi_soft_reset(struct tegra_dc_dsi_data *dsi)
1339 {
1340         tegra_dsi_writel(dsi,
1341                 DSI_POWER_CONTROL_LEG_DSI_ENABLE(TEGRA_DSI_DISABLE),
1342                 DSI_POWER_CONTROL);
1343         /* stabilization delay */
1344         udelay(300);
1345
1346         tegra_dsi_writel(dsi,
1347                 DSI_POWER_CONTROL_LEG_DSI_ENABLE(TEGRA_DSI_ENABLE),
1348                 DSI_POWER_CONTROL);
1349         /* stabilization delay */
1350         udelay(300);
1351 }
1352
1353 static void tegra_dsi_reset_read_count(struct tegra_dc_dsi_data *dsi)
1354 {
1355         u32 val;
1356
1357         val = tegra_dsi_readl(dsi, DSI_STATUS);
1358         val &= DSI_STATUS_RD_FIFO_COUNT(0x1f);
1359         if (val) {
1360                 dev_warn(&dsi->dc->ndev->dev,
1361                         "DSI read count not zero, resetting\n");
1362                 tegra_dsi_soft_reset(dsi);
1363         }
1364 }
1365
1366 static struct dsi_status *tegra_dsi_save_state_switch_to_host_cmd_mode(
1367                                                 struct tegra_dc_dsi_data *dsi,
1368                                                 struct tegra_dc *dc,
1369                                                 u8 lp_op)
1370 {
1371         struct dsi_status *init_status;
1372         int err;
1373
1374         init_status = kzalloc(sizeof(*init_status), GFP_KERNEL);
1375         if (!init_status)
1376                 return ERR_PTR(-ENOMEM);
1377
1378         *init_status = dsi->status;
1379
1380         if (dsi->status.lphs == DSI_LPHS_IN_HS_MODE) {
1381                 if (dsi->status.driven == DSI_DRIVEN_MODE_DC) {
1382                         if (dsi->status.dc_stream == DSI_DC_STREAM_ENABLE)
1383                                 tegra_dsi_stop_dc_stream_at_frame_end(dc, dsi);
1384                         dsi->driven_mode = TEGRA_DSI_DRIVEN_BY_HOST;
1385                         if (dsi->info.hs_cmd_mode_supported) {
1386                                 err = tegra_dsi_set_to_hs_mode(dc, dsi);
1387                                 if (err < 0) {
1388                                         dev_err(&dc->ndev->dev,
1389                                         "Switch to HS host mode failed\n");
1390                                         goto fail;
1391                                 }
1392                         }
1393                 }
1394                 if (!dsi->info.hs_cmd_mode_supported) {
1395                         err =
1396                         tegra_dsi_set_to_lp_mode(dc, dsi, lp_op);
1397                         if (err < 0) {
1398                                 dev_err(&dc->ndev->dev,
1399                                 "DSI failed to go to LP mode\n");
1400                                 goto fail;
1401                         }
1402                 }
1403         } else if (dsi->status.lphs == DSI_LPHS_IN_LP_MODE) {
1404                 if (dsi->status.lp_op != lp_op) {
1405                         err = tegra_dsi_set_to_lp_mode(dc, dsi, lp_op);
1406                         if (err < 0) {
1407                                 dev_err(&dc->ndev->dev,
1408                                 "DSI failed to go to LP mode\n");
1409                                 goto fail;
1410                         }
1411                 }
1412         }
1413
1414         return init_status;
1415 fail:
1416         kfree(init_status);
1417         return ERR_PTR(err);
1418 }
1419
1420 static struct dsi_status *tegra_dsi_prepare_host_transmission(
1421                                 struct tegra_dc *dc,
1422                                 struct tegra_dc_dsi_data *dsi,
1423                                 u8 lp_op)
1424 {
1425         int err = 0;
1426         struct dsi_status *init_status;
1427
1428         if (dsi->status.init != DSI_MODULE_INIT ||
1429                 dsi->ulpm) {
1430                 err = -EPERM;
1431                 goto fail;
1432         }
1433
1434         if (tegra_dsi_host_busy(dsi)) {
1435                 err = -EBUSY;
1436                 dev_err(&dc->ndev->dev, "DSI host busy\n");
1437                 goto fail;
1438         }
1439
1440         tegra_dsi_reset_underflow_overflow(dsi);
1441
1442         if (lp_op == DSI_LP_OP_READ)
1443                 tegra_dsi_reset_read_count(dsi);
1444
1445         if (dsi->status.lphs == DSI_LPHS_NOT_INIT) {
1446                 err = tegra_dsi_set_to_lp_mode(dc, dsi, lp_op);
1447                 if (err < 0) {
1448                         dev_err(&dc->ndev->dev, "Failed to config LP write\n");
1449                         goto fail;
1450                 }
1451         }
1452
1453         init_status = tegra_dsi_save_state_switch_to_host_cmd_mode
1454                                         (dsi, dc, lp_op);
1455         if (IS_ERR_OR_NULL(init_status)) {
1456                 err = PTR_ERR(init_status);
1457                 dev_err(&dc->ndev->dev, "DSI state saving failed\n");
1458                 goto fail;
1459         }
1460
1461         return init_status;
1462 fail:
1463         return ERR_PTR(err);
1464 }
1465
1466 static int tegra_dsi_restore_state(struct tegra_dc *dc,
1467                                 struct tegra_dc_dsi_data *dsi,
1468                                 struct dsi_status *init_status)
1469 {
1470         bool switch_back_to_dc_mode = false;
1471         bool switch_back_to_hs_mode = false;
1472         bool restart_dc_stream;
1473         int err = 0;
1474
1475         switch_back_to_dc_mode = (dsi->status.driven ==
1476                                 DSI_DRIVEN_MODE_HOST &&
1477                                 init_status->driven ==
1478                                 DSI_DRIVEN_MODE_DC);
1479         switch_back_to_hs_mode = (dsi->status.lphs ==
1480                                 DSI_LPHS_IN_LP_MODE &&
1481                                 init_status->lphs ==
1482                                 DSI_LPHS_IN_HS_MODE);
1483         restart_dc_stream = (dsi->status.dc_stream ==
1484                                 DSI_DC_STREAM_DISABLE &&
1485                                 init_status->dc_stream ==
1486                                 DSI_DC_STREAM_ENABLE);
1487
1488         if (dsi->status.lphs == DSI_LPHS_IN_LP_MODE &&
1489                 init_status->lphs == DSI_LPHS_IN_LP_MODE) {
1490                 if (dsi->status.lp_op != init_status->lp_op) {
1491                         err =
1492                         tegra_dsi_set_to_lp_mode(dc, dsi, init_status->lp_op);
1493                         if (err < 0) {
1494                                 dev_err(&dc->ndev->dev,
1495                                         "Failed to config LP mode\n");
1496                                 goto fail;
1497                         }
1498                 }
1499                 goto success;
1500         }
1501
1502         if (switch_back_to_dc_mode)
1503                 dsi->driven_mode = TEGRA_DSI_DRIVEN_BY_DC;
1504         if (switch_back_to_dc_mode || switch_back_to_hs_mode) {
1505                 err = tegra_dsi_set_to_hs_mode(dc, dsi);
1506                 if (err < 0) {
1507                         dev_err(&dc->ndev->dev, "Failed to config HS mode\n");
1508                         goto fail;
1509                 }
1510         }
1511         if (restart_dc_stream)
1512                 tegra_dsi_start_dc_stream(dc, dsi);
1513
1514 success:
1515 fail:
1516         kfree(init_status);
1517         return err;
1518 }
1519
1520 static int tegra_dsi_host_trigger(struct tegra_dc_dsi_data *dsi)
1521 {
1522         int status = 0;
1523
1524         if (tegra_dsi_readl(dsi, DSI_TRIGGER)) {
1525                 status = -EBUSY;
1526                 goto fail;
1527         }
1528
1529         tegra_dsi_writel(dsi,
1530                 DSI_TRIGGER_HOST_TRIGGER(TEGRA_DSI_ENABLE), DSI_TRIGGER);
1531
1532 #if DSI_USE_SYNC_POINTS
1533         status = tegra_dsi_syncpt(dsi);
1534         if (status < 0) {
1535                 dev_err(&dsi->dc->ndev->dev,
1536                         "DSI syncpt for host trigger failed\n");
1537                 goto fail;
1538         }
1539 #else
1540         if (tegra_dsi_write_busy(dsi)) {
1541                 status = -EBUSY;
1542                 dev_err(&dsi->dc->ndev->dev,
1543                         "Timeout waiting on write completion\n");
1544         }
1545 #endif
1546
1547 fail:
1548         return status;
1549 }
1550
1551 static int _tegra_dsi_write_data(struct tegra_dc_dsi_data *dsi,
1552                                         u8 *pdata, u8 data_id, u16 data_len)
1553 {
1554         u8 virtual_channel;
1555         u8 *pval;
1556         u32 val;
1557         int err;
1558
1559         err = 0;
1560
1561         virtual_channel = dsi->info.virtual_channel <<
1562                                                 DSI_VIR_CHANNEL_BIT_POSITION;
1563
1564         /* always use hw for ecc */
1565         val = (virtual_channel | data_id) << 0 |
1566                         data_len << 8;
1567         tegra_dsi_writel(dsi, val, DSI_WR_DATA);
1568
1569         /* if pdata != NULL, pkt type is long pkt */
1570         if (pdata != NULL) {
1571                 while (data_len) {
1572                         if (data_len >= 4) {
1573                                 val = ((u32 *) pdata)[0];
1574                                 data_len -= 4;
1575                                 pdata += 4;
1576                         } else {
1577                                 val = 0;
1578                                 pval = (u8 *) &val;
1579                                 do
1580                                         *pval++ = *pdata++;
1581                                 while (--data_len);
1582                         }
1583                         tegra_dsi_writel(dsi, val, DSI_WR_DATA);
1584                 }
1585         }
1586
1587         err = tegra_dsi_host_trigger(dsi);
1588         if (err < 0)
1589                 dev_err(&dsi->dc->ndev->dev, "DSI host trigger failed\n");
1590
1591         return err;
1592 }
1593
1594 int tegra_dsi_write_data(struct tegra_dc *dc,
1595                         struct tegra_dc_dsi_data *dsi,
1596                         u8 *pdata, u8 data_id, u16 data_len)
1597 {
1598         int err = 0;
1599         struct dsi_status *init_status;
1600
1601         tegra_dc_io_start(dc);
1602
1603         init_status = tegra_dsi_prepare_host_transmission(
1604                                 dc, dsi, DSI_LP_OP_WRITE);
1605         if (IS_ERR_OR_NULL(init_status)) {
1606                 err = PTR_ERR(init_status);
1607                 dev_err(&dc->ndev->dev, "DSI host config failed\n");
1608                 goto fail;
1609         }
1610
1611         err = _tegra_dsi_write_data(dsi, pdata, data_id, data_len);
1612 fail:
1613         err = tegra_dsi_restore_state(dc, dsi, init_status);
1614         if (err < 0)
1615                 dev_err(&dc->ndev->dev, "Failed to restore prev state\n");
1616         tegra_dc_io_end(dc);
1617         return err;
1618 }
1619 EXPORT_SYMBOL(tegra_dsi_write_data);
1620
1621 static int tegra_dsi_send_panel_cmd(struct tegra_dc *dc,
1622                                         struct tegra_dc_dsi_data *dsi,
1623                                         struct tegra_dsi_cmd *cmd,
1624                                         u32 n_cmd)
1625 {
1626         u32 i;
1627         int err;
1628
1629         err = 0;
1630         for (i = 0; i < n_cmd; i++) {
1631                 struct tegra_dsi_cmd *cur_cmd;
1632                 cur_cmd = &cmd[i];
1633
1634                 if (cur_cmd->cmd_type == TEGRA_DSI_DELAY_MS)
1635                         mdelay(cur_cmd->sp_len_dly.delay_ms);
1636                 else {
1637                         err = tegra_dsi_write_data(dc, dsi,
1638                                                 cur_cmd->pdata,
1639                                                 cur_cmd->data_id,
1640                                                 cur_cmd->sp_len_dly.data_len);
1641                         if (err < 0)
1642                                 break;
1643                 }
1644         }
1645         return err;
1646 }
1647
1648 static u8 get_8bit_ecc(u32 header)
1649 {
1650         char ecc_parity[24] = {
1651                 0x07, 0x0b, 0x0d, 0x0e, 0x13, 0x15, 0x16, 0x19,
1652                 0x1a, 0x1c, 0x23, 0x25, 0x26, 0x29, 0x2a, 0x2c,
1653                 0x31, 0x32, 0x34, 0x38, 0x1f, 0x2f, 0x37, 0x3b
1654         };
1655         u8 ecc_byte;
1656         int i;
1657
1658         ecc_byte = 0;
1659         for (i = 0; i < 24; i++)
1660                 ecc_byte ^= ((header >> i) & 1) ? ecc_parity[i] : 0x00;
1661
1662         return ecc_byte;
1663 }
1664
1665 /* This function is written to send DCS short write (1 parameter) only.
1666  * This means the cmd will contain only 1 byte of index and 1 byte of value.
1667  * The data type ID is fixed at 0x15 and the ECC is calculated based on the
1668  * data in pdata.
1669  * The command will be sent by hardware every frame.
1670  * pdata should contain both the index + value for each cmd.
1671  * data_len will be the total number of bytes in pdata.
1672  */
1673 int tegra_dsi_send_panel_short_cmd(struct tegra_dc *dc, u8 *pdata, u8 data_len)
1674 {
1675         u8 ecc8bits = 0, data_len_orig = 0;
1676         u32 val = 0, pkthdr = 0;
1677         int err = 0, count = 0;
1678         struct tegra_dc_dsi_data *dsi = tegra_dc_get_outdata(dc);
1679
1680         data_len_orig = data_len;
1681         if (pdata != NULL) {
1682                 while (data_len) {
1683                         if (data_len >= 2) {
1684                                 pkthdr = (CMD_SHORTW |
1685                                         (((u16 *)pdata)[0]) << 8 | 0x00 << 24);
1686                                 ecc8bits = get_8bit_ecc(pkthdr);
1687                                 val = (pkthdr | (ecc8bits << 24));
1688                                 data_len -= 2;
1689                                 pdata += 2;
1690                                 count++;
1691                         }
1692                         switch (count) {
1693                         case 1:
1694                                 tegra_dsi_writel(dsi, val, DSI_INIT_SEQ_DATA_0);
1695                                 break;
1696                         case 2:
1697                                 tegra_dsi_writel(dsi, val, DSI_INIT_SEQ_DATA_1);
1698                                 break;
1699                         case 3:
1700                                 tegra_dsi_writel(dsi, val, DSI_INIT_SEQ_DATA_2);
1701                                 break;
1702                         case 4:
1703                                 tegra_dsi_writel(dsi, val, DSI_INIT_SEQ_DATA_3);
1704                                 break;
1705                         case 5:
1706                                 tegra_dsi_writel(dsi, val, DSI_INIT_SEQ_DATA_4);
1707                                 break;
1708                         case 6:
1709                                 tegra_dsi_writel(dsi, val, DSI_INIT_SEQ_DATA_5);
1710                                 break;
1711                         case 7:
1712                                 tegra_dsi_writel(dsi, val, DSI_INIT_SEQ_DATA_6);
1713                                 break;
1714                         case 8:
1715                                 tegra_dsi_writel(dsi, val, DSI_INIT_SEQ_DATA_7);
1716                                 break;
1717                         default:
1718                                 err = 1;
1719                                 break;
1720                         }
1721                 }
1722         }
1723
1724         val = DSI_INIT_SEQ_CONTROL_DSI_FRAME_INIT_BYTE_COUNT(data_len_orig * 2)
1725                 | DSI_INIT_SEQ_CONTROL_DSI_SEND_INIT_SEQUENCE(1);
1726         tegra_dsi_writel(dsi, val, DSI_INIT_SEQ_CONTROL);
1727
1728         return err;
1729 }
1730 EXPORT_SYMBOL(tegra_dsi_send_panel_short_cmd);
1731
1732 static int tegra_dsi_bta(struct tegra_dc_dsi_data *dsi)
1733 {
1734         u32 val;
1735         u32 poll_time;
1736         int err;
1737
1738         poll_time = 0;
1739         err = 0;
1740
1741         val = tegra_dsi_readl(dsi, DSI_HOST_DSI_CONTROL);
1742         val |= DSI_HOST_DSI_CONTROL_IMM_BTA(TEGRA_DSI_ENABLE);
1743         tegra_dsi_writel(dsi, val, DSI_HOST_DSI_CONTROL);
1744
1745 #if DSI_USE_SYNC_POINTS
1746         /* FIXME: Workaround for nvhost_syncpt_read */
1747         dsi->syncpt_val = nvhost_syncpt_update_min(
1748                         &nvhost_get_host(dsi->dc->ndev)->syncpt,
1749                         dsi->syncpt_id);
1750
1751         val = DSI_INCR_SYNCPT_COND(OP_DONE) |
1752                 DSI_INCR_SYNCPT_INDX(dsi->syncpt_id);
1753         tegra_dsi_writel(dsi, val, DSI_INCR_SYNCPT);
1754
1755         /* TODO: Use interrupt rather than polling */
1756         err = nvhost_syncpt_wait(&nvhost_get_host(dsi->dc->ndev)->syncpt,
1757                 dsi->syncpt_id, dsi->syncpt_val + 1);
1758         if (err < 0)
1759                 dev_err(&dsi->dc->ndev->dev,
1760                         "DSI sync point failure\n");
1761         else
1762                 (dsi->syncpt_val)++;
1763 #else
1764         if (tegra_dsi_read_busy(dsi)) {
1765                 err = -EBUSY;
1766                 dev_err(&dsi->dc->ndev->dev,
1767                         "Timeout wating on read completion\n");
1768         }
1769 #endif
1770
1771         return err;
1772 }
1773
1774 static int tegra_dsi_parse_read_response(struct tegra_dc *dc,
1775                                         u32 rd_fifo_cnt, u8 *read_fifo)
1776 {
1777         int err;
1778         u32 payload_size;
1779
1780         payload_size = 0;
1781         err = 0;
1782
1783         switch (read_fifo[0]) {
1784         case DSI_ESCAPE_CMD:
1785                 dev_info(&dc->ndev->dev, "escape cmd[0x%x]\n", read_fifo[0]);
1786                 break;
1787         case DSI_ACK_NO_ERR:
1788                 dev_info(&dc->ndev->dev,
1789                         "Panel ack, no err[0x%x]\n", read_fifo[0]);
1790                 return err;
1791         default:
1792                 dev_info(&dc->ndev->dev, "Invalid read response\n");
1793                 break;
1794         }
1795
1796         switch (read_fifo[4] & 0xff) {
1797         case GEN_LONG_RD_RES:
1798                 /* Fall through */
1799         case DCS_LONG_RD_RES:
1800                 payload_size = (read_fifo[5] |
1801                                 (read_fifo[6] << 8)) & 0xFFFF;
1802                 dev_info(&dc->ndev->dev, "Long read response Packet\n"
1803                                 "payload_size[0x%x]\n", payload_size);
1804                 break;
1805         case GEN_1_BYTE_SHORT_RD_RES:
1806                 /* Fall through */
1807         case DCS_1_BYTE_SHORT_RD_RES:
1808                 payload_size = 1;
1809                 dev_info(&dc->ndev->dev, "Short read response Packet\n"
1810                         "payload_size[0x%x]\n", payload_size);
1811                 break;
1812         case GEN_2_BYTE_SHORT_RD_RES:
1813                 /* Fall through */
1814         case DCS_2_BYTE_SHORT_RD_RES:
1815                 payload_size = 2;
1816                 dev_info(&dc->ndev->dev, "Short read response Packet\n"
1817                         "payload_size[0x%x]\n", payload_size);
1818                 break;
1819         case ACK_ERR_RES:
1820                 payload_size = 2;
1821                 dev_info(&dc->ndev->dev, "Acknowledge error report response\n"
1822                         "Packet payload_size[0x%x]\n", payload_size);
1823                 break;
1824         default:
1825                 dev_info(&dc->ndev->dev, "Invalid response packet\n");
1826                 err = -EINVAL;
1827                 break;
1828         }
1829         return err;
1830 }
1831
1832 static int tegra_dsi_read_fifo(struct tegra_dc *dc,
1833                         struct tegra_dc_dsi_data *dsi,
1834                         u8 *read_fifo)
1835 {
1836         u32 val;
1837         u32 i;
1838         u32 poll_time = 0;
1839         u32 rd_fifo_cnt;
1840         int err = 0;
1841         u8 *read_fifo_cp = read_fifo;
1842
1843         while (poll_time <  DSI_DELAY_FOR_READ_FIFO) {
1844                 mdelay(1);
1845                 val = tegra_dsi_readl(dsi, DSI_STATUS);
1846                 rd_fifo_cnt = val & DSI_STATUS_RD_FIFO_COUNT(0x1f);
1847                 if (rd_fifo_cnt << 2 > DSI_READ_FIFO_DEPTH)
1848                         dev_err(&dc->ndev->dev,
1849                         "DSI RD_FIFO_CNT is greater than RD_FIFO_DEPTH\n");
1850                         break;
1851                 poll_time++;
1852         }
1853
1854         if (rd_fifo_cnt == 0) {
1855                 dev_info(&dc->ndev->dev,
1856                         "DSI RD_FIFO_CNT is zero\n");
1857                 err = -EINVAL;
1858                 goto fail;
1859         }
1860
1861         if (val & (DSI_STATUS_LB_UNDERFLOW(0x1) |
1862                 DSI_STATUS_LB_OVERFLOW(0x1))) {
1863                 dev_warn(&dc->ndev->dev,
1864                         "DSI overflow/underflow error\n");
1865         }
1866
1867         /* Read data from FIFO */
1868         for (i = 0; i < rd_fifo_cnt; i++) {
1869                 val = tegra_dsi_readl(dsi, DSI_RD_DATA);
1870                 if (enable_read_debug)
1871                         dev_info(&dc->ndev->dev,
1872                         "Read data[%d]: 0x%x\n", i, val);
1873                 memcpy(read_fifo, &val, 4);
1874                 read_fifo += 4;
1875         }
1876
1877         /* Make sure all the data is read from the FIFO */
1878         val = tegra_dsi_readl(dsi, DSI_STATUS);
1879         val &= DSI_STATUS_RD_FIFO_COUNT(0x1f);
1880         if (val)
1881                 dev_err(&dc->ndev->dev, "DSI FIFO_RD_CNT not zero"
1882                 " even after reading FIFO_RD_CNT words from read fifo\n");
1883
1884         if (enable_read_debug) {
1885                 err =
1886                 tegra_dsi_parse_read_response(dc, rd_fifo_cnt, read_fifo_cp);
1887                 if (err < 0)
1888                         dev_warn(&dc->ndev->dev, "Unexpected read data\n");
1889         }
1890 fail:
1891         return err;
1892 }
1893
1894 int tegra_dsi_read_data(struct tegra_dc *dc,
1895                                 struct tegra_dc_dsi_data *dsi,
1896                                 u32 max_ret_payload_size,
1897                                 u32 panel_reg_addr, u8 *read_data)
1898 {
1899         int err = 0;
1900         struct dsi_status *init_status;
1901
1902         tegra_dc_io_start(dc);
1903
1904         init_status = tegra_dsi_prepare_host_transmission(
1905                                 dc, dsi, DSI_LP_OP_WRITE);
1906         if (IS_ERR_OR_NULL(init_status)) {
1907                 err = PTR_ERR(init_status);
1908                 dev_err(&dc->ndev->dev, "DSI host config failed\n");
1909                 goto fail;
1910         }
1911
1912         /* Set max return payload size in words */
1913         err = _tegra_dsi_write_data(dsi, NULL,
1914                 dsi_command_max_return_pkt_size,
1915                 max_ret_payload_size);
1916         if (err < 0) {
1917                 dev_err(&dc->ndev->dev,
1918                                 "DSI write failed\n");
1919                 goto fail;
1920         }
1921
1922         /* DCS to read given panel register */
1923         err = _tegra_dsi_write_data(dsi, NULL,
1924                 dsi_command_dcs_read_with_no_params,
1925                 panel_reg_addr);
1926         if (err < 0) {
1927                 dev_err(&dc->ndev->dev,
1928                                 "DSI write failed\n");
1929                 goto fail;
1930         }
1931
1932         tegra_dsi_reset_read_count(dsi);
1933
1934         if (dsi->status.lp_op == DSI_LP_OP_WRITE) {
1935                 err = tegra_dsi_set_to_lp_mode(dc, dsi, DSI_LP_OP_READ);
1936                 if (err < 0) {
1937                         dev_err(&dc->ndev->dev,
1938                         "DSI failed to go to LP read mode\n");
1939                         goto fail;
1940                 }
1941         }
1942
1943         err = tegra_dsi_bta(dsi);
1944         if (err < 0) {
1945                 dev_err(&dc->ndev->dev,
1946                         "DSI IMM BTA timeout\n");
1947                 goto fail;
1948         }
1949
1950         err = tegra_dsi_read_fifo(dc, dsi, read_data);
1951         if (err < 0) {
1952                 dev_err(&dc->ndev->dev, "DSI read fifo failure\n");
1953                 goto fail;
1954         }
1955 fail:
1956         err = tegra_dsi_restore_state(dc, dsi, init_status);
1957         if (err < 0)
1958                 dev_err(&dc->ndev->dev, "Failed to restore prev state\n");
1959         tegra_dc_io_end(dc);
1960         return err;
1961 }
1962 EXPORT_SYMBOL(tegra_dsi_read_data);
1963
1964 int tegra_dsi_panel_sanity_check(struct tegra_dc *dc,
1965                                 struct tegra_dc_dsi_data *dsi)
1966 {
1967         int err = 0;
1968         u8 read_fifo[DSI_READ_FIFO_DEPTH];
1969         struct dsi_status *init_status;
1970         static struct tegra_dsi_cmd dsi_nop_cmd =
1971                         DSI_CMD_SHORT(0x05, 0x0, 0x0);
1972
1973         tegra_dc_io_start(dc);
1974
1975         init_status = tegra_dsi_prepare_host_transmission(
1976                                         dc, dsi, DSI_LP_OP_WRITE);
1977         if (IS_ERR_OR_NULL(init_status)) {
1978                 err = PTR_ERR(init_status);
1979                 dev_err(&dc->ndev->dev, "DSI host config failed\n");
1980                 goto fail;
1981         }
1982
1983         err = _tegra_dsi_write_data(dsi, NULL, dsi_nop_cmd.data_id, 0x0);
1984         if (err < 0) {
1985                 dev_err(&dc->ndev->dev, "DSI nop write failed\n");
1986                 goto fail;
1987         }
1988
1989         tegra_dsi_reset_read_count(dsi);
1990
1991         if (dsi->status.lp_op == DSI_LP_OP_WRITE) {
1992                 err = tegra_dsi_set_to_lp_mode(dc, dsi, DSI_LP_OP_READ);
1993                 if (err < 0) {
1994                         dev_err(&dc->ndev->dev,
1995                         "DSI failed to go to LP read mode\n");
1996                         goto fail;
1997                 }
1998         }
1999
2000         err = tegra_dsi_bta(dsi);
2001         if (err < 0) {
2002                 dev_err(&dc->ndev->dev, "DSI BTA failed\n");
2003                 goto fail;
2004         }
2005
2006         err = tegra_dsi_read_fifo(dc, dsi, read_fifo);
2007         if (err < 0) {
2008                 dev_err(&dc->ndev->dev, "DSI read fifo failure\n");
2009                 goto fail;
2010         }
2011
2012         if (read_fifo[0] != DSI_ACK_NO_ERR) {
2013                 dev_warn(&dc->ndev->dev,
2014                         "Ack no error trigger message not received\n");
2015                 err = -EAGAIN;
2016         }
2017 fail:
2018         err = tegra_dsi_restore_state(dc, dsi, init_status);
2019         if (err < 0)
2020                 dev_err(&dc->ndev->dev, "Failed to restore prev state\n");
2021         tegra_dc_io_end(dc);
2022         return err;
2023 }
2024 EXPORT_SYMBOL(tegra_dsi_panel_sanity_check);
2025
2026 static int tegra_dsi_enter_ulpm(struct tegra_dc_dsi_data *dsi)
2027 {
2028         u32 val;
2029         int ret;
2030
2031         ret = 0;
2032
2033         val = tegra_dsi_readl(dsi, DSI_HOST_DSI_CONTROL);
2034         val &= ~DSI_HOST_DSI_CONTROL_ULTRA_LOW_POWER(3);
2035         val |= DSI_HOST_DSI_CONTROL_ULTRA_LOW_POWER(ENTER_ULPM);
2036         tegra_dsi_writel(dsi, val, DSI_HOST_DSI_CONTROL);
2037
2038 #if DSI_USE_SYNC_POINTS
2039         ret = tegra_dsi_syncpt(dsi);
2040         if (ret < 0) {
2041                 dev_err(&dsi->dc->ndev->dev,
2042                         "DSI syncpt for ulpm enter failed\n");
2043                 goto fail;
2044         }
2045 #else
2046         /* TODO: Find exact delay required */
2047         mdelay(10);
2048 #endif
2049         dsi->ulpm = true;
2050 fail:
2051         return ret;
2052 }
2053
2054 static int tegra_dsi_exit_ulpm(struct tegra_dc_dsi_data *dsi)
2055 {
2056         u32 val;
2057         int ret;
2058
2059         ret = 0;
2060
2061         val = tegra_dsi_readl(dsi, DSI_HOST_DSI_CONTROL);
2062         val &= ~DSI_HOST_DSI_CONTROL_ULTRA_LOW_POWER(3);
2063         val |= DSI_HOST_DSI_CONTROL_ULTRA_LOW_POWER(EXIT_ULPM);
2064         tegra_dsi_writel(dsi, val, DSI_HOST_DSI_CONTROL);
2065
2066 #if DSI_USE_SYNC_POINTS
2067         ret = tegra_dsi_syncpt(dsi);
2068         if (ret < 0) {
2069                 dev_err(&dsi->dc->ndev->dev,
2070                         "DSI syncpt for ulpm exit failed\n");
2071                 goto fail;
2072         }
2073 #else
2074         /* TODO: Find exact delay required */
2075         mdelay(10);
2076 #endif
2077         dsi->ulpm = false;
2078
2079         val = tegra_dsi_readl(dsi, DSI_HOST_DSI_CONTROL);
2080         val &= ~DSI_HOST_DSI_CONTROL_ULTRA_LOW_POWER(0x3);
2081         val |= DSI_HOST_DSI_CONTROL_ULTRA_LOW_POWER(NORMAL);
2082         tegra_dsi_writel(dsi, val, DSI_HOST_DSI_CONTROL);
2083 fail:
2084         return ret;
2085
2086 }
2087
2088 static void tegra_dc_dsi_enable(struct tegra_dc *dc)
2089 {
2090         struct tegra_dc_dsi_data *dsi = tegra_dc_get_outdata(dc);
2091         int err;
2092         u32 val;
2093
2094         tegra_dc_io_start(dc);
2095         mutex_lock(&dsi->lock);
2096
2097         /* Stop DC stream before configuring DSI registers
2098          * to avoid visible glitches on panel during transition
2099          * from bootloader to kernel driver
2100          */
2101         tegra_dsi_stop_dc_stream(dc, dsi);
2102
2103         if (dsi->enabled) {
2104                 if (dsi->ulpm) {
2105                         if (tegra_dsi_exit_ulpm(dsi) < 0) {
2106                                 dev_err(&dc->ndev->dev,
2107                                         "DSI failed to exit ulpm\n");
2108                                 goto fail;
2109                         }
2110                 }
2111
2112                 if (dsi->info.panel_reset) {
2113                         err = tegra_dsi_send_panel_cmd(dc, dsi,
2114                                                         dsi->info.dsi_init_cmd,
2115                                                         dsi->info.n_init_cmd);
2116                         if (err < 0) {
2117                                 dev_err(&dc->ndev->dev,
2118                                 "dsi: error sending dsi init cmd\n");
2119                                 goto fail;
2120                         }
2121                 } else if (dsi->info.dsi_late_resume_cmd) {
2122                         err = tegra_dsi_send_panel_cmd(dc, dsi,
2123                                                 dsi->info.dsi_late_resume_cmd,
2124                                                 dsi->info.n_late_resume_cmd);
2125                         if (err < 0) {
2126                                 dev_err(&dc->ndev->dev,
2127                                 "dsi: error sending late resume cmd\n");
2128                                 goto fail;
2129                         }
2130                 }
2131         } else {
2132                 err = tegra_dsi_init_hw(dc, dsi);
2133                 if (err < 0) {
2134                         dev_err(&dc->ndev->dev,
2135                                 "dsi: not able to init dsi hardware\n");
2136                         goto fail;
2137                 }
2138
2139                 if (dsi->ulpm) {
2140                         if (tegra_dsi_enter_ulpm(dsi) < 0) {
2141                                 dev_err(&dc->ndev->dev,
2142                                         "DSI failed to enter ulpm\n");
2143                                 goto fail;
2144                         }
2145                         val = DSI_PAD_CONTROL_PAD_PDIO(0) |
2146                                 DSI_PAD_CONTROL_PAD_PDIO_CLK(0) |
2147                                 DSI_PAD_CONTROL_PAD_PULLDN_ENAB
2148                                                 (TEGRA_DSI_DISABLE);
2149                         tegra_dsi_writel(dsi, val, DSI_PAD_CONTROL);
2150                         if (tegra_dsi_exit_ulpm(dsi) < 0) {
2151                                 dev_err(&dc->ndev->dev,
2152                                         "DSI failed to exit ulpm\n");
2153                                 goto fail;
2154                         }
2155                 }
2156
2157                 err = tegra_dsi_set_to_lp_mode(dc, dsi, DSI_LP_OP_WRITE);
2158                 if (err < 0) {
2159                         dev_err(&dc->ndev->dev,
2160                                 "dsi: not able to set to lp mode\n");
2161                         goto fail;
2162                 }
2163
2164                 err = tegra_dsi_send_panel_cmd(dc, dsi, dsi->info.dsi_init_cmd,
2165                                                 dsi->info.n_init_cmd);
2166                 if (err < 0) {
2167                         dev_err(&dc->ndev->dev,
2168                                 "dsi: error while sending dsi init cmd\n");
2169                         goto fail;
2170                 }
2171
2172                 err = tegra_dsi_set_to_hs_mode(dc, dsi);
2173                 if (err < 0) {
2174                         dev_err(&dc->ndev->dev,
2175                                 "dsi: not able to set to hs mode\n");
2176                         goto fail;
2177                 }
2178
2179                 dsi->enabled = true;
2180         }
2181
2182         if (dsi->status.driven == DSI_DRIVEN_MODE_DC)
2183                 tegra_dsi_start_dc_stream(dc, dsi);
2184 fail:
2185         mutex_unlock(&dsi->lock);
2186         tegra_dc_io_end(dc);
2187 }
2188
2189 static void _tegra_dc_dsi_init(struct tegra_dc *dc)
2190 {
2191         struct tegra_dc_dsi_data *dsi = tegra_dc_get_outdata(dc);
2192
2193         tegra_dsi_init_sw(dc, dsi);
2194         /* TODO: Configure the CSI pad configuration */
2195 }
2196
2197 static int tegra_dc_dsi_cp_p_cmd(struct tegra_dsi_cmd *src,
2198                                         struct tegra_dsi_cmd *dst, u16 n_cmd)
2199 {
2200         u16 i;
2201         u16 len;
2202
2203         memcpy(dst, src, sizeof(*dst) * n_cmd);
2204
2205         for (i = 0; i < n_cmd; i++)
2206                 if (src[i].pdata) {
2207                         len = sizeof(*src[i].pdata) *
2208                                         src[i].sp_len_dly.data_len;
2209                         dst[i].pdata = kzalloc(len, GFP_KERNEL);
2210                         if (!dst[i].pdata)
2211                                 goto free_cmd_pdata;
2212                         memcpy(dst[i].pdata, src[i].pdata, len);
2213                 }
2214
2215         return 0;
2216
2217 free_cmd_pdata:
2218         for (--i; i >= 0; i--)
2219                 if (dst[i].pdata)
2220                         kfree(dst[i].pdata);
2221         return -ENOMEM;
2222 }
2223
2224 static int tegra_dc_dsi_cp_info(struct tegra_dc_dsi_data *dsi,
2225                                         struct tegra_dsi_out *p_dsi)
2226 {
2227         struct tegra_dsi_cmd *p_init_cmd;
2228         struct tegra_dsi_cmd *p_early_suspend_cmd;
2229         struct tegra_dsi_cmd *p_late_resume_cmd;
2230         struct tegra_dsi_cmd *p_suspend_cmd;
2231         int err;
2232
2233         if (p_dsi->n_data_lanes > MAX_DSI_DATA_LANES)
2234                 return -EINVAL;
2235
2236         p_init_cmd = kzalloc(sizeof(*p_init_cmd) *
2237                                 p_dsi->n_init_cmd, GFP_KERNEL);
2238         if (!p_init_cmd)
2239                 return -ENOMEM;
2240
2241         if (p_dsi->dsi_early_suspend_cmd) {
2242                 p_early_suspend_cmd = kzalloc(sizeof(*p_early_suspend_cmd) *
2243                                         p_dsi->n_early_suspend_cmd,
2244                                         GFP_KERNEL);
2245                 if (!p_early_suspend_cmd) {
2246                         err = -ENOMEM;
2247                         goto err_free_init_cmd;
2248                 }
2249         }
2250
2251         if (p_dsi->dsi_late_resume_cmd) {
2252                 p_late_resume_cmd = kzalloc(sizeof(*p_late_resume_cmd) *
2253                                         p_dsi->n_late_resume_cmd,
2254                                         GFP_KERNEL);
2255                 if (!p_late_resume_cmd) {
2256                         err = -ENOMEM;
2257                         goto err_free_p_early_suspend_cmd;
2258                 }
2259         }
2260
2261         p_suspend_cmd = kzalloc(sizeof(*p_suspend_cmd) * p_dsi->n_suspend_cmd,
2262                                 GFP_KERNEL);
2263         if (!p_suspend_cmd) {
2264                 err = -ENOMEM;
2265                 goto err_free_p_late_resume_cmd;
2266         }
2267
2268         memcpy(&dsi->info, p_dsi, sizeof(dsi->info));
2269
2270         /* Copy panel init cmd */
2271         err = tegra_dc_dsi_cp_p_cmd(p_dsi->dsi_init_cmd,
2272                                                 p_init_cmd, p_dsi->n_init_cmd);
2273         if (err < 0)
2274                 goto err_free;
2275         dsi->info.dsi_init_cmd = p_init_cmd;
2276
2277         /* Copy panel early suspend cmd */
2278         if (p_dsi->dsi_early_suspend_cmd) {
2279                 err = tegra_dc_dsi_cp_p_cmd(p_dsi->dsi_early_suspend_cmd,
2280                                         p_early_suspend_cmd,
2281                                         p_dsi->n_early_suspend_cmd);
2282                 if (err < 0)
2283                         goto err_free;
2284                 dsi->info.dsi_early_suspend_cmd = p_early_suspend_cmd;
2285         }
2286
2287         /* Copy panel late resume cmd */
2288         if (p_dsi->dsi_late_resume_cmd) {
2289                 err = tegra_dc_dsi_cp_p_cmd(p_dsi->dsi_late_resume_cmd,
2290                                                 p_late_resume_cmd,
2291                                                 p_dsi->n_late_resume_cmd);
2292                 if (err < 0)
2293                         goto err_free;
2294                 dsi->info.dsi_late_resume_cmd = p_late_resume_cmd;
2295         }
2296
2297         /* Copy panel suspend cmd */
2298         err = tegra_dc_dsi_cp_p_cmd(p_dsi->dsi_suspend_cmd, p_suspend_cmd,
2299                                         p_dsi->n_suspend_cmd);
2300         if (err < 0)
2301                 goto err_free;
2302         dsi->info.dsi_suspend_cmd = p_suspend_cmd;
2303
2304         if (!dsi->info.panel_reset_timeout_msec)
2305                 dsi->info.panel_reset_timeout_msec =
2306                                                 DEFAULT_PANEL_RESET_TIMEOUT;
2307
2308         if (!dsi->info.panel_buffer_size_byte)
2309                 dsi->info.panel_buffer_size_byte = DEFAULT_PANEL_BUFFER_BYTE;
2310
2311         if (!dsi->info.max_panel_freq_khz) {
2312                 dsi->info.max_panel_freq_khz = DEFAULT_MAX_DSI_PHY_CLK_KHZ;
2313
2314                 if (dsi->info.video_burst_mode >
2315                                 TEGRA_DSI_VIDEO_NONE_BURST_MODE_WITH_SYNC_END){
2316                         dev_err(&dsi->dc->ndev->dev, "DSI: max_panel_freq_khz"
2317                                         "is not set for DSI burst mode.\n");
2318                         dsi->info.video_burst_mode =
2319                                 TEGRA_DSI_VIDEO_BURST_MODE_LOWEST_SPEED;
2320                 }
2321         }
2322
2323         if (!dsi->info.lp_cmd_mode_freq_khz)
2324                 dsi->info.lp_cmd_mode_freq_khz = DEFAULT_LP_CMD_MODE_CLK_KHZ;
2325
2326         if (!dsi->info.chip_id || !dsi->info.chip_rev)
2327                 dev_warn(&dsi->dc->ndev->dev,
2328                         "DSI: Failed to get chip info\n");
2329
2330         if (!dsi->info.lp_read_cmd_mode_freq_khz)
2331                 dsi->info.lp_read_cmd_mode_freq_khz =
2332                         dsi->info.lp_cmd_mode_freq_khz;
2333
2334         /* host mode is for testing only */
2335         dsi->driven_mode = TEGRA_DSI_DRIVEN_BY_DC;
2336         return 0;
2337
2338 err_free:
2339         kfree(p_suspend_cmd);
2340 err_free_p_late_resume_cmd:
2341         kfree(p_late_resume_cmd);
2342 err_free_p_early_suspend_cmd:
2343         kfree(p_early_suspend_cmd);
2344 err_free_init_cmd:
2345         kfree(p_init_cmd);
2346         return err;
2347 }
2348
2349 static int tegra_dc_dsi_init(struct tegra_dc *dc)
2350 {
2351         struct tegra_dc_dsi_data *dsi;
2352         struct resource *res;
2353         struct resource *base_res;
2354         void __iomem *base;
2355         struct clk *dc_clk = NULL;
2356         struct clk *dsi_clk = NULL;
2357         struct tegra_dsi_out *dsi_pdata;
2358         int err;
2359
2360         err = 0;
2361
2362         dsi = kzalloc(sizeof(*dsi), GFP_KERNEL);
2363         if (!dsi)
2364                 return -ENOMEM;
2365
2366         res = nvhost_get_resource_byname(dc->ndev, IORESOURCE_MEM,
2367                                         "dsi_regs");
2368         if (!res) {
2369                 dev_err(&dc->ndev->dev, "dsi: no mem resource\n");
2370                 err = -ENOENT;
2371                 goto err_free_dsi;
2372         }
2373
2374         base_res = request_mem_region(res->start, resource_size(res),
2375                                 dc->ndev->name);
2376         if (!base_res) {
2377                 dev_err(&dc->ndev->dev, "dsi: request_mem_region failed\n");
2378                 err = -EBUSY;
2379                 goto err_free_dsi;
2380         }
2381
2382         base = ioremap(res->start, resource_size(res));
2383         if (!base) {
2384                 dev_err(&dc->ndev->dev, "dsi: registers can't be mapped\n");
2385                 err = -EBUSY;
2386                 goto err_release_regs;
2387         }
2388
2389         dsi_pdata = dc->pdata->default_out->dsi;
2390         if (!dsi_pdata) {
2391                 dev_err(&dc->ndev->dev, "dsi: dsi data not available\n");
2392                 goto err_release_regs;
2393         }
2394
2395         if (dsi_pdata->dsi_instance)
2396                 dsi_clk = clk_get(&dc->ndev->dev, "dsib");
2397         else
2398                 dsi_clk = clk_get(&dc->ndev->dev, "dsia");
2399
2400         if (IS_ERR_OR_NULL(dsi_clk)) {
2401                 dev_err(&dc->ndev->dev, "dsi: can't get clock\n");
2402                 err = -EBUSY;
2403                 goto err_release_regs;
2404         }
2405
2406         dc_clk = clk_get_sys(dev_name(&dc->ndev->dev), NULL);
2407         if (IS_ERR_OR_NULL(dc_clk)) {
2408                 dev_err(&dc->ndev->dev, "dsi: dc clock %s unavailable\n",
2409                         dev_name(&dc->ndev->dev));
2410                 err = -EBUSY;
2411                 goto err_clk_put;
2412         }
2413
2414         mutex_init(&dsi->lock);
2415         dsi->dc = dc;
2416         dsi->base = base;
2417         dsi->base_res = base_res;
2418         dsi->dc_clk = dc_clk;
2419         dsi->dsi_clk = dsi_clk;
2420
2421         err = tegra_dc_dsi_cp_info(dsi, dsi_pdata);
2422         if (err < 0)
2423                 goto err_dsi_data;
2424
2425         tegra_dc_set_outdata(dc, dsi);
2426         _tegra_dc_dsi_init(dc);
2427
2428         return 0;
2429
2430 err_dsi_data:
2431 err_clk_put:
2432         clk_put(dsi_clk);
2433 err_release_regs:
2434         release_resource(base_res);
2435 err_free_dsi:
2436         kfree(dsi);
2437
2438         return err;
2439 }
2440
2441 static void tegra_dc_dsi_destroy(struct tegra_dc *dc)
2442 {
2443         struct tegra_dc_dsi_data *dsi = tegra_dc_get_outdata(dc);
2444         u16 i;
2445         u32 val;
2446
2447         mutex_lock(&dsi->lock);
2448
2449         /* free up the pdata */
2450         for (i = 0; i < dsi->info.n_init_cmd; i++) {
2451                 if (dsi->info.dsi_init_cmd[i].pdata)
2452                         kfree(dsi->info.dsi_init_cmd[i].pdata);
2453         }
2454         kfree(dsi->info.dsi_init_cmd);
2455
2456         /* Disable dc stream */
2457         if (dsi->status.dc_stream == DSI_DC_STREAM_ENABLE)
2458                 tegra_dsi_stop_dc_stream_at_frame_end(dc, dsi);
2459
2460         /* Disable dsi phy clock */
2461         if (dsi->status.clk_out == DSI_PHYCLK_OUT_EN)
2462                 tegra_dsi_hs_clk_out_disable(dc, dsi);
2463
2464         val = DSI_POWER_CONTROL_LEG_DSI_ENABLE(TEGRA_DSI_DISABLE);
2465         tegra_dsi_writel(dsi, val, DSI_POWER_CONTROL);
2466
2467         iounmap(dsi->base);
2468         release_resource(dsi->base_res);
2469
2470         clk_put(dsi->dc_clk);
2471         clk_put(dsi->dsi_clk);
2472
2473         mutex_unlock(&dsi->lock);
2474
2475         mutex_destroy(&dsi->lock);
2476         kfree(dsi);
2477 }
2478
2479 static int tegra_dsi_deep_sleep(struct tegra_dc *dc,
2480                                 struct tegra_dc_dsi_data *dsi)
2481 {
2482         int err = 0;
2483         int val;
2484         struct clk *parent_clk = NULL;
2485         struct clk *base_clk = NULL;
2486
2487         if (!dsi->enabled) {
2488                 err = -EPERM;
2489                 goto fail;
2490         }
2491
2492         err = tegra_dsi_set_to_lp_mode(dc, dsi, DSI_LP_OP_WRITE);
2493         if (err < 0) {
2494                 dev_err(&dc->ndev->dev,
2495                 "DSI failed to go to LP mode\n");
2496                 goto fail;
2497         }
2498
2499         /* Suspend panel */
2500         err = tegra_dsi_send_panel_cmd(dc, dsi,
2501                         dsi->info.dsi_suspend_cmd,
2502                         dsi->info.n_suspend_cmd);
2503         if (err < 0) {
2504                 dev_err(&dc->ndev->dev,
2505                         "dsi: Error sending suspend cmd\n");
2506                 goto fail;
2507         }
2508
2509         if (!dsi->ulpm) {
2510                 err = tegra_dsi_enter_ulpm(dsi);
2511                 if (err < 0) {
2512                         dev_err(&dc->ndev->dev,
2513                                 "DSI failed to enter ulpm\n");
2514                         goto fail;
2515                 }
2516         }
2517
2518         /* Suspend pad */
2519         val = tegra_dsi_readl(dsi, DSI_PAD_CONTROL);
2520         val = DSI_PAD_CONTROL_PAD_PDIO(0x3) |
2521                 DSI_PAD_CONTROL_PAD_PDIO_CLK(0x1) |
2522                 DSI_PAD_CONTROL_PAD_PULLDN_ENAB(TEGRA_DSI_ENABLE);
2523         tegra_dsi_writel(dsi, val, DSI_PAD_CONTROL);
2524
2525         /* Suspend core-logic */
2526         val = DSI_POWER_CONTROL_LEG_DSI_ENABLE(TEGRA_DSI_DISABLE);
2527         tegra_dsi_writel(dsi, val, DSI_POWER_CONTROL);
2528
2529         /* Disable dsi fast and slow clock */
2530         parent_clk = clk_get_parent(dsi->dsi_clk);
2531         base_clk = clk_get_parent(parent_clk);
2532         if (dsi->info.dsi_instance)
2533                 tegra_clk_cfg_ex(base_clk,
2534                                 TEGRA_CLK_PLLD_CSI_OUT_ENB,
2535                                 0);
2536         else
2537                 tegra_clk_cfg_ex(base_clk,
2538                                 TEGRA_CLK_PLLD_DSI_OUT_ENB,
2539                                 0);
2540
2541         /* Disable dsi source clock */
2542         clk_disable(dsi->dsi_clk);
2543
2544         dsi->clk_ref = false;
2545         dsi->enabled = false;
2546
2547         return 0;
2548 fail:
2549         return err;
2550 }
2551
2552 static void tegra_dc_dsi_disable(struct tegra_dc *dc)
2553 {
2554         int err;
2555         struct tegra_dc_dsi_data *dsi = tegra_dc_get_outdata(dc);
2556
2557         tegra_dc_io_start(dc);
2558         mutex_lock(&dsi->lock);
2559
2560         if (dsi->status.dc_stream == DSI_DC_STREAM_ENABLE)
2561                 tegra_dsi_stop_dc_stream_at_frame_end(dc, dsi);
2562
2563         if (dsi->info.power_saving_suspend) {
2564                 if (tegra_dsi_deep_sleep(dc, dsi) < 0) {
2565                         dev_err(&dc->ndev->dev,
2566                                 "DSI failed to enter deep sleep\n");
2567                         goto fail;
2568                 }
2569         } else {
2570                 if (dsi->info.dsi_early_suspend_cmd) {
2571                         err = tegra_dsi_send_panel_cmd(dc, dsi,
2572                                 dsi->info.dsi_early_suspend_cmd,
2573                                 dsi->info.n_early_suspend_cmd);
2574                         if (err < 0) {
2575                                 dev_err(&dc->ndev->dev,
2576                                 "dsi: Error sending early suspend cmd\n");
2577                                 goto fail;
2578                         }
2579                 }
2580
2581                 if (!dsi->ulpm) {
2582                         if (tegra_dsi_enter_ulpm(dsi) < 0) {
2583                                 dev_err(&dc->ndev->dev,
2584                                         "DSI failed to enter ulpm\n");
2585                                 goto fail;
2586                         }
2587                 }
2588         }
2589
2590 fail:
2591         mutex_unlock(&dsi->lock);
2592         tegra_dc_io_end(dc);
2593 }
2594
2595 #ifdef CONFIG_PM
2596 static void tegra_dc_dsi_suspend(struct tegra_dc *dc)
2597 {
2598         struct tegra_dc_dsi_data *dsi;
2599
2600         dsi = tegra_dc_get_outdata(dc);
2601
2602         if (!dsi->enabled)
2603                 return;
2604
2605         tegra_dc_io_start(dc);
2606         mutex_lock(&dsi->lock);
2607
2608         if (!dsi->info.power_saving_suspend) {
2609                 if (dsi->ulpm) {
2610                         if (tegra_dsi_exit_ulpm(dsi) < 0) {
2611                                 dev_err(&dc->ndev->dev,
2612                                         "DSI failed to exit ulpm");
2613                                 goto fail;
2614                         }
2615                 }
2616
2617                 if (tegra_dsi_deep_sleep(dc, dsi) < 0) {
2618                         dev_err(&dc->ndev->dev,
2619                                 "DSI failed to enter deep sleep\n");
2620                         goto fail;
2621                 }
2622         }
2623 fail:
2624         mutex_unlock(&dsi->lock);
2625         tegra_dc_io_end(dc);
2626 }
2627
2628 static void tegra_dc_dsi_resume(struct tegra_dc *dc)
2629 {
2630         /* Not required since tegra_dc_dsi_enable
2631          * will reconfigure the controller from scratch
2632          */
2633 }
2634 #endif
2635
2636 struct tegra_dc_out_ops tegra_dc_dsi_ops = {
2637         .init = tegra_dc_dsi_init,
2638         .destroy = tegra_dc_dsi_destroy,
2639         .enable = tegra_dc_dsi_enable,
2640         .disable = tegra_dc_dsi_disable,
2641 #ifdef CONFIG_PM
2642         .suspend = tegra_dc_dsi_suspend,
2643         .resume = tegra_dc_dsi_resume,
2644 #endif
2645 };