video: tegra: dsi: Reset DSI state during system booting.
[linux-2.6.git] / drivers / video / tegra / dc / dsi.c
1 /*
2  * drivers/video/tegra/dc/dsi.c
3  *
4  * Copyright (c) 2011, NVIDIA Corporation.
5  *
6  * This software is licensed under the terms of the GNU General Public
7  * License version 2, as published by the Free Software Foundation, and
8  * may be copied, distributed, and modified under those terms.
9  *
10  * This program is distributed in the hope that it will be useful,
11  * but WITHOUT ANY WARRANTY; without even the implied warranty of
12  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
13  * GNU General Public License for more details.
14  *
15  */
16
17 #include <linux/clk.h>
18 #include <linux/delay.h>
19 #include <linux/err.h>
20 #include <linux/fb.h>
21 #include <linux/gpio.h>
22 #include <linux/interrupt.h>
23 #include <linux/kernel.h>
24 #include <linux/slab.h>
25 #include <linux/spinlock.h>
26 #include <linux/workqueue.h>
27
28 #include <mach/clk.h>
29 #include <mach/dc.h>
30 #include <mach/fb.h>
31 #include <linux/nvhost.h>
32 #include <../gpio-names.h>
33
34 #include "dc_reg.h"
35 #include "dc_priv.h"
36 #include "dsi_regs.h"
37 #include "dsi.h"
38
39 #define DSI_USE_SYNC_POINTS 1
40
41 #define DSI_STOP_DC_DURATION_MSEC 1000
42
43 #define DSI_MODULE_NOT_INIT             0x0
44 #define DSI_MODULE_INIT                 0x1
45
46 #define DSI_LPHS_NOT_INIT               0x0
47 #define DSI_LPHS_IN_LP_MODE             0x1
48 #define DSI_LPHS_IN_HS_MODE             0x2
49
50 #define DSI_VIDEO_TYPE_NOT_INIT         0x0
51 #define DSI_VIDEO_TYPE_VIDEO_MODE       0x1
52 #define DSI_VIDEO_TYPE_CMD_MODE         0x2
53
54 #define DSI_DRIVEN_MODE_NOT_INIT        0x0
55 #define DSI_DRIVEN_MODE_DC              0x1
56 #define DSI_DRIVEN_MODE_HOST            0x2
57
58 #define DSI_PHYCLK_OUT_DIS              0x0
59 #define DSI_PHYCLK_OUT_EN               0x1
60
61 #define DSI_PHYCLK_NOT_INIT             0x0
62 #define DSI_PHYCLK_CONTINUOUS           0x1
63 #define DSI_PHYCLK_TX_ONLY              0x2
64
65 #define DSI_CLK_BURST_NOT_INIT          0x0
66 #define DSI_CLK_BURST_NONE_BURST        0x1
67 #define DSI_CLK_BURST_BURST_MODE        0x2
68
69 #define DSI_DC_STREAM_DISABLE           0x0
70 #define DSI_DC_STREAM_ENABLE            0x1
71
72 struct dsi_status {
73         unsigned        init:2;
74
75         unsigned        lphs:2;
76
77         unsigned        vtype:2;
78         unsigned        driven:2;
79
80         unsigned        clk_out:2;
81         unsigned        clk_mode:2;
82         unsigned        clk_burst:2;
83
84         unsigned        dc_stream:1;
85 };
86
87 /* source of video data */
88 enum{
89         TEGRA_DSI_DRIVEN_BY_DC,
90         TEGRA_DSI_DRIVEN_BY_HOST,
91 };
92
93 struct tegra_dc_dsi_data {
94         struct tegra_dc *dc;
95         void __iomem    *base;
96         struct resource *base_res;
97
98         struct clk              *dc_clk;
99         struct clk              *dsi_clk;
100         bool                    clk_ref;
101
102         struct mutex    lock;
103
104         /* data from board info */
105         struct tegra_dsi_out info;
106
107         struct dsi_status       status;
108
109         u8              driven_mode;
110         u8              controller_index;
111
112         u8              pixel_scaler_mul;
113         u8              pixel_scaler_div;
114
115         u32             default_shift_clk_div;
116         u32             default_pixel_clk_khz;
117         u32             default_hs_clk_khz;
118
119         u32             shift_clk_div;
120         u32             target_hs_clk_khz;
121         u32             target_lp_clk_khz;
122
123         u32             syncpt_id;
124         u32             syncpt_val;
125
126         u16             current_bit_clk_ns;
127         u32             current_dsi_clk_khz;
128
129         u32             dsi_control_val;
130
131         bool            ulpm;
132         bool            enabled;
133 };
134
135 const u32 dsi_pkt_seq_reg[NUMOF_PKT_SEQ] = {
136         DSI_PKT_SEQ_0_LO,
137         DSI_PKT_SEQ_0_HI,
138         DSI_PKT_SEQ_1_LO,
139         DSI_PKT_SEQ_1_HI,
140         DSI_PKT_SEQ_2_LO,
141         DSI_PKT_SEQ_2_HI,
142         DSI_PKT_SEQ_3_LO,
143         DSI_PKT_SEQ_3_HI,
144         DSI_PKT_SEQ_4_LO,
145         DSI_PKT_SEQ_4_HI,
146         DSI_PKT_SEQ_5_LO,
147         DSI_PKT_SEQ_5_HI,
148 };
149
150 const u32 dsi_pkt_seq_video_non_burst_syne[NUMOF_PKT_SEQ] = {
151         PKT_ID0(CMD_VS) | PKT_LEN0(0) | PKT_ID1(CMD_EOT) | PKT_LEN1(0) | PKT_LP,
152         0,
153         PKT_ID0(CMD_VE) | PKT_LEN0(0) | PKT_ID1(CMD_EOT) | PKT_LEN1(0) | PKT_LP,
154         0,
155         PKT_ID0(CMD_HS) | PKT_LEN0(0) | PKT_ID1(CMD_EOT) | PKT_LEN1(0) | PKT_LP,
156         0,
157         PKT_ID0(CMD_HS) | PKT_LEN0(0) | PKT_ID1(CMD_BLNK) | PKT_LEN1(1) |
158                 PKT_ID2(CMD_HE) | PKT_LEN2(0),
159         PKT_ID3(CMD_BLNK) | PKT_LEN3(2) | PKT_ID4(CMD_RGB) | PKT_LEN4(3) |
160                 PKT_ID5(CMD_BLNK) | PKT_LEN5(4),
161         PKT_ID0(CMD_HS) | PKT_LEN0(0) | PKT_ID1(CMD_EOT) | PKT_LEN1(0) | PKT_LP,
162         0,
163         PKT_ID0(CMD_HS) | PKT_LEN0(0) | PKT_ID1(CMD_BLNK) | PKT_LEN1(1) |
164                 PKT_ID2(CMD_HE) | PKT_LEN2(0),
165         PKT_ID3(CMD_BLNK) | PKT_LEN3(2) | PKT_ID4(CMD_RGB) | PKT_LEN4(3) |
166                 PKT_ID5(CMD_BLNK) | PKT_LEN5(4),
167 };
168
169 const u32 dsi_pkt_seq_video_non_burst[NUMOF_PKT_SEQ] = {
170         PKT_ID0(CMD_VS) | PKT_LEN0(0) | PKT_ID1(CMD_EOT) | PKT_LEN1(0) | PKT_LP,
171         0,
172         PKT_ID0(CMD_HS) | PKT_LEN0(0) | PKT_ID1(CMD_EOT) | PKT_LEN1(0) | PKT_LP,
173         0,
174         PKT_ID0(CMD_HS) | PKT_LEN0(0) | PKT_ID1(CMD_EOT) | PKT_LEN1(0) | PKT_LP,
175         0,
176         PKT_ID0(CMD_HS) | PKT_LEN0(0) | PKT_ID1(CMD_BLNK) | PKT_LEN1(2) |
177                 PKT_ID2(CMD_RGB) | PKT_LEN2(3),
178         PKT_ID3(CMD_BLNK) | PKT_LEN3(4),
179         PKT_ID0(CMD_HS) | PKT_LEN0(0) | PKT_ID1(CMD_EOT) | PKT_LEN1(0) | PKT_LP,
180         0,
181         PKT_ID0(CMD_HS) | PKT_LEN0(0) | PKT_ID1(CMD_BLNK) | PKT_LEN1(2) |
182                 PKT_ID2(CMD_RGB) | PKT_LEN2(3),
183         PKT_ID3(CMD_BLNK) | PKT_LEN3(4),
184 };
185
186 static const u32 dsi_pkt_seq_video_burst[NUMOF_PKT_SEQ] = {
187         PKT_ID0(CMD_VS) | PKT_LEN0(0) | PKT_ID1(CMD_EOT) | PKT_LEN1(7) | PKT_LP,
188         0,
189         PKT_ID0(CMD_HS) | PKT_LEN0(0) | PKT_ID1(CMD_EOT) | PKT_LEN1(7) | PKT_LP,
190         0,
191         PKT_ID0(CMD_HS) | PKT_LEN0(0) | PKT_ID1(CMD_EOT) | PKT_LEN1(7) | PKT_LP,
192         0,
193         PKT_ID0(CMD_HS) | PKT_LEN0(0) | PKT_ID1(CMD_BLNK) | PKT_LEN1(2)|
194         PKT_ID2(CMD_RGB) | PKT_LEN2(3) | PKT_LP,
195         PKT_ID0(CMD_EOT) | PKT_LEN0(7),
196         PKT_ID0(CMD_HS) | PKT_LEN0(0) | PKT_ID1(CMD_EOT) | PKT_LEN1(7) | PKT_LP,
197         0,
198         PKT_ID0(CMD_HS) | PKT_LEN0(0) | PKT_ID1(CMD_BLNK) | PKT_LEN1(2)|
199         PKT_ID2(CMD_RGB) | PKT_LEN2(3) | PKT_LP,
200         PKT_ID0(CMD_EOT) | PKT_LEN0(7),
201 };
202
203 static const u32 dsi_pkt_seq_video_burst_no_eot[NUMOF_PKT_SEQ] = {
204         PKT_ID0(CMD_VS) | PKT_LEN0(0) | PKT_ID1(CMD_EOT) | PKT_LEN1(0) | PKT_LP,
205         0,
206         PKT_ID0(CMD_HS) | PKT_LEN0(0) | PKT_ID1(CMD_EOT) | PKT_LEN1(0) | PKT_LP,
207         0,
208         PKT_ID0(CMD_HS) | PKT_LEN0(0) | PKT_ID1(CMD_EOT) | PKT_LEN1(0) | PKT_LP,
209         0,
210         PKT_ID0(CMD_HS) | PKT_LEN0(0) | PKT_ID1(CMD_BLNK) | PKT_LEN1(2)|
211         PKT_ID2(CMD_RGB) | PKT_LEN2(3) | PKT_LP,
212         PKT_ID0(CMD_EOT) | PKT_LEN0(0),
213         PKT_ID0(CMD_HS) | PKT_LEN0(0) | PKT_ID1(CMD_EOT) | PKT_LEN1(0) | PKT_LP,
214         0,
215         PKT_ID0(CMD_HS) | PKT_LEN0(0) | PKT_ID1(CMD_BLNK) | PKT_LEN1(2)|
216         PKT_ID2(CMD_RGB) | PKT_LEN2(3) | PKT_LP,
217         PKT_ID0(CMD_EOT) | PKT_LEN0(0),
218 };
219
220 /* TODO: verify with hw about this format */
221 const u32 dsi_pkt_seq_cmd_mode[NUMOF_PKT_SEQ] = {
222         0,
223         0,
224         0,
225         0,
226         0,
227         0,
228         PKT_ID0(CMD_LONGW) | PKT_LEN0(3) | PKT_ID1(CMD_EOT) | PKT_LEN1(7),
229         0,
230         0,
231         0,
232         PKT_ID0(CMD_LONGW) | PKT_LEN0(3) | PKT_ID1(CMD_EOT) | PKT_LEN1(7),
233         0,
234 };
235
236 const u32 init_reg[] = {
237         DSI_INT_ENABLE,
238         DSI_INT_STATUS,
239         DSI_INT_MASK,
240         DSI_INIT_SEQ_DATA_0,
241         DSI_INIT_SEQ_DATA_1,
242         DSI_INIT_SEQ_DATA_2,
243         DSI_INIT_SEQ_DATA_3,
244         DSI_DCS_CMDS,
245         DSI_PKT_SEQ_0_LO,
246         DSI_PKT_SEQ_1_LO,
247         DSI_PKT_SEQ_2_LO,
248         DSI_PKT_SEQ_3_LO,
249         DSI_PKT_SEQ_4_LO,
250         DSI_PKT_SEQ_5_LO,
251         DSI_PKT_SEQ_0_HI,
252         DSI_PKT_SEQ_1_HI,
253         DSI_PKT_SEQ_2_HI,
254         DSI_PKT_SEQ_3_HI,
255         DSI_PKT_SEQ_4_HI,
256         DSI_PKT_SEQ_5_HI,
257         DSI_CONTROL,
258         DSI_HOST_DSI_CONTROL,
259         DSI_PAD_CONTROL,
260         DSI_PAD_CONTROL_CD,
261         DSI_SOL_DELAY,
262         DSI_MAX_THRESHOLD,
263         DSI_TRIGGER,
264         DSI_TX_CRC,
265         DSI_INIT_SEQ_CONTROL,
266         DSI_PKT_LEN_0_1,
267         DSI_PKT_LEN_2_3,
268         DSI_PKT_LEN_4_5,
269         DSI_PKT_LEN_6_7,
270 };
271
272 inline unsigned long tegra_dsi_readl(struct tegra_dc_dsi_data *dsi, u32 reg)
273 {
274         return readl(dsi->base + reg * 4);
275 }
276 EXPORT_SYMBOL(tegra_dsi_readl);
277
278 inline void tegra_dsi_writel(struct tegra_dc_dsi_data *dsi, u32 val, u32 reg)
279 {
280         writel(val, dsi->base + reg * 4);
281 }
282 EXPORT_SYMBOL(tegra_dsi_writel);
283
284 static int tegra_dsi_syncpt(struct tegra_dc_dsi_data *dsi)
285 {
286         u32 val;
287         int ret;
288
289         ret = 0;
290
291         dsi->syncpt_val = nvhost_syncpt_read(
292                         &dsi->dc->ndev->host->syncpt, dsi->syncpt_id);
293
294         val = DSI_INCR_SYNCPT_COND(OP_DONE) |
295                 DSI_INCR_SYNCPT_INDX(dsi->syncpt_id);
296         tegra_dsi_writel(dsi, val, DSI_INCR_SYNCPT);
297
298         /* TODO: Use interrupt rather than polling */
299         ret = nvhost_syncpt_wait(&dsi->dc->ndev->host->syncpt,
300                 dsi->syncpt_id, dsi->syncpt_val + 1);
301         if (ret < 0) {
302                 printk(KERN_ERR "DSI sync point failure\n");
303                 goto fail;
304         }
305
306         (dsi->syncpt_val)++;
307         return 0;
308 fail:
309         return ret;
310 }
311
312 static u32 tegra_dsi_get_hs_clk_rate(struct tegra_dc_dsi_data *dsi)
313 {
314         u32 dsi_clock_rate_khz;
315
316         switch (dsi->info.video_burst_mode) {
317         case TEGRA_DSI_VIDEO_BURST_MODE_LOW_SPEED:
318         case TEGRA_DSI_VIDEO_BURST_MODE_MEDIUM_SPEED:
319         case TEGRA_DSI_VIDEO_BURST_MODE_FAST_SPEED:
320         case TEGRA_DSI_VIDEO_BURST_MODE_FASTEST_SPEED:
321                 /* Calculate DSI HS clock rate for DSI burst mode */
322                 dsi_clock_rate_khz = dsi->default_pixel_clk_khz *
323                                                         dsi->shift_clk_div;
324                 break;
325         case TEGRA_DSI_VIDEO_NONE_BURST_MODE:
326         case TEGRA_DSI_VIDEO_NONE_BURST_MODE_WITH_SYNC_END:
327         case TEGRA_DSI_VIDEO_BURST_MODE_LOWEST_SPEED:
328         default:
329                 /* Clock rate is default DSI clock rate for non-burst mode */
330                 dsi_clock_rate_khz = dsi->default_hs_clk_khz;
331                 break;
332         }
333
334         return dsi_clock_rate_khz;
335 }
336
337 static u32 tegra_dsi_get_lp_clk_rate(struct tegra_dc_dsi_data *dsi)
338 {
339         u32 dsi_clock_rate_khz;
340
341         if (dsi->info.enable_hs_clock_on_lp_cmd_mode)
342                 if (dsi->info.hs_clk_in_lp_cmd_mode_freq_khz)
343                         dsi_clock_rate_khz =
344                                 dsi->info.hs_clk_in_lp_cmd_mode_freq_khz;
345                 else
346                         dsi_clock_rate_khz = tegra_dsi_get_hs_clk_rate(dsi);
347         else
348                 dsi_clock_rate_khz = dsi->info.lp_cmd_mode_freq_khz;
349
350         return dsi_clock_rate_khz;
351 }
352
353 static u32 tegra_dsi_get_shift_clk_div(struct tegra_dc_dsi_data *dsi)
354 {
355         u32 shift_clk_div;
356         u32 max_shift_clk_div;
357         u32 burst_width;
358         u32 burst_width_max;
359
360         /* Get the real value of default shift_clk_div. default_shift_clk_div
361          * holds the real value of shift_clk_div. */
362         shift_clk_div = dsi->default_shift_clk_div;
363
364         /* Calculate shift_clk_div which can matche the video_burst_mode.*/
365         if (dsi->info.video_burst_mode >=
366                         TEGRA_DSI_VIDEO_BURST_MODE_LOWEST_SPEED) {
367                 /* The max_shift_clk_div is multiplied by 10 to save the
368                  * fraction */
369                 if (dsi->info.max_panel_freq_khz >= dsi->default_hs_clk_khz)
370                         max_shift_clk_div = dsi->info.max_panel_freq_khz
371                                 * shift_clk_div * 10 / dsi->default_hs_clk_khz;
372                 else
373                         max_shift_clk_div = shift_clk_div * 10;
374
375                 burst_width = dsi->info.video_burst_mode
376                                 - TEGRA_DSI_VIDEO_BURST_MODE_LOWEST_SPEED;
377                 burst_width_max = TEGRA_DSI_VIDEO_BURST_MODE_FASTEST_SPEED
378                                 - TEGRA_DSI_VIDEO_BURST_MODE_LOWEST_SPEED;
379
380                 shift_clk_div = (max_shift_clk_div - shift_clk_div * 10) *
381                         burst_width / (burst_width_max * 10) + shift_clk_div;
382         }
383
384         return shift_clk_div;
385 }
386
387 static void tegra_dsi_init_sw(struct tegra_dc *dc,
388                                                 struct tegra_dc_dsi_data *dsi)
389 {
390         u32 h_width_pixels;
391         u32 v_width_lines;
392         u32 pixel_clk_hz;
393         u32 byte_clk_hz;
394         u32 plld_clk_mhz;
395
396         switch (dsi->info.pixel_format) {
397         case TEGRA_DSI_PIXEL_FORMAT_16BIT_P:
398                 /* 2 bytes per pixel */
399                 dsi->pixel_scaler_mul = 2;
400                 dsi->pixel_scaler_div = 1;
401                 break;
402         case TEGRA_DSI_PIXEL_FORMAT_18BIT_P:
403                 /* 2.25 bytes per pixel */
404                 dsi->pixel_scaler_mul = 9;
405                 dsi->pixel_scaler_div = 4;
406                 break;
407         case TEGRA_DSI_PIXEL_FORMAT_18BIT_NP:
408         case TEGRA_DSI_PIXEL_FORMAT_24BIT_P:
409                 /* 3 bytes per pixel */
410                 dsi->pixel_scaler_mul = 3;
411                 dsi->pixel_scaler_div = 1;
412                 break;
413         default:
414                 break;
415         }
416
417         dsi->controller_index = dc->ndev->id;
418         dsi->ulpm = false;
419         dsi->enabled = false;
420         dsi->clk_ref = false;
421
422         dsi->dsi_control_val =
423                         DSI_CONTROL_VIRTUAL_CHANNEL(dsi->info.virtual_channel) |
424                         DSI_CONTROL_NUM_DATA_LANES(dsi->info.n_data_lanes - 1) |
425                         DSI_CONTROL_VID_SOURCE(dsi->controller_index) |
426                         DSI_CONTROL_DATA_FORMAT(dsi->info.pixel_format);
427
428         /* Below we are going to calculate dsi and dc clock rate.
429          * Calcuate the horizontal and vertical width. */
430         h_width_pixels = dc->mode.h_back_porch + dc->mode.h_front_porch +
431                         dc->mode.h_sync_width + dc->mode.h_active;
432         v_width_lines = dc->mode.v_back_porch + dc->mode.v_front_porch +
433                         dc->mode.v_sync_width + dc->mode.v_active;
434
435         /* Calculate minimum required pixel rate. */
436         pixel_clk_hz = h_width_pixels * v_width_lines * dsi->info.refresh_rate;
437
438         dc->pixel_clk = pixel_clk_hz;
439
440         /* Calculate minimum byte rate on DSI interface. */
441         byte_clk_hz = (pixel_clk_hz * dsi->pixel_scaler_mul) /
442                         (dsi->pixel_scaler_div * dsi->info.n_data_lanes);
443
444         /* Round up to multiple of mega hz. */
445         plld_clk_mhz = DIV_ROUND_UP((byte_clk_hz * NUMOF_BIT_PER_BYTE),
446                                                                 1000000);
447
448         /* Calculate default real shift_clk_div. */
449         dsi->default_shift_clk_div = (NUMOF_BIT_PER_BYTE / 2) *
450                 dsi->pixel_scaler_mul / (dsi->pixel_scaler_div *
451                 dsi->info.n_data_lanes);
452         /* Calculate default DSI hs clock. DSI interface is double data rate.
453          * Data is transferred on both rising and falling edge of clk, div by 2
454          * to get the actual clock rate.
455          * */
456         dsi->default_hs_clk_khz = plld_clk_mhz * 1000 / 2;
457         dsi->default_pixel_clk_khz = plld_clk_mhz * 1000 / 2
458                                                 / dsi->default_shift_clk_div;
459
460         /* Get the actual shift_clk_div and clock rates. */
461         dsi->shift_clk_div = tegra_dsi_get_shift_clk_div(dsi);
462         dsi->target_lp_clk_khz = tegra_dsi_get_lp_clk_rate(dsi);
463         dsi->target_hs_clk_khz = tegra_dsi_get_hs_clk_rate(dsi);
464
465         dev_info(&dc->ndev->dev, "DSI: HS clock rate is %d\n",
466                                                         dsi->target_hs_clk_khz);
467
468         dsi->controller_index = dc->ndev->id;
469
470 #if DSI_USE_SYNC_POINTS
471         dsi->syncpt_id = NVSYNCPT_DSI;
472 #endif
473
474         /*
475          * Force video clock to be continuous mode if
476          * enable_hs_clock_on_lp_cmd_mode is set
477          */
478         if (dsi->info.enable_hs_clock_on_lp_cmd_mode) {
479                 if (dsi->info.video_clock_mode !=
480                                         TEGRA_DSI_VIDEO_CLOCK_CONTINUOUS)
481                         printk("Force to clock continuous mode\n");
482
483                 dsi->info.video_clock_mode = TEGRA_DSI_VIDEO_CLOCK_CONTINUOUS;
484         }
485
486 }
487
488 static void tegra_dsi_get_phy_timing(struct tegra_dc_dsi_data *dsi,
489                                 struct dsi_phy_timing_inclk *phy_timing_clk,
490                                 u32 clk_ns)
491 {
492
493         phy_timing_clk->t_hsdexit = dsi->info.phy_timing.t_hsdexit_ns ?
494                         (dsi->info.phy_timing.t_hsdexit_ns / clk_ns) :
495                         (T_HSEXIT_DEFAULT(clk_ns));
496
497         phy_timing_clk->t_hstrail = dsi->info.phy_timing.t_hstrail_ns ?
498                         (dsi->info.phy_timing.t_hstrail_ns / clk_ns) :
499                         (T_HSTRAIL_DEFAULT(clk_ns));
500
501         phy_timing_clk->t_datzero = dsi->info.phy_timing.t_datzero_ns ?
502                         (dsi->info.phy_timing.t_datzero_ns / clk_ns) :
503                         (T_DATZERO_DEFAULT(clk_ns));
504
505         phy_timing_clk->t_hsprepr = dsi->info.phy_timing.t_hsprepr_ns ?
506                         (dsi->info.phy_timing.t_hsprepr_ns / clk_ns) :
507                         (T_HSPREPR_DEFAULT(clk_ns));
508
509         phy_timing_clk->t_clktrail = dsi->info.phy_timing.t_clktrail_ns ?
510                                 (dsi->info.phy_timing.t_clktrail_ns / clk_ns) :
511                                 (T_CLKTRAIL_DEFAULT(clk_ns));
512
513         phy_timing_clk->t_clkpost = dsi->info.phy_timing.t_clkpost_ns ?
514                                 (dsi->info.phy_timing.t_clkpost_ns / clk_ns) :
515                                 (T_CLKPOST_DEFAULT(clk_ns));
516
517         phy_timing_clk->t_clkzero = dsi->info.phy_timing.t_clkzero_ns ?
518                                 (dsi->info.phy_timing.t_clkzero_ns / clk_ns) :
519                                 (T_CLKZERO_DEFAULT(clk_ns));
520
521         phy_timing_clk->t_tlpx = dsi->info.phy_timing.t_tlpx_ns ?
522                                 (dsi->info.phy_timing.t_tlpx_ns / clk_ns) :
523                                 (T_TLPX_DEFAULT(clk_ns));
524
525         phy_timing_clk->t_clkpre = T_CLKPRE_DEFAULT(clk_ns);
526         phy_timing_clk->t_clkprepare = T_CLKPREPARE_DEFAULT(clk_ns);
527         phy_timing_clk->t_wakeup = T_WAKEUP_DEFAULT(clk_ns);
528
529         phy_timing_clk->t_taget = 5 * phy_timing_clk->t_tlpx;
530         phy_timing_clk->t_tasure = 2 * phy_timing_clk->t_tlpx;
531         phy_timing_clk->t_tago = 4 * phy_timing_clk->t_tlpx;
532 }
533
534 static void tegra_dsi_set_phy_timing(struct tegra_dc_dsi_data *dsi)
535 {
536         u32 val;
537         struct dsi_phy_timing_inclk     phy_timing;
538
539         tegra_dsi_get_phy_timing(dsi, &phy_timing, dsi->current_bit_clk_ns);
540
541         val = DSI_PHY_TIMING_0_THSDEXIT(phy_timing.t_hsdexit) |
542                         DSI_PHY_TIMING_0_THSTRAIL(phy_timing.t_hstrail) |
543                         DSI_PHY_TIMING_0_TDATZERO(phy_timing.t_datzero) |
544                         DSI_PHY_TIMING_0_THSPREPR(phy_timing.t_hsprepr);
545         tegra_dsi_writel(dsi, val, DSI_PHY_TIMING_0);
546
547         val = DSI_PHY_TIMING_1_TCLKTRAIL(phy_timing.t_clktrail) |
548                         DSI_PHY_TIMING_1_TCLKPOST(phy_timing.t_clkpost) |
549                         DSI_PHY_TIMING_1_TCLKZERO(phy_timing.t_clkzero) |
550                         DSI_PHY_TIMING_1_TTLPX(phy_timing.t_tlpx);
551         tegra_dsi_writel(dsi, val, DSI_PHY_TIMING_1);
552
553         val = DSI_PHY_TIMING_2_TCLKPREPARE(phy_timing.t_clkprepare) |
554                 DSI_PHY_TIMING_2_TCLKPRE(phy_timing.t_clkpre) |
555                         DSI_PHY_TIMING_2_TWAKEUP(phy_timing.t_wakeup);
556         tegra_dsi_writel(dsi, val, DSI_PHY_TIMING_2);
557
558         val = DSI_BTA_TIMING_TTAGET(phy_timing.t_taget) |
559                         DSI_BTA_TIMING_TTASURE(phy_timing.t_tasure) |
560                         DSI_BTA_TIMING_TTAGO(phy_timing.t_tago);
561         tegra_dsi_writel(dsi, val, DSI_BTA_TIMING);
562 }
563
564 static u32 tegra_dsi_sol_delay_burst(struct tegra_dc *dc,
565                                                 struct tegra_dc_dsi_data *dsi)
566 {
567         u32 dsi_to_pixel_clk_ratio;
568         u32 temp;
569         u32 temp1;
570         u32 mipi_clk_adj_kHz;
571         u32 sol_delay;
572         struct tegra_dc_mode *dc_modes = &dc->mode;
573
574         /* Get Fdsi/Fpixel ration (note: Fdsi si in bit format) */
575         dsi_to_pixel_clk_ratio = (dsi->current_dsi_clk_khz * 2 +
576                 dsi->default_pixel_clk_khz - 1) / dsi->default_pixel_clk_khz;
577
578         /* Convert Fdsi to byte format */
579         dsi_to_pixel_clk_ratio *= 1000/8;
580
581         /* Multiplying by 1000 so that we don't loose the fraction part */
582         temp = dc_modes->h_active * 1000;
583         temp1 = dc_modes->h_active + dc_modes->h_back_porch +
584                         dc_modes->h_sync_width;
585
586         sol_delay = temp1 * dsi_to_pixel_clk_ratio -
587                         temp * dsi->pixel_scaler_mul /
588                         (dsi->pixel_scaler_div * dsi->info.n_data_lanes);
589
590         /* Do rounding on sol delay */
591         sol_delay = (sol_delay + 1000 - 1)/1000;
592
593         /* TODO:
594          * 1. find out the correct sol fifo depth to use
595          * 2. verify with hw about the clamping function
596          */
597         if (sol_delay > (480 * 4)) {
598                 sol_delay = (480 * 4);
599                 mipi_clk_adj_kHz = sol_delay +
600                         (dc_modes->h_active * dsi->pixel_scaler_mul) /
601                         (dsi->info.n_data_lanes * dsi->pixel_scaler_div);
602
603                 mipi_clk_adj_kHz *= (dsi->default_pixel_clk_khz / temp1);
604
605                 mipi_clk_adj_kHz *= 4;
606         }
607
608         dsi->target_hs_clk_khz = mipi_clk_adj_kHz;
609
610         return sol_delay;
611 }
612
613 static void tegra_dsi_set_sol_delay(struct tegra_dc *dc,
614                                                 struct tegra_dc_dsi_data *dsi)
615 {
616         u32 sol_delay;
617
618         if (dsi->info.video_burst_mode == TEGRA_DSI_VIDEO_NONE_BURST_MODE ||
619                 dsi->info.video_burst_mode ==
620                                 TEGRA_DSI_VIDEO_NONE_BURST_MODE_WITH_SYNC_END) {
621                 sol_delay = NUMOF_BIT_PER_BYTE * dsi->pixel_scaler_mul /
622                         (dsi->pixel_scaler_div * dsi->info.n_data_lanes);
623                 dsi->status.clk_burst = DSI_CLK_BURST_NONE_BURST;
624         } else {
625                 sol_delay = tegra_dsi_sol_delay_burst(dc, dsi);
626                 dsi->status.clk_burst = DSI_CLK_BURST_BURST_MODE;
627         }
628
629         tegra_dsi_writel(dsi, DSI_SOL_DELAY_SOL_DELAY(sol_delay),
630                                                                 DSI_SOL_DELAY);
631 }
632
633 static void tegra_dsi_set_timeout(struct tegra_dc_dsi_data *dsi)
634 {
635         u32 val;
636         u32 bytes_per_frame;
637         u32 timeout = 0;
638
639         /* TODO: verify the following eq */
640         bytes_per_frame = dsi->current_dsi_clk_khz * 1000 * 2 /
641                                                 (dsi->info.refresh_rate * 8);
642         timeout = bytes_per_frame / DSI_CYCLE_COUNTER_VALUE;
643         timeout = (timeout + DSI_HTX_TO_MARGIN) & 0xffff;
644
645         val = DSI_TIMEOUT_0_LRXH_TO(DSI_LRXH_TO_VALUE) |
646                         DSI_TIMEOUT_0_HTX_TO(timeout);
647         tegra_dsi_writel(dsi, val, DSI_TIMEOUT_0);
648
649         if (dsi->info.panel_reset_timeout_msec)
650                 timeout = (dsi->info.panel_reset_timeout_msec * 1000*1000)
651                                         / dsi->current_bit_clk_ns;
652         else
653                 timeout = DSI_PR_TO_VALUE;
654
655         val = DSI_TIMEOUT_1_PR_TO(timeout) |
656                 DSI_TIMEOUT_1_TA_TO(DSI_TA_TO_VALUE);
657         tegra_dsi_writel(dsi, val, DSI_TIMEOUT_1);
658
659         val = DSI_TO_TALLY_P_RESET_STATUS(IN_RESET) |
660                 DSI_TO_TALLY_TA_TALLY(DSI_TA_TALLY_VALUE)|
661                 DSI_TO_TALLY_LRXH_TALLY(DSI_LRXH_TALLY_VALUE)|
662                 DSI_TO_TALLY_HTX_TALLY(DSI_HTX_TALLY_VALUE);
663         tegra_dsi_writel(dsi, val, DSI_TO_TALLY);
664 }
665
666 static void tegra_dsi_setup_video_mode_pkt_length(struct tegra_dc *dc,
667                                                 struct tegra_dc_dsi_data *dsi)
668 {
669         u32 val;
670         u32 hact_pkt_len;
671         u32 hsa_pkt_len;
672         u32 hbp_pkt_len;
673         u32 hfp_pkt_len;
674
675         hact_pkt_len = dc->mode.h_active * dsi->pixel_scaler_mul /
676                                                         dsi->pixel_scaler_div;
677         hsa_pkt_len = dc->mode.h_sync_width * dsi->pixel_scaler_mul /
678                                                         dsi->pixel_scaler_div;
679         hbp_pkt_len = dc->mode.h_back_porch * dsi->pixel_scaler_mul /
680                                                         dsi->pixel_scaler_div;
681         hfp_pkt_len = dc->mode.h_front_porch * dsi->pixel_scaler_mul /
682                                                         dsi->pixel_scaler_div;
683
684         if (dsi->info.video_burst_mode !=
685                                 TEGRA_DSI_VIDEO_NONE_BURST_MODE_WITH_SYNC_END)
686                 hbp_pkt_len += hsa_pkt_len;
687
688         hsa_pkt_len -= DSI_HSYNC_BLNK_PKT_OVERHEAD;
689         hbp_pkt_len -= DSI_HBACK_PORCH_PKT_OVERHEAD;
690         hfp_pkt_len -= DSI_HFRONT_PORCH_PKT_OVERHEAD;
691
692         val = DSI_PKT_LEN_0_1_LENGTH_0(0) |
693                         DSI_PKT_LEN_0_1_LENGTH_1(hsa_pkt_len);
694         tegra_dsi_writel(dsi, val, DSI_PKT_LEN_0_1);
695
696         val = DSI_PKT_LEN_2_3_LENGTH_2(hbp_pkt_len) |
697                         DSI_PKT_LEN_2_3_LENGTH_3(hact_pkt_len);
698         tegra_dsi_writel(dsi, val, DSI_PKT_LEN_2_3);
699
700         val = DSI_PKT_LEN_4_5_LENGTH_4(hfp_pkt_len) |
701                         DSI_PKT_LEN_4_5_LENGTH_5(0);
702         tegra_dsi_writel(dsi, val, DSI_PKT_LEN_4_5);
703
704         val = DSI_PKT_LEN_6_7_LENGTH_6(0) | DSI_PKT_LEN_6_7_LENGTH_7(0);
705         tegra_dsi_writel(dsi, val, DSI_PKT_LEN_6_7);
706 }
707
708 static void tegra_dsi_setup_cmd_mode_pkt_length(struct tegra_dc *dc,
709                                                 struct tegra_dc_dsi_data *dsi)
710 {
711         unsigned long   val;
712         unsigned long   act_bytes;
713
714         act_bytes = dc->mode.h_active * dsi->pixel_scaler_mul /
715                         dsi->pixel_scaler_div + 1;
716
717         val = DSI_PKT_LEN_0_1_LENGTH_0(0) | DSI_PKT_LEN_0_1_LENGTH_1(0);
718         tegra_dsi_writel(dsi, val, DSI_PKT_LEN_0_1);
719
720         val = DSI_PKT_LEN_2_3_LENGTH_2(0) | DSI_PKT_LEN_2_3_LENGTH_3(act_bytes);
721         tegra_dsi_writel(dsi, val, DSI_PKT_LEN_2_3);
722
723         val = DSI_PKT_LEN_4_5_LENGTH_4(0) | DSI_PKT_LEN_4_5_LENGTH_5(act_bytes);
724         tegra_dsi_writel(dsi, val, DSI_PKT_LEN_4_5);
725
726         val = DSI_PKT_LEN_6_7_LENGTH_6(0) | DSI_PKT_LEN_6_7_LENGTH_7(0x0f0f);
727         tegra_dsi_writel(dsi, val, DSI_PKT_LEN_6_7);
728 }
729
730 static void tegra_dsi_set_pkt_length(struct tegra_dc *dc,
731                                                 struct tegra_dc_dsi_data *dsi)
732 {
733         if (dsi->driven_mode == TEGRA_DSI_DRIVEN_BY_HOST)
734                 return;
735
736         if (dsi->info.video_data_type == TEGRA_DSI_VIDEO_TYPE_VIDEO_MODE)
737                 tegra_dsi_setup_video_mode_pkt_length(dc, dsi);
738         else
739                 tegra_dsi_setup_cmd_mode_pkt_length(dc, dsi);
740 }
741
742 static void tegra_dsi_set_pkt_seq(struct tegra_dc *dc,
743                                                 struct tegra_dc_dsi_data *dsi)
744 {
745         const u32 *pkt_seq;
746         u32 rgb_info;
747         u32 pkt_seq_3_5_rgb_lo;
748         u32 pkt_seq_3_5_rgb_hi;
749         u32     val;
750         u32 reg;
751         u8  i;
752
753         if (dsi->driven_mode == TEGRA_DSI_DRIVEN_BY_HOST)
754                 return;
755
756         switch (dsi->info.pixel_format) {
757         case TEGRA_DSI_PIXEL_FORMAT_16BIT_P:
758                 rgb_info = CMD_RGB_16BPP;
759                 break;
760         case TEGRA_DSI_PIXEL_FORMAT_18BIT_P:
761                 rgb_info = CMD_RGB_18BPP;
762                 break;
763         case TEGRA_DSI_PIXEL_FORMAT_18BIT_NP:
764                 rgb_info = CMD_RGB_18BPPNP;
765                 break;
766         case TEGRA_DSI_PIXEL_FORMAT_24BIT_P:
767         default:
768                 rgb_info = CMD_RGB_24BPP;
769                 break;
770         }
771
772         pkt_seq_3_5_rgb_lo = 0;
773         pkt_seq_3_5_rgb_hi = 0;
774         if (dsi->info.video_data_type == TEGRA_DSI_VIDEO_TYPE_COMMAND_MODE)
775                 pkt_seq = dsi_pkt_seq_cmd_mode;
776         else {
777                 switch (dsi->info.video_burst_mode) {
778                 case TEGRA_DSI_VIDEO_BURST_MODE_LOWEST_SPEED:
779                 case TEGRA_DSI_VIDEO_BURST_MODE_LOW_SPEED:
780                 case TEGRA_DSI_VIDEO_BURST_MODE_MEDIUM_SPEED:
781                 case TEGRA_DSI_VIDEO_BURST_MODE_FAST_SPEED:
782                 case TEGRA_DSI_VIDEO_BURST_MODE_FASTEST_SPEED:
783                         pkt_seq_3_5_rgb_lo =
784                                         DSI_PKT_SEQ_3_LO_PKT_32_ID(rgb_info);
785                         if (!dsi->info.no_pkt_seq_eot)
786                                 pkt_seq = dsi_pkt_seq_video_burst;
787                         else
788                                 pkt_seq = dsi_pkt_seq_video_burst_no_eot;
789                         break;
790                 case TEGRA_DSI_VIDEO_NONE_BURST_MODE_WITH_SYNC_END:
791                         pkt_seq_3_5_rgb_hi =
792                                         DSI_PKT_SEQ_3_HI_PKT_34_ID(rgb_info);
793                         pkt_seq = dsi_pkt_seq_video_non_burst_syne;
794                         break;
795                 case TEGRA_DSI_VIDEO_NONE_BURST_MODE:
796                 default:
797                         pkt_seq_3_5_rgb_lo =
798                                         DSI_PKT_SEQ_3_LO_PKT_32_ID(rgb_info);
799                         pkt_seq = dsi_pkt_seq_video_non_burst;
800                         break;
801                 }
802         }
803
804         for (i = 0; i < NUMOF_PKT_SEQ; i++) {
805                 val = pkt_seq[i];
806                 reg = dsi_pkt_seq_reg[i];
807                 if ((reg == DSI_PKT_SEQ_3_LO) || (reg == DSI_PKT_SEQ_5_LO))
808                         val |= pkt_seq_3_5_rgb_lo;
809                 if ((reg == DSI_PKT_SEQ_3_HI) || (reg == DSI_PKT_SEQ_5_HI))
810                         val |= pkt_seq_3_5_rgb_hi;
811                 tegra_dsi_writel(dsi, val, reg);
812         }
813 }
814
815 static void tegra_dsi_stop_dc_stream(struct tegra_dc *dc,
816                                                 struct tegra_dc_dsi_data *dsi)
817 {
818         tegra_dc_writel(dc, 0, DC_DISP_DISP_WIN_OPTIONS);
819         tegra_dc_writel(dc, GENERAL_ACT_REQ << 8, DC_CMD_STATE_CONTROL);
820         tegra_dc_writel(dc, GENERAL_ACT_REQ, DC_CMD_STATE_CONTROL);
821
822         dsi->status.dc_stream = DSI_DC_STREAM_DISABLE;
823 }
824
825 void tegra_dsi_stop_dc_stream_at_frame_end(struct tegra_dc *dc,
826                                                 struct tegra_dc_dsi_data *dsi)
827 {
828         int val;
829         long timeout;
830
831         /* stop dc */
832         tegra_dsi_stop_dc_stream(dc, dsi);
833
834         /* enable vblank interrupt */
835         val = tegra_dc_readl(dc, DC_CMD_INT_ENABLE);
836         val |= V_BLANK_INT;
837         tegra_dc_writel(dc, val, DC_CMD_INT_ENABLE);
838
839         val = tegra_dc_readl(dc, DC_CMD_INT_MASK);
840         val |= V_BLANK_INT;
841         tegra_dc_writel(dc, val, DC_CMD_INT_MASK);
842
843         /* wait for vblank completion */
844         timeout = wait_for_completion_interruptible_timeout(
845                 &dc->vblank_complete, DSI_STOP_DC_DURATION_MSEC);
846
847         /* disable vblank interrupt */
848         val = tegra_dc_readl(dc, DC_CMD_INT_ENABLE);
849         val &= ~V_BLANK_INT;
850         tegra_dc_writel(dc, val, DC_CMD_INT_ENABLE);
851
852         if (timeout == 0)
853                 printk("Warning: dc dosen't stop at the end of the frame.\n");
854 }
855
856 static void tegra_dsi_start_dc_stream(struct tegra_dc *dc,
857                                                 struct tegra_dc_dsi_data *dsi)
858 {
859         u32 val;
860
861         tegra_dc_writel(dc, DSI_ENABLE, DC_DISP_DISP_WIN_OPTIONS);
862
863         /* TODO: clean up */
864         tegra_dc_writel(dc, PW0_ENABLE | PW1_ENABLE | PW2_ENABLE | PW3_ENABLE |
865                         PW4_ENABLE | PM0_ENABLE | PM1_ENABLE,
866                         DC_CMD_DISPLAY_POWER_CONTROL);
867
868         /* Configure one-shot mode or continuous mode */
869         if (dc->out->flags & TEGRA_DC_OUT_ONE_SHOT_MODE) {
870                 /* disable LSPI/LCD_DE output */
871                 val = PIN_OUTPUT_LSPI_OUTPUT_DIS;
872                 tegra_dc_writel(dc, val, DC_COM_PIN_OUTPUT_ENABLE3);
873
874                 /* enable MSF & set MSF polarity */
875                 val = MSF_ENABLE | MSF_LSPI;
876                 if (!dsi->info.te_polarity_low)
877                         val |= MSF_POLARITY_HIGH;
878                 else
879                         val |= MSF_POLARITY_LOW;
880                 tegra_dc_writel(dc, val, DC_CMD_DISPLAY_COMMAND_OPTION0);
881
882                 /* set non-continuous mode */
883                 tegra_dc_writel(dc, DISP_CTRL_MODE_NC_DISPLAY,
884                                                 DC_CMD_DISPLAY_COMMAND);
885                 tegra_dc_writel(dc, GENERAL_UPDATE, DC_CMD_STATE_CONTROL);
886                 tegra_dc_writel(dc, GENERAL_ACT_REQ | NC_HOST_TRIG,
887                                                 DC_CMD_STATE_CONTROL);
888         } else {
889                 /* set continuous mode */
890                 tegra_dc_writel(dc, DISP_CTRL_MODE_C_DISPLAY,
891                                                 DC_CMD_DISPLAY_COMMAND);
892                 tegra_dc_writel(dc, GENERAL_UPDATE, DC_CMD_STATE_CONTROL);
893                 tegra_dc_writel(dc, GENERAL_ACT_REQ, DC_CMD_STATE_CONTROL);
894         }
895
896         dsi->status.dc_stream = DSI_DC_STREAM_ENABLE;
897 }
898
899 static void tegra_dsi_set_dc_clk(struct tegra_dc *dc,
900                                                 struct tegra_dc_dsi_data *dsi)
901 {
902         u32 shift_clk_div_register;
903         u32 val;
904
905         /* Get the corresponding register value of shift_clk_div. */
906         shift_clk_div_register = dsi->shift_clk_div * 2 - 2;
907
908 #ifdef CONFIG_TEGRA_FPGA_PLATFORM
909         shift_clk_div_register = 1;
910 #endif
911
912         /* TODO: find out if PCD3 option is required */
913         val = PIXEL_CLK_DIVIDER_PCD1 |
914                                 SHIFT_CLK_DIVIDER(shift_clk_div_register);
915         tegra_dc_writel(dc, val, DC_DISP_DISP_CLOCK_CONTROL);
916 }
917
918 static void tegra_dsi_set_dsi_clk(struct tegra_dc *dc,
919                                         struct tegra_dc_dsi_data *dsi, u32 clk)
920 {
921         u32 rm;
922
923         rm = clk % 1000;
924         if (rm != 0)
925                 clk -= rm;
926
927         clk *= 2;       /*
928                          * Value for PLLD routine is required to be twice as
929                          * the desired clock rate
930                          */
931
932         dc->mode.pclk = clk*1000;
933         tegra_dc_setup_clk(dc, dsi->dsi_clk);
934         if (dsi->clk_ref == true)
935                 clk_disable(dsi->dsi_clk);
936         else
937                 dsi->clk_ref = true;
938         clk_enable(dsi->dsi_clk);
939         tegra_periph_reset_deassert(dsi->dsi_clk);
940
941         dsi->current_dsi_clk_khz = clk_get_rate(dsi->dsi_clk) / 1000;
942
943         dsi->current_bit_clk_ns =  1000*1000 / (dsi->current_dsi_clk_khz * 2);
944 }
945
946 static void tegra_dsi_hs_clk_out_enable(struct tegra_dc_dsi_data *dsi)
947 {
948         u32 val;
949
950         val = tegra_dsi_readl(dsi, DSI_CONTROL);
951         val &= ~DSI_CONTROL_HS_CLK_CTRL(1);
952
953         if (dsi->info.video_clock_mode == TEGRA_DSI_VIDEO_CLOCK_CONTINUOUS) {
954                 val |= DSI_CONTROL_HS_CLK_CTRL(CONTINUOUS);
955                 dsi->status.clk_mode = DSI_PHYCLK_CONTINUOUS;
956         } else {
957                 val |= DSI_CONTROL_HS_CLK_CTRL(TX_ONLY);
958                 dsi->status.clk_mode = DSI_PHYCLK_TX_ONLY;
959         }
960         tegra_dsi_writel(dsi, val, DSI_CONTROL);
961
962         val = tegra_dsi_readl(dsi, DSI_HOST_DSI_CONTROL);
963         val &= ~DSI_HOST_DSI_CONTROL_HIGH_SPEED_TRANS(1);
964         val |= DSI_HOST_DSI_CONTROL_HIGH_SPEED_TRANS(TEGRA_DSI_HIGH);
965         tegra_dsi_writel(dsi, val, DSI_HOST_DSI_CONTROL);
966
967         dsi->status.clk_out = DSI_PHYCLK_OUT_EN;
968 }
969
970 static void tegra_dsi_hs_clk_out_enable_in_lp(struct tegra_dc_dsi_data *dsi)
971 {
972         u32 val;
973         tegra_dsi_hs_clk_out_enable(dsi);
974
975         val = tegra_dsi_readl(dsi, DSI_HOST_DSI_CONTROL);
976         val &= ~DSI_HOST_DSI_CONTROL_HIGH_SPEED_TRANS(1);
977         val |= DSI_HOST_DSI_CONTROL_HIGH_SPEED_TRANS(TEGRA_DSI_LOW);
978         tegra_dsi_writel(dsi, val, DSI_HOST_DSI_CONTROL);
979 }
980
981 static void tegra_dsi_hs_clk_out_disable(struct tegra_dc *dc,
982                                                 struct tegra_dc_dsi_data *dsi)
983 {
984         u32 val;
985
986         if (dsi->status.dc_stream == DSI_DC_STREAM_ENABLE)
987                 tegra_dsi_stop_dc_stream(dc, dsi);
988
989         val = tegra_dsi_readl(dsi, DSI_CONTROL);
990         val &= ~DSI_CONTROL_HS_CLK_CTRL(1);
991         val |= DSI_CONTROL_HS_CLK_CTRL(TX_ONLY);
992         tegra_dsi_writel(dsi, val, DSI_CONTROL);
993
994         /* TODO: issue a cmd */
995
996         val = tegra_dsi_readl(dsi, DSI_HOST_DSI_CONTROL);
997         val &= ~DSI_HOST_DSI_CONTROL_HIGH_SPEED_TRANS(1);
998         val |= DSI_HOST_DSI_CONTROL_HIGH_SPEED_TRANS(TEGRA_DSI_LOW);
999         tegra_dsi_writel(dsi, val, DSI_HOST_DSI_CONTROL);
1000
1001         dsi->status.clk_mode = DSI_PHYCLK_NOT_INIT;
1002         dsi->status.clk_out = DSI_PHYCLK_OUT_DIS;
1003 }
1004
1005 static void tegra_dsi_set_control_reg_lp(struct tegra_dc_dsi_data *dsi)
1006 {
1007         u32 dsi_control;
1008         u32 host_dsi_control;
1009         u32 max_threshold;
1010
1011         dsi_control = dsi->dsi_control_val | DSI_CTRL_HOST_DRIVEN;
1012         host_dsi_control = HOST_DSI_CTRL_COMMON |
1013                         HOST_DSI_CTRL_HOST_DRIVEN |
1014                         DSI_HOST_DSI_CONTROL_HIGH_SPEED_TRANS(TEGRA_DSI_LOW);
1015         max_threshold = DSI_MAX_THRESHOLD_MAX_THRESHOLD(DSI_HOST_FIFO_DEPTH);
1016
1017         tegra_dsi_writel(dsi, max_threshold, DSI_MAX_THRESHOLD);
1018         tegra_dsi_writel(dsi, dsi_control, DSI_CONTROL);
1019         tegra_dsi_writel(dsi, host_dsi_control, DSI_HOST_DSI_CONTROL);
1020
1021         dsi->status.driven = DSI_DRIVEN_MODE_HOST;
1022         dsi->status.clk_burst = DSI_CLK_BURST_NOT_INIT;
1023         dsi->status.vtype = DSI_VIDEO_TYPE_NOT_INIT;
1024 }
1025
1026 static void tegra_dsi_set_control_reg_hs(struct tegra_dc_dsi_data *dsi)
1027 {
1028         u32 dsi_control;
1029         u32 host_dsi_control;
1030         u32 max_threshold;
1031         u32 dcs_cmd;
1032
1033         dsi_control = dsi->dsi_control_val;
1034         host_dsi_control = HOST_DSI_CTRL_COMMON;
1035         max_threshold = 0;
1036         dcs_cmd = 0;
1037
1038         if (dsi->driven_mode == TEGRA_DSI_DRIVEN_BY_HOST) {
1039                 dsi_control |= DSI_CTRL_HOST_DRIVEN;
1040                 host_dsi_control |= HOST_DSI_CTRL_HOST_DRIVEN;
1041                 max_threshold =
1042                         DSI_MAX_THRESHOLD_MAX_THRESHOLD(DSI_HOST_FIFO_DEPTH);
1043                 dsi->status.driven = DSI_DRIVEN_MODE_HOST;
1044         } else {
1045                 dsi_control |= DSI_CTRL_DC_DRIVEN;
1046                 host_dsi_control |= HOST_DSI_CTRL_DC_DRIVEN;
1047                 max_threshold =
1048                         DSI_MAX_THRESHOLD_MAX_THRESHOLD(DSI_VIDEO_FIFO_DEPTH);
1049                 dsi->status.driven = DSI_DRIVEN_MODE_DC;
1050         }
1051
1052         if (dsi->info.video_data_type == TEGRA_DSI_VIDEO_TYPE_COMMAND_MODE) {
1053                 dsi_control |= DSI_CTRL_CMD_MODE;
1054                 host_dsi_control |= HOST_DSI_CTRL_CMD_MODE;
1055                 dcs_cmd = DSI_DCS_CMDS_LT5_DCS_CMD(DSI_WRITE_MEMORY_START)|
1056                         DSI_DCS_CMDS_LT3_DCS_CMD(DSI_WRITE_MEMORY_CONTINUE);
1057                 dsi->status.vtype = DSI_VIDEO_TYPE_CMD_MODE;
1058
1059         } else {
1060                 dsi_control |= DSI_CTRL_VIDEO_MODE;
1061                 host_dsi_control |= HOST_DSI_CTRL_VIDEO_MODE;
1062                 dsi->status.vtype = DSI_VIDEO_TYPE_VIDEO_MODE;
1063         }
1064
1065         tegra_dsi_writel(dsi, max_threshold, DSI_MAX_THRESHOLD);
1066         tegra_dsi_writel(dsi, dcs_cmd, DSI_DCS_CMDS);
1067         tegra_dsi_writel(dsi, dsi_control, DSI_CONTROL);
1068         tegra_dsi_writel(dsi, host_dsi_control, DSI_HOST_DSI_CONTROL);
1069 }
1070
1071 static int tegra_dsi_init_hw(struct tegra_dc *dc,
1072                                                 struct tegra_dc_dsi_data *dsi)
1073 {
1074         u32 val;
1075         u32 i;
1076
1077         val = DSI_POWER_CONTROL_LEG_DSI_ENABLE(TEGRA_DSI_DISABLE);
1078         tegra_dsi_writel(dsi, val, DSI_POWER_CONTROL);
1079
1080         tegra_dsi_set_dsi_clk(dc, dsi, dsi->target_lp_clk_khz);
1081         if (dsi->info.dsi_instance) {
1082                 /* TODO:Set the misc register*/
1083         }
1084
1085         /* TODO: only need to change the timing for bta */
1086         tegra_dsi_set_phy_timing(dsi);
1087
1088         if (dsi->status.dc_stream == DSI_DC_STREAM_ENABLE)
1089                 tegra_dsi_stop_dc_stream(dc, dsi);
1090
1091         /* Initializing DSI registers */
1092         for (i = 0; i < ARRAY_SIZE(init_reg); i++)
1093                 tegra_dsi_writel(dsi, 0, init_reg[i]);
1094
1095         tegra_dsi_writel(dsi, dsi->dsi_control_val, DSI_CONTROL);
1096         /* Initialize DSI_PAD_CONTROL register. */
1097         val =   DSI_PAD_CONTROL_PAD_LPUPADJ(0x1) |
1098                 DSI_PAD_CONTROL_PAD_LPDNADJ(0x1) |
1099                 DSI_PAD_CONTROL_PAD_PREEMP_EN(0x1) |
1100                 DSI_PAD_CONTROL_PAD_SLEWDNADJ(0x6) |
1101                 DSI_PAD_CONTROL_PAD_SLEWUPADJ(0x6);
1102
1103         if (!dsi->ulpm) {
1104                 val |=  DSI_PAD_CONTROL_PAD_PDIO(0) |
1105                         DSI_PAD_CONTROL_PAD_PDIO_CLK(0) |
1106                         DSI_PAD_CONTROL_PAD_PULLDN_ENAB(TEGRA_DSI_DISABLE);
1107         } else {
1108                 val |=  DSI_PAD_CONTROL_PAD_PDIO(0x3) |
1109                         DSI_PAD_CONTROL_PAD_PDIO_CLK(0x1) |
1110                         DSI_PAD_CONTROL_PAD_PULLDN_ENAB(TEGRA_DSI_ENABLE);
1111         }
1112         tegra_dsi_writel(dsi, val, DSI_PAD_CONTROL);
1113
1114         val = DSI_POWER_CONTROL_LEG_DSI_ENABLE(TEGRA_DSI_ENABLE);
1115         tegra_dsi_writel(dsi, val, DSI_POWER_CONTROL);
1116
1117         while (tegra_dsi_readl(dsi, DSI_POWER_CONTROL) != val)
1118                 tegra_dsi_writel(dsi, val, DSI_POWER_CONTROL);
1119
1120         dsi->status.init = DSI_MODULE_INIT;
1121         dsi->status.lphs = DSI_LPHS_NOT_INIT;
1122         dsi->status.vtype = DSI_VIDEO_TYPE_NOT_INIT;
1123         dsi->status.driven = DSI_DRIVEN_MODE_NOT_INIT;
1124         dsi->status.clk_out = DSI_PHYCLK_OUT_DIS;
1125         dsi->status.clk_mode = DSI_PHYCLK_NOT_INIT;
1126         dsi->status.clk_burst = DSI_CLK_BURST_NOT_INIT;
1127         dsi->status.dc_stream = DSI_DC_STREAM_DISABLE;
1128
1129         return 0;
1130 }
1131
1132 static int tegra_dsi_set_to_lp_mode(struct tegra_dc *dc,
1133                                                 struct tegra_dc_dsi_data *dsi)
1134 {
1135         int     err;
1136
1137         if (dsi->status.init != DSI_MODULE_INIT) {
1138                 err = -EPERM;
1139                 goto fail;
1140         }
1141
1142         if (dsi->status.lphs == DSI_LPHS_IN_LP_MODE)
1143                 goto success;
1144
1145         if (dsi->status.dc_stream == DSI_DC_STREAM_ENABLE)
1146                 tegra_dsi_stop_dc_stream_at_frame_end(dc, dsi);
1147
1148         /* disable/enable hs clk according to enable_hs_clock_on_lp_cmd_mode */
1149         if ((dsi->status.clk_out == DSI_PHYCLK_OUT_EN) &&
1150                 (!dsi->info.enable_hs_clock_on_lp_cmd_mode))
1151                 tegra_dsi_hs_clk_out_disable(dc, dsi);
1152
1153         if (dsi->current_dsi_clk_khz != dsi->target_lp_clk_khz) {
1154                 tegra_dsi_set_dsi_clk(dc, dsi, dsi->target_lp_clk_khz);
1155                 tegra_dsi_set_timeout(dsi);
1156         }
1157
1158         tegra_dsi_set_control_reg_lp(dsi);
1159
1160         if ((dsi->status.clk_out == DSI_PHYCLK_OUT_DIS) &&
1161                 (dsi->info.enable_hs_clock_on_lp_cmd_mode))
1162                 tegra_dsi_hs_clk_out_enable_in_lp(dsi);
1163
1164 success:
1165         dsi->status.lphs = DSI_LPHS_IN_LP_MODE;
1166         err = 0;
1167 fail:
1168         return err;
1169 }
1170
1171 static int tegra_dsi_set_to_hs_mode(struct tegra_dc *dc,
1172                                                 struct tegra_dc_dsi_data *dsi)
1173 {
1174         int err;
1175
1176         if (dsi->status.init != DSI_MODULE_INIT) {
1177                 err = -EPERM;
1178                 goto fail;
1179         }
1180
1181         if (dsi->status.dc_stream == DSI_DC_STREAM_ENABLE)
1182                 tegra_dsi_stop_dc_stream_at_frame_end(dc, dsi);
1183
1184         if ((dsi->status.clk_out == DSI_PHYCLK_OUT_EN) &&
1185                 (!dsi->info.enable_hs_clock_on_lp_cmd_mode))
1186                 tegra_dsi_hs_clk_out_disable(dc, dsi);
1187
1188         if (dsi->current_dsi_clk_khz != dsi->target_hs_clk_khz) {
1189                 tegra_dsi_set_dsi_clk(dc, dsi, dsi->target_hs_clk_khz);
1190                 tegra_dsi_set_timeout(dsi);
1191         }
1192
1193         tegra_dsi_set_phy_timing(dsi);
1194
1195         if (dsi->driven_mode == TEGRA_DSI_DRIVEN_BY_DC) {
1196                 tegra_dsi_set_pkt_seq(dc, dsi);
1197                 tegra_dsi_set_pkt_length(dc, dsi);
1198                 tegra_dsi_set_sol_delay(dc, dsi);
1199                 tegra_dsi_set_dc_clk(dc, dsi);
1200         }
1201
1202         tegra_dsi_set_control_reg_hs(dsi);
1203
1204         if (dsi->status.clk_out == DSI_PHYCLK_OUT_DIS)
1205                 tegra_dsi_hs_clk_out_enable(dsi);
1206
1207         dsi->status.lphs = DSI_LPHS_IN_HS_MODE;
1208         err = 0;
1209 fail:
1210         return err;
1211 }
1212
1213 static bool tegra_dsi_is_controller_idle(struct tegra_dc_dsi_data *dsi)
1214 {
1215         u32 timeout = 0;
1216         bool retVal;
1217
1218         retVal = false;
1219         while (timeout <= DSI_MAX_COMMAND_DELAY_USEC) {
1220                 if (!tegra_dsi_readl(dsi, DSI_TRIGGER)) {
1221                         retVal = true;
1222                         break;
1223                 }
1224                 udelay(DSI_COMMAND_DELAY_STEPS_USEC);
1225                 timeout += DSI_COMMAND_DELAY_STEPS_USEC;
1226         }
1227
1228         return retVal;
1229 }
1230
1231 static int tegra_dsi_host_trigger(struct tegra_dc_dsi_data *dsi)
1232 {
1233         int status = 0;
1234
1235         if (tegra_dsi_readl(dsi, DSI_TRIGGER)) {
1236                 status = -EBUSY;
1237                 goto fail;
1238         }
1239
1240         tegra_dsi_writel(dsi,
1241                 DSI_TRIGGER_HOST_TRIGGER(TEGRA_DSI_ENABLE), DSI_TRIGGER);
1242
1243 #if DSI_USE_SYNC_POINTS
1244         status = tegra_dsi_syncpt(dsi);
1245         if (status < 0) {
1246                 printk(KERN_ERR "DSI syncpt for host trigger failed\n");
1247                 goto fail;
1248         }
1249 #else
1250         if (!tegra_dsi_is_controller_idle(dsi))
1251                 status = -EIO;
1252 #endif
1253
1254 fail:
1255         return status;
1256 }
1257
1258 static int _tegra_dsi_write_data(struct tegra_dc_dsi_data *dsi,
1259                                         u8 *pdata, u8 data_id, u16 data_len)
1260 {
1261         u8 virtual_channel;
1262         u8 *pval;
1263         u32 val;
1264         int err;
1265
1266         err = 0;
1267
1268         virtual_channel = dsi->info.virtual_channel <<
1269                                                 DSI_VIR_CHANNEL_BIT_POSITION;
1270
1271         /* always use hw for ecc */
1272         val = (virtual_channel | data_id) << 0 |
1273                         data_len << 8;
1274         tegra_dsi_writel(dsi, val, DSI_WR_DATA);
1275
1276         /* if pdata != NULL, pkt type is long pkt */
1277         if (pdata != NULL) {
1278                 while (data_len) {
1279                         if (data_len >= 4) {
1280                                 val = ((u32 *) pdata)[0];
1281                                 data_len -= 4;
1282                                 pdata += 4;
1283                         } else {
1284                                 val = 0;
1285                                 pval = (u8 *) &val;
1286                                 do
1287                                         *pval++ = *pdata++;
1288                                 while (--data_len);
1289                         }
1290                         tegra_dsi_writel(dsi, val, DSI_WR_DATA);
1291                 }
1292         }
1293
1294         err = tegra_dsi_host_trigger(dsi);
1295         if (err < 0)
1296                 printk(KERN_ERR "DSI host trigger failed\n");
1297
1298         return err;
1299 }
1300
1301 int tegra_dsi_write_data(struct tegra_dc *dc,
1302                                         struct tegra_dc_dsi_data *dsi,
1303                                         u8 *pdata, u8 data_id, u16 data_len)
1304 {
1305         bool switch_back_to_hs_mode;
1306         bool switch_back_to_dc_mode;
1307         int err;
1308
1309         err = 0;
1310         switch_back_to_hs_mode = false;
1311         switch_back_to_dc_mode = false;
1312
1313         if ((dsi->status.init != DSI_MODULE_INIT) ||
1314                 (dsi->status.lphs == DSI_LPHS_NOT_INIT)) {
1315                 err = -EPERM;
1316                 goto fail;
1317         }
1318
1319         if (!tegra_dsi_is_controller_idle(dsi)) {
1320                 err = -EBUSY;
1321                 goto fail;
1322         }
1323
1324         err = 0;
1325
1326         if (dsi->status.lphs == DSI_LPHS_IN_HS_MODE) {
1327                 if (dsi->info.hs_cmd_mode_supported) {
1328                         if (dsi->status.driven == DSI_DRIVEN_MODE_DC) {
1329                                 dsi->driven_mode = TEGRA_DSI_DRIVEN_BY_HOST;
1330                                 tegra_dsi_set_to_hs_mode(dc, dsi);
1331                                 switch_back_to_dc_mode = true;
1332                         }
1333                 } else {
1334                         tegra_dsi_set_to_lp_mode(dc, dsi);
1335                         switch_back_to_hs_mode = true;
1336                 }
1337         }
1338
1339         err = _tegra_dsi_write_data(dsi, pdata, data_id, data_len);
1340
1341
1342         if (switch_back_to_dc_mode)
1343                 dsi->driven_mode = TEGRA_DSI_DRIVEN_BY_DC;
1344         if (switch_back_to_dc_mode || switch_back_to_hs_mode)
1345                 tegra_dsi_set_to_hs_mode(dc, dsi);
1346
1347 fail:
1348         return err;
1349 }
1350 EXPORT_SYMBOL(tegra_dsi_write_data);
1351
1352 static int tegra_dsi_send_panel_cmd(struct tegra_dc *dc,
1353                                                 struct tegra_dc_dsi_data *dsi,
1354                                                 struct tegra_dsi_cmd *cmd,
1355                                                 u32 n_cmd)
1356 {
1357         u32 i;
1358         int err;
1359
1360         err = 0;
1361         for (i = 0; i < n_cmd; i++) {
1362                 struct tegra_dsi_cmd *cur_cmd;
1363                 cur_cmd = &cmd[i];
1364
1365                 if (cur_cmd->cmd_type == TEGRA_DSI_DELAY_MS)
1366                         mdelay(cur_cmd->sp_len_dly.delay_ms);
1367                 else {
1368                         err = tegra_dsi_write_data(dc, dsi,
1369                                                 cur_cmd->pdata,
1370                                                 cur_cmd->data_id,
1371                                                 cur_cmd->sp_len_dly.data_len);
1372                         if (err < 0)
1373                                 break;
1374                 }
1375         }
1376         return err;
1377 }
1378
1379 static int tegra_dsi_bta(struct tegra_dc_dsi_data *dsi)
1380 {
1381         u32 val;
1382         u32 poll_time;
1383         int err;
1384
1385         poll_time = 0;
1386         err = 0;
1387
1388         val = tegra_dsi_readl(dsi, DSI_HOST_DSI_CONTROL);
1389         val |= DSI_HOST_DSI_CONTROL_IMM_BTA(TEGRA_DSI_ENABLE);
1390         tegra_dsi_writel(dsi, val, DSI_HOST_DSI_CONTROL);
1391
1392 #if DSI_USE_SYNC_POINTS
1393         /* FIXME: Workaround for nvhost_syncpt_read */
1394         dsi->syncpt_val = nvhost_syncpt_update_min(
1395                         &dsi->dc->ndev->host->syncpt, dsi->syncpt_id);
1396
1397         val = DSI_INCR_SYNCPT_COND(OP_DONE) |
1398                 DSI_INCR_SYNCPT_INDX(dsi->syncpt_id);
1399         tegra_dsi_writel(dsi, val, DSI_INCR_SYNCPT);
1400
1401         /* TODO: Use interrupt rather than polling */
1402         err = nvhost_syncpt_wait(&dsi->dc->ndev->host->syncpt,
1403                 dsi->syncpt_id, dsi->syncpt_val + 1);
1404         if (err < 0)
1405                 printk(KERN_ERR "DSI sync point failure\n");
1406         else
1407                 (dsi->syncpt_val)++;
1408 #else
1409         while (poll_time <  DSI_STATUS_POLLING_DURATION_USEC) {
1410                 val = tegra_dsi_readl(dsi, DSI_HOST_DSI_CONTROL);
1411                 val &= DSI_HOST_DSI_CONTROL_IMM_BTA(TEGRA_DSI_ENABLE);
1412                 if (!val)
1413                         break;
1414                 udelay(DSI_STATUS_POLLING_DELAY_USEC);
1415                 poll_time += DSI_STATUS_POLLING_DELAY_USEC;
1416         }
1417         if (poll_time > DSI_STATUS_POLLING_DURATION_USEC)
1418                 err = -EBUSY;
1419 #endif
1420
1421         return err;
1422 }
1423
1424 static void tegra_dsi_read_fifo(struct tegra_dc *dc,
1425                         struct tegra_dc_dsi_data *dsi,
1426                         u32 rd_fifo_cnt,
1427                         u8 *read_fifo)
1428 {
1429         u32 val;
1430         u32 i;
1431
1432         /* Read data from FIFO */
1433         for (i = 0; i < rd_fifo_cnt; i++) {
1434                 val = tegra_dsi_readl(dsi, DSI_RD_DATA);
1435                 printk(KERN_INFO "Read data[%d]: 0x%x\n", i, val);
1436                 memcpy(read_fifo, &val, 4);
1437                 read_fifo += 4;
1438         }
1439
1440         /* Make sure all the data is read from the FIFO */
1441         val = tegra_dsi_readl(dsi, DSI_STATUS);
1442         val &= DSI_STATUS_RD_FIFO_COUNT(0x1f);
1443         if (val)
1444                 dev_err(&dc->ndev->dev, "DSI FIFO_RD_CNT not zero"
1445                 " even after reading FIFO_RD_CNT words from read fifo\n");
1446 }
1447
1448 static int tegra_dsi_parse_read_response(struct tegra_dc *dc,
1449                                 u32 rd_fifo_cnt, u8 *read_fifo)
1450 {
1451         int err;
1452         u32 payload_size;
1453
1454         payload_size = 0;
1455         err = 0;
1456
1457         printk(KERN_INFO "escape sequence[0x%x]\n", read_fifo[0]);
1458         switch (read_fifo[4] & 0xff) {
1459         case GEN_LONG_RD_RES:
1460                 /* Fall through */
1461         case DCS_LONG_RD_RES:
1462                 payload_size = (read_fifo[5] |
1463                                 (read_fifo[6] << 8)) & 0xFFFF;
1464                 printk(KERN_INFO "Long read response Packet\n"
1465                                 "payload_size[0x%x]\n", payload_size);
1466                 break;
1467         case GEN_1_BYTE_SHORT_RD_RES:
1468                 /* Fall through */
1469         case DCS_1_BYTE_SHORT_RD_RES:
1470                 payload_size = 1;
1471                 printk(KERN_INFO "Short read response Packet\n"
1472                         "payload_size[0x%x]\n", payload_size);
1473                 break;
1474         case GEN_2_BYTE_SHORT_RD_RES:
1475                 /* Fall through */
1476         case DCS_2_BYTE_SHORT_RD_RES:
1477                 payload_size = 2;
1478                 printk(KERN_INFO "Short read response Packet\n"
1479                         "payload_size[0x%x]\n", payload_size);
1480                 break;
1481         case ACK_ERR_RES:
1482                 payload_size = 2;
1483                 printk(KERN_INFO "Acknowledge error report response\n"
1484                         "Packet payload_size[0x%x]\n", payload_size);
1485                 break;
1486         default:
1487                 /*reading from RD_FIFO_COUNT*/
1488                 printk(KERN_INFO "Invalid read response payload_size\n");
1489                 err = -EINVAL;
1490                 break;
1491         }
1492         return err;
1493 }
1494
1495 int tegra_dsi_read_data(struct tegra_dc *dc,
1496                                 struct tegra_dc_dsi_data *dsi,
1497                                 u32 max_ret_payload_size,
1498                                 u32 panel_reg_addr, u8 *read_data)
1499 {
1500         u32 val;
1501         int err;
1502         u32 poll_time;
1503         u32 rd_fifo_cnt;
1504         bool switch_back_to_hs_mode;
1505         bool restart_dc_stream;
1506         bool switch_back_to_dc_mode;
1507
1508         err = 0;
1509         switch_back_to_hs_mode = false;
1510         restart_dc_stream = false;
1511         switch_back_to_dc_mode = false;
1512
1513         if ((dsi->status.init != DSI_MODULE_INIT) ||
1514                 (dsi->status.lphs == DSI_LPHS_NOT_INIT) ||
1515                 (dsi->status.driven == DSI_DRIVEN_MODE_NOT_INIT)) {
1516                 err = -EPERM;
1517                 goto fail;
1518         }
1519
1520         val = tegra_dsi_readl(dsi, DSI_STATUS);
1521         val &= DSI_STATUS_RD_FIFO_COUNT(0x1f);
1522         if (val) {
1523                 err = -EBUSY;
1524                 dev_err(&dc->ndev->dev, "DSI fifo count not zero\n");
1525                 goto fail;
1526         }
1527
1528         if (!tegra_dsi_is_controller_idle(dsi)) {
1529                 err = -EBUSY;
1530                 dev_err(&dc->ndev->dev, "DSI trigger bit is already set\n");
1531                 goto fail;
1532         }
1533
1534         if (dsi->status.lphs == DSI_LPHS_IN_HS_MODE) {
1535                 if (dsi->status.driven == DSI_DRIVEN_MODE_DC) {
1536                         if (dsi->status.dc_stream == DSI_DC_STREAM_ENABLE)
1537                                 restart_dc_stream = true;
1538                         dsi->driven_mode = TEGRA_DSI_DRIVEN_BY_HOST;
1539                         switch_back_to_dc_mode = true;
1540                         if (dsi->info.hs_cmd_mode_supported) {
1541                                 err = tegra_dsi_set_to_hs_mode(dc, dsi);
1542                                 if (err < 0) {
1543                                         dev_err(&dc->ndev->dev,
1544                                         "DSI failed to go to HS mode host driven\n");
1545                                         goto fail;
1546                                 }
1547                         }
1548                 }
1549                 if (!dsi->info.hs_cmd_mode_supported) {
1550                         err = tegra_dsi_set_to_lp_mode(dc, dsi);
1551                         if (err < 0) {
1552                                 dev_err(&dc->ndev->dev,
1553                                 "DSI failed to go to LP mode\n");
1554                                 goto fail;
1555                         }
1556                         switch_back_to_hs_mode = true;
1557                 }
1558         }
1559
1560         /* Set max return payload size in words */
1561         err = _tegra_dsi_write_data(dsi, NULL,
1562                 dsi_command_max_return_pkt_size,
1563                 max_ret_payload_size);
1564         if (err < 0) {
1565                 dev_err(&dc->ndev->dev,
1566                                 "DSI write failed\n");
1567                 goto fail;
1568         }
1569
1570         /* DCS to read given panel register */
1571         err = _tegra_dsi_write_data(dsi, NULL,
1572                 dsi_command_dcs_read_with_no_params,
1573                 panel_reg_addr);
1574         if (err < 0) {
1575                 dev_err(&dc->ndev->dev,
1576                                 "DSI write failed\n");
1577                 goto fail;
1578         }
1579
1580         err = tegra_dsi_bta(dsi);
1581         if (err < 0) {
1582                 dev_err(&dc->ndev->dev,
1583                         "DSI IMM BTA timeout\n");
1584                 goto fail;
1585         }
1586
1587         poll_time = 0;
1588         while (poll_time <  DSI_DELAY_FOR_READ_FIFO) {
1589                 mdelay(1);
1590                 val = tegra_dsi_readl(dsi, DSI_STATUS);
1591                 rd_fifo_cnt = val & DSI_STATUS_RD_FIFO_COUNT(0x1f);
1592                 if (rd_fifo_cnt << 2 > DSI_READ_FIFO_DEPTH)
1593                         dev_err(&dc->ndev->dev,
1594                         "DSI RD_FIFO_CNT is greater than RD_FIFO_DEPTH\n");
1595                         break;
1596                 poll_time++;
1597         }
1598
1599         if (rd_fifo_cnt == 0) {
1600                 dev_info(&dc->ndev->dev,
1601                         "DSI RD_FIFO_CNT is zero\n");
1602                 err = -EINVAL;
1603                 goto fail;
1604         }
1605
1606         if (val & DSI_STATUS_LB_UNDERFLOW(0x1) ||
1607                 val & DSI_STATUS_LB_OVERFLOW(0x1)) {
1608                 dev_err(&dc->ndev->dev,
1609                         "DSI overflow/underflow error\n");
1610                 err = -EINVAL;
1611                 goto fail;
1612         }
1613
1614         tegra_dsi_read_fifo(dc, dsi, rd_fifo_cnt, read_data);
1615
1616         err = tegra_dsi_parse_read_response(dc, rd_fifo_cnt, read_data);
1617 fail:
1618         if (switch_back_to_dc_mode)
1619                 dsi->driven_mode = TEGRA_DSI_DRIVEN_BY_DC;
1620         if (switch_back_to_dc_mode || switch_back_to_hs_mode)
1621                 tegra_dsi_set_to_hs_mode(dc, dsi);
1622         if (restart_dc_stream)
1623                 tegra_dsi_start_dc_stream(dc, dsi);
1624
1625         return err;
1626 }
1627 EXPORT_SYMBOL(tegra_dsi_read_data);
1628
1629 static int tegra_dsi_enter_ulpm(struct tegra_dc_dsi_data *dsi)
1630 {
1631         u32 val;
1632         int ret;
1633
1634         ret = 0;
1635
1636         val = tegra_dsi_readl(dsi, DSI_HOST_DSI_CONTROL);
1637         val &= ~DSI_HOST_DSI_CONTROL_ULTRA_LOW_POWER(3);
1638         val |= DSI_HOST_DSI_CONTROL_ULTRA_LOW_POWER(ENTER_ULPM);
1639         tegra_dsi_writel(dsi, val, DSI_HOST_DSI_CONTROL);
1640
1641 #if DSI_USE_SYNC_POINTS
1642         ret = tegra_dsi_syncpt(dsi);
1643         if (ret < 0) {
1644                 printk(KERN_ERR "DSI syncpt for ulpm enter failed\n");
1645                 goto fail;
1646         }
1647 #else
1648         /* TODO: Find exact delay required */
1649         mdelay(10);
1650 #endif
1651         dsi->ulpm = true;
1652 fail:
1653         return ret;
1654 }
1655
1656 static int tegra_dsi_exit_ulpm(struct tegra_dc_dsi_data *dsi)
1657 {
1658         u32 val;
1659         int ret;
1660
1661         ret = 0;
1662
1663         val = tegra_dsi_readl(dsi, DSI_HOST_DSI_CONTROL);
1664         val &= ~DSI_HOST_DSI_CONTROL_ULTRA_LOW_POWER(3);
1665         val |= DSI_HOST_DSI_CONTROL_ULTRA_LOW_POWER(EXIT_ULPM);
1666         tegra_dsi_writel(dsi, val, DSI_HOST_DSI_CONTROL);
1667
1668 #if DSI_USE_SYNC_POINTS
1669         ret = tegra_dsi_syncpt(dsi);
1670         if (ret < 0) {
1671                 printk(KERN_ERR "DSI syncpt for ulpm exit failed\n");
1672                 goto fail;
1673         }
1674 #else
1675         /* TODO: Find exact delay required */
1676         mdelay(10);
1677 #endif
1678         dsi->ulpm = false;
1679
1680         val = tegra_dsi_readl(dsi, DSI_HOST_DSI_CONTROL);
1681         val &= ~DSI_HOST_DSI_CONTROL_ULTRA_LOW_POWER(0x3);
1682         val |= DSI_HOST_DSI_CONTROL_ULTRA_LOW_POWER(NORMAL);
1683         tegra_dsi_writel(dsi, val, DSI_HOST_DSI_CONTROL);
1684 fail:
1685         return ret;
1686
1687 }
1688
1689 static void tegra_dc_dsi_enable(struct tegra_dc *dc)
1690 {
1691         struct tegra_dc_dsi_data *dsi = tegra_dc_get_outdata(dc);
1692         int err;
1693         u32 val;
1694
1695         tegra_dc_io_start(dc);
1696         mutex_lock(&dsi->lock);
1697
1698         /* Stop DC stream before configuring DSI registers
1699          * to avoid visible glitches on panel during transition
1700          * from bootloader to kernel driver
1701          */
1702         tegra_dsi_stop_dc_stream_at_frame_end(dc, dsi);
1703
1704         if (dsi->enabled) {
1705                 if (dsi->ulpm) {
1706                         if (tegra_dsi_exit_ulpm(dsi) < 0) {
1707                                 printk(KERN_ERR "DSI failed to exit ulpm\n");
1708                                 goto fail;
1709                         }
1710                 }
1711
1712                 if (dsi->info.panel_reset) {
1713                         err = tegra_dsi_send_panel_cmd(dc, dsi,
1714                                                         dsi->info.dsi_init_cmd,
1715                                                         dsi->info.n_init_cmd);
1716                         if (err < 0) {
1717                                 dev_err(&dc->ndev->dev,
1718                                 "dsi: error sending dsi init cmd\n");
1719                                 goto fail;
1720                         }
1721                 } else if (dsi->info.dsi_late_resume_cmd) {
1722                         err = tegra_dsi_send_panel_cmd(dc, dsi,
1723                                                 dsi->info.dsi_late_resume_cmd,
1724                                                 dsi->info.n_late_resume_cmd);
1725                         if (err < 0) {
1726                                 dev_err(&dc->ndev->dev,
1727                                 "dsi: error sending late resume cmd\n");
1728                                 goto fail;
1729                         }
1730                 }
1731         } else {
1732                 err = tegra_dsi_init_hw(dc, dsi);
1733                 if (err < 0) {
1734                         dev_err(&dc->ndev->dev,
1735                                 "dsi: not able to init dsi hardware\n");
1736                         goto fail;
1737                 }
1738
1739                 if (dsi->ulpm) {
1740                         if (tegra_dsi_enter_ulpm(dsi) < 0) {
1741                                 printk(KERN_ERR "DSI failed to enter ulpm\n");
1742                                 goto fail;
1743                         }
1744                         val = DSI_PAD_CONTROL_PAD_PDIO(0) |
1745                                 DSI_PAD_CONTROL_PAD_PDIO_CLK(0) |
1746                                 DSI_PAD_CONTROL_PAD_PULLDN_ENAB(TEGRA_DSI_DISABLE);
1747                         tegra_dsi_writel(dsi, val, DSI_PAD_CONTROL);
1748                         if (tegra_dsi_exit_ulpm(dsi) < 0) {
1749                                 printk(KERN_ERR "DSI failed to exit ulpm\n");
1750                                 goto fail;
1751                         }
1752                 }
1753
1754                 err = tegra_dsi_set_to_lp_mode(dc, dsi);
1755                 if (err < 0) {
1756                         dev_err(&dc->ndev->dev,
1757                                 "dsi: not able to set to lp mode\n");
1758                         goto fail;
1759                 }
1760
1761                 err = tegra_dsi_send_panel_cmd(dc, dsi, dsi->info.dsi_init_cmd,
1762                                                 dsi->info.n_init_cmd);
1763                 if (err < 0) {
1764                         dev_err(&dc->ndev->dev,
1765                                 "dsi: error while sending dsi init cmd\n");
1766                         goto fail;
1767                 }
1768
1769                 err = tegra_dsi_set_to_hs_mode(dc, dsi);
1770                 if (err < 0) {
1771                         dev_err(&dc->ndev->dev,
1772                                 "dsi: not able to set to hs mode\n");
1773                         goto fail;
1774                 }
1775
1776                 dsi->enabled = true;
1777         }
1778
1779         if (dsi->status.driven == DSI_DRIVEN_MODE_DC)
1780                 tegra_dsi_start_dc_stream(dc, dsi);
1781 fail:
1782         mutex_unlock(&dsi->lock);
1783         tegra_dc_io_end(dc);
1784 }
1785
1786 static void _tegra_dc_dsi_init(struct tegra_dc *dc)
1787 {
1788         struct tegra_dc_dsi_data *dsi = tegra_dc_get_outdata(dc);
1789
1790         tegra_dsi_init_sw(dc, dsi);
1791         /* TODO: Configure the CSI pad configuration */
1792 }
1793
1794 static int tegra_dc_dsi_cp_p_cmd(struct tegra_dsi_cmd *src,
1795                                         struct tegra_dsi_cmd *dst, u16 n_cmd)
1796 {
1797         u16 i;
1798         u16 len;
1799
1800         memcpy(dst, src, sizeof(*dst) * n_cmd);
1801
1802         for (i = 0; i < n_cmd; i++)
1803                 if (src[i].pdata) {
1804                         len = sizeof(*src[i].pdata) *
1805                                         src[i].sp_len_dly.data_len;
1806                         dst[i].pdata = kzalloc(len, GFP_KERNEL);
1807                         if (!dst[i].pdata)
1808                                 goto free_cmd_pdata;
1809                         memcpy(dst[i].pdata, src[i].pdata, len);
1810                 }
1811
1812         return 0;
1813
1814 free_cmd_pdata:
1815         for (--i; i >= 0; i--)
1816                 if (dst[i].pdata)
1817                         kfree(dst[i].pdata);
1818         return -ENOMEM;
1819 }
1820
1821 static int tegra_dc_dsi_cp_info(struct tegra_dc_dsi_data *dsi,
1822                                                 struct tegra_dsi_out *p_dsi)
1823 {
1824         struct tegra_dsi_cmd *p_init_cmd;
1825         struct tegra_dsi_cmd *p_early_suspend_cmd;
1826         struct tegra_dsi_cmd *p_late_resume_cmd;
1827         struct tegra_dsi_cmd *p_suspend_cmd;
1828         int err;
1829
1830         if (p_dsi->n_data_lanes > MAX_DSI_DATA_LANES)
1831                 return -EINVAL;
1832
1833         p_init_cmd = kzalloc(sizeof(*p_init_cmd) *
1834                                 p_dsi->n_init_cmd, GFP_KERNEL);
1835         if (!p_init_cmd)
1836                 return -ENOMEM;
1837
1838         if (p_dsi->dsi_early_suspend_cmd) {
1839                 p_early_suspend_cmd = kzalloc(sizeof(*p_early_suspend_cmd) *
1840                                         p_dsi->n_early_suspend_cmd,
1841                                         GFP_KERNEL);
1842                 if (!p_early_suspend_cmd) {
1843                         err = -ENOMEM;
1844                         goto err_free_init_cmd;
1845                 }
1846         }
1847
1848         if (p_dsi->dsi_late_resume_cmd) {
1849                 p_late_resume_cmd = kzalloc(sizeof(*p_late_resume_cmd) *
1850                                         p_dsi->n_late_resume_cmd,
1851                                         GFP_KERNEL);
1852                 if (!p_late_resume_cmd) {
1853                         err = -ENOMEM;
1854                         goto err_free_p_early_suspend_cmd;
1855                 }
1856         }
1857
1858         p_suspend_cmd = kzalloc(sizeof(*p_suspend_cmd) * p_dsi->n_suspend_cmd,
1859                                 GFP_KERNEL);
1860         if (!p_suspend_cmd) {
1861                 err = -ENOMEM;
1862                 goto err_free_p_late_resume_cmd;
1863         }
1864
1865         memcpy(&dsi->info, p_dsi, sizeof(dsi->info));
1866
1867         /* Copy panel init cmd */
1868         err = tegra_dc_dsi_cp_p_cmd(p_dsi->dsi_init_cmd,
1869                                                 p_init_cmd, p_dsi->n_init_cmd);
1870         if (err < 0)
1871                 goto err_free;
1872         dsi->info.dsi_init_cmd = p_init_cmd;
1873
1874         /* Copy panel early suspend cmd */
1875         if (p_dsi->dsi_early_suspend_cmd) {
1876                 err = tegra_dc_dsi_cp_p_cmd(p_dsi->dsi_early_suspend_cmd,
1877                                         p_early_suspend_cmd,
1878                                         p_dsi->n_early_suspend_cmd);
1879                 if (err < 0)
1880                         goto err_free;
1881                 dsi->info.dsi_early_suspend_cmd = p_early_suspend_cmd;
1882         }
1883
1884         /* Copy panel late resume cmd */
1885         if (p_dsi->dsi_late_resume_cmd) {
1886                 err = tegra_dc_dsi_cp_p_cmd(p_dsi->dsi_late_resume_cmd,
1887                                                 p_late_resume_cmd,
1888                                                 p_dsi->n_late_resume_cmd);
1889                 if (err < 0)
1890                         goto err_free;
1891                 dsi->info.dsi_late_resume_cmd = p_late_resume_cmd;
1892         }
1893
1894         /* Copy panel suspend cmd */
1895         err = tegra_dc_dsi_cp_p_cmd(p_dsi->dsi_suspend_cmd, p_suspend_cmd,
1896                                         p_dsi->n_suspend_cmd);
1897         if (err < 0)
1898                 goto err_free;
1899         dsi->info.dsi_suspend_cmd = p_suspend_cmd;
1900
1901         if (!dsi->info.panel_reset_timeout_msec)
1902                 dsi->info.panel_reset_timeout_msec =
1903                                                 DEFAULT_PANEL_RESET_TIMEOUT;
1904
1905         if (!dsi->info.panel_buffer_size_byte)
1906                 dsi->info.panel_buffer_size_byte = DEFAULT_PANEL_BUFFER_BYTE;
1907
1908         if (!dsi->info.max_panel_freq_khz) {
1909                 dsi->info.max_panel_freq_khz = DEFAULT_MAX_DSI_PHY_CLK_KHZ;
1910
1911                 if (dsi->info.video_burst_mode >
1912                                 TEGRA_DSI_VIDEO_NONE_BURST_MODE_WITH_SYNC_END){
1913                         dev_err(&dsi->dc->ndev->dev, "DSI: max_panel_freq_khz"
1914                                         "is not set for DSI burst mode.\n");
1915                         dsi->info.video_burst_mode =
1916                                 TEGRA_DSI_VIDEO_BURST_MODE_LOWEST_SPEED;
1917                 }
1918         }
1919
1920         if (!dsi->info.lp_cmd_mode_freq_khz)
1921                 dsi->info.lp_cmd_mode_freq_khz = DEFAULT_LP_CMD_MODE_CLK_KHZ;
1922
1923         if (!dsi->info.chip_id || !dsi->info.chip_rev)
1924                 printk(KERN_WARNING "DSI: Failed to get chip info\n");
1925
1926         /* host mode is for testing only*/
1927         dsi->driven_mode = TEGRA_DSI_DRIVEN_BY_DC;
1928         return 0;
1929
1930 err_free:
1931         kfree(p_suspend_cmd);
1932 err_free_p_late_resume_cmd:
1933         kfree(p_late_resume_cmd);
1934 err_free_p_early_suspend_cmd:
1935         kfree(p_early_suspend_cmd);
1936 err_free_init_cmd:
1937         kfree(p_init_cmd);
1938         return err;
1939 }
1940
1941 static int tegra_dc_dsi_init(struct tegra_dc *dc)
1942 {
1943         struct tegra_dc_dsi_data *dsi;
1944         struct resource *res;
1945         struct resource *base_res;
1946         void __iomem *base;
1947         struct clk *dc_clk = NULL;
1948         struct clk *dsi_clk = NULL;
1949         struct tegra_dsi_out *dsi_pdata;
1950         int err;
1951
1952         err = 0;
1953
1954         dsi = kzalloc(sizeof(*dsi), GFP_KERNEL);
1955         if (!dsi)
1956                 return -ENOMEM;
1957
1958         res = nvhost_get_resource_byname(dc->ndev, IORESOURCE_MEM,
1959                                         "dsi_regs");
1960         if (!res) {
1961                 dev_err(&dc->ndev->dev, "dsi: no mem resource\n");
1962                 err = -ENOENT;
1963                 goto err_free_dsi;
1964         }
1965
1966         base_res = request_mem_region(res->start, resource_size(res),
1967                                 dc->ndev->name);
1968         if (!base_res) {
1969                 dev_err(&dc->ndev->dev, "dsi: request_mem_region failed\n");
1970                 err = -EBUSY;
1971                 goto err_free_dsi;
1972         }
1973
1974         base = ioremap(res->start, resource_size(res));
1975         if (!base) {
1976                 dev_err(&dc->ndev->dev, "dsi: registers can't be mapped\n");
1977                 err = -EBUSY;
1978                 goto err_release_regs;
1979         }
1980
1981         dsi_pdata = dc->pdata->default_out->dsi;
1982         if (!dsi_pdata) {
1983                 dev_err(&dc->ndev->dev, "dsi: dsi data not available\n");
1984                 goto err_release_regs;
1985         }
1986
1987         if (dsi_pdata->dsi_instance)
1988                 dsi_clk = clk_get(&dc->ndev->dev, "dsib");
1989         else
1990                 dsi_clk = clk_get(&dc->ndev->dev, "dsia");
1991
1992         if (IS_ERR_OR_NULL(dsi_clk)) {
1993                 dev_err(&dc->ndev->dev, "dsi: can't get clock\n");
1994                 err = -EBUSY;
1995                 goto err_release_regs;
1996         }
1997
1998         dc_clk = clk_get_sys(dev_name(&dc->ndev->dev), NULL);
1999         if (IS_ERR_OR_NULL(dc_clk)) {
2000                 dev_err(&dc->ndev->dev, "dsi: dc clock %s unavailable\n",
2001                         dev_name(&dc->ndev->dev));
2002                 err = -EBUSY;
2003                 goto err_clk_put;
2004         }
2005
2006         mutex_init(&dsi->lock);
2007         dsi->dc = dc;
2008         dsi->base = base;
2009         dsi->base_res = base_res;
2010         dsi->dc_clk = dc_clk;
2011         dsi->dsi_clk = dsi_clk;
2012
2013         err = tegra_dc_dsi_cp_info(dsi, dsi_pdata);
2014         if (err < 0)
2015                 goto err_dsi_data;
2016
2017         tegra_dc_set_outdata(dc, dsi);
2018         _tegra_dc_dsi_init(dc);
2019
2020         return 0;
2021
2022 err_dsi_data:
2023 err_clk_put:
2024         clk_put(dsi_clk);
2025 err_release_regs:
2026         release_resource(base_res);
2027 err_free_dsi:
2028         kfree(dsi);
2029
2030         return err;
2031 }
2032
2033 static void tegra_dc_dsi_destroy(struct tegra_dc *dc)
2034 {
2035         struct tegra_dc_dsi_data *dsi = tegra_dc_get_outdata(dc);
2036         u16 i;
2037         u32 val;
2038
2039         mutex_lock(&dsi->lock);
2040
2041         /* free up the pdata*/
2042         for (i = 0; i < dsi->info.n_init_cmd; i++) {
2043                 if (dsi->info.dsi_init_cmd[i].pdata)
2044                         kfree(dsi->info.dsi_init_cmd[i].pdata);
2045         }
2046         kfree(dsi->info.dsi_init_cmd);
2047
2048         /* Disable dc stream*/
2049         if (dsi->status.dc_stream == DSI_DC_STREAM_ENABLE)
2050                 tegra_dsi_stop_dc_stream(dc, dsi);
2051
2052         /* Disable dsi phy clock*/
2053         if (dsi->status.clk_out == DSI_PHYCLK_OUT_EN)
2054                 tegra_dsi_hs_clk_out_disable(dc, dsi);
2055
2056         val = DSI_POWER_CONTROL_LEG_DSI_ENABLE(TEGRA_DSI_DISABLE);
2057         tegra_dsi_writel(dsi, val, DSI_POWER_CONTROL);
2058
2059         iounmap(dsi->base);
2060         release_resource(dsi->base_res);
2061
2062         clk_put(dsi->dc_clk);
2063         clk_put(dsi->dsi_clk);
2064
2065         mutex_unlock(&dsi->lock);
2066
2067         mutex_destroy(&dsi->lock);
2068         kfree(dsi);
2069 }
2070
2071 static void tegra_dc_dsi_disable(struct tegra_dc *dc)
2072 {
2073         int err;
2074         u32 val;
2075         struct clk *base_clk;
2076         struct tegra_dc_dsi_data *dsi = tegra_dc_get_outdata(dc);
2077
2078         tegra_dc_io_start(dc);
2079         mutex_lock(&dsi->lock);
2080
2081         if (dsi->status.dc_stream == DSI_DC_STREAM_ENABLE)
2082                 tegra_dsi_stop_dc_stream_at_frame_end(dc, dsi);
2083
2084         if (dsi->info.power_saving_suspend) {
2085                 if (!dsi->enabled)
2086                         goto fail;
2087
2088                 err = tegra_dsi_set_to_lp_mode(dc, dsi);
2089                 if (err < 0) {
2090                         dev_err(&dc->ndev->dev,
2091                         "DSI failed to go to LP mode\n");
2092                         goto fail;
2093                 }
2094
2095                 err = tegra_dsi_send_panel_cmd(dc, dsi,
2096                                 dsi->info.dsi_suspend_cmd,
2097                                 dsi->info.n_suspend_cmd);
2098                 if (err < 0) {
2099                         dev_err(&dc->ndev->dev,
2100                                 "dsi: Error sending suspend cmd\n");
2101                         goto fail;
2102                 }
2103
2104                 if (!dsi->ulpm) {
2105                         if (tegra_dsi_enter_ulpm(dsi) < 0)
2106                                 printk(KERN_ERR "DSI failed to enter ulpm\n");
2107                 }
2108
2109                 /* Suspend pad */
2110                 val = tegra_dsi_readl(dsi, DSI_PAD_CONTROL);
2111                 val = DSI_PAD_CONTROL_PAD_PDIO(0x3) |
2112                         DSI_PAD_CONTROL_PAD_PDIO_CLK(0x1) |
2113                         DSI_PAD_CONTROL_PAD_PULLDN_ENAB(TEGRA_DSI_ENABLE);
2114                 tegra_dsi_writel(dsi, val, DSI_PAD_CONTROL);
2115
2116                 /* Suspend core-logic */
2117                 val = DSI_POWER_CONTROL_LEG_DSI_ENABLE(TEGRA_DSI_DISABLE);
2118                 tegra_dsi_writel(dsi, val, DSI_POWER_CONTROL);
2119
2120                 /* Disable phy clock */
2121                 base_clk = clk_get_parent(dsi->dsi_clk);
2122                 if (dsi->info.dsi_instance)
2123                         tegra_clk_cfg_ex(base_clk,
2124                                         TEGRA_CLK_PLLD_CSI_OUT_ENB,
2125                                         0);
2126                 else
2127                         tegra_clk_cfg_ex(base_clk,
2128                                         TEGRA_CLK_PLLD_DSI_OUT_ENB,
2129                                         0);
2130
2131                 /* Disable DSI source clock */
2132                 clk_disable(dsi->dsi_clk);
2133                 dsi->clk_ref = false;
2134                 dsi->enabled = false;
2135         } else {
2136                 if (dsi->info.dsi_early_suspend_cmd) {
2137                         err = tegra_dsi_send_panel_cmd(dc, dsi,
2138                                 dsi->info.dsi_early_suspend_cmd,
2139                                 dsi->info.n_early_suspend_cmd);
2140                         if (err < 0) {
2141                                 dev_err(&dc->ndev->dev,
2142                                 "dsi: Error sending early suspend cmd\n");
2143                                 goto fail;
2144                         }
2145                 }
2146
2147                 if (!dsi->ulpm) {
2148                         if (tegra_dsi_enter_ulpm(dsi) < 0)
2149                                 printk(KERN_ERR "DSI failed to enter ulpm\n");
2150                 }
2151         }
2152
2153 fail:
2154         mutex_unlock(&dsi->lock);
2155         tegra_dc_io_end(dc);
2156 }
2157
2158 #ifdef CONFIG_PM
2159 static void tegra_dc_dsi_suspend(struct tegra_dc *dc)
2160 {
2161         struct tegra_dc_dsi_data *dsi;
2162         int err;
2163         u32 val;
2164
2165         dsi = tegra_dc_get_outdata(dc);
2166
2167         tegra_dc_io_start(dc);
2168         mutex_lock(&dsi->lock);
2169
2170         if (!dsi->enabled)
2171                 goto fail;
2172
2173         if (!dsi->info.power_saving_suspend) {
2174                 if (dsi->ulpm) {
2175                         if (tegra_dsi_exit_ulpm(dsi) < 0) {
2176                                 printk(KERN_ERR "DSI failed to exit ulpm");
2177                                 goto fail;
2178                         }
2179                 }
2180
2181                 /* Suspend Panel */
2182                 err = tegra_dsi_send_panel_cmd(dc, dsi,
2183                                 dsi->info.dsi_suspend_cmd,
2184                                 dsi->info.n_suspend_cmd);
2185                 if (err < 0) {
2186                         dev_err(&dc->ndev->dev,
2187                                 "dsi: Error sending suspend cmd\n");
2188                         goto fail;
2189                 }
2190                 if (!dsi->ulpm) {
2191                         if (tegra_dsi_enter_ulpm(dsi) < 0) {
2192                                 printk(KERN_ERR "DSI failed to enter ulpm\n");
2193                                 goto fail;
2194                         }
2195                 }
2196
2197                 /* Suspend pad */
2198                 val = tegra_dsi_readl(dsi, DSI_PAD_CONTROL);
2199                 val = DSI_PAD_CONTROL_PAD_PDIO(0x3) |
2200                         DSI_PAD_CONTROL_PAD_PDIO_CLK(0x1) |
2201                         DSI_PAD_CONTROL_PAD_PULLDN_ENAB(TEGRA_DSI_ENABLE);
2202                 tegra_dsi_writel(dsi, val, DSI_PAD_CONTROL);
2203
2204                 /* Suspend core-logic */
2205                 val = DSI_POWER_CONTROL_LEG_DSI_ENABLE(TEGRA_DSI_DISABLE);
2206                 tegra_dsi_writel(dsi, val, DSI_POWER_CONTROL);
2207
2208                 dsi->enabled = false;
2209
2210                 clk_disable(dsi->dsi_clk);
2211                 dsi->clk_ref = false;
2212         }
2213 fail:
2214         mutex_unlock(&dsi->lock);
2215         tegra_dc_io_end(dc);
2216 }
2217
2218 static void tegra_dc_dsi_resume(struct tegra_dc *dc)
2219 {
2220         /* Not required since tegra_dc_dsi_enable
2221          * will reconfigure the controller from scratch
2222          */
2223 }
2224 #endif
2225
2226 struct tegra_dc_out_ops tegra_dc_dsi_ops = {
2227         .init = tegra_dc_dsi_init,
2228         .destroy = tegra_dc_dsi_destroy,
2229         .enable = tegra_dc_dsi_enable,
2230         .disable = tegra_dc_dsi_disable,
2231 #ifdef CONFIG_PM
2232         .suspend = tegra_dc_dsi_suspend,
2233         .resume = tegra_dc_dsi_resume,
2234 #endif
2235 };