video: tegra: dsi: Adjust two CSI registers in DSI module.
[linux-2.6.git] / drivers / video / tegra / dc / dsi.c
1 /*
2  * drivers/video/tegra/dc/dsi.c
3  *
4  * Copyright (c) 2011, NVIDIA Corporation.
5  *
6  * This software is licensed under the terms of the GNU General Public
7  * License version 2, as published by the Free Software Foundation, and
8  * may be copied, distributed, and modified under those terms.
9  *
10  * This program is distributed in the hope that it will be useful,
11  * but WITHOUT ANY WARRANTY; without even the implied warranty of
12  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
13  * GNU General Public License for more details.
14  *
15  */
16
17 #include <linux/clk.h>
18 #include <linux/delay.h>
19 #include <linux/err.h>
20 #include <linux/fb.h>
21 #include <linux/gpio.h>
22 #include <linux/interrupt.h>
23 #include <linux/kernel.h>
24 #include <linux/slab.h>
25 #include <linux/spinlock.h>
26 #include <linux/workqueue.h>
27
28 #include <mach/clk.h>
29 #include <mach/dc.h>
30 #include <mach/fb.h>
31 #include <mach/csi.h>
32 #include <linux/nvhost.h>
33 #include <../gpio-names.h>
34
35 #include "dc_reg.h"
36 #include "dc_priv.h"
37 #include "dsi_regs.h"
38 #include "dsi.h"
39
40 #define DSI_USE_SYNC_POINTS             1
41
42 #define DSI_STOP_DC_DURATION_MSEC       1000
43
44 #define DSI_MODULE_NOT_INIT             0x0
45 #define DSI_MODULE_INIT                 0x1
46
47 #define DSI_LPHS_NOT_INIT               0x0
48 #define DSI_LPHS_IN_LP_MODE             0x1
49 #define DSI_LPHS_IN_HS_MODE             0x2
50
51 #define DSI_VIDEO_TYPE_NOT_INIT         0x0
52 #define DSI_VIDEO_TYPE_VIDEO_MODE       0x1
53 #define DSI_VIDEO_TYPE_CMD_MODE         0x2
54
55 #define DSI_DRIVEN_MODE_NOT_INIT        0x0
56 #define DSI_DRIVEN_MODE_DC              0x1
57 #define DSI_DRIVEN_MODE_HOST            0x2
58
59 #define DSI_PHYCLK_OUT_DIS              0x0
60 #define DSI_PHYCLK_OUT_EN               0x1
61
62 #define DSI_PHYCLK_NOT_INIT             0x0
63 #define DSI_PHYCLK_CONTINUOUS           0x1
64 #define DSI_PHYCLK_TX_ONLY              0x2
65
66 #define DSI_CLK_BURST_NOT_INIT          0x0
67 #define DSI_CLK_BURST_NONE_BURST        0x1
68 #define DSI_CLK_BURST_BURST_MODE        0x2
69
70 #define DSI_DC_STREAM_DISABLE           0x0
71 #define DSI_DC_STREAM_ENABLE            0x1
72
73 #define DSI_LP_OP_NOT_INIT              0x0
74 #define DSI_LP_OP_WRITE                 0x1
75 #define DSI_LP_OP_READ                  0x2
76
77 struct dsi_status {
78         unsigned init:2;
79
80         unsigned lphs:2;
81
82         unsigned vtype:2;
83         unsigned driven:2;
84
85         unsigned clk_out:2;
86         unsigned clk_mode:2;
87         unsigned clk_burst:2;
88
89         unsigned lp_op:2;
90
91         unsigned dc_stream:1;
92 };
93
94 /* source of video data */
95 enum {
96         TEGRA_DSI_DRIVEN_BY_DC,
97         TEGRA_DSI_DRIVEN_BY_HOST,
98 };
99
100 struct tegra_dc_dsi_data {
101         struct tegra_dc *dc;
102         void __iomem *base;
103         struct resource *base_res;
104
105         struct clk *dc_clk;
106         struct clk *dsi_clk;
107         bool clk_ref;
108
109         struct mutex lock;
110
111         /* data from board info */
112         struct tegra_dsi_out info;
113
114         struct dsi_status status;
115
116         u8 driven_mode;
117         u8 controller_index;
118
119         u8 pixel_scaler_mul;
120         u8 pixel_scaler_div;
121
122         u32 default_shift_clk_div;
123         u32 default_pixel_clk_khz;
124         u32 default_hs_clk_khz;
125
126         u32 shift_clk_div;
127         u32 target_hs_clk_khz;
128         u32 target_lp_clk_khz;
129
130         u32 syncpt_id;
131         u32 syncpt_val;
132
133         u16 current_bit_clk_ns;
134         u32 current_dsi_clk_khz;
135
136         u32 dsi_control_val;
137
138         bool ulpm;
139         bool enabled;
140 };
141
142 const u32 dsi_pkt_seq_reg[NUMOF_PKT_SEQ] = {
143         DSI_PKT_SEQ_0_LO,
144         DSI_PKT_SEQ_0_HI,
145         DSI_PKT_SEQ_1_LO,
146         DSI_PKT_SEQ_1_HI,
147         DSI_PKT_SEQ_2_LO,
148         DSI_PKT_SEQ_2_HI,
149         DSI_PKT_SEQ_3_LO,
150         DSI_PKT_SEQ_3_HI,
151         DSI_PKT_SEQ_4_LO,
152         DSI_PKT_SEQ_4_HI,
153         DSI_PKT_SEQ_5_LO,
154         DSI_PKT_SEQ_5_HI,
155 };
156
157 const u32 dsi_pkt_seq_video_non_burst_syne[NUMOF_PKT_SEQ] = {
158         PKT_ID0(CMD_VS) | PKT_LEN0(0) | PKT_ID1(CMD_EOT) | PKT_LEN1(0) | PKT_LP,
159         0,
160         PKT_ID0(CMD_VE) | PKT_LEN0(0) | PKT_ID1(CMD_EOT) | PKT_LEN1(0) | PKT_LP,
161         0,
162         PKT_ID0(CMD_HS) | PKT_LEN0(0) | PKT_ID1(CMD_EOT) | PKT_LEN1(0) | PKT_LP,
163         0,
164         PKT_ID0(CMD_HS) | PKT_LEN0(0) | PKT_ID1(CMD_BLNK) | PKT_LEN1(1) |
165         PKT_ID2(CMD_HE) | PKT_LEN2(0),
166         PKT_ID3(CMD_BLNK) | PKT_LEN3(2) | PKT_ID4(CMD_RGB) | PKT_LEN4(3) |
167         PKT_ID5(CMD_BLNK) | PKT_LEN5(4),
168         PKT_ID0(CMD_HS) | PKT_LEN0(0) | PKT_ID1(CMD_EOT) | PKT_LEN1(0) | PKT_LP,
169         0,
170         PKT_ID0(CMD_HS) | PKT_LEN0(0) | PKT_ID1(CMD_BLNK) | PKT_LEN1(1) |
171         PKT_ID2(CMD_HE) | PKT_LEN2(0),
172         PKT_ID3(CMD_BLNK) | PKT_LEN3(2) | PKT_ID4(CMD_RGB) | PKT_LEN4(3) |
173         PKT_ID5(CMD_BLNK) | PKT_LEN5(4),
174 };
175
176 const u32 dsi_pkt_seq_video_non_burst[NUMOF_PKT_SEQ] = {
177         PKT_ID0(CMD_VS) | PKT_LEN0(0) | PKT_ID1(CMD_EOT) | PKT_LEN1(0) | PKT_LP,
178         0,
179         PKT_ID0(CMD_HS) | PKT_LEN0(0) | PKT_ID1(CMD_EOT) | PKT_LEN1(0) | PKT_LP,
180         0,
181         PKT_ID0(CMD_HS) | PKT_LEN0(0) | PKT_ID1(CMD_EOT) | PKT_LEN1(0) | PKT_LP,
182         0,
183         PKT_ID0(CMD_HS) | PKT_LEN0(0) | PKT_ID1(CMD_BLNK) | PKT_LEN1(2) |
184         PKT_ID2(CMD_RGB) | PKT_LEN2(3),
185         PKT_ID3(CMD_BLNK) | PKT_LEN3(4),
186         PKT_ID0(CMD_HS) | PKT_LEN0(0) | PKT_ID1(CMD_EOT) | PKT_LEN1(0) | PKT_LP,
187         0,
188         PKT_ID0(CMD_HS) | PKT_LEN0(0) | PKT_ID1(CMD_BLNK) | PKT_LEN1(2) |
189         PKT_ID2(CMD_RGB) | PKT_LEN2(3),
190         PKT_ID3(CMD_BLNK) | PKT_LEN3(4),
191 };
192
193 static const u32 dsi_pkt_seq_video_burst[NUMOF_PKT_SEQ] = {
194         PKT_ID0(CMD_VS) | PKT_LEN0(0) | PKT_ID1(CMD_EOT) | PKT_LEN1(7) | PKT_LP,
195         0,
196         PKT_ID0(CMD_HS) | PKT_LEN0(0) | PKT_ID1(CMD_EOT) | PKT_LEN1(7) | PKT_LP,
197         0,
198         PKT_ID0(CMD_HS) | PKT_LEN0(0) | PKT_ID1(CMD_EOT) | PKT_LEN1(7) | PKT_LP,
199         0,
200         PKT_ID0(CMD_HS) | PKT_LEN0(0) | PKT_ID1(CMD_BLNK) | PKT_LEN1(2)|
201         PKT_ID2(CMD_RGB) | PKT_LEN2(3) | PKT_LP,
202         PKT_ID0(CMD_EOT) | PKT_LEN0(7),
203         PKT_ID0(CMD_HS) | PKT_LEN0(0) | PKT_ID1(CMD_EOT) | PKT_LEN1(7) | PKT_LP,
204         0,
205         PKT_ID0(CMD_HS) | PKT_LEN0(0) | PKT_ID1(CMD_BLNK) | PKT_LEN1(2)|
206         PKT_ID2(CMD_RGB) | PKT_LEN2(3) | PKT_LP,
207         PKT_ID0(CMD_EOT) | PKT_LEN0(7),
208 };
209
210 static const u32 dsi_pkt_seq_video_burst_no_eot[NUMOF_PKT_SEQ] = {
211         PKT_ID0(CMD_VS) | PKT_LEN0(0) | PKT_ID1(CMD_EOT) | PKT_LEN1(0) | PKT_LP,
212         0,
213         PKT_ID0(CMD_HS) | PKT_LEN0(0) | PKT_ID1(CMD_EOT) | PKT_LEN1(0) | PKT_LP,
214         0,
215         PKT_ID0(CMD_HS) | PKT_LEN0(0) | PKT_ID1(CMD_EOT) | PKT_LEN1(0) | PKT_LP,
216         0,
217         PKT_ID0(CMD_HS) | PKT_LEN0(0) | PKT_ID1(CMD_BLNK) | PKT_LEN1(2)|
218         PKT_ID2(CMD_RGB) | PKT_LEN2(3) | PKT_LP,
219         PKT_ID0(CMD_EOT) | PKT_LEN0(0),
220         PKT_ID0(CMD_HS) | PKT_LEN0(0) | PKT_ID1(CMD_EOT) | PKT_LEN1(0) | PKT_LP,
221         0,
222         PKT_ID0(CMD_HS) | PKT_LEN0(0) | PKT_ID1(CMD_BLNK) | PKT_LEN1(2)|
223         PKT_ID2(CMD_RGB) | PKT_LEN2(3) | PKT_LP,
224         PKT_ID0(CMD_EOT) | PKT_LEN0(0),
225 };
226
227 /* TODO: verify with hw about this format */
228 const u32 dsi_pkt_seq_cmd_mode[NUMOF_PKT_SEQ] = {
229         0,
230         0,
231         0,
232         0,
233         0,
234         0,
235         PKT_ID0(CMD_LONGW) | PKT_LEN0(3) | PKT_ID1(CMD_EOT) | PKT_LEN1(7),
236         0,
237         0,
238         0,
239         PKT_ID0(CMD_LONGW) | PKT_LEN0(3) | PKT_ID1(CMD_EOT) | PKT_LEN1(7),
240         0,
241 };
242
243 const u32 init_reg[] = {
244         DSI_INT_ENABLE,
245         DSI_INT_STATUS,
246         DSI_INT_MASK,
247         DSI_INIT_SEQ_DATA_0,
248         DSI_INIT_SEQ_DATA_1,
249         DSI_INIT_SEQ_DATA_2,
250         DSI_INIT_SEQ_DATA_3,
251         DSI_DCS_CMDS,
252         DSI_PKT_SEQ_0_LO,
253         DSI_PKT_SEQ_1_LO,
254         DSI_PKT_SEQ_2_LO,
255         DSI_PKT_SEQ_3_LO,
256         DSI_PKT_SEQ_4_LO,
257         DSI_PKT_SEQ_5_LO,
258         DSI_PKT_SEQ_0_HI,
259         DSI_PKT_SEQ_1_HI,
260         DSI_PKT_SEQ_2_HI,
261         DSI_PKT_SEQ_3_HI,
262         DSI_PKT_SEQ_4_HI,
263         DSI_PKT_SEQ_5_HI,
264         DSI_CONTROL,
265         DSI_HOST_DSI_CONTROL,
266         DSI_PAD_CONTROL,
267         DSI_PAD_CONTROL_CD,
268         DSI_SOL_DELAY,
269         DSI_MAX_THRESHOLD,
270         DSI_TRIGGER,
271         DSI_TX_CRC,
272         DSI_INIT_SEQ_CONTROL,
273         DSI_PKT_LEN_0_1,
274         DSI_PKT_LEN_2_3,
275         DSI_PKT_LEN_4_5,
276         DSI_PKT_LEN_6_7,
277 };
278
279 inline unsigned long tegra_dsi_readl(struct tegra_dc_dsi_data *dsi, u32 reg)
280 {
281         return readl(dsi->base + reg * 4);
282 }
283 EXPORT_SYMBOL(tegra_dsi_readl);
284
285 inline void tegra_dsi_writel(struct tegra_dc_dsi_data *dsi, u32 val, u32 reg)
286 {
287         writel(val, dsi->base + reg * 4);
288 }
289 EXPORT_SYMBOL(tegra_dsi_writel);
290
291 static int tegra_dsi_syncpt(struct tegra_dc_dsi_data *dsi)
292 {
293         u32 val;
294         int ret;
295
296         ret = 0;
297
298         dsi->syncpt_val = nvhost_syncpt_read(
299                         &dsi->dc->ndev->host->syncpt, dsi->syncpt_id);
300
301         val = DSI_INCR_SYNCPT_COND(OP_DONE) |
302                 DSI_INCR_SYNCPT_INDX(dsi->syncpt_id);
303         tegra_dsi_writel(dsi, val, DSI_INCR_SYNCPT);
304
305         /* TODO: Use interrupt rather than polling */
306         ret = nvhost_syncpt_wait(&dsi->dc->ndev->host->syncpt,
307                 dsi->syncpt_id, dsi->syncpt_val + 1);
308         if (ret < 0) {
309                 printk(KERN_ERR "DSI sync point failure\n");
310                 goto fail;
311         }
312
313         (dsi->syncpt_val)++;
314         return 0;
315 fail:
316         return ret;
317 }
318
319 static u32 tegra_dsi_get_hs_clk_rate(struct tegra_dc_dsi_data *dsi)
320 {
321         u32 dsi_clock_rate_khz;
322
323         switch (dsi->info.video_burst_mode) {
324         case TEGRA_DSI_VIDEO_BURST_MODE_LOW_SPEED:
325         case TEGRA_DSI_VIDEO_BURST_MODE_MEDIUM_SPEED:
326         case TEGRA_DSI_VIDEO_BURST_MODE_FAST_SPEED:
327         case TEGRA_DSI_VIDEO_BURST_MODE_FASTEST_SPEED:
328                 /* Calculate DSI HS clock rate for DSI burst mode */
329                 dsi_clock_rate_khz = dsi->default_pixel_clk_khz *
330                                                         dsi->shift_clk_div;
331                 break;
332         case TEGRA_DSI_VIDEO_NONE_BURST_MODE:
333         case TEGRA_DSI_VIDEO_NONE_BURST_MODE_WITH_SYNC_END:
334         case TEGRA_DSI_VIDEO_BURST_MODE_LOWEST_SPEED:
335         default:
336                 /* Clock rate is default DSI clock rate for non-burst mode */
337                 dsi_clock_rate_khz = dsi->default_hs_clk_khz;
338                 break;
339         }
340
341         return dsi_clock_rate_khz;
342 }
343
344 static u32 tegra_dsi_get_lp_clk_rate(struct tegra_dc_dsi_data *dsi, u8 lp_op)
345 {
346         u32 dsi_clock_rate_khz;
347
348         if (dsi->info.enable_hs_clock_on_lp_cmd_mode)
349                 if (dsi->info.hs_clk_in_lp_cmd_mode_freq_khz)
350                         dsi_clock_rate_khz =
351                                 dsi->info.hs_clk_in_lp_cmd_mode_freq_khz;
352                 else
353                         dsi_clock_rate_khz = tegra_dsi_get_hs_clk_rate(dsi);
354         else
355                 if (lp_op == DSI_LP_OP_READ)
356                         dsi_clock_rate_khz =
357                                 dsi->info.lp_read_cmd_mode_freq_khz;
358                 else
359                         dsi_clock_rate_khz =
360                                 dsi->info.lp_cmd_mode_freq_khz;
361
362         return dsi_clock_rate_khz;
363 }
364
365 static u32 tegra_dsi_get_shift_clk_div(struct tegra_dc_dsi_data *dsi)
366 {
367         u32 shift_clk_div;
368         u32 max_shift_clk_div;
369         u32 burst_width;
370         u32 burst_width_max;
371
372         /* Get the real value of default shift_clk_div. default_shift_clk_div
373          * holds the real value of shift_clk_div.
374          */
375         shift_clk_div = dsi->default_shift_clk_div;
376
377         /* Calculate shift_clk_div which can matche the video_burst_mode. */
378         if (dsi->info.video_burst_mode >=
379                         TEGRA_DSI_VIDEO_BURST_MODE_LOWEST_SPEED) {
380                 /* The max_shift_clk_div is multiplied by 10 to save the
381                  * fraction
382                  */
383                 if (dsi->info.max_panel_freq_khz >= dsi->default_hs_clk_khz)
384                         max_shift_clk_div = dsi->info.max_panel_freq_khz
385                                 * shift_clk_div * 10 / dsi->default_hs_clk_khz;
386                 else
387                         max_shift_clk_div = shift_clk_div * 10;
388
389                 burst_width = dsi->info.video_burst_mode
390                                 - TEGRA_DSI_VIDEO_BURST_MODE_LOWEST_SPEED;
391                 burst_width_max = TEGRA_DSI_VIDEO_BURST_MODE_FASTEST_SPEED
392                                 - TEGRA_DSI_VIDEO_BURST_MODE_LOWEST_SPEED;
393
394                 shift_clk_div = (max_shift_clk_div - shift_clk_div * 10) *
395                         burst_width / (burst_width_max * 10) + shift_clk_div;
396         }
397
398         return shift_clk_div;
399 }
400
401 static void tegra_dsi_init_sw(struct tegra_dc *dc,
402                         struct tegra_dc_dsi_data *dsi)
403 {
404         u32 h_width_pixels;
405         u32 v_width_lines;
406         u32 pixel_clk_hz;
407         u32 byte_clk_hz;
408         u32 plld_clk_mhz;
409
410         switch (dsi->info.pixel_format) {
411         case TEGRA_DSI_PIXEL_FORMAT_16BIT_P:
412                 /* 2 bytes per pixel */
413                 dsi->pixel_scaler_mul = 2;
414                 dsi->pixel_scaler_div = 1;
415                 break;
416         case TEGRA_DSI_PIXEL_FORMAT_18BIT_P:
417                 /* 2.25 bytes per pixel */
418                 dsi->pixel_scaler_mul = 9;
419                 dsi->pixel_scaler_div = 4;
420                 break;
421         case TEGRA_DSI_PIXEL_FORMAT_18BIT_NP:
422         case TEGRA_DSI_PIXEL_FORMAT_24BIT_P:
423                 /* 3 bytes per pixel */
424                 dsi->pixel_scaler_mul = 3;
425                 dsi->pixel_scaler_div = 1;
426                 break;
427         default:
428                 break;
429         }
430
431         dsi->controller_index = dc->ndev->id;
432         dsi->ulpm = false;
433         dsi->enabled = false;
434         dsi->clk_ref = false;
435
436         dsi->dsi_control_val =
437                         DSI_CONTROL_VIRTUAL_CHANNEL(dsi->info.virtual_channel) |
438                         DSI_CONTROL_NUM_DATA_LANES(dsi->info.n_data_lanes - 1) |
439                         DSI_CONTROL_VID_SOURCE(dsi->controller_index) |
440                         DSI_CONTROL_DATA_FORMAT(dsi->info.pixel_format);
441
442         /* Below we are going to calculate dsi and dc clock rate.
443          * Calcuate the horizontal and vertical width.
444          */
445         h_width_pixels = dc->mode.h_back_porch + dc->mode.h_front_porch +
446                         dc->mode.h_sync_width + dc->mode.h_active;
447         v_width_lines = dc->mode.v_back_porch + dc->mode.v_front_porch +
448                         dc->mode.v_sync_width + dc->mode.v_active;
449
450         /* Calculate minimum required pixel rate. */
451         pixel_clk_hz = h_width_pixels * v_width_lines * dsi->info.refresh_rate;
452
453         dc->pixel_clk = pixel_clk_hz;
454
455         /* Calculate minimum byte rate on DSI interface. */
456         byte_clk_hz = (pixel_clk_hz * dsi->pixel_scaler_mul) /
457                         (dsi->pixel_scaler_div * dsi->info.n_data_lanes);
458
459         /* Round up to multiple of mega hz. */
460         plld_clk_mhz = DIV_ROUND_UP((byte_clk_hz * NUMOF_BIT_PER_BYTE),
461                                                                 1000000);
462
463         /* Calculate default real shift_clk_div. */
464         dsi->default_shift_clk_div = (NUMOF_BIT_PER_BYTE / 2) *
465                 dsi->pixel_scaler_mul / (dsi->pixel_scaler_div *
466                 dsi->info.n_data_lanes);
467         /* Calculate default DSI hs clock. DSI interface is double data rate.
468          * Data is transferred on both rising and falling edge of clk, div by 2
469          * to get the actual clock rate.
470          */
471         dsi->default_hs_clk_khz = plld_clk_mhz * 1000 / 2;
472         dsi->default_pixel_clk_khz = plld_clk_mhz * 1000 / 2
473                                                 / dsi->default_shift_clk_div;
474
475         /* Get the actual shift_clk_div and clock rates. */
476         dsi->shift_clk_div = tegra_dsi_get_shift_clk_div(dsi);
477         dsi->target_lp_clk_khz =
478                         tegra_dsi_get_lp_clk_rate(dsi, DSI_LP_OP_WRITE);
479         dsi->target_hs_clk_khz = tegra_dsi_get_hs_clk_rate(dsi);
480
481         dev_info(&dc->ndev->dev, "DSI: HS clock rate is %d\n",
482                                                         dsi->target_hs_clk_khz);
483
484         dsi->controller_index = dc->ndev->id;
485
486 #if DSI_USE_SYNC_POINTS
487         dsi->syncpt_id = NVSYNCPT_DSI;
488 #endif
489
490         /*
491          * Force video clock to be continuous mode if
492          * enable_hs_clock_on_lp_cmd_mode is set
493          */
494         if (dsi->info.enable_hs_clock_on_lp_cmd_mode) {
495                 if (dsi->info.video_clock_mode !=
496                                         TEGRA_DSI_VIDEO_CLOCK_CONTINUOUS)
497                         printk(KERN_WARNING "Force clock continuous mode\n");
498
499                 dsi->info.video_clock_mode = TEGRA_DSI_VIDEO_CLOCK_CONTINUOUS;
500         }
501
502 }
503
504 static void tegra_dsi_get_phy_timing(struct tegra_dc_dsi_data *dsi,
505                                 struct dsi_phy_timing_inclk *phy_timing_clk,
506                                 u32 clk_ns)
507 {
508
509         phy_timing_clk->t_hsdexit = dsi->info.phy_timing.t_hsdexit_ns ?
510                         (dsi->info.phy_timing.t_hsdexit_ns / clk_ns) :
511                         (T_HSEXIT_DEFAULT(clk_ns));
512
513         phy_timing_clk->t_hstrail = dsi->info.phy_timing.t_hstrail_ns ?
514                         (dsi->info.phy_timing.t_hstrail_ns / clk_ns) :
515                         (T_HSTRAIL_DEFAULT(clk_ns));
516
517         phy_timing_clk->t_datzero = dsi->info.phy_timing.t_datzero_ns ?
518                         (dsi->info.phy_timing.t_datzero_ns / clk_ns) :
519                         (T_DATZERO_DEFAULT(clk_ns));
520
521         phy_timing_clk->t_hsprepr = dsi->info.phy_timing.t_hsprepr_ns ?
522                         (dsi->info.phy_timing.t_hsprepr_ns / clk_ns) :
523                         (T_HSPREPR_DEFAULT(clk_ns));
524
525         phy_timing_clk->t_clktrail = dsi->info.phy_timing.t_clktrail_ns ?
526                                 (dsi->info.phy_timing.t_clktrail_ns / clk_ns) :
527                                 (T_CLKTRAIL_DEFAULT(clk_ns));
528
529         phy_timing_clk->t_clkpost = dsi->info.phy_timing.t_clkpost_ns ?
530                                 (dsi->info.phy_timing.t_clkpost_ns / clk_ns) :
531                                 (T_CLKPOST_DEFAULT(clk_ns));
532
533         phy_timing_clk->t_clkzero = dsi->info.phy_timing.t_clkzero_ns ?
534                                 (dsi->info.phy_timing.t_clkzero_ns / clk_ns) :
535                                 (T_CLKZERO_DEFAULT(clk_ns));
536
537         phy_timing_clk->t_tlpx = dsi->info.phy_timing.t_tlpx_ns ?
538                                 (dsi->info.phy_timing.t_tlpx_ns / clk_ns) :
539                                 (T_TLPX_DEFAULT(clk_ns));
540
541         phy_timing_clk->t_clkpre = T_CLKPRE_DEFAULT(clk_ns);
542         phy_timing_clk->t_clkprepare = T_CLKPREPARE_DEFAULT(clk_ns);
543         phy_timing_clk->t_wakeup = T_WAKEUP_DEFAULT(clk_ns);
544
545         phy_timing_clk->t_taget = 5 * phy_timing_clk->t_tlpx;
546         phy_timing_clk->t_tasure = 2 * phy_timing_clk->t_tlpx;
547         phy_timing_clk->t_tago = 4 * phy_timing_clk->t_tlpx;
548 }
549
550 static void tegra_dsi_set_phy_timing(struct tegra_dc_dsi_data *dsi)
551 {
552         u32 val;
553         struct dsi_phy_timing_inclk phy_timing;
554
555         tegra_dsi_get_phy_timing(dsi, &phy_timing, dsi->current_bit_clk_ns);
556
557         val = DSI_PHY_TIMING_0_THSDEXIT(phy_timing.t_hsdexit) |
558                         DSI_PHY_TIMING_0_THSTRAIL(phy_timing.t_hstrail) |
559                         DSI_PHY_TIMING_0_TDATZERO(phy_timing.t_datzero) |
560                         DSI_PHY_TIMING_0_THSPREPR(phy_timing.t_hsprepr);
561         tegra_dsi_writel(dsi, val, DSI_PHY_TIMING_0);
562
563         val = DSI_PHY_TIMING_1_TCLKTRAIL(phy_timing.t_clktrail) |
564                         DSI_PHY_TIMING_1_TCLKPOST(phy_timing.t_clkpost) |
565                         DSI_PHY_TIMING_1_TCLKZERO(phy_timing.t_clkzero) |
566                         DSI_PHY_TIMING_1_TTLPX(phy_timing.t_tlpx);
567         tegra_dsi_writel(dsi, val, DSI_PHY_TIMING_1);
568
569         val = DSI_PHY_TIMING_2_TCLKPREPARE(phy_timing.t_clkprepare) |
570                 DSI_PHY_TIMING_2_TCLKPRE(phy_timing.t_clkpre) |
571                         DSI_PHY_TIMING_2_TWAKEUP(phy_timing.t_wakeup);
572         tegra_dsi_writel(dsi, val, DSI_PHY_TIMING_2);
573
574         val = DSI_BTA_TIMING_TTAGET(phy_timing.t_taget) |
575                         DSI_BTA_TIMING_TTASURE(phy_timing.t_tasure) |
576                         DSI_BTA_TIMING_TTAGO(phy_timing.t_tago);
577         tegra_dsi_writel(dsi, val, DSI_BTA_TIMING);
578 }
579
580 static u32 tegra_dsi_sol_delay_burst(struct tegra_dc *dc,
581                                 struct tegra_dc_dsi_data *dsi)
582 {
583         u32 dsi_to_pixel_clk_ratio;
584         u32 temp;
585         u32 temp1;
586         u32 mipi_clk_adj_kHz;
587         u32 sol_delay;
588         struct tegra_dc_mode *dc_modes = &dc->mode;
589
590         /* Get Fdsi/Fpixel ration (note: Fdsi is in bit format) */
591         dsi_to_pixel_clk_ratio = (dsi->current_dsi_clk_khz * 2 +
592                 dsi->default_pixel_clk_khz - 1) / dsi->default_pixel_clk_khz;
593
594         /* Convert Fdsi to byte format */
595         dsi_to_pixel_clk_ratio *= 1000/8;
596
597         /* Multiplying by 1000 so that we don't loose the fraction part */
598         temp = dc_modes->h_active * 1000;
599         temp1 = dc_modes->h_active + dc_modes->h_back_porch +
600                         dc_modes->h_sync_width;
601
602         sol_delay = temp1 * dsi_to_pixel_clk_ratio -
603                         temp * dsi->pixel_scaler_mul /
604                         (dsi->pixel_scaler_div * dsi->info.n_data_lanes);
605
606         /* Do rounding on sol delay */
607         sol_delay = (sol_delay + 1000 - 1)/1000;
608
609         /* TODO:
610          * 1. find out the correct sol fifo depth to use
611          * 2. verify with hw about the clamping function
612          */
613         if (sol_delay > (480 * 4)) {
614                 sol_delay = (480 * 4);
615                 mipi_clk_adj_kHz = sol_delay +
616                         (dc_modes->h_active * dsi->pixel_scaler_mul) /
617                         (dsi->info.n_data_lanes * dsi->pixel_scaler_div);
618
619                 mipi_clk_adj_kHz *= (dsi->default_pixel_clk_khz / temp1);
620
621                 mipi_clk_adj_kHz *= 4;
622         }
623
624         dsi->target_hs_clk_khz = mipi_clk_adj_kHz;
625
626         return sol_delay;
627 }
628
629 static void tegra_dsi_set_sol_delay(struct tegra_dc *dc,
630                                 struct tegra_dc_dsi_data *dsi)
631 {
632         u32 sol_delay;
633
634         if (dsi->info.video_burst_mode == TEGRA_DSI_VIDEO_NONE_BURST_MODE ||
635                 dsi->info.video_burst_mode ==
636                                 TEGRA_DSI_VIDEO_NONE_BURST_MODE_WITH_SYNC_END) {
637                 sol_delay = NUMOF_BIT_PER_BYTE * dsi->pixel_scaler_mul /
638                         (dsi->pixel_scaler_div * dsi->info.n_data_lanes);
639                 dsi->status.clk_burst = DSI_CLK_BURST_NONE_BURST;
640         } else {
641                 sol_delay = tegra_dsi_sol_delay_burst(dc, dsi);
642                 dsi->status.clk_burst = DSI_CLK_BURST_BURST_MODE;
643         }
644
645         tegra_dsi_writel(dsi, DSI_SOL_DELAY_SOL_DELAY(sol_delay),
646                                                                 DSI_SOL_DELAY);
647 }
648
649 static void tegra_dsi_set_timeout(struct tegra_dc_dsi_data *dsi)
650 {
651         u32 val;
652         u32 bytes_per_frame;
653         u32 timeout = 0;
654
655         /* TODO: verify the following equation */
656         bytes_per_frame = dsi->current_dsi_clk_khz * 1000 * 2 /
657                                                 (dsi->info.refresh_rate * 8);
658         timeout = bytes_per_frame / DSI_CYCLE_COUNTER_VALUE;
659         timeout = (timeout + DSI_HTX_TO_MARGIN) & 0xffff;
660
661         val = DSI_TIMEOUT_0_LRXH_TO(DSI_LRXH_TO_VALUE) |
662                         DSI_TIMEOUT_0_HTX_TO(timeout);
663         tegra_dsi_writel(dsi, val, DSI_TIMEOUT_0);
664
665         if (dsi->info.panel_reset_timeout_msec)
666                 timeout = (dsi->info.panel_reset_timeout_msec * 1000*1000)
667                                         / dsi->current_bit_clk_ns;
668         else
669                 timeout = DSI_PR_TO_VALUE;
670
671         val = DSI_TIMEOUT_1_PR_TO(timeout) |
672                 DSI_TIMEOUT_1_TA_TO(DSI_TA_TO_VALUE);
673         tegra_dsi_writel(dsi, val, DSI_TIMEOUT_1);
674
675         val = DSI_TO_TALLY_P_RESET_STATUS(IN_RESET) |
676                 DSI_TO_TALLY_TA_TALLY(DSI_TA_TALLY_VALUE)|
677                 DSI_TO_TALLY_LRXH_TALLY(DSI_LRXH_TALLY_VALUE)|
678                 DSI_TO_TALLY_HTX_TALLY(DSI_HTX_TALLY_VALUE);
679         tegra_dsi_writel(dsi, val, DSI_TO_TALLY);
680 }
681
682 static void tegra_dsi_setup_video_mode_pkt_length(struct tegra_dc *dc,
683                                                 struct tegra_dc_dsi_data *dsi)
684 {
685         u32 val;
686         u32 hact_pkt_len;
687         u32 hsa_pkt_len;
688         u32 hbp_pkt_len;
689         u32 hfp_pkt_len;
690
691         hact_pkt_len = dc->mode.h_active * dsi->pixel_scaler_mul /
692                                                         dsi->pixel_scaler_div;
693         hsa_pkt_len = dc->mode.h_sync_width * dsi->pixel_scaler_mul /
694                                                         dsi->pixel_scaler_div;
695         hbp_pkt_len = dc->mode.h_back_porch * dsi->pixel_scaler_mul /
696                                                         dsi->pixel_scaler_div;
697         hfp_pkt_len = dc->mode.h_front_porch * dsi->pixel_scaler_mul /
698                                                         dsi->pixel_scaler_div;
699
700         if (dsi->info.video_burst_mode !=
701                                 TEGRA_DSI_VIDEO_NONE_BURST_MODE_WITH_SYNC_END)
702                 hbp_pkt_len += hsa_pkt_len;
703
704         hsa_pkt_len -= DSI_HSYNC_BLNK_PKT_OVERHEAD;
705         hbp_pkt_len -= DSI_HBACK_PORCH_PKT_OVERHEAD;
706         hfp_pkt_len -= DSI_HFRONT_PORCH_PKT_OVERHEAD;
707
708         val = DSI_PKT_LEN_0_1_LENGTH_0(0) |
709                         DSI_PKT_LEN_0_1_LENGTH_1(hsa_pkt_len);
710         tegra_dsi_writel(dsi, val, DSI_PKT_LEN_0_1);
711
712         val = DSI_PKT_LEN_2_3_LENGTH_2(hbp_pkt_len) |
713                         DSI_PKT_LEN_2_3_LENGTH_3(hact_pkt_len);
714         tegra_dsi_writel(dsi, val, DSI_PKT_LEN_2_3);
715
716         val = DSI_PKT_LEN_4_5_LENGTH_4(hfp_pkt_len) |
717                         DSI_PKT_LEN_4_5_LENGTH_5(0);
718         tegra_dsi_writel(dsi, val, DSI_PKT_LEN_4_5);
719
720         val = DSI_PKT_LEN_6_7_LENGTH_6(0) | DSI_PKT_LEN_6_7_LENGTH_7(0);
721         tegra_dsi_writel(dsi, val, DSI_PKT_LEN_6_7);
722 }
723
724 static void tegra_dsi_setup_cmd_mode_pkt_length(struct tegra_dc *dc,
725                                                 struct tegra_dc_dsi_data *dsi)
726 {
727         unsigned long   val;
728         unsigned long   act_bytes;
729
730         act_bytes = dc->mode.h_active * dsi->pixel_scaler_mul /
731                         dsi->pixel_scaler_div + 1;
732
733         val = DSI_PKT_LEN_0_1_LENGTH_0(0) | DSI_PKT_LEN_0_1_LENGTH_1(0);
734         tegra_dsi_writel(dsi, val, DSI_PKT_LEN_0_1);
735
736         val = DSI_PKT_LEN_2_3_LENGTH_2(0) | DSI_PKT_LEN_2_3_LENGTH_3(act_bytes);
737         tegra_dsi_writel(dsi, val, DSI_PKT_LEN_2_3);
738
739         val = DSI_PKT_LEN_4_5_LENGTH_4(0) | DSI_PKT_LEN_4_5_LENGTH_5(act_bytes);
740         tegra_dsi_writel(dsi, val, DSI_PKT_LEN_4_5);
741
742         val = DSI_PKT_LEN_6_7_LENGTH_6(0) | DSI_PKT_LEN_6_7_LENGTH_7(0x0f0f);
743         tegra_dsi_writel(dsi, val, DSI_PKT_LEN_6_7);
744 }
745
746 static void tegra_dsi_set_pkt_length(struct tegra_dc *dc,
747                                 struct tegra_dc_dsi_data *dsi)
748 {
749         if (dsi->driven_mode == TEGRA_DSI_DRIVEN_BY_HOST)
750                 return;
751
752         if (dsi->info.video_data_type == TEGRA_DSI_VIDEO_TYPE_VIDEO_MODE)
753                 tegra_dsi_setup_video_mode_pkt_length(dc, dsi);
754         else
755                 tegra_dsi_setup_cmd_mode_pkt_length(dc, dsi);
756 }
757
758 static void tegra_dsi_set_pkt_seq(struct tegra_dc *dc,
759                                 struct tegra_dc_dsi_data *dsi)
760 {
761         const u32 *pkt_seq;
762         u32 rgb_info;
763         u32 pkt_seq_3_5_rgb_lo;
764         u32 pkt_seq_3_5_rgb_hi;
765         u32     val;
766         u32 reg;
767         u8  i;
768
769         if (dsi->driven_mode == TEGRA_DSI_DRIVEN_BY_HOST)
770                 return;
771
772         switch (dsi->info.pixel_format) {
773         case TEGRA_DSI_PIXEL_FORMAT_16BIT_P:
774                 rgb_info = CMD_RGB_16BPP;
775                 break;
776         case TEGRA_DSI_PIXEL_FORMAT_18BIT_P:
777                 rgb_info = CMD_RGB_18BPP;
778                 break;
779         case TEGRA_DSI_PIXEL_FORMAT_18BIT_NP:
780                 rgb_info = CMD_RGB_18BPPNP;
781                 break;
782         case TEGRA_DSI_PIXEL_FORMAT_24BIT_P:
783         default:
784                 rgb_info = CMD_RGB_24BPP;
785                 break;
786         }
787
788         pkt_seq_3_5_rgb_lo = 0;
789         pkt_seq_3_5_rgb_hi = 0;
790         if (dsi->info.video_data_type == TEGRA_DSI_VIDEO_TYPE_COMMAND_MODE)
791                 pkt_seq = dsi_pkt_seq_cmd_mode;
792         else {
793                 switch (dsi->info.video_burst_mode) {
794                 case TEGRA_DSI_VIDEO_BURST_MODE_LOWEST_SPEED:
795                 case TEGRA_DSI_VIDEO_BURST_MODE_LOW_SPEED:
796                 case TEGRA_DSI_VIDEO_BURST_MODE_MEDIUM_SPEED:
797                 case TEGRA_DSI_VIDEO_BURST_MODE_FAST_SPEED:
798                 case TEGRA_DSI_VIDEO_BURST_MODE_FASTEST_SPEED:
799                         pkt_seq_3_5_rgb_lo =
800                                         DSI_PKT_SEQ_3_LO_PKT_32_ID(rgb_info);
801                         if (!dsi->info.no_pkt_seq_eot)
802                                 pkt_seq = dsi_pkt_seq_video_burst;
803                         else
804                                 pkt_seq = dsi_pkt_seq_video_burst_no_eot;
805                         break;
806                 case TEGRA_DSI_VIDEO_NONE_BURST_MODE_WITH_SYNC_END:
807                         pkt_seq_3_5_rgb_hi =
808                                         DSI_PKT_SEQ_3_HI_PKT_34_ID(rgb_info);
809                         pkt_seq = dsi_pkt_seq_video_non_burst_syne;
810                         break;
811                 case TEGRA_DSI_VIDEO_NONE_BURST_MODE:
812                 default:
813                         pkt_seq_3_5_rgb_lo =
814                                         DSI_PKT_SEQ_3_LO_PKT_32_ID(rgb_info);
815                         pkt_seq = dsi_pkt_seq_video_non_burst;
816                         break;
817                 }
818         }
819
820         for (i = 0; i < NUMOF_PKT_SEQ; i++) {
821                 val = pkt_seq[i];
822                 reg = dsi_pkt_seq_reg[i];
823                 if ((reg == DSI_PKT_SEQ_3_LO) || (reg == DSI_PKT_SEQ_5_LO))
824                         val |= pkt_seq_3_5_rgb_lo;
825                 if ((reg == DSI_PKT_SEQ_3_HI) || (reg == DSI_PKT_SEQ_5_HI))
826                         val |= pkt_seq_3_5_rgb_hi;
827                 tegra_dsi_writel(dsi, val, reg);
828         }
829 }
830
831 static void tegra_dsi_stop_dc_stream(struct tegra_dc *dc,
832                                         struct tegra_dc_dsi_data *dsi)
833 {
834         tegra_dc_writel(dc, 0, DC_DISP_DISP_WIN_OPTIONS);
835         tegra_dc_writel(dc, GENERAL_ACT_REQ << 8, DC_CMD_STATE_CONTROL);
836         tegra_dc_writel(dc, GENERAL_ACT_REQ, DC_CMD_STATE_CONTROL);
837
838         dsi->status.dc_stream = DSI_DC_STREAM_DISABLE;
839 }
840
841 void tegra_dsi_stop_dc_stream_at_frame_end(struct tegra_dc *dc,
842                                                 struct tegra_dc_dsi_data *dsi)
843 {
844         int val;
845         long timeout;
846
847         /* stop dc */
848         tegra_dsi_stop_dc_stream(dc, dsi);
849
850         /* enable vblank interrupt */
851         val = tegra_dc_readl(dc, DC_CMD_INT_ENABLE);
852         val |= V_BLANK_INT;
853         tegra_dc_writel(dc, val, DC_CMD_INT_ENABLE);
854
855         val = tegra_dc_readl(dc, DC_CMD_INT_MASK);
856         val |= V_BLANK_INT;
857         tegra_dc_writel(dc, val, DC_CMD_INT_MASK);
858
859         /* wait for vblank completion */
860         timeout = wait_for_completion_interruptible_timeout(
861                 &dc->vblank_complete, DSI_STOP_DC_DURATION_MSEC);
862
863         /* disable vblank interrupt */
864         val = tegra_dc_readl(dc, DC_CMD_INT_ENABLE);
865         val &= ~V_BLANK_INT;
866         tegra_dc_writel(dc, val, DC_CMD_INT_ENABLE);
867
868         if (timeout == 0)
869                 printk(KERN_WARNING "DC doesn't stop at end of frame.\n");
870 }
871
872 static void tegra_dsi_start_dc_stream(struct tegra_dc *dc,
873                                         struct tegra_dc_dsi_data *dsi)
874 {
875         u32 val;
876
877         tegra_dc_writel(dc, DSI_ENABLE, DC_DISP_DISP_WIN_OPTIONS);
878
879         /* TODO: clean up */
880         tegra_dc_writel(dc, PW0_ENABLE | PW1_ENABLE | PW2_ENABLE | PW3_ENABLE |
881                         PW4_ENABLE | PM0_ENABLE | PM1_ENABLE,
882                         DC_CMD_DISPLAY_POWER_CONTROL);
883
884         /* Configure one-shot mode or continuous mode */
885         if (dc->out->flags & TEGRA_DC_OUT_ONE_SHOT_MODE) {
886                 /* disable LSPI/LCD_DE output */
887                 val = PIN_OUTPUT_LSPI_OUTPUT_DIS;
888                 tegra_dc_writel(dc, val, DC_COM_PIN_OUTPUT_ENABLE3);
889
890                 /* enable MSF & set MSF polarity */
891                 val = MSF_ENABLE | MSF_LSPI;
892                 if (!dsi->info.te_polarity_low)
893                         val |= MSF_POLARITY_HIGH;
894                 else
895                         val |= MSF_POLARITY_LOW;
896                 tegra_dc_writel(dc, val, DC_CMD_DISPLAY_COMMAND_OPTION0);
897
898                 /* set non-continuous mode */
899                 tegra_dc_writel(dc, DISP_CTRL_MODE_NC_DISPLAY,
900                                                 DC_CMD_DISPLAY_COMMAND);
901                 tegra_dc_writel(dc, GENERAL_UPDATE, DC_CMD_STATE_CONTROL);
902                 tegra_dc_writel(dc, GENERAL_ACT_REQ | NC_HOST_TRIG,
903                                                 DC_CMD_STATE_CONTROL);
904         } else {
905                 /* set continuous mode */
906                 tegra_dc_writel(dc, DISP_CTRL_MODE_C_DISPLAY,
907                                                 DC_CMD_DISPLAY_COMMAND);
908                 tegra_dc_writel(dc, GENERAL_UPDATE, DC_CMD_STATE_CONTROL);
909                 tegra_dc_writel(dc, GENERAL_ACT_REQ, DC_CMD_STATE_CONTROL);
910         }
911
912         dsi->status.dc_stream = DSI_DC_STREAM_ENABLE;
913 }
914
915 static void tegra_dsi_set_dc_clk(struct tegra_dc *dc,
916                                 struct tegra_dc_dsi_data *dsi)
917 {
918         u32 shift_clk_div_register;
919         u32 val;
920
921         /* Get the corresponding register value of shift_clk_div. */
922         shift_clk_div_register = dsi->shift_clk_div * 2 - 2;
923
924 #ifdef CONFIG_TEGRA_FPGA_PLATFORM
925         shift_clk_div_register = 1;
926 #endif
927
928         /* TODO: find out if PCD3 option is required */
929         val = PIXEL_CLK_DIVIDER_PCD1 |
930                 SHIFT_CLK_DIVIDER(shift_clk_div_register);
931         tegra_dc_writel(dc, val, DC_DISP_DISP_CLOCK_CONTROL);
932 }
933
934 static void tegra_dsi_set_dsi_clk(struct tegra_dc *dc,
935                         struct tegra_dc_dsi_data *dsi, u32 clk)
936 {
937         u32 rm;
938
939         rm = clk % 1000;
940         if (rm != 0)
941                 clk -= rm;
942
943         clk *= 2;       /*
944                          * Value for PLLD routine is required to be twice as
945                          * the desired clock rate
946                          */
947
948         dc->mode.pclk = clk*1000;
949         tegra_dc_setup_clk(dc, dsi->dsi_clk);
950         if (dsi->clk_ref == true)
951                 clk_disable(dsi->dsi_clk);
952         else
953                 dsi->clk_ref = true;
954         clk_enable(dsi->dsi_clk);
955         tegra_periph_reset_deassert(dsi->dsi_clk);
956
957         dsi->current_dsi_clk_khz = clk_get_rate(dsi->dsi_clk) / 1000;
958
959         dsi->current_bit_clk_ns =  1000*1000 / (dsi->current_dsi_clk_khz * 2);
960 }
961
962 static void tegra_dsi_hs_clk_out_enable(struct tegra_dc_dsi_data *dsi)
963 {
964         u32 val;
965
966         val = tegra_dsi_readl(dsi, DSI_CONTROL);
967         val &= ~DSI_CONTROL_HS_CLK_CTRL(1);
968
969         if (dsi->info.video_clock_mode == TEGRA_DSI_VIDEO_CLOCK_CONTINUOUS) {
970                 val |= DSI_CONTROL_HS_CLK_CTRL(CONTINUOUS);
971                 dsi->status.clk_mode = DSI_PHYCLK_CONTINUOUS;
972         } else {
973                 val |= DSI_CONTROL_HS_CLK_CTRL(TX_ONLY);
974                 dsi->status.clk_mode = DSI_PHYCLK_TX_ONLY;
975         }
976         tegra_dsi_writel(dsi, val, DSI_CONTROL);
977
978         val = tegra_dsi_readl(dsi, DSI_HOST_DSI_CONTROL);
979         val &= ~DSI_HOST_DSI_CONTROL_HIGH_SPEED_TRANS(1);
980         val |= DSI_HOST_DSI_CONTROL_HIGH_SPEED_TRANS(TEGRA_DSI_HIGH);
981         tegra_dsi_writel(dsi, val, DSI_HOST_DSI_CONTROL);
982
983         dsi->status.clk_out = DSI_PHYCLK_OUT_EN;
984 }
985
986 static void tegra_dsi_hs_clk_out_enable_in_lp(struct tegra_dc_dsi_data *dsi)
987 {
988         u32 val;
989         tegra_dsi_hs_clk_out_enable(dsi);
990
991         val = tegra_dsi_readl(dsi, DSI_HOST_DSI_CONTROL);
992         val &= ~DSI_HOST_DSI_CONTROL_HIGH_SPEED_TRANS(1);
993         val |= DSI_HOST_DSI_CONTROL_HIGH_SPEED_TRANS(TEGRA_DSI_LOW);
994         tegra_dsi_writel(dsi, val, DSI_HOST_DSI_CONTROL);
995 }
996
997 static void tegra_dsi_hs_clk_out_disable(struct tegra_dc *dc,
998                                                 struct tegra_dc_dsi_data *dsi)
999 {
1000         u32 val;
1001
1002         if (dsi->status.dc_stream == DSI_DC_STREAM_ENABLE)
1003                 tegra_dsi_stop_dc_stream(dc, dsi);
1004
1005         val = tegra_dsi_readl(dsi, DSI_CONTROL);
1006         val &= ~DSI_CONTROL_HS_CLK_CTRL(1);
1007         val |= DSI_CONTROL_HS_CLK_CTRL(TX_ONLY);
1008         tegra_dsi_writel(dsi, val, DSI_CONTROL);
1009
1010         /* TODO: issue a cmd */
1011
1012         val = tegra_dsi_readl(dsi, DSI_HOST_DSI_CONTROL);
1013         val &= ~DSI_HOST_DSI_CONTROL_HIGH_SPEED_TRANS(1);
1014         val |= DSI_HOST_DSI_CONTROL_HIGH_SPEED_TRANS(TEGRA_DSI_LOW);
1015         tegra_dsi_writel(dsi, val, DSI_HOST_DSI_CONTROL);
1016
1017         dsi->status.clk_mode = DSI_PHYCLK_NOT_INIT;
1018         dsi->status.clk_out = DSI_PHYCLK_OUT_DIS;
1019 }
1020
1021 static void tegra_dsi_set_control_reg_lp(struct tegra_dc_dsi_data *dsi)
1022 {
1023         u32 dsi_control;
1024         u32 host_dsi_control;
1025         u32 max_threshold;
1026
1027         dsi_control = dsi->dsi_control_val | DSI_CTRL_HOST_DRIVEN;
1028         host_dsi_control = HOST_DSI_CTRL_COMMON |
1029                         HOST_DSI_CTRL_HOST_DRIVEN |
1030                         DSI_HOST_DSI_CONTROL_HIGH_SPEED_TRANS(TEGRA_DSI_LOW);
1031         max_threshold = DSI_MAX_THRESHOLD_MAX_THRESHOLD(DSI_HOST_FIFO_DEPTH);
1032
1033         tegra_dsi_writel(dsi, max_threshold, DSI_MAX_THRESHOLD);
1034         tegra_dsi_writel(dsi, dsi_control, DSI_CONTROL);
1035         tegra_dsi_writel(dsi, host_dsi_control, DSI_HOST_DSI_CONTROL);
1036
1037         dsi->status.driven = DSI_DRIVEN_MODE_HOST;
1038         dsi->status.clk_burst = DSI_CLK_BURST_NOT_INIT;
1039         dsi->status.vtype = DSI_VIDEO_TYPE_NOT_INIT;
1040 }
1041
1042 static void tegra_dsi_set_control_reg_hs(struct tegra_dc_dsi_data *dsi)
1043 {
1044         u32 dsi_control;
1045         u32 host_dsi_control;
1046         u32 max_threshold;
1047         u32 dcs_cmd;
1048
1049         dsi_control = dsi->dsi_control_val;
1050         host_dsi_control = HOST_DSI_CTRL_COMMON;
1051         max_threshold = 0;
1052         dcs_cmd = 0;
1053
1054         if (dsi->driven_mode == TEGRA_DSI_DRIVEN_BY_HOST) {
1055                 dsi_control |= DSI_CTRL_HOST_DRIVEN;
1056                 host_dsi_control |= HOST_DSI_CTRL_HOST_DRIVEN;
1057                 max_threshold =
1058                         DSI_MAX_THRESHOLD_MAX_THRESHOLD(DSI_HOST_FIFO_DEPTH);
1059                 dsi->status.driven = DSI_DRIVEN_MODE_HOST;
1060         } else {
1061                 dsi_control |= DSI_CTRL_DC_DRIVEN;
1062                 host_dsi_control |= HOST_DSI_CTRL_DC_DRIVEN;
1063                 max_threshold =
1064                         DSI_MAX_THRESHOLD_MAX_THRESHOLD(DSI_VIDEO_FIFO_DEPTH);
1065                 dsi->status.driven = DSI_DRIVEN_MODE_DC;
1066         }
1067
1068         if (dsi->info.video_data_type == TEGRA_DSI_VIDEO_TYPE_COMMAND_MODE) {
1069                 dsi_control |= DSI_CTRL_CMD_MODE;
1070                 host_dsi_control |= HOST_DSI_CTRL_CMD_MODE;
1071                 dcs_cmd = DSI_DCS_CMDS_LT5_DCS_CMD(DSI_WRITE_MEMORY_START)|
1072                         DSI_DCS_CMDS_LT3_DCS_CMD(DSI_WRITE_MEMORY_CONTINUE);
1073                 dsi->status.vtype = DSI_VIDEO_TYPE_CMD_MODE;
1074
1075         } else {
1076                 dsi_control |= DSI_CTRL_VIDEO_MODE;
1077                 host_dsi_control |= HOST_DSI_CTRL_VIDEO_MODE;
1078                 dsi->status.vtype = DSI_VIDEO_TYPE_VIDEO_MODE;
1079         }
1080
1081         tegra_dsi_writel(dsi, max_threshold, DSI_MAX_THRESHOLD);
1082         tegra_dsi_writel(dsi, dcs_cmd, DSI_DCS_CMDS);
1083         tegra_dsi_writel(dsi, dsi_control, DSI_CONTROL);
1084         tegra_dsi_writel(dsi, host_dsi_control, DSI_HOST_DSI_CONTROL);
1085 }
1086
1087 static int tegra_dsi_init_hw(struct tegra_dc *dc,
1088                                 struct tegra_dc_dsi_data *dsi)
1089 {
1090         u32 val;
1091         u32 i;
1092
1093         val = DSI_POWER_CONTROL_LEG_DSI_ENABLE(TEGRA_DSI_DISABLE);
1094         tegra_dsi_writel(dsi, val, DSI_POWER_CONTROL);
1095
1096         tegra_dsi_set_dsi_clk(dc, dsi, dsi->target_lp_clk_khz);
1097         if (dsi->info.dsi_instance) {
1098                 /* TODO:Set the misc register */
1099         }
1100
1101         /* TODO: only need to change the timing for bta */
1102         tegra_dsi_set_phy_timing(dsi);
1103
1104         if (dsi->status.dc_stream == DSI_DC_STREAM_ENABLE)
1105                 tegra_dsi_stop_dc_stream(dc, dsi);
1106
1107         /* Initializing DSI registers */
1108         for (i = 0; i < ARRAY_SIZE(init_reg); i++)
1109                 tegra_dsi_writel(dsi, 0, init_reg[i]);
1110
1111         tegra_dsi_writel(dsi, dsi->dsi_control_val, DSI_CONTROL);
1112         /* Initialize DSI_PAD_CONTROL register. */
1113         val =   DSI_PAD_CONTROL_PAD_LPUPADJ(0x1) |
1114                 DSI_PAD_CONTROL_PAD_LPDNADJ(0x1) |
1115                 DSI_PAD_CONTROL_PAD_PREEMP_EN(0x1) |
1116                 DSI_PAD_CONTROL_PAD_SLEWDNADJ(0x6) |
1117                 DSI_PAD_CONTROL_PAD_SLEWUPADJ(0x6);
1118
1119         if (!dsi->ulpm) {
1120                 val |=  DSI_PAD_CONTROL_PAD_PDIO(0) |
1121                         DSI_PAD_CONTROL_PAD_PDIO_CLK(0) |
1122                         DSI_PAD_CONTROL_PAD_PULLDN_ENAB(TEGRA_DSI_DISABLE);
1123         } else {
1124                 val |=  DSI_PAD_CONTROL_PAD_PDIO(0x3) |
1125                         DSI_PAD_CONTROL_PAD_PDIO_CLK(0x1) |
1126                         DSI_PAD_CONTROL_PAD_PULLDN_ENAB(TEGRA_DSI_ENABLE);
1127         }
1128         tegra_dsi_writel(dsi, val, DSI_PAD_CONTROL);
1129
1130         val = MIPI_CAL_TERMOSA(0x4);
1131         tegra_vi_csi_writel(val, CSI_CILA_MIPI_CAL_CONFIG_0);
1132
1133         val = MIPI_CAL_TERMOSB(0x4);
1134         tegra_vi_csi_writel(val, CSI_CILB_MIPI_CAL_CONFIG_0);
1135
1136         val = MIPI_CAL_HSPUOSD(0x3) | MIPI_CAL_HSPDOSD(0x4);
1137         tegra_vi_csi_writel(val, CSI_DSI_MIPI_CAL_CONFIG);
1138
1139         val = PAD_DRIV_DN_REF(0x5) | PAD_DRIV_UP_REF(0x7);
1140         tegra_vi_csi_writel(val, CSI_MIPIBIAS_PAD_CONFIG);
1141
1142         val = DSI_POWER_CONTROL_LEG_DSI_ENABLE(TEGRA_DSI_ENABLE);
1143         tegra_dsi_writel(dsi, val, DSI_POWER_CONTROL);
1144
1145         while (tegra_dsi_readl(dsi, DSI_POWER_CONTROL) != val)
1146                 tegra_dsi_writel(dsi, val, DSI_POWER_CONTROL);
1147
1148         dsi->status.init = DSI_MODULE_INIT;
1149         dsi->status.lphs = DSI_LPHS_NOT_INIT;
1150         dsi->status.vtype = DSI_VIDEO_TYPE_NOT_INIT;
1151         dsi->status.driven = DSI_DRIVEN_MODE_NOT_INIT;
1152         dsi->status.clk_out = DSI_PHYCLK_OUT_DIS;
1153         dsi->status.clk_mode = DSI_PHYCLK_NOT_INIT;
1154         dsi->status.clk_burst = DSI_CLK_BURST_NOT_INIT;
1155         dsi->status.dc_stream = DSI_DC_STREAM_DISABLE;
1156         dsi->status.lp_op = DSI_LP_OP_NOT_INIT;
1157
1158         return 0;
1159 }
1160
1161 static int tegra_dsi_set_to_lp_mode(struct tegra_dc *dc,
1162                         struct tegra_dc_dsi_data *dsi, u8 lp_op)
1163 {
1164         int err;
1165
1166         if (dsi->status.init != DSI_MODULE_INIT) {
1167                 err = -EPERM;
1168                 goto fail;
1169         }
1170
1171         if (dsi->status.lphs == DSI_LPHS_IN_LP_MODE &&
1172                         dsi->status.lp_op == lp_op)
1173                 goto success;
1174
1175         if (dsi->status.dc_stream == DSI_DC_STREAM_ENABLE)
1176                 tegra_dsi_stop_dc_stream_at_frame_end(dc, dsi);
1177
1178         /* disable/enable hs clk according to enable_hs_clock_on_lp_cmd_mode */
1179         if ((dsi->status.clk_out == DSI_PHYCLK_OUT_EN) &&
1180                 (!dsi->info.enable_hs_clock_on_lp_cmd_mode))
1181                 tegra_dsi_hs_clk_out_disable(dc, dsi);
1182
1183         dsi->target_lp_clk_khz = tegra_dsi_get_lp_clk_rate(dsi, lp_op);
1184         if (dsi->current_dsi_clk_khz != dsi->target_lp_clk_khz) {
1185                 tegra_dsi_set_dsi_clk(dc, dsi, dsi->target_lp_clk_khz);
1186                 tegra_dsi_set_timeout(dsi);
1187         }
1188
1189         tegra_dsi_set_control_reg_lp(dsi);
1190
1191         if ((dsi->status.clk_out == DSI_PHYCLK_OUT_DIS) &&
1192                 (dsi->info.enable_hs_clock_on_lp_cmd_mode))
1193                 tegra_dsi_hs_clk_out_enable_in_lp(dsi);
1194
1195 success:
1196         dsi->status.lphs = DSI_LPHS_IN_LP_MODE;
1197         dsi->status.lp_op = lp_op;
1198         err = 0;
1199 fail:
1200         return err;
1201 }
1202
1203 static int tegra_dsi_set_to_hs_mode(struct tegra_dc *dc,
1204                                         struct tegra_dc_dsi_data *dsi)
1205 {
1206         int err;
1207
1208         if (dsi->status.init != DSI_MODULE_INIT) {
1209                 err = -EPERM;
1210                 goto fail;
1211         }
1212
1213         if (dsi->status.dc_stream == DSI_DC_STREAM_ENABLE)
1214                 tegra_dsi_stop_dc_stream_at_frame_end(dc, dsi);
1215
1216         if ((dsi->status.clk_out == DSI_PHYCLK_OUT_EN) &&
1217                 (!dsi->info.enable_hs_clock_on_lp_cmd_mode))
1218                 tegra_dsi_hs_clk_out_disable(dc, dsi);
1219
1220         if (dsi->current_dsi_clk_khz != dsi->target_hs_clk_khz) {
1221                 tegra_dsi_set_dsi_clk(dc, dsi, dsi->target_hs_clk_khz);
1222                 tegra_dsi_set_timeout(dsi);
1223         }
1224
1225         tegra_dsi_set_phy_timing(dsi);
1226
1227         if (dsi->driven_mode == TEGRA_DSI_DRIVEN_BY_DC) {
1228                 tegra_dsi_set_pkt_seq(dc, dsi);
1229                 tegra_dsi_set_pkt_length(dc, dsi);
1230                 tegra_dsi_set_sol_delay(dc, dsi);
1231                 tegra_dsi_set_dc_clk(dc, dsi);
1232         }
1233
1234         tegra_dsi_set_control_reg_hs(dsi);
1235
1236         if (dsi->status.clk_out == DSI_PHYCLK_OUT_DIS)
1237                 tegra_dsi_hs_clk_out_enable(dsi);
1238
1239         dsi->status.lphs = DSI_LPHS_IN_HS_MODE;
1240         err = 0;
1241 fail:
1242         return err;
1243 }
1244
1245 static bool tegra_dsi_is_controller_idle(struct tegra_dc_dsi_data *dsi)
1246 {
1247         u32 timeout = 0;
1248         bool retVal;
1249
1250         retVal = false;
1251         while (timeout <= DSI_MAX_COMMAND_DELAY_USEC) {
1252                 if (!tegra_dsi_readl(dsi, DSI_TRIGGER)) {
1253                         retVal = true;
1254                         break;
1255                 }
1256                 udelay(DSI_COMMAND_DELAY_STEPS_USEC);
1257                 timeout += DSI_COMMAND_DELAY_STEPS_USEC;
1258         }
1259
1260         return retVal;
1261 }
1262
1263 static int tegra_dsi_host_trigger(struct tegra_dc_dsi_data *dsi)
1264 {
1265         int status = 0;
1266
1267         if (tegra_dsi_readl(dsi, DSI_TRIGGER)) {
1268                 status = -EBUSY;
1269                 goto fail;
1270         }
1271
1272         tegra_dsi_writel(dsi,
1273                 DSI_TRIGGER_HOST_TRIGGER(TEGRA_DSI_ENABLE), DSI_TRIGGER);
1274
1275 #if DSI_USE_SYNC_POINTS
1276         status = tegra_dsi_syncpt(dsi);
1277         if (status < 0) {
1278                 printk(KERN_ERR "DSI syncpt for host trigger failed\n");
1279                 goto fail;
1280         }
1281 #else
1282         if (!tegra_dsi_is_controller_idle(dsi))
1283                 status = -EIO;
1284 #endif
1285
1286 fail:
1287         return status;
1288 }
1289
1290 static int _tegra_dsi_write_data(struct tegra_dc_dsi_data *dsi,
1291                                         u8 *pdata, u8 data_id, u16 data_len)
1292 {
1293         u8 virtual_channel;
1294         u8 *pval;
1295         u32 val;
1296         int err;
1297
1298         err = 0;
1299
1300         virtual_channel = dsi->info.virtual_channel <<
1301                                                 DSI_VIR_CHANNEL_BIT_POSITION;
1302
1303         /* always use hw for ecc */
1304         val = (virtual_channel | data_id) << 0 |
1305                         data_len << 8;
1306         tegra_dsi_writel(dsi, val, DSI_WR_DATA);
1307
1308         /* if pdata != NULL, pkt type is long pkt */
1309         if (pdata != NULL) {
1310                 while (data_len) {
1311                         if (data_len >= 4) {
1312                                 val = ((u32 *) pdata)[0];
1313                                 data_len -= 4;
1314                                 pdata += 4;
1315                         } else {
1316                                 val = 0;
1317                                 pval = (u8 *) &val;
1318                                 do
1319                                         *pval++ = *pdata++;
1320                                 while (--data_len);
1321                         }
1322                         tegra_dsi_writel(dsi, val, DSI_WR_DATA);
1323                 }
1324         }
1325
1326         err = tegra_dsi_host_trigger(dsi);
1327         if (err < 0)
1328                 printk(KERN_ERR "DSI host trigger failed\n");
1329
1330         return err;
1331 }
1332
1333 int tegra_dsi_write_data(struct tegra_dc *dc,
1334                         struct tegra_dc_dsi_data *dsi,
1335                         u8 *pdata, u8 data_id, u16 data_len)
1336 {
1337         bool switch_back_to_hs_mode;
1338         bool switch_back_to_dc_mode;
1339         int err;
1340
1341         err = 0;
1342         switch_back_to_hs_mode = false;
1343         switch_back_to_dc_mode = false;
1344
1345         if ((dsi->status.init != DSI_MODULE_INIT) ||
1346                 (dsi->status.lphs == DSI_LPHS_NOT_INIT) ||
1347                 (dsi->status.lp_op == DSI_LP_OP_NOT_INIT)) {
1348                 err = -EPERM;
1349                 goto fail;
1350         }
1351
1352         if (!tegra_dsi_is_controller_idle(dsi)) {
1353                 err = -EBUSY;
1354                 goto fail;
1355         }
1356
1357         err = 0;
1358
1359         if (dsi->status.lphs == DSI_LPHS_IN_HS_MODE) {
1360                 if (dsi->info.hs_cmd_mode_supported) {
1361                         if (dsi->status.driven == DSI_DRIVEN_MODE_DC) {
1362                                 dsi->driven_mode = TEGRA_DSI_DRIVEN_BY_HOST;
1363                                 tegra_dsi_set_to_hs_mode(dc, dsi);
1364                                 switch_back_to_dc_mode = true;
1365                         }
1366                 } else {
1367                         tegra_dsi_set_to_lp_mode(dc, dsi, DSI_LP_OP_WRITE);
1368                         switch_back_to_hs_mode = true;
1369                 }
1370         }
1371
1372         err = _tegra_dsi_write_data(dsi, pdata, data_id, data_len);
1373
1374
1375         if (switch_back_to_dc_mode)
1376                 dsi->driven_mode = TEGRA_DSI_DRIVEN_BY_DC;
1377         if (switch_back_to_dc_mode || switch_back_to_hs_mode)
1378                 tegra_dsi_set_to_hs_mode(dc, dsi);
1379
1380 fail:
1381         return err;
1382 }
1383 EXPORT_SYMBOL(tegra_dsi_write_data);
1384
1385 static int tegra_dsi_send_panel_cmd(struct tegra_dc *dc,
1386                                         struct tegra_dc_dsi_data *dsi,
1387                                         struct tegra_dsi_cmd *cmd,
1388                                         u32 n_cmd)
1389 {
1390         u32 i;
1391         int err;
1392
1393         err = 0;
1394         for (i = 0; i < n_cmd; i++) {
1395                 struct tegra_dsi_cmd *cur_cmd;
1396                 cur_cmd = &cmd[i];
1397
1398                 if (cur_cmd->cmd_type == TEGRA_DSI_DELAY_MS)
1399                         mdelay(cur_cmd->sp_len_dly.delay_ms);
1400                 else {
1401                         err = tegra_dsi_write_data(dc, dsi,
1402                                                 cur_cmd->pdata,
1403                                                 cur_cmd->data_id,
1404                                                 cur_cmd->sp_len_dly.data_len);
1405                         if (err < 0)
1406                                 break;
1407                 }
1408         }
1409         return err;
1410 }
1411
1412 static int tegra_dsi_bta(struct tegra_dc_dsi_data *dsi)
1413 {
1414         u32 val;
1415         u32 poll_time;
1416         int err;
1417
1418         poll_time = 0;
1419         err = 0;
1420
1421         val = tegra_dsi_readl(dsi, DSI_HOST_DSI_CONTROL);
1422         val |= DSI_HOST_DSI_CONTROL_IMM_BTA(TEGRA_DSI_ENABLE);
1423         tegra_dsi_writel(dsi, val, DSI_HOST_DSI_CONTROL);
1424
1425 #if DSI_USE_SYNC_POINTS
1426         /* FIXME: Workaround for nvhost_syncpt_read */
1427         dsi->syncpt_val = nvhost_syncpt_update_min(
1428                         &dsi->dc->ndev->host->syncpt, dsi->syncpt_id);
1429
1430         val = DSI_INCR_SYNCPT_COND(OP_DONE) |
1431                 DSI_INCR_SYNCPT_INDX(dsi->syncpt_id);
1432         tegra_dsi_writel(dsi, val, DSI_INCR_SYNCPT);
1433
1434         /* TODO: Use interrupt rather than polling */
1435         err = nvhost_syncpt_wait(&dsi->dc->ndev->host->syncpt,
1436                 dsi->syncpt_id, dsi->syncpt_val + 1);
1437         if (err < 0)
1438                 printk(KERN_ERR "DSI sync point failure\n");
1439         else
1440                 (dsi->syncpt_val)++;
1441 #else
1442         while (poll_time <  DSI_STATUS_POLLING_DURATION_USEC) {
1443                 val = tegra_dsi_readl(dsi, DSI_HOST_DSI_CONTROL);
1444                 val &= DSI_HOST_DSI_CONTROL_IMM_BTA(TEGRA_DSI_ENABLE);
1445                 if (!val)
1446                         break;
1447                 udelay(DSI_STATUS_POLLING_DELAY_USEC);
1448                 poll_time += DSI_STATUS_POLLING_DELAY_USEC;
1449         }
1450         if (poll_time > DSI_STATUS_POLLING_DURATION_USEC)
1451                 err = -EBUSY;
1452 #endif
1453
1454         return err;
1455 }
1456
1457 static void tegra_dsi_read_fifo(struct tegra_dc *dc,
1458                         struct tegra_dc_dsi_data *dsi,
1459                         u32 rd_fifo_cnt, u8 *read_fifo)
1460 {
1461         u32 val;
1462         u32 i;
1463
1464         /* Read data from FIFO */
1465         for (i = 0; i < rd_fifo_cnt; i++) {
1466                 val = tegra_dsi_readl(dsi, DSI_RD_DATA);
1467                 printk(KERN_INFO "Read data[%d]: 0x%x\n", i, val);
1468                 memcpy(read_fifo, &val, 4);
1469                 read_fifo += 4;
1470         }
1471
1472         /* Make sure all the data is read from the FIFO */
1473         val = tegra_dsi_readl(dsi, DSI_STATUS);
1474         val &= DSI_STATUS_RD_FIFO_COUNT(0x1f);
1475         if (val)
1476                 dev_err(&dc->ndev->dev, "DSI FIFO_RD_CNT not zero"
1477                 " even after reading FIFO_RD_CNT words from read fifo\n");
1478 }
1479
1480 static int tegra_dsi_parse_read_response(struct tegra_dc *dc,
1481                                         u32 rd_fifo_cnt, u8 *read_fifo)
1482 {
1483         int err;
1484         u32 payload_size;
1485
1486         payload_size = 0;
1487         err = 0;
1488
1489         printk(KERN_INFO "escape sequence[0x%x]\n", read_fifo[0]);
1490         switch (read_fifo[4] & 0xff) {
1491         case GEN_LONG_RD_RES:
1492                 /* Fall through */
1493         case DCS_LONG_RD_RES:
1494                 payload_size = (read_fifo[5] |
1495                                 (read_fifo[6] << 8)) & 0xFFFF;
1496                 printk(KERN_INFO "Long read response Packet\n"
1497                                 "payload_size[0x%x]\n", payload_size);
1498                 break;
1499         case GEN_1_BYTE_SHORT_RD_RES:
1500                 /* Fall through */
1501         case DCS_1_BYTE_SHORT_RD_RES:
1502                 payload_size = 1;
1503                 printk(KERN_INFO "Short read response Packet\n"
1504                         "payload_size[0x%x]\n", payload_size);
1505                 break;
1506         case GEN_2_BYTE_SHORT_RD_RES:
1507                 /* Fall through */
1508         case DCS_2_BYTE_SHORT_RD_RES:
1509                 payload_size = 2;
1510                 printk(KERN_INFO "Short read response Packet\n"
1511                         "payload_size[0x%x]\n", payload_size);
1512                 break;
1513         case ACK_ERR_RES:
1514                 payload_size = 2;
1515                 printk(KERN_INFO "Acknowledge error report response\n"
1516                         "Packet payload_size[0x%x]\n", payload_size);
1517                 break;
1518         default:
1519                 /*reading from RD_FIFO_COUNT*/
1520                 printk(KERN_INFO "Invalid read response payload_size\n");
1521                 err = -EINVAL;
1522                 break;
1523         }
1524         return err;
1525 }
1526
1527 int tegra_dsi_read_data(struct tegra_dc *dc,
1528                                 struct tegra_dc_dsi_data *dsi,
1529                                 u32 max_ret_payload_size,
1530                                 u32 panel_reg_addr, u8 *read_data)
1531 {
1532         u32 val;
1533         int err;
1534         u32 poll_time;
1535         u32 rd_fifo_cnt;
1536         bool switch_back_to_hs_mode;
1537         bool restart_dc_stream;
1538         bool switch_back_to_dc_mode;
1539
1540         err = 0;
1541         switch_back_to_hs_mode = false;
1542         restart_dc_stream = false;
1543         switch_back_to_dc_mode = false;
1544
1545         if ((dsi->status.init != DSI_MODULE_INIT) ||
1546                 (dsi->status.lphs == DSI_LPHS_NOT_INIT) ||
1547                 (dsi->status.driven == DSI_DRIVEN_MODE_NOT_INIT) ||
1548                 (dsi->status.lp_op == DSI_LP_OP_NOT_INIT)) {
1549                 err = -EPERM;
1550                 goto fail;
1551         }
1552
1553         tegra_dc_io_start(dc);
1554
1555         val = tegra_dsi_readl(dsi, DSI_STATUS);
1556         val &= DSI_STATUS_RD_FIFO_COUNT(0x1f);
1557         if (val) {
1558                 err = -EBUSY;
1559                 dev_err(&dc->ndev->dev, "DSI fifo count not zero\n");
1560                 goto fail;
1561         }
1562
1563         if (!tegra_dsi_is_controller_idle(dsi)) {
1564                 err = -EBUSY;
1565                 dev_err(&dc->ndev->dev, "DSI trigger bit is already set\n");
1566                 goto fail;
1567         }
1568
1569         val = tegra_dsi_readl(dsi, DSI_STATUS);
1570         val &= (DSI_STATUS_LB_OVERFLOW(0x1) | DSI_STATUS_LB_UNDERFLOW(0x1));
1571         if (val) {
1572                 dev_warn(&dc->ndev->dev, "Reset overflow/underflow\n");
1573                 val = tegra_dsi_readl(dsi, DSI_HOST_DSI_CONTROL);
1574                 val |= DSI_HOST_CONTROL_FIFO_STAT_RESET(0x1);
1575                 tegra_dsi_writel(dsi, val, DSI_HOST_DSI_CONTROL);
1576                 ndelay(200);
1577         }
1578
1579         if (dsi->status.lphs == DSI_LPHS_IN_HS_MODE) {
1580                 if (dsi->status.driven == DSI_DRIVEN_MODE_DC) {
1581                         if (dsi->status.dc_stream == DSI_DC_STREAM_ENABLE) {
1582                                 tegra_dsi_stop_dc_stream_at_frame_end(dc, dsi);
1583                                 restart_dc_stream = true;
1584                         }
1585                         dsi->driven_mode = TEGRA_DSI_DRIVEN_BY_HOST;
1586                         switch_back_to_dc_mode = true;
1587                         if (dsi->info.hs_cmd_mode_supported) {
1588                                 err = tegra_dsi_set_to_hs_mode(dc, dsi);
1589                                 if (err < 0) {
1590                                         dev_err(&dc->ndev->dev,
1591                                         "DSI failed to go to HS host driven mode\n");
1592                                         goto fail;
1593                                 }
1594                         }
1595                 }
1596                 if (!dsi->info.hs_cmd_mode_supported) {
1597                         err =
1598                         tegra_dsi_set_to_lp_mode(dc, dsi, DSI_LP_OP_WRITE);
1599                         if (err < 0) {
1600                                 dev_err(&dc->ndev->dev,
1601                                 "DSI failed to go to LP mode\n");
1602                                 goto fail;
1603                         }
1604                         switch_back_to_hs_mode = true;
1605                 }
1606         }
1607
1608         /* Set max return payload size in words */
1609         err = _tegra_dsi_write_data(dsi, NULL,
1610                 dsi_command_max_return_pkt_size,
1611                 max_ret_payload_size);
1612         if (err < 0) {
1613                 dev_err(&dc->ndev->dev,
1614                                 "DSI write failed\n");
1615                 goto fail;
1616         }
1617
1618         /* DCS to read given panel register */
1619         err = _tegra_dsi_write_data(dsi, NULL,
1620                 dsi_command_dcs_read_with_no_params,
1621                 panel_reg_addr);
1622         if (err < 0) {
1623                 dev_err(&dc->ndev->dev,
1624                                 "DSI write failed\n");
1625                 goto fail;
1626         }
1627
1628         if (switch_back_to_hs_mode) {
1629                 err = tegra_dsi_set_to_lp_mode(dc, dsi, DSI_LP_OP_READ);
1630                 if (err < 0) {
1631                         dev_err(&dc->ndev->dev,
1632                         "DSI failed to go to LP mode\n");
1633                         goto fail;
1634                 }
1635         }
1636
1637         err = tegra_dsi_bta(dsi);
1638         if (err < 0) {
1639                 dev_err(&dc->ndev->dev,
1640                         "DSI IMM BTA timeout\n");
1641                 goto fail;
1642         }
1643
1644         poll_time = 0;
1645         while (poll_time <  DSI_DELAY_FOR_READ_FIFO) {
1646                 mdelay(1);
1647                 val = tegra_dsi_readl(dsi, DSI_STATUS);
1648                 rd_fifo_cnt = val & DSI_STATUS_RD_FIFO_COUNT(0x1f);
1649                 if (rd_fifo_cnt << 2 > DSI_READ_FIFO_DEPTH)
1650                         dev_err(&dc->ndev->dev,
1651                         "DSI RD_FIFO_CNT is greater than RD_FIFO_DEPTH\n");
1652                         break;
1653                 poll_time++;
1654         }
1655
1656         if (rd_fifo_cnt == 0) {
1657                 dev_info(&dc->ndev->dev,
1658                         "DSI RD_FIFO_CNT is zero\n");
1659                 err = -EINVAL;
1660                 goto fail;
1661         }
1662
1663         if (val & DSI_STATUS_LB_UNDERFLOW(0x1) ||
1664                 val & DSI_STATUS_LB_OVERFLOW(0x1)) {
1665                 dev_err(&dc->ndev->dev,
1666                         "DSI overflow/underflow error\n");
1667                 err = -EINVAL;
1668                 goto fail;
1669         }
1670
1671         tegra_dsi_read_fifo(dc, dsi, rd_fifo_cnt, read_data);
1672
1673         err = tegra_dsi_parse_read_response(dc, rd_fifo_cnt, read_data);
1674 fail:
1675         if (switch_back_to_dc_mode)
1676                 dsi->driven_mode = TEGRA_DSI_DRIVEN_BY_DC;
1677         if (switch_back_to_dc_mode || switch_back_to_hs_mode)
1678                 tegra_dsi_set_to_hs_mode(dc, dsi);
1679         if (restart_dc_stream)
1680                 tegra_dsi_start_dc_stream(dc, dsi);
1681
1682         tegra_dc_io_end(dc);
1683
1684         return err;
1685 }
1686 EXPORT_SYMBOL(tegra_dsi_read_data);
1687
1688 static int tegra_dsi_enter_ulpm(struct tegra_dc_dsi_data *dsi)
1689 {
1690         u32 val;
1691         int ret;
1692
1693         ret = 0;
1694
1695         val = tegra_dsi_readl(dsi, DSI_HOST_DSI_CONTROL);
1696         val &= ~DSI_HOST_DSI_CONTROL_ULTRA_LOW_POWER(3);
1697         val |= DSI_HOST_DSI_CONTROL_ULTRA_LOW_POWER(ENTER_ULPM);
1698         tegra_dsi_writel(dsi, val, DSI_HOST_DSI_CONTROL);
1699
1700 #if DSI_USE_SYNC_POINTS
1701         ret = tegra_dsi_syncpt(dsi);
1702         if (ret < 0) {
1703                 printk(KERN_ERR "DSI syncpt for ulpm enter failed\n");
1704                 goto fail;
1705         }
1706 #else
1707         /* TODO: Find exact delay required */
1708         mdelay(10);
1709 #endif
1710         dsi->ulpm = true;
1711 fail:
1712         return ret;
1713 }
1714
1715 static int tegra_dsi_exit_ulpm(struct tegra_dc_dsi_data *dsi)
1716 {
1717         u32 val;
1718         int ret;
1719
1720         ret = 0;
1721
1722         val = tegra_dsi_readl(dsi, DSI_HOST_DSI_CONTROL);
1723         val &= ~DSI_HOST_DSI_CONTROL_ULTRA_LOW_POWER(3);
1724         val |= DSI_HOST_DSI_CONTROL_ULTRA_LOW_POWER(EXIT_ULPM);
1725         tegra_dsi_writel(dsi, val, DSI_HOST_DSI_CONTROL);
1726
1727 #if DSI_USE_SYNC_POINTS
1728         ret = tegra_dsi_syncpt(dsi);
1729         if (ret < 0) {
1730                 printk(KERN_ERR "DSI syncpt for ulpm exit failed\n");
1731                 goto fail;
1732         }
1733 #else
1734         /* TODO: Find exact delay required */
1735         mdelay(10);
1736 #endif
1737         dsi->ulpm = false;
1738
1739         val = tegra_dsi_readl(dsi, DSI_HOST_DSI_CONTROL);
1740         val &= ~DSI_HOST_DSI_CONTROL_ULTRA_LOW_POWER(0x3);
1741         val |= DSI_HOST_DSI_CONTROL_ULTRA_LOW_POWER(NORMAL);
1742         tegra_dsi_writel(dsi, val, DSI_HOST_DSI_CONTROL);
1743 fail:
1744         return ret;
1745
1746 }
1747
1748 static void tegra_dc_dsi_enable(struct tegra_dc *dc)
1749 {
1750         struct tegra_dc_dsi_data *dsi = tegra_dc_get_outdata(dc);
1751         int err;
1752         u32 val;
1753
1754         tegra_dc_io_start(dc);
1755         mutex_lock(&dsi->lock);
1756
1757         /* Stop DC stream before configuring DSI registers
1758          * to avoid visible glitches on panel during transition
1759          * from bootloader to kernel driver
1760          */
1761         tegra_dsi_stop_dc_stream_at_frame_end(dc, dsi);
1762
1763         if (dsi->enabled) {
1764                 if (dsi->ulpm) {
1765                         if (tegra_dsi_exit_ulpm(dsi) < 0) {
1766                                 printk(KERN_ERR "DSI failed to exit ulpm\n");
1767                                 goto fail;
1768                         }
1769                 }
1770
1771                 if (dsi->info.panel_reset) {
1772                         err = tegra_dsi_send_panel_cmd(dc, dsi,
1773                                                         dsi->info.dsi_init_cmd,
1774                                                         dsi->info.n_init_cmd);
1775                         if (err < 0) {
1776                                 dev_err(&dc->ndev->dev,
1777                                 "dsi: error sending dsi init cmd\n");
1778                                 goto fail;
1779                         }
1780                 } else if (dsi->info.dsi_late_resume_cmd) {
1781                         err = tegra_dsi_send_panel_cmd(dc, dsi,
1782                                                 dsi->info.dsi_late_resume_cmd,
1783                                                 dsi->info.n_late_resume_cmd);
1784                         if (err < 0) {
1785                                 dev_err(&dc->ndev->dev,
1786                                 "dsi: error sending late resume cmd\n");
1787                                 goto fail;
1788                         }
1789                 }
1790         } else {
1791                 err = tegra_dsi_init_hw(dc, dsi);
1792                 if (err < 0) {
1793                         dev_err(&dc->ndev->dev,
1794                                 "dsi: not able to init dsi hardware\n");
1795                         goto fail;
1796                 }
1797
1798                 if (dsi->ulpm) {
1799                         if (tegra_dsi_enter_ulpm(dsi) < 0) {
1800                                 printk(KERN_ERR "DSI failed to enter ulpm\n");
1801                                 goto fail;
1802                         }
1803                         val = DSI_PAD_CONTROL_PAD_PDIO(0) |
1804                                 DSI_PAD_CONTROL_PAD_PDIO_CLK(0) |
1805                                 DSI_PAD_CONTROL_PAD_PULLDN_ENAB
1806                                                 (TEGRA_DSI_DISABLE);
1807                         tegra_dsi_writel(dsi, val, DSI_PAD_CONTROL);
1808                         if (tegra_dsi_exit_ulpm(dsi) < 0) {
1809                                 printk(KERN_ERR "DSI failed to exit ulpm\n");
1810                                 goto fail;
1811                         }
1812                 }
1813
1814                 err = tegra_dsi_set_to_lp_mode(dc, dsi, DSI_LP_OP_WRITE);
1815                 if (err < 0) {
1816                         dev_err(&dc->ndev->dev,
1817                                 "dsi: not able to set to lp mode\n");
1818                         goto fail;
1819                 }
1820
1821                 err = tegra_dsi_send_panel_cmd(dc, dsi, dsi->info.dsi_init_cmd,
1822                                                 dsi->info.n_init_cmd);
1823                 if (err < 0) {
1824                         dev_err(&dc->ndev->dev,
1825                                 "dsi: error while sending dsi init cmd\n");
1826                         goto fail;
1827                 }
1828
1829                 err = tegra_dsi_set_to_hs_mode(dc, dsi);
1830                 if (err < 0) {
1831                         dev_err(&dc->ndev->dev,
1832                                 "dsi: not able to set to hs mode\n");
1833                         goto fail;
1834                 }
1835
1836                 dsi->enabled = true;
1837         }
1838
1839         if (dsi->status.driven == DSI_DRIVEN_MODE_DC)
1840                 tegra_dsi_start_dc_stream(dc, dsi);
1841 fail:
1842         mutex_unlock(&dsi->lock);
1843         tegra_dc_io_end(dc);
1844 }
1845
1846 static void _tegra_dc_dsi_init(struct tegra_dc *dc)
1847 {
1848         struct tegra_dc_dsi_data *dsi = tegra_dc_get_outdata(dc);
1849
1850         tegra_dsi_init_sw(dc, dsi);
1851         /* TODO: Configure the CSI pad configuration */
1852 }
1853
1854 static int tegra_dc_dsi_cp_p_cmd(struct tegra_dsi_cmd *src,
1855                                         struct tegra_dsi_cmd *dst, u16 n_cmd)
1856 {
1857         u16 i;
1858         u16 len;
1859
1860         memcpy(dst, src, sizeof(*dst) * n_cmd);
1861
1862         for (i = 0; i < n_cmd; i++)
1863                 if (src[i].pdata) {
1864                         len = sizeof(*src[i].pdata) *
1865                                         src[i].sp_len_dly.data_len;
1866                         dst[i].pdata = kzalloc(len, GFP_KERNEL);
1867                         if (!dst[i].pdata)
1868                                 goto free_cmd_pdata;
1869                         memcpy(dst[i].pdata, src[i].pdata, len);
1870                 }
1871
1872         return 0;
1873
1874 free_cmd_pdata:
1875         for (--i; i >= 0; i--)
1876                 if (dst[i].pdata)
1877                         kfree(dst[i].pdata);
1878         return -ENOMEM;
1879 }
1880
1881 static int tegra_dc_dsi_cp_info(struct tegra_dc_dsi_data *dsi,
1882                                         struct tegra_dsi_out *p_dsi)
1883 {
1884         struct tegra_dsi_cmd *p_init_cmd;
1885         struct tegra_dsi_cmd *p_early_suspend_cmd;
1886         struct tegra_dsi_cmd *p_late_resume_cmd;
1887         struct tegra_dsi_cmd *p_suspend_cmd;
1888         int err;
1889
1890         if (p_dsi->n_data_lanes > MAX_DSI_DATA_LANES)
1891                 return -EINVAL;
1892
1893         p_init_cmd = kzalloc(sizeof(*p_init_cmd) *
1894                                 p_dsi->n_init_cmd, GFP_KERNEL);
1895         if (!p_init_cmd)
1896                 return -ENOMEM;
1897
1898         if (p_dsi->dsi_early_suspend_cmd) {
1899                 p_early_suspend_cmd = kzalloc(sizeof(*p_early_suspend_cmd) *
1900                                         p_dsi->n_early_suspend_cmd,
1901                                         GFP_KERNEL);
1902                 if (!p_early_suspend_cmd) {
1903                         err = -ENOMEM;
1904                         goto err_free_init_cmd;
1905                 }
1906         }
1907
1908         if (p_dsi->dsi_late_resume_cmd) {
1909                 p_late_resume_cmd = kzalloc(sizeof(*p_late_resume_cmd) *
1910                                         p_dsi->n_late_resume_cmd,
1911                                         GFP_KERNEL);
1912                 if (!p_late_resume_cmd) {
1913                         err = -ENOMEM;
1914                         goto err_free_p_early_suspend_cmd;
1915                 }
1916         }
1917
1918         p_suspend_cmd = kzalloc(sizeof(*p_suspend_cmd) * p_dsi->n_suspend_cmd,
1919                                 GFP_KERNEL);
1920         if (!p_suspend_cmd) {
1921                 err = -ENOMEM;
1922                 goto err_free_p_late_resume_cmd;
1923         }
1924
1925         memcpy(&dsi->info, p_dsi, sizeof(dsi->info));
1926
1927         /* Copy panel init cmd */
1928         err = tegra_dc_dsi_cp_p_cmd(p_dsi->dsi_init_cmd,
1929                                                 p_init_cmd, p_dsi->n_init_cmd);
1930         if (err < 0)
1931                 goto err_free;
1932         dsi->info.dsi_init_cmd = p_init_cmd;
1933
1934         /* Copy panel early suspend cmd */
1935         if (p_dsi->dsi_early_suspend_cmd) {
1936                 err = tegra_dc_dsi_cp_p_cmd(p_dsi->dsi_early_suspend_cmd,
1937                                         p_early_suspend_cmd,
1938                                         p_dsi->n_early_suspend_cmd);
1939                 if (err < 0)
1940                         goto err_free;
1941                 dsi->info.dsi_early_suspend_cmd = p_early_suspend_cmd;
1942         }
1943
1944         /* Copy panel late resume cmd */
1945         if (p_dsi->dsi_late_resume_cmd) {
1946                 err = tegra_dc_dsi_cp_p_cmd(p_dsi->dsi_late_resume_cmd,
1947                                                 p_late_resume_cmd,
1948                                                 p_dsi->n_late_resume_cmd);
1949                 if (err < 0)
1950                         goto err_free;
1951                 dsi->info.dsi_late_resume_cmd = p_late_resume_cmd;
1952         }
1953
1954         /* Copy panel suspend cmd */
1955         err = tegra_dc_dsi_cp_p_cmd(p_dsi->dsi_suspend_cmd, p_suspend_cmd,
1956                                         p_dsi->n_suspend_cmd);
1957         if (err < 0)
1958                 goto err_free;
1959         dsi->info.dsi_suspend_cmd = p_suspend_cmd;
1960
1961         if (!dsi->info.panel_reset_timeout_msec)
1962                 dsi->info.panel_reset_timeout_msec =
1963                                                 DEFAULT_PANEL_RESET_TIMEOUT;
1964
1965         if (!dsi->info.panel_buffer_size_byte)
1966                 dsi->info.panel_buffer_size_byte = DEFAULT_PANEL_BUFFER_BYTE;
1967
1968         if (!dsi->info.max_panel_freq_khz) {
1969                 dsi->info.max_panel_freq_khz = DEFAULT_MAX_DSI_PHY_CLK_KHZ;
1970
1971                 if (dsi->info.video_burst_mode >
1972                                 TEGRA_DSI_VIDEO_NONE_BURST_MODE_WITH_SYNC_END){
1973                         dev_err(&dsi->dc->ndev->dev, "DSI: max_panel_freq_khz"
1974                                         "is not set for DSI burst mode.\n");
1975                         dsi->info.video_burst_mode =
1976                                 TEGRA_DSI_VIDEO_BURST_MODE_LOWEST_SPEED;
1977                 }
1978         }
1979
1980         if (!dsi->info.lp_cmd_mode_freq_khz)
1981                 dsi->info.lp_cmd_mode_freq_khz = DEFAULT_LP_CMD_MODE_CLK_KHZ;
1982
1983         if (!dsi->info.chip_id || !dsi->info.chip_rev)
1984                 printk(KERN_WARNING "DSI: Failed to get chip info\n");
1985
1986         if (!dsi->info.lp_read_cmd_mode_freq_khz)
1987                 dsi->info.lp_read_cmd_mode_freq_khz =
1988                         dsi->info.lp_cmd_mode_freq_khz;
1989
1990         /* host mode is for testing only */
1991         dsi->driven_mode = TEGRA_DSI_DRIVEN_BY_DC;
1992         return 0;
1993
1994 err_free:
1995         kfree(p_suspend_cmd);
1996 err_free_p_late_resume_cmd:
1997         kfree(p_late_resume_cmd);
1998 err_free_p_early_suspend_cmd:
1999         kfree(p_early_suspend_cmd);
2000 err_free_init_cmd:
2001         kfree(p_init_cmd);
2002         return err;
2003 }
2004
2005 static int tegra_dc_dsi_init(struct tegra_dc *dc)
2006 {
2007         struct tegra_dc_dsi_data *dsi;
2008         struct resource *res;
2009         struct resource *base_res;
2010         void __iomem *base;
2011         struct clk *dc_clk = NULL;
2012         struct clk *dsi_clk = NULL;
2013         struct tegra_dsi_out *dsi_pdata;
2014         int err;
2015
2016         err = 0;
2017
2018         dsi = kzalloc(sizeof(*dsi), GFP_KERNEL);
2019         if (!dsi)
2020                 return -ENOMEM;
2021
2022         res = nvhost_get_resource_byname(dc->ndev, IORESOURCE_MEM,
2023                                         "dsi_regs");
2024         if (!res) {
2025                 dev_err(&dc->ndev->dev, "dsi: no mem resource\n");
2026                 err = -ENOENT;
2027                 goto err_free_dsi;
2028         }
2029
2030         base_res = request_mem_region(res->start, resource_size(res),
2031                                 dc->ndev->name);
2032         if (!base_res) {
2033                 dev_err(&dc->ndev->dev, "dsi: request_mem_region failed\n");
2034                 err = -EBUSY;
2035                 goto err_free_dsi;
2036         }
2037
2038         base = ioremap(res->start, resource_size(res));
2039         if (!base) {
2040                 dev_err(&dc->ndev->dev, "dsi: registers can't be mapped\n");
2041                 err = -EBUSY;
2042                 goto err_release_regs;
2043         }
2044
2045         dsi_pdata = dc->pdata->default_out->dsi;
2046         if (!dsi_pdata) {
2047                 dev_err(&dc->ndev->dev, "dsi: dsi data not available\n");
2048                 goto err_release_regs;
2049         }
2050
2051         if (dsi_pdata->dsi_instance)
2052                 dsi_clk = clk_get(&dc->ndev->dev, "dsib");
2053         else
2054                 dsi_clk = clk_get(&dc->ndev->dev, "dsia");
2055
2056         if (IS_ERR_OR_NULL(dsi_clk)) {
2057                 dev_err(&dc->ndev->dev, "dsi: can't get clock\n");
2058                 err = -EBUSY;
2059                 goto err_release_regs;
2060         }
2061
2062         dc_clk = clk_get_sys(dev_name(&dc->ndev->dev), NULL);
2063         if (IS_ERR_OR_NULL(dc_clk)) {
2064                 dev_err(&dc->ndev->dev, "dsi: dc clock %s unavailable\n",
2065                         dev_name(&dc->ndev->dev));
2066                 err = -EBUSY;
2067                 goto err_clk_put;
2068         }
2069
2070         mutex_init(&dsi->lock);
2071         dsi->dc = dc;
2072         dsi->base = base;
2073         dsi->base_res = base_res;
2074         dsi->dc_clk = dc_clk;
2075         dsi->dsi_clk = dsi_clk;
2076
2077         err = tegra_dc_dsi_cp_info(dsi, dsi_pdata);
2078         if (err < 0)
2079                 goto err_dsi_data;
2080
2081         tegra_dc_set_outdata(dc, dsi);
2082         _tegra_dc_dsi_init(dc);
2083
2084         return 0;
2085
2086 err_dsi_data:
2087 err_clk_put:
2088         clk_put(dsi_clk);
2089 err_release_regs:
2090         release_resource(base_res);
2091 err_free_dsi:
2092         kfree(dsi);
2093
2094         return err;
2095 }
2096
2097 static void tegra_dc_dsi_destroy(struct tegra_dc *dc)
2098 {
2099         struct tegra_dc_dsi_data *dsi = tegra_dc_get_outdata(dc);
2100         u16 i;
2101         u32 val;
2102
2103         mutex_lock(&dsi->lock);
2104
2105         /* free up the pdata */
2106         for (i = 0; i < dsi->info.n_init_cmd; i++) {
2107                 if (dsi->info.dsi_init_cmd[i].pdata)
2108                         kfree(dsi->info.dsi_init_cmd[i].pdata);
2109         }
2110         kfree(dsi->info.dsi_init_cmd);
2111
2112         /* Disable dc stream */
2113         if (dsi->status.dc_stream == DSI_DC_STREAM_ENABLE)
2114                 tegra_dsi_stop_dc_stream(dc, dsi);
2115
2116         /* Disable dsi phy clock */
2117         if (dsi->status.clk_out == DSI_PHYCLK_OUT_EN)
2118                 tegra_dsi_hs_clk_out_disable(dc, dsi);
2119
2120         val = DSI_POWER_CONTROL_LEG_DSI_ENABLE(TEGRA_DSI_DISABLE);
2121         tegra_dsi_writel(dsi, val, DSI_POWER_CONTROL);
2122
2123         iounmap(dsi->base);
2124         release_resource(dsi->base_res);
2125
2126         clk_put(dsi->dc_clk);
2127         clk_put(dsi->dsi_clk);
2128
2129         mutex_unlock(&dsi->lock);
2130
2131         mutex_destroy(&dsi->lock);
2132         kfree(dsi);
2133 }
2134
2135 static int tegra_dsi_deep_sleep(struct tegra_dc *dc,
2136                                 struct tegra_dc_dsi_data *dsi)
2137 {
2138         int err = 0;
2139         int val;
2140         struct clk *parent_clk = NULL;
2141         struct clk *base_clk = NULL;
2142
2143         if (!dsi->enabled) {
2144                 err = -EPERM;
2145                 goto fail;
2146         }
2147
2148         err = tegra_dsi_set_to_lp_mode(dc, dsi, DSI_LP_OP_WRITE);
2149         if (err < 0) {
2150                 dev_err(&dc->ndev->dev,
2151                 "DSI failed to go to LP mode\n");
2152                 goto fail;
2153         }
2154
2155         /* Suspend panel */
2156         err = tegra_dsi_send_panel_cmd(dc, dsi,
2157                         dsi->info.dsi_suspend_cmd,
2158                         dsi->info.n_suspend_cmd);
2159         if (err < 0) {
2160                 dev_err(&dc->ndev->dev,
2161                         "dsi: Error sending suspend cmd\n");
2162                 goto fail;
2163         }
2164
2165         if (!dsi->ulpm) {
2166                 err = tegra_dsi_enter_ulpm(dsi);
2167                 if (err < 0) {
2168                         dev_err(&dc->ndev->dev,
2169                                 "DSI failed to enter ulpm\n");
2170                         goto fail;
2171                 }
2172         }
2173
2174         /* Suspend pad */
2175         val = tegra_dsi_readl(dsi, DSI_PAD_CONTROL);
2176         val = DSI_PAD_CONTROL_PAD_PDIO(0x3) |
2177                 DSI_PAD_CONTROL_PAD_PDIO_CLK(0x1) |
2178                 DSI_PAD_CONTROL_PAD_PULLDN_ENAB(TEGRA_DSI_ENABLE);
2179         tegra_dsi_writel(dsi, val, DSI_PAD_CONTROL);
2180
2181         /* Suspend core-logic */
2182         val = DSI_POWER_CONTROL_LEG_DSI_ENABLE(TEGRA_DSI_DISABLE);
2183         tegra_dsi_writel(dsi, val, DSI_POWER_CONTROL);
2184
2185         /* Disable dsi fast and slow clock */
2186         parent_clk = clk_get_parent(dsi->dsi_clk);
2187         base_clk = clk_get_parent(parent_clk);
2188         if (dsi->info.dsi_instance)
2189                 tegra_clk_cfg_ex(base_clk,
2190                                 TEGRA_CLK_PLLD_CSI_OUT_ENB,
2191                                 0);
2192         else
2193                 tegra_clk_cfg_ex(base_clk,
2194                                 TEGRA_CLK_PLLD_DSI_OUT_ENB,
2195                                 0);
2196
2197         /* Disable dsi source clock */
2198         clk_disable(dsi->dsi_clk);
2199
2200         dsi->clk_ref = false;
2201         dsi->enabled = false;
2202
2203         return 0;
2204 fail:
2205         return err;
2206 }
2207
2208 static void tegra_dc_dsi_disable(struct tegra_dc *dc)
2209 {
2210         int err;
2211         struct tegra_dc_dsi_data *dsi = tegra_dc_get_outdata(dc);
2212
2213         tegra_dc_io_start(dc);
2214         mutex_lock(&dsi->lock);
2215
2216         if (dsi->status.dc_stream == DSI_DC_STREAM_ENABLE)
2217                 tegra_dsi_stop_dc_stream_at_frame_end(dc, dsi);
2218
2219         if (dsi->info.power_saving_suspend) {
2220                 if (tegra_dsi_deep_sleep(dc, dsi) < 0) {
2221                         printk(KERN_ERR "DSI failed to enter deep sleep\n");
2222                         goto fail;
2223                 }
2224         } else {
2225                 if (dsi->info.dsi_early_suspend_cmd) {
2226                         err = tegra_dsi_send_panel_cmd(dc, dsi,
2227                                 dsi->info.dsi_early_suspend_cmd,
2228                                 dsi->info.n_early_suspend_cmd);
2229                         if (err < 0) {
2230                                 dev_err(&dc->ndev->dev,
2231                                 "dsi: Error sending early suspend cmd\n");
2232                                 goto fail;
2233                         }
2234                 }
2235
2236                 if (!dsi->ulpm) {
2237                         if (tegra_dsi_enter_ulpm(dsi) < 0) {
2238                                 printk(KERN_ERR "DSI failed to enter ulpm\n");
2239                                 goto fail;
2240                         }
2241                 }
2242         }
2243
2244 fail:
2245         mutex_unlock(&dsi->lock);
2246         tegra_dc_io_end(dc);
2247 }
2248
2249 #ifdef CONFIG_PM
2250 static void tegra_dc_dsi_suspend(struct tegra_dc *dc)
2251 {
2252         struct tegra_dc_dsi_data *dsi;
2253
2254         dsi = tegra_dc_get_outdata(dc);
2255
2256         tegra_dc_io_start(dc);
2257         mutex_lock(&dsi->lock);
2258
2259         if (!dsi->enabled)
2260                 goto fail;
2261
2262         if (!dsi->info.power_saving_suspend) {
2263                 if (dsi->ulpm) {
2264                         if (tegra_dsi_exit_ulpm(dsi) < 0) {
2265                                 printk(KERN_ERR "DSI failed to exit ulpm");
2266                                 goto fail;
2267                         }
2268                 }
2269
2270                 if (tegra_dsi_deep_sleep(dc, dsi) < 0) {
2271                         printk(KERN_ERR "DSI failed to enter deep sleep\n");
2272                         goto fail;
2273                 }
2274         }
2275 fail:
2276         mutex_unlock(&dsi->lock);
2277         tegra_dc_io_end(dc);
2278 }
2279
2280 static void tegra_dc_dsi_resume(struct tegra_dc *dc)
2281 {
2282         /* Not required since tegra_dc_dsi_enable
2283          * will reconfigure the controller from scratch
2284          */
2285 }
2286 #endif
2287
2288 struct tegra_dc_out_ops tegra_dc_dsi_ops = {
2289         .init = tegra_dc_dsi_init,
2290         .destroy = tegra_dc_dsi_destroy,
2291         .enable = tegra_dc_dsi_enable,
2292         .disable = tegra_dc_dsi_disable,
2293 #ifdef CONFIG_PM
2294         .suspend = tegra_dc_dsi_suspend,
2295         .resume = tegra_dc_dsi_resume,
2296 #endif
2297 };