video: tegra: dsi: Soft reset if dsi host busy
[linux-2.6.git] / drivers / video / tegra / dc / dsi.c
1 /*
2  * drivers/video/tegra/dc/dsi.c
3  *
4  * Copyright (c) 2011, NVIDIA Corporation.
5  *
6  * This software is licensed under the terms of the GNU General Public
7  * License version 2, as published by the Free Software Foundation, and
8  * may be copied, distributed, and modified under those terms.
9  *
10  * This program is distributed in the hope that it will be useful,
11  * but WITHOUT ANY WARRANTY; without even the implied warranty of
12  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
13  * GNU General Public License for more details.
14  *
15  */
16
17 #include <linux/clk.h>
18 #include <linux/delay.h>
19 #include <linux/err.h>
20 #include <linux/fb.h>
21 #include <linux/gpio.h>
22 #include <linux/interrupt.h>
23 #include <linux/kernel.h>
24 #include <linux/slab.h>
25 #include <linux/spinlock.h>
26 #include <linux/workqueue.h>
27
28 #include <mach/clk.h>
29 #include <mach/dc.h>
30 #include <mach/fb.h>
31 #include <mach/csi.h>
32 #include <linux/nvhost.h>
33
34 #include "dc_reg.h"
35 #include "dc_priv.h"
36 #include "dsi_regs.h"
37 #include "dsi.h"
38
39 #define DSI_USE_SYNC_POINTS             1
40 #define S_TO_MS(x)                      (1000 * (x))
41
42 #define DSI_MODULE_NOT_INIT             0x0
43 #define DSI_MODULE_INIT                 0x1
44
45 #define DSI_LPHS_NOT_INIT               0x0
46 #define DSI_LPHS_IN_LP_MODE             0x1
47 #define DSI_LPHS_IN_HS_MODE             0x2
48
49 #define DSI_VIDEO_TYPE_NOT_INIT         0x0
50 #define DSI_VIDEO_TYPE_VIDEO_MODE       0x1
51 #define DSI_VIDEO_TYPE_CMD_MODE         0x2
52
53 #define DSI_DRIVEN_MODE_NOT_INIT        0x0
54 #define DSI_DRIVEN_MODE_DC              0x1
55 #define DSI_DRIVEN_MODE_HOST            0x2
56
57 #define DSI_PHYCLK_OUT_DIS              0x0
58 #define DSI_PHYCLK_OUT_EN               0x1
59
60 #define DSI_PHYCLK_NOT_INIT             0x0
61 #define DSI_PHYCLK_CONTINUOUS           0x1
62 #define DSI_PHYCLK_TX_ONLY              0x2
63
64 #define DSI_CLK_BURST_NOT_INIT          0x0
65 #define DSI_CLK_BURST_NONE_BURST        0x1
66 #define DSI_CLK_BURST_BURST_MODE        0x2
67
68 #define DSI_DC_STREAM_DISABLE           0x0
69 #define DSI_DC_STREAM_ENABLE            0x1
70
71 #define DSI_LP_OP_NOT_INIT              0x0
72 #define DSI_LP_OP_WRITE                 0x1
73 #define DSI_LP_OP_READ                  0x2
74
75 static bool enable_read_debug;
76 module_param(enable_read_debug, bool, 0644);
77 MODULE_PARM_DESC(enable_read_debug,
78                 "Enable to print read fifo and return packet type");
79
80 struct dsi_status {
81         unsigned init:2;
82
83         unsigned lphs:2;
84
85         unsigned vtype:2;
86         unsigned driven:2;
87
88         unsigned clk_out:2;
89         unsigned clk_mode:2;
90         unsigned clk_burst:2;
91
92         unsigned lp_op:2;
93
94         unsigned dc_stream:1;
95 };
96
97 /* source of video data */
98 enum {
99         TEGRA_DSI_DRIVEN_BY_DC,
100         TEGRA_DSI_DRIVEN_BY_HOST,
101 };
102
103 struct tegra_dc_dsi_data {
104         struct tegra_dc *dc;
105         void __iomem *base;
106         struct resource *base_res;
107
108         struct clk *dc_clk;
109         struct clk *dsi_clk;
110         bool clk_ref;
111
112         struct mutex lock;
113
114         /* data from board info */
115         struct tegra_dsi_out info;
116
117         struct dsi_status status;
118
119         u8 driven_mode;
120         u8 controller_index;
121
122         u8 pixel_scaler_mul;
123         u8 pixel_scaler_div;
124
125         u32 default_shift_clk_div;
126         u32 default_pixel_clk_khz;
127         u32 default_hs_clk_khz;
128
129         u32 shift_clk_div;
130         u32 target_hs_clk_khz;
131         u32 target_lp_clk_khz;
132
133         u32 syncpt_id;
134         u32 syncpt_val;
135
136         u16 current_bit_clk_ns;
137         u32 current_dsi_clk_khz;
138
139         u32 dsi_control_val;
140
141         bool ulpm;
142         bool enabled;
143 };
144
145 const u32 dsi_pkt_seq_reg[NUMOF_PKT_SEQ] = {
146         DSI_PKT_SEQ_0_LO,
147         DSI_PKT_SEQ_0_HI,
148         DSI_PKT_SEQ_1_LO,
149         DSI_PKT_SEQ_1_HI,
150         DSI_PKT_SEQ_2_LO,
151         DSI_PKT_SEQ_2_HI,
152         DSI_PKT_SEQ_3_LO,
153         DSI_PKT_SEQ_3_HI,
154         DSI_PKT_SEQ_4_LO,
155         DSI_PKT_SEQ_4_HI,
156         DSI_PKT_SEQ_5_LO,
157         DSI_PKT_SEQ_5_HI,
158 };
159
160 const u32 dsi_pkt_seq_video_non_burst_syne[NUMOF_PKT_SEQ] = {
161         PKT_ID0(CMD_VS) | PKT_LEN0(0) | PKT_ID1(CMD_EOT) | PKT_LEN1(0) | PKT_LP,
162         0,
163         PKT_ID0(CMD_VE) | PKT_LEN0(0) | PKT_ID1(CMD_EOT) | PKT_LEN1(0) | PKT_LP,
164         0,
165         PKT_ID0(CMD_HS) | PKT_LEN0(0) | PKT_ID1(CMD_EOT) | PKT_LEN1(0) | PKT_LP,
166         0,
167         PKT_ID0(CMD_HS) | PKT_LEN0(0) | PKT_ID1(CMD_BLNK) | PKT_LEN1(1) |
168         PKT_ID2(CMD_HE) | PKT_LEN2(0),
169         PKT_ID3(CMD_BLNK) | PKT_LEN3(2) | PKT_ID4(CMD_RGB) | PKT_LEN4(3) |
170         PKT_ID5(CMD_BLNK) | PKT_LEN5(4),
171         PKT_ID0(CMD_HS) | PKT_LEN0(0) | PKT_ID1(CMD_EOT) | PKT_LEN1(0) | PKT_LP,
172         0,
173         PKT_ID0(CMD_HS) | PKT_LEN0(0) | PKT_ID1(CMD_BLNK) | PKT_LEN1(1) |
174         PKT_ID2(CMD_HE) | PKT_LEN2(0),
175         PKT_ID3(CMD_BLNK) | PKT_LEN3(2) | PKT_ID4(CMD_RGB) | PKT_LEN4(3) |
176         PKT_ID5(CMD_BLNK) | PKT_LEN5(4),
177 };
178
179 const u32 dsi_pkt_seq_video_non_burst[NUMOF_PKT_SEQ] = {
180         PKT_ID0(CMD_VS) | PKT_LEN0(0) | PKT_ID1(CMD_EOT) | PKT_LEN1(0) | PKT_LP,
181         0,
182         PKT_ID0(CMD_HS) | PKT_LEN0(0) | PKT_ID1(CMD_EOT) | PKT_LEN1(0) | PKT_LP,
183         0,
184         PKT_ID0(CMD_HS) | PKT_LEN0(0) | PKT_ID1(CMD_EOT) | PKT_LEN1(0) | PKT_LP,
185         0,
186         PKT_ID0(CMD_HS) | PKT_LEN0(0) | PKT_ID1(CMD_BLNK) | PKT_LEN1(2) |
187         PKT_ID2(CMD_RGB) | PKT_LEN2(3),
188         PKT_ID3(CMD_BLNK) | PKT_LEN3(4),
189         PKT_ID0(CMD_HS) | PKT_LEN0(0) | PKT_ID1(CMD_EOT) | PKT_LEN1(0) | PKT_LP,
190         0,
191         PKT_ID0(CMD_HS) | PKT_LEN0(0) | PKT_ID1(CMD_BLNK) | PKT_LEN1(2) |
192         PKT_ID2(CMD_RGB) | PKT_LEN2(3),
193         PKT_ID3(CMD_BLNK) | PKT_LEN3(4),
194 };
195
196 static const u32 dsi_pkt_seq_video_burst[NUMOF_PKT_SEQ] = {
197         PKT_ID0(CMD_VS) | PKT_LEN0(0) | PKT_ID1(CMD_EOT) | PKT_LEN1(7) | PKT_LP,
198         0,
199         PKT_ID0(CMD_HS) | PKT_LEN0(0) | PKT_ID1(CMD_EOT) | PKT_LEN1(7) | PKT_LP,
200         0,
201         PKT_ID0(CMD_HS) | PKT_LEN0(0) | PKT_ID1(CMD_EOT) | PKT_LEN1(7) | PKT_LP,
202         0,
203         PKT_ID0(CMD_HS) | PKT_LEN0(0) | PKT_ID1(CMD_BLNK) | PKT_LEN1(2)|
204         PKT_ID2(CMD_RGB) | PKT_LEN2(3) | PKT_LP,
205         PKT_ID0(CMD_EOT) | PKT_LEN0(7),
206         PKT_ID0(CMD_HS) | PKT_LEN0(0) | PKT_ID1(CMD_EOT) | PKT_LEN1(7) | PKT_LP,
207         0,
208         PKT_ID0(CMD_HS) | PKT_LEN0(0) | PKT_ID1(CMD_BLNK) | PKT_LEN1(2)|
209         PKT_ID2(CMD_RGB) | PKT_LEN2(3) | PKT_LP,
210         PKT_ID0(CMD_EOT) | PKT_LEN0(7),
211 };
212
213 static const u32 dsi_pkt_seq_video_burst_no_eot[NUMOF_PKT_SEQ] = {
214         PKT_ID0(CMD_VS) | PKT_LEN0(0) | PKT_ID1(CMD_EOT) | PKT_LEN1(0) | PKT_LP,
215         0,
216         PKT_ID0(CMD_HS) | PKT_LEN0(0) | PKT_ID1(CMD_EOT) | PKT_LEN1(0) | PKT_LP,
217         0,
218         PKT_ID0(CMD_HS) | PKT_LEN0(0) | PKT_ID1(CMD_EOT) | PKT_LEN1(0) | PKT_LP,
219         0,
220         PKT_ID0(CMD_HS) | PKT_LEN0(0) | PKT_ID1(CMD_BLNK) | PKT_LEN1(2)|
221         PKT_ID2(CMD_RGB) | PKT_LEN2(3) | PKT_LP,
222         PKT_ID0(CMD_EOT) | PKT_LEN0(0),
223         PKT_ID0(CMD_HS) | PKT_LEN0(0) | PKT_ID1(CMD_EOT) | PKT_LEN1(0) | PKT_LP,
224         0,
225         PKT_ID0(CMD_HS) | PKT_LEN0(0) | PKT_ID1(CMD_BLNK) | PKT_LEN1(2)|
226         PKT_ID2(CMD_RGB) | PKT_LEN2(3) | PKT_LP,
227         PKT_ID0(CMD_EOT) | PKT_LEN0(0),
228 };
229
230 /* TODO: verify with hw about this format */
231 const u32 dsi_pkt_seq_cmd_mode[NUMOF_PKT_SEQ] = {
232         0,
233         0,
234         0,
235         0,
236         0,
237         0,
238         PKT_ID0(CMD_LONGW) | PKT_LEN0(3) | PKT_ID1(CMD_EOT) | PKT_LEN1(7),
239         0,
240         0,
241         0,
242         PKT_ID0(CMD_LONGW) | PKT_LEN0(3) | PKT_ID1(CMD_EOT) | PKT_LEN1(7),
243         0,
244 };
245
246 const u32 init_reg[] = {
247         DSI_INT_ENABLE,
248         DSI_INT_STATUS,
249         DSI_INT_MASK,
250         DSI_INIT_SEQ_DATA_0,
251         DSI_INIT_SEQ_DATA_1,
252         DSI_INIT_SEQ_DATA_2,
253         DSI_INIT_SEQ_DATA_3,
254         DSI_INIT_SEQ_DATA_4,
255         DSI_INIT_SEQ_DATA_5,
256         DSI_INIT_SEQ_DATA_6,
257         DSI_INIT_SEQ_DATA_7,
258         DSI_DCS_CMDS,
259         DSI_PKT_SEQ_0_LO,
260         DSI_PKT_SEQ_1_LO,
261         DSI_PKT_SEQ_2_LO,
262         DSI_PKT_SEQ_3_LO,
263         DSI_PKT_SEQ_4_LO,
264         DSI_PKT_SEQ_5_LO,
265         DSI_PKT_SEQ_0_HI,
266         DSI_PKT_SEQ_1_HI,
267         DSI_PKT_SEQ_2_HI,
268         DSI_PKT_SEQ_3_HI,
269         DSI_PKT_SEQ_4_HI,
270         DSI_PKT_SEQ_5_HI,
271         DSI_CONTROL,
272         DSI_HOST_DSI_CONTROL,
273         DSI_PAD_CONTROL,
274         DSI_PAD_CONTROL_CD,
275         DSI_SOL_DELAY,
276         DSI_MAX_THRESHOLD,
277         DSI_TRIGGER,
278         DSI_TX_CRC,
279         DSI_INIT_SEQ_CONTROL,
280         DSI_PKT_LEN_0_1,
281         DSI_PKT_LEN_2_3,
282         DSI_PKT_LEN_4_5,
283         DSI_PKT_LEN_6_7,
284 };
285
286 inline unsigned long tegra_dsi_readl(struct tegra_dc_dsi_data *dsi, u32 reg)
287 {
288         return readl(dsi->base + reg * 4);
289 }
290 EXPORT_SYMBOL(tegra_dsi_readl);
291
292 inline void tegra_dsi_writel(struct tegra_dc_dsi_data *dsi, u32 val, u32 reg)
293 {
294         writel(val, dsi->base + reg * 4);
295 }
296 EXPORT_SYMBOL(tegra_dsi_writel);
297
298 static int tegra_dsi_syncpt(struct tegra_dc_dsi_data *dsi)
299 {
300         u32 val;
301         int ret;
302
303         ret = 0;
304
305         dsi->syncpt_val = nvhost_syncpt_read(
306                         &nvhost_get_host(dsi->dc->ndev)->syncpt,
307                         dsi->syncpt_id);
308
309         val = DSI_INCR_SYNCPT_COND(OP_DONE) |
310                 DSI_INCR_SYNCPT_INDX(dsi->syncpt_id);
311         tegra_dsi_writel(dsi, val, DSI_INCR_SYNCPT);
312
313         /* TODO: Use interrupt rather than polling */
314         ret = nvhost_syncpt_wait(&nvhost_get_host(dsi->dc->ndev)->syncpt,
315                 dsi->syncpt_id, dsi->syncpt_val + 1);
316         if (ret < 0) {
317                 dev_err(&dsi->dc->ndev->dev, "DSI sync point failure\n");
318                 goto fail;
319         }
320
321         (dsi->syncpt_val)++;
322         return 0;
323 fail:
324         return ret;
325 }
326
327 static u32 tegra_dsi_get_hs_clk_rate(struct tegra_dc_dsi_data *dsi)
328 {
329         u32 dsi_clock_rate_khz;
330
331         switch (dsi->info.video_burst_mode) {
332         case TEGRA_DSI_VIDEO_BURST_MODE_LOW_SPEED:
333         case TEGRA_DSI_VIDEO_BURST_MODE_MEDIUM_SPEED:
334         case TEGRA_DSI_VIDEO_BURST_MODE_FAST_SPEED:
335         case TEGRA_DSI_VIDEO_BURST_MODE_FASTEST_SPEED:
336                 /* Calculate DSI HS clock rate for DSI burst mode */
337                 dsi_clock_rate_khz = dsi->default_pixel_clk_khz *
338                                                         dsi->shift_clk_div;
339                 break;
340         case TEGRA_DSI_VIDEO_NONE_BURST_MODE:
341         case TEGRA_DSI_VIDEO_NONE_BURST_MODE_WITH_SYNC_END:
342         case TEGRA_DSI_VIDEO_BURST_MODE_LOWEST_SPEED:
343         default:
344                 /* Clock rate is default DSI clock rate for non-burst mode */
345                 dsi_clock_rate_khz = dsi->default_hs_clk_khz;
346                 break;
347         }
348
349         return dsi_clock_rate_khz;
350 }
351
352 static u32 tegra_dsi_get_lp_clk_rate(struct tegra_dc_dsi_data *dsi, u8 lp_op)
353 {
354         u32 dsi_clock_rate_khz;
355
356         if (dsi->info.enable_hs_clock_on_lp_cmd_mode)
357                 if (dsi->info.hs_clk_in_lp_cmd_mode_freq_khz)
358                         dsi_clock_rate_khz =
359                                 dsi->info.hs_clk_in_lp_cmd_mode_freq_khz;
360                 else
361                         dsi_clock_rate_khz = tegra_dsi_get_hs_clk_rate(dsi);
362         else
363                 if (lp_op == DSI_LP_OP_READ)
364                         dsi_clock_rate_khz =
365                                 dsi->info.lp_read_cmd_mode_freq_khz;
366                 else
367                         dsi_clock_rate_khz =
368                                 dsi->info.lp_cmd_mode_freq_khz;
369
370         return dsi_clock_rate_khz;
371 }
372
373 static u32 tegra_dsi_get_shift_clk_div(struct tegra_dc_dsi_data *dsi)
374 {
375         u32 shift_clk_div;
376         u32 max_shift_clk_div;
377         u32 burst_width;
378         u32 burst_width_max;
379
380         /* Get the real value of default shift_clk_div. default_shift_clk_div
381          * holds the real value of shift_clk_div.
382          */
383         shift_clk_div = dsi->default_shift_clk_div;
384
385         /* Calculate shift_clk_div which can matche the video_burst_mode. */
386         if (dsi->info.video_burst_mode >=
387                         TEGRA_DSI_VIDEO_BURST_MODE_LOWEST_SPEED) {
388                 /* The max_shift_clk_div is multiplied by 10 to save the
389                  * fraction
390                  */
391                 if (dsi->info.max_panel_freq_khz >= dsi->default_hs_clk_khz)
392                         max_shift_clk_div = dsi->info.max_panel_freq_khz
393                                 * shift_clk_div * 10 / dsi->default_hs_clk_khz;
394                 else
395                         max_shift_clk_div = shift_clk_div * 10;
396
397                 burst_width = dsi->info.video_burst_mode
398                                 - TEGRA_DSI_VIDEO_BURST_MODE_LOWEST_SPEED;
399                 burst_width_max = TEGRA_DSI_VIDEO_BURST_MODE_FASTEST_SPEED
400                                 - TEGRA_DSI_VIDEO_BURST_MODE_LOWEST_SPEED;
401
402                 shift_clk_div = (max_shift_clk_div - shift_clk_div * 10) *
403                         burst_width / (burst_width_max * 10) + shift_clk_div;
404         }
405
406         return shift_clk_div;
407 }
408
409 static void tegra_dsi_init_sw(struct tegra_dc *dc,
410                         struct tegra_dc_dsi_data *dsi)
411 {
412         u32 h_width_pixels;
413         u32 v_width_lines;
414         u32 pixel_clk_hz;
415         u32 byte_clk_hz;
416         u32 plld_clk_mhz;
417
418         switch (dsi->info.pixel_format) {
419         case TEGRA_DSI_PIXEL_FORMAT_16BIT_P:
420                 /* 2 bytes per pixel */
421                 dsi->pixel_scaler_mul = 2;
422                 dsi->pixel_scaler_div = 1;
423                 break;
424         case TEGRA_DSI_PIXEL_FORMAT_18BIT_P:
425                 /* 2.25 bytes per pixel */
426                 dsi->pixel_scaler_mul = 9;
427                 dsi->pixel_scaler_div = 4;
428                 break;
429         case TEGRA_DSI_PIXEL_FORMAT_18BIT_NP:
430         case TEGRA_DSI_PIXEL_FORMAT_24BIT_P:
431                 /* 3 bytes per pixel */
432                 dsi->pixel_scaler_mul = 3;
433                 dsi->pixel_scaler_div = 1;
434                 break;
435         default:
436                 break;
437         }
438
439         dsi->controller_index = dc->ndev->id;
440         dsi->ulpm = false;
441         dsi->enabled = false;
442         dsi->clk_ref = false;
443
444         dsi->dsi_control_val =
445                         DSI_CONTROL_VIRTUAL_CHANNEL(dsi->info.virtual_channel) |
446                         DSI_CONTROL_NUM_DATA_LANES(dsi->info.n_data_lanes - 1) |
447                         DSI_CONTROL_VID_SOURCE(dsi->controller_index) |
448                         DSI_CONTROL_DATA_FORMAT(dsi->info.pixel_format);
449
450         /* Below we are going to calculate dsi and dc clock rate.
451          * Calcuate the horizontal and vertical width.
452          */
453         h_width_pixels = dc->mode.h_back_porch + dc->mode.h_front_porch +
454                         dc->mode.h_sync_width + dc->mode.h_active;
455         v_width_lines = dc->mode.v_back_porch + dc->mode.v_front_porch +
456                         dc->mode.v_sync_width + dc->mode.v_active;
457
458         /* Calculate minimum required pixel rate. */
459         pixel_clk_hz = h_width_pixels * v_width_lines * dsi->info.refresh_rate;
460
461         /* Calculate minimum byte rate on DSI interface. */
462         byte_clk_hz = (pixel_clk_hz * dsi->pixel_scaler_mul) /
463                         (dsi->pixel_scaler_div * dsi->info.n_data_lanes);
464
465         /* Round up to multiple of mega hz. */
466         plld_clk_mhz = DIV_ROUND_UP((byte_clk_hz * NUMOF_BIT_PER_BYTE),
467                                                                 1000000);
468
469         /* Calculate default real shift_clk_div. */
470         dsi->default_shift_clk_div = (NUMOF_BIT_PER_BYTE / 2) *
471                 dsi->pixel_scaler_mul / (dsi->pixel_scaler_div *
472                 dsi->info.n_data_lanes);
473         /* Calculate default DSI hs clock. DSI interface is double data rate.
474          * Data is transferred on both rising and falling edge of clk, div by 2
475          * to get the actual clock rate.
476          */
477         dsi->default_hs_clk_khz = plld_clk_mhz * 1000 / 2;
478         dsi->default_pixel_clk_khz = plld_clk_mhz * 1000 / 2
479                                                 / dsi->default_shift_clk_div;
480
481         /* Get the actual shift_clk_div and clock rates. */
482         dsi->shift_clk_div = tegra_dsi_get_shift_clk_div(dsi);
483         dsi->target_lp_clk_khz =
484                         tegra_dsi_get_lp_clk_rate(dsi, DSI_LP_OP_WRITE);
485         dsi->target_hs_clk_khz = tegra_dsi_get_hs_clk_rate(dsi);
486
487         dev_info(&dc->ndev->dev, "DSI: HS clock rate is %d\n",
488                                                         dsi->target_hs_clk_khz);
489
490         dsi->controller_index = dc->ndev->id;
491
492 #if DSI_USE_SYNC_POINTS
493         dsi->syncpt_id = NVSYNCPT_DSI;
494 #endif
495
496         /*
497          * Force video clock to be continuous mode if
498          * enable_hs_clock_on_lp_cmd_mode is set
499          */
500         if (dsi->info.enable_hs_clock_on_lp_cmd_mode) {
501                 if (dsi->info.video_clock_mode !=
502                                         TEGRA_DSI_VIDEO_CLOCK_CONTINUOUS)
503                         dev_warn(&dc->ndev->dev,
504                                 "Force clock continuous mode\n");
505
506                 dsi->info.video_clock_mode = TEGRA_DSI_VIDEO_CLOCK_CONTINUOUS;
507         }
508
509 }
510
511 static void tegra_dsi_get_phy_timing(struct tegra_dc_dsi_data *dsi,
512                                 struct dsi_phy_timing_inclk *phy_timing_clk,
513                                 u32 clk_ns)
514 {
515
516         phy_timing_clk->t_hsdexit = dsi->info.phy_timing.t_hsdexit_ns ?
517                         (dsi->info.phy_timing.t_hsdexit_ns / clk_ns) :
518                         (T_HSEXIT_DEFAULT(clk_ns));
519
520         phy_timing_clk->t_hstrail = dsi->info.phy_timing.t_hstrail_ns ?
521                         (dsi->info.phy_timing.t_hstrail_ns / clk_ns) :
522                         (T_HSTRAIL_DEFAULT(clk_ns));
523
524         phy_timing_clk->t_datzero = dsi->info.phy_timing.t_datzero_ns ?
525                         (dsi->info.phy_timing.t_datzero_ns / clk_ns) :
526                         (T_DATZERO_DEFAULT(clk_ns));
527
528         phy_timing_clk->t_hsprepr = dsi->info.phy_timing.t_hsprepr_ns ?
529                         (dsi->info.phy_timing.t_hsprepr_ns / clk_ns) :
530                         (T_HSPREPR_DEFAULT(clk_ns));
531
532         phy_timing_clk->t_clktrail = dsi->info.phy_timing.t_clktrail_ns ?
533                                 (dsi->info.phy_timing.t_clktrail_ns / clk_ns) :
534                                 (T_CLKTRAIL_DEFAULT(clk_ns));
535
536         phy_timing_clk->t_clkpost = dsi->info.phy_timing.t_clkpost_ns ?
537                                 (dsi->info.phy_timing.t_clkpost_ns / clk_ns) :
538                                 (T_CLKPOST_DEFAULT(clk_ns));
539
540         phy_timing_clk->t_clkzero = dsi->info.phy_timing.t_clkzero_ns ?
541                                 (dsi->info.phy_timing.t_clkzero_ns / clk_ns) :
542                                 (T_CLKZERO_DEFAULT(clk_ns));
543
544         phy_timing_clk->t_tlpx = dsi->info.phy_timing.t_tlpx_ns ?
545                                 (dsi->info.phy_timing.t_tlpx_ns / clk_ns) :
546                                 (T_TLPX_DEFAULT(clk_ns));
547
548         phy_timing_clk->t_clkpre = T_CLKPRE_DEFAULT(clk_ns);
549         phy_timing_clk->t_clkprepare = T_CLKPREPARE_DEFAULT(clk_ns);
550         phy_timing_clk->t_wakeup = T_WAKEUP_DEFAULT(clk_ns);
551
552         phy_timing_clk->t_taget = 5 * phy_timing_clk->t_tlpx;
553         phy_timing_clk->t_tasure = 2 * phy_timing_clk->t_tlpx;
554         phy_timing_clk->t_tago = 4 * phy_timing_clk->t_tlpx;
555 }
556
557 static void tegra_dsi_set_phy_timing(struct tegra_dc_dsi_data *dsi)
558 {
559         u32 val;
560         struct dsi_phy_timing_inclk phy_timing;
561
562         tegra_dsi_get_phy_timing(dsi, &phy_timing, dsi->current_bit_clk_ns);
563
564         val = DSI_PHY_TIMING_0_THSDEXIT(phy_timing.t_hsdexit) |
565                         DSI_PHY_TIMING_0_THSTRAIL(phy_timing.t_hstrail) |
566                         DSI_PHY_TIMING_0_TDATZERO(phy_timing.t_datzero) |
567                         DSI_PHY_TIMING_0_THSPREPR(phy_timing.t_hsprepr);
568         tegra_dsi_writel(dsi, val, DSI_PHY_TIMING_0);
569
570         val = DSI_PHY_TIMING_1_TCLKTRAIL(phy_timing.t_clktrail) |
571                         DSI_PHY_TIMING_1_TCLKPOST(phy_timing.t_clkpost) |
572                         DSI_PHY_TIMING_1_TCLKZERO(phy_timing.t_clkzero) |
573                         DSI_PHY_TIMING_1_TTLPX(phy_timing.t_tlpx);
574         tegra_dsi_writel(dsi, val, DSI_PHY_TIMING_1);
575
576         val = DSI_PHY_TIMING_2_TCLKPREPARE(phy_timing.t_clkprepare) |
577                 DSI_PHY_TIMING_2_TCLKPRE(phy_timing.t_clkpre) |
578                         DSI_PHY_TIMING_2_TWAKEUP(phy_timing.t_wakeup);
579         tegra_dsi_writel(dsi, val, DSI_PHY_TIMING_2);
580
581         val = DSI_BTA_TIMING_TTAGET(phy_timing.t_taget) |
582                         DSI_BTA_TIMING_TTASURE(phy_timing.t_tasure) |
583                         DSI_BTA_TIMING_TTAGO(phy_timing.t_tago);
584         tegra_dsi_writel(dsi, val, DSI_BTA_TIMING);
585 }
586
587 static u32 tegra_dsi_sol_delay_burst(struct tegra_dc *dc,
588                                 struct tegra_dc_dsi_data *dsi)
589 {
590         u32 dsi_to_pixel_clk_ratio;
591         u32 temp;
592         u32 temp1;
593         u32 mipi_clk_adj_kHz;
594         u32 sol_delay;
595         struct tegra_dc_mode *dc_modes = &dc->mode;
596
597         /* Get Fdsi/Fpixel ration (note: Fdsi is in bit format) */
598         dsi_to_pixel_clk_ratio = (dsi->current_dsi_clk_khz * 2 +
599                 dsi->default_pixel_clk_khz - 1) / dsi->default_pixel_clk_khz;
600
601         /* Convert Fdsi to byte format */
602         dsi_to_pixel_clk_ratio *= 1000/8;
603
604         /* Multiplying by 1000 so that we don't loose the fraction part */
605         temp = dc_modes->h_active * 1000;
606         temp1 = dc_modes->h_active + dc_modes->h_back_porch +
607                         dc_modes->h_sync_width;
608
609         sol_delay = temp1 * dsi_to_pixel_clk_ratio -
610                         temp * dsi->pixel_scaler_mul /
611                         (dsi->pixel_scaler_div * dsi->info.n_data_lanes);
612
613         /* Do rounding on sol delay */
614         sol_delay = (sol_delay + 1000 - 1)/1000;
615
616         /* TODO:
617          * 1. find out the correct sol fifo depth to use
618          * 2. verify with hw about the clamping function
619          */
620         if (sol_delay > (480 * 4)) {
621                 sol_delay = (480 * 4);
622                 mipi_clk_adj_kHz = sol_delay +
623                         (dc_modes->h_active * dsi->pixel_scaler_mul) /
624                         (dsi->info.n_data_lanes * dsi->pixel_scaler_div);
625
626                 mipi_clk_adj_kHz *= (dsi->default_pixel_clk_khz / temp1);
627
628                 mipi_clk_adj_kHz *= 4;
629         }
630
631         dsi->target_hs_clk_khz = mipi_clk_adj_kHz;
632
633         return sol_delay;
634 }
635
636 static void tegra_dsi_set_sol_delay(struct tegra_dc *dc,
637                                 struct tegra_dc_dsi_data *dsi)
638 {
639         u32 sol_delay;
640
641         if (dsi->info.video_burst_mode == TEGRA_DSI_VIDEO_NONE_BURST_MODE ||
642                 dsi->info.video_burst_mode ==
643                                 TEGRA_DSI_VIDEO_NONE_BURST_MODE_WITH_SYNC_END) {
644                 sol_delay = NUMOF_BIT_PER_BYTE * dsi->pixel_scaler_mul /
645                         (dsi->pixel_scaler_div * dsi->info.n_data_lanes);
646                 dsi->status.clk_burst = DSI_CLK_BURST_NONE_BURST;
647         } else {
648                 sol_delay = tegra_dsi_sol_delay_burst(dc, dsi);
649                 dsi->status.clk_burst = DSI_CLK_BURST_BURST_MODE;
650         }
651
652         tegra_dsi_writel(dsi, DSI_SOL_DELAY_SOL_DELAY(sol_delay),
653                                                                 DSI_SOL_DELAY);
654 }
655
656 static void tegra_dsi_set_timeout(struct tegra_dc_dsi_data *dsi)
657 {
658         u32 val;
659         u32 bytes_per_frame;
660         u32 timeout = 0;
661
662         /* TODO: verify the following equation */
663         bytes_per_frame = dsi->current_dsi_clk_khz * 1000 * 2 /
664                                                 (dsi->info.refresh_rate * 8);
665         timeout = bytes_per_frame / DSI_CYCLE_COUNTER_VALUE;
666         timeout = (timeout + DSI_HTX_TO_MARGIN) & 0xffff;
667
668         val = DSI_TIMEOUT_0_LRXH_TO(DSI_LRXH_TO_VALUE) |
669                         DSI_TIMEOUT_0_HTX_TO(timeout);
670         tegra_dsi_writel(dsi, val, DSI_TIMEOUT_0);
671
672         if (dsi->info.panel_reset_timeout_msec)
673                 timeout = (dsi->info.panel_reset_timeout_msec * 1000*1000)
674                                         / dsi->current_bit_clk_ns;
675         else
676                 timeout = DSI_PR_TO_VALUE;
677
678         val = DSI_TIMEOUT_1_PR_TO(timeout) |
679                 DSI_TIMEOUT_1_TA_TO(DSI_TA_TO_VALUE);
680         tegra_dsi_writel(dsi, val, DSI_TIMEOUT_1);
681
682         val = DSI_TO_TALLY_P_RESET_STATUS(IN_RESET) |
683                 DSI_TO_TALLY_TA_TALLY(DSI_TA_TALLY_VALUE)|
684                 DSI_TO_TALLY_LRXH_TALLY(DSI_LRXH_TALLY_VALUE)|
685                 DSI_TO_TALLY_HTX_TALLY(DSI_HTX_TALLY_VALUE);
686         tegra_dsi_writel(dsi, val, DSI_TO_TALLY);
687 }
688
689 static void tegra_dsi_setup_video_mode_pkt_length(struct tegra_dc *dc,
690                                                 struct tegra_dc_dsi_data *dsi)
691 {
692         u32 val;
693         u32 hact_pkt_len;
694         u32 hsa_pkt_len;
695         u32 hbp_pkt_len;
696         u32 hfp_pkt_len;
697
698         hact_pkt_len = dc->mode.h_active * dsi->pixel_scaler_mul /
699                                                         dsi->pixel_scaler_div;
700         hsa_pkt_len = dc->mode.h_sync_width * dsi->pixel_scaler_mul /
701                                                         dsi->pixel_scaler_div;
702         hbp_pkt_len = dc->mode.h_back_porch * dsi->pixel_scaler_mul /
703                                                         dsi->pixel_scaler_div;
704         hfp_pkt_len = dc->mode.h_front_porch * dsi->pixel_scaler_mul /
705                                                         dsi->pixel_scaler_div;
706
707         if (dsi->info.video_burst_mode !=
708                                 TEGRA_DSI_VIDEO_NONE_BURST_MODE_WITH_SYNC_END)
709                 hbp_pkt_len += hsa_pkt_len;
710
711         hsa_pkt_len -= DSI_HSYNC_BLNK_PKT_OVERHEAD;
712         hbp_pkt_len -= DSI_HBACK_PORCH_PKT_OVERHEAD;
713         hfp_pkt_len -= DSI_HFRONT_PORCH_PKT_OVERHEAD;
714
715         val = DSI_PKT_LEN_0_1_LENGTH_0(0) |
716                         DSI_PKT_LEN_0_1_LENGTH_1(hsa_pkt_len);
717         tegra_dsi_writel(dsi, val, DSI_PKT_LEN_0_1);
718
719         val = DSI_PKT_LEN_2_3_LENGTH_2(hbp_pkt_len) |
720                         DSI_PKT_LEN_2_3_LENGTH_3(hact_pkt_len);
721         tegra_dsi_writel(dsi, val, DSI_PKT_LEN_2_3);
722
723         val = DSI_PKT_LEN_4_5_LENGTH_4(hfp_pkt_len) |
724                         DSI_PKT_LEN_4_5_LENGTH_5(0);
725         tegra_dsi_writel(dsi, val, DSI_PKT_LEN_4_5);
726
727         val = DSI_PKT_LEN_6_7_LENGTH_6(0) | DSI_PKT_LEN_6_7_LENGTH_7(0);
728         tegra_dsi_writel(dsi, val, DSI_PKT_LEN_6_7);
729 }
730
731 static void tegra_dsi_setup_cmd_mode_pkt_length(struct tegra_dc *dc,
732                                                 struct tegra_dc_dsi_data *dsi)
733 {
734         unsigned long   val;
735         unsigned long   act_bytes;
736
737         act_bytes = dc->mode.h_active * dsi->pixel_scaler_mul /
738                         dsi->pixel_scaler_div + 1;
739
740         val = DSI_PKT_LEN_0_1_LENGTH_0(0) | DSI_PKT_LEN_0_1_LENGTH_1(0);
741         tegra_dsi_writel(dsi, val, DSI_PKT_LEN_0_1);
742
743         val = DSI_PKT_LEN_2_3_LENGTH_2(0) | DSI_PKT_LEN_2_3_LENGTH_3(act_bytes);
744         tegra_dsi_writel(dsi, val, DSI_PKT_LEN_2_3);
745
746         val = DSI_PKT_LEN_4_5_LENGTH_4(0) | DSI_PKT_LEN_4_5_LENGTH_5(act_bytes);
747         tegra_dsi_writel(dsi, val, DSI_PKT_LEN_4_5);
748
749         val = DSI_PKT_LEN_6_7_LENGTH_6(0) | DSI_PKT_LEN_6_7_LENGTH_7(0x0f0f);
750         tegra_dsi_writel(dsi, val, DSI_PKT_LEN_6_7);
751 }
752
753 static void tegra_dsi_set_pkt_length(struct tegra_dc *dc,
754                                 struct tegra_dc_dsi_data *dsi)
755 {
756         if (dsi->driven_mode == TEGRA_DSI_DRIVEN_BY_HOST)
757                 return;
758
759         if (dsi->info.video_data_type == TEGRA_DSI_VIDEO_TYPE_VIDEO_MODE)
760                 tegra_dsi_setup_video_mode_pkt_length(dc, dsi);
761         else
762                 tegra_dsi_setup_cmd_mode_pkt_length(dc, dsi);
763 }
764
765 static void tegra_dsi_set_pkt_seq(struct tegra_dc *dc,
766                                 struct tegra_dc_dsi_data *dsi)
767 {
768         const u32 *pkt_seq;
769         u32 rgb_info;
770         u32 pkt_seq_3_5_rgb_lo;
771         u32 pkt_seq_3_5_rgb_hi;
772         u32     val;
773         u32 reg;
774         u8  i;
775
776         if (dsi->driven_mode == TEGRA_DSI_DRIVEN_BY_HOST)
777                 return;
778
779         switch (dsi->info.pixel_format) {
780         case TEGRA_DSI_PIXEL_FORMAT_16BIT_P:
781                 rgb_info = CMD_RGB_16BPP;
782                 break;
783         case TEGRA_DSI_PIXEL_FORMAT_18BIT_P:
784                 rgb_info = CMD_RGB_18BPP;
785                 break;
786         case TEGRA_DSI_PIXEL_FORMAT_18BIT_NP:
787                 rgb_info = CMD_RGB_18BPPNP;
788                 break;
789         case TEGRA_DSI_PIXEL_FORMAT_24BIT_P:
790         default:
791                 rgb_info = CMD_RGB_24BPP;
792                 break;
793         }
794
795         pkt_seq_3_5_rgb_lo = 0;
796         pkt_seq_3_5_rgb_hi = 0;
797         if (dsi->info.video_data_type == TEGRA_DSI_VIDEO_TYPE_COMMAND_MODE)
798                 pkt_seq = dsi_pkt_seq_cmd_mode;
799         else {
800                 switch (dsi->info.video_burst_mode) {
801                 case TEGRA_DSI_VIDEO_BURST_MODE_LOWEST_SPEED:
802                 case TEGRA_DSI_VIDEO_BURST_MODE_LOW_SPEED:
803                 case TEGRA_DSI_VIDEO_BURST_MODE_MEDIUM_SPEED:
804                 case TEGRA_DSI_VIDEO_BURST_MODE_FAST_SPEED:
805                 case TEGRA_DSI_VIDEO_BURST_MODE_FASTEST_SPEED:
806                         pkt_seq_3_5_rgb_lo =
807                                         DSI_PKT_SEQ_3_LO_PKT_32_ID(rgb_info);
808                         if (!dsi->info.no_pkt_seq_eot)
809                                 pkt_seq = dsi_pkt_seq_video_burst;
810                         else
811                                 pkt_seq = dsi_pkt_seq_video_burst_no_eot;
812                         break;
813                 case TEGRA_DSI_VIDEO_NONE_BURST_MODE_WITH_SYNC_END:
814                         pkt_seq_3_5_rgb_hi =
815                                         DSI_PKT_SEQ_3_HI_PKT_34_ID(rgb_info);
816                         pkt_seq = dsi_pkt_seq_video_non_burst_syne;
817                         break;
818                 case TEGRA_DSI_VIDEO_NONE_BURST_MODE:
819                 default:
820                         pkt_seq_3_5_rgb_lo =
821                                         DSI_PKT_SEQ_3_LO_PKT_32_ID(rgb_info);
822                         pkt_seq = dsi_pkt_seq_video_non_burst;
823                         break;
824                 }
825         }
826
827         for (i = 0; i < NUMOF_PKT_SEQ; i++) {
828                 val = pkt_seq[i];
829                 reg = dsi_pkt_seq_reg[i];
830                 if ((reg == DSI_PKT_SEQ_3_LO) || (reg == DSI_PKT_SEQ_5_LO))
831                         val |= pkt_seq_3_5_rgb_lo;
832                 if ((reg == DSI_PKT_SEQ_3_HI) || (reg == DSI_PKT_SEQ_5_HI))
833                         val |= pkt_seq_3_5_rgb_hi;
834                 tegra_dsi_writel(dsi, val, reg);
835         }
836 }
837
838 static void tegra_dsi_stop_dc_stream(struct tegra_dc *dc,
839                                         struct tegra_dc_dsi_data *dsi)
840 {
841         tegra_dc_writel(dc, DISP_CTRL_MODE_STOP, DC_CMD_DISPLAY_COMMAND);
842         tegra_dc_writel(dc, 0, DC_DISP_DISP_WIN_OPTIONS);
843         tegra_dc_writel(dc, GENERAL_UPDATE, DC_CMD_STATE_CONTROL);
844         tegra_dc_writel(dc, GENERAL_ACT_REQ , DC_CMD_STATE_CONTROL);
845
846         dsi->status.dc_stream = DSI_DC_STREAM_DISABLE;
847 }
848
849 static void tegra_dsi_stop_dc_stream_at_frame_end(struct tegra_dc *dc,
850                                                 struct tegra_dc_dsi_data *dsi)
851 {
852         int val;
853         long timeout;
854         u32 frame_period = DIV_ROUND_UP(S_TO_MS(1), dsi->info.refresh_rate);
855
856         /* stop dc */
857         tegra_dsi_stop_dc_stream(dc, dsi);
858
859         /* enable frame end interrupt */
860         val = tegra_dc_readl(dc, DC_CMD_INT_MASK);
861         val |= FRAME_END_INT;
862         tegra_dc_writel(dc, val, DC_CMD_INT_MASK);
863
864         /* wait for frame_end completion.
865          * timeout is 2 frame duration to accomodate for
866          * internal delay.
867          */
868         timeout = wait_for_completion_interruptible_timeout(
869                         &dc->frame_end_complete,
870                         msecs_to_jiffies(2 * frame_period));
871
872         /* disable frame end interrupt */
873         val = tegra_dc_readl(dc, DC_CMD_INT_MASK);
874         val &= ~FRAME_END_INT;
875         tegra_dc_writel(dc, val, DC_CMD_INT_MASK);
876
877         if (timeout == 0)
878                 dev_warn(&dc->ndev->dev,
879                         "DC doesn't stop at end of frame.\n");
880 }
881
882 static void tegra_dsi_start_dc_stream(struct tegra_dc *dc,
883                                         struct tegra_dc_dsi_data *dsi)
884 {
885         u32 val;
886
887         tegra_dc_writel(dc, DSI_ENABLE, DC_DISP_DISP_WIN_OPTIONS);
888
889         /* TODO: clean up */
890         tegra_dc_writel(dc, PW0_ENABLE | PW1_ENABLE | PW2_ENABLE | PW3_ENABLE |
891                         PW4_ENABLE | PM0_ENABLE | PM1_ENABLE,
892                         DC_CMD_DISPLAY_POWER_CONTROL);
893
894         /* Configure one-shot mode or continuous mode */
895         if (dc->out->flags & TEGRA_DC_OUT_ONE_SHOT_MODE) {
896                 /* disable LSPI/LCD_DE output */
897                 val = PIN_OUTPUT_LSPI_OUTPUT_DIS;
898                 tegra_dc_writel(dc, val, DC_COM_PIN_OUTPUT_ENABLE3);
899
900                 /* enable MSF & set MSF polarity */
901                 val = MSF_ENABLE | MSF_LSPI;
902                 if (!dsi->info.te_polarity_low)
903                         val |= MSF_POLARITY_HIGH;
904                 else
905                         val |= MSF_POLARITY_LOW;
906                 tegra_dc_writel(dc, val, DC_CMD_DISPLAY_COMMAND_OPTION0);
907
908                 /* set non-continuous mode */
909                 tegra_dc_writel(dc, DISP_CTRL_MODE_NC_DISPLAY,
910                                                 DC_CMD_DISPLAY_COMMAND);
911                 tegra_dc_writel(dc, GENERAL_UPDATE, DC_CMD_STATE_CONTROL);
912                 tegra_dc_writel(dc, GENERAL_ACT_REQ | NC_HOST_TRIG,
913                                                 DC_CMD_STATE_CONTROL);
914         } else {
915                 /* set continuous mode */
916                 tegra_dc_writel(dc, DISP_CTRL_MODE_C_DISPLAY,
917                                                 DC_CMD_DISPLAY_COMMAND);
918                 tegra_dc_writel(dc, GENERAL_UPDATE, DC_CMD_STATE_CONTROL);
919                 tegra_dc_writel(dc, GENERAL_ACT_REQ, DC_CMD_STATE_CONTROL);
920         }
921
922         dsi->status.dc_stream = DSI_DC_STREAM_ENABLE;
923 }
924
925 static void tegra_dsi_set_dc_clk(struct tegra_dc *dc,
926                                 struct tegra_dc_dsi_data *dsi)
927 {
928         u32 shift_clk_div_register;
929         u32 val;
930
931         /* Get the corresponding register value of shift_clk_div. */
932         shift_clk_div_register = dsi->shift_clk_div * 2 - 2;
933
934 #ifdef CONFIG_TEGRA_FPGA_PLATFORM
935         shift_clk_div_register = 1;
936 #endif
937
938         /* TODO: find out if PCD3 option is required */
939         val = PIXEL_CLK_DIVIDER_PCD1 |
940                 SHIFT_CLK_DIVIDER(shift_clk_div_register);
941         tegra_dc_writel(dc, val, DC_DISP_DISP_CLOCK_CONTROL);
942 }
943
944 static void tegra_dsi_set_dsi_clk(struct tegra_dc *dc,
945                         struct tegra_dc_dsi_data *dsi, u32 clk)
946 {
947         u32 rm;
948
949         /* Round up to MHz */
950         rm = clk % 1000;
951         if (rm != 0)
952                 clk -= rm;
953
954         /* Set up pixel clock */
955         dc->shift_clk_div = dsi->shift_clk_div;
956         dc->mode.pclk = (clk * 1000) / dsi->shift_clk_div;
957         /* TODO: Define one shot work delay in board file. */
958         /* Since for one-shot mode, refresh rate is usually set larger than
959          * expected refresh rate, it needs at least 3 frame period. Less
960          * delay one shot work is, more powering saving we have. */
961         dc->one_shot_delay_ms = 4 *
962                         DIV_ROUND_UP(S_TO_MS(1), dsi->info.refresh_rate);
963
964         /* Enable DSI clock */
965         tegra_dc_setup_clk(dc, dsi->dsi_clk);
966         if (!dsi->clk_ref) {
967                 dsi->clk_ref = true;
968                 clk_enable(dsi->dsi_clk);
969                 tegra_periph_reset_deassert(dsi->dsi_clk);
970         }
971         dsi->current_dsi_clk_khz = clk_get_rate(dsi->dsi_clk) / 1000;
972         dsi->current_bit_clk_ns =  1000*1000 / (dsi->current_dsi_clk_khz * 2);
973 }
974
975 static void tegra_dsi_hs_clk_out_enable(struct tegra_dc_dsi_data *dsi)
976 {
977         u32 val;
978
979         val = tegra_dsi_readl(dsi, DSI_CONTROL);
980         val &= ~DSI_CONTROL_HS_CLK_CTRL(1);
981
982         if (dsi->info.video_clock_mode == TEGRA_DSI_VIDEO_CLOCK_CONTINUOUS) {
983                 val |= DSI_CONTROL_HS_CLK_CTRL(CONTINUOUS);
984                 dsi->status.clk_mode = DSI_PHYCLK_CONTINUOUS;
985         } else {
986                 val |= DSI_CONTROL_HS_CLK_CTRL(TX_ONLY);
987                 dsi->status.clk_mode = DSI_PHYCLK_TX_ONLY;
988         }
989         tegra_dsi_writel(dsi, val, DSI_CONTROL);
990
991         val = tegra_dsi_readl(dsi, DSI_HOST_DSI_CONTROL);
992         val &= ~DSI_HOST_DSI_CONTROL_HIGH_SPEED_TRANS(1);
993         val |= DSI_HOST_DSI_CONTROL_HIGH_SPEED_TRANS(TEGRA_DSI_HIGH);
994         tegra_dsi_writel(dsi, val, DSI_HOST_DSI_CONTROL);
995
996         dsi->status.clk_out = DSI_PHYCLK_OUT_EN;
997 }
998
999 static void tegra_dsi_hs_clk_out_enable_in_lp(struct tegra_dc_dsi_data *dsi)
1000 {
1001         u32 val;
1002         tegra_dsi_hs_clk_out_enable(dsi);
1003
1004         val = tegra_dsi_readl(dsi, DSI_HOST_DSI_CONTROL);
1005         val &= ~DSI_HOST_DSI_CONTROL_HIGH_SPEED_TRANS(1);
1006         val |= DSI_HOST_DSI_CONTROL_HIGH_SPEED_TRANS(TEGRA_DSI_LOW);
1007         tegra_dsi_writel(dsi, val, DSI_HOST_DSI_CONTROL);
1008 }
1009
1010 static void tegra_dsi_hs_clk_out_disable(struct tegra_dc *dc,
1011                                                 struct tegra_dc_dsi_data *dsi)
1012 {
1013         u32 val;
1014
1015         if (dsi->status.dc_stream == DSI_DC_STREAM_ENABLE)
1016                 tegra_dsi_stop_dc_stream_at_frame_end(dc, dsi);
1017
1018         tegra_dsi_writel(dsi, TEGRA_DSI_DISABLE, DSI_POWER_CONTROL);
1019         /* stabilization delay */
1020         udelay(300);
1021
1022         val = tegra_dsi_readl(dsi, DSI_HOST_DSI_CONTROL);
1023         val &= ~DSI_HOST_DSI_CONTROL_HIGH_SPEED_TRANS(1);
1024         val |= DSI_HOST_DSI_CONTROL_HIGH_SPEED_TRANS(TEGRA_DSI_LOW);
1025         tegra_dsi_writel(dsi, val, DSI_HOST_DSI_CONTROL);
1026
1027         tegra_dsi_writel(dsi, TEGRA_DSI_ENABLE, DSI_POWER_CONTROL);
1028         /* stabilization delay */
1029         udelay(300);
1030
1031         dsi->status.clk_mode = DSI_PHYCLK_NOT_INIT;
1032         dsi->status.clk_out = DSI_PHYCLK_OUT_DIS;
1033 }
1034
1035 static void tegra_dsi_set_control_reg_lp(struct tegra_dc_dsi_data *dsi)
1036 {
1037         u32 dsi_control;
1038         u32 host_dsi_control;
1039         u32 max_threshold;
1040
1041         dsi_control = dsi->dsi_control_val | DSI_CTRL_HOST_DRIVEN;
1042         host_dsi_control = HOST_DSI_CTRL_COMMON |
1043                         HOST_DSI_CTRL_HOST_DRIVEN |
1044                         DSI_HOST_DSI_CONTROL_HIGH_SPEED_TRANS(TEGRA_DSI_LOW);
1045         max_threshold = DSI_MAX_THRESHOLD_MAX_THRESHOLD(DSI_HOST_FIFO_DEPTH);
1046
1047         tegra_dsi_writel(dsi, max_threshold, DSI_MAX_THRESHOLD);
1048         tegra_dsi_writel(dsi, dsi_control, DSI_CONTROL);
1049         tegra_dsi_writel(dsi, host_dsi_control, DSI_HOST_DSI_CONTROL);
1050
1051         dsi->status.driven = DSI_DRIVEN_MODE_HOST;
1052         dsi->status.clk_burst = DSI_CLK_BURST_NOT_INIT;
1053         dsi->status.vtype = DSI_VIDEO_TYPE_NOT_INIT;
1054 }
1055
1056 static void tegra_dsi_set_control_reg_hs(struct tegra_dc_dsi_data *dsi)
1057 {
1058         u32 dsi_control;
1059         u32 host_dsi_control;
1060         u32 max_threshold;
1061         u32 dcs_cmd;
1062
1063         dsi_control = dsi->dsi_control_val;
1064         host_dsi_control = HOST_DSI_CTRL_COMMON;
1065         max_threshold = 0;
1066         dcs_cmd = 0;
1067
1068         if (dsi->driven_mode == TEGRA_DSI_DRIVEN_BY_HOST) {
1069                 dsi_control |= DSI_CTRL_HOST_DRIVEN;
1070                 host_dsi_control |= HOST_DSI_CTRL_HOST_DRIVEN;
1071                 max_threshold =
1072                         DSI_MAX_THRESHOLD_MAX_THRESHOLD(DSI_HOST_FIFO_DEPTH);
1073                 dsi->status.driven = DSI_DRIVEN_MODE_HOST;
1074         } else {
1075                 dsi_control |= DSI_CTRL_DC_DRIVEN;
1076                 host_dsi_control |= HOST_DSI_CTRL_DC_DRIVEN;
1077                 max_threshold =
1078                         DSI_MAX_THRESHOLD_MAX_THRESHOLD(DSI_VIDEO_FIFO_DEPTH);
1079                 dsi->status.driven = DSI_DRIVEN_MODE_DC;
1080         }
1081
1082         if (dsi->info.video_data_type == TEGRA_DSI_VIDEO_TYPE_COMMAND_MODE) {
1083                 dsi_control |= DSI_CTRL_CMD_MODE;
1084                 dcs_cmd = DSI_DCS_CMDS_LT5_DCS_CMD(DSI_WRITE_MEMORY_START)|
1085                         DSI_DCS_CMDS_LT3_DCS_CMD(DSI_WRITE_MEMORY_CONTINUE);
1086                 dsi->status.vtype = DSI_VIDEO_TYPE_CMD_MODE;
1087
1088         } else {
1089                 dsi_control |= DSI_CTRL_VIDEO_MODE;
1090                 dsi->status.vtype = DSI_VIDEO_TYPE_VIDEO_MODE;
1091         }
1092
1093         tegra_dsi_writel(dsi, max_threshold, DSI_MAX_THRESHOLD);
1094         tegra_dsi_writel(dsi, dcs_cmd, DSI_DCS_CMDS);
1095         tegra_dsi_writel(dsi, dsi_control, DSI_CONTROL);
1096         tegra_dsi_writel(dsi, host_dsi_control, DSI_HOST_DSI_CONTROL);
1097 }
1098
1099 static void tegra_dsi_pad_calibration(struct tegra_dc_dsi_data *dsi)
1100 {
1101         u32 val;
1102
1103         val =   DSI_PAD_CONTROL_PAD_LPUPADJ(0x1) |
1104                 DSI_PAD_CONTROL_PAD_LPDNADJ(0x1) |
1105                 DSI_PAD_CONTROL_PAD_PREEMP_EN(0x1) |
1106                 DSI_PAD_CONTROL_PAD_SLEWDNADJ(0x6) |
1107                 DSI_PAD_CONTROL_PAD_SLEWUPADJ(0x6);
1108         if (!dsi->ulpm) {
1109                 val |=  DSI_PAD_CONTROL_PAD_PDIO(0) |
1110                         DSI_PAD_CONTROL_PAD_PDIO_CLK(0) |
1111                         DSI_PAD_CONTROL_PAD_PULLDN_ENAB(TEGRA_DSI_DISABLE);
1112         } else {
1113                 val |=  DSI_PAD_CONTROL_PAD_PDIO(0x3) |
1114                         DSI_PAD_CONTROL_PAD_PDIO_CLK(0x1) |
1115                         DSI_PAD_CONTROL_PAD_PULLDN_ENAB(TEGRA_DSI_ENABLE);
1116         }
1117         tegra_dsi_writel(dsi, val, DSI_PAD_CONTROL);
1118
1119         val = MIPI_CAL_TERMOSA(0x4);
1120         tegra_vi_csi_writel(val, CSI_CILA_MIPI_CAL_CONFIG_0);
1121
1122         val = MIPI_CAL_TERMOSB(0x4);
1123         tegra_vi_csi_writel(val, CSI_CILB_MIPI_CAL_CONFIG_0);
1124
1125         val = MIPI_CAL_HSPUOSD(0x3) | MIPI_CAL_HSPDOSD(0x4);
1126         tegra_vi_csi_writel(val, CSI_DSI_MIPI_CAL_CONFIG);
1127
1128         val = PAD_DRIV_DN_REF(0x5) | PAD_DRIV_UP_REF(0x7);
1129         tegra_vi_csi_writel(val, CSI_MIPIBIAS_PAD_CONFIG);
1130 }
1131
1132 static int tegra_dsi_init_hw(struct tegra_dc *dc,
1133                                                 struct tegra_dc_dsi_data *dsi)
1134 {
1135         u32 i;
1136
1137         tegra_dsi_writel(dsi,
1138                 DSI_POWER_CONTROL_LEG_DSI_ENABLE(TEGRA_DSI_DISABLE),
1139                 DSI_POWER_CONTROL);
1140         /* stabilization delay */
1141         udelay(300);
1142
1143         tegra_dsi_set_dsi_clk(dc, dsi, dsi->target_lp_clk_khz);
1144         if (dsi->info.dsi_instance) {
1145                 /* TODO:Set the misc register*/
1146         }
1147
1148         /* TODO: only need to change the timing for bta */
1149         tegra_dsi_set_phy_timing(dsi);
1150
1151         if (dsi->status.dc_stream == DSI_DC_STREAM_ENABLE)
1152                 tegra_dsi_stop_dc_stream_at_frame_end(dc, dsi);
1153
1154         /* Initializing DSI registers */
1155         for (i = 0; i < ARRAY_SIZE(init_reg); i++)
1156                 tegra_dsi_writel(dsi, 0, init_reg[i]);
1157
1158         tegra_dsi_writel(dsi, dsi->dsi_control_val, DSI_CONTROL);
1159
1160         tegra_dsi_pad_calibration(dsi);
1161
1162         tegra_dsi_writel(dsi,
1163                 DSI_POWER_CONTROL_LEG_DSI_ENABLE(TEGRA_DSI_ENABLE),
1164                 DSI_POWER_CONTROL);
1165         /* stabilization delay */
1166         udelay(300);
1167
1168         dsi->status.init = DSI_MODULE_INIT;
1169         dsi->status.lphs = DSI_LPHS_NOT_INIT;
1170         dsi->status.vtype = DSI_VIDEO_TYPE_NOT_INIT;
1171         dsi->status.driven = DSI_DRIVEN_MODE_NOT_INIT;
1172         dsi->status.clk_out = DSI_PHYCLK_OUT_DIS;
1173         dsi->status.clk_mode = DSI_PHYCLK_NOT_INIT;
1174         dsi->status.clk_burst = DSI_CLK_BURST_NOT_INIT;
1175         dsi->status.dc_stream = DSI_DC_STREAM_DISABLE;
1176         dsi->status.lp_op = DSI_LP_OP_NOT_INIT;
1177
1178         return 0;
1179 }
1180
1181 static int tegra_dsi_set_to_lp_mode(struct tegra_dc *dc,
1182                         struct tegra_dc_dsi_data *dsi, u8 lp_op)
1183 {
1184         int err;
1185
1186         if (dsi->status.init != DSI_MODULE_INIT) {
1187                 err = -EPERM;
1188                 goto fail;
1189         }
1190
1191         if (dsi->status.lphs == DSI_LPHS_IN_LP_MODE &&
1192                         dsi->status.lp_op == lp_op)
1193                 goto success;
1194
1195         if (dsi->status.dc_stream == DSI_DC_STREAM_ENABLE)
1196                 tegra_dsi_stop_dc_stream_at_frame_end(dc, dsi);
1197
1198         /* disable/enable hs clk according to enable_hs_clock_on_lp_cmd_mode */
1199         if ((dsi->status.clk_out == DSI_PHYCLK_OUT_EN) &&
1200                 (!dsi->info.enable_hs_clock_on_lp_cmd_mode))
1201                 tegra_dsi_hs_clk_out_disable(dc, dsi);
1202
1203         dsi->target_lp_clk_khz = tegra_dsi_get_lp_clk_rate(dsi, lp_op);
1204         if (dsi->current_dsi_clk_khz != dsi->target_lp_clk_khz) {
1205                 tegra_dsi_set_dsi_clk(dc, dsi, dsi->target_lp_clk_khz);
1206                 tegra_dsi_set_timeout(dsi);
1207         }
1208
1209         tegra_dsi_set_control_reg_lp(dsi);
1210
1211         if ((dsi->status.clk_out == DSI_PHYCLK_OUT_DIS) &&
1212                 (dsi->info.enable_hs_clock_on_lp_cmd_mode))
1213                 tegra_dsi_hs_clk_out_enable_in_lp(dsi);
1214
1215         dsi->status.lphs = DSI_LPHS_IN_LP_MODE;
1216         dsi->status.lp_op = lp_op;
1217 success:
1218         err = 0;
1219 fail:
1220         return err;
1221 }
1222
1223 static int tegra_dsi_set_to_hs_mode(struct tegra_dc *dc,
1224                                         struct tegra_dc_dsi_data *dsi)
1225 {
1226         int err;
1227
1228         if (dsi->status.init != DSI_MODULE_INIT) {
1229                 err = -EPERM;
1230                 goto fail;
1231         }
1232
1233         if (dsi->status.lphs == DSI_LPHS_IN_HS_MODE)
1234                 goto success;
1235
1236         if (dsi->status.dc_stream == DSI_DC_STREAM_ENABLE)
1237                 tegra_dsi_stop_dc_stream_at_frame_end(dc, dsi);
1238
1239         if ((dsi->status.clk_out == DSI_PHYCLK_OUT_EN) &&
1240                 (!dsi->info.enable_hs_clock_on_lp_cmd_mode))
1241                 tegra_dsi_hs_clk_out_disable(dc, dsi);
1242
1243         if (dsi->current_dsi_clk_khz != dsi->target_hs_clk_khz) {
1244                 tegra_dsi_set_dsi_clk(dc, dsi, dsi->target_hs_clk_khz);
1245                 tegra_dsi_set_timeout(dsi);
1246         }
1247
1248         tegra_dsi_set_phy_timing(dsi);
1249
1250         if (dsi->driven_mode == TEGRA_DSI_DRIVEN_BY_DC) {
1251                 tegra_dsi_set_pkt_seq(dc, dsi);
1252                 tegra_dsi_set_pkt_length(dc, dsi);
1253                 tegra_dsi_set_sol_delay(dc, dsi);
1254                 tegra_dsi_set_dc_clk(dc, dsi);
1255         }
1256
1257         tegra_dsi_set_control_reg_hs(dsi);
1258
1259         if (dsi->status.clk_out == DSI_PHYCLK_OUT_DIS ||
1260                 dsi->info.enable_hs_clock_on_lp_cmd_mode)
1261                 tegra_dsi_hs_clk_out_enable(dsi);
1262
1263         dsi->status.lphs = DSI_LPHS_IN_HS_MODE;
1264 success:
1265         dsi->status.lp_op = DSI_LP_OP_NOT_INIT;
1266         err = 0;
1267 fail:
1268         return err;
1269 }
1270
1271 static bool tegra_dsi_write_busy(struct tegra_dc_dsi_data *dsi)
1272 {
1273         u32 timeout = 0;
1274         bool retVal = true;
1275
1276         while (timeout <= DSI_MAX_COMMAND_DELAY_USEC) {
1277                 if (!(DSI_TRIGGER_HOST_TRIGGER(0x1) &
1278                         tegra_dsi_readl(dsi, DSI_TRIGGER))) {
1279                         retVal = false;
1280                         break;
1281                 }
1282                 udelay(DSI_COMMAND_DELAY_STEPS_USEC);
1283                 timeout += DSI_COMMAND_DELAY_STEPS_USEC;
1284         }
1285
1286         return retVal;
1287 }
1288
1289 static bool tegra_dsi_read_busy(struct tegra_dc_dsi_data *dsi)
1290 {
1291         u32 timeout = 0;
1292         bool retVal = true;
1293
1294         while (timeout <  DSI_STATUS_POLLING_DURATION_USEC) {
1295                 if (!(DSI_HOST_DSI_CONTROL_IMM_BTA(0x1) &
1296                         tegra_dsi_readl(dsi, DSI_HOST_DSI_CONTROL))) {
1297                         retVal = false;
1298                         break;
1299                 }
1300                 udelay(DSI_STATUS_POLLING_DELAY_USEC);
1301                 timeout += DSI_STATUS_POLLING_DELAY_USEC;
1302         }
1303
1304         return retVal;
1305 }
1306
1307 static bool tegra_dsi_host_busy(struct tegra_dc_dsi_data *dsi)
1308 {
1309         int err = 0;
1310
1311         if (tegra_dsi_write_busy(dsi)) {
1312                 err = -EBUSY;
1313                 dev_err(&dsi->dc->ndev->dev,
1314                         "DSI trigger bit already set\n");
1315                 goto fail;
1316         }
1317
1318         if (tegra_dsi_read_busy(dsi)) {
1319                 err = -EBUSY;
1320                 dev_err(&dsi->dc->ndev->dev,
1321                         "DSI immediate bta bit already set\n");
1322                 goto fail;
1323         }
1324 fail:
1325         return (err < 0 ? true : false);
1326 }
1327
1328 static void tegra_dsi_reset_underflow_overflow
1329                                 (struct tegra_dc_dsi_data *dsi)
1330 {
1331         u32 val;
1332
1333         val = tegra_dsi_readl(dsi, DSI_STATUS);
1334         val &= (DSI_STATUS_LB_OVERFLOW(0x1) | DSI_STATUS_LB_UNDERFLOW(0x1));
1335         if (val) {
1336                 dev_warn(&dsi->dc->ndev->dev, "Reset overflow/underflow\n");
1337                 val = tegra_dsi_readl(dsi, DSI_HOST_DSI_CONTROL);
1338                 val |= DSI_HOST_CONTROL_FIFO_STAT_RESET(0x1);
1339                 tegra_dsi_writel(dsi, val, DSI_HOST_DSI_CONTROL);
1340                 ndelay(200);
1341         }
1342 }
1343
1344 static void tegra_dsi_soft_reset(struct tegra_dc_dsi_data *dsi)
1345 {
1346         tegra_dsi_writel(dsi,
1347                 DSI_POWER_CONTROL_LEG_DSI_ENABLE(TEGRA_DSI_DISABLE),
1348                 DSI_POWER_CONTROL);
1349         /* stabilization delay */
1350         udelay(300);
1351
1352         tegra_dsi_writel(dsi,
1353                 DSI_POWER_CONTROL_LEG_DSI_ENABLE(TEGRA_DSI_ENABLE),
1354                 DSI_POWER_CONTROL);
1355         /* stabilization delay */
1356         udelay(300);
1357 }
1358
1359 static void tegra_dsi_reset_read_count(struct tegra_dc_dsi_data *dsi)
1360 {
1361         u32 val;
1362
1363         val = tegra_dsi_readl(dsi, DSI_STATUS);
1364         val &= DSI_STATUS_RD_FIFO_COUNT(0x1f);
1365         if (val) {
1366                 dev_warn(&dsi->dc->ndev->dev,
1367                         "DSI read count not zero, resetting\n");
1368                 tegra_dsi_soft_reset(dsi);
1369         }
1370 }
1371
1372 static struct dsi_status *tegra_dsi_save_state_switch_to_host_cmd_mode(
1373                                                 struct tegra_dc_dsi_data *dsi,
1374                                                 struct tegra_dc *dc,
1375                                                 u8 lp_op)
1376 {
1377         struct dsi_status *init_status;
1378         int err;
1379
1380         init_status = kzalloc(sizeof(*init_status), GFP_KERNEL);
1381         if (!init_status)
1382                 return ERR_PTR(-ENOMEM);
1383
1384         *init_status = dsi->status;
1385
1386         if (dsi->status.lphs == DSI_LPHS_IN_HS_MODE) {
1387                 if (dsi->status.driven == DSI_DRIVEN_MODE_DC) {
1388                         if (dsi->status.dc_stream == DSI_DC_STREAM_ENABLE)
1389                                 tegra_dsi_stop_dc_stream_at_frame_end(dc, dsi);
1390                         dsi->driven_mode = TEGRA_DSI_DRIVEN_BY_HOST;
1391                         if (dsi->info.hs_cmd_mode_supported) {
1392                                 err = tegra_dsi_set_to_hs_mode(dc, dsi);
1393                                 if (err < 0) {
1394                                         dev_err(&dc->ndev->dev,
1395                                         "Switch to HS host mode failed\n");
1396                                         goto fail;
1397                                 }
1398                         }
1399                 }
1400                 if (!dsi->info.hs_cmd_mode_supported) {
1401                         err =
1402                         tegra_dsi_set_to_lp_mode(dc, dsi, lp_op);
1403                         if (err < 0) {
1404                                 dev_err(&dc->ndev->dev,
1405                                 "DSI failed to go to LP mode\n");
1406                                 goto fail;
1407                         }
1408                 }
1409         } else if (dsi->status.lphs == DSI_LPHS_IN_LP_MODE) {
1410                 if (dsi->status.lp_op != lp_op) {
1411                         err = tegra_dsi_set_to_lp_mode(dc, dsi, lp_op);
1412                         if (err < 0) {
1413                                 dev_err(&dc->ndev->dev,
1414                                 "DSI failed to go to LP mode\n");
1415                                 goto fail;
1416                         }
1417                 }
1418         }
1419
1420         return init_status;
1421 fail:
1422         kfree(init_status);
1423         return ERR_PTR(err);
1424 }
1425
1426 static struct dsi_status *tegra_dsi_prepare_host_transmission(
1427                                 struct tegra_dc *dc,
1428                                 struct tegra_dc_dsi_data *dsi,
1429                                 u8 lp_op)
1430 {
1431         int err = 0;
1432         struct dsi_status *init_status;
1433
1434         if (dsi->status.init != DSI_MODULE_INIT ||
1435                 dsi->ulpm) {
1436                 err = -EPERM;
1437                 goto fail;
1438         }
1439
1440         if (tegra_dsi_host_busy(dsi)) {
1441                 tegra_dsi_soft_reset(dsi);
1442                 if (tegra_dsi_host_busy(dsi)) {
1443                         err = -EBUSY;
1444                         dev_err(&dc->ndev->dev, "DSI host busy\n");
1445                         goto fail;
1446                 }
1447         }
1448
1449         tegra_dsi_reset_underflow_overflow(dsi);
1450
1451         if (lp_op == DSI_LP_OP_READ)
1452                 tegra_dsi_reset_read_count(dsi);
1453
1454         if (dsi->status.lphs == DSI_LPHS_NOT_INIT) {
1455                 err = tegra_dsi_set_to_lp_mode(dc, dsi, lp_op);
1456                 if (err < 0) {
1457                         dev_err(&dc->ndev->dev, "Failed to config LP write\n");
1458                         goto fail;
1459                 }
1460         }
1461
1462         init_status = tegra_dsi_save_state_switch_to_host_cmd_mode
1463                                         (dsi, dc, lp_op);
1464         if (IS_ERR_OR_NULL(init_status)) {
1465                 err = PTR_ERR(init_status);
1466                 dev_err(&dc->ndev->dev, "DSI state saving failed\n");
1467                 goto fail;
1468         }
1469
1470         return init_status;
1471 fail:
1472         return ERR_PTR(err);
1473 }
1474
1475 static int tegra_dsi_restore_state(struct tegra_dc *dc,
1476                                 struct tegra_dc_dsi_data *dsi,
1477                                 struct dsi_status *init_status)
1478 {
1479         bool switch_back_to_dc_mode = false;
1480         bool switch_back_to_hs_mode = false;
1481         bool restart_dc_stream;
1482         int err = 0;
1483
1484         switch_back_to_dc_mode = (dsi->status.driven ==
1485                                 DSI_DRIVEN_MODE_HOST &&
1486                                 init_status->driven ==
1487                                 DSI_DRIVEN_MODE_DC);
1488         switch_back_to_hs_mode = (dsi->status.lphs ==
1489                                 DSI_LPHS_IN_LP_MODE &&
1490                                 init_status->lphs ==
1491                                 DSI_LPHS_IN_HS_MODE);
1492         restart_dc_stream = (dsi->status.dc_stream ==
1493                                 DSI_DC_STREAM_DISABLE &&
1494                                 init_status->dc_stream ==
1495                                 DSI_DC_STREAM_ENABLE);
1496
1497         if (dsi->status.lphs == DSI_LPHS_IN_LP_MODE &&
1498                 init_status->lphs == DSI_LPHS_IN_LP_MODE) {
1499                 if (dsi->status.lp_op != init_status->lp_op) {
1500                         err =
1501                         tegra_dsi_set_to_lp_mode(dc, dsi, init_status->lp_op);
1502                         if (err < 0) {
1503                                 dev_err(&dc->ndev->dev,
1504                                         "Failed to config LP mode\n");
1505                                 goto fail;
1506                         }
1507                 }
1508                 goto success;
1509         }
1510
1511         if (switch_back_to_dc_mode)
1512                 dsi->driven_mode = TEGRA_DSI_DRIVEN_BY_DC;
1513         if (switch_back_to_dc_mode || switch_back_to_hs_mode) {
1514                 err = tegra_dsi_set_to_hs_mode(dc, dsi);
1515                 if (err < 0) {
1516                         dev_err(&dc->ndev->dev, "Failed to config HS mode\n");
1517                         goto fail;
1518                 }
1519         }
1520         if (restart_dc_stream)
1521                 tegra_dsi_start_dc_stream(dc, dsi);
1522
1523 success:
1524 fail:
1525         kfree(init_status);
1526         return err;
1527 }
1528
1529 static int tegra_dsi_host_trigger(struct tegra_dc_dsi_data *dsi)
1530 {
1531         int status = 0;
1532
1533         if (tegra_dsi_readl(dsi, DSI_TRIGGER)) {
1534                 status = -EBUSY;
1535                 goto fail;
1536         }
1537
1538         tegra_dsi_writel(dsi,
1539                 DSI_TRIGGER_HOST_TRIGGER(TEGRA_DSI_ENABLE), DSI_TRIGGER);
1540
1541 #if DSI_USE_SYNC_POINTS
1542         status = tegra_dsi_syncpt(dsi);
1543         if (status < 0) {
1544                 dev_err(&dsi->dc->ndev->dev,
1545                         "DSI syncpt for host trigger failed\n");
1546                 goto fail;
1547         }
1548 #else
1549         if (tegra_dsi_write_busy(dsi)) {
1550                 status = -EBUSY;
1551                 dev_err(&dsi->dc->ndev->dev,
1552                         "Timeout waiting on write completion\n");
1553         }
1554 #endif
1555
1556 fail:
1557         return status;
1558 }
1559
1560 static int _tegra_dsi_write_data(struct tegra_dc_dsi_data *dsi,
1561                                         u8 *pdata, u8 data_id, u16 data_len)
1562 {
1563         u8 virtual_channel;
1564         u8 *pval;
1565         u32 val;
1566         int err;
1567
1568         err = 0;
1569
1570         virtual_channel = dsi->info.virtual_channel <<
1571                                                 DSI_VIR_CHANNEL_BIT_POSITION;
1572
1573         /* always use hw for ecc */
1574         val = (virtual_channel | data_id) << 0 |
1575                         data_len << 8;
1576         tegra_dsi_writel(dsi, val, DSI_WR_DATA);
1577
1578         /* if pdata != NULL, pkt type is long pkt */
1579         if (pdata != NULL) {
1580                 while (data_len) {
1581                         if (data_len >= 4) {
1582                                 val = ((u32 *) pdata)[0];
1583                                 data_len -= 4;
1584                                 pdata += 4;
1585                         } else {
1586                                 val = 0;
1587                                 pval = (u8 *) &val;
1588                                 do
1589                                         *pval++ = *pdata++;
1590                                 while (--data_len);
1591                         }
1592                         tegra_dsi_writel(dsi, val, DSI_WR_DATA);
1593                 }
1594         }
1595
1596         err = tegra_dsi_host_trigger(dsi);
1597         if (err < 0)
1598                 dev_err(&dsi->dc->ndev->dev, "DSI host trigger failed\n");
1599
1600         return err;
1601 }
1602
1603 int tegra_dsi_write_data(struct tegra_dc *dc,
1604                         struct tegra_dc_dsi_data *dsi,
1605                         u8 *pdata, u8 data_id, u16 data_len)
1606 {
1607         int err = 0;
1608         struct dsi_status *init_status;
1609
1610         tegra_dc_io_start(dc);
1611
1612         init_status = tegra_dsi_prepare_host_transmission(
1613                                 dc, dsi, DSI_LP_OP_WRITE);
1614         if (IS_ERR_OR_NULL(init_status)) {
1615                 err = PTR_ERR(init_status);
1616                 dev_err(&dc->ndev->dev, "DSI host config failed\n");
1617                 goto fail;
1618         }
1619
1620         err = _tegra_dsi_write_data(dsi, pdata, data_id, data_len);
1621 fail:
1622         err = tegra_dsi_restore_state(dc, dsi, init_status);
1623         if (err < 0)
1624                 dev_err(&dc->ndev->dev, "Failed to restore prev state\n");
1625         tegra_dc_io_end(dc);
1626         return err;
1627 }
1628 EXPORT_SYMBOL(tegra_dsi_write_data);
1629
1630 static int tegra_dsi_send_panel_cmd(struct tegra_dc *dc,
1631                                         struct tegra_dc_dsi_data *dsi,
1632                                         struct tegra_dsi_cmd *cmd,
1633                                         u32 n_cmd)
1634 {
1635         u32 i;
1636         int err;
1637
1638         err = 0;
1639         for (i = 0; i < n_cmd; i++) {
1640                 struct tegra_dsi_cmd *cur_cmd;
1641                 cur_cmd = &cmd[i];
1642
1643                 if (cur_cmd->cmd_type == TEGRA_DSI_DELAY_MS)
1644                         mdelay(cur_cmd->sp_len_dly.delay_ms);
1645                 else {
1646                         err = tegra_dsi_write_data(dc, dsi,
1647                                                 cur_cmd->pdata,
1648                                                 cur_cmd->data_id,
1649                                                 cur_cmd->sp_len_dly.data_len);
1650                         if (err < 0)
1651                                 break;
1652                 }
1653         }
1654         return err;
1655 }
1656
1657 static u8 get_8bit_ecc(u32 header)
1658 {
1659         char ecc_parity[24] = {
1660                 0x07, 0x0b, 0x0d, 0x0e, 0x13, 0x15, 0x16, 0x19,
1661                 0x1a, 0x1c, 0x23, 0x25, 0x26, 0x29, 0x2a, 0x2c,
1662                 0x31, 0x32, 0x34, 0x38, 0x1f, 0x2f, 0x37, 0x3b
1663         };
1664         u8 ecc_byte;
1665         int i;
1666
1667         ecc_byte = 0;
1668         for (i = 0; i < 24; i++)
1669                 ecc_byte ^= ((header >> i) & 1) ? ecc_parity[i] : 0x00;
1670
1671         return ecc_byte;
1672 }
1673
1674 /* This function is written to send DCS short write (1 parameter) only.
1675  * This means the cmd will contain only 1 byte of index and 1 byte of value.
1676  * The data type ID is fixed at 0x15 and the ECC is calculated based on the
1677  * data in pdata.
1678  * The command will be sent by hardware every frame.
1679  * pdata should contain both the index + value for each cmd.
1680  * data_len will be the total number of bytes in pdata.
1681  */
1682 int tegra_dsi_send_panel_short_cmd(struct tegra_dc *dc, u8 *pdata, u8 data_len)
1683 {
1684         u8 ecc8bits = 0, data_len_orig = 0;
1685         u32 val = 0, pkthdr = 0;
1686         int err = 0, count = 0;
1687         struct tegra_dc_dsi_data *dsi = tegra_dc_get_outdata(dc);
1688
1689         data_len_orig = data_len;
1690         if (pdata != NULL) {
1691                 while (data_len) {
1692                         if (data_len >= 2) {
1693                                 pkthdr = (CMD_SHORTW |
1694                                         (((u16 *)pdata)[0]) << 8 | 0x00 << 24);
1695                                 ecc8bits = get_8bit_ecc(pkthdr);
1696                                 val = (pkthdr | (ecc8bits << 24));
1697                                 data_len -= 2;
1698                                 pdata += 2;
1699                                 count++;
1700                         }
1701                         switch (count) {
1702                         case 1:
1703                                 tegra_dsi_writel(dsi, val, DSI_INIT_SEQ_DATA_0);
1704                                 break;
1705                         case 2:
1706                                 tegra_dsi_writel(dsi, val, DSI_INIT_SEQ_DATA_1);
1707                                 break;
1708                         case 3:
1709                                 tegra_dsi_writel(dsi, val, DSI_INIT_SEQ_DATA_2);
1710                                 break;
1711                         case 4:
1712                                 tegra_dsi_writel(dsi, val, DSI_INIT_SEQ_DATA_3);
1713                                 break;
1714                         case 5:
1715                                 tegra_dsi_writel(dsi, val, DSI_INIT_SEQ_DATA_4);
1716                                 break;
1717                         case 6:
1718                                 tegra_dsi_writel(dsi, val, DSI_INIT_SEQ_DATA_5);
1719                                 break;
1720                         case 7:
1721                                 tegra_dsi_writel(dsi, val, DSI_INIT_SEQ_DATA_6);
1722                                 break;
1723                         case 8:
1724                                 tegra_dsi_writel(dsi, val, DSI_INIT_SEQ_DATA_7);
1725                                 break;
1726                         default:
1727                                 err = 1;
1728                                 break;
1729                         }
1730                 }
1731         }
1732
1733         val = DSI_INIT_SEQ_CONTROL_DSI_FRAME_INIT_BYTE_COUNT(data_len_orig * 2)
1734                 | DSI_INIT_SEQ_CONTROL_DSI_SEND_INIT_SEQUENCE(1);
1735         tegra_dsi_writel(dsi, val, DSI_INIT_SEQ_CONTROL);
1736
1737         return err;
1738 }
1739 EXPORT_SYMBOL(tegra_dsi_send_panel_short_cmd);
1740
1741 static int tegra_dsi_bta(struct tegra_dc_dsi_data *dsi)
1742 {
1743         u32 val;
1744         u32 poll_time;
1745         int err;
1746
1747         poll_time = 0;
1748         err = 0;
1749
1750         val = tegra_dsi_readl(dsi, DSI_HOST_DSI_CONTROL);
1751         val |= DSI_HOST_DSI_CONTROL_IMM_BTA(TEGRA_DSI_ENABLE);
1752         tegra_dsi_writel(dsi, val, DSI_HOST_DSI_CONTROL);
1753
1754 #if DSI_USE_SYNC_POINTS
1755         /* FIXME: Workaround for nvhost_syncpt_read */
1756         dsi->syncpt_val = nvhost_syncpt_update_min(
1757                         &nvhost_get_host(dsi->dc->ndev)->syncpt,
1758                         dsi->syncpt_id);
1759
1760         val = DSI_INCR_SYNCPT_COND(OP_DONE) |
1761                 DSI_INCR_SYNCPT_INDX(dsi->syncpt_id);
1762         tegra_dsi_writel(dsi, val, DSI_INCR_SYNCPT);
1763
1764         /* TODO: Use interrupt rather than polling */
1765         err = nvhost_syncpt_wait(&nvhost_get_host(dsi->dc->ndev)->syncpt,
1766                 dsi->syncpt_id, dsi->syncpt_val + 1);
1767         if (err < 0)
1768                 dev_err(&dsi->dc->ndev->dev,
1769                         "DSI sync point failure\n");
1770         else
1771                 (dsi->syncpt_val)++;
1772 #else
1773         if (tegra_dsi_read_busy(dsi)) {
1774                 err = -EBUSY;
1775                 dev_err(&dsi->dc->ndev->dev,
1776                         "Timeout wating on read completion\n");
1777         }
1778 #endif
1779
1780         return err;
1781 }
1782
1783 static int tegra_dsi_parse_read_response(struct tegra_dc *dc,
1784                                         u32 rd_fifo_cnt, u8 *read_fifo)
1785 {
1786         int err;
1787         u32 payload_size;
1788
1789         payload_size = 0;
1790         err = 0;
1791
1792         switch (read_fifo[0]) {
1793         case DSI_ESCAPE_CMD:
1794                 dev_info(&dc->ndev->dev, "escape cmd[0x%x]\n", read_fifo[0]);
1795                 break;
1796         case DSI_ACK_NO_ERR:
1797                 dev_info(&dc->ndev->dev,
1798                         "Panel ack, no err[0x%x]\n", read_fifo[0]);
1799                 return err;
1800         default:
1801                 dev_info(&dc->ndev->dev, "Invalid read response\n");
1802                 break;
1803         }
1804
1805         switch (read_fifo[4] & 0xff) {
1806         case GEN_LONG_RD_RES:
1807                 /* Fall through */
1808         case DCS_LONG_RD_RES:
1809                 payload_size = (read_fifo[5] |
1810                                 (read_fifo[6] << 8)) & 0xFFFF;
1811                 dev_info(&dc->ndev->dev, "Long read response Packet\n"
1812                                 "payload_size[0x%x]\n", payload_size);
1813                 break;
1814         case GEN_1_BYTE_SHORT_RD_RES:
1815                 /* Fall through */
1816         case DCS_1_BYTE_SHORT_RD_RES:
1817                 payload_size = 1;
1818                 dev_info(&dc->ndev->dev, "Short read response Packet\n"
1819                         "payload_size[0x%x]\n", payload_size);
1820                 break;
1821         case GEN_2_BYTE_SHORT_RD_RES:
1822                 /* Fall through */
1823         case DCS_2_BYTE_SHORT_RD_RES:
1824                 payload_size = 2;
1825                 dev_info(&dc->ndev->dev, "Short read response Packet\n"
1826                         "payload_size[0x%x]\n", payload_size);
1827                 break;
1828         case ACK_ERR_RES:
1829                 payload_size = 2;
1830                 dev_info(&dc->ndev->dev, "Acknowledge error report response\n"
1831                         "Packet payload_size[0x%x]\n", payload_size);
1832                 break;
1833         default:
1834                 dev_info(&dc->ndev->dev, "Invalid response packet\n");
1835                 err = -EINVAL;
1836                 break;
1837         }
1838         return err;
1839 }
1840
1841 static int tegra_dsi_read_fifo(struct tegra_dc *dc,
1842                         struct tegra_dc_dsi_data *dsi,
1843                         u8 *read_fifo)
1844 {
1845         u32 val;
1846         u32 i;
1847         u32 poll_time = 0;
1848         u32 rd_fifo_cnt;
1849         int err = 0;
1850         u8 *read_fifo_cp = read_fifo;
1851
1852         while (poll_time <  DSI_DELAY_FOR_READ_FIFO) {
1853                 mdelay(1);
1854                 val = tegra_dsi_readl(dsi, DSI_STATUS);
1855                 rd_fifo_cnt = val & DSI_STATUS_RD_FIFO_COUNT(0x1f);
1856                 if (rd_fifo_cnt << 2 > DSI_READ_FIFO_DEPTH)
1857                         dev_err(&dc->ndev->dev,
1858                         "DSI RD_FIFO_CNT is greater than RD_FIFO_DEPTH\n");
1859                         break;
1860                 poll_time++;
1861         }
1862
1863         if (rd_fifo_cnt == 0) {
1864                 dev_info(&dc->ndev->dev,
1865                         "DSI RD_FIFO_CNT is zero\n");
1866                 err = -EINVAL;
1867                 goto fail;
1868         }
1869
1870         if (val & (DSI_STATUS_LB_UNDERFLOW(0x1) |
1871                 DSI_STATUS_LB_OVERFLOW(0x1))) {
1872                 dev_warn(&dc->ndev->dev,
1873                         "DSI overflow/underflow error\n");
1874         }
1875
1876         /* Read data from FIFO */
1877         for (i = 0; i < rd_fifo_cnt; i++) {
1878                 val = tegra_dsi_readl(dsi, DSI_RD_DATA);
1879                 if (enable_read_debug)
1880                         dev_info(&dc->ndev->dev,
1881                         "Read data[%d]: 0x%x\n", i, val);
1882                 memcpy(read_fifo, &val, 4);
1883                 read_fifo += 4;
1884         }
1885
1886         /* Make sure all the data is read from the FIFO */
1887         val = tegra_dsi_readl(dsi, DSI_STATUS);
1888         val &= DSI_STATUS_RD_FIFO_COUNT(0x1f);
1889         if (val)
1890                 dev_err(&dc->ndev->dev, "DSI FIFO_RD_CNT not zero"
1891                 " even after reading FIFO_RD_CNT words from read fifo\n");
1892
1893         if (enable_read_debug) {
1894                 err =
1895                 tegra_dsi_parse_read_response(dc, rd_fifo_cnt, read_fifo_cp);
1896                 if (err < 0)
1897                         dev_warn(&dc->ndev->dev, "Unexpected read data\n");
1898         }
1899 fail:
1900         return err;
1901 }
1902
1903 int tegra_dsi_read_data(struct tegra_dc *dc,
1904                                 struct tegra_dc_dsi_data *dsi,
1905                                 u32 max_ret_payload_size,
1906                                 u32 panel_reg_addr, u8 *read_data)
1907 {
1908         int err = 0;
1909         struct dsi_status *init_status;
1910
1911         tegra_dc_io_start(dc);
1912
1913         init_status = tegra_dsi_prepare_host_transmission(
1914                                 dc, dsi, DSI_LP_OP_WRITE);
1915         if (IS_ERR_OR_NULL(init_status)) {
1916                 err = PTR_ERR(init_status);
1917                 dev_err(&dc->ndev->dev, "DSI host config failed\n");
1918                 goto fail;
1919         }
1920
1921         /* Set max return payload size in words */
1922         err = _tegra_dsi_write_data(dsi, NULL,
1923                 dsi_command_max_return_pkt_size,
1924                 max_ret_payload_size);
1925         if (err < 0) {
1926                 dev_err(&dc->ndev->dev,
1927                                 "DSI write failed\n");
1928                 goto fail;
1929         }
1930
1931         /* DCS to read given panel register */
1932         err = _tegra_dsi_write_data(dsi, NULL,
1933                 dsi_command_dcs_read_with_no_params,
1934                 panel_reg_addr);
1935         if (err < 0) {
1936                 dev_err(&dc->ndev->dev,
1937                                 "DSI write failed\n");
1938                 goto fail;
1939         }
1940
1941         tegra_dsi_reset_read_count(dsi);
1942
1943         if (dsi->status.lp_op == DSI_LP_OP_WRITE) {
1944                 err = tegra_dsi_set_to_lp_mode(dc, dsi, DSI_LP_OP_READ);
1945                 if (err < 0) {
1946                         dev_err(&dc->ndev->dev,
1947                         "DSI failed to go to LP read mode\n");
1948                         goto fail;
1949                 }
1950         }
1951
1952         err = tegra_dsi_bta(dsi);
1953         if (err < 0) {
1954                 dev_err(&dc->ndev->dev,
1955                         "DSI IMM BTA timeout\n");
1956                 goto fail;
1957         }
1958
1959         err = tegra_dsi_read_fifo(dc, dsi, read_data);
1960         if (err < 0) {
1961                 dev_err(&dc->ndev->dev, "DSI read fifo failure\n");
1962                 goto fail;
1963         }
1964 fail:
1965         err = tegra_dsi_restore_state(dc, dsi, init_status);
1966         if (err < 0)
1967                 dev_err(&dc->ndev->dev, "Failed to restore prev state\n");
1968         tegra_dc_io_end(dc);
1969         return err;
1970 }
1971 EXPORT_SYMBOL(tegra_dsi_read_data);
1972
1973 int tegra_dsi_panel_sanity_check(struct tegra_dc *dc,
1974                                 struct tegra_dc_dsi_data *dsi)
1975 {
1976         int err = 0;
1977         u8 read_fifo[DSI_READ_FIFO_DEPTH];
1978         struct dsi_status *init_status;
1979         static struct tegra_dsi_cmd dsi_nop_cmd =
1980                         DSI_CMD_SHORT(0x05, 0x0, 0x0);
1981
1982         tegra_dc_io_start(dc);
1983
1984         init_status = tegra_dsi_prepare_host_transmission(
1985                                         dc, dsi, DSI_LP_OP_WRITE);
1986         if (IS_ERR_OR_NULL(init_status)) {
1987                 err = PTR_ERR(init_status);
1988                 dev_err(&dc->ndev->dev, "DSI host config failed\n");
1989                 goto fail;
1990         }
1991
1992         err = _tegra_dsi_write_data(dsi, NULL, dsi_nop_cmd.data_id, 0x0);
1993         if (err < 0) {
1994                 dev_err(&dc->ndev->dev, "DSI nop write failed\n");
1995                 goto fail;
1996         }
1997
1998         tegra_dsi_reset_read_count(dsi);
1999
2000         if (dsi->status.lp_op == DSI_LP_OP_WRITE) {
2001                 err = tegra_dsi_set_to_lp_mode(dc, dsi, DSI_LP_OP_READ);
2002                 if (err < 0) {
2003                         dev_err(&dc->ndev->dev,
2004                         "DSI failed to go to LP read mode\n");
2005                         goto fail;
2006                 }
2007         }
2008
2009         err = tegra_dsi_bta(dsi);
2010         if (err < 0) {
2011                 dev_err(&dc->ndev->dev, "DSI BTA failed\n");
2012                 goto fail;
2013         }
2014
2015         err = tegra_dsi_read_fifo(dc, dsi, read_fifo);
2016         if (err < 0) {
2017                 dev_err(&dc->ndev->dev, "DSI read fifo failure\n");
2018                 goto fail;
2019         }
2020
2021         if (read_fifo[0] != DSI_ACK_NO_ERR) {
2022                 dev_warn(&dc->ndev->dev,
2023                         "Ack no error trigger message not received\n");
2024                 err = -EAGAIN;
2025         }
2026 fail:
2027         err = tegra_dsi_restore_state(dc, dsi, init_status);
2028         if (err < 0)
2029                 dev_err(&dc->ndev->dev, "Failed to restore prev state\n");
2030         tegra_dc_io_end(dc);
2031         return err;
2032 }
2033 EXPORT_SYMBOL(tegra_dsi_panel_sanity_check);
2034
2035 static int tegra_dsi_enter_ulpm(struct tegra_dc_dsi_data *dsi)
2036 {
2037         u32 val;
2038         int ret;
2039
2040         ret = 0;
2041
2042         val = tegra_dsi_readl(dsi, DSI_HOST_DSI_CONTROL);
2043         val &= ~DSI_HOST_DSI_CONTROL_ULTRA_LOW_POWER(3);
2044         val |= DSI_HOST_DSI_CONTROL_ULTRA_LOW_POWER(ENTER_ULPM);
2045         tegra_dsi_writel(dsi, val, DSI_HOST_DSI_CONTROL);
2046
2047 #if DSI_USE_SYNC_POINTS
2048         ret = tegra_dsi_syncpt(dsi);
2049         if (ret < 0) {
2050                 dev_err(&dsi->dc->ndev->dev,
2051                         "DSI syncpt for ulpm enter failed\n");
2052                 goto fail;
2053         }
2054 #else
2055         /* TODO: Find exact delay required */
2056         mdelay(10);
2057 #endif
2058         dsi->ulpm = true;
2059 fail:
2060         return ret;
2061 }
2062
2063 static int tegra_dsi_exit_ulpm(struct tegra_dc_dsi_data *dsi)
2064 {
2065         u32 val;
2066         int ret;
2067
2068         ret = 0;
2069
2070         val = tegra_dsi_readl(dsi, DSI_HOST_DSI_CONTROL);
2071         val &= ~DSI_HOST_DSI_CONTROL_ULTRA_LOW_POWER(3);
2072         val |= DSI_HOST_DSI_CONTROL_ULTRA_LOW_POWER(EXIT_ULPM);
2073         tegra_dsi_writel(dsi, val, DSI_HOST_DSI_CONTROL);
2074
2075 #if DSI_USE_SYNC_POINTS
2076         ret = tegra_dsi_syncpt(dsi);
2077         if (ret < 0) {
2078                 dev_err(&dsi->dc->ndev->dev,
2079                         "DSI syncpt for ulpm exit failed\n");
2080                 goto fail;
2081         }
2082 #else
2083         /* TODO: Find exact delay required */
2084         mdelay(10);
2085 #endif
2086         dsi->ulpm = false;
2087
2088         val = tegra_dsi_readl(dsi, DSI_HOST_DSI_CONTROL);
2089         val &= ~DSI_HOST_DSI_CONTROL_ULTRA_LOW_POWER(0x3);
2090         val |= DSI_HOST_DSI_CONTROL_ULTRA_LOW_POWER(NORMAL);
2091         tegra_dsi_writel(dsi, val, DSI_HOST_DSI_CONTROL);
2092 fail:
2093         return ret;
2094
2095 }
2096
2097 static void tegra_dc_dsi_enable(struct tegra_dc *dc)
2098 {
2099         struct tegra_dc_dsi_data *dsi = tegra_dc_get_outdata(dc);
2100         int err;
2101         u32 val;
2102
2103         tegra_dc_io_start(dc);
2104         mutex_lock(&dsi->lock);
2105
2106         /* Stop DC stream before configuring DSI registers
2107          * to avoid visible glitches on panel during transition
2108          * from bootloader to kernel driver
2109          */
2110         tegra_dsi_stop_dc_stream(dc, dsi);
2111
2112         if (dsi->enabled) {
2113                 if (dsi->ulpm) {
2114                         if (tegra_dsi_exit_ulpm(dsi) < 0) {
2115                                 dev_err(&dc->ndev->dev,
2116                                         "DSI failed to exit ulpm\n");
2117                                 goto fail;
2118                         }
2119                 }
2120
2121                 if (dsi->info.panel_reset) {
2122                         err = tegra_dsi_send_panel_cmd(dc, dsi,
2123                                                         dsi->info.dsi_init_cmd,
2124                                                         dsi->info.n_init_cmd);
2125                         if (err < 0) {
2126                                 dev_err(&dc->ndev->dev,
2127                                 "dsi: error sending dsi init cmd\n");
2128                                 goto fail;
2129                         }
2130                 } else if (dsi->info.dsi_late_resume_cmd) {
2131                         err = tegra_dsi_send_panel_cmd(dc, dsi,
2132                                                 dsi->info.dsi_late_resume_cmd,
2133                                                 dsi->info.n_late_resume_cmd);
2134                         if (err < 0) {
2135                                 dev_err(&dc->ndev->dev,
2136                                 "dsi: error sending late resume cmd\n");
2137                                 goto fail;
2138                         }
2139                 }
2140         } else {
2141                 err = tegra_dsi_init_hw(dc, dsi);
2142                 if (err < 0) {
2143                         dev_err(&dc->ndev->dev,
2144                                 "dsi: not able to init dsi hardware\n");
2145                         goto fail;
2146                 }
2147
2148                 if (dsi->ulpm) {
2149                         if (tegra_dsi_enter_ulpm(dsi) < 0) {
2150                                 dev_err(&dc->ndev->dev,
2151                                         "DSI failed to enter ulpm\n");
2152                                 goto fail;
2153                         }
2154                         val = DSI_PAD_CONTROL_PAD_PDIO(0) |
2155                                 DSI_PAD_CONTROL_PAD_PDIO_CLK(0) |
2156                                 DSI_PAD_CONTROL_PAD_PULLDN_ENAB
2157                                                 (TEGRA_DSI_DISABLE);
2158                         tegra_dsi_writel(dsi, val, DSI_PAD_CONTROL);
2159                         if (tegra_dsi_exit_ulpm(dsi) < 0) {
2160                                 dev_err(&dc->ndev->dev,
2161                                         "DSI failed to exit ulpm\n");
2162                                 goto fail;
2163                         }
2164                 }
2165
2166                 err = tegra_dsi_set_to_lp_mode(dc, dsi, DSI_LP_OP_WRITE);
2167                 if (err < 0) {
2168                         dev_err(&dc->ndev->dev,
2169                                 "dsi: not able to set to lp mode\n");
2170                         goto fail;
2171                 }
2172
2173                 err = tegra_dsi_send_panel_cmd(dc, dsi, dsi->info.dsi_init_cmd,
2174                                                 dsi->info.n_init_cmd);
2175                 if (err < 0) {
2176                         dev_err(&dc->ndev->dev,
2177                                 "dsi: error while sending dsi init cmd\n");
2178                         goto fail;
2179                 }
2180
2181                 err = tegra_dsi_set_to_hs_mode(dc, dsi);
2182                 if (err < 0) {
2183                         dev_err(&dc->ndev->dev,
2184                                 "dsi: not able to set to hs mode\n");
2185                         goto fail;
2186                 }
2187
2188                 dsi->enabled = true;
2189         }
2190
2191         if (dsi->status.driven == DSI_DRIVEN_MODE_DC)
2192                 tegra_dsi_start_dc_stream(dc, dsi);
2193 fail:
2194         mutex_unlock(&dsi->lock);
2195         tegra_dc_io_end(dc);
2196 }
2197
2198 static void _tegra_dc_dsi_init(struct tegra_dc *dc)
2199 {
2200         struct tegra_dc_dsi_data *dsi = tegra_dc_get_outdata(dc);
2201
2202         tegra_dsi_init_sw(dc, dsi);
2203         /* TODO: Configure the CSI pad configuration */
2204 }
2205
2206 static int tegra_dc_dsi_cp_p_cmd(struct tegra_dsi_cmd *src,
2207                                         struct tegra_dsi_cmd *dst, u16 n_cmd)
2208 {
2209         u16 i;
2210         u16 len;
2211
2212         memcpy(dst, src, sizeof(*dst) * n_cmd);
2213
2214         for (i = 0; i < n_cmd; i++)
2215                 if (src[i].pdata) {
2216                         len = sizeof(*src[i].pdata) *
2217                                         src[i].sp_len_dly.data_len;
2218                         dst[i].pdata = kzalloc(len, GFP_KERNEL);
2219                         if (!dst[i].pdata)
2220                                 goto free_cmd_pdata;
2221                         memcpy(dst[i].pdata, src[i].pdata, len);
2222                 }
2223
2224         return 0;
2225
2226 free_cmd_pdata:
2227         for (--i; i >= 0; i--)
2228                 if (dst[i].pdata)
2229                         kfree(dst[i].pdata);
2230         return -ENOMEM;
2231 }
2232
2233 static int tegra_dc_dsi_cp_info(struct tegra_dc_dsi_data *dsi,
2234                                         struct tegra_dsi_out *p_dsi)
2235 {
2236         struct tegra_dsi_cmd *p_init_cmd;
2237         struct tegra_dsi_cmd *p_early_suspend_cmd;
2238         struct tegra_dsi_cmd *p_late_resume_cmd;
2239         struct tegra_dsi_cmd *p_suspend_cmd;
2240         int err;
2241
2242         if (p_dsi->n_data_lanes > MAX_DSI_DATA_LANES)
2243                 return -EINVAL;
2244
2245         p_init_cmd = kzalloc(sizeof(*p_init_cmd) *
2246                                 p_dsi->n_init_cmd, GFP_KERNEL);
2247         if (!p_init_cmd)
2248                 return -ENOMEM;
2249
2250         if (p_dsi->dsi_early_suspend_cmd) {
2251                 p_early_suspend_cmd = kzalloc(sizeof(*p_early_suspend_cmd) *
2252                                         p_dsi->n_early_suspend_cmd,
2253                                         GFP_KERNEL);
2254                 if (!p_early_suspend_cmd) {
2255                         err = -ENOMEM;
2256                         goto err_free_init_cmd;
2257                 }
2258         }
2259
2260         if (p_dsi->dsi_late_resume_cmd) {
2261                 p_late_resume_cmd = kzalloc(sizeof(*p_late_resume_cmd) *
2262                                         p_dsi->n_late_resume_cmd,
2263                                         GFP_KERNEL);
2264                 if (!p_late_resume_cmd) {
2265                         err = -ENOMEM;
2266                         goto err_free_p_early_suspend_cmd;
2267                 }
2268         }
2269
2270         p_suspend_cmd = kzalloc(sizeof(*p_suspend_cmd) * p_dsi->n_suspend_cmd,
2271                                 GFP_KERNEL);
2272         if (!p_suspend_cmd) {
2273                 err = -ENOMEM;
2274                 goto err_free_p_late_resume_cmd;
2275         }
2276
2277         memcpy(&dsi->info, p_dsi, sizeof(dsi->info));
2278
2279         /* Copy panel init cmd */
2280         err = tegra_dc_dsi_cp_p_cmd(p_dsi->dsi_init_cmd,
2281                                                 p_init_cmd, p_dsi->n_init_cmd);
2282         if (err < 0)
2283                 goto err_free;
2284         dsi->info.dsi_init_cmd = p_init_cmd;
2285
2286         /* Copy panel early suspend cmd */
2287         if (p_dsi->dsi_early_suspend_cmd) {
2288                 err = tegra_dc_dsi_cp_p_cmd(p_dsi->dsi_early_suspend_cmd,
2289                                         p_early_suspend_cmd,
2290                                         p_dsi->n_early_suspend_cmd);
2291                 if (err < 0)
2292                         goto err_free;
2293                 dsi->info.dsi_early_suspend_cmd = p_early_suspend_cmd;
2294         }
2295
2296         /* Copy panel late resume cmd */
2297         if (p_dsi->dsi_late_resume_cmd) {
2298                 err = tegra_dc_dsi_cp_p_cmd(p_dsi->dsi_late_resume_cmd,
2299                                                 p_late_resume_cmd,
2300                                                 p_dsi->n_late_resume_cmd);
2301                 if (err < 0)
2302                         goto err_free;
2303                 dsi->info.dsi_late_resume_cmd = p_late_resume_cmd;
2304         }
2305
2306         /* Copy panel suspend cmd */
2307         err = tegra_dc_dsi_cp_p_cmd(p_dsi->dsi_suspend_cmd, p_suspend_cmd,
2308                                         p_dsi->n_suspend_cmd);
2309         if (err < 0)
2310                 goto err_free;
2311         dsi->info.dsi_suspend_cmd = p_suspend_cmd;
2312
2313         if (!dsi->info.panel_reset_timeout_msec)
2314                 dsi->info.panel_reset_timeout_msec =
2315                                                 DEFAULT_PANEL_RESET_TIMEOUT;
2316
2317         if (!dsi->info.panel_buffer_size_byte)
2318                 dsi->info.panel_buffer_size_byte = DEFAULT_PANEL_BUFFER_BYTE;
2319
2320         if (!dsi->info.max_panel_freq_khz) {
2321                 dsi->info.max_panel_freq_khz = DEFAULT_MAX_DSI_PHY_CLK_KHZ;
2322
2323                 if (dsi->info.video_burst_mode >
2324                                 TEGRA_DSI_VIDEO_NONE_BURST_MODE_WITH_SYNC_END){
2325                         dev_err(&dsi->dc->ndev->dev, "DSI: max_panel_freq_khz"
2326                                         "is not set for DSI burst mode.\n");
2327                         dsi->info.video_burst_mode =
2328                                 TEGRA_DSI_VIDEO_BURST_MODE_LOWEST_SPEED;
2329                 }
2330         }
2331
2332         if (!dsi->info.lp_cmd_mode_freq_khz)
2333                 dsi->info.lp_cmd_mode_freq_khz = DEFAULT_LP_CMD_MODE_CLK_KHZ;
2334
2335         if (!dsi->info.chip_id || !dsi->info.chip_rev)
2336                 dev_warn(&dsi->dc->ndev->dev,
2337                         "DSI: Failed to get chip info\n");
2338
2339         if (!dsi->info.lp_read_cmd_mode_freq_khz)
2340                 dsi->info.lp_read_cmd_mode_freq_khz =
2341                         dsi->info.lp_cmd_mode_freq_khz;
2342
2343         /* host mode is for testing only */
2344         dsi->driven_mode = TEGRA_DSI_DRIVEN_BY_DC;
2345         return 0;
2346
2347 err_free:
2348         kfree(p_suspend_cmd);
2349 err_free_p_late_resume_cmd:
2350         kfree(p_late_resume_cmd);
2351 err_free_p_early_suspend_cmd:
2352         kfree(p_early_suspend_cmd);
2353 err_free_init_cmd:
2354         kfree(p_init_cmd);
2355         return err;
2356 }
2357
2358 static int tegra_dc_dsi_init(struct tegra_dc *dc)
2359 {
2360         struct tegra_dc_dsi_data *dsi;
2361         struct resource *res;
2362         struct resource *base_res;
2363         void __iomem *base;
2364         struct clk *dc_clk = NULL;
2365         struct clk *dsi_clk = NULL;
2366         struct tegra_dsi_out *dsi_pdata;
2367         int err;
2368
2369         err = 0;
2370
2371         dsi = kzalloc(sizeof(*dsi), GFP_KERNEL);
2372         if (!dsi)
2373                 return -ENOMEM;
2374
2375         res = nvhost_get_resource_byname(dc->ndev, IORESOURCE_MEM,
2376                                         "dsi_regs");
2377         if (!res) {
2378                 dev_err(&dc->ndev->dev, "dsi: no mem resource\n");
2379                 err = -ENOENT;
2380                 goto err_free_dsi;
2381         }
2382
2383         base_res = request_mem_region(res->start, resource_size(res),
2384                                 dc->ndev->name);
2385         if (!base_res) {
2386                 dev_err(&dc->ndev->dev, "dsi: request_mem_region failed\n");
2387                 err = -EBUSY;
2388                 goto err_free_dsi;
2389         }
2390
2391         base = ioremap(res->start, resource_size(res));
2392         if (!base) {
2393                 dev_err(&dc->ndev->dev, "dsi: registers can't be mapped\n");
2394                 err = -EBUSY;
2395                 goto err_release_regs;
2396         }
2397
2398         dsi_pdata = dc->pdata->default_out->dsi;
2399         if (!dsi_pdata) {
2400                 dev_err(&dc->ndev->dev, "dsi: dsi data not available\n");
2401                 goto err_release_regs;
2402         }
2403
2404         if (dsi_pdata->dsi_instance)
2405                 dsi_clk = clk_get(&dc->ndev->dev, "dsib");
2406         else
2407                 dsi_clk = clk_get(&dc->ndev->dev, "dsia");
2408
2409         if (IS_ERR_OR_NULL(dsi_clk)) {
2410                 dev_err(&dc->ndev->dev, "dsi: can't get clock\n");
2411                 err = -EBUSY;
2412                 goto err_release_regs;
2413         }
2414
2415         dc_clk = clk_get_sys(dev_name(&dc->ndev->dev), NULL);
2416         if (IS_ERR_OR_NULL(dc_clk)) {
2417                 dev_err(&dc->ndev->dev, "dsi: dc clock %s unavailable\n",
2418                         dev_name(&dc->ndev->dev));
2419                 err = -EBUSY;
2420                 goto err_clk_put;
2421         }
2422
2423         mutex_init(&dsi->lock);
2424         dsi->dc = dc;
2425         dsi->base = base;
2426         dsi->base_res = base_res;
2427         dsi->dc_clk = dc_clk;
2428         dsi->dsi_clk = dsi_clk;
2429
2430         err = tegra_dc_dsi_cp_info(dsi, dsi_pdata);
2431         if (err < 0)
2432                 goto err_dsi_data;
2433
2434         tegra_dc_set_outdata(dc, dsi);
2435         _tegra_dc_dsi_init(dc);
2436
2437         return 0;
2438
2439 err_dsi_data:
2440 err_clk_put:
2441         clk_put(dsi_clk);
2442 err_release_regs:
2443         release_resource(base_res);
2444 err_free_dsi:
2445         kfree(dsi);
2446
2447         return err;
2448 }
2449
2450 static void tegra_dc_dsi_destroy(struct tegra_dc *dc)
2451 {
2452         struct tegra_dc_dsi_data *dsi = tegra_dc_get_outdata(dc);
2453         u16 i;
2454         u32 val;
2455
2456         mutex_lock(&dsi->lock);
2457
2458         /* free up the pdata */
2459         for (i = 0; i < dsi->info.n_init_cmd; i++) {
2460                 if (dsi->info.dsi_init_cmd[i].pdata)
2461                         kfree(dsi->info.dsi_init_cmd[i].pdata);
2462         }
2463         kfree(dsi->info.dsi_init_cmd);
2464
2465         /* Disable dc stream */
2466         if (dsi->status.dc_stream == DSI_DC_STREAM_ENABLE)
2467                 tegra_dsi_stop_dc_stream_at_frame_end(dc, dsi);
2468
2469         /* Disable dsi phy clock */
2470         if (dsi->status.clk_out == DSI_PHYCLK_OUT_EN)
2471                 tegra_dsi_hs_clk_out_disable(dc, dsi);
2472
2473         val = DSI_POWER_CONTROL_LEG_DSI_ENABLE(TEGRA_DSI_DISABLE);
2474         tegra_dsi_writel(dsi, val, DSI_POWER_CONTROL);
2475
2476         iounmap(dsi->base);
2477         release_resource(dsi->base_res);
2478
2479         clk_put(dsi->dc_clk);
2480         clk_put(dsi->dsi_clk);
2481
2482         mutex_unlock(&dsi->lock);
2483
2484         mutex_destroy(&dsi->lock);
2485         kfree(dsi);
2486 }
2487
2488 static int tegra_dsi_deep_sleep(struct tegra_dc *dc,
2489                                 struct tegra_dc_dsi_data *dsi)
2490 {
2491         int err = 0;
2492         int val;
2493         struct clk *parent_clk = NULL;
2494         struct clk *base_clk = NULL;
2495
2496         if (!dsi->enabled) {
2497                 err = -EPERM;
2498                 goto fail;
2499         }
2500
2501         err = tegra_dsi_set_to_lp_mode(dc, dsi, DSI_LP_OP_WRITE);
2502         if (err < 0) {
2503                 dev_err(&dc->ndev->dev,
2504                 "DSI failed to go to LP mode\n");
2505                 goto fail;
2506         }
2507
2508         /* Suspend panel */
2509         err = tegra_dsi_send_panel_cmd(dc, dsi,
2510                         dsi->info.dsi_suspend_cmd,
2511                         dsi->info.n_suspend_cmd);
2512         if (err < 0) {
2513                 dev_err(&dc->ndev->dev,
2514                         "dsi: Error sending suspend cmd\n");
2515                 goto fail;
2516         }
2517
2518         if (!dsi->ulpm) {
2519                 err = tegra_dsi_enter_ulpm(dsi);
2520                 if (err < 0) {
2521                         dev_err(&dc->ndev->dev,
2522                                 "DSI failed to enter ulpm\n");
2523                         goto fail;
2524                 }
2525         }
2526
2527         /* Suspend pad */
2528         val = tegra_dsi_readl(dsi, DSI_PAD_CONTROL);
2529         val = DSI_PAD_CONTROL_PAD_PDIO(0x3) |
2530                 DSI_PAD_CONTROL_PAD_PDIO_CLK(0x1) |
2531                 DSI_PAD_CONTROL_PAD_PULLDN_ENAB(TEGRA_DSI_ENABLE);
2532         tegra_dsi_writel(dsi, val, DSI_PAD_CONTROL);
2533
2534         /* Suspend core-logic */
2535         val = DSI_POWER_CONTROL_LEG_DSI_ENABLE(TEGRA_DSI_DISABLE);
2536         tegra_dsi_writel(dsi, val, DSI_POWER_CONTROL);
2537
2538         /* Disable dsi fast and slow clock */
2539         parent_clk = clk_get_parent(dsi->dsi_clk);
2540         base_clk = clk_get_parent(parent_clk);
2541         if (dsi->info.dsi_instance)
2542                 tegra_clk_cfg_ex(base_clk,
2543                                 TEGRA_CLK_PLLD_CSI_OUT_ENB,
2544                                 0);
2545         else
2546                 tegra_clk_cfg_ex(base_clk,
2547                                 TEGRA_CLK_PLLD_DSI_OUT_ENB,
2548                                 0);
2549
2550         /* Disable dsi source clock */
2551         clk_disable(dsi->dsi_clk);
2552
2553         dsi->clk_ref = false;
2554         dsi->enabled = false;
2555
2556         return 0;
2557 fail:
2558         return err;
2559 }
2560
2561 static void tegra_dc_dsi_disable(struct tegra_dc *dc)
2562 {
2563         int err;
2564         struct tegra_dc_dsi_data *dsi = tegra_dc_get_outdata(dc);
2565
2566         tegra_dc_io_start(dc);
2567         mutex_lock(&dsi->lock);
2568
2569         if (dsi->status.dc_stream == DSI_DC_STREAM_ENABLE)
2570                 tegra_dsi_stop_dc_stream_at_frame_end(dc, dsi);
2571
2572         if (dsi->info.power_saving_suspend) {
2573                 if (tegra_dsi_deep_sleep(dc, dsi) < 0) {
2574                         dev_err(&dc->ndev->dev,
2575                                 "DSI failed to enter deep sleep\n");
2576                         goto fail;
2577                 }
2578         } else {
2579                 if (dsi->info.dsi_early_suspend_cmd) {
2580                         err = tegra_dsi_send_panel_cmd(dc, dsi,
2581                                 dsi->info.dsi_early_suspend_cmd,
2582                                 dsi->info.n_early_suspend_cmd);
2583                         if (err < 0) {
2584                                 dev_err(&dc->ndev->dev,
2585                                 "dsi: Error sending early suspend cmd\n");
2586                                 goto fail;
2587                         }
2588                 }
2589
2590                 if (!dsi->ulpm) {
2591                         if (tegra_dsi_enter_ulpm(dsi) < 0) {
2592                                 dev_err(&dc->ndev->dev,
2593                                         "DSI failed to enter ulpm\n");
2594                                 goto fail;
2595                         }
2596                 }
2597         }
2598
2599 fail:
2600         mutex_unlock(&dsi->lock);
2601         tegra_dc_io_end(dc);
2602 }
2603
2604 #ifdef CONFIG_PM
2605 static void tegra_dc_dsi_suspend(struct tegra_dc *dc)
2606 {
2607         struct tegra_dc_dsi_data *dsi;
2608
2609         dsi = tegra_dc_get_outdata(dc);
2610
2611         if (!dsi->enabled)
2612                 return;
2613
2614         tegra_dc_io_start(dc);
2615         mutex_lock(&dsi->lock);
2616
2617         if (!dsi->info.power_saving_suspend) {
2618                 if (dsi->ulpm) {
2619                         if (tegra_dsi_exit_ulpm(dsi) < 0) {
2620                                 dev_err(&dc->ndev->dev,
2621                                         "DSI failed to exit ulpm");
2622                                 goto fail;
2623                         }
2624                 }
2625
2626                 if (tegra_dsi_deep_sleep(dc, dsi) < 0) {
2627                         dev_err(&dc->ndev->dev,
2628                                 "DSI failed to enter deep sleep\n");
2629                         goto fail;
2630                 }
2631         }
2632 fail:
2633         mutex_unlock(&dsi->lock);
2634         tegra_dc_io_end(dc);
2635 }
2636
2637 static void tegra_dc_dsi_resume(struct tegra_dc *dc)
2638 {
2639         /* Not required since tegra_dc_dsi_enable
2640          * will reconfigure the controller from scratch
2641          */
2642 }
2643 #endif
2644
2645 struct tegra_dc_out_ops tegra_dc_dsi_ops = {
2646         .init = tegra_dc_dsi_init,
2647         .destroy = tegra_dc_dsi_destroy,
2648         .enable = tegra_dc_dsi_enable,
2649         .disable = tegra_dc_dsi_disable,
2650 #ifdef CONFIG_PM
2651         .suspend = tegra_dc_dsi_suspend,
2652         .resume = tegra_dc_dsi_resume,
2653 #endif
2654 };