video: dsi: tegra: Support for dsi 2nd instance
[linux-2.6.git] / drivers / video / tegra / dc / dsi.c
1 /*
2  * drivers/video/tegra/dc/dsi.c
3  *
4  * Copyright (c) 2011, NVIDIA Corporation.
5  *
6  * This software is licensed under the terms of the GNU General Public
7  * License version 2, as published by the Free Software Foundation, and
8  * may be copied, distributed, and modified under those terms.
9  *
10  * This program is distributed in the hope that it will be useful,
11  * but WITHOUT ANY WARRANTY; without even the implied warranty of
12  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
13  * GNU General Public License for more details.
14  *
15  */
16
17 #include <linux/clk.h>
18 #include <linux/delay.h>
19 #include <linux/err.h>
20 #include <linux/fb.h>
21 #include <linux/gpio.h>
22 #include <linux/interrupt.h>
23 #include <linux/kernel.h>
24 #include <linux/slab.h>
25 #include <linux/spinlock.h>
26 #include <linux/workqueue.h>
27
28 #include <mach/clk.h>
29 #include <mach/dc.h>
30 #include <mach/fb.h>
31 #include <mach/nvhost.h>
32 #include <../gpio-names.h>
33
34 #include "dc_reg.h"
35 #include "dc_priv.h"
36 #include "dsi_regs.h"
37 #include "dsi.h"
38
39 #define DSI_USE_SYNC_POINTS 0
40
41
42 #define DSI_MODULE_NOT_INIT             0x0
43 #define DSI_MODULE_INIT                 0x1
44
45 #define DSI_LPHS_NOT_INIT               0x0
46 #define DSI_LPHS_IN_LP_MODE             0x1
47 #define DSI_LPHS_IN_HS_MODE             0x2
48
49 #define DSI_VIDEO_TYPE_NOT_INIT         0x0
50 #define DSI_VIDEO_TYPE_VIDEO_MODE       0x1
51 #define DSI_VIDEO_TYPE_CMD_MODE         0x2
52
53 #define DSI_DRIVEN_MODE_NOT_INIT        0x0
54 #define DSI_DRIVEN_MODE_DC              0x1
55 #define DSI_DRIVEN_MODE_HOST            0x2
56
57 #define DSI_PHYCLK_OUT_DIS              0x0
58 #define DSI_PHYCLK_OUT_EN               0x1
59
60 #define DSI_PHYCLK_NOT_INIT             0x0
61 #define DSI_PHYCLK_CONTINUOUS           0x1
62 #define DSI_PHYCLK_TX_ONLY              0x2
63
64 #define DSI_CLK_BURST_NOT_INIT          0x0
65 #define DSI_CLK_BURST_NONE_BURST        0x1
66 #define DSI_CLK_BURST_BURST_MODE        0x2
67
68 struct dsi_status {
69         unsigned        init:2;
70
71         unsigned        lphs:2;
72
73         unsigned        vtype:2;
74         unsigned        driven:2;
75
76         unsigned        clk_out:2;
77         unsigned        clk_mode:2;
78         unsigned        clk_burst:2;
79 };
80
81 /* source of video data */
82 enum{
83         TEGRA_DSI_DRIVEN_BY_DC,
84         TEGRA_DSI_DRIVEN_BY_HOST,
85 };
86
87 struct tegra_dc_dsi_data {
88         struct tegra_dc *dc;
89         void __iomem    *base;
90         struct resource *base_res;
91
92         struct clk              *dc_clk;
93         struct clk              *dsi_clk;
94
95         struct mutex    lock;
96
97         /* data from board info */
98         struct tegra_dsi_out info;
99
100         struct dsi_status       status;
101
102         u8              driven_mode;
103         u8              controller_index;
104
105         u8              pixel_scaler_mul;
106         u8              pixel_scaler_div;
107
108         u32             default_pixel_clk_khz;
109         u32             default_hs_clk_khz;
110
111         u32             target_hs_clk_khz;
112         u32             target_lp_clk_khz;
113
114         u16             current_bit_clk_ns;
115         u32             current_dsi_clk_khz;
116
117         u32             dsi_control_val;
118 };
119
120 const u32 dsi_pkt_seq_reg[NUMOF_PKT_SEQ] = {
121         DSI_PKT_SEQ_0_LO,
122         DSI_PKT_SEQ_0_HI,
123         DSI_PKT_SEQ_1_LO,
124         DSI_PKT_SEQ_1_HI,
125         DSI_PKT_SEQ_2_LO,
126         DSI_PKT_SEQ_2_HI,
127         DSI_PKT_SEQ_3_LO,
128         DSI_PKT_SEQ_3_HI,
129         DSI_PKT_SEQ_4_LO,
130         DSI_PKT_SEQ_4_HI,
131         DSI_PKT_SEQ_5_LO,
132         DSI_PKT_SEQ_5_HI,
133 };
134
135 const u32 dsi_pkt_seq_video_non_burst_syne[NUMOF_PKT_SEQ] = {
136         PKT_ID0(CMD_VS) | PKT_LEN0(0) | PKT_ID1(CMD_EOT) | PKT_LEN1(0) | PKT_LP,
137         0,
138         PKT_ID0(CMD_VE) | PKT_LEN0(0) | PKT_ID1(CMD_EOT) | PKT_LEN1(0) | PKT_LP,
139         0,
140         PKT_ID0(CMD_HS) | PKT_LEN0(0) | PKT_ID1(CMD_EOT) | PKT_LEN1(0) | PKT_LP,
141         0,
142         PKT_ID0(CMD_HS) | PKT_LEN0(0) | PKT_ID1(CMD_BLNK) | PKT_LEN1(1) |
143                 PKT_ID2(CMD_HE) | PKT_LEN2(0),
144         PKT_ID3(CMD_BLNK) | PKT_LEN3(2) | PKT_ID4(CMD_RGB) | PKT_LEN4(3) |
145                 PKT_ID5(CMD_BLNK) | PKT_LEN5(4),
146         PKT_ID0(CMD_HS) | PKT_LEN0(0) | PKT_ID1(CMD_EOT) | PKT_LEN1(0) | PKT_LP,
147         0,
148         PKT_ID0(CMD_HS) | PKT_LEN0(0) | PKT_ID1(CMD_BLNK) | PKT_LEN1(1) |
149                 PKT_ID2(CMD_HE) | PKT_LEN2(0),
150         PKT_ID3(CMD_BLNK) | PKT_LEN3(2) | PKT_ID4(CMD_RGB) | PKT_LEN4(3) |
151                 PKT_ID5(CMD_BLNK) | PKT_LEN5(4),
152 };
153
154 const u32 dsi_pkt_seq_video_non_burst[NUMOF_PKT_SEQ] = {
155         PKT_ID0(CMD_VS) | PKT_LEN0(0) | PKT_ID1(CMD_EOT) | PKT_LEN1(0) | PKT_LP,
156         0,
157         PKT_ID0(CMD_HS) | PKT_LEN0(0) | PKT_ID1(CMD_EOT) | PKT_LEN1(0) | PKT_LP,
158         0,
159         PKT_ID0(CMD_HS) | PKT_LEN0(0) | PKT_ID1(CMD_EOT) | PKT_LEN1(0) | PKT_LP,
160         0,
161         PKT_ID0(CMD_HS) | PKT_LEN0(0) | PKT_ID1(CMD_BLNK) | PKT_LEN1(2) |
162                 PKT_ID2(CMD_RGB) | PKT_LEN2(3),
163         PKT_ID3(CMD_BLNK) | PKT_LEN3(4),
164         PKT_ID0(CMD_HS) | PKT_LEN0(0) | PKT_ID1(CMD_EOT) | PKT_LEN1(0) | PKT_LP,
165         0,
166         PKT_ID0(CMD_HS) | PKT_LEN0(0) | PKT_ID1(CMD_BLNK) | PKT_LEN1(2) |
167                 PKT_ID2(CMD_RGB) | PKT_LEN2(3),
168         PKT_ID3(CMD_BLNK) | PKT_LEN3(4),
169 };
170
171 static const u32 dsi_pkt_seq_video_burst[NUMOF_PKT_SEQ] = {
172         PKT_ID0(CMD_NULL) | PKT_LEN0(4) | PKT_ID1(CMD_VS) | PKT_LEN1(0) |
173                 PKT_ID2(CMD_EOT) | PKT_LEN2(0) | PKT_LP,
174         0,
175         PKT_ID0(CMD_NULL) | PKT_LEN0(4) | PKT_ID1(CMD_HS) | PKT_LEN1(0) |
176                 PKT_ID2(CMD_EOT) | PKT_LEN2(0) | PKT_LP,
177         0,
178         PKT_ID0(CMD_NULL) | PKT_LEN0(4) | PKT_ID1(CMD_HS) | PKT_LEN1(0) |
179                 PKT_ID2(CMD_EOT) | PKT_LEN2(0) | PKT_LP,
180         PKT_ID0(CMD_BLNK) | PKT_LEN0(4) | PKT_ID1(CMD_HS) | PKT_LEN1(0) |
181                 PKT_ID2(CMD_BLNK) | PKT_LEN2(2),
182         PKT_ID3(CMD_RGB) | PKT_LEN3(3) | PKT_ID4(CMD_EOT) | PKT_LEN4(0),
183         PKT_ID0(CMD_NULL) | PKT_LEN0(4) | PKT_ID1(CMD_HS) | PKT_LEN1(0) |
184                 PKT_ID2(CMD_EOT) | PKT_LEN2(0) | PKT_LP,
185         0,
186         PKT_ID0(CMD_BLNK) | PKT_LEN0(4) | PKT_ID1(CMD_HS) | PKT_LEN1(0) |
187                 PKT_ID2(CMD_BLNK) | PKT_LEN2(2),
188         PKT_ID3(CMD_RGB) | PKT_LEN3(3) | PKT_ID4(CMD_EOT) | PKT_LEN4(0),
189 };
190
191 /* TODO: verify with hw about this format */
192 const u32 dsi_pkt_seq_cmd_mode [NUMOF_PKT_SEQ] = {
193         0,
194         0,
195         0,
196         0,
197         0,
198         0,
199         PKT_ID0(CMD_LONGW) | PKT_LEN0(3) | PKT_ID1(CMD_EOT) | PKT_LEN1(7),
200         0,
201         0,
202         0,
203         PKT_ID0(CMD_LONGW) | PKT_LEN0(3) | PKT_ID1(CMD_EOT) | PKT_LEN1(7),
204         0,
205 };
206
207 const u32 init_reg[] = {
208         DSI_WR_DATA,
209         DSI_INT_ENABLE,
210         DSI_INT_STATUS,
211         DSI_INT_MASK,
212         DSI_INIT_SEQ_DATA_0,
213         DSI_INIT_SEQ_DATA_1,
214         DSI_INIT_SEQ_DATA_2,
215         DSI_INIT_SEQ_DATA_3,
216         DSI_DCS_CMDS,
217         DSI_PKT_SEQ_0_LO,
218         DSI_PKT_SEQ_1_LO,
219         DSI_PKT_SEQ_2_LO,
220         DSI_PKT_SEQ_3_LO,
221         DSI_PKT_SEQ_4_LO,
222         DSI_PKT_SEQ_5_LO,
223         DSI_PKT_SEQ_0_HI,
224         DSI_PKT_SEQ_1_HI,
225         DSI_PKT_SEQ_2_HI,
226         DSI_PKT_SEQ_3_HI,
227         DSI_PKT_SEQ_4_HI,
228         DSI_PKT_SEQ_5_HI,
229         DSI_CONTROL,
230         DSI_HOST_DSI_CONTROL,
231         DSI_PAD_CONTROL,
232         DSI_PAD_CONTROL_CD,
233         DSI_SOL_DELAY,
234         DSI_MAX_THRESHOLD,
235         DSI_TRIGGER,
236         DSI_TX_CRC,
237         DSI_INIT_SEQ_CONTROL,
238         DSI_PKT_LEN_0_1,
239         DSI_PKT_LEN_2_3,
240         DSI_PKT_LEN_4_5,
241         DSI_PKT_LEN_6_7,
242 };
243
244 static inline unsigned long tegra_dsi_readl(struct tegra_dc_dsi_data *dsi,
245                                                                         u32 reg)
246 {
247         return readl(dsi->base + reg * 4);
248 }
249
250 static inline void tegra_dsi_writel(struct tegra_dc_dsi_data *dsi,u32 val,
251                                                                         u32 reg)
252 {
253         writel(val, dsi->base + reg * 4);
254 }
255
256 static u32 tegra_dsi_get_hs_clk_rate(struct tegra_dc_dsi_data *dsi)
257 {
258         u32 dsi_clock_rate_khz;
259
260         switch (dsi->info.video_burst_mode) {
261         case TEGRA_DSI_VIDEO_BURST_MODE_LOW_SPEED:
262         case TEGRA_DSI_VIDEO_BURST_MODE_MEDIUM_SPEED:
263         case TEGRA_DSI_VIDEO_BURST_MODE_FAST_SPEED:
264         case TEGRA_DSI_VIDEO_BURST_MODE_FASTEST_SPEED:
265                 /* TODO: implement algo for these speed rate */
266
267         case TEGRA_DSI_VIDEO_BURST_MODE_MANUAL:
268                 if (dsi->info.burst_mode_freq_khz) {
269                         dsi_clock_rate_khz = dsi->info.burst_mode_freq_khz;
270                         break;
271                 }
272         case TEGRA_DSI_VIDEO_NONE_BURST_MODE:
273         case TEGRA_DSI_VIDEO_NONE_BURST_MODE_WITH_SYNC_END:
274         case TEGRA_DSI_VIDEO_BURST_MODE_LOWEST_SPEED:
275         default:
276                 dsi_clock_rate_khz = dsi->default_hs_clk_khz;
277                 break;
278         }
279
280         return dsi_clock_rate_khz;
281 }
282
283 static u32 tegra_dsi_get_lp_clk_rate(struct tegra_dc_dsi_data *dsi)
284 {
285         u32 dsi_clock_rate_khz;
286
287         if (dsi->info.enable_hs_clock_on_lp_cmd_mode)
288                 if (dsi->info.hs_clk_in_lp_cmd_mode_freq_khz)
289                         dsi_clock_rate_khz =
290                                 dsi->info.hs_clk_in_lp_cmd_mode_freq_khz;
291                 else
292                         dsi_clock_rate_khz = tegra_dsi_get_hs_clk_rate(dsi);
293         else
294                 dsi_clock_rate_khz = dsi->info.lp_cmd_mode_freq_khz;
295
296         return dsi_clock_rate_khz;
297 }
298
299 static void tegra_dsi_init_sw(struct tegra_dc *dc,
300                                                 struct tegra_dc_dsi_data *dsi)
301 {
302         u32 h_width_pixels;
303         u32 v_width_lines;
304         u32 pixel_clk_hz;
305         u32 byte_clk_hz;
306
307         switch (dsi->info.pixel_format) {
308                 case TEGRA_DSI_PIXEL_FORMAT_16BIT_P:
309                         /* 2 bytes per pixel */
310                         dsi->pixel_scaler_mul = 2;
311                         dsi->pixel_scaler_div = 1;
312                         break;
313                 case TEGRA_DSI_PIXEL_FORMAT_18BIT_P:
314                         /* 2.25 bytes per pixel */
315                         dsi->pixel_scaler_mul = 9;
316                         dsi->pixel_scaler_div = 4;
317                         break;
318                 case TEGRA_DSI_PIXEL_FORMAT_18BIT_NP:
319                 case TEGRA_DSI_PIXEL_FORMAT_24BIT_P:
320                         /* 3 bytes per pixel */
321                         dsi->pixel_scaler_mul = 3;
322                         dsi->pixel_scaler_div = 1;
323                         break;
324                 default:
325                         break;
326         }
327
328         h_width_pixels = dc->mode.h_back_porch + dc->mode.h_front_porch +
329                         dc->mode.h_sync_width + dc->mode.h_active;
330         v_width_lines = dc->mode.v_back_porch + dc->mode.v_front_porch +
331                         dc->mode.v_sync_width + dc->mode.v_active;
332
333         /* The slowest pixel rate that is required */
334         /*   for the given display timing       */
335         pixel_clk_hz = h_width_pixels * v_width_lines * dsi->info.refresh_rate;
336
337         /* Pixel byte rate on DSI interface */
338         byte_clk_hz     = (pixel_clk_hz * dsi->pixel_scaler_mul) /
339                         (dsi->pixel_scaler_div * dsi->info.n_data_lanes);
340
341         dsi->default_pixel_clk_khz = pixel_clk_hz / 1000;
342
343         printk("dsi: default pixel rate %d khz\n", dsi->default_pixel_clk_khz);
344
345         /*
346          * Pixel bit rate on DSI. Since DSI interface is double data rate (
347          * transferring data on both rising and falling edge of clk), div by 2
348          * to get the actual clock rate.
349          */
350         dsi->default_hs_clk_khz =
351                         (byte_clk_hz * NUMOF_BIT_PER_BYTE) / (1000 * 2);
352
353         dsi->controller_index = dc->ndev->id;
354
355         dsi->dsi_control_val =
356                         DSI_CONTROL_VIRTUAL_CHANNEL(dsi->info.virtual_channel) |
357                         DSI_CONTROL_NUM_DATA_LANES(dsi->info.n_data_lanes - 1) |
358                         DSI_CONTROL_VID_SOURCE(dsi->controller_index) |
359                         DSI_CONTROL_DATA_FORMAT(dsi->info.pixel_format);
360
361         dsi->target_lp_clk_khz = tegra_dsi_get_lp_clk_rate(dsi);
362         dsi->target_hs_clk_khz = tegra_dsi_get_hs_clk_rate(dsi);
363
364         /*
365          * Force video clock to be continuous mode if
366          * enable_hs_clock_on_lp_cmd_mode is set
367          */
368         if (dsi->info.enable_hs_clock_on_lp_cmd_mode) {
369                 if (dsi->info.video_clock_mode != TEGRA_DSI_VIDEO_CLOCK_CONTINUOUS)
370                         printk("Force to clock continuous mode\n");
371
372                 dsi->info.video_clock_mode = TEGRA_DSI_VIDEO_CLOCK_CONTINUOUS;
373         }
374
375 }
376
377 static void tegra_dsi_get_phy_timing(struct tegra_dc_dsi_data *dsi,
378                                 struct dsi_phy_timing_inclk *phy_timing_clk,
379                                 u32 clk_ns)
380 {
381
382         phy_timing_clk->t_hsdexit = dsi->info.phy_timing.t_hsdexit_ns ?
383                         (dsi->info.phy_timing.t_hsdexit_ns / clk_ns) :
384                         (T_HSEXIT_DEFAULT(clk_ns));
385
386         phy_timing_clk->t_hstrail = dsi->info.phy_timing.t_hstrail_ns ?
387                         (dsi->info.phy_timing.t_hstrail_ns / clk_ns) :
388                         (T_HSTRAIL_DEFAULT(clk_ns));
389
390         phy_timing_clk->t_datzero = dsi->info.phy_timing.t_datzero_ns ?
391                         (dsi->info.phy_timing.t_datzero_ns / clk_ns) :
392                         (T_DATZERO_DEFAULT(clk_ns));
393
394         phy_timing_clk->t_hsprepr = dsi->info.phy_timing.t_hsprepr_ns ?
395                         (dsi->info.phy_timing.t_hsprepr_ns / clk_ns) :
396                         (T_HSPREPR_DEFAULT(clk_ns));
397
398         phy_timing_clk->t_clktrail = dsi->info.phy_timing.t_clktrail_ns ?
399                                 (dsi->info.phy_timing.t_clktrail_ns / clk_ns) :
400                                 (T_CLKTRAIL_DEFAULT(clk_ns));
401
402         phy_timing_clk->t_clkpost = dsi->info.phy_timing.t_clkpost_ns ?
403                                 (dsi->info.phy_timing.t_clkpost_ns / clk_ns) :
404                                 (T_CLKPOST_DEFAULT(clk_ns));
405
406         phy_timing_clk->t_clkzero = dsi->info.phy_timing.t_clkzero_ns ?
407                                 (dsi->info.phy_timing.t_clkzero_ns / clk_ns) :
408                                 (T_CLKZERO_DEFAULT(clk_ns));
409
410         phy_timing_clk->t_tlpx = dsi->info.phy_timing.t_tlpx_ns ?
411                                 (dsi->info.phy_timing.t_tlpx_ns / clk_ns) :
412                                 (T_TLPX_DEFAULT(clk_ns));
413
414         phy_timing_clk->t_clkpre = T_CLKPRE_DEFAULT(clk_ns);
415         phy_timing_clk->t_clkprepare = T_CLKPREPARE_DEFAULT(clk_ns);
416         phy_timing_clk->t_wakeup = T_WAKEUP_DEFAULT(clk_ns);
417
418         phy_timing_clk->t_taget = 5 * phy_timing_clk->t_tlpx;
419         phy_timing_clk->t_tasure = 2 * phy_timing_clk->t_tlpx;
420         phy_timing_clk->t_tago = 4 * phy_timing_clk->t_tlpx;
421 }
422
423 static void tegra_dsi_set_phy_timing(struct tegra_dc_dsi_data *dsi)
424 {
425         u32 val;
426         struct dsi_phy_timing_inclk     phy_timing;
427
428         tegra_dsi_get_phy_timing(dsi, &phy_timing, dsi->current_bit_clk_ns);
429
430         val = DSI_PHY_TIMING_0_THSDEXIT(phy_timing.t_hsdexit) |
431                         DSI_PHY_TIMING_0_THSTRAIL(phy_timing.t_hstrail) |
432                         DSI_PHY_TIMING_0_TDATZERO(phy_timing.t_datzero) |
433                         DSI_PHY_TIMING_0_THSPREPR(phy_timing.t_hsprepr);
434         tegra_dsi_writel(dsi, val, DSI_PHY_TIMING_0);
435
436         val = DSI_PHY_TIMING_1_TCLKTRAIL(phy_timing.t_clktrail) |
437                         DSI_PHY_TIMING_1_TCLKPOST(phy_timing.t_clkpost) |
438                         DSI_PHY_TIMING_1_TCLKZERO(phy_timing.t_clkzero) |
439                         DSI_PHY_TIMING_1_TTLPX(phy_timing.t_tlpx);
440         tegra_dsi_writel(dsi, val, DSI_PHY_TIMING_1);
441
442         val = DSI_PHY_TIMING_2_TCLKPREPARE(phy_timing.t_clkprepare) |
443                 DSI_PHY_TIMING_2_TCLKPRE(phy_timing.t_clkpre) |
444                         DSI_PHY_TIMING_2_TWAKEUP(phy_timing.t_wakeup);
445         tegra_dsi_writel(dsi, val, DSI_PHY_TIMING_2);
446
447         val = DSI_BTA_TIMING_TTAGET(phy_timing.t_taget) |
448                         DSI_BTA_TIMING_TTASURE(phy_timing.t_tasure) |
449                         DSI_BTA_TIMING_TTAGO(phy_timing.t_tago);
450         tegra_dsi_writel(dsi, val, DSI_BTA_TIMING);
451 }
452
453 static u32 tegra_dsi_sol_delay_burst(struct tegra_dc *dc,
454                                                 struct tegra_dc_dsi_data *dsi)
455 {
456         u32 dsi_to_pixel_clk_ratio;
457         u32 temp;
458         u32 temp1;
459         u32 mipi_clk_adj_kHz;
460         u32 sol_delay;
461         struct tegra_dc_mode *dc_modes = &dc->mode;
462
463         /* Get Fdsi/Fpixel ration (note: Fdsi si in bit format) */
464         dsi_to_pixel_clk_ratio = (dsi->current_dsi_clk_khz * 2 +
465                 dsi->default_pixel_clk_khz - 1) / dsi->default_pixel_clk_khz;
466
467         /* Convert Fdsi to byte format */
468         dsi_to_pixel_clk_ratio *= 1000/8;
469
470         /* Multiplying by 1000 so that we don't loose the fraction part */
471         temp = dc_modes->h_active * 1000;
472         temp1 = dc_modes->h_active + dc_modes->h_back_porch +
473                         dc_modes->h_sync_width;
474
475         sol_delay = temp1 * dsi_to_pixel_clk_ratio -
476                         temp * dsi->pixel_scaler_mul /
477                         (dsi->pixel_scaler_div * dsi->info.n_data_lanes);
478
479         /* Do rounding on sol delay */
480         sol_delay = (sol_delay + 1000 - 1)/1000;
481
482         /* TODO:
483          * 1. find out the correct sol fifo depth to use
484          * 2. verify with hw about the clamping function
485          */
486         if (sol_delay > (480 * 4)) {
487                 sol_delay = (480 * 4);
488                 mipi_clk_adj_kHz = sol_delay +
489                         (dc_modes->h_active * dsi->pixel_scaler_mul) /
490                         (dsi->info.n_data_lanes * dsi->pixel_scaler_div);
491
492                 mipi_clk_adj_kHz *= (dsi->default_pixel_clk_khz / temp1);
493
494                 mipi_clk_adj_kHz *= 4;
495         }
496
497         dsi->target_hs_clk_khz = mipi_clk_adj_kHz;
498
499         return sol_delay;
500 }
501
502 static void tegra_dsi_set_sol_delay(struct tegra_dc *dc,
503                                                 struct tegra_dc_dsi_data *dsi)
504 {
505         u32 sol_delay;
506
507         if (dsi->info.video_burst_mode == TEGRA_DSI_VIDEO_NONE_BURST_MODE ||
508                 dsi->info.video_burst_mode ==
509                                 TEGRA_DSI_VIDEO_NONE_BURST_MODE_WITH_SYNC_END) {
510                 sol_delay = NUMOF_BIT_PER_BYTE * dsi->pixel_scaler_mul /
511                         (dsi->pixel_scaler_div * dsi->info.n_data_lanes);
512                 dsi->status.clk_burst = DSI_CLK_BURST_NONE_BURST;
513         } else {
514                 sol_delay = tegra_dsi_sol_delay_burst(dc, dsi);
515                 dsi->status.clk_burst = DSI_CLK_BURST_BURST_MODE;
516         }
517
518         tegra_dsi_writel(dsi, DSI_SOL_DELAY_SOL_DELAY(sol_delay),
519                                                                 DSI_SOL_DELAY);
520 }
521
522 static void tegra_dsi_set_timeout(struct tegra_dc_dsi_data *dsi)
523 {
524         u32 val;
525         u32 bytes_per_frame;
526         u32 timeout = 0;
527
528         /* TODO: verify the following eq */
529         bytes_per_frame = dsi->current_dsi_clk_khz * 1000 * 2 /
530                                                 (dsi->info.refresh_rate * 8);
531         timeout = bytes_per_frame / DSI_CYCLE_COUNTER_VALUE;
532         timeout = (timeout + DSI_HTX_TO_MARGIN) & 0xffff;
533
534         val = DSI_TIMEOUT_0_LRXH_TO(DSI_LRXH_TO_VALUE) |
535                         DSI_TIMEOUT_0_HTX_TO(timeout);
536         tegra_dsi_writel(dsi, val, DSI_TIMEOUT_0);
537
538         if (dsi->info.panel_reset_timeout_msec)
539                 timeout = (dsi->info.panel_reset_timeout_msec * 1000*1000)
540                                         / dsi->current_bit_clk_ns;
541         else
542                 timeout = DSI_PR_TO_VALUE;
543
544         val = DSI_TIMEOUT_1_PR_TO(timeout) |
545                 DSI_TIMEOUT_1_TA_TO(DSI_TA_TO_VALUE);
546         tegra_dsi_writel(dsi, val, DSI_TIMEOUT_1);
547
548         val = DSI_TO_TALLY_P_RESET_STATUS(IN_RESET) |
549                 DSI_TO_TALLY_TA_TALLY(DSI_TA_TALLY_VALUE)|
550                 DSI_TO_TALLY_LRXH_TALLY(DSI_LRXH_TALLY_VALUE)|
551                 DSI_TO_TALLY_HTX_TALLY(DSI_HTX_TALLY_VALUE);
552         tegra_dsi_writel(dsi, val, DSI_TO_TALLY);
553 }
554
555 static void tegra_dsi_setup_video_mode_pkt_length(struct tegra_dc *dc,
556                                                 struct tegra_dc_dsi_data *dsi)
557 {
558         u32 val;
559         u32 hact_pkt_len;
560         u32 hsa_pkt_len;
561         u32 hbp_pkt_len;
562         u32 hfp_pkt_len;
563
564         hact_pkt_len = dc->mode.h_active * dsi->pixel_scaler_mul /
565                                                         dsi->pixel_scaler_div;
566         hsa_pkt_len = dc->mode.h_sync_width * dsi->pixel_scaler_mul /
567                                                         dsi->pixel_scaler_div;
568         hbp_pkt_len = dc->mode.h_back_porch * dsi->pixel_scaler_mul /
569                                                         dsi->pixel_scaler_div;
570         hfp_pkt_len = dc->mode.h_front_porch * dsi->pixel_scaler_mul /
571                                                         dsi->pixel_scaler_div;
572
573         if (dsi->info.video_burst_mode !=
574                                 TEGRA_DSI_VIDEO_NONE_BURST_MODE_WITH_SYNC_END)
575                 hbp_pkt_len += hsa_pkt_len;
576
577         hsa_pkt_len -= DSI_HSYNC_BLNK_PKT_OVERHEAD;
578         hbp_pkt_len -= DSI_HBACK_PORCH_PKT_OVERHEAD;
579         hfp_pkt_len -= DSI_HFRONT_PORCH_PKT_OVERHEAD;
580
581         val = DSI_PKT_LEN_0_1_LENGTH_0(0) | DSI_PKT_LEN_0_1_LENGTH_1(hsa_pkt_len);
582         tegra_dsi_writel(dsi, val, DSI_PKT_LEN_0_1);
583
584         val = DSI_PKT_LEN_2_3_LENGTH_2(hbp_pkt_len) |
585                         DSI_PKT_LEN_2_3_LENGTH_3(hact_pkt_len);
586         tegra_dsi_writel(dsi, val, DSI_PKT_LEN_2_3);
587
588         val = DSI_PKT_LEN_4_5_LENGTH_4(hfp_pkt_len) | DSI_PKT_LEN_4_5_LENGTH_5(0);
589         tegra_dsi_writel(dsi, val, DSI_PKT_LEN_4_5);
590
591         val = DSI_PKT_LEN_6_7_LENGTH_6(0) | DSI_PKT_LEN_6_7_LENGTH_7(0);
592         tegra_dsi_writel(dsi, val, DSI_PKT_LEN_6_7);
593 }
594
595 static void tegra_dsi_setup_cmd_mode_pkt_length(struct tegra_dc *dc,
596                                                 struct tegra_dc_dsi_data *dsi)
597 {
598         unsigned long   val;
599         unsigned long   act_bytes;
600
601         act_bytes = dc->mode.h_active * dsi->pixel_scaler_mul /
602                         dsi->pixel_scaler_div + 1;
603
604         val = DSI_PKT_LEN_0_1_LENGTH_0(0) | DSI_PKT_LEN_0_1_LENGTH_1(0);
605         tegra_dsi_writel(dsi, val, DSI_PKT_LEN_0_1);
606
607         val = DSI_PKT_LEN_2_3_LENGTH_2(0) | DSI_PKT_LEN_2_3_LENGTH_3(act_bytes);
608         tegra_dsi_writel(dsi, val, DSI_PKT_LEN_2_3);
609
610         val = DSI_PKT_LEN_4_5_LENGTH_4(0) | DSI_PKT_LEN_4_5_LENGTH_5(act_bytes);
611         tegra_dsi_writel(dsi, val, DSI_PKT_LEN_4_5);
612
613         val = DSI_PKT_LEN_6_7_LENGTH_6(0) | DSI_PKT_LEN_6_7_LENGTH_7(0x0f0f);
614         tegra_dsi_writel(dsi, val, DSI_PKT_LEN_6_7);
615 }
616
617 static void tegra_dsi_set_pkt_length(struct tegra_dc *dc,
618                                                 struct tegra_dc_dsi_data *dsi)
619 {
620         if (dsi->driven_mode == TEGRA_DSI_DRIVEN_BY_HOST)
621                 return;
622
623         if (dsi->info.video_data_type == TEGRA_DSI_VIDEO_TYPE_VIDEO_MODE)
624                 tegra_dsi_setup_video_mode_pkt_length(dc, dsi);
625         else
626                 tegra_dsi_setup_cmd_mode_pkt_length(dc, dsi);
627 }
628
629 static void tegra_dsi_set_pkt_seq(struct tegra_dc *dc,
630                                                 struct tegra_dc_dsi_data *dsi)
631 {
632         const u32 *pkt_seq;
633         u32 rgb_info;
634         u32 pkt_seq_3_5_rgb_lo;
635         u32 pkt_seq_3_5_rgb_hi;
636         u32     val;
637         u32 reg;
638         u8  i;
639
640         if (dsi->driven_mode == TEGRA_DSI_DRIVEN_BY_HOST)
641                 return;
642
643         switch(dsi->info.pixel_format) {
644         case TEGRA_DSI_PIXEL_FORMAT_16BIT_P:
645                 rgb_info = CMD_RGB_16BPP;
646                 break;
647         case TEGRA_DSI_PIXEL_FORMAT_18BIT_P:
648                 rgb_info = CMD_RGB_18BPP;
649                 break;
650         case TEGRA_DSI_PIXEL_FORMAT_18BIT_NP:
651                 rgb_info = CMD_RGB_18BPPNP;
652                 break;
653         case TEGRA_DSI_PIXEL_FORMAT_24BIT_P:
654         default:
655                 rgb_info = CMD_RGB_24BPP;
656                 break;
657         }
658
659         pkt_seq_3_5_rgb_lo = 0;
660         pkt_seq_3_5_rgb_hi = 0;
661         if (dsi->info.video_data_type == TEGRA_DSI_VIDEO_TYPE_COMMAND_MODE)
662                 pkt_seq = dsi_pkt_seq_cmd_mode;
663         else {
664                 switch (dsi->info.video_burst_mode) {
665                 case TEGRA_DSI_VIDEO_BURST_MODE_LOWEST_SPEED:
666                 case TEGRA_DSI_VIDEO_BURST_MODE_LOW_SPEED:
667                 case TEGRA_DSI_VIDEO_BURST_MODE_MEDIUM_SPEED:
668                 case TEGRA_DSI_VIDEO_BURST_MODE_FAST_SPEED:
669                 case TEGRA_DSI_VIDEO_BURST_MODE_FASTEST_SPEED:
670                 case TEGRA_DSI_VIDEO_BURST_MODE_MANUAL:
671                         pkt_seq_3_5_rgb_hi = DSI_PKT_SEQ_3_HI_PKT_33_ID(rgb_info);
672                         pkt_seq = dsi_pkt_seq_video_burst;
673                         break;
674                 case TEGRA_DSI_VIDEO_NONE_BURST_MODE_WITH_SYNC_END:
675                         pkt_seq_3_5_rgb_hi = DSI_PKT_SEQ_3_HI_PKT_34_ID(rgb_info);
676                         pkt_seq = dsi_pkt_seq_video_non_burst_syne;
677                         break;
678                 case TEGRA_DSI_VIDEO_NONE_BURST_MODE:
679                 default:
680                         pkt_seq_3_5_rgb_lo = DSI_PKT_SEQ_3_LO_PKT_32_ID(rgb_info);
681                         pkt_seq = dsi_pkt_seq_video_non_burst;
682                         break;
683                 }
684         }
685
686         for (i = 0; i < NUMOF_PKT_SEQ; i++) {
687                 val = pkt_seq[i];
688                 reg = dsi_pkt_seq_reg[i];
689                 if ((reg == DSI_PKT_SEQ_3_LO) || (reg == DSI_PKT_SEQ_5_LO))
690                         val |= pkt_seq_3_5_rgb_lo;
691                 if ((reg == DSI_PKT_SEQ_3_HI) || (reg == DSI_PKT_SEQ_5_HI))
692                         val |= pkt_seq_3_5_rgb_hi;
693                 tegra_dsi_writel(dsi, val, reg);
694         }
695 }
696
697 static void tegra_dsi_stop_dc_stream(struct tegra_dc *dc,
698                                                 struct tegra_dc_dsi_data *dsi)
699 {
700         /*
701          * TODO: It is possible that we are in the middle of video stream,
702          * Add code to wait for vsync and then stop DC from sending data to dsi
703          */
704         tegra_dc_writel(dc, 0, DC_DISP_DISP_WIN_OPTIONS);
705 }
706
707 static void tegra_dsi_start_dc_stream(struct tegra_dc *dc,
708                                                 struct tegra_dc_dsi_data *dsi)
709 {
710         u32 val;
711         tegra_dc_writel(dc, DSI_ENABLE, DC_DISP_DISP_WIN_OPTIONS);
712
713         /* TODO: clean up */
714         val = PIN_INPUT_LSPI_INPUT_EN;
715         tegra_dc_writel(dc, val, DC_COM_PIN_INPUT_ENABLE3);
716
717         val = PIN_OUTPUT_LSPI_OUTPUT_DIS;
718         tegra_dc_writel(dc, val, DC_COM_PIN_OUTPUT_ENABLE3);
719
720         tegra_dc_writel(dc, PW0_ENABLE | PW1_ENABLE | PW2_ENABLE | PW3_ENABLE |
721                         PW4_ENABLE | PM0_ENABLE | PM1_ENABLE,
722                         DC_CMD_DISPLAY_POWER_CONTROL);
723
724         val = MSF_POLARITY_HIGH | MSF_ENABLE | MSF_LSPI;
725         tegra_dc_writel(dc, val, DC_CMD_DISPLAY_COMMAND_OPTION0);
726
727
728         /* TODO: using continuous video mode for now */
729         /* if (dsi->info.panel_has_frame_buffer) {*/
730         if (0) {
731                 tegra_dc_writel(dc, DISP_CTRL_MODE_NC_DISPLAY, DC_CMD_DISPLAY_COMMAND);
732                 tegra_dc_writel(dc, GENERAL_UPDATE, DC_CMD_STATE_CONTROL);
733                 val = GENERAL_ACT_REQ | NC_HOST_TRIG;
734                 tegra_dc_writel(dc, val, DC_CMD_STATE_CONTROL);
735         } else {
736                 tegra_dc_writel(dc, DISP_CTRL_MODE_C_DISPLAY, DC_CMD_DISPLAY_COMMAND);
737                 tegra_dc_writel(dc, GENERAL_ACT_REQ << 8, DC_CMD_STATE_CONTROL);
738                 tegra_dc_writel(dc, GENERAL_ACT_REQ, DC_CMD_STATE_CONTROL);
739         }
740 }
741
742 static void tegra_dsi_set_dc_clk(struct tegra_dc *dc,
743                                                 struct tegra_dc_dsi_data *dsi)
744 {
745         u32 shift_clk_div;
746         u32 val;
747
748         if (dsi->info.video_burst_mode == TEGRA_DSI_VIDEO_NONE_BURST_MODE ||
749                 dsi->info.video_burst_mode ==
750                                 TEGRA_DSI_VIDEO_NONE_BURST_MODE_WITH_SYNC_END)
751                 shift_clk_div = NUMOF_BIT_PER_BYTE * dsi->pixel_scaler_mul /
752                         (dsi->pixel_scaler_div * dsi->info.n_data_lanes) - 2;
753         else
754                 shift_clk_div = (dsi->current_dsi_clk_khz * 2 +
755                                                 dsi->default_hs_clk_khz - 1) /
756                                                 (dsi->default_hs_clk_khz) - 2;
757
758 #ifdef CONFIG_TEGRA_FPGA_PLATFORM
759         shift_clk_div = 1;
760 #endif
761
762         /* TODO: find out if PCD3 option is required */
763         val = PIXEL_CLK_DIVIDER_PCD1 | SHIFT_CLK_DIVIDER(shift_clk_div);
764         tegra_dc_writel(dc, val, DC_DISP_DISP_CLOCK_CONTROL);
765
766         clk_enable(dsi->dc_clk);
767 }
768
769 static void tegra_dsi_set_dsi_clk(struct tegra_dc *dc,
770                                         struct tegra_dc_dsi_data *dsi, u32 clk)
771 {
772         u32 rm;
773
774         rm = clk % 1000;
775         if (rm != 0)
776                 clk -= rm;
777
778         clk *= 2;       /* Value for PLLD routine is required to be twice as */
779                         /* the desired clock rate */
780
781         dc->mode.pclk = clk*1000;
782         tegra_dc_setup_clk(dc, dsi->dsi_clk);
783         clk_enable(dsi->dsi_clk);
784         tegra_periph_reset_deassert(dsi->dsi_clk);
785
786         dsi->current_dsi_clk_khz = clk_get_rate(dsi->dsi_clk) / 1000;
787
788         dsi->current_bit_clk_ns =  1000*1000 / (dsi->current_dsi_clk_khz * 2);
789 }
790
791 static void tegra_dsi_hs_clk_out_enable(struct tegra_dc_dsi_data *dsi)
792 {
793         u32 val;
794
795         val = tegra_dsi_readl(dsi, DSI_CONTROL);
796         val &= ~DSI_CONTROL_HS_CLK_CTRL(1);
797
798         if (dsi->info.video_clock_mode == TEGRA_DSI_VIDEO_CLOCK_CONTINUOUS) {
799                 val |= DSI_CONTROL_HS_CLK_CTRL(CONTINUOUS);
800                 dsi->status.clk_mode = DSI_PHYCLK_CONTINUOUS;
801         } else {
802                 val |= DSI_CONTROL_HS_CLK_CTRL(TX_ONLY);
803                 dsi->status.clk_mode = DSI_PHYCLK_TX_ONLY;
804         }
805         tegra_dsi_writel(dsi, val, DSI_CONTROL);
806
807         val = tegra_dsi_readl(dsi, DSI_HOST_DSI_CONTROL);
808         val &= ~DSI_HOST_DSI_CONTROL_HIGH_SPEED_TRANS(1);
809         val |= DSI_HOST_DSI_CONTROL_HIGH_SPEED_TRANS(TEGRA_DSI_HIGH);
810         tegra_dsi_writel(dsi, val, DSI_HOST_DSI_CONTROL);
811
812         dsi->status.clk_out = DSI_PHYCLK_OUT_EN;
813 }
814
815 static void tegra_dsi_hs_clk_out_enable_in_lp(struct tegra_dc_dsi_data *dsi)
816 {
817         u32 val;
818         tegra_dsi_hs_clk_out_enable(dsi);
819
820         val = tegra_dsi_readl(dsi, DSI_HOST_DSI_CONTROL);
821         val &= ~DSI_HOST_DSI_CONTROL_HIGH_SPEED_TRANS(1);
822         val |= DSI_HOST_DSI_CONTROL_HIGH_SPEED_TRANS(TEGRA_DSI_LOW);
823         tegra_dsi_writel(dsi, val, DSI_HOST_DSI_CONTROL);
824 }
825
826 static void tegra_dsi_hs_clk_out_disable(struct tegra_dc *dc,
827                                                 struct tegra_dc_dsi_data *dsi)
828 {
829         u32 val;
830
831         if (dsi->status.driven == DSI_DRIVEN_MODE_DC)
832                 tegra_dsi_stop_dc_stream(dc, dsi);
833
834         val = tegra_dsi_readl(dsi, DSI_CONTROL);
835         val &= ~DSI_CONTROL_HS_CLK_CTRL(1);
836         val |= DSI_CONTROL_HS_CLK_CTRL(TX_ONLY);
837         tegra_dsi_writel(dsi, val, DSI_CONTROL);
838
839         /* TODO: issue a cmd */
840
841         val = tegra_dsi_readl(dsi, DSI_HOST_DSI_CONTROL);
842         val &= ~DSI_HOST_DSI_CONTROL_HIGH_SPEED_TRANS(1);
843         val |= DSI_HOST_DSI_CONTROL_HIGH_SPEED_TRANS(TEGRA_DSI_LOW);
844         tegra_dsi_writel(dsi, val, DSI_HOST_DSI_CONTROL);
845
846         dsi->status.clk_mode = DSI_PHYCLK_NOT_INIT;
847         dsi->status.clk_out = DSI_PHYCLK_OUT_DIS;
848 }
849
850 static void tegra_dsi_set_control_reg_lp(struct tegra_dc_dsi_data *dsi)
851 {
852         u32 dsi_control;
853         u32 host_dsi_control;
854         u32 max_threshold;
855
856         dsi_control = dsi->dsi_control_val | DSI_CTRL_HOST_DRIVEN;
857         host_dsi_control = HOST_DSI_CTRL_COMMON |
858                         HOST_DSI_CTRL_HOST_DRIVEN |
859                         DSI_HOST_DSI_CONTROL_HIGH_SPEED_TRANS(TEGRA_DSI_LOW);
860         max_threshold = DSI_MAX_THRESHOLD_MAX_THRESHOLD(DSI_HOST_FIFO_DEPTH);
861
862         tegra_dsi_writel(dsi, max_threshold, DSI_MAX_THRESHOLD);
863         tegra_dsi_writel(dsi, dsi_control, DSI_CONTROL);
864         tegra_dsi_writel(dsi, host_dsi_control, DSI_HOST_DSI_CONTROL);
865
866         dsi->status.driven = DSI_DRIVEN_MODE_HOST;
867         dsi->status.clk_burst = DSI_CLK_BURST_NOT_INIT;
868         dsi->status.vtype = DSI_VIDEO_TYPE_NOT_INIT;
869 }
870
871 static void tegra_dsi_set_control_reg_hs(struct tegra_dc_dsi_data *dsi)
872 {
873         u32 dsi_control;
874         u32 host_dsi_control;
875         u32 max_threshold;
876         u32 dcs_cmd;
877
878         dsi_control = dsi->dsi_control_val;
879         host_dsi_control = HOST_DSI_CTRL_COMMON;
880         max_threshold = 0;
881         dcs_cmd = 0;
882
883         if (dsi->driven_mode == TEGRA_DSI_DRIVEN_BY_HOST) {
884                 dsi_control |= DSI_CTRL_HOST_DRIVEN;
885                 host_dsi_control |= HOST_DSI_CTRL_HOST_DRIVEN;
886                 max_threshold = DSI_MAX_THRESHOLD_MAX_THRESHOLD(DSI_HOST_FIFO_DEPTH);
887                 dsi->status.driven = DSI_DRIVEN_MODE_HOST;
888         } else {
889                 dsi_control |= DSI_CTRL_DC_DRIVEN;
890                 host_dsi_control |= HOST_DSI_CTRL_DC_DRIVEN;
891                 max_threshold = DSI_MAX_THRESHOLD_MAX_THRESHOLD(DSI_VIDEO_FIFO_DEPTH);
892                 dsi->status.driven = DSI_DRIVEN_MODE_DC;
893         }
894
895         if (dsi->info.video_data_type == TEGRA_DSI_VIDEO_TYPE_COMMAND_MODE) {
896                 dsi_control |= DSI_CTRL_CMD_MODE;
897                 host_dsi_control |= HOST_DSI_CTRL_CMD_MODE;
898                 dcs_cmd = DSI_DCS_CMDS_LT5_DCS_CMD(DSI_WRITE_MEMORY_START)|
899                                 DSI_DCS_CMDS_LT3_DCS_CMD(DSI_WRITE_MEMORY_CONTINUE);
900                 dsi->status.vtype = DSI_VIDEO_TYPE_CMD_MODE;
901
902         } else {
903                 dsi_control |= DSI_CTRL_VIDEO_MODE;
904                 host_dsi_control |= HOST_DSI_CTRL_VIDEO_MODE;
905                 dsi->status.vtype = DSI_VIDEO_TYPE_VIDEO_MODE;
906         }
907
908         tegra_dsi_writel(dsi, max_threshold, DSI_MAX_THRESHOLD);
909         tegra_dsi_writel(dsi, dcs_cmd, DSI_DCS_CMDS);
910         tegra_dsi_writel(dsi, dsi_control, DSI_CONTROL);
911         tegra_dsi_writel(dsi, host_dsi_control, DSI_HOST_DSI_CONTROL);
912 }
913
914 static int tegra_dsi_init_hw(struct tegra_dc *dc,
915                                                 struct tegra_dc_dsi_data *dsi)
916 {
917         u32 val;
918         u32 i;
919         int err;
920         tegra_dsi_set_dsi_clk(dc, dsi, dsi->target_lp_clk_khz);
921         if (dsi->info.dsi_instance) {
922                 /* TODO:Set the misc register*/
923         }
924
925         /* TODO: only need to change the timing for bta */
926         tegra_dsi_set_phy_timing(dsi);
927
928         err = gpio_request(TEGRA_GPIO_PJ1, "DSI TE");
929         if (err < 0)
930                 goto fail;
931
932         err = gpio_direction_input(TEGRA_GPIO_PJ1);
933         if (err < 0) {
934                 gpio_free(TEGRA_GPIO_PJ1);
935                 goto fail;
936         }
937         tegra_gpio_enable(TEGRA_GPIO_PJ1);
938
939         if (dsi->status.driven == DSI_DRIVEN_MODE_DC)
940                 tegra_dsi_stop_dc_stream(dc, dsi);
941
942         /* Initializing DSI registers */
943         for (i = 0; i < ARRAY_SIZE(init_reg); i++) {
944                 tegra_dsi_writel(dsi, 0, init_reg[i]);
945         }
946         tegra_dsi_writel(dsi, dsi->dsi_control_val, DSI_CONTROL);
947
948         val = DSI_PAD_CONTROL_PAD_PDIO(0) |
949                         DSI_PAD_CONTROL_PAD_PDIO_CLK(0) |
950                         DSI_PAD_CONTROL_PAD_PULLDN_ENAB(TEGRA_DSI_DISABLE);
951         tegra_dsi_writel(dsi, val, DSI_PAD_CONTROL);
952
953         val = DSI_POWER_CONTROL_LEG_DSI_ENABLE(TEGRA_DSI_ENABLE);
954         tegra_dsi_writel(dsi, val, DSI_POWER_CONTROL);
955
956         while (tegra_dsi_readl(dsi, DSI_POWER_CONTROL) != val) {
957                 tegra_dsi_writel(dsi, val, DSI_POWER_CONTROL);
958         }
959
960         dsi->status.init = DSI_MODULE_INIT;
961         dsi->status.lphs = DSI_LPHS_NOT_INIT;
962         dsi->status.vtype = DSI_VIDEO_TYPE_NOT_INIT;
963         dsi->status.driven = DSI_DRIVEN_MODE_NOT_INIT;
964         dsi->status.clk_out = DSI_PHYCLK_OUT_DIS;
965         dsi->status.clk_mode = DSI_PHYCLK_NOT_INIT;
966         dsi->status.clk_burst = DSI_CLK_BURST_NOT_INIT;
967 fail:
968         return err;
969 }
970
971 static int tegra_dsi_set_to_lp_mode(struct tegra_dc *dc,
972                                                 struct tegra_dc_dsi_data *dsi)
973 {
974         int     err;
975
976         if (dsi->status.init != DSI_MODULE_INIT) {
977                 err = -EPERM;
978                 goto fail;
979         }
980
981         if (dsi->status.lphs == DSI_LPHS_IN_LP_MODE)
982                 goto success;
983
984         if (dsi->status.driven == DSI_DRIVEN_MODE_DC)
985                 tegra_dsi_stop_dc_stream(dc, dsi);
986
987         /* disable/enable hs clock according to enable_hs_clock_on_lp_cmd_mode */
988         if ((dsi->status.clk_out == DSI_PHYCLK_OUT_EN) &&
989                 (!dsi->info.enable_hs_clock_on_lp_cmd_mode))
990                 tegra_dsi_hs_clk_out_disable(dc, dsi);
991
992         if (dsi->current_dsi_clk_khz != dsi->target_lp_clk_khz){
993                 tegra_dsi_set_dsi_clk(dc, dsi, dsi->target_lp_clk_khz);
994                 tegra_dsi_set_timeout(dsi);
995         }
996
997         tegra_dsi_set_control_reg_lp(dsi);
998
999         if ((dsi->status.clk_out == DSI_PHYCLK_OUT_DIS) &&
1000                 (dsi->info.enable_hs_clock_on_lp_cmd_mode))
1001                 tegra_dsi_hs_clk_out_enable_in_lp(dsi);
1002
1003 success:
1004         dsi->status.lphs = DSI_LPHS_IN_LP_MODE;
1005         err = 0;
1006 fail:
1007         return err;
1008 }
1009
1010 static int tegra_dsi_set_to_hs_mode(struct tegra_dc *dc,
1011                                                 struct tegra_dc_dsi_data *dsi)
1012 {
1013         int err;
1014
1015         if (dsi->status.init != DSI_MODULE_INIT) {
1016                 err = -EPERM;
1017                 goto fail;
1018         }
1019
1020         if (dsi->status.driven == DSI_DRIVEN_MODE_DC)
1021                 tegra_dsi_stop_dc_stream(dc, dsi);
1022
1023         if ((dsi->status.clk_out == DSI_PHYCLK_OUT_EN) &&
1024                 (!dsi->info.enable_hs_clock_on_lp_cmd_mode))
1025                 tegra_dsi_hs_clk_out_disable(dc, dsi);
1026
1027         if (dsi->current_dsi_clk_khz != dsi->target_hs_clk_khz) {
1028                 tegra_dsi_set_dsi_clk(dc, dsi, dsi->target_hs_clk_khz);
1029                 tegra_dsi_set_timeout(dsi);
1030         }
1031
1032         tegra_dsi_set_phy_timing(dsi);
1033
1034         if (dsi->driven_mode == TEGRA_DSI_DRIVEN_BY_DC){
1035                 tegra_dsi_set_pkt_seq(dc, dsi);
1036                 tegra_dsi_set_pkt_length(dc, dsi);
1037                 tegra_dsi_set_sol_delay(dc, dsi);
1038                 tegra_dsi_set_dc_clk(dc, dsi);
1039         }
1040
1041         tegra_dsi_set_control_reg_hs(dsi);
1042
1043         if (dsi->status.clk_out == DSI_PHYCLK_OUT_DIS)
1044                 tegra_dsi_hs_clk_out_enable(dsi);
1045
1046         dsi->status.lphs = DSI_LPHS_IN_HS_MODE;
1047         err = 0;
1048 fail:
1049         return err;
1050 }
1051
1052 static bool tegra_dsi_is_controller_idle(struct tegra_dc_dsi_data *dsi)
1053 {
1054         u32 timeout = 0;
1055         bool retVal;
1056
1057         retVal = false;
1058         while (timeout <= DSI_MAX_COMMAND_DELAY_USEC) {
1059                 if (!tegra_dsi_readl(dsi, DSI_TRIGGER)) {
1060                         retVal = true;
1061                         break;
1062                 }
1063                 udelay(DSI_COMMAND_DELAY_STEPS_USEC);
1064                 timeout += DSI_COMMAND_DELAY_STEPS_USEC;
1065         }
1066
1067         return retVal;
1068 }
1069
1070 static bool tegra_dsi_host_trigger(struct tegra_dc_dsi_data *dsi)
1071 {
1072         bool status;
1073
1074         status = false;
1075         if (tegra_dsi_readl(dsi, DSI_TRIGGER))
1076                 goto fail;
1077
1078         tegra_dsi_writel(dsi, DSI_TRIGGER_HOST_TRIGGER(TEGRA_DSI_ENABLE),
1079                                                                 DSI_TRIGGER);
1080
1081 #if DSI_USE_SYNC_POINTS
1082         /* TODO: Implement sync point */
1083 #else
1084         status = tegra_dsi_is_controller_idle(dsi);
1085 #endif
1086
1087 fail:
1088         return status;
1089 }
1090
1091 static int tegra_dsi_read_data(struct tegra_dc *dc,
1092                                                 struct tegra_dc_dsi_data *dsi)
1093 {
1094         /* TODO: implement DSI read */
1095         return ENXIO;
1096 }
1097
1098 static int tegra_dsi_write_data(struct tegra_dc *dc,
1099                                         struct tegra_dc_dsi_data *dsi,
1100                                         u8* pdata, u8 data_id, u16 data_len)
1101 {
1102         bool switch_back_to_hs_mode;
1103         bool switch_back_to_dc_mode;
1104         u32 val;
1105         u8 *pval;
1106         int     err;
1107         u8  virtua_channel;
1108
1109         err = 0;
1110         switch_back_to_hs_mode = false;
1111         switch_back_to_dc_mode = false;
1112
1113         if ((dsi->status.init != DSI_MODULE_INIT) ||
1114                 (dsi->status.lphs == DSI_LPHS_NOT_INIT)) {
1115                 err = -EPERM;
1116                 goto fail;
1117         }
1118
1119         if (!tegra_dsi_is_controller_idle(dsi)) {
1120                 err = -EBUSY;
1121                 goto fail;
1122         }
1123
1124         err = 0;
1125
1126         if (dsi->status.lphs == DSI_LPHS_IN_HS_MODE) {
1127                 if (dsi->info.hs_cmd_mode_supported) {
1128                         if (dsi->status.driven == DSI_DRIVEN_MODE_DC) {
1129                                 dsi->driven_mode = TEGRA_DSI_DRIVEN_BY_HOST;
1130                                 tegra_dsi_set_to_hs_mode(dc, dsi);
1131                                 switch_back_to_dc_mode = true;
1132                         }
1133                 } else {
1134                         tegra_dsi_set_to_lp_mode(dc, dsi);
1135                         switch_back_to_hs_mode = true;
1136                 }
1137         }
1138
1139         virtua_channel = dsi->info.virtual_channel << DSI_VIR_CHANNEL_BIT_POSITION;
1140
1141         /* always use hw for ecc */
1142         val = (virtua_channel | data_id) << 0 |
1143                         data_len << 8;
1144         tegra_dsi_writel(dsi, val, DSI_WR_DATA);
1145
1146         /* if pdata != NULL, pkt type is long pkt */
1147         if (pdata != NULL) {
1148                 while (data_len) {
1149                         if (data_len >= 4) {
1150                                 val = ((u32*) pdata)[0];
1151                                 data_len -= 4;
1152                                 pdata += 4;
1153                         } else {
1154                                 val = 0;
1155                                 pval = (u8*) &val;
1156                                 do
1157                                         *pval++ = *pdata++;
1158                                 while(--data_len);
1159                         }
1160                         tegra_dsi_writel(dsi, val, DSI_WR_DATA);
1161                 }
1162         }
1163
1164         if (!tegra_dsi_host_trigger(dsi))
1165                 err = -EIO;
1166
1167         if (switch_back_to_dc_mode)
1168                 dsi->driven_mode = TEGRA_DSI_DRIVEN_BY_DC;
1169         if (switch_back_to_dc_mode || switch_back_to_hs_mode)
1170                 tegra_dsi_set_to_hs_mode(dc, dsi);
1171
1172 fail:
1173         return err;
1174 }
1175
1176 static int tegra_dsi_init_panel(struct tegra_dc *dc,
1177                                                 struct tegra_dc_dsi_data *dsi)
1178 {
1179         u32     i;
1180         int err;
1181
1182         err = 0;
1183         for (i = 0; i < dsi->info.n_init_cmd; i++) {
1184                 struct tegra_dsi_cmd *cur_cmd;
1185                 cur_cmd = &dsi->info.dsi_init_cmd[i];
1186
1187                 if (cur_cmd->cmd_type == TEGRA_DSI_DELAY_MS)
1188                         mdelay(cur_cmd->sp_len_dly.delay_ms);
1189                 else {
1190                         err = tegra_dsi_write_data(dc, dsi,
1191                                                 cur_cmd->pdata,
1192                                                 cur_cmd->data_id,
1193                                                 cur_cmd->sp_len_dly.data_len);
1194                         if (err < 0)
1195                                 break;
1196                 }
1197         }
1198         return err;
1199 }
1200
1201 static void tegra_dc_dsi_enable(struct tegra_dc *dc)
1202 {
1203         struct tegra_dc_dsi_data *dsi = tegra_dc_get_outdata(dc);
1204         int err;
1205
1206         tegra_dc_io_start(dc);
1207         mutex_lock(&dsi->lock);
1208
1209         err = tegra_dsi_init_hw(dc, dsi);
1210         if (err < 0) {
1211                 dev_err(&dc->ndev->dev, "dsi: not able to init dsi hardware\n");
1212                 return;
1213         }
1214
1215         err = tegra_dsi_set_to_lp_mode(dc, dsi);
1216         if (err < 0) {
1217                 dev_err(&dc->ndev->dev, "dsi: not able to set to lp mode\n");
1218                 return;
1219         }
1220
1221         err = tegra_dsi_init_panel(dc, dsi);
1222         if (err < 0) {
1223                 dev_err(&dc->ndev->dev, "dsi: error while sending dsi cmd\n");
1224                 return;
1225         }
1226
1227         err = tegra_dsi_set_to_hs_mode(dc, dsi);
1228         if (err < 0) {
1229                         dev_err(&dc->ndev->dev,
1230                                         "dsi: not able to set to hs mode\n");
1231                 return;
1232         }
1233
1234         if (dsi->status.driven == DSI_DRIVEN_MODE_DC) {
1235                 tegra_dsi_start_dc_stream(dc, dsi);
1236         }
1237
1238         mutex_unlock(&dsi->lock);
1239         tegra_dc_io_end(dc);
1240 }
1241
1242 static void _tegra_dc_dsi_init(struct tegra_dc *dc)
1243 {
1244         struct tegra_dc_dsi_data *dsi = tegra_dc_get_outdata(dc);
1245
1246         tegra_dsi_init_sw(dc, dsi);
1247         /* TODO: Configure the CSI pad configuration */
1248 }
1249
1250 static int tegra_dc_dsi_cp_init_cmd(struct tegra_dsi_cmd* src,
1251                                         struct tegra_dsi_cmd* dst, u16 n_cmd)
1252 {
1253         u16 i;
1254         u16 len;
1255
1256         memcpy(dst, src, sizeof(*dst) * n_cmd);
1257
1258         for (i = 0; i < n_cmd; i++)
1259                 if (src[i].pdata) {
1260                         len = sizeof(*src[i].pdata) * src[i].sp_len_dly.data_len;
1261                         dst[i].pdata = kzalloc(len, GFP_KERNEL);
1262                         if (!dst[i].pdata)
1263                                 goto free_cmd_pdata;
1264                         memcpy(dst[i].pdata, src[i].pdata, len);
1265                 }
1266
1267         return 0;
1268
1269 free_cmd_pdata:
1270         for (--i; i >=0; i--)
1271                 if (dst[i].pdata)
1272                         kfree(dst[i].pdata);
1273         return -ENOMEM;
1274 }
1275
1276 static int tegra_dc_dsi_cp_info(struct tegra_dc_dsi_data* dsi,
1277                                                 struct tegra_dsi_out* p_dsi)
1278 {
1279         struct tegra_dsi_cmd* pcmd;
1280         int err;
1281
1282         pcmd = kzalloc(sizeof(*pcmd) * p_dsi->n_init_cmd, GFP_KERNEL);
1283         if (!pcmd)
1284                 return -ENOMEM;
1285
1286         if (p_dsi->n_data_lanes > MAX_DSI_DATA_LANES) {
1287                 err = -EINVAL;
1288                 goto err_free_pcmd;
1289         }
1290
1291         memcpy(&dsi->info, p_dsi, sizeof(dsi->info));
1292
1293         err = tegra_dc_dsi_cp_init_cmd(p_dsi->dsi_init_cmd,
1294                                                 pcmd, p_dsi->n_init_cmd);
1295         if (err < 0)
1296                 goto err_free_pcmd;
1297
1298         dsi->info.dsi_init_cmd = pcmd;
1299
1300         if (!dsi->info.panel_reset_timeout_msec)
1301                 dsi->info.panel_reset_timeout_msec = DEFAULT_PANEL_RESET_TIMEOUT;
1302
1303         if (!dsi->info.panel_buffer_size_byte)
1304                 dsi->info.panel_buffer_size_byte = DEFAULT_PANEL_BUFFER_BYTE;
1305
1306         if (!dsi->info.max_panel_freq_khz)
1307                 dsi->info.max_panel_freq_khz = DEFAULT_MAX_DSI_PHY_CLK_KHZ;
1308
1309         if (!dsi->info.lp_cmd_mode_freq_khz)
1310                 dsi->info.lp_cmd_mode_freq_khz = DEFAULT_LP_CMD_MODE_CLK_KHZ;
1311
1312         /* host mode is for testing only*/
1313         dsi->driven_mode = TEGRA_DSI_DRIVEN_BY_DC;
1314
1315         return 0;
1316
1317 err_free_pcmd:
1318         kfree(pcmd);
1319         return err;
1320 }
1321
1322 static int tegra_dc_dsi_init(struct tegra_dc *dc)
1323 {
1324         struct tegra_dc_dsi_data *dsi;
1325         struct resource *res;
1326         struct resource *base_res;
1327         void __iomem *base;
1328         struct clk *dc_clk = NULL;
1329         struct clk *dsi_clk = NULL;
1330         struct tegra_dsi_out *dsi_pdata;
1331         int err;
1332
1333         err = 0;
1334
1335         dsi = kzalloc(sizeof(*dsi), GFP_KERNEL);
1336         if (!dsi)
1337                 return -ENOMEM;
1338
1339         res = nvhost_get_resource_byname(dc->ndev, IORESOURCE_MEM,
1340                                         "dsi_regs");
1341         if (!res) {
1342                 dev_err(&dc->ndev->dev, "dsi: no mem resource\n");
1343                 err = -ENOENT;
1344                 goto err_free_dsi;
1345         }
1346
1347         base_res = request_mem_region(res->start, resource_size(res),
1348                                 dc->ndev->name);
1349         if (!base_res) {
1350                 dev_err(&dc->ndev->dev, "dsi: request_mem_region failed\n");
1351                 err = -EBUSY;
1352                 goto err_free_dsi;
1353         }
1354
1355         base = ioremap(res->start, resource_size(res));
1356         if (!base) {
1357                 dev_err(&dc->ndev->dev, "dsi: registers can't be mapped\n");
1358                 err = -EBUSY;
1359                 goto err_release_regs;
1360         }
1361
1362         dsi_pdata = dc->pdata->default_out->dsi;
1363         if (!dsi_pdata) {
1364                 dev_err(&dc->ndev->dev, "dsi: dsi data not available\n");
1365                 goto err_release_regs;
1366         }
1367
1368         if (dsi_pdata->dsi_instance)
1369                 dsi_clk = clk_get(&dc->ndev->dev, "dsib");
1370         else
1371                 dsi_clk = clk_get(&dc->ndev->dev, "dsia");
1372
1373         if (IS_ERR_OR_NULL(dsi_clk)) {
1374                 dev_err(&dc->ndev->dev, "dsi: can't get clock\n");
1375                 err = -EBUSY;
1376                 goto err_release_regs;
1377         }
1378
1379         dc_clk = clk_get_sys(dev_name(&dc->ndev->dev), NULL);
1380         if (IS_ERR_OR_NULL(dc_clk)) {
1381                 dev_err(&dc->ndev->dev, "dsi: dc clock %s unavailable\n",
1382                         dev_name(&dc->ndev->dev));
1383                 err = -EBUSY;
1384                 goto err_clk_put;
1385         }
1386
1387         err = tegra_dc_dsi_cp_info(dsi, dsi_pdata);
1388         if (err < 0)
1389                 goto err_dsi_data;
1390
1391         mutex_init(&dsi->lock);
1392         dsi->dc = dc;
1393         dsi->base = base;
1394         dsi->base_res = base_res;
1395         dsi->dc_clk = dc_clk;
1396         dsi->dsi_clk = dsi_clk;
1397
1398         tegra_dc_set_outdata(dc, dsi);
1399         _tegra_dc_dsi_init(dc);
1400
1401         return 0;
1402
1403 err_dsi_data:
1404 err_clk_put:
1405         clk_put(dsi_clk);
1406 err_release_regs:
1407         release_resource(base_res);
1408 err_free_dsi:
1409         kfree(dsi);
1410
1411         return err;
1412 }
1413
1414 static void tegra_dc_dsi_destroy(struct tegra_dc *dc)
1415 {
1416         struct tegra_dc_dsi_data *dsi = tegra_dc_get_outdata(dc);
1417         u16 i;
1418         u32 val;
1419
1420         mutex_lock(&dsi->lock);
1421
1422         /* free up the pdata*/
1423         for(i = 0; i < dsi->info.n_init_cmd; i++){
1424                 if(dsi->info.dsi_init_cmd[i].pdata)
1425                         kfree(dsi->info.dsi_init_cmd[i].pdata);
1426         }
1427         kfree(dsi->info.dsi_init_cmd);
1428
1429         /* Disable dc stream*/
1430         if(dsi->status.driven == DSI_DRIVEN_MODE_DC)
1431                 tegra_dsi_stop_dc_stream(dc, dsi);
1432
1433         /* Disable dsi phy clock*/
1434         if(dsi->status.clk_out == DSI_PHYCLK_OUT_EN)
1435                 tegra_dsi_hs_clk_out_disable(dc, dsi);
1436
1437         val = DSI_POWER_CONTROL_LEG_DSI_ENABLE(TEGRA_DSI_DISABLE);
1438         tegra_dsi_writel(dsi, val, DSI_POWER_CONTROL);
1439
1440         iounmap(dsi->base);
1441         release_resource(dsi->base_res);
1442
1443         clk_put(dsi->dc_clk);
1444         clk_put(dsi->dsi_clk);
1445
1446         mutex_unlock(&dsi->lock);
1447
1448         mutex_destroy(&dsi->lock);
1449         kfree(dsi);
1450 }
1451
1452 static void tegra_dc_dsi_disable(struct tegra_dc *dc)
1453 {
1454         struct tegra_dc_dsi_data *dsi = tegra_dc_get_outdata(dc);
1455
1456         mutex_lock(&dsi->lock);
1457
1458         if (dsi->status.driven == DSI_DRIVEN_MODE_DC)
1459                 tegra_dsi_stop_dc_stream(dc, dsi);
1460
1461         if (dsi->status.clk_out == DSI_PHYCLK_OUT_EN)
1462                 tegra_dsi_hs_clk_out_disable(dc, dsi);
1463
1464         mutex_unlock(&dsi->lock);
1465
1466         dev_err(&dc->ndev->dev, "dsi: disable\n");
1467 }
1468
1469 struct tegra_dc_out_ops tegra_dc_dsi_ops = {
1470         .init = tegra_dc_dsi_init,
1471         .destroy = tegra_dc_dsi_destroy,
1472         .enable = tegra_dc_dsi_enable,
1473         .disable = tegra_dc_dsi_disable,
1474 };