video: dsi: tegra: driver power management
[linux-2.6.git] / drivers / video / tegra / dc / dsi.c
1 /*
2  * drivers/video/tegra/dc/dsi.c
3  *
4  * Copyright (c) 2011, NVIDIA Corporation.
5  *
6  * This software is licensed under the terms of the GNU General Public
7  * License version 2, as published by the Free Software Foundation, and
8  * may be copied, distributed, and modified under those terms.
9  *
10  * This program is distributed in the hope that it will be useful,
11  * but WITHOUT ANY WARRANTY; without even the implied warranty of
12  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
13  * GNU General Public License for more details.
14  *
15  */
16
17 #include <linux/clk.h>
18 #include <linux/delay.h>
19 #include <linux/err.h>
20 #include <linux/fb.h>
21 #include <linux/gpio.h>
22 #include <linux/interrupt.h>
23 #include <linux/kernel.h>
24 #include <linux/slab.h>
25 #include <linux/spinlock.h>
26 #include <linux/workqueue.h>
27
28 #include <mach/clk.h>
29 #include <mach/dc.h>
30 #include <mach/fb.h>
31 #include <mach/nvhost.h>
32 #include <../gpio-names.h>
33
34 #include "dc_reg.h"
35 #include "dc_priv.h"
36 #include "dsi_regs.h"
37 #include "dsi.h"
38
39 #define DSI_USE_SYNC_POINTS 0
40
41 #define DSI_STOP_DC_DURATION_MSEC 1000
42
43 #define DSI_MODULE_NOT_INIT             0x0
44 #define DSI_MODULE_INIT                 0x1
45
46 #define DSI_LPHS_NOT_INIT               0x0
47 #define DSI_LPHS_IN_LP_MODE             0x1
48 #define DSI_LPHS_IN_HS_MODE             0x2
49
50 #define DSI_VIDEO_TYPE_NOT_INIT         0x0
51 #define DSI_VIDEO_TYPE_VIDEO_MODE       0x1
52 #define DSI_VIDEO_TYPE_CMD_MODE         0x2
53
54 #define DSI_DRIVEN_MODE_NOT_INIT        0x0
55 #define DSI_DRIVEN_MODE_DC              0x1
56 #define DSI_DRIVEN_MODE_HOST            0x2
57
58 #define DSI_PHYCLK_OUT_DIS              0x0
59 #define DSI_PHYCLK_OUT_EN               0x1
60
61 #define DSI_PHYCLK_NOT_INIT             0x0
62 #define DSI_PHYCLK_CONTINUOUS           0x1
63 #define DSI_PHYCLK_TX_ONLY              0x2
64
65 #define DSI_CLK_BURST_NOT_INIT          0x0
66 #define DSI_CLK_BURST_NONE_BURST        0x1
67 #define DSI_CLK_BURST_BURST_MODE        0x2
68
69 #define DSI_DC_STREAM_DISABLE           0x0
70 #define DSI_DC_STREAM_ENABLE            0x1
71
72 struct dsi_status {
73         unsigned        init:2;
74
75         unsigned        lphs:2;
76
77         unsigned        vtype:2;
78         unsigned        driven:2;
79
80         unsigned        clk_out:2;
81         unsigned        clk_mode:2;
82         unsigned        clk_burst:2;
83
84         unsigned        dc_stream:1;
85 };
86
87 /* source of video data */
88 enum{
89         TEGRA_DSI_DRIVEN_BY_DC,
90         TEGRA_DSI_DRIVEN_BY_HOST,
91 };
92
93 struct tegra_dc_dsi_data {
94         struct tegra_dc *dc;
95         void __iomem    *base;
96         struct resource *base_res;
97
98         struct clk              *dc_clk;
99         struct clk              *dsi_clk;
100
101         struct mutex    lock;
102
103         /* data from board info */
104         struct tegra_dsi_out info;
105
106         struct dsi_status       status;
107
108         u8              driven_mode;
109         u8              controller_index;
110
111         u8              pixel_scaler_mul;
112         u8              pixel_scaler_div;
113
114         u32             default_pixel_clk_khz;
115         u32             default_hs_clk_khz;
116
117         u32             target_hs_clk_khz;
118         u32             target_lp_clk_khz;
119
120         u16             current_bit_clk_ns;
121         u32             current_dsi_clk_khz;
122
123         u32             dsi_control_val;
124
125         bool            ulpm;
126 };
127
128 const u32 dsi_pkt_seq_reg[NUMOF_PKT_SEQ] = {
129         DSI_PKT_SEQ_0_LO,
130         DSI_PKT_SEQ_0_HI,
131         DSI_PKT_SEQ_1_LO,
132         DSI_PKT_SEQ_1_HI,
133         DSI_PKT_SEQ_2_LO,
134         DSI_PKT_SEQ_2_HI,
135         DSI_PKT_SEQ_3_LO,
136         DSI_PKT_SEQ_3_HI,
137         DSI_PKT_SEQ_4_LO,
138         DSI_PKT_SEQ_4_HI,
139         DSI_PKT_SEQ_5_LO,
140         DSI_PKT_SEQ_5_HI,
141 };
142
143 const u32 dsi_pkt_seq_video_non_burst_syne[NUMOF_PKT_SEQ] = {
144         PKT_ID0(CMD_VS) | PKT_LEN0(0) | PKT_ID1(CMD_EOT) | PKT_LEN1(0) | PKT_LP,
145         0,
146         PKT_ID0(CMD_VE) | PKT_LEN0(0) | PKT_ID1(CMD_EOT) | PKT_LEN1(0) | PKT_LP,
147         0,
148         PKT_ID0(CMD_HS) | PKT_LEN0(0) | PKT_ID1(CMD_EOT) | PKT_LEN1(0) | PKT_LP,
149         0,
150         PKT_ID0(CMD_HS) | PKT_LEN0(0) | PKT_ID1(CMD_BLNK) | PKT_LEN1(1) |
151                 PKT_ID2(CMD_HE) | PKT_LEN2(0),
152         PKT_ID3(CMD_BLNK) | PKT_LEN3(2) | PKT_ID4(CMD_RGB) | PKT_LEN4(3) |
153                 PKT_ID5(CMD_BLNK) | PKT_LEN5(4),
154         PKT_ID0(CMD_HS) | PKT_LEN0(0) | PKT_ID1(CMD_EOT) | PKT_LEN1(0) | PKT_LP,
155         0,
156         PKT_ID0(CMD_HS) | PKT_LEN0(0) | PKT_ID1(CMD_BLNK) | PKT_LEN1(1) |
157                 PKT_ID2(CMD_HE) | PKT_LEN2(0),
158         PKT_ID3(CMD_BLNK) | PKT_LEN3(2) | PKT_ID4(CMD_RGB) | PKT_LEN4(3) |
159                 PKT_ID5(CMD_BLNK) | PKT_LEN5(4),
160 };
161
162 const u32 dsi_pkt_seq_video_non_burst[NUMOF_PKT_SEQ] = {
163         PKT_ID0(CMD_VS) | PKT_LEN0(0) | PKT_ID1(CMD_EOT) | PKT_LEN1(0) | PKT_LP,
164         0,
165         PKT_ID0(CMD_HS) | PKT_LEN0(0) | PKT_ID1(CMD_EOT) | PKT_LEN1(0) | PKT_LP,
166         0,
167         PKT_ID0(CMD_HS) | PKT_LEN0(0) | PKT_ID1(CMD_EOT) | PKT_LEN1(0) | PKT_LP,
168         0,
169         PKT_ID0(CMD_HS) | PKT_LEN0(0) | PKT_ID1(CMD_BLNK) | PKT_LEN1(2) |
170                 PKT_ID2(CMD_RGB) | PKT_LEN2(3),
171         PKT_ID3(CMD_BLNK) | PKT_LEN3(4),
172         PKT_ID0(CMD_HS) | PKT_LEN0(0) | PKT_ID1(CMD_EOT) | PKT_LEN1(0) | PKT_LP,
173         0,
174         PKT_ID0(CMD_HS) | PKT_LEN0(0) | PKT_ID1(CMD_BLNK) | PKT_LEN1(2) |
175                 PKT_ID2(CMD_RGB) | PKT_LEN2(3),
176         PKT_ID3(CMD_BLNK) | PKT_LEN3(4),
177 };
178
179 static const u32 dsi_pkt_seq_video_burst[NUMOF_PKT_SEQ] = {
180         PKT_ID0(CMD_VS) | PKT_LEN0(0) | PKT_ID1(CMD_EOT) | PKT_LEN1(7) | PKT_LP,
181         0,
182         PKT_ID0(CMD_HS) | PKT_LEN0(0) | PKT_ID1(CMD_EOT) | PKT_LEN1(7) | PKT_LP,
183         0,
184         PKT_ID0(CMD_HS) | PKT_LEN0(0) | PKT_ID1(CMD_EOT) | PKT_LEN1(7) | PKT_LP,
185         0,
186         PKT_ID0(CMD_HS) | PKT_LEN0(0) | PKT_ID1(CMD_BLNK) | PKT_LEN1(2)|
187         PKT_ID2(CMD_RGB) | PKT_LEN2(3) | PKT_LP,
188         PKT_ID0(CMD_EOT) | PKT_LEN0(7),
189         PKT_ID0(CMD_HS) | PKT_LEN0(0) | PKT_ID1(CMD_EOT) | PKT_LEN1(7) | PKT_LP,
190         0,
191         PKT_ID0(CMD_HS) | PKT_LEN0(0) | PKT_ID1(CMD_BLNK) | PKT_LEN1(2)|
192         PKT_ID2(CMD_RGB) | PKT_LEN2(3) | PKT_LP,
193         PKT_ID0(CMD_EOT) | PKT_LEN0(7),
194 };
195
196 static const u32 dsi_pkt_seq_video_burst_no_eot[NUMOF_PKT_SEQ] = {
197         PKT_ID0(CMD_VS) | PKT_LEN0(0) | PKT_ID1(CMD_EOT) | PKT_LEN1(0) | PKT_LP,
198         0,
199         PKT_ID0(CMD_HS) | PKT_LEN0(0) | PKT_ID1(CMD_EOT) | PKT_LEN1(0) | PKT_LP,
200         0,
201         PKT_ID0(CMD_HS) | PKT_LEN0(0) | PKT_ID1(CMD_EOT) | PKT_LEN1(0) | PKT_LP,
202         0,
203         PKT_ID0(CMD_HS) | PKT_LEN0(0) | PKT_ID1(CMD_BLNK) | PKT_LEN1(2)|
204         PKT_ID2(CMD_RGB) | PKT_LEN2(3) | PKT_LP,
205         PKT_ID0(CMD_EOT) | PKT_LEN0(0),
206         PKT_ID0(CMD_HS) | PKT_LEN0(0) | PKT_ID1(CMD_EOT) | PKT_LEN1(0) | PKT_LP,
207         0,
208         PKT_ID0(CMD_HS) | PKT_LEN0(0) | PKT_ID1(CMD_BLNK) | PKT_LEN1(2)|
209         PKT_ID2(CMD_RGB) | PKT_LEN2(3) | PKT_LP,
210         PKT_ID0(CMD_EOT) | PKT_LEN0(0),
211 };
212
213 /* TODO: verify with hw about this format */
214 const u32 dsi_pkt_seq_cmd_mode [NUMOF_PKT_SEQ] = {
215         0,
216         0,
217         0,
218         0,
219         0,
220         0,
221         PKT_ID0(CMD_LONGW) | PKT_LEN0(3) | PKT_ID1(CMD_EOT) | PKT_LEN1(7),
222         0,
223         0,
224         0,
225         PKT_ID0(CMD_LONGW) | PKT_LEN0(3) | PKT_ID1(CMD_EOT) | PKT_LEN1(7),
226         0,
227 };
228
229 const u32 init_reg[] = {
230         DSI_WR_DATA,
231         DSI_INT_ENABLE,
232         DSI_INT_STATUS,
233         DSI_INT_MASK,
234         DSI_INIT_SEQ_DATA_0,
235         DSI_INIT_SEQ_DATA_1,
236         DSI_INIT_SEQ_DATA_2,
237         DSI_INIT_SEQ_DATA_3,
238         DSI_DCS_CMDS,
239         DSI_PKT_SEQ_0_LO,
240         DSI_PKT_SEQ_1_LO,
241         DSI_PKT_SEQ_2_LO,
242         DSI_PKT_SEQ_3_LO,
243         DSI_PKT_SEQ_4_LO,
244         DSI_PKT_SEQ_5_LO,
245         DSI_PKT_SEQ_0_HI,
246         DSI_PKT_SEQ_1_HI,
247         DSI_PKT_SEQ_2_HI,
248         DSI_PKT_SEQ_3_HI,
249         DSI_PKT_SEQ_4_HI,
250         DSI_PKT_SEQ_5_HI,
251         DSI_CONTROL,
252         DSI_HOST_DSI_CONTROL,
253         DSI_PAD_CONTROL,
254         DSI_PAD_CONTROL_CD,
255         DSI_SOL_DELAY,
256         DSI_MAX_THRESHOLD,
257         DSI_TRIGGER,
258         DSI_TX_CRC,
259         DSI_INIT_SEQ_CONTROL,
260         DSI_PKT_LEN_0_1,
261         DSI_PKT_LEN_2_3,
262         DSI_PKT_LEN_4_5,
263         DSI_PKT_LEN_6_7,
264 };
265
266 static inline unsigned long tegra_dsi_readl(struct tegra_dc_dsi_data *dsi,
267                                                                         u32 reg)
268 {
269         return readl(dsi->base + reg * 4);
270 }
271
272 static inline void tegra_dsi_writel(struct tegra_dc_dsi_data *dsi,u32 val,
273                                                                         u32 reg)
274 {
275         writel(val, dsi->base + reg * 4);
276 }
277
278 static u32 tegra_dsi_get_hs_clk_rate(struct tegra_dc_dsi_data *dsi)
279 {
280         u32 dsi_clock_rate_khz;
281
282         switch (dsi->info.video_burst_mode) {
283         case TEGRA_DSI_VIDEO_BURST_MODE_LOW_SPEED:
284         case TEGRA_DSI_VIDEO_BURST_MODE_MEDIUM_SPEED:
285         case TEGRA_DSI_VIDEO_BURST_MODE_FAST_SPEED:
286         case TEGRA_DSI_VIDEO_BURST_MODE_FASTEST_SPEED:
287                 /* TODO: implement algo for these speed rate */
288
289         case TEGRA_DSI_VIDEO_BURST_MODE_MANUAL:
290                 if (dsi->info.burst_mode_freq_khz) {
291                         dsi_clock_rate_khz = dsi->info.burst_mode_freq_khz;
292                         break;
293                 }
294         case TEGRA_DSI_VIDEO_NONE_BURST_MODE:
295         case TEGRA_DSI_VIDEO_NONE_BURST_MODE_WITH_SYNC_END:
296         case TEGRA_DSI_VIDEO_BURST_MODE_LOWEST_SPEED:
297         default:
298                 dsi_clock_rate_khz = dsi->default_hs_clk_khz;
299                 break;
300         }
301
302         return dsi_clock_rate_khz;
303 }
304
305 static u32 tegra_dsi_get_lp_clk_rate(struct tegra_dc_dsi_data *dsi)
306 {
307         u32 dsi_clock_rate_khz;
308
309         if (dsi->info.enable_hs_clock_on_lp_cmd_mode)
310                 if (dsi->info.hs_clk_in_lp_cmd_mode_freq_khz)
311                         dsi_clock_rate_khz =
312                                 dsi->info.hs_clk_in_lp_cmd_mode_freq_khz;
313                 else
314                         dsi_clock_rate_khz = tegra_dsi_get_hs_clk_rate(dsi);
315         else
316                 dsi_clock_rate_khz = dsi->info.lp_cmd_mode_freq_khz;
317
318         return dsi_clock_rate_khz;
319 }
320
321 static void tegra_dsi_init_sw(struct tegra_dc *dc,
322                                                 struct tegra_dc_dsi_data *dsi)
323 {
324         u32 h_width_pixels;
325         u32 v_width_lines;
326         u32 pixel_clk_hz;
327         u32 byte_clk_hz;
328
329         switch (dsi->info.pixel_format) {
330                 case TEGRA_DSI_PIXEL_FORMAT_16BIT_P:
331                         /* 2 bytes per pixel */
332                         dsi->pixel_scaler_mul = 2;
333                         dsi->pixel_scaler_div = 1;
334                         break;
335                 case TEGRA_DSI_PIXEL_FORMAT_18BIT_P:
336                         /* 2.25 bytes per pixel */
337                         dsi->pixel_scaler_mul = 9;
338                         dsi->pixel_scaler_div = 4;
339                         break;
340                 case TEGRA_DSI_PIXEL_FORMAT_18BIT_NP:
341                 case TEGRA_DSI_PIXEL_FORMAT_24BIT_P:
342                         /* 3 bytes per pixel */
343                         dsi->pixel_scaler_mul = 3;
344                         dsi->pixel_scaler_div = 1;
345                         break;
346                 default:
347                         break;
348         }
349
350         h_width_pixels = dc->mode.h_back_porch + dc->mode.h_front_porch +
351                         dc->mode.h_sync_width + dc->mode.h_active;
352         v_width_lines = dc->mode.v_back_porch + dc->mode.v_front_porch +
353                         dc->mode.v_sync_width + dc->mode.v_active;
354
355         /* The slowest pixel rate that is required */
356         /*   for the given display timing       */
357         pixel_clk_hz = h_width_pixels * v_width_lines * dsi->info.refresh_rate;
358
359         /* Pixel byte rate on DSI interface */
360         byte_clk_hz     = (pixel_clk_hz * dsi->pixel_scaler_mul) /
361                         (dsi->pixel_scaler_div * dsi->info.n_data_lanes);
362
363         dsi->default_pixel_clk_khz = pixel_clk_hz / 1000;
364
365         printk("dsi: default pixel rate %d khz\n", dsi->default_pixel_clk_khz);
366
367         /*
368          * Pixel bit rate on DSI. Since DSI interface is double data rate (
369          * transferring data on both rising and falling edge of clk), div by 2
370          * to get the actual clock rate.
371          */
372         dsi->default_hs_clk_khz =
373                         (byte_clk_hz * NUMOF_BIT_PER_BYTE) / (1000 * 2);
374
375         dsi->controller_index = dc->ndev->id;
376         dsi->ulpm = false;
377
378         dsi->dsi_control_val =
379                         DSI_CONTROL_VIRTUAL_CHANNEL(dsi->info.virtual_channel) |
380                         DSI_CONTROL_NUM_DATA_LANES(dsi->info.n_data_lanes - 1) |
381                         DSI_CONTROL_VID_SOURCE(dsi->controller_index) |
382                         DSI_CONTROL_DATA_FORMAT(dsi->info.pixel_format);
383
384         dsi->target_lp_clk_khz = tegra_dsi_get_lp_clk_rate(dsi);
385         dsi->target_hs_clk_khz = tegra_dsi_get_hs_clk_rate(dsi);
386
387         /*
388          * Force video clock to be continuous mode if
389          * enable_hs_clock_on_lp_cmd_mode is set
390          */
391         if (dsi->info.enable_hs_clock_on_lp_cmd_mode) {
392                 if (dsi->info.video_clock_mode != TEGRA_DSI_VIDEO_CLOCK_CONTINUOUS)
393                         printk("Force to clock continuous mode\n");
394
395                 dsi->info.video_clock_mode = TEGRA_DSI_VIDEO_CLOCK_CONTINUOUS;
396         }
397
398 }
399
400 static void tegra_dsi_get_phy_timing(struct tegra_dc_dsi_data *dsi,
401                                 struct dsi_phy_timing_inclk *phy_timing_clk,
402                                 u32 clk_ns)
403 {
404
405         phy_timing_clk->t_hsdexit = dsi->info.phy_timing.t_hsdexit_ns ?
406                         (dsi->info.phy_timing.t_hsdexit_ns / clk_ns) :
407                         (T_HSEXIT_DEFAULT(clk_ns));
408
409         phy_timing_clk->t_hstrail = dsi->info.phy_timing.t_hstrail_ns ?
410                         (dsi->info.phy_timing.t_hstrail_ns / clk_ns) :
411                         (T_HSTRAIL_DEFAULT(clk_ns));
412
413         phy_timing_clk->t_datzero = dsi->info.phy_timing.t_datzero_ns ?
414                         (dsi->info.phy_timing.t_datzero_ns / clk_ns) :
415                         (T_DATZERO_DEFAULT(clk_ns));
416
417         phy_timing_clk->t_hsprepr = dsi->info.phy_timing.t_hsprepr_ns ?
418                         (dsi->info.phy_timing.t_hsprepr_ns / clk_ns) :
419                         (T_HSPREPR_DEFAULT(clk_ns));
420
421         phy_timing_clk->t_clktrail = dsi->info.phy_timing.t_clktrail_ns ?
422                                 (dsi->info.phy_timing.t_clktrail_ns / clk_ns) :
423                                 (T_CLKTRAIL_DEFAULT(clk_ns));
424
425         phy_timing_clk->t_clkpost = dsi->info.phy_timing.t_clkpost_ns ?
426                                 (dsi->info.phy_timing.t_clkpost_ns / clk_ns) :
427                                 (T_CLKPOST_DEFAULT(clk_ns));
428
429         phy_timing_clk->t_clkzero = dsi->info.phy_timing.t_clkzero_ns ?
430                                 (dsi->info.phy_timing.t_clkzero_ns / clk_ns) :
431                                 (T_CLKZERO_DEFAULT(clk_ns));
432
433         phy_timing_clk->t_tlpx = dsi->info.phy_timing.t_tlpx_ns ?
434                                 (dsi->info.phy_timing.t_tlpx_ns / clk_ns) :
435                                 (T_TLPX_DEFAULT(clk_ns));
436
437         phy_timing_clk->t_clkpre = T_CLKPRE_DEFAULT(clk_ns);
438         phy_timing_clk->t_clkprepare = T_CLKPREPARE_DEFAULT(clk_ns);
439         phy_timing_clk->t_wakeup = T_WAKEUP_DEFAULT(clk_ns);
440
441         phy_timing_clk->t_taget = 5 * phy_timing_clk->t_tlpx;
442         phy_timing_clk->t_tasure = 2 * phy_timing_clk->t_tlpx;
443         phy_timing_clk->t_tago = 4 * phy_timing_clk->t_tlpx;
444 }
445
446 static void tegra_dsi_set_phy_timing(struct tegra_dc_dsi_data *dsi)
447 {
448         u32 val;
449         struct dsi_phy_timing_inclk     phy_timing;
450
451         tegra_dsi_get_phy_timing(dsi, &phy_timing, dsi->current_bit_clk_ns);
452
453         val = DSI_PHY_TIMING_0_THSDEXIT(phy_timing.t_hsdexit) |
454                         DSI_PHY_TIMING_0_THSTRAIL(phy_timing.t_hstrail) |
455                         DSI_PHY_TIMING_0_TDATZERO(phy_timing.t_datzero) |
456                         DSI_PHY_TIMING_0_THSPREPR(phy_timing.t_hsprepr);
457         tegra_dsi_writel(dsi, val, DSI_PHY_TIMING_0);
458
459         val = DSI_PHY_TIMING_1_TCLKTRAIL(phy_timing.t_clktrail) |
460                         DSI_PHY_TIMING_1_TCLKPOST(phy_timing.t_clkpost) |
461                         DSI_PHY_TIMING_1_TCLKZERO(phy_timing.t_clkzero) |
462                         DSI_PHY_TIMING_1_TTLPX(phy_timing.t_tlpx);
463         tegra_dsi_writel(dsi, val, DSI_PHY_TIMING_1);
464
465         val = DSI_PHY_TIMING_2_TCLKPREPARE(phy_timing.t_clkprepare) |
466                 DSI_PHY_TIMING_2_TCLKPRE(phy_timing.t_clkpre) |
467                         DSI_PHY_TIMING_2_TWAKEUP(phy_timing.t_wakeup);
468         tegra_dsi_writel(dsi, val, DSI_PHY_TIMING_2);
469
470         val = DSI_BTA_TIMING_TTAGET(phy_timing.t_taget) |
471                         DSI_BTA_TIMING_TTASURE(phy_timing.t_tasure) |
472                         DSI_BTA_TIMING_TTAGO(phy_timing.t_tago);
473         tegra_dsi_writel(dsi, val, DSI_BTA_TIMING);
474 }
475
476 static u32 tegra_dsi_sol_delay_burst(struct tegra_dc *dc,
477                                                 struct tegra_dc_dsi_data *dsi)
478 {
479         u32 dsi_to_pixel_clk_ratio;
480         u32 temp;
481         u32 temp1;
482         u32 mipi_clk_adj_kHz;
483         u32 sol_delay;
484         struct tegra_dc_mode *dc_modes = &dc->mode;
485
486         /* Get Fdsi/Fpixel ration (note: Fdsi si in bit format) */
487         dsi_to_pixel_clk_ratio = (dsi->current_dsi_clk_khz * 2 +
488                 dsi->default_pixel_clk_khz - 1) / dsi->default_pixel_clk_khz;
489
490         /* Convert Fdsi to byte format */
491         dsi_to_pixel_clk_ratio *= 1000/8;
492
493         /* Multiplying by 1000 so that we don't loose the fraction part */
494         temp = dc_modes->h_active * 1000;
495         temp1 = dc_modes->h_active + dc_modes->h_back_porch +
496                         dc_modes->h_sync_width;
497
498         sol_delay = temp1 * dsi_to_pixel_clk_ratio -
499                         temp * dsi->pixel_scaler_mul /
500                         (dsi->pixel_scaler_div * dsi->info.n_data_lanes);
501
502         /* Do rounding on sol delay */
503         sol_delay = (sol_delay + 1000 - 1)/1000;
504
505         /* TODO:
506          * 1. find out the correct sol fifo depth to use
507          * 2. verify with hw about the clamping function
508          */
509         if (sol_delay > (480 * 4)) {
510                 sol_delay = (480 * 4);
511                 mipi_clk_adj_kHz = sol_delay +
512                         (dc_modes->h_active * dsi->pixel_scaler_mul) /
513                         (dsi->info.n_data_lanes * dsi->pixel_scaler_div);
514
515                 mipi_clk_adj_kHz *= (dsi->default_pixel_clk_khz / temp1);
516
517                 mipi_clk_adj_kHz *= 4;
518         }
519
520         dsi->target_hs_clk_khz = mipi_clk_adj_kHz;
521
522         return sol_delay;
523 }
524
525 static void tegra_dsi_set_sol_delay(struct tegra_dc *dc,
526                                                 struct tegra_dc_dsi_data *dsi)
527 {
528         u32 sol_delay;
529
530         if (dsi->info.video_burst_mode == TEGRA_DSI_VIDEO_NONE_BURST_MODE ||
531                 dsi->info.video_burst_mode ==
532                                 TEGRA_DSI_VIDEO_NONE_BURST_MODE_WITH_SYNC_END) {
533                 sol_delay = NUMOF_BIT_PER_BYTE * dsi->pixel_scaler_mul /
534                         (dsi->pixel_scaler_div * dsi->info.n_data_lanes);
535                 dsi->status.clk_burst = DSI_CLK_BURST_NONE_BURST;
536         } else {
537                 sol_delay = tegra_dsi_sol_delay_burst(dc, dsi);
538                 dsi->status.clk_burst = DSI_CLK_BURST_BURST_MODE;
539         }
540
541         tegra_dsi_writel(dsi, DSI_SOL_DELAY_SOL_DELAY(sol_delay),
542                                                                 DSI_SOL_DELAY);
543 }
544
545 static void tegra_dsi_set_timeout(struct tegra_dc_dsi_data *dsi)
546 {
547         u32 val;
548         u32 bytes_per_frame;
549         u32 timeout = 0;
550
551         /* TODO: verify the following eq */
552         bytes_per_frame = dsi->current_dsi_clk_khz * 1000 * 2 /
553                                                 (dsi->info.refresh_rate * 8);
554         timeout = bytes_per_frame / DSI_CYCLE_COUNTER_VALUE;
555         timeout = (timeout + DSI_HTX_TO_MARGIN) & 0xffff;
556
557         val = DSI_TIMEOUT_0_LRXH_TO(DSI_LRXH_TO_VALUE) |
558                         DSI_TIMEOUT_0_HTX_TO(timeout);
559         tegra_dsi_writel(dsi, val, DSI_TIMEOUT_0);
560
561         if (dsi->info.panel_reset_timeout_msec)
562                 timeout = (dsi->info.panel_reset_timeout_msec * 1000*1000)
563                                         / dsi->current_bit_clk_ns;
564         else
565                 timeout = DSI_PR_TO_VALUE;
566
567         val = DSI_TIMEOUT_1_PR_TO(timeout) |
568                 DSI_TIMEOUT_1_TA_TO(DSI_TA_TO_VALUE);
569         tegra_dsi_writel(dsi, val, DSI_TIMEOUT_1);
570
571         val = DSI_TO_TALLY_P_RESET_STATUS(IN_RESET) |
572                 DSI_TO_TALLY_TA_TALLY(DSI_TA_TALLY_VALUE)|
573                 DSI_TO_TALLY_LRXH_TALLY(DSI_LRXH_TALLY_VALUE)|
574                 DSI_TO_TALLY_HTX_TALLY(DSI_HTX_TALLY_VALUE);
575         tegra_dsi_writel(dsi, val, DSI_TO_TALLY);
576 }
577
578 static void tegra_dsi_setup_video_mode_pkt_length(struct tegra_dc *dc,
579                                                 struct tegra_dc_dsi_data *dsi)
580 {
581         u32 val;
582         u32 hact_pkt_len;
583         u32 hsa_pkt_len;
584         u32 hbp_pkt_len;
585         u32 hfp_pkt_len;
586
587         hact_pkt_len = dc->mode.h_active * dsi->pixel_scaler_mul /
588                                                         dsi->pixel_scaler_div;
589         hsa_pkt_len = dc->mode.h_sync_width * dsi->pixel_scaler_mul /
590                                                         dsi->pixel_scaler_div;
591         hbp_pkt_len = dc->mode.h_back_porch * dsi->pixel_scaler_mul /
592                                                         dsi->pixel_scaler_div;
593         hfp_pkt_len = dc->mode.h_front_porch * dsi->pixel_scaler_mul /
594                                                         dsi->pixel_scaler_div;
595
596         if (dsi->info.video_burst_mode !=
597                                 TEGRA_DSI_VIDEO_NONE_BURST_MODE_WITH_SYNC_END)
598                 hbp_pkt_len += hsa_pkt_len;
599
600         hsa_pkt_len -= DSI_HSYNC_BLNK_PKT_OVERHEAD;
601         hbp_pkt_len -= DSI_HBACK_PORCH_PKT_OVERHEAD;
602         hfp_pkt_len -= DSI_HFRONT_PORCH_PKT_OVERHEAD;
603
604         val = DSI_PKT_LEN_0_1_LENGTH_0(0) | DSI_PKT_LEN_0_1_LENGTH_1(hsa_pkt_len);
605         tegra_dsi_writel(dsi, val, DSI_PKT_LEN_0_1);
606
607         val = DSI_PKT_LEN_2_3_LENGTH_2(hbp_pkt_len) |
608                         DSI_PKT_LEN_2_3_LENGTH_3(hact_pkt_len);
609         tegra_dsi_writel(dsi, val, DSI_PKT_LEN_2_3);
610
611         val = DSI_PKT_LEN_4_5_LENGTH_4(hfp_pkt_len) | DSI_PKT_LEN_4_5_LENGTH_5(0);
612         tegra_dsi_writel(dsi, val, DSI_PKT_LEN_4_5);
613
614         val = DSI_PKT_LEN_6_7_LENGTH_6(0) | DSI_PKT_LEN_6_7_LENGTH_7(0);
615         tegra_dsi_writel(dsi, val, DSI_PKT_LEN_6_7);
616 }
617
618 static void tegra_dsi_setup_cmd_mode_pkt_length(struct tegra_dc *dc,
619                                                 struct tegra_dc_dsi_data *dsi)
620 {
621         unsigned long   val;
622         unsigned long   act_bytes;
623
624         act_bytes = dc->mode.h_active * dsi->pixel_scaler_mul /
625                         dsi->pixel_scaler_div + 1;
626
627         val = DSI_PKT_LEN_0_1_LENGTH_0(0) | DSI_PKT_LEN_0_1_LENGTH_1(0);
628         tegra_dsi_writel(dsi, val, DSI_PKT_LEN_0_1);
629
630         val = DSI_PKT_LEN_2_3_LENGTH_2(0) | DSI_PKT_LEN_2_3_LENGTH_3(act_bytes);
631         tegra_dsi_writel(dsi, val, DSI_PKT_LEN_2_3);
632
633         val = DSI_PKT_LEN_4_5_LENGTH_4(0) | DSI_PKT_LEN_4_5_LENGTH_5(act_bytes);
634         tegra_dsi_writel(dsi, val, DSI_PKT_LEN_4_5);
635
636         val = DSI_PKT_LEN_6_7_LENGTH_6(0) | DSI_PKT_LEN_6_7_LENGTH_7(0x0f0f);
637         tegra_dsi_writel(dsi, val, DSI_PKT_LEN_6_7);
638 }
639
640 static void tegra_dsi_set_pkt_length(struct tegra_dc *dc,
641                                                 struct tegra_dc_dsi_data *dsi)
642 {
643         if (dsi->driven_mode == TEGRA_DSI_DRIVEN_BY_HOST)
644                 return;
645
646         if (dsi->info.video_data_type == TEGRA_DSI_VIDEO_TYPE_VIDEO_MODE)
647                 tegra_dsi_setup_video_mode_pkt_length(dc, dsi);
648         else
649                 tegra_dsi_setup_cmd_mode_pkt_length(dc, dsi);
650 }
651
652 static void tegra_dsi_set_pkt_seq(struct tegra_dc *dc,
653                                                 struct tegra_dc_dsi_data *dsi)
654 {
655         const u32 *pkt_seq;
656         u32 rgb_info;
657         u32 pkt_seq_3_5_rgb_lo;
658         u32 pkt_seq_3_5_rgb_hi;
659         u32     val;
660         u32 reg;
661         u8  i;
662
663         if (dsi->driven_mode == TEGRA_DSI_DRIVEN_BY_HOST)
664                 return;
665
666         switch(dsi->info.pixel_format) {
667         case TEGRA_DSI_PIXEL_FORMAT_16BIT_P:
668                 rgb_info = CMD_RGB_16BPP;
669                 break;
670         case TEGRA_DSI_PIXEL_FORMAT_18BIT_P:
671                 rgb_info = CMD_RGB_18BPP;
672                 break;
673         case TEGRA_DSI_PIXEL_FORMAT_18BIT_NP:
674                 rgb_info = CMD_RGB_18BPPNP;
675                 break;
676         case TEGRA_DSI_PIXEL_FORMAT_24BIT_P:
677         default:
678                 rgb_info = CMD_RGB_24BPP;
679                 break;
680         }
681
682         pkt_seq_3_5_rgb_lo = 0;
683         pkt_seq_3_5_rgb_hi = 0;
684         if (dsi->info.video_data_type == TEGRA_DSI_VIDEO_TYPE_COMMAND_MODE)
685                 pkt_seq = dsi_pkt_seq_cmd_mode;
686         else {
687                 switch (dsi->info.video_burst_mode) {
688                 case TEGRA_DSI_VIDEO_BURST_MODE_LOWEST_SPEED:
689                 case TEGRA_DSI_VIDEO_BURST_MODE_LOW_SPEED:
690                 case TEGRA_DSI_VIDEO_BURST_MODE_MEDIUM_SPEED:
691                 case TEGRA_DSI_VIDEO_BURST_MODE_FAST_SPEED:
692                 case TEGRA_DSI_VIDEO_BURST_MODE_FASTEST_SPEED:
693                 case TEGRA_DSI_VIDEO_BURST_MODE_MANUAL:
694                         pkt_seq_3_5_rgb_lo = DSI_PKT_SEQ_3_LO_PKT_32_ID(rgb_info);
695                         if(!dsi->info.no_pkt_seq_eot)
696                                 pkt_seq = dsi_pkt_seq_video_burst;
697                         else
698                                 pkt_seq = dsi_pkt_seq_video_burst_no_eot;
699                         break;
700                 case TEGRA_DSI_VIDEO_NONE_BURST_MODE_WITH_SYNC_END:
701                         pkt_seq_3_5_rgb_hi = DSI_PKT_SEQ_3_HI_PKT_34_ID(rgb_info);
702                         pkt_seq = dsi_pkt_seq_video_non_burst_syne;
703                         break;
704                 case TEGRA_DSI_VIDEO_NONE_BURST_MODE:
705                 default:
706                         pkt_seq_3_5_rgb_lo = DSI_PKT_SEQ_3_LO_PKT_32_ID(rgb_info);
707                         pkt_seq = dsi_pkt_seq_video_non_burst;
708                         break;
709                 }
710         }
711
712         for (i = 0; i < NUMOF_PKT_SEQ; i++) {
713                 val = pkt_seq[i];
714                 reg = dsi_pkt_seq_reg[i];
715                 if ((reg == DSI_PKT_SEQ_3_LO) || (reg == DSI_PKT_SEQ_5_LO))
716                         val |= pkt_seq_3_5_rgb_lo;
717                 if ((reg == DSI_PKT_SEQ_3_HI) || (reg == DSI_PKT_SEQ_5_HI))
718                         val |= pkt_seq_3_5_rgb_hi;
719                 tegra_dsi_writel(dsi, val, reg);
720         }
721 }
722
723 static void tegra_dsi_stop_dc_stream(struct tegra_dc *dc,
724                                                 struct tegra_dc_dsi_data *dsi)
725 {
726         tegra_dc_writel(dc, 0, DC_DISP_DISP_WIN_OPTIONS);
727         tegra_dc_writel(dc, GENERAL_ACT_REQ << 8, DC_CMD_STATE_CONTROL);
728         tegra_dc_writel(dc, GENERAL_ACT_REQ, DC_CMD_STATE_CONTROL);
729
730         dsi->status.dc_stream = DSI_DC_STREAM_DISABLE;
731 }
732
733 void tegra_dsi_stop_dc_stream_at_frame_end(struct tegra_dc *dc, struct tegra_dc_dsi_data *dsi)
734 {
735         int val;
736         long timeout;
737
738         /* stop dc */
739         tegra_dsi_stop_dc_stream(dc, dsi);
740
741         /* enable vblank interrupt */
742         val = tegra_dc_readl(dc, DC_CMD_INT_ENABLE);
743         val |= V_BLANK_INT;
744         tegra_dc_writel(dc, val, DC_CMD_INT_ENABLE);
745
746         val = tegra_dc_readl(dc, DC_CMD_INT_MASK);
747         val |= V_BLANK_INT;
748         tegra_dc_writel(dc, val, DC_CMD_INT_MASK);
749
750         /* wait for vblank completion */
751         timeout = wait_for_completion_interruptible_timeout(
752                 &dc->vblank_complete, DSI_STOP_DC_DURATION_MSEC);
753
754         /* disable vblank interrupt */
755         val = tegra_dc_readl(dc, DC_CMD_INT_ENABLE);
756         val &= ~V_BLANK_INT;
757         tegra_dc_writel(dc, val, DC_CMD_INT_ENABLE);
758
759         if(timeout == 0)
760                 printk("Warning: dc dosen't stop at the end of the frame.\n");
761 }
762
763 static void tegra_dsi_start_dc_stream(struct tegra_dc *dc,
764                                                 struct tegra_dc_dsi_data *dsi)
765 {
766         u32 val;
767
768         tegra_dc_writel(dc, DSI_ENABLE, DC_DISP_DISP_WIN_OPTIONS);
769
770         /* TODO: clean up */
771         val = PIN_INPUT_LSPI_INPUT_EN;
772         tegra_dc_writel(dc, val, DC_COM_PIN_INPUT_ENABLE3);
773
774         val = PIN_OUTPUT_LSPI_OUTPUT_DIS;
775         tegra_dc_writel(dc, val, DC_COM_PIN_OUTPUT_ENABLE3);
776
777         tegra_dc_writel(dc, PW0_ENABLE | PW1_ENABLE | PW2_ENABLE | PW3_ENABLE |
778                         PW4_ENABLE | PM0_ENABLE | PM1_ENABLE,
779                         DC_CMD_DISPLAY_POWER_CONTROL);
780
781         val = MSF_POLARITY_HIGH | MSF_ENABLE | MSF_LSPI;
782         tegra_dc_writel(dc, val, DC_CMD_DISPLAY_COMMAND_OPTION0);
783
784
785         /* TODO: using continuous video mode for now */
786         /* if (dsi->info.panel_has_frame_buffer) {*/
787         if (0) {
788                 tegra_dc_writel(dc, DISP_CTRL_MODE_NC_DISPLAY, DC_CMD_DISPLAY_COMMAND);
789                 tegra_dc_writel(dc, GENERAL_UPDATE, DC_CMD_STATE_CONTROL);
790                 val = GENERAL_ACT_REQ | NC_HOST_TRIG;
791                 tegra_dc_writel(dc, val, DC_CMD_STATE_CONTROL);
792         } else {
793                 tegra_dc_writel(dc, DISP_CTRL_MODE_C_DISPLAY, DC_CMD_DISPLAY_COMMAND);
794                 tegra_dc_writel(dc, GENERAL_ACT_REQ << 8, DC_CMD_STATE_CONTROL);
795                 tegra_dc_writel(dc, GENERAL_ACT_REQ, DC_CMD_STATE_CONTROL);
796         }
797
798         dsi->status.dc_stream = DSI_DC_STREAM_ENABLE;
799 }
800
801 static void tegra_dsi_set_dc_clk(struct tegra_dc *dc,
802                                                 struct tegra_dc_dsi_data *dsi)
803 {
804         u32 shift_clk_div;
805         u32 val;
806
807         if (dsi->info.video_burst_mode == TEGRA_DSI_VIDEO_NONE_BURST_MODE ||
808                 dsi->info.video_burst_mode ==
809                                 TEGRA_DSI_VIDEO_NONE_BURST_MODE_WITH_SYNC_END)
810                 shift_clk_div = NUMOF_BIT_PER_BYTE * dsi->pixel_scaler_mul /
811                         (dsi->pixel_scaler_div * dsi->info.n_data_lanes) - 2;
812         else
813                 shift_clk_div = (dsi->current_dsi_clk_khz * 2 +
814                                                 dsi->default_hs_clk_khz - 1) /
815                                                 (dsi->default_hs_clk_khz) - 2;
816
817 #ifdef CONFIG_TEGRA_FPGA_PLATFORM
818         shift_clk_div = 1;
819 #endif
820
821         /* TODO: find out if PCD3 option is required */
822         val = PIXEL_CLK_DIVIDER_PCD1 | SHIFT_CLK_DIVIDER(shift_clk_div);
823         tegra_dc_writel(dc, val, DC_DISP_DISP_CLOCK_CONTROL);
824
825         clk_enable(dsi->dc_clk);
826 }
827
828 static void tegra_dsi_set_dsi_clk(struct tegra_dc *dc,
829                                         struct tegra_dc_dsi_data *dsi, u32 clk)
830 {
831         u32 rm;
832
833         rm = clk % 1000;
834         if (rm != 0)
835                 clk -= rm;
836
837         clk *= 2;       /* Value for PLLD routine is required to be twice as */
838                         /* the desired clock rate */
839
840         dc->mode.pclk = clk*1000;
841         tegra_dc_setup_clk(dc, dsi->dsi_clk);
842         clk_enable(dsi->dsi_clk);
843         tegra_periph_reset_deassert(dsi->dsi_clk);
844
845         dsi->current_dsi_clk_khz = clk_get_rate(dsi->dsi_clk) / 1000;
846
847         dsi->current_bit_clk_ns =  1000*1000 / (dsi->current_dsi_clk_khz * 2);
848 }
849
850 static void tegra_dsi_hs_clk_out_enable(struct tegra_dc_dsi_data *dsi)
851 {
852         u32 val;
853
854         val = tegra_dsi_readl(dsi, DSI_CONTROL);
855         val &= ~DSI_CONTROL_HS_CLK_CTRL(1);
856
857         if (dsi->info.video_clock_mode == TEGRA_DSI_VIDEO_CLOCK_CONTINUOUS) {
858                 val |= DSI_CONTROL_HS_CLK_CTRL(CONTINUOUS);
859                 dsi->status.clk_mode = DSI_PHYCLK_CONTINUOUS;
860         } else {
861                 val |= DSI_CONTROL_HS_CLK_CTRL(TX_ONLY);
862                 dsi->status.clk_mode = DSI_PHYCLK_TX_ONLY;
863         }
864         tegra_dsi_writel(dsi, val, DSI_CONTROL);
865
866         val = tegra_dsi_readl(dsi, DSI_HOST_DSI_CONTROL);
867         val &= ~DSI_HOST_DSI_CONTROL_HIGH_SPEED_TRANS(1);
868         val |= DSI_HOST_DSI_CONTROL_HIGH_SPEED_TRANS(TEGRA_DSI_HIGH);
869         tegra_dsi_writel(dsi, val, DSI_HOST_DSI_CONTROL);
870
871         dsi->status.clk_out = DSI_PHYCLK_OUT_EN;
872 }
873
874 static void tegra_dsi_hs_clk_out_enable_in_lp(struct tegra_dc_dsi_data *dsi)
875 {
876         u32 val;
877         tegra_dsi_hs_clk_out_enable(dsi);
878
879         val = tegra_dsi_readl(dsi, DSI_HOST_DSI_CONTROL);
880         val &= ~DSI_HOST_DSI_CONTROL_HIGH_SPEED_TRANS(1);
881         val |= DSI_HOST_DSI_CONTROL_HIGH_SPEED_TRANS(TEGRA_DSI_LOW);
882         tegra_dsi_writel(dsi, val, DSI_HOST_DSI_CONTROL);
883 }
884
885 static void tegra_dsi_hs_clk_out_disable(struct tegra_dc *dc,
886                                                 struct tegra_dc_dsi_data *dsi)
887 {
888         u32 val;
889
890         if (dsi->status.dc_stream == DSI_DC_STREAM_ENABLE)
891                 tegra_dsi_stop_dc_stream(dc, dsi);
892
893         val = tegra_dsi_readl(dsi, DSI_CONTROL);
894         val &= ~DSI_CONTROL_HS_CLK_CTRL(1);
895         val |= DSI_CONTROL_HS_CLK_CTRL(TX_ONLY);
896         tegra_dsi_writel(dsi, val, DSI_CONTROL);
897
898         /* TODO: issue a cmd */
899
900         val = tegra_dsi_readl(dsi, DSI_HOST_DSI_CONTROL);
901         val &= ~DSI_HOST_DSI_CONTROL_HIGH_SPEED_TRANS(1);
902         val |= DSI_HOST_DSI_CONTROL_HIGH_SPEED_TRANS(TEGRA_DSI_LOW);
903         tegra_dsi_writel(dsi, val, DSI_HOST_DSI_CONTROL);
904
905         dsi->status.clk_mode = DSI_PHYCLK_NOT_INIT;
906         dsi->status.clk_out = DSI_PHYCLK_OUT_DIS;
907 }
908
909 static void tegra_dsi_set_control_reg_lp(struct tegra_dc_dsi_data *dsi)
910 {
911         u32 dsi_control;
912         u32 host_dsi_control;
913         u32 max_threshold;
914
915         dsi_control = dsi->dsi_control_val | DSI_CTRL_HOST_DRIVEN;
916         host_dsi_control = HOST_DSI_CTRL_COMMON |
917                         HOST_DSI_CTRL_HOST_DRIVEN |
918                         DSI_HOST_DSI_CONTROL_HIGH_SPEED_TRANS(TEGRA_DSI_LOW);
919         max_threshold = DSI_MAX_THRESHOLD_MAX_THRESHOLD(DSI_HOST_FIFO_DEPTH);
920
921         tegra_dsi_writel(dsi, max_threshold, DSI_MAX_THRESHOLD);
922         tegra_dsi_writel(dsi, dsi_control, DSI_CONTROL);
923         tegra_dsi_writel(dsi, host_dsi_control, DSI_HOST_DSI_CONTROL);
924
925         dsi->status.driven = DSI_DRIVEN_MODE_HOST;
926         dsi->status.clk_burst = DSI_CLK_BURST_NOT_INIT;
927         dsi->status.vtype = DSI_VIDEO_TYPE_NOT_INIT;
928 }
929
930 static void tegra_dsi_set_control_reg_hs(struct tegra_dc_dsi_data *dsi)
931 {
932         u32 dsi_control;
933         u32 host_dsi_control;
934         u32 max_threshold;
935         u32 dcs_cmd;
936
937         dsi_control = dsi->dsi_control_val;
938         host_dsi_control = HOST_DSI_CTRL_COMMON;
939         max_threshold = 0;
940         dcs_cmd = 0;
941
942         if (dsi->driven_mode == TEGRA_DSI_DRIVEN_BY_HOST) {
943                 dsi_control |= DSI_CTRL_HOST_DRIVEN;
944                 host_dsi_control |= HOST_DSI_CTRL_HOST_DRIVEN;
945                 max_threshold = DSI_MAX_THRESHOLD_MAX_THRESHOLD(DSI_HOST_FIFO_DEPTH);
946                 dsi->status.driven = DSI_DRIVEN_MODE_HOST;
947         } else {
948                 dsi_control |= DSI_CTRL_DC_DRIVEN;
949                 host_dsi_control |= HOST_DSI_CTRL_DC_DRIVEN;
950                 max_threshold = DSI_MAX_THRESHOLD_MAX_THRESHOLD(DSI_VIDEO_FIFO_DEPTH);
951                 dsi->status.driven = DSI_DRIVEN_MODE_DC;
952         }
953
954         if (dsi->info.video_data_type == TEGRA_DSI_VIDEO_TYPE_COMMAND_MODE) {
955                 dsi_control |= DSI_CTRL_CMD_MODE;
956                 host_dsi_control |= HOST_DSI_CTRL_CMD_MODE;
957                 dcs_cmd = DSI_DCS_CMDS_LT5_DCS_CMD(DSI_WRITE_MEMORY_START)|
958                                 DSI_DCS_CMDS_LT3_DCS_CMD(DSI_WRITE_MEMORY_CONTINUE);
959                 dsi->status.vtype = DSI_VIDEO_TYPE_CMD_MODE;
960
961         } else {
962                 dsi_control |= DSI_CTRL_VIDEO_MODE;
963                 host_dsi_control |= HOST_DSI_CTRL_VIDEO_MODE;
964                 dsi->status.vtype = DSI_VIDEO_TYPE_VIDEO_MODE;
965         }
966
967         tegra_dsi_writel(dsi, max_threshold, DSI_MAX_THRESHOLD);
968         tegra_dsi_writel(dsi, dcs_cmd, DSI_DCS_CMDS);
969         tegra_dsi_writel(dsi, dsi_control, DSI_CONTROL);
970         tegra_dsi_writel(dsi, host_dsi_control, DSI_HOST_DSI_CONTROL);
971 }
972
973 static int tegra_dsi_init_hw(struct tegra_dc *dc,
974                                                 struct tegra_dc_dsi_data *dsi)
975 {
976         u32 val;
977         u32 i;
978
979         tegra_dsi_set_dsi_clk(dc, dsi, dsi->target_lp_clk_khz);
980         if (dsi->info.dsi_instance) {
981                 /* TODO:Set the misc register*/
982         }
983
984         /* TODO: only need to change the timing for bta */
985         tegra_dsi_set_phy_timing(dsi);
986
987         if (dsi->status.dc_stream == DSI_DC_STREAM_ENABLE)
988                 tegra_dsi_stop_dc_stream(dc, dsi);
989
990         /* Initializing DSI registers */
991         for (i = 0; i < ARRAY_SIZE(init_reg); i++) {
992                 tegra_dsi_writel(dsi, 0, init_reg[i]);
993         }
994         tegra_dsi_writel(dsi, dsi->dsi_control_val, DSI_CONTROL);
995
996         val = DSI_PAD_CONTROL_PAD_PDIO(0) |
997                         DSI_PAD_CONTROL_PAD_PDIO_CLK(0) |
998                         DSI_PAD_CONTROL_PAD_PULLDN_ENAB(TEGRA_DSI_DISABLE);
999         tegra_dsi_writel(dsi, val, DSI_PAD_CONTROL);
1000
1001         val = DSI_POWER_CONTROL_LEG_DSI_ENABLE(TEGRA_DSI_ENABLE);
1002         tegra_dsi_writel(dsi, val, DSI_POWER_CONTROL);
1003
1004         while (tegra_dsi_readl(dsi, DSI_POWER_CONTROL) != val) {
1005                 tegra_dsi_writel(dsi, val, DSI_POWER_CONTROL);
1006         }
1007
1008         dsi->status.init = DSI_MODULE_INIT;
1009         dsi->status.lphs = DSI_LPHS_NOT_INIT;
1010         dsi->status.vtype = DSI_VIDEO_TYPE_NOT_INIT;
1011         dsi->status.driven = DSI_DRIVEN_MODE_NOT_INIT;
1012         dsi->status.clk_out = DSI_PHYCLK_OUT_DIS;
1013         dsi->status.clk_mode = DSI_PHYCLK_NOT_INIT;
1014         dsi->status.clk_burst = DSI_CLK_BURST_NOT_INIT;
1015         dsi->status.dc_stream = DSI_DC_STREAM_DISABLE;
1016
1017         return 0;
1018 }
1019
1020 static int tegra_dsi_set_to_lp_mode(struct tegra_dc *dc,
1021                                                 struct tegra_dc_dsi_data *dsi)
1022 {
1023         int     err;
1024
1025         if (dsi->status.init != DSI_MODULE_INIT) {
1026                 err = -EPERM;
1027                 goto fail;
1028         }
1029
1030         if (dsi->status.lphs == DSI_LPHS_IN_LP_MODE)
1031                 goto success;
1032
1033         if (dsi->status.dc_stream == DSI_DC_STREAM_ENABLE)
1034                 tegra_dsi_stop_dc_stream_at_frame_end(dc, dsi);
1035
1036         /* disable/enable hs clock according to enable_hs_clock_on_lp_cmd_mode */
1037         if ((dsi->status.clk_out == DSI_PHYCLK_OUT_EN) &&
1038                 (!dsi->info.enable_hs_clock_on_lp_cmd_mode))
1039                 tegra_dsi_hs_clk_out_disable(dc, dsi);
1040
1041         if (dsi->current_dsi_clk_khz != dsi->target_lp_clk_khz){
1042                 tegra_dsi_set_dsi_clk(dc, dsi, dsi->target_lp_clk_khz);
1043                 tegra_dsi_set_timeout(dsi);
1044         }
1045
1046         tegra_dsi_set_control_reg_lp(dsi);
1047
1048         if ((dsi->status.clk_out == DSI_PHYCLK_OUT_DIS) &&
1049                 (dsi->info.enable_hs_clock_on_lp_cmd_mode))
1050                 tegra_dsi_hs_clk_out_enable_in_lp(dsi);
1051
1052 success:
1053         dsi->status.lphs = DSI_LPHS_IN_LP_MODE;
1054         err = 0;
1055 fail:
1056         return err;
1057 }
1058
1059 static int tegra_dsi_set_to_hs_mode(struct tegra_dc *dc,
1060                                                 struct tegra_dc_dsi_data *dsi)
1061 {
1062         int err;
1063
1064         if (dsi->status.init != DSI_MODULE_INIT) {
1065                 err = -EPERM;
1066                 goto fail;
1067         }
1068
1069         if (dsi->status.dc_stream == DSI_DC_STREAM_ENABLE)
1070                 tegra_dsi_stop_dc_stream_at_frame_end(dc, dsi);
1071
1072         if ((dsi->status.clk_out == DSI_PHYCLK_OUT_EN) &&
1073                 (!dsi->info.enable_hs_clock_on_lp_cmd_mode))
1074                 tegra_dsi_hs_clk_out_disable(dc, dsi);
1075
1076         if (dsi->current_dsi_clk_khz != dsi->target_hs_clk_khz) {
1077                 tegra_dsi_set_dsi_clk(dc, dsi, dsi->target_hs_clk_khz);
1078                 tegra_dsi_set_timeout(dsi);
1079         }
1080
1081         tegra_dsi_set_phy_timing(dsi);
1082
1083         if (dsi->driven_mode == TEGRA_DSI_DRIVEN_BY_DC){
1084                 tegra_dsi_set_pkt_seq(dc, dsi);
1085                 tegra_dsi_set_pkt_length(dc, dsi);
1086                 tegra_dsi_set_sol_delay(dc, dsi);
1087                 tegra_dsi_set_dc_clk(dc, dsi);
1088         }
1089
1090         tegra_dsi_set_control_reg_hs(dsi);
1091
1092         if (dsi->status.clk_out == DSI_PHYCLK_OUT_DIS)
1093                 tegra_dsi_hs_clk_out_enable(dsi);
1094
1095         dsi->status.lphs = DSI_LPHS_IN_HS_MODE;
1096         err = 0;
1097 fail:
1098         return err;
1099 }
1100
1101 static bool tegra_dsi_is_controller_idle(struct tegra_dc_dsi_data *dsi)
1102 {
1103         u32 timeout = 0;
1104         bool retVal;
1105
1106         retVal = false;
1107         while (timeout <= DSI_MAX_COMMAND_DELAY_USEC) {
1108                 if (!tegra_dsi_readl(dsi, DSI_TRIGGER)) {
1109                         retVal = true;
1110                         break;
1111                 }
1112                 udelay(DSI_COMMAND_DELAY_STEPS_USEC);
1113                 timeout += DSI_COMMAND_DELAY_STEPS_USEC;
1114         }
1115
1116         return retVal;
1117 }
1118
1119 static bool tegra_dsi_host_trigger(struct tegra_dc_dsi_data *dsi)
1120 {
1121         bool status;
1122
1123         status = false;
1124         if (tegra_dsi_readl(dsi, DSI_TRIGGER))
1125                 goto fail;
1126
1127         tegra_dsi_writel(dsi, DSI_TRIGGER_HOST_TRIGGER(TEGRA_DSI_ENABLE),
1128                                                                 DSI_TRIGGER);
1129
1130 #if DSI_USE_SYNC_POINTS
1131         /* TODO: Implement sync point */
1132 #else
1133         status = tegra_dsi_is_controller_idle(dsi);
1134 #endif
1135
1136 fail:
1137         return status;
1138 }
1139
1140 static int _tegra_dsi_write_data(struct tegra_dc_dsi_data *dsi,
1141                                         u8* pdata, u8 data_id, u16 data_len)
1142 {
1143         u8 virtual_channel;
1144         u8 *pval;
1145         u32 val;
1146         int err;
1147
1148         err = 0;
1149
1150         virtual_channel = dsi->info.virtual_channel << DSI_VIR_CHANNEL_BIT_POSITION;
1151
1152         /* always use hw for ecc */
1153         val = (virtual_channel | data_id) << 0 |
1154                         data_len << 8;
1155         tegra_dsi_writel(dsi, val, DSI_WR_DATA);
1156
1157         /* if pdata != NULL, pkt type is long pkt */
1158         if (pdata != NULL) {
1159                 while (data_len) {
1160                         if (data_len >= 4) {
1161                                 val = ((u32*) pdata)[0];
1162                                 data_len -= 4;
1163                                 pdata += 4;
1164                         } else {
1165                                 val = 0;
1166                                 pval = (u8*) &val;
1167                                 do
1168                                         *pval++ = *pdata++;
1169                                 while(--data_len);
1170                         }
1171                         tegra_dsi_writel(dsi, val, DSI_WR_DATA);
1172                 }
1173         }
1174
1175         if (!tegra_dsi_host_trigger(dsi))
1176                 err = -EIO;
1177
1178         return err;
1179 }
1180
1181 static int tegra_dsi_write_data(struct tegra_dc *dc,
1182                                         struct tegra_dc_dsi_data *dsi,
1183                                         u8* pdata, u8 data_id, u16 data_len)
1184 {
1185         bool switch_back_to_hs_mode;
1186         bool switch_back_to_dc_mode;
1187         int err;
1188
1189         err = 0;
1190         switch_back_to_hs_mode = false;
1191         switch_back_to_dc_mode = false;
1192
1193         if ((dsi->status.init != DSI_MODULE_INIT) ||
1194                 (dsi->status.lphs == DSI_LPHS_NOT_INIT)) {
1195                 err = -EPERM;
1196                 goto fail;
1197         }
1198
1199         if (!tegra_dsi_is_controller_idle(dsi)) {
1200                 err = -EBUSY;
1201                 goto fail;
1202         }
1203
1204         err = 0;
1205
1206         if (dsi->status.lphs == DSI_LPHS_IN_HS_MODE) {
1207                 if (dsi->info.hs_cmd_mode_supported) {
1208                         if (dsi->status.driven == DSI_DRIVEN_MODE_DC) {
1209                                 dsi->driven_mode = TEGRA_DSI_DRIVEN_BY_HOST;
1210                                 tegra_dsi_set_to_hs_mode(dc, dsi);
1211                                 switch_back_to_dc_mode = true;
1212                         }
1213                 } else {
1214                         tegra_dsi_set_to_lp_mode(dc, dsi);
1215                         switch_back_to_hs_mode = true;
1216                 }
1217         }
1218
1219         err = _tegra_dsi_write_data(dsi, pdata, data_id, data_len);
1220
1221
1222         if (switch_back_to_dc_mode)
1223                 dsi->driven_mode = TEGRA_DSI_DRIVEN_BY_DC;
1224         if (switch_back_to_dc_mode || switch_back_to_hs_mode)
1225                 tegra_dsi_set_to_hs_mode(dc, dsi);
1226
1227 fail:
1228         return err;
1229 }
1230
1231 static int tegra_dsi_send_panel_cmd(struct tegra_dc *dc,
1232                                                 struct tegra_dc_dsi_data *dsi,
1233                                                 struct tegra_dsi_cmd *cmd,
1234                                                 u32 n_cmd)
1235 {
1236         u32 i;
1237         int err;
1238
1239         err = 0;
1240         for (i = 0; i < n_cmd; i++) {
1241                 struct tegra_dsi_cmd *cur_cmd;
1242                 cur_cmd = &cmd[i];
1243
1244                 if (cur_cmd->cmd_type == TEGRA_DSI_DELAY_MS)
1245                         mdelay(cur_cmd->sp_len_dly.delay_ms);
1246                 else {
1247                         err = tegra_dsi_write_data(dc, dsi,
1248                                                 cur_cmd->pdata,
1249                                                 cur_cmd->data_id,
1250                                                 cur_cmd->sp_len_dly.data_len);
1251                         if (err < 0)
1252                                 break;
1253                 }
1254         }
1255         return err;
1256 }
1257
1258 static int tegra_dsi_bta(struct tegra_dc_dsi_data *dsi)
1259 {
1260         u32 val;
1261         u32 poll_time;
1262         int err;
1263
1264         poll_time = 0;
1265         err = 0;
1266
1267         val = tegra_dsi_readl(dsi, DSI_HOST_DSI_CONTROL);
1268         val |= DSI_HOST_DSI_CONTROL_IMM_BTA(TEGRA_DSI_ENABLE);
1269         tegra_dsi_writel(dsi, val, DSI_HOST_DSI_CONTROL);
1270
1271         while (poll_time <  DSI_STATUS_POLLING_DURATION_USEC) {
1272                 val = tegra_dsi_readl(dsi, DSI_HOST_DSI_CONTROL);
1273                 val &= DSI_HOST_DSI_CONTROL_IMM_BTA(TEGRA_DSI_ENABLE);
1274                 if (!val)
1275                         break;
1276                 udelay(DSI_STATUS_POLLING_DELAY_USEC);
1277                 poll_time += DSI_STATUS_POLLING_DELAY_USEC;
1278         }
1279         if (poll_time > DSI_STATUS_POLLING_DURATION_USEC)
1280                 err = -EBUSY;
1281
1282         return err;
1283 }
1284
1285 static void tegra_dsi_read_fifo(struct tegra_dc *dc,
1286                         struct tegra_dc_dsi_data *dsi,
1287                         u32 rd_fifo_cnt,
1288                         u8 *read_fifo)
1289 {
1290         u32 val;
1291         u32 i;
1292
1293         /* Read data from FIFO */
1294         for (i = 0; i < rd_fifo_cnt; i++) {
1295                 val = tegra_dsi_readl(dsi, DSI_RD_DATA);
1296                 printk(KERN_INFO "Read data[%d]: 0x%x\n", i, val);
1297                 memcpy(read_fifo, &val, 4);
1298                 read_fifo += 4;
1299         }
1300
1301         /* Make sure all the data is read from the FIFO */
1302         val = tegra_dsi_readl(dsi, DSI_STATUS);
1303         val &= DSI_STATUS_RD_FIFO_COUNT(0x1f);
1304         if (val)
1305                 dev_err(&dc->ndev->dev, "DSI FIFO_RD_CNT not zero"
1306                 " even after reading FIFO_RD_CNT words from read fifo\n");
1307 }
1308
1309 static int tegra_dsi_parse_read_response(struct tegra_dc *dc,
1310                                 u32 rd_fifo_cnt, u8 *read_fifo)
1311 {
1312         int err;
1313         u32 payload_size;
1314
1315         payload_size = 0;
1316         err = 0;
1317
1318         printk(KERN_INFO "escape sequence[0x%x]\n", read_fifo[0]);
1319         switch (read_fifo[4] & 0xff) {
1320         case GEN_LONG_RD_RES:
1321                 /* Fall through */
1322         case DCS_LONG_RD_RES:
1323                 payload_size = (read_fifo[5] |
1324                                 (read_fifo[6] << 8)) & 0xFFFF;
1325                 printk(KERN_INFO "Long read response Packet\n"
1326                                 "payload_size[0x%x]\n", payload_size);
1327                 break;
1328         case GEN_1_BYTE_SHORT_RD_RES:
1329                 /* Fall through */
1330         case DCS_1_BYTE_SHORT_RD_RES:
1331                 payload_size = 1;
1332                 printk(KERN_INFO "Short read response Packet\n"
1333                         "payload_size[0x%x]\n", payload_size);
1334                 break;
1335         case GEN_2_BYTE_SHORT_RD_RES:
1336                 /* Fall through */
1337         case DCS_2_BYTE_SHORT_RD_RES:
1338                 payload_size = 2;
1339                 printk(KERN_INFO "Short read response Packet\n"
1340                         "payload_size[0x%x]\n", payload_size);
1341                 break;
1342         case ACK_ERR_RES:
1343                 payload_size = 2;
1344                 printk(KERN_INFO "Acknowledge error report response\n"
1345                         "Packet payload_size[0x%x]\n", payload_size);
1346                 break;
1347         default:
1348                 /*reading from RD_FIFO_COUNT*/
1349                 printk(KERN_INFO "Invalid read response payload_size\n");
1350                 err = -EINVAL;
1351                 break;
1352         }
1353         return err;
1354 }
1355
1356 static int tegra_dsi_read_data(struct tegra_dc *dc,
1357                                 struct tegra_dc_dsi_data *dsi,
1358                                 u32 max_ret_payload_size,
1359                                 u32 panel_reg_addr, u8 *read_data)
1360 {
1361         u32 val;
1362         int err;
1363         u32 poll_time;
1364         u32 rd_fifo_cnt;
1365         bool switch_back_to_hs_mode;
1366         bool restart_dc_stream;
1367         bool switch_back_to_dc_mode;
1368
1369         err = 0;
1370         switch_back_to_hs_mode = false;
1371         restart_dc_stream = false;
1372         switch_back_to_dc_mode = false;
1373
1374         if ((dsi->status.init != DSI_MODULE_INIT) ||
1375                 (dsi->status.lphs == DSI_LPHS_NOT_INIT) ||
1376                 (dsi->status.driven == DSI_DRIVEN_MODE_NOT_INIT)) {
1377                 err = -EPERM;
1378                 goto fail;
1379         }
1380
1381         val = tegra_dsi_readl(dsi, DSI_STATUS);
1382         val &= DSI_STATUS_RD_FIFO_COUNT(0x1f);
1383         if (val) {
1384                 err = -EBUSY;
1385                 dev_err(&dc->ndev->dev, "DSI fifo count not zero\n");
1386                 goto fail;
1387         }
1388
1389         if (!tegra_dsi_is_controller_idle(dsi)) {
1390                 err = -EBUSY;
1391                 dev_err(&dc->ndev->dev, "DSI trigger bit is already set\n");
1392                 goto fail;
1393         }
1394
1395         if (dsi->status.lphs == DSI_LPHS_IN_HS_MODE) {
1396                 if (dsi->status.driven == DSI_DRIVEN_MODE_DC) {
1397                         if (dsi->status.dc_stream == DSI_DC_STREAM_ENABLE)
1398                                 restart_dc_stream = true;
1399                         dsi->driven_mode = TEGRA_DSI_DRIVEN_BY_HOST;
1400                         switch_back_to_dc_mode = true;
1401                         if (dsi->info.hs_cmd_mode_supported) {
1402                                 err = tegra_dsi_set_to_hs_mode(dc, dsi);
1403                                 if (err < 0) {
1404                                         dev_err(&dc->ndev->dev,
1405                                         "DSI failed to go to HS mode host driven\n");
1406                                         goto fail;
1407                                 }
1408                         }
1409                 }
1410                 if (!dsi->info.hs_cmd_mode_supported) {
1411                         err = tegra_dsi_set_to_lp_mode(dc, dsi);
1412                         if (err < 0) {
1413                                 dev_err(&dc->ndev->dev,
1414                                 "DSI failed to go to LP mode\n");
1415                                 goto fail;
1416                         }
1417                         switch_back_to_hs_mode = true;
1418                 }
1419         }
1420
1421         /* Set max return payload size in words */
1422         err = _tegra_dsi_write_data(dsi, NULL,
1423                 dsi_command_max_return_pkt_size,
1424                 max_ret_payload_size);
1425         if (err < 0) {
1426                 dev_err(&dc->ndev->dev,
1427                                 "DSI write failed\n");
1428                 goto fail;
1429         }
1430
1431         /* DCS to read given panel register */
1432         err = _tegra_dsi_write_data(dsi, NULL,
1433                 dsi_command_dcs_read_with_no_params,
1434                 panel_reg_addr);
1435         if (err < 0) {
1436                 dev_err(&dc->ndev->dev,
1437                                 "DSI write failed\n");
1438                 goto fail;
1439         }
1440
1441         err = tegra_dsi_bta(dsi);
1442         if (err < 0) {
1443                 dev_err(&dc->ndev->dev,
1444                         "DSI IMM BTA timeout\n");
1445                 goto fail;
1446         }
1447
1448         poll_time = 0;
1449         while (poll_time <  DSI_DELAY_FOR_READ_FIFO) {
1450                 mdelay(1);
1451                 val = tegra_dsi_readl(dsi, DSI_STATUS);
1452                 rd_fifo_cnt = val & DSI_STATUS_RD_FIFO_COUNT(0x1f);
1453                 if (rd_fifo_cnt << 2 > DSI_READ_FIFO_DEPTH)
1454                         dev_err(&dc->ndev->dev,
1455                         "DSI RD_FIFO_CNT is greater than RD_FIFO_DEPTH\n");
1456                         break;
1457                 poll_time++;
1458         }
1459
1460         if (rd_fifo_cnt == 0) {
1461                 dev_info(&dc->ndev->dev,
1462                         "DSI RD_FIFO_CNT is zero\n");
1463                 err = -EINVAL;
1464                 goto fail;
1465         }
1466
1467         if (val & DSI_STATUS_LB_UNDERFLOW(0x1) ||
1468                 val & DSI_STATUS_LB_OVERFLOW(0x1)) {
1469                 dev_err(&dc->ndev->dev,
1470                         "DSI overflow/underflow error\n");
1471                 err = -EINVAL;
1472                 goto fail;
1473         }
1474
1475         tegra_dsi_read_fifo(dc, dsi, rd_fifo_cnt, read_data);
1476
1477         err = tegra_dsi_parse_read_response(dc, rd_fifo_cnt, read_data);
1478 fail:
1479         if (switch_back_to_dc_mode)
1480                 dsi->driven_mode = TEGRA_DSI_DRIVEN_BY_DC;
1481         if (switch_back_to_dc_mode || switch_back_to_hs_mode)
1482                 tegra_dsi_set_to_hs_mode(dc, dsi);
1483         if (restart_dc_stream)
1484                 tegra_dsi_start_dc_stream(dc, dsi);
1485
1486         return err;
1487 }
1488
1489 static void tegra_dsi_enter_ulpm(struct tegra_dc_dsi_data *dsi)
1490 {
1491         u32 val;
1492
1493         val = tegra_dsi_readl(dsi, DSI_HOST_DSI_CONTROL);
1494         val &= ~DSI_HOST_DSI_CONTROL_ULTRA_LOW_POWER(3);
1495         val |= DSI_HOST_DSI_CONTROL_ULTRA_LOW_POWER(ENTER_ULPM);
1496         tegra_dsi_writel(dsi, val, DSI_HOST_DSI_CONTROL);
1497
1498         dsi->ulpm = true;
1499 }
1500
1501 static void tegra_dsi_exit_ulpm(struct tegra_dc_dsi_data *dsi)
1502 {
1503         u32 val;
1504
1505         val = tegra_dsi_readl(dsi, DSI_HOST_DSI_CONTROL);
1506         val &= ~DSI_HOST_DSI_CONTROL_ULTRA_LOW_POWER(3);
1507         val |= DSI_HOST_DSI_CONTROL_ULTRA_LOW_POWER(EXIT_ULPM);
1508         tegra_dsi_writel(dsi, val, DSI_HOST_DSI_CONTROL);
1509
1510         val &= ~DSI_HOST_DSI_CONTROL_ULTRA_LOW_POWER(3);
1511         val |= DSI_HOST_DSI_CONTROL_ULTRA_LOW_POWER(NORMAL);
1512         tegra_dsi_writel(dsi, val, DSI_HOST_DSI_CONTROL);
1513
1514         /* TODO: Find exact delay required */
1515         mdelay(5);
1516         dsi->ulpm = false;
1517 }
1518
1519 static void tegra_dc_dsi_enable(struct tegra_dc *dc)
1520 {
1521         struct tegra_dc_dsi_data *dsi = tegra_dc_get_outdata(dc);
1522         int err;
1523
1524         tegra_dc_io_start(dc);
1525         mutex_lock(&dsi->lock);
1526
1527         if (dsi->ulpm) {
1528                 tegra_dsi_exit_ulpm(dsi);
1529                 if (dsi->info.panel_reset) {
1530                         err = tegra_dsi_send_panel_cmd(dc, dsi,
1531                                                         dsi->info.dsi_init_cmd,
1532                                                         dsi->info.n_init_cmd);
1533                         if (err < 0) {
1534                                 dev_err(&dc->ndev->dev,
1535                                 "dsi: error while sending dsi init cmd\n");
1536                                 return;
1537                         }
1538                 }
1539         } else {
1540                 err = tegra_dsi_init_hw(dc, dsi);
1541                 if (err < 0) {
1542                         dev_err(&dc->ndev->dev,
1543                                 "dsi: not able to init dsi hardware\n");
1544                         return;
1545                 }
1546
1547                 err = tegra_dsi_set_to_lp_mode(dc, dsi);
1548                 if (err < 0) {
1549                         dev_err(&dc->ndev->dev,
1550                                 "dsi: not able to set to lp mode\n");
1551                         return;
1552                 }
1553
1554                 err = tegra_dsi_send_panel_cmd(dc, dsi, dsi->info.dsi_init_cmd,
1555                                                 dsi->info.n_init_cmd);
1556                 if (err < 0) {
1557                         dev_err(&dc->ndev->dev,
1558                                 "dsi: error while sending dsi init cmd\n");
1559                         return;
1560                 }
1561
1562                 err = tegra_dsi_set_to_hs_mode(dc, dsi);
1563                 if (err < 0) {
1564                                 dev_err(&dc->ndev->dev,
1565                                         "dsi: not able to set to hs mode\n");
1566                         return;
1567                 }
1568         }
1569
1570         if (dsi->status.driven == DSI_DRIVEN_MODE_DC) {
1571                 tegra_dsi_start_dc_stream(dc, dsi);
1572         }
1573
1574         mutex_unlock(&dsi->lock);
1575         tegra_dc_io_end(dc);
1576 }
1577
1578 static void _tegra_dc_dsi_init(struct tegra_dc *dc)
1579 {
1580         struct tegra_dc_dsi_data *dsi = tegra_dc_get_outdata(dc);
1581
1582         tegra_dsi_init_sw(dc, dsi);
1583         /* TODO: Configure the CSI pad configuration */
1584 }
1585
1586 static int tegra_dc_dsi_cp_p_cmd(struct tegra_dsi_cmd* src,
1587                                         struct tegra_dsi_cmd* dst, u16 n_cmd)
1588 {
1589         u16 i;
1590         u16 len;
1591
1592         memcpy(dst, src, sizeof(*dst) * n_cmd);
1593
1594         for (i = 0; i < n_cmd; i++)
1595                 if (src[i].pdata) {
1596                         len = sizeof(*src[i].pdata) * src[i].sp_len_dly.data_len;
1597                         dst[i].pdata = kzalloc(len, GFP_KERNEL);
1598                         if (!dst[i].pdata)
1599                                 goto free_cmd_pdata;
1600                         memcpy(dst[i].pdata, src[i].pdata, len);
1601                 }
1602
1603         return 0;
1604
1605 free_cmd_pdata:
1606         for (--i; i >=0; i--)
1607                 if (dst[i].pdata)
1608                         kfree(dst[i].pdata);
1609         return -ENOMEM;
1610 }
1611
1612 static int tegra_dc_dsi_cp_info(struct tegra_dc_dsi_data* dsi,
1613                                                 struct tegra_dsi_out* p_dsi)
1614 {
1615         struct tegra_dsi_cmd* p_init_cmd;
1616         struct tegra_dsi_cmd *p_suspend_cmd;
1617         int err;
1618
1619         if (p_dsi->n_data_lanes > MAX_DSI_DATA_LANES)
1620                 return -EINVAL;
1621
1622         p_init_cmd = kzalloc(sizeof(*p_init_cmd) * p_dsi->n_init_cmd, GFP_KERNEL);
1623         if (!p_init_cmd)
1624                 return -ENOMEM;
1625
1626         p_suspend_cmd = kzalloc(sizeof(*p_suspend_cmd) * p_dsi->n_suspend_cmd,
1627                                 GFP_KERNEL);
1628         if (!p_suspend_cmd) {
1629                 err = -ENOMEM;
1630                 goto err_free_p_init_cmd;
1631         }
1632
1633         memcpy(&dsi->info, p_dsi, sizeof(dsi->info));
1634
1635         err = tegra_dc_dsi_cp_p_cmd(p_dsi->dsi_init_cmd,
1636                                                 p_init_cmd, p_dsi->n_init_cmd);
1637         if (err < 0)
1638                 goto err_free;
1639         dsi->info.dsi_init_cmd = p_init_cmd;
1640
1641         err = tegra_dc_dsi_cp_p_cmd(p_dsi->dsi_suspend_cmd, p_suspend_cmd,
1642                                         p_dsi->n_suspend_cmd);
1643         if (err < 0)
1644                 goto err_free;
1645         dsi->info.dsi_suspend_cmd = p_suspend_cmd;
1646
1647         if (!dsi->info.panel_reset_timeout_msec)
1648                 dsi->info.panel_reset_timeout_msec = DEFAULT_PANEL_RESET_TIMEOUT;
1649
1650         if (!dsi->info.panel_buffer_size_byte)
1651                 dsi->info.panel_buffer_size_byte = DEFAULT_PANEL_BUFFER_BYTE;
1652
1653         if (!dsi->info.max_panel_freq_khz)
1654                 dsi->info.max_panel_freq_khz = DEFAULT_MAX_DSI_PHY_CLK_KHZ;
1655
1656         if (!dsi->info.lp_cmd_mode_freq_khz)
1657                 dsi->info.lp_cmd_mode_freq_khz = DEFAULT_LP_CMD_MODE_CLK_KHZ;
1658
1659         /* host mode is for testing only*/
1660         dsi->driven_mode = TEGRA_DSI_DRIVEN_BY_DC;
1661
1662         return 0;
1663
1664 err_free:
1665         kfree(p_suspend_cmd);
1666 err_free_p_init_cmd:
1667         kfree(p_init_cmd);
1668         return err;
1669 }
1670
1671 static int tegra_dc_dsi_init(struct tegra_dc *dc)
1672 {
1673         struct tegra_dc_dsi_data *dsi;
1674         struct resource *res;
1675         struct resource *base_res;
1676         void __iomem *base;
1677         struct clk *dc_clk = NULL;
1678         struct clk *dsi_clk = NULL;
1679         struct tegra_dsi_out *dsi_pdata;
1680         int err;
1681
1682         err = 0;
1683
1684         dsi = kzalloc(sizeof(*dsi), GFP_KERNEL);
1685         if (!dsi)
1686                 return -ENOMEM;
1687
1688         res = nvhost_get_resource_byname(dc->ndev, IORESOURCE_MEM,
1689                                         "dsi_regs");
1690         if (!res) {
1691                 dev_err(&dc->ndev->dev, "dsi: no mem resource\n");
1692                 err = -ENOENT;
1693                 goto err_free_dsi;
1694         }
1695
1696         base_res = request_mem_region(res->start, resource_size(res),
1697                                 dc->ndev->name);
1698         if (!base_res) {
1699                 dev_err(&dc->ndev->dev, "dsi: request_mem_region failed\n");
1700                 err = -EBUSY;
1701                 goto err_free_dsi;
1702         }
1703
1704         base = ioremap(res->start, resource_size(res));
1705         if (!base) {
1706                 dev_err(&dc->ndev->dev, "dsi: registers can't be mapped\n");
1707                 err = -EBUSY;
1708                 goto err_release_regs;
1709         }
1710
1711         dsi_pdata = dc->pdata->default_out->dsi;
1712         if (!dsi_pdata) {
1713                 dev_err(&dc->ndev->dev, "dsi: dsi data not available\n");
1714                 goto err_release_regs;
1715         }
1716
1717         if (dsi_pdata->dsi_instance)
1718                 dsi_clk = clk_get(&dc->ndev->dev, "dsib");
1719         else
1720                 dsi_clk = clk_get(&dc->ndev->dev, "dsia");
1721
1722         if (IS_ERR_OR_NULL(dsi_clk)) {
1723                 dev_err(&dc->ndev->dev, "dsi: can't get clock\n");
1724                 err = -EBUSY;
1725                 goto err_release_regs;
1726         }
1727
1728         dc_clk = clk_get_sys(dev_name(&dc->ndev->dev), NULL);
1729         if (IS_ERR_OR_NULL(dc_clk)) {
1730                 dev_err(&dc->ndev->dev, "dsi: dc clock %s unavailable\n",
1731                         dev_name(&dc->ndev->dev));
1732                 err = -EBUSY;
1733                 goto err_clk_put;
1734         }
1735
1736         err = tegra_dc_dsi_cp_info(dsi, dsi_pdata);
1737         if (err < 0)
1738                 goto err_dsi_data;
1739
1740         mutex_init(&dsi->lock);
1741         dsi->dc = dc;
1742         dsi->base = base;
1743         dsi->base_res = base_res;
1744         dsi->dc_clk = dc_clk;
1745         dsi->dsi_clk = dsi_clk;
1746
1747         tegra_dc_set_outdata(dc, dsi);
1748         _tegra_dc_dsi_init(dc);
1749
1750         return 0;
1751
1752 err_dsi_data:
1753 err_clk_put:
1754         clk_put(dsi_clk);
1755 err_release_regs:
1756         release_resource(base_res);
1757 err_free_dsi:
1758         kfree(dsi);
1759
1760         return err;
1761 }
1762
1763 static void tegra_dc_dsi_destroy(struct tegra_dc *dc)
1764 {
1765         struct tegra_dc_dsi_data *dsi = tegra_dc_get_outdata(dc);
1766         u16 i;
1767         u32 val;
1768
1769         mutex_lock(&dsi->lock);
1770
1771         /* free up the pdata*/
1772         for(i = 0; i < dsi->info.n_init_cmd; i++){
1773                 if(dsi->info.dsi_init_cmd[i].pdata)
1774                         kfree(dsi->info.dsi_init_cmd[i].pdata);
1775         }
1776         kfree(dsi->info.dsi_init_cmd);
1777
1778         /* Disable dc stream*/
1779         if(dsi->status.dc_stream == DSI_DC_STREAM_ENABLE)
1780                 tegra_dsi_stop_dc_stream(dc, dsi);
1781
1782         /* Disable dsi phy clock*/
1783         if(dsi->status.clk_out == DSI_PHYCLK_OUT_EN)
1784                 tegra_dsi_hs_clk_out_disable(dc, dsi);
1785
1786         val = DSI_POWER_CONTROL_LEG_DSI_ENABLE(TEGRA_DSI_DISABLE);
1787         tegra_dsi_writel(dsi, val, DSI_POWER_CONTROL);
1788
1789         iounmap(dsi->base);
1790         release_resource(dsi->base_res);
1791
1792         clk_put(dsi->dc_clk);
1793         clk_put(dsi->dsi_clk);
1794
1795         mutex_unlock(&dsi->lock);
1796
1797         mutex_destroy(&dsi->lock);
1798         kfree(dsi);
1799 }
1800
1801 static void tegra_dc_dsi_disable(struct tegra_dc *dc)
1802 {
1803         struct tegra_dc_dsi_data *dsi = tegra_dc_get_outdata(dc);
1804
1805         mutex_lock(&dsi->lock);
1806
1807         if (dsi->status.dc_stream == DSI_DC_STREAM_ENABLE)
1808                 tegra_dsi_stop_dc_stream(dc, dsi);
1809
1810         if (!dsi->ulpm)
1811                 tegra_dsi_enter_ulpm(dsi);
1812
1813         mutex_unlock(&dsi->lock);
1814 }
1815
1816 #ifdef CONFIG_PM
1817 static void tegra_dc_dsi_suspend(struct tegra_dc *dc)
1818 {
1819         struct tegra_dc_dsi_data *dsi;
1820         int err;
1821
1822         dsi = tegra_dc_get_outdata(dc);
1823
1824         tegra_dc_io_start(dc);
1825         mutex_lock(&dsi->lock);
1826
1827         if (dsi->ulpm)
1828                 tegra_dsi_exit_ulpm(dsi);
1829
1830         err = tegra_dsi_send_panel_cmd(dc, dsi, dsi->info.dsi_suspend_cmd,
1831                                 dsi->info.n_suspend_cmd);
1832         if (err < 0) {
1833                 dev_err(&dc->ndev->dev,
1834                         "dsi: error while sending dsi suspend cmd\n");
1835                 return;
1836         }
1837
1838         clk_disable(dsi->dsi_clk);
1839
1840         mutex_unlock(&dsi->lock);
1841         tegra_dc_io_end(dc);
1842 }
1843
1844 static void tegra_dc_dsi_resume(struct tegra_dc *dc)
1845 {
1846         /* Not required since tegra_dc_dsi_enable
1847          * will reconfigure the controller from scratch
1848          */
1849 }
1850 #endif
1851
1852 struct tegra_dc_out_ops tegra_dc_dsi_ops = {
1853         .init = tegra_dc_dsi_init,
1854         .destroy = tegra_dc_dsi_destroy,
1855         .enable = tegra_dc_dsi_enable,
1856         .disable = tegra_dc_dsi_disable,
1857 #ifdef CONFIG_PM
1858         .suspend = tegra_dc_dsi_suspend,
1859         .resume = tegra_dc_dsi_resume,
1860 #endif
1861 };