video: dsi: tegra: Improve suspend code
[linux-2.6.git] / drivers / video / tegra / dc / dsi.c
1 /*
2  * drivers/video/tegra/dc/dsi.c
3  *
4  * Copyright (c) 2011, NVIDIA Corporation.
5  *
6  * This software is licensed under the terms of the GNU General Public
7  * License version 2, as published by the Free Software Foundation, and
8  * may be copied, distributed, and modified under those terms.
9  *
10  * This program is distributed in the hope that it will be useful,
11  * but WITHOUT ANY WARRANTY; without even the implied warranty of
12  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
13  * GNU General Public License for more details.
14  *
15  */
16
17 #include <linux/clk.h>
18 #include <linux/delay.h>
19 #include <linux/err.h>
20 #include <linux/fb.h>
21 #include <linux/gpio.h>
22 #include <linux/interrupt.h>
23 #include <linux/kernel.h>
24 #include <linux/slab.h>
25 #include <linux/spinlock.h>
26 #include <linux/workqueue.h>
27
28 #include <mach/clk.h>
29 #include <mach/dc.h>
30 #include <mach/fb.h>
31 #include <mach/nvhost.h>
32 #include <../gpio-names.h>
33
34 #include "dc_reg.h"
35 #include "dc_priv.h"
36 #include "dsi_regs.h"
37 #include "dsi.h"
38
39 #define DSI_USE_SYNC_POINTS 1
40
41 #define DSI_STOP_DC_DURATION_MSEC 1000
42
43 #define DSI_MODULE_NOT_INIT             0x0
44 #define DSI_MODULE_INIT                 0x1
45
46 #define DSI_LPHS_NOT_INIT               0x0
47 #define DSI_LPHS_IN_LP_MODE             0x1
48 #define DSI_LPHS_IN_HS_MODE             0x2
49
50 #define DSI_VIDEO_TYPE_NOT_INIT         0x0
51 #define DSI_VIDEO_TYPE_VIDEO_MODE       0x1
52 #define DSI_VIDEO_TYPE_CMD_MODE         0x2
53
54 #define DSI_DRIVEN_MODE_NOT_INIT        0x0
55 #define DSI_DRIVEN_MODE_DC              0x1
56 #define DSI_DRIVEN_MODE_HOST            0x2
57
58 #define DSI_PHYCLK_OUT_DIS              0x0
59 #define DSI_PHYCLK_OUT_EN               0x1
60
61 #define DSI_PHYCLK_NOT_INIT             0x0
62 #define DSI_PHYCLK_CONTINUOUS           0x1
63 #define DSI_PHYCLK_TX_ONLY              0x2
64
65 #define DSI_CLK_BURST_NOT_INIT          0x0
66 #define DSI_CLK_BURST_NONE_BURST        0x1
67 #define DSI_CLK_BURST_BURST_MODE        0x2
68
69 #define DSI_DC_STREAM_DISABLE           0x0
70 #define DSI_DC_STREAM_ENABLE            0x1
71
72 struct dsi_status {
73         unsigned        init:2;
74
75         unsigned        lphs:2;
76
77         unsigned        vtype:2;
78         unsigned        driven:2;
79
80         unsigned        clk_out:2;
81         unsigned        clk_mode:2;
82         unsigned        clk_burst:2;
83
84         unsigned        dc_stream:1;
85 };
86
87 /* source of video data */
88 enum{
89         TEGRA_DSI_DRIVEN_BY_DC,
90         TEGRA_DSI_DRIVEN_BY_HOST,
91 };
92
93 struct tegra_dc_dsi_data {
94         struct tegra_dc *dc;
95         void __iomem    *base;
96         struct resource *base_res;
97
98         struct clk              *dc_clk;
99         struct clk              *dsi_clk;
100
101         struct mutex    lock;
102
103         /* data from board info */
104         struct tegra_dsi_out info;
105
106         struct dsi_status       status;
107
108         u8              driven_mode;
109         u8              controller_index;
110
111         u8              pixel_scaler_mul;
112         u8              pixel_scaler_div;
113
114         u32             default_shift_clk_div;
115         u32             default_pixel_clk_khz;
116         u32             default_hs_clk_khz;
117
118         u32             shift_clk_div;
119         u32             target_hs_clk_khz;
120         u32             target_lp_clk_khz;
121
122         u32             syncpt_id;
123         u32             syncpt_val;
124
125         u16             current_bit_clk_ns;
126         u32             current_dsi_clk_khz;
127
128         u32             dsi_control_val;
129
130         bool            ulpm;
131         bool            enabled;
132 };
133
134 const u32 dsi_pkt_seq_reg[NUMOF_PKT_SEQ] = {
135         DSI_PKT_SEQ_0_LO,
136         DSI_PKT_SEQ_0_HI,
137         DSI_PKT_SEQ_1_LO,
138         DSI_PKT_SEQ_1_HI,
139         DSI_PKT_SEQ_2_LO,
140         DSI_PKT_SEQ_2_HI,
141         DSI_PKT_SEQ_3_LO,
142         DSI_PKT_SEQ_3_HI,
143         DSI_PKT_SEQ_4_LO,
144         DSI_PKT_SEQ_4_HI,
145         DSI_PKT_SEQ_5_LO,
146         DSI_PKT_SEQ_5_HI,
147 };
148
149 const u32 dsi_pkt_seq_video_non_burst_syne[NUMOF_PKT_SEQ] = {
150         PKT_ID0(CMD_VS) | PKT_LEN0(0) | PKT_ID1(CMD_EOT) | PKT_LEN1(0) | PKT_LP,
151         0,
152         PKT_ID0(CMD_VE) | PKT_LEN0(0) | PKT_ID1(CMD_EOT) | PKT_LEN1(0) | PKT_LP,
153         0,
154         PKT_ID0(CMD_HS) | PKT_LEN0(0) | PKT_ID1(CMD_EOT) | PKT_LEN1(0) | PKT_LP,
155         0,
156         PKT_ID0(CMD_HS) | PKT_LEN0(0) | PKT_ID1(CMD_BLNK) | PKT_LEN1(1) |
157                 PKT_ID2(CMD_HE) | PKT_LEN2(0),
158         PKT_ID3(CMD_BLNK) | PKT_LEN3(2) | PKT_ID4(CMD_RGB) | PKT_LEN4(3) |
159                 PKT_ID5(CMD_BLNK) | PKT_LEN5(4),
160         PKT_ID0(CMD_HS) | PKT_LEN0(0) | PKT_ID1(CMD_EOT) | PKT_LEN1(0) | PKT_LP,
161         0,
162         PKT_ID0(CMD_HS) | PKT_LEN0(0) | PKT_ID1(CMD_BLNK) | PKT_LEN1(1) |
163                 PKT_ID2(CMD_HE) | PKT_LEN2(0),
164         PKT_ID3(CMD_BLNK) | PKT_LEN3(2) | PKT_ID4(CMD_RGB) | PKT_LEN4(3) |
165                 PKT_ID5(CMD_BLNK) | PKT_LEN5(4),
166 };
167
168 const u32 dsi_pkt_seq_video_non_burst[NUMOF_PKT_SEQ] = {
169         PKT_ID0(CMD_VS) | PKT_LEN0(0) | PKT_ID1(CMD_EOT) | PKT_LEN1(0) | PKT_LP,
170         0,
171         PKT_ID0(CMD_HS) | PKT_LEN0(0) | PKT_ID1(CMD_EOT) | PKT_LEN1(0) | PKT_LP,
172         0,
173         PKT_ID0(CMD_HS) | PKT_LEN0(0) | PKT_ID1(CMD_EOT) | PKT_LEN1(0) | PKT_LP,
174         0,
175         PKT_ID0(CMD_HS) | PKT_LEN0(0) | PKT_ID1(CMD_BLNK) | PKT_LEN1(2) |
176                 PKT_ID2(CMD_RGB) | PKT_LEN2(3),
177         PKT_ID3(CMD_BLNK) | PKT_LEN3(4),
178         PKT_ID0(CMD_HS) | PKT_LEN0(0) | PKT_ID1(CMD_EOT) | PKT_LEN1(0) | PKT_LP,
179         0,
180         PKT_ID0(CMD_HS) | PKT_LEN0(0) | PKT_ID1(CMD_BLNK) | PKT_LEN1(2) |
181                 PKT_ID2(CMD_RGB) | PKT_LEN2(3),
182         PKT_ID3(CMD_BLNK) | PKT_LEN3(4),
183 };
184
185 static const u32 dsi_pkt_seq_video_burst[NUMOF_PKT_SEQ] = {
186         PKT_ID0(CMD_VS) | PKT_LEN0(0) | PKT_ID1(CMD_EOT) | PKT_LEN1(7) | PKT_LP,
187         0,
188         PKT_ID0(CMD_HS) | PKT_LEN0(0) | PKT_ID1(CMD_EOT) | PKT_LEN1(7) | PKT_LP,
189         0,
190         PKT_ID0(CMD_HS) | PKT_LEN0(0) | PKT_ID1(CMD_EOT) | PKT_LEN1(7) | PKT_LP,
191         0,
192         PKT_ID0(CMD_HS) | PKT_LEN0(0) | PKT_ID1(CMD_BLNK) | PKT_LEN1(2)|
193         PKT_ID2(CMD_RGB) | PKT_LEN2(3) | PKT_LP,
194         PKT_ID0(CMD_EOT) | PKT_LEN0(7),
195         PKT_ID0(CMD_HS) | PKT_LEN0(0) | PKT_ID1(CMD_EOT) | PKT_LEN1(7) | PKT_LP,
196         0,
197         PKT_ID0(CMD_HS) | PKT_LEN0(0) | PKT_ID1(CMD_BLNK) | PKT_LEN1(2)|
198         PKT_ID2(CMD_RGB) | PKT_LEN2(3) | PKT_LP,
199         PKT_ID0(CMD_EOT) | PKT_LEN0(7),
200 };
201
202 static const u32 dsi_pkt_seq_video_burst_no_eot[NUMOF_PKT_SEQ] = {
203         PKT_ID0(CMD_VS) | PKT_LEN0(0) | PKT_ID1(CMD_EOT) | PKT_LEN1(0) | PKT_LP,
204         0,
205         PKT_ID0(CMD_HS) | PKT_LEN0(0) | PKT_ID1(CMD_EOT) | PKT_LEN1(0) | PKT_LP,
206         0,
207         PKT_ID0(CMD_HS) | PKT_LEN0(0) | PKT_ID1(CMD_EOT) | PKT_LEN1(0) | PKT_LP,
208         0,
209         PKT_ID0(CMD_HS) | PKT_LEN0(0) | PKT_ID1(CMD_BLNK) | PKT_LEN1(2)|
210         PKT_ID2(CMD_RGB) | PKT_LEN2(3) | PKT_LP,
211         PKT_ID0(CMD_EOT) | PKT_LEN0(0),
212         PKT_ID0(CMD_HS) | PKT_LEN0(0) | PKT_ID1(CMD_EOT) | PKT_LEN1(0) | PKT_LP,
213         0,
214         PKT_ID0(CMD_HS) | PKT_LEN0(0) | PKT_ID1(CMD_BLNK) | PKT_LEN1(2)|
215         PKT_ID2(CMD_RGB) | PKT_LEN2(3) | PKT_LP,
216         PKT_ID0(CMD_EOT) | PKT_LEN0(0),
217 };
218
219 /* TODO: verify with hw about this format */
220 const u32 dsi_pkt_seq_cmd_mode [NUMOF_PKT_SEQ] = {
221         0,
222         0,
223         0,
224         0,
225         0,
226         0,
227         PKT_ID0(CMD_LONGW) | PKT_LEN0(3) | PKT_ID1(CMD_EOT) | PKT_LEN1(7),
228         0,
229         0,
230         0,
231         PKT_ID0(CMD_LONGW) | PKT_LEN0(3) | PKT_ID1(CMD_EOT) | PKT_LEN1(7),
232         0,
233 };
234
235 const u32 init_reg[] = {
236         DSI_WR_DATA,
237         DSI_INT_ENABLE,
238         DSI_INT_STATUS,
239         DSI_INT_MASK,
240         DSI_INIT_SEQ_DATA_0,
241         DSI_INIT_SEQ_DATA_1,
242         DSI_INIT_SEQ_DATA_2,
243         DSI_INIT_SEQ_DATA_3,
244         DSI_DCS_CMDS,
245         DSI_PKT_SEQ_0_LO,
246         DSI_PKT_SEQ_1_LO,
247         DSI_PKT_SEQ_2_LO,
248         DSI_PKT_SEQ_3_LO,
249         DSI_PKT_SEQ_4_LO,
250         DSI_PKT_SEQ_5_LO,
251         DSI_PKT_SEQ_0_HI,
252         DSI_PKT_SEQ_1_HI,
253         DSI_PKT_SEQ_2_HI,
254         DSI_PKT_SEQ_3_HI,
255         DSI_PKT_SEQ_4_HI,
256         DSI_PKT_SEQ_5_HI,
257         DSI_CONTROL,
258         DSI_HOST_DSI_CONTROL,
259         DSI_PAD_CONTROL,
260         DSI_PAD_CONTROL_CD,
261         DSI_SOL_DELAY,
262         DSI_MAX_THRESHOLD,
263         DSI_TRIGGER,
264         DSI_TX_CRC,
265         DSI_INIT_SEQ_CONTROL,
266         DSI_PKT_LEN_0_1,
267         DSI_PKT_LEN_2_3,
268         DSI_PKT_LEN_4_5,
269         DSI_PKT_LEN_6_7,
270 };
271
272 static inline unsigned long tegra_dsi_readl(struct tegra_dc_dsi_data *dsi,
273                                                                         u32 reg)
274 {
275         return readl(dsi->base + reg * 4);
276 }
277
278 static inline void tegra_dsi_writel(struct tegra_dc_dsi_data *dsi,u32 val,
279                                                                         u32 reg)
280 {
281         writel(val, dsi->base + reg * 4);
282 }
283
284 static int tegra_dsi_syncpt(struct tegra_dc_dsi_data *dsi)
285 {
286         u32 val;
287         int ret;
288
289         ret = 0;
290
291         dsi->syncpt_val = nvhost_syncpt_read(
292                         &dsi->dc->ndev->host->syncpt, dsi->syncpt_id);
293
294         val = DSI_INCR_SYNCPT_COND(OP_DONE) |
295                 DSI_INCR_SYNCPT_INDX(dsi->syncpt_id);
296         tegra_dsi_writel(dsi, val, DSI_INCR_SYNCPT);
297
298         /* TODO: Use interrupt rather than polling */
299         ret = nvhost_syncpt_wait(&dsi->dc->ndev->host->syncpt,
300                 dsi->syncpt_id, dsi->syncpt_val + 1);
301         if (ret < 0) {
302                 printk(KERN_ERR "DSI sync point failure\n");
303                 goto fail;
304         }
305
306         (dsi->syncpt_val)++;
307         return 0;
308 fail:
309         return ret;
310 }
311
312 static u32 tegra_dsi_get_hs_clk_rate(struct tegra_dc_dsi_data *dsi)
313 {
314         u32 dsi_clock_rate_khz;
315
316         switch (dsi->info.video_burst_mode) {
317         case TEGRA_DSI_VIDEO_BURST_MODE_LOW_SPEED:
318         case TEGRA_DSI_VIDEO_BURST_MODE_MEDIUM_SPEED:
319         case TEGRA_DSI_VIDEO_BURST_MODE_FAST_SPEED:
320         case TEGRA_DSI_VIDEO_BURST_MODE_FASTEST_SPEED:
321                 /* Calculate DSI HS clock rate for DSI burst mode */
322                 dsi_clock_rate_khz = dsi->default_pixel_clk_khz *
323                                                         dsi->shift_clk_div;
324                 break;
325         case TEGRA_DSI_VIDEO_NONE_BURST_MODE:
326         case TEGRA_DSI_VIDEO_NONE_BURST_MODE_WITH_SYNC_END:
327         case TEGRA_DSI_VIDEO_BURST_MODE_LOWEST_SPEED:
328         default:
329                 /* Clock rate is default DSI clock rate for non-burst mode */
330                 dsi_clock_rate_khz = dsi->default_hs_clk_khz;
331                 break;
332         }
333
334         return dsi_clock_rate_khz;
335 }
336
337 static u32 tegra_dsi_get_lp_clk_rate(struct tegra_dc_dsi_data *dsi)
338 {
339         u32 dsi_clock_rate_khz;
340
341         if (dsi->info.enable_hs_clock_on_lp_cmd_mode)
342                 if (dsi->info.hs_clk_in_lp_cmd_mode_freq_khz)
343                         dsi_clock_rate_khz =
344                                 dsi->info.hs_clk_in_lp_cmd_mode_freq_khz;
345                 else
346                         dsi_clock_rate_khz = tegra_dsi_get_hs_clk_rate(dsi);
347         else
348                 dsi_clock_rate_khz = dsi->info.lp_cmd_mode_freq_khz;
349
350         return dsi_clock_rate_khz;
351 }
352
353 static u32 tegra_dsi_get_shift_clk_div(struct tegra_dc_dsi_data *dsi)
354 {
355         u32 shift_clk_div;
356         u32 max_shift_clk_div;
357         u32 burst_width;
358         u32 burst_width_max;
359
360         /* Get the real value of default shift_clk_div. default_shift_clk_div
361          * holds the real value of shift_clk_div. */
362         shift_clk_div = dsi->default_shift_clk_div;
363
364         /* Calculate shift_clk_div which can matche the video_burst_mode.*/
365         if (dsi->info.video_burst_mode >=
366                         TEGRA_DSI_VIDEO_BURST_MODE_LOWEST_SPEED) {
367                 /* The max_shift_clk_div is multiplied by 10 to save the
368                  * fraction */
369                 if (dsi->info.max_panel_freq_khz >= dsi->default_hs_clk_khz)
370                         max_shift_clk_div = dsi->info.max_panel_freq_khz
371                                 * shift_clk_div * 10 / dsi->default_hs_clk_khz;
372                 else
373                         max_shift_clk_div = shift_clk_div * 10;
374
375                 burst_width = dsi->info.video_burst_mode
376                                 - TEGRA_DSI_VIDEO_BURST_MODE_LOWEST_SPEED;
377                 burst_width_max = TEGRA_DSI_VIDEO_BURST_MODE_FASTEST_SPEED
378                                 - TEGRA_DSI_VIDEO_BURST_MODE_LOWEST_SPEED;
379
380                 shift_clk_div = (max_shift_clk_div - shift_clk_div * 10) *
381                         burst_width / (burst_width_max * 10) + shift_clk_div;
382         }
383
384         return shift_clk_div;
385 }
386
387 static void tegra_dsi_init_sw(struct tegra_dc *dc,
388                                                 struct tegra_dc_dsi_data *dsi)
389 {
390         u32 h_width_pixels;
391         u32 v_width_lines;
392         u32 pixel_clk_hz;
393         u32 byte_clk_hz;
394         u32 plld_clk_mhz;
395
396         switch (dsi->info.pixel_format) {
397                 case TEGRA_DSI_PIXEL_FORMAT_16BIT_P:
398                         /* 2 bytes per pixel */
399                         dsi->pixel_scaler_mul = 2;
400                         dsi->pixel_scaler_div = 1;
401                         break;
402                 case TEGRA_DSI_PIXEL_FORMAT_18BIT_P:
403                         /* 2.25 bytes per pixel */
404                         dsi->pixel_scaler_mul = 9;
405                         dsi->pixel_scaler_div = 4;
406                         break;
407                 case TEGRA_DSI_PIXEL_FORMAT_18BIT_NP:
408                 case TEGRA_DSI_PIXEL_FORMAT_24BIT_P:
409                         /* 3 bytes per pixel */
410                         dsi->pixel_scaler_mul = 3;
411                         dsi->pixel_scaler_div = 1;
412                         break;
413                 default:
414                         break;
415         }
416
417         dsi->controller_index = dc->ndev->id;
418         dsi->ulpm = false;
419         dsi->enabled = false;
420
421         dsi->dsi_control_val =
422                         DSI_CONTROL_VIRTUAL_CHANNEL(dsi->info.virtual_channel) |
423                         DSI_CONTROL_NUM_DATA_LANES(dsi->info.n_data_lanes - 1) |
424                         DSI_CONTROL_VID_SOURCE(dsi->controller_index) |
425                         DSI_CONTROL_DATA_FORMAT(dsi->info.pixel_format);
426
427         /* Below we are going to calculate dsi and dc clock rate.
428          * Calcuate the horizontal and vertical width. */
429         h_width_pixels = dc->mode.h_back_porch + dc->mode.h_front_porch +
430                         dc->mode.h_sync_width + dc->mode.h_active;
431         v_width_lines = dc->mode.v_back_porch + dc->mode.v_front_porch +
432                         dc->mode.v_sync_width + dc->mode.v_active;
433
434         /* Calculate minimum required pixel rate. */
435         pixel_clk_hz = h_width_pixels * v_width_lines * dsi->info.refresh_rate;
436
437         /* Calculate minimum byte rate on DSI interface. */
438         byte_clk_hz = (pixel_clk_hz * dsi->pixel_scaler_mul) /
439                         (dsi->pixel_scaler_div * dsi->info.n_data_lanes);
440
441         /* Round up to multiple of mega hz. */
442         plld_clk_mhz = DIV_ROUND_UP((byte_clk_hz * NUMOF_BIT_PER_BYTE),
443                                                                 1000000);
444
445         /* Calculate default real shift_clk_div. */
446         dsi->default_shift_clk_div = (NUMOF_BIT_PER_BYTE / 2) *
447                 dsi->pixel_scaler_mul / (dsi->pixel_scaler_div *
448                 dsi->info.n_data_lanes);
449         /* Calculate default DSI hs clock. DSI interface is double data rate.
450          * Data is transferred on both rising and falling edge of clk, div by 2
451          * to get the actual clock rate.
452          * */
453         dsi->default_hs_clk_khz = plld_clk_mhz * 1000 / 2;
454         dsi->default_pixel_clk_khz = plld_clk_mhz * 1000 / 2
455                                                 / dsi->default_shift_clk_div;
456
457         /* Get the actual shift_clk_div and clock rates. */
458         dsi->shift_clk_div = tegra_dsi_get_shift_clk_div(dsi);
459         dsi->target_lp_clk_khz = tegra_dsi_get_lp_clk_rate(dsi);
460         dsi->target_hs_clk_khz = tegra_dsi_get_hs_clk_rate(dsi);
461
462         dev_info(&dc->ndev->dev, "DSI: HS clock rate is %d\n",
463                                                         dsi->target_hs_clk_khz);
464
465         dsi->controller_index = dc->ndev->id;
466         dsi->ulpm = false;
467
468 #if DSI_USE_SYNC_POINTS
469         dsi->syncpt_id = NVSYNCPT_DSI;
470 #endif
471
472         /*
473          * Force video clock to be continuous mode if
474          * enable_hs_clock_on_lp_cmd_mode is set
475          */
476         if (dsi->info.enable_hs_clock_on_lp_cmd_mode) {
477                 if (dsi->info.video_clock_mode != TEGRA_DSI_VIDEO_CLOCK_CONTINUOUS)
478                         printk("Force to clock continuous mode\n");
479
480                 dsi->info.video_clock_mode = TEGRA_DSI_VIDEO_CLOCK_CONTINUOUS;
481         }
482
483 }
484
485 static void tegra_dsi_get_phy_timing(struct tegra_dc_dsi_data *dsi,
486                                 struct dsi_phy_timing_inclk *phy_timing_clk,
487                                 u32 clk_ns)
488 {
489
490         phy_timing_clk->t_hsdexit = dsi->info.phy_timing.t_hsdexit_ns ?
491                         (dsi->info.phy_timing.t_hsdexit_ns / clk_ns) :
492                         (T_HSEXIT_DEFAULT(clk_ns));
493
494         phy_timing_clk->t_hstrail = dsi->info.phy_timing.t_hstrail_ns ?
495                         (dsi->info.phy_timing.t_hstrail_ns / clk_ns) :
496                         (T_HSTRAIL_DEFAULT(clk_ns));
497
498         phy_timing_clk->t_datzero = dsi->info.phy_timing.t_datzero_ns ?
499                         (dsi->info.phy_timing.t_datzero_ns / clk_ns) :
500                         (T_DATZERO_DEFAULT(clk_ns));
501
502         phy_timing_clk->t_hsprepr = dsi->info.phy_timing.t_hsprepr_ns ?
503                         (dsi->info.phy_timing.t_hsprepr_ns / clk_ns) :
504                         (T_HSPREPR_DEFAULT(clk_ns));
505
506         phy_timing_clk->t_clktrail = dsi->info.phy_timing.t_clktrail_ns ?
507                                 (dsi->info.phy_timing.t_clktrail_ns / clk_ns) :
508                                 (T_CLKTRAIL_DEFAULT(clk_ns));
509
510         phy_timing_clk->t_clkpost = dsi->info.phy_timing.t_clkpost_ns ?
511                                 (dsi->info.phy_timing.t_clkpost_ns / clk_ns) :
512                                 (T_CLKPOST_DEFAULT(clk_ns));
513
514         phy_timing_clk->t_clkzero = dsi->info.phy_timing.t_clkzero_ns ?
515                                 (dsi->info.phy_timing.t_clkzero_ns / clk_ns) :
516                                 (T_CLKZERO_DEFAULT(clk_ns));
517
518         phy_timing_clk->t_tlpx = dsi->info.phy_timing.t_tlpx_ns ?
519                                 (dsi->info.phy_timing.t_tlpx_ns / clk_ns) :
520                                 (T_TLPX_DEFAULT(clk_ns));
521
522         phy_timing_clk->t_clkpre = T_CLKPRE_DEFAULT(clk_ns);
523         phy_timing_clk->t_clkprepare = T_CLKPREPARE_DEFAULT(clk_ns);
524         phy_timing_clk->t_wakeup = T_WAKEUP_DEFAULT(clk_ns);
525
526         phy_timing_clk->t_taget = 5 * phy_timing_clk->t_tlpx;
527         phy_timing_clk->t_tasure = 2 * phy_timing_clk->t_tlpx;
528         phy_timing_clk->t_tago = 4 * phy_timing_clk->t_tlpx;
529 }
530
531 static void tegra_dsi_set_phy_timing(struct tegra_dc_dsi_data *dsi)
532 {
533         u32 val;
534         struct dsi_phy_timing_inclk     phy_timing;
535
536         tegra_dsi_get_phy_timing(dsi, &phy_timing, dsi->current_bit_clk_ns);
537
538         val = DSI_PHY_TIMING_0_THSDEXIT(phy_timing.t_hsdexit) |
539                         DSI_PHY_TIMING_0_THSTRAIL(phy_timing.t_hstrail) |
540                         DSI_PHY_TIMING_0_TDATZERO(phy_timing.t_datzero) |
541                         DSI_PHY_TIMING_0_THSPREPR(phy_timing.t_hsprepr);
542         tegra_dsi_writel(dsi, val, DSI_PHY_TIMING_0);
543
544         val = DSI_PHY_TIMING_1_TCLKTRAIL(phy_timing.t_clktrail) |
545                         DSI_PHY_TIMING_1_TCLKPOST(phy_timing.t_clkpost) |
546                         DSI_PHY_TIMING_1_TCLKZERO(phy_timing.t_clkzero) |
547                         DSI_PHY_TIMING_1_TTLPX(phy_timing.t_tlpx);
548         tegra_dsi_writel(dsi, val, DSI_PHY_TIMING_1);
549
550         val = DSI_PHY_TIMING_2_TCLKPREPARE(phy_timing.t_clkprepare) |
551                 DSI_PHY_TIMING_2_TCLKPRE(phy_timing.t_clkpre) |
552                         DSI_PHY_TIMING_2_TWAKEUP(phy_timing.t_wakeup);
553         tegra_dsi_writel(dsi, val, DSI_PHY_TIMING_2);
554
555         val = DSI_BTA_TIMING_TTAGET(phy_timing.t_taget) |
556                         DSI_BTA_TIMING_TTASURE(phy_timing.t_tasure) |
557                         DSI_BTA_TIMING_TTAGO(phy_timing.t_tago);
558         tegra_dsi_writel(dsi, val, DSI_BTA_TIMING);
559 }
560
561 static u32 tegra_dsi_sol_delay_burst(struct tegra_dc *dc,
562                                                 struct tegra_dc_dsi_data *dsi)
563 {
564         u32 dsi_to_pixel_clk_ratio;
565         u32 temp;
566         u32 temp1;
567         u32 mipi_clk_adj_kHz;
568         u32 sol_delay;
569         struct tegra_dc_mode *dc_modes = &dc->mode;
570
571         /* Get Fdsi/Fpixel ration (note: Fdsi si in bit format) */
572         dsi_to_pixel_clk_ratio = (dsi->current_dsi_clk_khz * 2 +
573                 dsi->default_pixel_clk_khz - 1) / dsi->default_pixel_clk_khz;
574
575         /* Convert Fdsi to byte format */
576         dsi_to_pixel_clk_ratio *= 1000/8;
577
578         /* Multiplying by 1000 so that we don't loose the fraction part */
579         temp = dc_modes->h_active * 1000;
580         temp1 = dc_modes->h_active + dc_modes->h_back_porch +
581                         dc_modes->h_sync_width;
582
583         sol_delay = temp1 * dsi_to_pixel_clk_ratio -
584                         temp * dsi->pixel_scaler_mul /
585                         (dsi->pixel_scaler_div * dsi->info.n_data_lanes);
586
587         /* Do rounding on sol delay */
588         sol_delay = (sol_delay + 1000 - 1)/1000;
589
590         /* TODO:
591          * 1. find out the correct sol fifo depth to use
592          * 2. verify with hw about the clamping function
593          */
594         if (sol_delay > (480 * 4)) {
595                 sol_delay = (480 * 4);
596                 mipi_clk_adj_kHz = sol_delay +
597                         (dc_modes->h_active * dsi->pixel_scaler_mul) /
598                         (dsi->info.n_data_lanes * dsi->pixel_scaler_div);
599
600                 mipi_clk_adj_kHz *= (dsi->default_pixel_clk_khz / temp1);
601
602                 mipi_clk_adj_kHz *= 4;
603         }
604
605         dsi->target_hs_clk_khz = mipi_clk_adj_kHz;
606
607         return sol_delay;
608 }
609
610 static void tegra_dsi_set_sol_delay(struct tegra_dc *dc,
611                                                 struct tegra_dc_dsi_data *dsi)
612 {
613         u32 sol_delay;
614
615         if (dsi->info.video_burst_mode == TEGRA_DSI_VIDEO_NONE_BURST_MODE ||
616                 dsi->info.video_burst_mode ==
617                                 TEGRA_DSI_VIDEO_NONE_BURST_MODE_WITH_SYNC_END) {
618                 sol_delay = NUMOF_BIT_PER_BYTE * dsi->pixel_scaler_mul /
619                         (dsi->pixel_scaler_div * dsi->info.n_data_lanes);
620                 dsi->status.clk_burst = DSI_CLK_BURST_NONE_BURST;
621         } else {
622                 sol_delay = tegra_dsi_sol_delay_burst(dc, dsi);
623                 dsi->status.clk_burst = DSI_CLK_BURST_BURST_MODE;
624         }
625
626         tegra_dsi_writel(dsi, DSI_SOL_DELAY_SOL_DELAY(sol_delay),
627                                                                 DSI_SOL_DELAY);
628 }
629
630 static void tegra_dsi_set_timeout(struct tegra_dc_dsi_data *dsi)
631 {
632         u32 val;
633         u32 bytes_per_frame;
634         u32 timeout = 0;
635
636         /* TODO: verify the following eq */
637         bytes_per_frame = dsi->current_dsi_clk_khz * 1000 * 2 /
638                                                 (dsi->info.refresh_rate * 8);
639         timeout = bytes_per_frame / DSI_CYCLE_COUNTER_VALUE;
640         timeout = (timeout + DSI_HTX_TO_MARGIN) & 0xffff;
641
642         val = DSI_TIMEOUT_0_LRXH_TO(DSI_LRXH_TO_VALUE) |
643                         DSI_TIMEOUT_0_HTX_TO(timeout);
644         tegra_dsi_writel(dsi, val, DSI_TIMEOUT_0);
645
646         if (dsi->info.panel_reset_timeout_msec)
647                 timeout = (dsi->info.panel_reset_timeout_msec * 1000*1000)
648                                         / dsi->current_bit_clk_ns;
649         else
650                 timeout = DSI_PR_TO_VALUE;
651
652         val = DSI_TIMEOUT_1_PR_TO(timeout) |
653                 DSI_TIMEOUT_1_TA_TO(DSI_TA_TO_VALUE);
654         tegra_dsi_writel(dsi, val, DSI_TIMEOUT_1);
655
656         val = DSI_TO_TALLY_P_RESET_STATUS(IN_RESET) |
657                 DSI_TO_TALLY_TA_TALLY(DSI_TA_TALLY_VALUE)|
658                 DSI_TO_TALLY_LRXH_TALLY(DSI_LRXH_TALLY_VALUE)|
659                 DSI_TO_TALLY_HTX_TALLY(DSI_HTX_TALLY_VALUE);
660         tegra_dsi_writel(dsi, val, DSI_TO_TALLY);
661 }
662
663 static void tegra_dsi_setup_video_mode_pkt_length(struct tegra_dc *dc,
664                                                 struct tegra_dc_dsi_data *dsi)
665 {
666         u32 val;
667         u32 hact_pkt_len;
668         u32 hsa_pkt_len;
669         u32 hbp_pkt_len;
670         u32 hfp_pkt_len;
671
672         hact_pkt_len = dc->mode.h_active * dsi->pixel_scaler_mul /
673                                                         dsi->pixel_scaler_div;
674         hsa_pkt_len = dc->mode.h_sync_width * dsi->pixel_scaler_mul /
675                                                         dsi->pixel_scaler_div;
676         hbp_pkt_len = dc->mode.h_back_porch * dsi->pixel_scaler_mul /
677                                                         dsi->pixel_scaler_div;
678         hfp_pkt_len = dc->mode.h_front_porch * dsi->pixel_scaler_mul /
679                                                         dsi->pixel_scaler_div;
680
681         if (dsi->info.video_burst_mode !=
682                                 TEGRA_DSI_VIDEO_NONE_BURST_MODE_WITH_SYNC_END)
683                 hbp_pkt_len += hsa_pkt_len;
684
685         hsa_pkt_len -= DSI_HSYNC_BLNK_PKT_OVERHEAD;
686         hbp_pkt_len -= DSI_HBACK_PORCH_PKT_OVERHEAD;
687         hfp_pkt_len -= DSI_HFRONT_PORCH_PKT_OVERHEAD;
688
689         val = DSI_PKT_LEN_0_1_LENGTH_0(0) | DSI_PKT_LEN_0_1_LENGTH_1(hsa_pkt_len);
690         tegra_dsi_writel(dsi, val, DSI_PKT_LEN_0_1);
691
692         val = DSI_PKT_LEN_2_3_LENGTH_2(hbp_pkt_len) |
693                         DSI_PKT_LEN_2_3_LENGTH_3(hact_pkt_len);
694         tegra_dsi_writel(dsi, val, DSI_PKT_LEN_2_3);
695
696         val = DSI_PKT_LEN_4_5_LENGTH_4(hfp_pkt_len) | DSI_PKT_LEN_4_5_LENGTH_5(0);
697         tegra_dsi_writel(dsi, val, DSI_PKT_LEN_4_5);
698
699         val = DSI_PKT_LEN_6_7_LENGTH_6(0) | DSI_PKT_LEN_6_7_LENGTH_7(0);
700         tegra_dsi_writel(dsi, val, DSI_PKT_LEN_6_7);
701 }
702
703 static void tegra_dsi_setup_cmd_mode_pkt_length(struct tegra_dc *dc,
704                                                 struct tegra_dc_dsi_data *dsi)
705 {
706         unsigned long   val;
707         unsigned long   act_bytes;
708
709         act_bytes = dc->mode.h_active * dsi->pixel_scaler_mul /
710                         dsi->pixel_scaler_div + 1;
711
712         val = DSI_PKT_LEN_0_1_LENGTH_0(0) | DSI_PKT_LEN_0_1_LENGTH_1(0);
713         tegra_dsi_writel(dsi, val, DSI_PKT_LEN_0_1);
714
715         val = DSI_PKT_LEN_2_3_LENGTH_2(0) | DSI_PKT_LEN_2_3_LENGTH_3(act_bytes);
716         tegra_dsi_writel(dsi, val, DSI_PKT_LEN_2_3);
717
718         val = DSI_PKT_LEN_4_5_LENGTH_4(0) | DSI_PKT_LEN_4_5_LENGTH_5(act_bytes);
719         tegra_dsi_writel(dsi, val, DSI_PKT_LEN_4_5);
720
721         val = DSI_PKT_LEN_6_7_LENGTH_6(0) | DSI_PKT_LEN_6_7_LENGTH_7(0x0f0f);
722         tegra_dsi_writel(dsi, val, DSI_PKT_LEN_6_7);
723 }
724
725 static void tegra_dsi_set_pkt_length(struct tegra_dc *dc,
726                                                 struct tegra_dc_dsi_data *dsi)
727 {
728         if (dsi->driven_mode == TEGRA_DSI_DRIVEN_BY_HOST)
729                 return;
730
731         if (dsi->info.video_data_type == TEGRA_DSI_VIDEO_TYPE_VIDEO_MODE)
732                 tegra_dsi_setup_video_mode_pkt_length(dc, dsi);
733         else
734                 tegra_dsi_setup_cmd_mode_pkt_length(dc, dsi);
735 }
736
737 static void tegra_dsi_set_pkt_seq(struct tegra_dc *dc,
738                                                 struct tegra_dc_dsi_data *dsi)
739 {
740         const u32 *pkt_seq;
741         u32 rgb_info;
742         u32 pkt_seq_3_5_rgb_lo;
743         u32 pkt_seq_3_5_rgb_hi;
744         u32     val;
745         u32 reg;
746         u8  i;
747
748         if (dsi->driven_mode == TEGRA_DSI_DRIVEN_BY_HOST)
749                 return;
750
751         switch(dsi->info.pixel_format) {
752         case TEGRA_DSI_PIXEL_FORMAT_16BIT_P:
753                 rgb_info = CMD_RGB_16BPP;
754                 break;
755         case TEGRA_DSI_PIXEL_FORMAT_18BIT_P:
756                 rgb_info = CMD_RGB_18BPP;
757                 break;
758         case TEGRA_DSI_PIXEL_FORMAT_18BIT_NP:
759                 rgb_info = CMD_RGB_18BPPNP;
760                 break;
761         case TEGRA_DSI_PIXEL_FORMAT_24BIT_P:
762         default:
763                 rgb_info = CMD_RGB_24BPP;
764                 break;
765         }
766
767         pkt_seq_3_5_rgb_lo = 0;
768         pkt_seq_3_5_rgb_hi = 0;
769         if (dsi->info.video_data_type == TEGRA_DSI_VIDEO_TYPE_COMMAND_MODE)
770                 pkt_seq = dsi_pkt_seq_cmd_mode;
771         else {
772                 switch (dsi->info.video_burst_mode) {
773                 case TEGRA_DSI_VIDEO_BURST_MODE_LOWEST_SPEED:
774                 case TEGRA_DSI_VIDEO_BURST_MODE_LOW_SPEED:
775                 case TEGRA_DSI_VIDEO_BURST_MODE_MEDIUM_SPEED:
776                 case TEGRA_DSI_VIDEO_BURST_MODE_FAST_SPEED:
777                 case TEGRA_DSI_VIDEO_BURST_MODE_FASTEST_SPEED:
778                         pkt_seq_3_5_rgb_lo = DSI_PKT_SEQ_3_LO_PKT_32_ID(rgb_info);
779                         if(!dsi->info.no_pkt_seq_eot)
780                                 pkt_seq = dsi_pkt_seq_video_burst;
781                         else
782                                 pkt_seq = dsi_pkt_seq_video_burst_no_eot;
783                         break;
784                 case TEGRA_DSI_VIDEO_NONE_BURST_MODE_WITH_SYNC_END:
785                         pkt_seq_3_5_rgb_hi = DSI_PKT_SEQ_3_HI_PKT_34_ID(rgb_info);
786                         pkt_seq = dsi_pkt_seq_video_non_burst_syne;
787                         break;
788                 case TEGRA_DSI_VIDEO_NONE_BURST_MODE:
789                 default:
790                         pkt_seq_3_5_rgb_lo = DSI_PKT_SEQ_3_LO_PKT_32_ID(rgb_info);
791                         pkt_seq = dsi_pkt_seq_video_non_burst;
792                         break;
793                 }
794         }
795
796         for (i = 0; i < NUMOF_PKT_SEQ; i++) {
797                 val = pkt_seq[i];
798                 reg = dsi_pkt_seq_reg[i];
799                 if ((reg == DSI_PKT_SEQ_3_LO) || (reg == DSI_PKT_SEQ_5_LO))
800                         val |= pkt_seq_3_5_rgb_lo;
801                 if ((reg == DSI_PKT_SEQ_3_HI) || (reg == DSI_PKT_SEQ_5_HI))
802                         val |= pkt_seq_3_5_rgb_hi;
803                 tegra_dsi_writel(dsi, val, reg);
804         }
805 }
806
807 static void tegra_dsi_stop_dc_stream(struct tegra_dc *dc,
808                                                 struct tegra_dc_dsi_data *dsi)
809 {
810         tegra_dc_writel(dc, 0, DC_DISP_DISP_WIN_OPTIONS);
811         tegra_dc_writel(dc, GENERAL_ACT_REQ << 8, DC_CMD_STATE_CONTROL);
812         tegra_dc_writel(dc, GENERAL_ACT_REQ, DC_CMD_STATE_CONTROL);
813
814         dsi->status.dc_stream = DSI_DC_STREAM_DISABLE;
815 }
816
817 void tegra_dsi_stop_dc_stream_at_frame_end(struct tegra_dc *dc, struct tegra_dc_dsi_data *dsi)
818 {
819         int val;
820         long timeout;
821
822         /* stop dc */
823         tegra_dsi_stop_dc_stream(dc, dsi);
824
825         /* enable vblank interrupt */
826         val = tegra_dc_readl(dc, DC_CMD_INT_ENABLE);
827         val |= V_BLANK_INT;
828         tegra_dc_writel(dc, val, DC_CMD_INT_ENABLE);
829
830         val = tegra_dc_readl(dc, DC_CMD_INT_MASK);
831         val |= V_BLANK_INT;
832         tegra_dc_writel(dc, val, DC_CMD_INT_MASK);
833
834         /* wait for vblank completion */
835         timeout = wait_for_completion_interruptible_timeout(
836                 &dc->vblank_complete, DSI_STOP_DC_DURATION_MSEC);
837
838         /* disable vblank interrupt */
839         val = tegra_dc_readl(dc, DC_CMD_INT_ENABLE);
840         val &= ~V_BLANK_INT;
841         tegra_dc_writel(dc, val, DC_CMD_INT_ENABLE);
842
843         if(timeout == 0)
844                 printk("Warning: dc dosen't stop at the end of the frame.\n");
845 }
846
847 static void tegra_dsi_start_dc_stream(struct tegra_dc *dc,
848                                                 struct tegra_dc_dsi_data *dsi)
849 {
850         u32 val;
851
852         tegra_dc_writel(dc, DSI_ENABLE, DC_DISP_DISP_WIN_OPTIONS);
853
854         /* TODO: clean up */
855         val = PIN_INPUT_LSPI_INPUT_EN;
856         tegra_dc_writel(dc, val, DC_COM_PIN_INPUT_ENABLE3);
857
858         val = PIN_OUTPUT_LSPI_OUTPUT_DIS;
859         tegra_dc_writel(dc, val, DC_COM_PIN_OUTPUT_ENABLE3);
860
861         tegra_dc_writel(dc, PW0_ENABLE | PW1_ENABLE | PW2_ENABLE | PW3_ENABLE |
862                         PW4_ENABLE | PM0_ENABLE | PM1_ENABLE,
863                         DC_CMD_DISPLAY_POWER_CONTROL);
864
865         val = MSF_POLARITY_HIGH | MSF_ENABLE | MSF_LSPI;
866         tegra_dc_writel(dc, val, DC_CMD_DISPLAY_COMMAND_OPTION0);
867
868
869         /* TODO: using continuous video mode for now */
870         /* if (dsi->info.panel_has_frame_buffer) {*/
871         if (0) {
872                 tegra_dc_writel(dc, DISP_CTRL_MODE_NC_DISPLAY, DC_CMD_DISPLAY_COMMAND);
873                 tegra_dc_writel(dc, GENERAL_UPDATE, DC_CMD_STATE_CONTROL);
874                 val = GENERAL_ACT_REQ | NC_HOST_TRIG;
875                 tegra_dc_writel(dc, val, DC_CMD_STATE_CONTROL);
876         } else {
877                 tegra_dc_writel(dc, DISP_CTRL_MODE_C_DISPLAY, DC_CMD_DISPLAY_COMMAND);
878                 tegra_dc_writel(dc, GENERAL_ACT_REQ << 8, DC_CMD_STATE_CONTROL);
879                 tegra_dc_writel(dc, GENERAL_ACT_REQ, DC_CMD_STATE_CONTROL);
880         }
881
882         dsi->status.dc_stream = DSI_DC_STREAM_ENABLE;
883 }
884
885 static void tegra_dsi_set_dc_clk(struct tegra_dc *dc,
886                                                 struct tegra_dc_dsi_data *dsi)
887 {
888         u32 shift_clk_div_register;
889         u32 val;
890
891         /* Get the corresponding register value of shift_clk_div. */
892         shift_clk_div_register = dsi->shift_clk_div * 2 - 2;
893
894 #ifdef CONFIG_TEGRA_FPGA_PLATFORM
895         shift_clk_div_register = 1;
896 #endif
897
898         /* TODO: find out if PCD3 option is required */
899         val = PIXEL_CLK_DIVIDER_PCD1 |
900                                 SHIFT_CLK_DIVIDER(shift_clk_div_register);
901         tegra_dc_writel(dc, val, DC_DISP_DISP_CLOCK_CONTROL);
902
903         clk_enable(dsi->dc_clk);
904 }
905
906 static void tegra_dsi_set_dsi_clk(struct tegra_dc *dc,
907                                         struct tegra_dc_dsi_data *dsi, u32 clk)
908 {
909         u32 rm;
910
911         rm = clk % 1000;
912         if (rm != 0)
913                 clk -= rm;
914
915         clk *= 2;       /* Value for PLLD routine is required to be twice as */
916                         /* the desired clock rate */
917
918         dc->mode.pclk = clk*1000;
919         tegra_dc_setup_clk(dc, dsi->dsi_clk);
920         clk_enable(dsi->dsi_clk);
921         tegra_periph_reset_deassert(dsi->dsi_clk);
922
923         dsi->current_dsi_clk_khz = clk_get_rate(dsi->dsi_clk) / 1000;
924
925         dsi->current_bit_clk_ns =  1000*1000 / (dsi->current_dsi_clk_khz * 2);
926 }
927
928 static void tegra_dsi_hs_clk_out_enable(struct tegra_dc_dsi_data *dsi)
929 {
930         u32 val;
931
932         val = tegra_dsi_readl(dsi, DSI_CONTROL);
933         val &= ~DSI_CONTROL_HS_CLK_CTRL(1);
934
935         if (dsi->info.video_clock_mode == TEGRA_DSI_VIDEO_CLOCK_CONTINUOUS) {
936                 val |= DSI_CONTROL_HS_CLK_CTRL(CONTINUOUS);
937                 dsi->status.clk_mode = DSI_PHYCLK_CONTINUOUS;
938         } else {
939                 val |= DSI_CONTROL_HS_CLK_CTRL(TX_ONLY);
940                 dsi->status.clk_mode = DSI_PHYCLK_TX_ONLY;
941         }
942         tegra_dsi_writel(dsi, val, DSI_CONTROL);
943
944         val = tegra_dsi_readl(dsi, DSI_HOST_DSI_CONTROL);
945         val &= ~DSI_HOST_DSI_CONTROL_HIGH_SPEED_TRANS(1);
946         val |= DSI_HOST_DSI_CONTROL_HIGH_SPEED_TRANS(TEGRA_DSI_HIGH);
947         tegra_dsi_writel(dsi, val, DSI_HOST_DSI_CONTROL);
948
949         dsi->status.clk_out = DSI_PHYCLK_OUT_EN;
950 }
951
952 static void tegra_dsi_hs_clk_out_enable_in_lp(struct tegra_dc_dsi_data *dsi)
953 {
954         u32 val;
955         tegra_dsi_hs_clk_out_enable(dsi);
956
957         val = tegra_dsi_readl(dsi, DSI_HOST_DSI_CONTROL);
958         val &= ~DSI_HOST_DSI_CONTROL_HIGH_SPEED_TRANS(1);
959         val |= DSI_HOST_DSI_CONTROL_HIGH_SPEED_TRANS(TEGRA_DSI_LOW);
960         tegra_dsi_writel(dsi, val, DSI_HOST_DSI_CONTROL);
961 }
962
963 static void tegra_dsi_hs_clk_out_disable(struct tegra_dc *dc,
964                                                 struct tegra_dc_dsi_data *dsi)
965 {
966         u32 val;
967
968         if (dsi->status.dc_stream == DSI_DC_STREAM_ENABLE)
969                 tegra_dsi_stop_dc_stream(dc, dsi);
970
971         val = tegra_dsi_readl(dsi, DSI_CONTROL);
972         val &= ~DSI_CONTROL_HS_CLK_CTRL(1);
973         val |= DSI_CONTROL_HS_CLK_CTRL(TX_ONLY);
974         tegra_dsi_writel(dsi, val, DSI_CONTROL);
975
976         /* TODO: issue a cmd */
977
978         val = tegra_dsi_readl(dsi, DSI_HOST_DSI_CONTROL);
979         val &= ~DSI_HOST_DSI_CONTROL_HIGH_SPEED_TRANS(1);
980         val |= DSI_HOST_DSI_CONTROL_HIGH_SPEED_TRANS(TEGRA_DSI_LOW);
981         tegra_dsi_writel(dsi, val, DSI_HOST_DSI_CONTROL);
982
983         dsi->status.clk_mode = DSI_PHYCLK_NOT_INIT;
984         dsi->status.clk_out = DSI_PHYCLK_OUT_DIS;
985 }
986
987 static void tegra_dsi_set_control_reg_lp(struct tegra_dc_dsi_data *dsi)
988 {
989         u32 dsi_control;
990         u32 host_dsi_control;
991         u32 max_threshold;
992
993         dsi_control = dsi->dsi_control_val | DSI_CTRL_HOST_DRIVEN;
994         host_dsi_control = HOST_DSI_CTRL_COMMON |
995                         HOST_DSI_CTRL_HOST_DRIVEN |
996                         DSI_HOST_DSI_CONTROL_HIGH_SPEED_TRANS(TEGRA_DSI_LOW);
997         max_threshold = DSI_MAX_THRESHOLD_MAX_THRESHOLD(DSI_HOST_FIFO_DEPTH);
998
999         tegra_dsi_writel(dsi, max_threshold, DSI_MAX_THRESHOLD);
1000         tegra_dsi_writel(dsi, dsi_control, DSI_CONTROL);
1001         tegra_dsi_writel(dsi, host_dsi_control, DSI_HOST_DSI_CONTROL);
1002
1003         dsi->status.driven = DSI_DRIVEN_MODE_HOST;
1004         dsi->status.clk_burst = DSI_CLK_BURST_NOT_INIT;
1005         dsi->status.vtype = DSI_VIDEO_TYPE_NOT_INIT;
1006 }
1007
1008 static void tegra_dsi_set_control_reg_hs(struct tegra_dc_dsi_data *dsi)
1009 {
1010         u32 dsi_control;
1011         u32 host_dsi_control;
1012         u32 max_threshold;
1013         u32 dcs_cmd;
1014
1015         dsi_control = dsi->dsi_control_val;
1016         host_dsi_control = HOST_DSI_CTRL_COMMON;
1017         max_threshold = 0;
1018         dcs_cmd = 0;
1019
1020         if (dsi->driven_mode == TEGRA_DSI_DRIVEN_BY_HOST) {
1021                 dsi_control |= DSI_CTRL_HOST_DRIVEN;
1022                 host_dsi_control |= HOST_DSI_CTRL_HOST_DRIVEN;
1023                 max_threshold = DSI_MAX_THRESHOLD_MAX_THRESHOLD(DSI_HOST_FIFO_DEPTH);
1024                 dsi->status.driven = DSI_DRIVEN_MODE_HOST;
1025         } else {
1026                 dsi_control |= DSI_CTRL_DC_DRIVEN;
1027                 host_dsi_control |= HOST_DSI_CTRL_DC_DRIVEN;
1028                 max_threshold = DSI_MAX_THRESHOLD_MAX_THRESHOLD(DSI_VIDEO_FIFO_DEPTH);
1029                 dsi->status.driven = DSI_DRIVEN_MODE_DC;
1030         }
1031
1032         if (dsi->info.video_data_type == TEGRA_DSI_VIDEO_TYPE_COMMAND_MODE) {
1033                 dsi_control |= DSI_CTRL_CMD_MODE;
1034                 host_dsi_control |= HOST_DSI_CTRL_CMD_MODE;
1035                 dcs_cmd = DSI_DCS_CMDS_LT5_DCS_CMD(DSI_WRITE_MEMORY_START)|
1036                                 DSI_DCS_CMDS_LT3_DCS_CMD(DSI_WRITE_MEMORY_CONTINUE);
1037                 dsi->status.vtype = DSI_VIDEO_TYPE_CMD_MODE;
1038
1039         } else {
1040                 dsi_control |= DSI_CTRL_VIDEO_MODE;
1041                 host_dsi_control |= HOST_DSI_CTRL_VIDEO_MODE;
1042                 dsi->status.vtype = DSI_VIDEO_TYPE_VIDEO_MODE;
1043         }
1044
1045         tegra_dsi_writel(dsi, max_threshold, DSI_MAX_THRESHOLD);
1046         tegra_dsi_writel(dsi, dcs_cmd, DSI_DCS_CMDS);
1047         tegra_dsi_writel(dsi, dsi_control, DSI_CONTROL);
1048         tegra_dsi_writel(dsi, host_dsi_control, DSI_HOST_DSI_CONTROL);
1049 }
1050
1051 static int tegra_dsi_init_hw(struct tegra_dc *dc,
1052                                                 struct tegra_dc_dsi_data *dsi)
1053 {
1054         u32 val;
1055         u32 i;
1056
1057         tegra_dsi_set_dsi_clk(dc, dsi, dsi->target_lp_clk_khz);
1058         if (dsi->info.dsi_instance) {
1059                 /* TODO:Set the misc register*/
1060         }
1061
1062         /* TODO: only need to change the timing for bta */
1063         tegra_dsi_set_phy_timing(dsi);
1064
1065         if (dsi->status.dc_stream == DSI_DC_STREAM_ENABLE)
1066                 tegra_dsi_stop_dc_stream(dc, dsi);
1067
1068         /* Initializing DSI registers */
1069         for (i = 0; i < ARRAY_SIZE(init_reg); i++) {
1070                 tegra_dsi_writel(dsi, 0, init_reg[i]);
1071         }
1072         tegra_dsi_writel(dsi, dsi->dsi_control_val, DSI_CONTROL);
1073
1074         /* Initialize DSI_PAD_CONTROL register. */
1075         val =   DSI_PAD_CONTROL_PAD_LPUPADJ(0x1) |
1076                 DSI_PAD_CONTROL_PAD_LPDNADJ(0x1) |
1077                 DSI_PAD_CONTROL_PAD_PREEMP_EN(0x1) |
1078                 DSI_PAD_CONTROL_PAD_SLEWDNADJ(0x6) |
1079                 DSI_PAD_CONTROL_PAD_SLEWUPADJ(0x6);
1080         if (!dsi->ulpm) {
1081                 val |=  DSI_PAD_CONTROL_PAD_PDIO(0) |
1082                         DSI_PAD_CONTROL_PAD_PDIO_CLK(0) |
1083                         DSI_PAD_CONTROL_PAD_PULLDN_ENAB(TEGRA_DSI_DISABLE);
1084         } else {
1085                 val |=  DSI_PAD_CONTROL_PAD_PDIO(0x3) |
1086                         DSI_PAD_CONTROL_PAD_PDIO_CLK(0x1) |
1087                         DSI_PAD_CONTROL_PAD_PULLDN_ENAB(TEGRA_DSI_ENABLE);
1088         }
1089         tegra_dsi_writel(dsi, val, DSI_PAD_CONTROL);
1090
1091         val = DSI_POWER_CONTROL_LEG_DSI_ENABLE(TEGRA_DSI_ENABLE);
1092         tegra_dsi_writel(dsi, val, DSI_POWER_CONTROL);
1093
1094         while (tegra_dsi_readl(dsi, DSI_POWER_CONTROL) != val) {
1095                 tegra_dsi_writel(dsi, val, DSI_POWER_CONTROL);
1096         }
1097
1098         dsi->status.init = DSI_MODULE_INIT;
1099         dsi->status.lphs = DSI_LPHS_NOT_INIT;
1100         dsi->status.vtype = DSI_VIDEO_TYPE_NOT_INIT;
1101         dsi->status.driven = DSI_DRIVEN_MODE_NOT_INIT;
1102         dsi->status.clk_out = DSI_PHYCLK_OUT_DIS;
1103         dsi->status.clk_mode = DSI_PHYCLK_NOT_INIT;
1104         dsi->status.clk_burst = DSI_CLK_BURST_NOT_INIT;
1105         dsi->status.dc_stream = DSI_DC_STREAM_DISABLE;
1106
1107         return 0;
1108 }
1109
1110 static int tegra_dsi_set_to_lp_mode(struct tegra_dc *dc,
1111                                                 struct tegra_dc_dsi_data *dsi)
1112 {
1113         int     err;
1114
1115         if (dsi->status.init != DSI_MODULE_INIT) {
1116                 err = -EPERM;
1117                 goto fail;
1118         }
1119
1120         if (dsi->status.lphs == DSI_LPHS_IN_LP_MODE)
1121                 goto success;
1122
1123         if (dsi->status.dc_stream == DSI_DC_STREAM_ENABLE)
1124                 tegra_dsi_stop_dc_stream_at_frame_end(dc, dsi);
1125
1126         /* disable/enable hs clock according to enable_hs_clock_on_lp_cmd_mode */
1127         if ((dsi->status.clk_out == DSI_PHYCLK_OUT_EN) &&
1128                 (!dsi->info.enable_hs_clock_on_lp_cmd_mode))
1129                 tegra_dsi_hs_clk_out_disable(dc, dsi);
1130
1131         if (dsi->current_dsi_clk_khz != dsi->target_lp_clk_khz){
1132                 tegra_dsi_set_dsi_clk(dc, dsi, dsi->target_lp_clk_khz);
1133                 tegra_dsi_set_timeout(dsi);
1134         }
1135
1136         tegra_dsi_set_control_reg_lp(dsi);
1137
1138         if ((dsi->status.clk_out == DSI_PHYCLK_OUT_DIS) &&
1139                 (dsi->info.enable_hs_clock_on_lp_cmd_mode))
1140                 tegra_dsi_hs_clk_out_enable_in_lp(dsi);
1141
1142 success:
1143         dsi->status.lphs = DSI_LPHS_IN_LP_MODE;
1144         err = 0;
1145 fail:
1146         return err;
1147 }
1148
1149 static int tegra_dsi_set_to_hs_mode(struct tegra_dc *dc,
1150                                                 struct tegra_dc_dsi_data *dsi)
1151 {
1152         int err;
1153
1154         if (dsi->status.init != DSI_MODULE_INIT) {
1155                 err = -EPERM;
1156                 goto fail;
1157         }
1158
1159         if (dsi->status.dc_stream == DSI_DC_STREAM_ENABLE)
1160                 tegra_dsi_stop_dc_stream_at_frame_end(dc, dsi);
1161
1162         if ((dsi->status.clk_out == DSI_PHYCLK_OUT_EN) &&
1163                 (!dsi->info.enable_hs_clock_on_lp_cmd_mode))
1164                 tegra_dsi_hs_clk_out_disable(dc, dsi);
1165
1166         if (dsi->current_dsi_clk_khz != dsi->target_hs_clk_khz) {
1167                 tegra_dsi_set_dsi_clk(dc, dsi, dsi->target_hs_clk_khz);
1168                 tegra_dsi_set_timeout(dsi);
1169         }
1170
1171         tegra_dsi_set_phy_timing(dsi);
1172
1173         if (dsi->driven_mode == TEGRA_DSI_DRIVEN_BY_DC){
1174                 tegra_dsi_set_pkt_seq(dc, dsi);
1175                 tegra_dsi_set_pkt_length(dc, dsi);
1176                 tegra_dsi_set_sol_delay(dc, dsi);
1177                 tegra_dsi_set_dc_clk(dc, dsi);
1178         }
1179
1180         tegra_dsi_set_control_reg_hs(dsi);
1181
1182         if (dsi->status.clk_out == DSI_PHYCLK_OUT_DIS)
1183                 tegra_dsi_hs_clk_out_enable(dsi);
1184
1185         dsi->status.lphs = DSI_LPHS_IN_HS_MODE;
1186         err = 0;
1187 fail:
1188         return err;
1189 }
1190
1191 static bool tegra_dsi_is_controller_idle(struct tegra_dc_dsi_data *dsi)
1192 {
1193         u32 timeout = 0;
1194         bool retVal;
1195
1196         retVal = false;
1197         while (timeout <= DSI_MAX_COMMAND_DELAY_USEC) {
1198                 if (!tegra_dsi_readl(dsi, DSI_TRIGGER)) {
1199                         retVal = true;
1200                         break;
1201                 }
1202                 udelay(DSI_COMMAND_DELAY_STEPS_USEC);
1203                 timeout += DSI_COMMAND_DELAY_STEPS_USEC;
1204         }
1205
1206         return retVal;
1207 }
1208
1209 static int tegra_dsi_host_trigger(struct tegra_dc_dsi_data *dsi)
1210 {
1211         int status;
1212         u32 val;
1213
1214         status = 0;
1215
1216         if (tegra_dsi_readl(dsi, DSI_TRIGGER)) {
1217                 status = -EBUSY;
1218                 goto fail;
1219         }
1220
1221         tegra_dsi_writel(dsi,
1222                 DSI_TRIGGER_HOST_TRIGGER(TEGRA_DSI_ENABLE), DSI_TRIGGER);
1223
1224 #if DSI_USE_SYNC_POINTS
1225         status = tegra_dsi_syncpt(dsi);
1226         if (status < 0) {
1227                 printk(KERN_ERR "DSI syncpt for host trigger failed\n");
1228                 goto fail;
1229         }
1230 #else
1231         if (!tegra_dsi_is_controller_idle(dsi))
1232                 status = -EIO;
1233 #endif
1234
1235 fail:
1236         return status;
1237 }
1238
1239 static int _tegra_dsi_write_data(struct tegra_dc_dsi_data *dsi,
1240                                         u8* pdata, u8 data_id, u16 data_len)
1241 {
1242         u8 virtual_channel;
1243         u8 *pval;
1244         u32 val;
1245         int err;
1246
1247         err = 0;
1248
1249         virtual_channel = dsi->info.virtual_channel << DSI_VIR_CHANNEL_BIT_POSITION;
1250
1251         /* always use hw for ecc */
1252         val = (virtual_channel | data_id) << 0 |
1253                         data_len << 8;
1254         tegra_dsi_writel(dsi, val, DSI_WR_DATA);
1255
1256         /* if pdata != NULL, pkt type is long pkt */
1257         if (pdata != NULL) {
1258                 while (data_len) {
1259                         if (data_len >= 4) {
1260                                 val = ((u32*) pdata)[0];
1261                                 data_len -= 4;
1262                                 pdata += 4;
1263                         } else {
1264                                 val = 0;
1265                                 pval = (u8*) &val;
1266                                 do
1267                                         *pval++ = *pdata++;
1268                                 while(--data_len);
1269                         }
1270                         tegra_dsi_writel(dsi, val, DSI_WR_DATA);
1271                 }
1272         }
1273
1274         err = tegra_dsi_host_trigger(dsi);
1275         if (err < 0)
1276                 printk(KERN_ERR "DSI host trigger failed\n");
1277
1278         return err;
1279 }
1280
1281 static int tegra_dsi_write_data(struct tegra_dc *dc,
1282                                         struct tegra_dc_dsi_data *dsi,
1283                                         u8* pdata, u8 data_id, u16 data_len)
1284 {
1285         bool switch_back_to_hs_mode;
1286         bool switch_back_to_dc_mode;
1287         int err;
1288
1289         err = 0;
1290         switch_back_to_hs_mode = false;
1291         switch_back_to_dc_mode = false;
1292
1293         if ((dsi->status.init != DSI_MODULE_INIT) ||
1294                 (dsi->status.lphs == DSI_LPHS_NOT_INIT)) {
1295                 err = -EPERM;
1296                 goto fail;
1297         }
1298
1299         if (!tegra_dsi_is_controller_idle(dsi)) {
1300                 err = -EBUSY;
1301                 goto fail;
1302         }
1303
1304         err = 0;
1305
1306         if (dsi->status.lphs == DSI_LPHS_IN_HS_MODE) {
1307                 if (dsi->info.hs_cmd_mode_supported) {
1308                         if (dsi->status.driven == DSI_DRIVEN_MODE_DC) {
1309                                 dsi->driven_mode = TEGRA_DSI_DRIVEN_BY_HOST;
1310                                 tegra_dsi_set_to_hs_mode(dc, dsi);
1311                                 switch_back_to_dc_mode = true;
1312                         }
1313                 } else {
1314                         tegra_dsi_set_to_lp_mode(dc, dsi);
1315                         switch_back_to_hs_mode = true;
1316                 }
1317         }
1318
1319         err = _tegra_dsi_write_data(dsi, pdata, data_id, data_len);
1320
1321
1322         if (switch_back_to_dc_mode)
1323                 dsi->driven_mode = TEGRA_DSI_DRIVEN_BY_DC;
1324         if (switch_back_to_dc_mode || switch_back_to_hs_mode)
1325                 tegra_dsi_set_to_hs_mode(dc, dsi);
1326
1327 fail:
1328         return err;
1329 }
1330
1331 static int tegra_dsi_send_panel_cmd(struct tegra_dc *dc,
1332                                                 struct tegra_dc_dsi_data *dsi,
1333                                                 struct tegra_dsi_cmd *cmd,
1334                                                 u32 n_cmd)
1335 {
1336         u32 i;
1337         int err;
1338
1339         err = 0;
1340         for (i = 0; i < n_cmd; i++) {
1341                 struct tegra_dsi_cmd *cur_cmd;
1342                 cur_cmd = &cmd[i];
1343
1344                 if (cur_cmd->cmd_type == TEGRA_DSI_DELAY_MS)
1345                         mdelay(cur_cmd->sp_len_dly.delay_ms);
1346                 else {
1347                         err = tegra_dsi_write_data(dc, dsi,
1348                                                 cur_cmd->pdata,
1349                                                 cur_cmd->data_id,
1350                                                 cur_cmd->sp_len_dly.data_len);
1351                         if (err < 0)
1352                                 break;
1353                 }
1354         }
1355         return err;
1356 }
1357
1358 static int tegra_dsi_bta(struct tegra_dc_dsi_data *dsi)
1359 {
1360         u32 val;
1361         u32 poll_time;
1362         int err;
1363
1364         poll_time = 0;
1365         err = 0;
1366
1367         val = tegra_dsi_readl(dsi, DSI_HOST_DSI_CONTROL);
1368         val |= DSI_HOST_DSI_CONTROL_IMM_BTA(TEGRA_DSI_ENABLE);
1369         tegra_dsi_writel(dsi, val, DSI_HOST_DSI_CONTROL);
1370
1371 #if DSI_USE_SYNC_POINTS
1372         /* FIXME: Workaround for nvhost_syncpt_read */
1373         dsi->syncpt_val = nvhost_syncpt_update_min(
1374                         &dsi->dc->ndev->host->syncpt, dsi->syncpt_id);
1375
1376         val = DSI_INCR_SYNCPT_COND(OP_DONE) |
1377                 DSI_INCR_SYNCPT_INDX(dsi->syncpt_id);
1378         tegra_dsi_writel(dsi, val, DSI_INCR_SYNCPT);
1379
1380         /* TODO: Use interrupt rather than polling */
1381         err = nvhost_syncpt_wait(&dsi->dc->ndev->host->syncpt,
1382                 dsi->syncpt_id, dsi->syncpt_val + 1);
1383         if (err < 0)
1384                 printk(KERN_ERR "DSI sync point failure\n");
1385         else
1386                 (dsi->syncpt_val)++;
1387 #else
1388         while (poll_time <  DSI_STATUS_POLLING_DURATION_USEC) {
1389                 val = tegra_dsi_readl(dsi, DSI_HOST_DSI_CONTROL);
1390                 val &= DSI_HOST_DSI_CONTROL_IMM_BTA(TEGRA_DSI_ENABLE);
1391                 if (!val)
1392                         break;
1393                 udelay(DSI_STATUS_POLLING_DELAY_USEC);
1394                 poll_time += DSI_STATUS_POLLING_DELAY_USEC;
1395         }
1396         if (poll_time > DSI_STATUS_POLLING_DURATION_USEC)
1397                 err = -EBUSY;
1398 #endif
1399
1400         return err;
1401 }
1402
1403 static void tegra_dsi_read_fifo(struct tegra_dc *dc,
1404                         struct tegra_dc_dsi_data *dsi,
1405                         u32 rd_fifo_cnt,
1406                         u8 *read_fifo)
1407 {
1408         u32 val;
1409         u32 i;
1410
1411         /* Read data from FIFO */
1412         for (i = 0; i < rd_fifo_cnt; i++) {
1413                 val = tegra_dsi_readl(dsi, DSI_RD_DATA);
1414                 printk(KERN_INFO "Read data[%d]: 0x%x\n", i, val);
1415                 memcpy(read_fifo, &val, 4);
1416                 read_fifo += 4;
1417         }
1418
1419         /* Make sure all the data is read from the FIFO */
1420         val = tegra_dsi_readl(dsi, DSI_STATUS);
1421         val &= DSI_STATUS_RD_FIFO_COUNT(0x1f);
1422         if (val)
1423                 dev_err(&dc->ndev->dev, "DSI FIFO_RD_CNT not zero"
1424                 " even after reading FIFO_RD_CNT words from read fifo\n");
1425 }
1426
1427 static int tegra_dsi_parse_read_response(struct tegra_dc *dc,
1428                                 u32 rd_fifo_cnt, u8 *read_fifo)
1429 {
1430         int err;
1431         u32 payload_size;
1432
1433         payload_size = 0;
1434         err = 0;
1435
1436         printk(KERN_INFO "escape sequence[0x%x]\n", read_fifo[0]);
1437         switch (read_fifo[4] & 0xff) {
1438         case GEN_LONG_RD_RES:
1439                 /* Fall through */
1440         case DCS_LONG_RD_RES:
1441                 payload_size = (read_fifo[5] |
1442                                 (read_fifo[6] << 8)) & 0xFFFF;
1443                 printk(KERN_INFO "Long read response Packet\n"
1444                                 "payload_size[0x%x]\n", payload_size);
1445                 break;
1446         case GEN_1_BYTE_SHORT_RD_RES:
1447                 /* Fall through */
1448         case DCS_1_BYTE_SHORT_RD_RES:
1449                 payload_size = 1;
1450                 printk(KERN_INFO "Short read response Packet\n"
1451                         "payload_size[0x%x]\n", payload_size);
1452                 break;
1453         case GEN_2_BYTE_SHORT_RD_RES:
1454                 /* Fall through */
1455         case DCS_2_BYTE_SHORT_RD_RES:
1456                 payload_size = 2;
1457                 printk(KERN_INFO "Short read response Packet\n"
1458                         "payload_size[0x%x]\n", payload_size);
1459                 break;
1460         case ACK_ERR_RES:
1461                 payload_size = 2;
1462                 printk(KERN_INFO "Acknowledge error report response\n"
1463                         "Packet payload_size[0x%x]\n", payload_size);
1464                 break;
1465         default:
1466                 /*reading from RD_FIFO_COUNT*/
1467                 printk(KERN_INFO "Invalid read response payload_size\n");
1468                 err = -EINVAL;
1469                 break;
1470         }
1471         return err;
1472 }
1473
1474 static int tegra_dsi_read_data(struct tegra_dc *dc,
1475                                 struct tegra_dc_dsi_data *dsi,
1476                                 u32 max_ret_payload_size,
1477                                 u32 panel_reg_addr, u8 *read_data)
1478 {
1479         u32 val;
1480         int err;
1481         u32 poll_time;
1482         u32 rd_fifo_cnt;
1483         bool switch_back_to_hs_mode;
1484         bool restart_dc_stream;
1485         bool switch_back_to_dc_mode;
1486
1487         err = 0;
1488         switch_back_to_hs_mode = false;
1489         restart_dc_stream = false;
1490         switch_back_to_dc_mode = false;
1491
1492         if ((dsi->status.init != DSI_MODULE_INIT) ||
1493                 (dsi->status.lphs == DSI_LPHS_NOT_INIT) ||
1494                 (dsi->status.driven == DSI_DRIVEN_MODE_NOT_INIT)) {
1495                 err = -EPERM;
1496                 goto fail;
1497         }
1498
1499         val = tegra_dsi_readl(dsi, DSI_STATUS);
1500         val &= DSI_STATUS_RD_FIFO_COUNT(0x1f);
1501         if (val) {
1502                 err = -EBUSY;
1503                 dev_err(&dc->ndev->dev, "DSI fifo count not zero\n");
1504                 goto fail;
1505         }
1506
1507         if (!tegra_dsi_is_controller_idle(dsi)) {
1508                 err = -EBUSY;
1509                 dev_err(&dc->ndev->dev, "DSI trigger bit is already set\n");
1510                 goto fail;
1511         }
1512
1513         if (dsi->status.lphs == DSI_LPHS_IN_HS_MODE) {
1514                 if (dsi->status.driven == DSI_DRIVEN_MODE_DC) {
1515                         if (dsi->status.dc_stream == DSI_DC_STREAM_ENABLE)
1516                                 restart_dc_stream = true;
1517                         dsi->driven_mode = TEGRA_DSI_DRIVEN_BY_HOST;
1518                         switch_back_to_dc_mode = true;
1519                         if (dsi->info.hs_cmd_mode_supported) {
1520                                 err = tegra_dsi_set_to_hs_mode(dc, dsi);
1521                                 if (err < 0) {
1522                                         dev_err(&dc->ndev->dev,
1523                                         "DSI failed to go to HS mode host driven\n");
1524                                         goto fail;
1525                                 }
1526                         }
1527                 }
1528                 if (!dsi->info.hs_cmd_mode_supported) {
1529                         err = tegra_dsi_set_to_lp_mode(dc, dsi);
1530                         if (err < 0) {
1531                                 dev_err(&dc->ndev->dev,
1532                                 "DSI failed to go to LP mode\n");
1533                                 goto fail;
1534                         }
1535                         switch_back_to_hs_mode = true;
1536                 }
1537         }
1538
1539         /* Set max return payload size in words */
1540         err = _tegra_dsi_write_data(dsi, NULL,
1541                 dsi_command_max_return_pkt_size,
1542                 max_ret_payload_size);
1543         if (err < 0) {
1544                 dev_err(&dc->ndev->dev,
1545                                 "DSI write failed\n");
1546                 goto fail;
1547         }
1548
1549         /* DCS to read given panel register */
1550         err = _tegra_dsi_write_data(dsi, NULL,
1551                 dsi_command_dcs_read_with_no_params,
1552                 panel_reg_addr);
1553         if (err < 0) {
1554                 dev_err(&dc->ndev->dev,
1555                                 "DSI write failed\n");
1556                 goto fail;
1557         }
1558
1559         err = tegra_dsi_bta(dsi);
1560         if (err < 0) {
1561                 dev_err(&dc->ndev->dev,
1562                         "DSI IMM BTA timeout\n");
1563                 goto fail;
1564         }
1565
1566         poll_time = 0;
1567         while (poll_time <  DSI_DELAY_FOR_READ_FIFO) {
1568                 mdelay(1);
1569                 val = tegra_dsi_readl(dsi, DSI_STATUS);
1570                 rd_fifo_cnt = val & DSI_STATUS_RD_FIFO_COUNT(0x1f);
1571                 if (rd_fifo_cnt << 2 > DSI_READ_FIFO_DEPTH)
1572                         dev_err(&dc->ndev->dev,
1573                         "DSI RD_FIFO_CNT is greater than RD_FIFO_DEPTH\n");
1574                         break;
1575                 poll_time++;
1576         }
1577
1578         if (rd_fifo_cnt == 0) {
1579                 dev_info(&dc->ndev->dev,
1580                         "DSI RD_FIFO_CNT is zero\n");
1581                 err = -EINVAL;
1582                 goto fail;
1583         }
1584
1585         if (val & DSI_STATUS_LB_UNDERFLOW(0x1) ||
1586                 val & DSI_STATUS_LB_OVERFLOW(0x1)) {
1587                 dev_err(&dc->ndev->dev,
1588                         "DSI overflow/underflow error\n");
1589                 err = -EINVAL;
1590                 goto fail;
1591         }
1592
1593         tegra_dsi_read_fifo(dc, dsi, rd_fifo_cnt, read_data);
1594
1595         err = tegra_dsi_parse_read_response(dc, rd_fifo_cnt, read_data);
1596 fail:
1597         if (switch_back_to_dc_mode)
1598                 dsi->driven_mode = TEGRA_DSI_DRIVEN_BY_DC;
1599         if (switch_back_to_dc_mode || switch_back_to_hs_mode)
1600                 tegra_dsi_set_to_hs_mode(dc, dsi);
1601         if (restart_dc_stream)
1602                 tegra_dsi_start_dc_stream(dc, dsi);
1603
1604         return err;
1605 }
1606
1607 static int tegra_dsi_enter_ulpm(struct tegra_dc_dsi_data *dsi)
1608 {
1609         u32 val;
1610         int ret;
1611
1612         ret = 0;
1613
1614         val = tegra_dsi_readl(dsi, DSI_HOST_DSI_CONTROL);
1615         val &= ~DSI_HOST_DSI_CONTROL_ULTRA_LOW_POWER(3);
1616         val |= DSI_HOST_DSI_CONTROL_ULTRA_LOW_POWER(ENTER_ULPM);
1617         tegra_dsi_writel(dsi, val, DSI_HOST_DSI_CONTROL);
1618
1619 #if DSI_USE_SYNC_POINTS
1620         ret = tegra_dsi_syncpt(dsi);
1621         if (ret < 0) {
1622                 printk(KERN_ERR "DSI syncpt for ulpm enter failed\n");
1623                 goto fail;
1624         }
1625 #else
1626         /* TODO: Find exact delay required */
1627         mdelay(10);
1628 #endif
1629         dsi->ulpm = true;
1630 fail:
1631         return ret;
1632 }
1633
1634 static int tegra_dsi_exit_ulpm(struct tegra_dc_dsi_data *dsi)
1635 {
1636         u32 val;
1637         int ret;
1638
1639         ret = 0;
1640
1641         val = tegra_dsi_readl(dsi, DSI_HOST_DSI_CONTROL);
1642         val &= ~DSI_HOST_DSI_CONTROL_ULTRA_LOW_POWER(3);
1643         val |= DSI_HOST_DSI_CONTROL_ULTRA_LOW_POWER(EXIT_ULPM);
1644         tegra_dsi_writel(dsi, val, DSI_HOST_DSI_CONTROL);
1645
1646 #if DSI_USE_SYNC_POINTS
1647         ret = tegra_dsi_syncpt(dsi);
1648         if (ret < 0) {
1649                 printk(KERN_ERR "DSI syncpt for ulpm exit failed\n");
1650                 goto fail;
1651         }
1652 #else
1653         /* TODO: Find exact delay required */
1654         mdelay(10);
1655 #endif
1656         dsi->ulpm = false;
1657
1658         val = tegra_dsi_readl(dsi, DSI_HOST_DSI_CONTROL);
1659         val &= ~DSI_HOST_DSI_CONTROL_ULTRA_LOW_POWER(0x3);
1660         val |= DSI_HOST_DSI_CONTROL_ULTRA_LOW_POWER(NORMAL);
1661         tegra_dsi_writel(dsi, val, DSI_HOST_DSI_CONTROL);
1662 fail:
1663         return ret;
1664
1665 }
1666
1667 static void tegra_dc_dsi_enable(struct tegra_dc *dc)
1668 {
1669         struct tegra_dc_dsi_data *dsi = tegra_dc_get_outdata(dc);
1670         int err;
1671         u32 val;
1672
1673         tegra_dc_io_start(dc);
1674         mutex_lock(&dsi->lock);
1675
1676         /* Stop DC stream before configuring DSI registers
1677          * to avoid visible glitches on panel during transition
1678          * from bootloader to kernel driver
1679          */
1680         tegra_dsi_stop_dc_stream_at_frame_end(dc, dsi);
1681
1682         if (dsi->enabled) {
1683                 if (dsi->ulpm) {
1684                         if (tegra_dsi_exit_ulpm(dsi) < 0) {
1685                                 printk(KERN_ERR "DSI failed to exit ulpm\n");
1686                                 goto fail;
1687                         }
1688                 }
1689                 if (dsi->info.panel_reset) {
1690                         err = tegra_dsi_send_panel_cmd(dc, dsi,
1691                                                         dsi->info.dsi_init_cmd,
1692                                                         dsi->info.n_init_cmd);
1693                         if (err < 0) {
1694                                 dev_err(&dc->ndev->dev,
1695                                 "dsi: error while sending dsi init cmd\n");
1696                                 goto fail;
1697                         }
1698                 }
1699         } else {
1700                 err = tegra_dsi_init_hw(dc, dsi);
1701                 if (err < 0) {
1702                         dev_err(&dc->ndev->dev,
1703                                 "dsi: not able to init dsi hardware\n");
1704                         goto fail;
1705                 }
1706
1707                 if (dsi->ulpm) {
1708                         if (tegra_dsi_enter_ulpm(dsi) < 0) {
1709                                 printk(KERN_ERR "DSI failed to enter ulpm\n");
1710                                 goto fail;
1711                         }
1712                         val = DSI_PAD_CONTROL_PAD_PDIO(0) |
1713                                 DSI_PAD_CONTROL_PAD_PDIO_CLK(0) |
1714                                 DSI_PAD_CONTROL_PAD_PULLDN_ENAB(TEGRA_DSI_DISABLE);
1715                         tegra_dsi_writel(dsi, val, DSI_PAD_CONTROL);
1716                         if (tegra_dsi_exit_ulpm(dsi) < 0) {
1717                                 printk(KERN_ERR "DSI failed to exit ulpm\n");
1718                                 goto fail;
1719                         }
1720                 }
1721
1722                 err = tegra_dsi_set_to_lp_mode(dc, dsi);
1723                 if (err < 0) {
1724                         dev_err(&dc->ndev->dev,
1725                                 "dsi: not able to set to lp mode\n");
1726                         goto fail;
1727                 }
1728
1729                 err = tegra_dsi_send_panel_cmd(dc, dsi, dsi->info.dsi_init_cmd,
1730                                                 dsi->info.n_init_cmd);
1731                 if (err < 0) {
1732                         dev_err(&dc->ndev->dev,
1733                                 "dsi: error while sending dsi init cmd\n");
1734                         goto fail;
1735                 }
1736
1737                 err = tegra_dsi_set_to_hs_mode(dc, dsi);
1738                 if (err < 0) {
1739                         dev_err(&dc->ndev->dev,
1740                                 "dsi: not able to set to hs mode\n");
1741                         goto fail;
1742                 }
1743
1744                 dsi->enabled = true;
1745         }
1746
1747         if (dsi->status.driven == DSI_DRIVEN_MODE_DC)
1748                 tegra_dsi_start_dc_stream(dc, dsi);
1749 fail:
1750         mutex_unlock(&dsi->lock);
1751         tegra_dc_io_end(dc);
1752 }
1753
1754 static void _tegra_dc_dsi_init(struct tegra_dc *dc)
1755 {
1756         struct tegra_dc_dsi_data *dsi = tegra_dc_get_outdata(dc);
1757
1758         tegra_dsi_init_sw(dc, dsi);
1759         /* TODO: Configure the CSI pad configuration */
1760 }
1761
1762 static int tegra_dc_dsi_cp_p_cmd(struct tegra_dsi_cmd* src,
1763                                         struct tegra_dsi_cmd* dst, u16 n_cmd)
1764 {
1765         u16 i;
1766         u16 len;
1767
1768         memcpy(dst, src, sizeof(*dst) * n_cmd);
1769
1770         for (i = 0; i < n_cmd; i++)
1771                 if (src[i].pdata) {
1772                         len = sizeof(*src[i].pdata) * src[i].sp_len_dly.data_len;
1773                         dst[i].pdata = kzalloc(len, GFP_KERNEL);
1774                         if (!dst[i].pdata)
1775                                 goto free_cmd_pdata;
1776                         memcpy(dst[i].pdata, src[i].pdata, len);
1777                 }
1778
1779         return 0;
1780
1781 free_cmd_pdata:
1782         for (--i; i >=0; i--)
1783                 if (dst[i].pdata)
1784                         kfree(dst[i].pdata);
1785         return -ENOMEM;
1786 }
1787
1788 static int tegra_dc_dsi_cp_info(struct tegra_dc_dsi_data* dsi,
1789                                                 struct tegra_dsi_out* p_dsi)
1790 {
1791         struct tegra_dsi_cmd* p_init_cmd;
1792         struct tegra_dsi_cmd *p_suspend_cmd;
1793         int err;
1794
1795         if (p_dsi->n_data_lanes > MAX_DSI_DATA_LANES)
1796                 return -EINVAL;
1797
1798         p_init_cmd = kzalloc(sizeof(*p_init_cmd) * p_dsi->n_init_cmd, GFP_KERNEL);
1799         if (!p_init_cmd)
1800                 return -ENOMEM;
1801
1802         p_suspend_cmd = kzalloc(sizeof(*p_suspend_cmd) * p_dsi->n_suspend_cmd,
1803                                 GFP_KERNEL);
1804         if (!p_suspend_cmd) {
1805                 err = -ENOMEM;
1806                 goto err_free_p_init_cmd;
1807         }
1808
1809         memcpy(&dsi->info, p_dsi, sizeof(dsi->info));
1810
1811         err = tegra_dc_dsi_cp_p_cmd(p_dsi->dsi_init_cmd,
1812                                                 p_init_cmd, p_dsi->n_init_cmd);
1813         if (err < 0)
1814                 goto err_free;
1815         dsi->info.dsi_init_cmd = p_init_cmd;
1816
1817         err = tegra_dc_dsi_cp_p_cmd(p_dsi->dsi_suspend_cmd, p_suspend_cmd,
1818                                         p_dsi->n_suspend_cmd);
1819         if (err < 0)
1820                 goto err_free;
1821         dsi->info.dsi_suspend_cmd = p_suspend_cmd;
1822
1823         if (!dsi->info.panel_reset_timeout_msec)
1824                 dsi->info.panel_reset_timeout_msec = DEFAULT_PANEL_RESET_TIMEOUT;
1825
1826         if (!dsi->info.panel_buffer_size_byte)
1827                 dsi->info.panel_buffer_size_byte = DEFAULT_PANEL_BUFFER_BYTE;
1828
1829         if (!dsi->info.max_panel_freq_khz) {
1830                 dsi->info.max_panel_freq_khz = DEFAULT_MAX_DSI_PHY_CLK_KHZ;
1831
1832                 if (dsi->info.video_burst_mode >
1833                                 TEGRA_DSI_VIDEO_NONE_BURST_MODE_WITH_SYNC_END){
1834                         dev_err(&dsi->dc->ndev->dev, "DSI: max_panel_freq_khz"
1835                                         "is not set for DSI burst mode.\n");
1836                         dsi->info.video_burst_mode =
1837                                 TEGRA_DSI_VIDEO_BURST_MODE_LOWEST_SPEED;
1838                 }
1839         }
1840
1841         if (!dsi->info.lp_cmd_mode_freq_khz)
1842                 dsi->info.lp_cmd_mode_freq_khz = DEFAULT_LP_CMD_MODE_CLK_KHZ;
1843
1844         /* host mode is for testing only*/
1845         dsi->driven_mode = TEGRA_DSI_DRIVEN_BY_DC;
1846
1847         return 0;
1848
1849 err_free:
1850         kfree(p_suspend_cmd);
1851 err_free_p_init_cmd:
1852         kfree(p_init_cmd);
1853         return err;
1854 }
1855
1856 static int tegra_dc_dsi_init(struct tegra_dc *dc)
1857 {
1858         struct tegra_dc_dsi_data *dsi;
1859         struct resource *res;
1860         struct resource *base_res;
1861         void __iomem *base;
1862         struct clk *dc_clk = NULL;
1863         struct clk *dsi_clk = NULL;
1864         struct tegra_dsi_out *dsi_pdata;
1865         int err;
1866
1867         err = 0;
1868
1869         dsi = kzalloc(sizeof(*dsi), GFP_KERNEL);
1870         if (!dsi)
1871                 return -ENOMEM;
1872
1873         res = nvhost_get_resource_byname(dc->ndev, IORESOURCE_MEM,
1874                                         "dsi_regs");
1875         if (!res) {
1876                 dev_err(&dc->ndev->dev, "dsi: no mem resource\n");
1877                 err = -ENOENT;
1878                 goto err_free_dsi;
1879         }
1880
1881         base_res = request_mem_region(res->start, resource_size(res),
1882                                 dc->ndev->name);
1883         if (!base_res) {
1884                 dev_err(&dc->ndev->dev, "dsi: request_mem_region failed\n");
1885                 err = -EBUSY;
1886                 goto err_free_dsi;
1887         }
1888
1889         base = ioremap(res->start, resource_size(res));
1890         if (!base) {
1891                 dev_err(&dc->ndev->dev, "dsi: registers can't be mapped\n");
1892                 err = -EBUSY;
1893                 goto err_release_regs;
1894         }
1895
1896         dsi_pdata = dc->pdata->default_out->dsi;
1897         if (!dsi_pdata) {
1898                 dev_err(&dc->ndev->dev, "dsi: dsi data not available\n");
1899                 goto err_release_regs;
1900         }
1901
1902         if (dsi_pdata->dsi_instance)
1903                 dsi_clk = clk_get(&dc->ndev->dev, "dsib");
1904         else
1905                 dsi_clk = clk_get(&dc->ndev->dev, "dsia");
1906
1907         if (IS_ERR_OR_NULL(dsi_clk)) {
1908                 dev_err(&dc->ndev->dev, "dsi: can't get clock\n");
1909                 err = -EBUSY;
1910                 goto err_release_regs;
1911         }
1912
1913         dc_clk = clk_get_sys(dev_name(&dc->ndev->dev), NULL);
1914         if (IS_ERR_OR_NULL(dc_clk)) {
1915                 dev_err(&dc->ndev->dev, "dsi: dc clock %s unavailable\n",
1916                         dev_name(&dc->ndev->dev));
1917                 err = -EBUSY;
1918                 goto err_clk_put;
1919         }
1920
1921         err = tegra_dc_dsi_cp_info(dsi, dsi_pdata);
1922         if (err < 0)
1923                 goto err_dsi_data;
1924
1925         mutex_init(&dsi->lock);
1926         dsi->dc = dc;
1927         dsi->base = base;
1928         dsi->base_res = base_res;
1929         dsi->dc_clk = dc_clk;
1930         dsi->dsi_clk = dsi_clk;
1931
1932         tegra_dc_set_outdata(dc, dsi);
1933         _tegra_dc_dsi_init(dc);
1934
1935         return 0;
1936
1937 err_dsi_data:
1938 err_clk_put:
1939         clk_put(dsi_clk);
1940 err_release_regs:
1941         release_resource(base_res);
1942 err_free_dsi:
1943         kfree(dsi);
1944
1945         return err;
1946 }
1947
1948 static void tegra_dc_dsi_destroy(struct tegra_dc *dc)
1949 {
1950         struct tegra_dc_dsi_data *dsi = tegra_dc_get_outdata(dc);
1951         u16 i;
1952         u32 val;
1953
1954         mutex_lock(&dsi->lock);
1955
1956         /* free up the pdata*/
1957         for(i = 0; i < dsi->info.n_init_cmd; i++){
1958                 if(dsi->info.dsi_init_cmd[i].pdata)
1959                         kfree(dsi->info.dsi_init_cmd[i].pdata);
1960         }
1961         kfree(dsi->info.dsi_init_cmd);
1962
1963         /* Disable dc stream*/
1964         if(dsi->status.dc_stream == DSI_DC_STREAM_ENABLE)
1965                 tegra_dsi_stop_dc_stream(dc, dsi);
1966
1967         /* Disable dsi phy clock*/
1968         if(dsi->status.clk_out == DSI_PHYCLK_OUT_EN)
1969                 tegra_dsi_hs_clk_out_disable(dc, dsi);
1970
1971         val = DSI_POWER_CONTROL_LEG_DSI_ENABLE(TEGRA_DSI_DISABLE);
1972         tegra_dsi_writel(dsi, val, DSI_POWER_CONTROL);
1973
1974         iounmap(dsi->base);
1975         release_resource(dsi->base_res);
1976
1977         clk_put(dsi->dc_clk);
1978         clk_put(dsi->dsi_clk);
1979
1980         mutex_unlock(&dsi->lock);
1981
1982         mutex_destroy(&dsi->lock);
1983         kfree(dsi);
1984 }
1985
1986 static void tegra_dc_dsi_disable(struct tegra_dc *dc)
1987 {
1988         struct tegra_dc_dsi_data *dsi = tegra_dc_get_outdata(dc);
1989
1990         mutex_lock(&dsi->lock);
1991
1992         if (dsi->status.dc_stream == DSI_DC_STREAM_ENABLE)
1993                 tegra_dsi_stop_dc_stream(dc, dsi);
1994
1995         if (!dsi->ulpm) {
1996                 if (tegra_dsi_enter_ulpm(dsi) < 0)
1997                         printk(KERN_ERR "DSI failed to enter ulpm\n");
1998         }
1999
2000         mutex_unlock(&dsi->lock);
2001 }
2002
2003 #ifdef CONFIG_PM
2004 static void tegra_dc_dsi_suspend(struct tegra_dc *dc)
2005 {
2006         struct tegra_dc_dsi_data *dsi;
2007         int err;
2008         u32 val;
2009
2010         dsi = tegra_dc_get_outdata(dc);
2011
2012         tegra_dc_io_start(dc);
2013         mutex_lock(&dsi->lock);
2014
2015         if (!dsi->enabled)
2016                 goto fail;
2017
2018         if (dsi->ulpm) {
2019                 if (tegra_dsi_exit_ulpm(dsi) < 0) {
2020                         printk(KERN_ERR "DSI failed to exit ulpm");
2021                         goto fail;
2022                 }
2023         }
2024
2025         /* Suspend Panel */
2026         err = tegra_dsi_send_panel_cmd(dc, dsi, dsi->info.dsi_suspend_cmd,
2027                                 dsi->info.n_suspend_cmd);
2028         if (err < 0) {
2029                 dev_err(&dc->ndev->dev,
2030                         "dsi: Error while sending dsi suspend cmd\n");
2031                 goto fail;
2032         }
2033
2034         if (!dsi->ulpm) {
2035                 if (tegra_dsi_enter_ulpm(dsi) < 0) {
2036                         printk(KERN_ERR "DSI failed to enter ulpm\n");
2037                         goto fail;
2038                 }
2039         }
2040
2041         /* Suspend pad */
2042         val = tegra_dsi_readl(dsi, DSI_PAD_CONTROL);
2043         val = DSI_PAD_CONTROL_PAD_PDIO(0x3) |
2044                 DSI_PAD_CONTROL_PAD_PDIO_CLK(0x1) |
2045                 DSI_PAD_CONTROL_PAD_PULLDN_ENAB(TEGRA_DSI_ENABLE);
2046         tegra_dsi_writel(dsi, val, DSI_PAD_CONTROL);
2047
2048         /* Suspend core-logic */
2049         val = DSI_POWER_CONTROL_LEG_DSI_ENABLE(TEGRA_DSI_DISABLE);
2050         tegra_dsi_writel(dsi, val, DSI_POWER_CONTROL);
2051
2052         dsi->enabled = false;
2053
2054         clk_disable(dsi->dsi_clk);
2055 fail:
2056         mutex_unlock(&dsi->lock);
2057         tegra_dc_io_end(dc);
2058 }
2059
2060 static void tegra_dc_dsi_resume(struct tegra_dc *dc)
2061 {
2062         /* Not required since tegra_dc_dsi_enable
2063          * will reconfigure the controller from scratch
2064          */
2065 }
2066 #endif
2067
2068 struct tegra_dc_out_ops tegra_dc_dsi_ops = {
2069         .init = tegra_dc_dsi_init,
2070         .destroy = tegra_dc_dsi_destroy,
2071         .enable = tegra_dc_dsi_enable,
2072         .disable = tegra_dc_dsi_disable,
2073 #ifdef CONFIG_PM
2074         .suspend = tegra_dc_dsi_suspend,
2075         .resume = tegra_dc_dsi_resume,
2076 #endif
2077 };