video: tegra: dsi: Adjusted the values of packet sequence registers.
[linux-2.6.git] / drivers / video / tegra / dc / dsi.c
1 /*
2  * drivers/video/tegra/dc/dsi.c
3  *
4  * Copyright (c) 2011, NVIDIA Corporation.
5  *
6  * This software is licensed under the terms of the GNU General Public
7  * License version 2, as published by the Free Software Foundation, and
8  * may be copied, distributed, and modified under those terms.
9  *
10  * This program is distributed in the hope that it will be useful,
11  * but WITHOUT ANY WARRANTY; without even the implied warranty of
12  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
13  * GNU General Public License for more details.
14  *
15  */
16
17 #include <linux/clk.h>
18 #include <linux/delay.h>
19 #include <linux/err.h>
20 #include <linux/fb.h>
21 #include <linux/gpio.h>
22 #include <linux/interrupt.h>
23 #include <linux/kernel.h>
24 #include <linux/slab.h>
25 #include <linux/spinlock.h>
26 #include <linux/workqueue.h>
27
28 #include <mach/clk.h>
29 #include <mach/dc.h>
30 #include <mach/fb.h>
31 #include <mach/nvhost.h>
32 #include <../gpio-names.h>
33
34 #include "dc_reg.h"
35 #include "dc_priv.h"
36 #include "dsi_regs.h"
37 #include "dsi.h"
38
39 #define DSI_USE_SYNC_POINTS 0
40
41 #define DSI_STOP_DC_DURATION_MSEC 1000
42
43 #define DSI_MODULE_NOT_INIT             0x0
44 #define DSI_MODULE_INIT                 0x1
45
46 #define DSI_LPHS_NOT_INIT               0x0
47 #define DSI_LPHS_IN_LP_MODE             0x1
48 #define DSI_LPHS_IN_HS_MODE             0x2
49
50 #define DSI_VIDEO_TYPE_NOT_INIT         0x0
51 #define DSI_VIDEO_TYPE_VIDEO_MODE       0x1
52 #define DSI_VIDEO_TYPE_CMD_MODE         0x2
53
54 #define DSI_DRIVEN_MODE_NOT_INIT        0x0
55 #define DSI_DRIVEN_MODE_DC              0x1
56 #define DSI_DRIVEN_MODE_HOST            0x2
57
58 #define DSI_PHYCLK_OUT_DIS              0x0
59 #define DSI_PHYCLK_OUT_EN               0x1
60
61 #define DSI_PHYCLK_NOT_INIT             0x0
62 #define DSI_PHYCLK_CONTINUOUS           0x1
63 #define DSI_PHYCLK_TX_ONLY              0x2
64
65 #define DSI_CLK_BURST_NOT_INIT          0x0
66 #define DSI_CLK_BURST_NONE_BURST        0x1
67 #define DSI_CLK_BURST_BURST_MODE        0x2
68
69 #define DSI_DC_STREAM_DISABLE           0x0
70 #define DSI_DC_STREAM_ENABLE            0x1
71
72 struct dsi_status {
73         unsigned        init:2;
74
75         unsigned        lphs:2;
76
77         unsigned        vtype:2;
78         unsigned        driven:2;
79
80         unsigned        clk_out:2;
81         unsigned        clk_mode:2;
82         unsigned        clk_burst:2;
83
84         unsigned        dc_stream:1;
85 };
86
87 /* source of video data */
88 enum{
89         TEGRA_DSI_DRIVEN_BY_DC,
90         TEGRA_DSI_DRIVEN_BY_HOST,
91 };
92
93 struct tegra_dc_dsi_data {
94         struct tegra_dc *dc;
95         void __iomem    *base;
96         struct resource *base_res;
97
98         struct clk              *dc_clk;
99         struct clk              *dsi_clk;
100
101         struct mutex    lock;
102
103         /* data from board info */
104         struct tegra_dsi_out info;
105
106         struct dsi_status       status;
107
108         u8              driven_mode;
109         u8              controller_index;
110
111         u8              pixel_scaler_mul;
112         u8              pixel_scaler_div;
113
114         u32             default_pixel_clk_khz;
115         u32             default_hs_clk_khz;
116
117         u32             target_hs_clk_khz;
118         u32             target_lp_clk_khz;
119
120         u16             current_bit_clk_ns;
121         u32             current_dsi_clk_khz;
122
123         u32             dsi_control_val;
124 };
125
126 const u32 dsi_pkt_seq_reg[NUMOF_PKT_SEQ] = {
127         DSI_PKT_SEQ_0_LO,
128         DSI_PKT_SEQ_0_HI,
129         DSI_PKT_SEQ_1_LO,
130         DSI_PKT_SEQ_1_HI,
131         DSI_PKT_SEQ_2_LO,
132         DSI_PKT_SEQ_2_HI,
133         DSI_PKT_SEQ_3_LO,
134         DSI_PKT_SEQ_3_HI,
135         DSI_PKT_SEQ_4_LO,
136         DSI_PKT_SEQ_4_HI,
137         DSI_PKT_SEQ_5_LO,
138         DSI_PKT_SEQ_5_HI,
139 };
140
141 const u32 dsi_pkt_seq_video_non_burst_syne[NUMOF_PKT_SEQ] = {
142         PKT_ID0(CMD_VS) | PKT_LEN0(0) | PKT_ID1(CMD_EOT) | PKT_LEN1(0) | PKT_LP,
143         0,
144         PKT_ID0(CMD_VE) | PKT_LEN0(0) | PKT_ID1(CMD_EOT) | PKT_LEN1(0) | PKT_LP,
145         0,
146         PKT_ID0(CMD_HS) | PKT_LEN0(0) | PKT_ID1(CMD_EOT) | PKT_LEN1(0) | PKT_LP,
147         0,
148         PKT_ID0(CMD_HS) | PKT_LEN0(0) | PKT_ID1(CMD_BLNK) | PKT_LEN1(1) |
149                 PKT_ID2(CMD_HE) | PKT_LEN2(0),
150         PKT_ID3(CMD_BLNK) | PKT_LEN3(2) | PKT_ID4(CMD_RGB) | PKT_LEN4(3) |
151                 PKT_ID5(CMD_BLNK) | PKT_LEN5(4),
152         PKT_ID0(CMD_HS) | PKT_LEN0(0) | PKT_ID1(CMD_EOT) | PKT_LEN1(0) | PKT_LP,
153         0,
154         PKT_ID0(CMD_HS) | PKT_LEN0(0) | PKT_ID1(CMD_BLNK) | PKT_LEN1(1) |
155                 PKT_ID2(CMD_HE) | PKT_LEN2(0),
156         PKT_ID3(CMD_BLNK) | PKT_LEN3(2) | PKT_ID4(CMD_RGB) | PKT_LEN4(3) |
157                 PKT_ID5(CMD_BLNK) | PKT_LEN5(4),
158 };
159
160 const u32 dsi_pkt_seq_video_non_burst[NUMOF_PKT_SEQ] = {
161         PKT_ID0(CMD_VS) | PKT_LEN0(0) | PKT_ID1(CMD_EOT) | PKT_LEN1(0) | PKT_LP,
162         0,
163         PKT_ID0(CMD_HS) | PKT_LEN0(0) | PKT_ID1(CMD_EOT) | PKT_LEN1(0) | PKT_LP,
164         0,
165         PKT_ID0(CMD_HS) | PKT_LEN0(0) | PKT_ID1(CMD_EOT) | PKT_LEN1(0) | PKT_LP,
166         0,
167         PKT_ID0(CMD_HS) | PKT_LEN0(0) | PKT_ID1(CMD_BLNK) | PKT_LEN1(2) |
168                 PKT_ID2(CMD_RGB) | PKT_LEN2(3),
169         PKT_ID3(CMD_BLNK) | PKT_LEN3(4),
170         PKT_ID0(CMD_HS) | PKT_LEN0(0) | PKT_ID1(CMD_EOT) | PKT_LEN1(0) | PKT_LP,
171         0,
172         PKT_ID0(CMD_HS) | PKT_LEN0(0) | PKT_ID1(CMD_BLNK) | PKT_LEN1(2) |
173                 PKT_ID2(CMD_RGB) | PKT_LEN2(3),
174         PKT_ID3(CMD_BLNK) | PKT_LEN3(4),
175 };
176
177 static const u32 dsi_pkt_seq_video_burst[NUMOF_PKT_SEQ] = {
178         PKT_ID0(CMD_VS) | PKT_LEN0(0) | PKT_ID1(CMD_EOT) | PKT_LEN1(7) | PKT_LP,
179         0,
180         PKT_ID0(CMD_HS) | PKT_LEN0(0) | PKT_ID1(CMD_EOT) | PKT_LEN1(7) | PKT_LP,
181         0,
182         PKT_ID0(CMD_HS) | PKT_LEN0(0) | PKT_ID1(CMD_EOT) | PKT_LEN1(7) | PKT_LP,
183         0,
184         PKT_ID0(CMD_HS) | PKT_LEN0(0) | PKT_ID1(CMD_BLNK) | PKT_LEN1(2)|
185         PKT_ID2(CMD_RGB) | PKT_LEN2(3) | PKT_LP,
186         PKT_ID0(CMD_EOT) | PKT_LEN0(7),
187         PKT_ID0(CMD_HS) | PKT_LEN0(0) | PKT_ID1(CMD_EOT) | PKT_LEN1(7) | PKT_LP,
188         0,
189         PKT_ID0(CMD_HS) | PKT_LEN0(0) | PKT_ID1(CMD_BLNK) | PKT_LEN1(2)|
190         PKT_ID2(CMD_RGB) | PKT_LEN2(3) | PKT_LP,
191         PKT_ID0(CMD_EOT) | PKT_LEN0(7),
192 };
193
194 static const u32 dsi_pkt_seq_video_burst_no_eot[NUMOF_PKT_SEQ] = {
195         PKT_ID0(CMD_VS) | PKT_LEN0(0) | PKT_ID1(CMD_EOT) | PKT_LEN1(0) | PKT_LP,
196         0,
197         PKT_ID0(CMD_HS) | PKT_LEN0(0) | PKT_ID1(CMD_EOT) | PKT_LEN1(0) | PKT_LP,
198         0,
199         PKT_ID0(CMD_HS) | PKT_LEN0(0) | PKT_ID1(CMD_EOT) | PKT_LEN1(0) | PKT_LP,
200         0,
201         PKT_ID0(CMD_HS) | PKT_LEN0(0) | PKT_ID1(CMD_BLNK) | PKT_LEN1(2)|
202         PKT_ID2(CMD_RGB) | PKT_LEN2(3) | PKT_LP,
203         PKT_ID0(CMD_EOT) | PKT_LEN0(0),
204         PKT_ID0(CMD_HS) | PKT_LEN0(0) | PKT_ID1(CMD_EOT) | PKT_LEN1(0) | PKT_LP,
205         0,
206         PKT_ID0(CMD_HS) | PKT_LEN0(0) | PKT_ID1(CMD_BLNK) | PKT_LEN1(2)|
207         PKT_ID2(CMD_RGB) | PKT_LEN2(3) | PKT_LP,
208         PKT_ID0(CMD_EOT) | PKT_LEN0(0),
209 };
210
211 /* TODO: verify with hw about this format */
212 const u32 dsi_pkt_seq_cmd_mode [NUMOF_PKT_SEQ] = {
213         0,
214         0,
215         0,
216         0,
217         0,
218         0,
219         PKT_ID0(CMD_LONGW) | PKT_LEN0(3) | PKT_ID1(CMD_EOT) | PKT_LEN1(7),
220         0,
221         0,
222         0,
223         PKT_ID0(CMD_LONGW) | PKT_LEN0(3) | PKT_ID1(CMD_EOT) | PKT_LEN1(7),
224         0,
225 };
226
227 const u32 init_reg[] = {
228         DSI_WR_DATA,
229         DSI_INT_ENABLE,
230         DSI_INT_STATUS,
231         DSI_INT_MASK,
232         DSI_INIT_SEQ_DATA_0,
233         DSI_INIT_SEQ_DATA_1,
234         DSI_INIT_SEQ_DATA_2,
235         DSI_INIT_SEQ_DATA_3,
236         DSI_DCS_CMDS,
237         DSI_PKT_SEQ_0_LO,
238         DSI_PKT_SEQ_1_LO,
239         DSI_PKT_SEQ_2_LO,
240         DSI_PKT_SEQ_3_LO,
241         DSI_PKT_SEQ_4_LO,
242         DSI_PKT_SEQ_5_LO,
243         DSI_PKT_SEQ_0_HI,
244         DSI_PKT_SEQ_1_HI,
245         DSI_PKT_SEQ_2_HI,
246         DSI_PKT_SEQ_3_HI,
247         DSI_PKT_SEQ_4_HI,
248         DSI_PKT_SEQ_5_HI,
249         DSI_CONTROL,
250         DSI_HOST_DSI_CONTROL,
251         DSI_PAD_CONTROL,
252         DSI_PAD_CONTROL_CD,
253         DSI_SOL_DELAY,
254         DSI_MAX_THRESHOLD,
255         DSI_TRIGGER,
256         DSI_TX_CRC,
257         DSI_INIT_SEQ_CONTROL,
258         DSI_PKT_LEN_0_1,
259         DSI_PKT_LEN_2_3,
260         DSI_PKT_LEN_4_5,
261         DSI_PKT_LEN_6_7,
262 };
263
264 static inline unsigned long tegra_dsi_readl(struct tegra_dc_dsi_data *dsi,
265                                                                         u32 reg)
266 {
267         return readl(dsi->base + reg * 4);
268 }
269
270 static inline void tegra_dsi_writel(struct tegra_dc_dsi_data *dsi,u32 val,
271                                                                         u32 reg)
272 {
273         writel(val, dsi->base + reg * 4);
274 }
275
276 static u32 tegra_dsi_get_hs_clk_rate(struct tegra_dc_dsi_data *dsi)
277 {
278         u32 dsi_clock_rate_khz;
279
280         switch (dsi->info.video_burst_mode) {
281         case TEGRA_DSI_VIDEO_BURST_MODE_LOW_SPEED:
282         case TEGRA_DSI_VIDEO_BURST_MODE_MEDIUM_SPEED:
283         case TEGRA_DSI_VIDEO_BURST_MODE_FAST_SPEED:
284         case TEGRA_DSI_VIDEO_BURST_MODE_FASTEST_SPEED:
285                 /* TODO: implement algo for these speed rate */
286
287         case TEGRA_DSI_VIDEO_BURST_MODE_MANUAL:
288                 if (dsi->info.burst_mode_freq_khz) {
289                         dsi_clock_rate_khz = dsi->info.burst_mode_freq_khz;
290                         break;
291                 }
292         case TEGRA_DSI_VIDEO_NONE_BURST_MODE:
293         case TEGRA_DSI_VIDEO_NONE_BURST_MODE_WITH_SYNC_END:
294         case TEGRA_DSI_VIDEO_BURST_MODE_LOWEST_SPEED:
295         default:
296                 dsi_clock_rate_khz = dsi->default_hs_clk_khz;
297                 break;
298         }
299
300         return dsi_clock_rate_khz;
301 }
302
303 static u32 tegra_dsi_get_lp_clk_rate(struct tegra_dc_dsi_data *dsi)
304 {
305         u32 dsi_clock_rate_khz;
306
307         if (dsi->info.enable_hs_clock_on_lp_cmd_mode)
308                 if (dsi->info.hs_clk_in_lp_cmd_mode_freq_khz)
309                         dsi_clock_rate_khz =
310                                 dsi->info.hs_clk_in_lp_cmd_mode_freq_khz;
311                 else
312                         dsi_clock_rate_khz = tegra_dsi_get_hs_clk_rate(dsi);
313         else
314                 dsi_clock_rate_khz = dsi->info.lp_cmd_mode_freq_khz;
315
316         return dsi_clock_rate_khz;
317 }
318
319 static void tegra_dsi_init_sw(struct tegra_dc *dc,
320                                                 struct tegra_dc_dsi_data *dsi)
321 {
322         u32 h_width_pixels;
323         u32 v_width_lines;
324         u32 pixel_clk_hz;
325         u32 byte_clk_hz;
326
327         switch (dsi->info.pixel_format) {
328                 case TEGRA_DSI_PIXEL_FORMAT_16BIT_P:
329                         /* 2 bytes per pixel */
330                         dsi->pixel_scaler_mul = 2;
331                         dsi->pixel_scaler_div = 1;
332                         break;
333                 case TEGRA_DSI_PIXEL_FORMAT_18BIT_P:
334                         /* 2.25 bytes per pixel */
335                         dsi->pixel_scaler_mul = 9;
336                         dsi->pixel_scaler_div = 4;
337                         break;
338                 case TEGRA_DSI_PIXEL_FORMAT_18BIT_NP:
339                 case TEGRA_DSI_PIXEL_FORMAT_24BIT_P:
340                         /* 3 bytes per pixel */
341                         dsi->pixel_scaler_mul = 3;
342                         dsi->pixel_scaler_div = 1;
343                         break;
344                 default:
345                         break;
346         }
347
348         h_width_pixels = dc->mode.h_back_porch + dc->mode.h_front_porch +
349                         dc->mode.h_sync_width + dc->mode.h_active;
350         v_width_lines = dc->mode.v_back_porch + dc->mode.v_front_porch +
351                         dc->mode.v_sync_width + dc->mode.v_active;
352
353         /* The slowest pixel rate that is required */
354         /*   for the given display timing       */
355         pixel_clk_hz = h_width_pixels * v_width_lines * dsi->info.refresh_rate;
356
357         /* Pixel byte rate on DSI interface */
358         byte_clk_hz     = (pixel_clk_hz * dsi->pixel_scaler_mul) /
359                         (dsi->pixel_scaler_div * dsi->info.n_data_lanes);
360
361         dsi->default_pixel_clk_khz = pixel_clk_hz / 1000;
362
363         printk("dsi: default pixel rate %d khz\n", dsi->default_pixel_clk_khz);
364
365         /*
366          * Pixel bit rate on DSI. Since DSI interface is double data rate (
367          * transferring data on both rising and falling edge of clk), div by 2
368          * to get the actual clock rate.
369          */
370         dsi->default_hs_clk_khz =
371                         (byte_clk_hz * NUMOF_BIT_PER_BYTE) / (1000 * 2);
372
373         dsi->controller_index = dc->ndev->id;
374
375         dsi->dsi_control_val =
376                         DSI_CONTROL_VIRTUAL_CHANNEL(dsi->info.virtual_channel) |
377                         DSI_CONTROL_NUM_DATA_LANES(dsi->info.n_data_lanes - 1) |
378                         DSI_CONTROL_VID_SOURCE(dsi->controller_index) |
379                         DSI_CONTROL_DATA_FORMAT(dsi->info.pixel_format);
380
381         dsi->target_lp_clk_khz = tegra_dsi_get_lp_clk_rate(dsi);
382         dsi->target_hs_clk_khz = tegra_dsi_get_hs_clk_rate(dsi);
383
384         /*
385          * Force video clock to be continuous mode if
386          * enable_hs_clock_on_lp_cmd_mode is set
387          */
388         if (dsi->info.enable_hs_clock_on_lp_cmd_mode) {
389                 if (dsi->info.video_clock_mode != TEGRA_DSI_VIDEO_CLOCK_CONTINUOUS)
390                         printk("Force to clock continuous mode\n");
391
392                 dsi->info.video_clock_mode = TEGRA_DSI_VIDEO_CLOCK_CONTINUOUS;
393         }
394
395 }
396
397 static void tegra_dsi_get_phy_timing(struct tegra_dc_dsi_data *dsi,
398                                 struct dsi_phy_timing_inclk *phy_timing_clk,
399                                 u32 clk_ns)
400 {
401
402         phy_timing_clk->t_hsdexit = dsi->info.phy_timing.t_hsdexit_ns ?
403                         (dsi->info.phy_timing.t_hsdexit_ns / clk_ns) :
404                         (T_HSEXIT_DEFAULT(clk_ns));
405
406         phy_timing_clk->t_hstrail = dsi->info.phy_timing.t_hstrail_ns ?
407                         (dsi->info.phy_timing.t_hstrail_ns / clk_ns) :
408                         (T_HSTRAIL_DEFAULT(clk_ns));
409
410         phy_timing_clk->t_datzero = dsi->info.phy_timing.t_datzero_ns ?
411                         (dsi->info.phy_timing.t_datzero_ns / clk_ns) :
412                         (T_DATZERO_DEFAULT(clk_ns));
413
414         phy_timing_clk->t_hsprepr = dsi->info.phy_timing.t_hsprepr_ns ?
415                         (dsi->info.phy_timing.t_hsprepr_ns / clk_ns) :
416                         (T_HSPREPR_DEFAULT(clk_ns));
417
418         phy_timing_clk->t_clktrail = dsi->info.phy_timing.t_clktrail_ns ?
419                                 (dsi->info.phy_timing.t_clktrail_ns / clk_ns) :
420                                 (T_CLKTRAIL_DEFAULT(clk_ns));
421
422         phy_timing_clk->t_clkpost = dsi->info.phy_timing.t_clkpost_ns ?
423                                 (dsi->info.phy_timing.t_clkpost_ns / clk_ns) :
424                                 (T_CLKPOST_DEFAULT(clk_ns));
425
426         phy_timing_clk->t_clkzero = dsi->info.phy_timing.t_clkzero_ns ?
427                                 (dsi->info.phy_timing.t_clkzero_ns / clk_ns) :
428                                 (T_CLKZERO_DEFAULT(clk_ns));
429
430         phy_timing_clk->t_tlpx = dsi->info.phy_timing.t_tlpx_ns ?
431                                 (dsi->info.phy_timing.t_tlpx_ns / clk_ns) :
432                                 (T_TLPX_DEFAULT(clk_ns));
433
434         phy_timing_clk->t_clkpre = T_CLKPRE_DEFAULT(clk_ns);
435         phy_timing_clk->t_clkprepare = T_CLKPREPARE_DEFAULT(clk_ns);
436         phy_timing_clk->t_wakeup = T_WAKEUP_DEFAULT(clk_ns);
437
438         phy_timing_clk->t_taget = 5 * phy_timing_clk->t_tlpx;
439         phy_timing_clk->t_tasure = 2 * phy_timing_clk->t_tlpx;
440         phy_timing_clk->t_tago = 4 * phy_timing_clk->t_tlpx;
441 }
442
443 static void tegra_dsi_set_phy_timing(struct tegra_dc_dsi_data *dsi)
444 {
445         u32 val;
446         struct dsi_phy_timing_inclk     phy_timing;
447
448         tegra_dsi_get_phy_timing(dsi, &phy_timing, dsi->current_bit_clk_ns);
449
450         val = DSI_PHY_TIMING_0_THSDEXIT(phy_timing.t_hsdexit) |
451                         DSI_PHY_TIMING_0_THSTRAIL(phy_timing.t_hstrail) |
452                         DSI_PHY_TIMING_0_TDATZERO(phy_timing.t_datzero) |
453                         DSI_PHY_TIMING_0_THSPREPR(phy_timing.t_hsprepr);
454         tegra_dsi_writel(dsi, val, DSI_PHY_TIMING_0);
455
456         val = DSI_PHY_TIMING_1_TCLKTRAIL(phy_timing.t_clktrail) |
457                         DSI_PHY_TIMING_1_TCLKPOST(phy_timing.t_clkpost) |
458                         DSI_PHY_TIMING_1_TCLKZERO(phy_timing.t_clkzero) |
459                         DSI_PHY_TIMING_1_TTLPX(phy_timing.t_tlpx);
460         tegra_dsi_writel(dsi, val, DSI_PHY_TIMING_1);
461
462         val = DSI_PHY_TIMING_2_TCLKPREPARE(phy_timing.t_clkprepare) |
463                 DSI_PHY_TIMING_2_TCLKPRE(phy_timing.t_clkpre) |
464                         DSI_PHY_TIMING_2_TWAKEUP(phy_timing.t_wakeup);
465         tegra_dsi_writel(dsi, val, DSI_PHY_TIMING_2);
466
467         val = DSI_BTA_TIMING_TTAGET(phy_timing.t_taget) |
468                         DSI_BTA_TIMING_TTASURE(phy_timing.t_tasure) |
469                         DSI_BTA_TIMING_TTAGO(phy_timing.t_tago);
470         tegra_dsi_writel(dsi, val, DSI_BTA_TIMING);
471 }
472
473 static u32 tegra_dsi_sol_delay_burst(struct tegra_dc *dc,
474                                                 struct tegra_dc_dsi_data *dsi)
475 {
476         u32 dsi_to_pixel_clk_ratio;
477         u32 temp;
478         u32 temp1;
479         u32 mipi_clk_adj_kHz;
480         u32 sol_delay;
481         struct tegra_dc_mode *dc_modes = &dc->mode;
482
483         /* Get Fdsi/Fpixel ration (note: Fdsi si in bit format) */
484         dsi_to_pixel_clk_ratio = (dsi->current_dsi_clk_khz * 2 +
485                 dsi->default_pixel_clk_khz - 1) / dsi->default_pixel_clk_khz;
486
487         /* Convert Fdsi to byte format */
488         dsi_to_pixel_clk_ratio *= 1000/8;
489
490         /* Multiplying by 1000 so that we don't loose the fraction part */
491         temp = dc_modes->h_active * 1000;
492         temp1 = dc_modes->h_active + dc_modes->h_back_porch +
493                         dc_modes->h_sync_width;
494
495         sol_delay = temp1 * dsi_to_pixel_clk_ratio -
496                         temp * dsi->pixel_scaler_mul /
497                         (dsi->pixel_scaler_div * dsi->info.n_data_lanes);
498
499         /* Do rounding on sol delay */
500         sol_delay = (sol_delay + 1000 - 1)/1000;
501
502         /* TODO:
503          * 1. find out the correct sol fifo depth to use
504          * 2. verify with hw about the clamping function
505          */
506         if (sol_delay > (480 * 4)) {
507                 sol_delay = (480 * 4);
508                 mipi_clk_adj_kHz = sol_delay +
509                         (dc_modes->h_active * dsi->pixel_scaler_mul) /
510                         (dsi->info.n_data_lanes * dsi->pixel_scaler_div);
511
512                 mipi_clk_adj_kHz *= (dsi->default_pixel_clk_khz / temp1);
513
514                 mipi_clk_adj_kHz *= 4;
515         }
516
517         dsi->target_hs_clk_khz = mipi_clk_adj_kHz;
518
519         return sol_delay;
520 }
521
522 static void tegra_dsi_set_sol_delay(struct tegra_dc *dc,
523                                                 struct tegra_dc_dsi_data *dsi)
524 {
525         u32 sol_delay;
526
527         if (dsi->info.video_burst_mode == TEGRA_DSI_VIDEO_NONE_BURST_MODE ||
528                 dsi->info.video_burst_mode ==
529                                 TEGRA_DSI_VIDEO_NONE_BURST_MODE_WITH_SYNC_END) {
530                 sol_delay = NUMOF_BIT_PER_BYTE * dsi->pixel_scaler_mul /
531                         (dsi->pixel_scaler_div * dsi->info.n_data_lanes);
532                 dsi->status.clk_burst = DSI_CLK_BURST_NONE_BURST;
533         } else {
534                 sol_delay = tegra_dsi_sol_delay_burst(dc, dsi);
535                 dsi->status.clk_burst = DSI_CLK_BURST_BURST_MODE;
536         }
537
538         tegra_dsi_writel(dsi, DSI_SOL_DELAY_SOL_DELAY(sol_delay),
539                                                                 DSI_SOL_DELAY);
540 }
541
542 static void tegra_dsi_set_timeout(struct tegra_dc_dsi_data *dsi)
543 {
544         u32 val;
545         u32 bytes_per_frame;
546         u32 timeout = 0;
547
548         /* TODO: verify the following eq */
549         bytes_per_frame = dsi->current_dsi_clk_khz * 1000 * 2 /
550                                                 (dsi->info.refresh_rate * 8);
551         timeout = bytes_per_frame / DSI_CYCLE_COUNTER_VALUE;
552         timeout = (timeout + DSI_HTX_TO_MARGIN) & 0xffff;
553
554         val = DSI_TIMEOUT_0_LRXH_TO(DSI_LRXH_TO_VALUE) |
555                         DSI_TIMEOUT_0_HTX_TO(timeout);
556         tegra_dsi_writel(dsi, val, DSI_TIMEOUT_0);
557
558         if (dsi->info.panel_reset_timeout_msec)
559                 timeout = (dsi->info.panel_reset_timeout_msec * 1000*1000)
560                                         / dsi->current_bit_clk_ns;
561         else
562                 timeout = DSI_PR_TO_VALUE;
563
564         val = DSI_TIMEOUT_1_PR_TO(timeout) |
565                 DSI_TIMEOUT_1_TA_TO(DSI_TA_TO_VALUE);
566         tegra_dsi_writel(dsi, val, DSI_TIMEOUT_1);
567
568         val = DSI_TO_TALLY_P_RESET_STATUS(IN_RESET) |
569                 DSI_TO_TALLY_TA_TALLY(DSI_TA_TALLY_VALUE)|
570                 DSI_TO_TALLY_LRXH_TALLY(DSI_LRXH_TALLY_VALUE)|
571                 DSI_TO_TALLY_HTX_TALLY(DSI_HTX_TALLY_VALUE);
572         tegra_dsi_writel(dsi, val, DSI_TO_TALLY);
573 }
574
575 static void tegra_dsi_setup_video_mode_pkt_length(struct tegra_dc *dc,
576                                                 struct tegra_dc_dsi_data *dsi)
577 {
578         u32 val;
579         u32 hact_pkt_len;
580         u32 hsa_pkt_len;
581         u32 hbp_pkt_len;
582         u32 hfp_pkt_len;
583
584         hact_pkt_len = dc->mode.h_active * dsi->pixel_scaler_mul /
585                                                         dsi->pixel_scaler_div;
586         hsa_pkt_len = dc->mode.h_sync_width * dsi->pixel_scaler_mul /
587                                                         dsi->pixel_scaler_div;
588         hbp_pkt_len = dc->mode.h_back_porch * dsi->pixel_scaler_mul /
589                                                         dsi->pixel_scaler_div;
590         hfp_pkt_len = dc->mode.h_front_porch * dsi->pixel_scaler_mul /
591                                                         dsi->pixel_scaler_div;
592
593         if (dsi->info.video_burst_mode !=
594                                 TEGRA_DSI_VIDEO_NONE_BURST_MODE_WITH_SYNC_END)
595                 hbp_pkt_len += hsa_pkt_len;
596
597         hsa_pkt_len -= DSI_HSYNC_BLNK_PKT_OVERHEAD;
598         hbp_pkt_len -= DSI_HBACK_PORCH_PKT_OVERHEAD;
599         hfp_pkt_len -= DSI_HFRONT_PORCH_PKT_OVERHEAD;
600
601         val = DSI_PKT_LEN_0_1_LENGTH_0(0) | DSI_PKT_LEN_0_1_LENGTH_1(hsa_pkt_len);
602         tegra_dsi_writel(dsi, val, DSI_PKT_LEN_0_1);
603
604         val = DSI_PKT_LEN_2_3_LENGTH_2(hbp_pkt_len) |
605                         DSI_PKT_LEN_2_3_LENGTH_3(hact_pkt_len);
606         tegra_dsi_writel(dsi, val, DSI_PKT_LEN_2_3);
607
608         val = DSI_PKT_LEN_4_5_LENGTH_4(hfp_pkt_len) | DSI_PKT_LEN_4_5_LENGTH_5(0);
609         tegra_dsi_writel(dsi, val, DSI_PKT_LEN_4_5);
610
611         val = DSI_PKT_LEN_6_7_LENGTH_6(0) | DSI_PKT_LEN_6_7_LENGTH_7(0);
612         tegra_dsi_writel(dsi, val, DSI_PKT_LEN_6_7);
613 }
614
615 static void tegra_dsi_setup_cmd_mode_pkt_length(struct tegra_dc *dc,
616                                                 struct tegra_dc_dsi_data *dsi)
617 {
618         unsigned long   val;
619         unsigned long   act_bytes;
620
621         act_bytes = dc->mode.h_active * dsi->pixel_scaler_mul /
622                         dsi->pixel_scaler_div + 1;
623
624         val = DSI_PKT_LEN_0_1_LENGTH_0(0) | DSI_PKT_LEN_0_1_LENGTH_1(0);
625         tegra_dsi_writel(dsi, val, DSI_PKT_LEN_0_1);
626
627         val = DSI_PKT_LEN_2_3_LENGTH_2(0) | DSI_PKT_LEN_2_3_LENGTH_3(act_bytes);
628         tegra_dsi_writel(dsi, val, DSI_PKT_LEN_2_3);
629
630         val = DSI_PKT_LEN_4_5_LENGTH_4(0) | DSI_PKT_LEN_4_5_LENGTH_5(act_bytes);
631         tegra_dsi_writel(dsi, val, DSI_PKT_LEN_4_5);
632
633         val = DSI_PKT_LEN_6_7_LENGTH_6(0) | DSI_PKT_LEN_6_7_LENGTH_7(0x0f0f);
634         tegra_dsi_writel(dsi, val, DSI_PKT_LEN_6_7);
635 }
636
637 static void tegra_dsi_set_pkt_length(struct tegra_dc *dc,
638                                                 struct tegra_dc_dsi_data *dsi)
639 {
640         if (dsi->driven_mode == TEGRA_DSI_DRIVEN_BY_HOST)
641                 return;
642
643         if (dsi->info.video_data_type == TEGRA_DSI_VIDEO_TYPE_VIDEO_MODE)
644                 tegra_dsi_setup_video_mode_pkt_length(dc, dsi);
645         else
646                 tegra_dsi_setup_cmd_mode_pkt_length(dc, dsi);
647 }
648
649 static void tegra_dsi_set_pkt_seq(struct tegra_dc *dc,
650                                                 struct tegra_dc_dsi_data *dsi)
651 {
652         const u32 *pkt_seq;
653         u32 rgb_info;
654         u32 pkt_seq_3_5_rgb_lo;
655         u32 pkt_seq_3_5_rgb_hi;
656         u32     val;
657         u32 reg;
658         u8  i;
659
660         if (dsi->driven_mode == TEGRA_DSI_DRIVEN_BY_HOST)
661                 return;
662
663         switch(dsi->info.pixel_format) {
664         case TEGRA_DSI_PIXEL_FORMAT_16BIT_P:
665                 rgb_info = CMD_RGB_16BPP;
666                 break;
667         case TEGRA_DSI_PIXEL_FORMAT_18BIT_P:
668                 rgb_info = CMD_RGB_18BPP;
669                 break;
670         case TEGRA_DSI_PIXEL_FORMAT_18BIT_NP:
671                 rgb_info = CMD_RGB_18BPPNP;
672                 break;
673         case TEGRA_DSI_PIXEL_FORMAT_24BIT_P:
674         default:
675                 rgb_info = CMD_RGB_24BPP;
676                 break;
677         }
678
679         pkt_seq_3_5_rgb_lo = 0;
680         pkt_seq_3_5_rgb_hi = 0;
681         if (dsi->info.video_data_type == TEGRA_DSI_VIDEO_TYPE_COMMAND_MODE)
682                 pkt_seq = dsi_pkt_seq_cmd_mode;
683         else {
684                 switch (dsi->info.video_burst_mode) {
685                 case TEGRA_DSI_VIDEO_BURST_MODE_LOWEST_SPEED:
686                 case TEGRA_DSI_VIDEO_BURST_MODE_LOW_SPEED:
687                 case TEGRA_DSI_VIDEO_BURST_MODE_MEDIUM_SPEED:
688                 case TEGRA_DSI_VIDEO_BURST_MODE_FAST_SPEED:
689                 case TEGRA_DSI_VIDEO_BURST_MODE_FASTEST_SPEED:
690                 case TEGRA_DSI_VIDEO_BURST_MODE_MANUAL:
691                         pkt_seq_3_5_rgb_lo = DSI_PKT_SEQ_3_LO_PKT_32_ID(rgb_info);
692                         if(!dsi->info.no_pkt_seq_eot)
693                                 pkt_seq = dsi_pkt_seq_video_burst;
694                         else
695                                 pkt_seq = dsi_pkt_seq_video_burst_no_eot;
696                         break;
697                 case TEGRA_DSI_VIDEO_NONE_BURST_MODE_WITH_SYNC_END:
698                         pkt_seq_3_5_rgb_hi = DSI_PKT_SEQ_3_HI_PKT_34_ID(rgb_info);
699                         pkt_seq = dsi_pkt_seq_video_non_burst_syne;
700                         break;
701                 case TEGRA_DSI_VIDEO_NONE_BURST_MODE:
702                 default:
703                         pkt_seq_3_5_rgb_lo = DSI_PKT_SEQ_3_LO_PKT_32_ID(rgb_info);
704                         pkt_seq = dsi_pkt_seq_video_non_burst;
705                         break;
706                 }
707         }
708
709         for (i = 0; i < NUMOF_PKT_SEQ; i++) {
710                 val = pkt_seq[i];
711                 reg = dsi_pkt_seq_reg[i];
712                 if ((reg == DSI_PKT_SEQ_3_LO) || (reg == DSI_PKT_SEQ_5_LO))
713                         val |= pkt_seq_3_5_rgb_lo;
714                 if ((reg == DSI_PKT_SEQ_3_HI) || (reg == DSI_PKT_SEQ_5_HI))
715                         val |= pkt_seq_3_5_rgb_hi;
716                 tegra_dsi_writel(dsi, val, reg);
717         }
718 }
719
720 static void tegra_dsi_stop_dc_stream(struct tegra_dc *dc,
721                                                 struct tegra_dc_dsi_data *dsi)
722 {
723         tegra_dc_writel(dc, 0, DC_DISP_DISP_WIN_OPTIONS);
724         tegra_dc_writel(dc, GENERAL_ACT_REQ << 8, DC_CMD_STATE_CONTROL);
725         tegra_dc_writel(dc, GENERAL_ACT_REQ, DC_CMD_STATE_CONTROL);
726
727         dsi->status.dc_stream = DSI_DC_STREAM_DISABLE;
728 }
729
730 void tegra_dsi_stop_dc_stream_at_frame_end(struct tegra_dc *dc, struct tegra_dc_dsi_data *dsi)
731 {
732         int val;
733         long timeout;
734
735         /* stop dc */
736         tegra_dsi_stop_dc_stream(dc, dsi);
737
738         /* enable vblank interrupt */
739         val = tegra_dc_readl(dc, DC_CMD_INT_ENABLE);
740         val |= V_BLANK_INT;
741         tegra_dc_writel(dc, val, DC_CMD_INT_ENABLE);
742
743         val = tegra_dc_readl(dc, DC_CMD_INT_MASK);
744         val |= V_BLANK_INT;
745         tegra_dc_writel(dc, val, DC_CMD_INT_MASK);
746
747         /* wait for vblank completion */
748         timeout = wait_for_completion_interruptible_timeout(
749                 &dc->vblank_complete, DSI_STOP_DC_DURATION_MSEC);
750
751         /* disable vblank interrupt */
752         val = tegra_dc_readl(dc, DC_CMD_INT_ENABLE);
753         val &= ~V_BLANK_INT;
754         tegra_dc_writel(dc, val, DC_CMD_INT_ENABLE);
755
756         if(timeout == 0)
757                 printk("Warning: dc dosen't stop at the end of the frame.\n");
758 }
759
760 static void tegra_dsi_start_dc_stream(struct tegra_dc *dc,
761                                                 struct tegra_dc_dsi_data *dsi)
762 {
763         u32 val;
764
765         tegra_dc_writel(dc, DSI_ENABLE, DC_DISP_DISP_WIN_OPTIONS);
766
767         /* TODO: clean up */
768         val = PIN_INPUT_LSPI_INPUT_EN;
769         tegra_dc_writel(dc, val, DC_COM_PIN_INPUT_ENABLE3);
770
771         val = PIN_OUTPUT_LSPI_OUTPUT_DIS;
772         tegra_dc_writel(dc, val, DC_COM_PIN_OUTPUT_ENABLE3);
773
774         tegra_dc_writel(dc, PW0_ENABLE | PW1_ENABLE | PW2_ENABLE | PW3_ENABLE |
775                         PW4_ENABLE | PM0_ENABLE | PM1_ENABLE,
776                         DC_CMD_DISPLAY_POWER_CONTROL);
777
778         val = MSF_POLARITY_HIGH | MSF_ENABLE | MSF_LSPI;
779         tegra_dc_writel(dc, val, DC_CMD_DISPLAY_COMMAND_OPTION0);
780
781
782         /* TODO: using continuous video mode for now */
783         /* if (dsi->info.panel_has_frame_buffer) {*/
784         if (0) {
785                 tegra_dc_writel(dc, DISP_CTRL_MODE_NC_DISPLAY, DC_CMD_DISPLAY_COMMAND);
786                 tegra_dc_writel(dc, GENERAL_UPDATE, DC_CMD_STATE_CONTROL);
787                 val = GENERAL_ACT_REQ | NC_HOST_TRIG;
788                 tegra_dc_writel(dc, val, DC_CMD_STATE_CONTROL);
789         } else {
790                 tegra_dc_writel(dc, DISP_CTRL_MODE_C_DISPLAY, DC_CMD_DISPLAY_COMMAND);
791                 tegra_dc_writel(dc, GENERAL_ACT_REQ << 8, DC_CMD_STATE_CONTROL);
792                 tegra_dc_writel(dc, GENERAL_ACT_REQ, DC_CMD_STATE_CONTROL);
793         }
794
795         dsi->status.dc_stream = DSI_DC_STREAM_ENABLE;
796 }
797
798 static void tegra_dsi_set_dc_clk(struct tegra_dc *dc,
799                                                 struct tegra_dc_dsi_data *dsi)
800 {
801         u32 shift_clk_div;
802         u32 val;
803
804         if (dsi->info.video_burst_mode == TEGRA_DSI_VIDEO_NONE_BURST_MODE ||
805                 dsi->info.video_burst_mode ==
806                                 TEGRA_DSI_VIDEO_NONE_BURST_MODE_WITH_SYNC_END)
807                 shift_clk_div = NUMOF_BIT_PER_BYTE * dsi->pixel_scaler_mul /
808                         (dsi->pixel_scaler_div * dsi->info.n_data_lanes) - 2;
809         else
810                 shift_clk_div = (dsi->current_dsi_clk_khz * 2 +
811                                                 dsi->default_hs_clk_khz - 1) /
812                                                 (dsi->default_hs_clk_khz) - 2;
813
814 #ifdef CONFIG_TEGRA_FPGA_PLATFORM
815         shift_clk_div = 1;
816 #endif
817
818         /* TODO: find out if PCD3 option is required */
819         val = PIXEL_CLK_DIVIDER_PCD1 | SHIFT_CLK_DIVIDER(shift_clk_div);
820         tegra_dc_writel(dc, val, DC_DISP_DISP_CLOCK_CONTROL);
821
822         clk_enable(dsi->dc_clk);
823 }
824
825 static void tegra_dsi_set_dsi_clk(struct tegra_dc *dc,
826                                         struct tegra_dc_dsi_data *dsi, u32 clk)
827 {
828         u32 rm;
829
830         rm = clk % 1000;
831         if (rm != 0)
832                 clk -= rm;
833
834         clk *= 2;       /* Value for PLLD routine is required to be twice as */
835                         /* the desired clock rate */
836
837         dc->mode.pclk = clk*1000;
838         tegra_dc_setup_clk(dc, dsi->dsi_clk);
839         clk_enable(dsi->dsi_clk);
840         tegra_periph_reset_deassert(dsi->dsi_clk);
841
842         dsi->current_dsi_clk_khz = clk_get_rate(dsi->dsi_clk) / 1000;
843
844         dsi->current_bit_clk_ns =  1000*1000 / (dsi->current_dsi_clk_khz * 2);
845 }
846
847 static void tegra_dsi_hs_clk_out_enable(struct tegra_dc_dsi_data *dsi)
848 {
849         u32 val;
850
851         val = tegra_dsi_readl(dsi, DSI_CONTROL);
852         val &= ~DSI_CONTROL_HS_CLK_CTRL(1);
853
854         if (dsi->info.video_clock_mode == TEGRA_DSI_VIDEO_CLOCK_CONTINUOUS) {
855                 val |= DSI_CONTROL_HS_CLK_CTRL(CONTINUOUS);
856                 dsi->status.clk_mode = DSI_PHYCLK_CONTINUOUS;
857         } else {
858                 val |= DSI_CONTROL_HS_CLK_CTRL(TX_ONLY);
859                 dsi->status.clk_mode = DSI_PHYCLK_TX_ONLY;
860         }
861         tegra_dsi_writel(dsi, val, DSI_CONTROL);
862
863         val = tegra_dsi_readl(dsi, DSI_HOST_DSI_CONTROL);
864         val &= ~DSI_HOST_DSI_CONTROL_HIGH_SPEED_TRANS(1);
865         val |= DSI_HOST_DSI_CONTROL_HIGH_SPEED_TRANS(TEGRA_DSI_HIGH);
866         tegra_dsi_writel(dsi, val, DSI_HOST_DSI_CONTROL);
867
868         dsi->status.clk_out = DSI_PHYCLK_OUT_EN;
869 }
870
871 static void tegra_dsi_hs_clk_out_enable_in_lp(struct tegra_dc_dsi_data *dsi)
872 {
873         u32 val;
874         tegra_dsi_hs_clk_out_enable(dsi);
875
876         val = tegra_dsi_readl(dsi, DSI_HOST_DSI_CONTROL);
877         val &= ~DSI_HOST_DSI_CONTROL_HIGH_SPEED_TRANS(1);
878         val |= DSI_HOST_DSI_CONTROL_HIGH_SPEED_TRANS(TEGRA_DSI_LOW);
879         tegra_dsi_writel(dsi, val, DSI_HOST_DSI_CONTROL);
880 }
881
882 static void tegra_dsi_hs_clk_out_disable(struct tegra_dc *dc,
883                                                 struct tegra_dc_dsi_data *dsi)
884 {
885         u32 val;
886
887         if (dsi->status.dc_stream == DSI_DC_STREAM_ENABLE)
888                 tegra_dsi_stop_dc_stream(dc, dsi);
889
890         val = tegra_dsi_readl(dsi, DSI_CONTROL);
891         val &= ~DSI_CONTROL_HS_CLK_CTRL(1);
892         val |= DSI_CONTROL_HS_CLK_CTRL(TX_ONLY);
893         tegra_dsi_writel(dsi, val, DSI_CONTROL);
894
895         /* TODO: issue a cmd */
896
897         val = tegra_dsi_readl(dsi, DSI_HOST_DSI_CONTROL);
898         val &= ~DSI_HOST_DSI_CONTROL_HIGH_SPEED_TRANS(1);
899         val |= DSI_HOST_DSI_CONTROL_HIGH_SPEED_TRANS(TEGRA_DSI_LOW);
900         tegra_dsi_writel(dsi, val, DSI_HOST_DSI_CONTROL);
901
902         dsi->status.clk_mode = DSI_PHYCLK_NOT_INIT;
903         dsi->status.clk_out = DSI_PHYCLK_OUT_DIS;
904 }
905
906 static void tegra_dsi_set_control_reg_lp(struct tegra_dc_dsi_data *dsi)
907 {
908         u32 dsi_control;
909         u32 host_dsi_control;
910         u32 max_threshold;
911
912         dsi_control = dsi->dsi_control_val | DSI_CTRL_HOST_DRIVEN;
913         host_dsi_control = HOST_DSI_CTRL_COMMON |
914                         HOST_DSI_CTRL_HOST_DRIVEN |
915                         DSI_HOST_DSI_CONTROL_HIGH_SPEED_TRANS(TEGRA_DSI_LOW);
916         max_threshold = DSI_MAX_THRESHOLD_MAX_THRESHOLD(DSI_HOST_FIFO_DEPTH);
917
918         tegra_dsi_writel(dsi, max_threshold, DSI_MAX_THRESHOLD);
919         tegra_dsi_writel(dsi, dsi_control, DSI_CONTROL);
920         tegra_dsi_writel(dsi, host_dsi_control, DSI_HOST_DSI_CONTROL);
921
922         dsi->status.driven = DSI_DRIVEN_MODE_HOST;
923         dsi->status.clk_burst = DSI_CLK_BURST_NOT_INIT;
924         dsi->status.vtype = DSI_VIDEO_TYPE_NOT_INIT;
925 }
926
927 static void tegra_dsi_set_control_reg_hs(struct tegra_dc_dsi_data *dsi)
928 {
929         u32 dsi_control;
930         u32 host_dsi_control;
931         u32 max_threshold;
932         u32 dcs_cmd;
933
934         dsi_control = dsi->dsi_control_val;
935         host_dsi_control = HOST_DSI_CTRL_COMMON;
936         max_threshold = 0;
937         dcs_cmd = 0;
938
939         if (dsi->driven_mode == TEGRA_DSI_DRIVEN_BY_HOST) {
940                 dsi_control |= DSI_CTRL_HOST_DRIVEN;
941                 host_dsi_control |= HOST_DSI_CTRL_HOST_DRIVEN;
942                 max_threshold = DSI_MAX_THRESHOLD_MAX_THRESHOLD(DSI_HOST_FIFO_DEPTH);
943                 dsi->status.driven = DSI_DRIVEN_MODE_HOST;
944         } else {
945                 dsi_control |= DSI_CTRL_DC_DRIVEN;
946                 host_dsi_control |= HOST_DSI_CTRL_DC_DRIVEN;
947                 max_threshold = DSI_MAX_THRESHOLD_MAX_THRESHOLD(DSI_VIDEO_FIFO_DEPTH);
948                 dsi->status.driven = DSI_DRIVEN_MODE_DC;
949         }
950
951         if (dsi->info.video_data_type == TEGRA_DSI_VIDEO_TYPE_COMMAND_MODE) {
952                 dsi_control |= DSI_CTRL_CMD_MODE;
953                 host_dsi_control |= HOST_DSI_CTRL_CMD_MODE;
954                 dcs_cmd = DSI_DCS_CMDS_LT5_DCS_CMD(DSI_WRITE_MEMORY_START)|
955                                 DSI_DCS_CMDS_LT3_DCS_CMD(DSI_WRITE_MEMORY_CONTINUE);
956                 dsi->status.vtype = DSI_VIDEO_TYPE_CMD_MODE;
957
958         } else {
959                 dsi_control |= DSI_CTRL_VIDEO_MODE;
960                 host_dsi_control |= HOST_DSI_CTRL_VIDEO_MODE;
961                 dsi->status.vtype = DSI_VIDEO_TYPE_VIDEO_MODE;
962         }
963
964         tegra_dsi_writel(dsi, max_threshold, DSI_MAX_THRESHOLD);
965         tegra_dsi_writel(dsi, dcs_cmd, DSI_DCS_CMDS);
966         tegra_dsi_writel(dsi, dsi_control, DSI_CONTROL);
967         tegra_dsi_writel(dsi, host_dsi_control, DSI_HOST_DSI_CONTROL);
968 }
969
970 static int tegra_dsi_init_hw(struct tegra_dc *dc,
971                                                 struct tegra_dc_dsi_data *dsi)
972 {
973         u32 val;
974         u32 i;
975         int err;
976         tegra_dsi_set_dsi_clk(dc, dsi, dsi->target_lp_clk_khz);
977         if (dsi->info.dsi_instance) {
978                 /* TODO:Set the misc register*/
979         }
980
981         /* TODO: only need to change the timing for bta */
982         tegra_dsi_set_phy_timing(dsi);
983
984         err = gpio_request(TEGRA_GPIO_PJ1, "DSI TE");
985         if (err < 0)
986                 goto fail;
987
988         err = gpio_direction_input(TEGRA_GPIO_PJ1);
989         if (err < 0) {
990                 gpio_free(TEGRA_GPIO_PJ1);
991                 goto fail;
992         }
993         tegra_gpio_enable(TEGRA_GPIO_PJ1);
994
995         if (dsi->status.dc_stream == DSI_DC_STREAM_ENABLE)
996                 tegra_dsi_stop_dc_stream(dc, dsi);
997
998         /* Initializing DSI registers */
999         for (i = 0; i < ARRAY_SIZE(init_reg); i++) {
1000                 tegra_dsi_writel(dsi, 0, init_reg[i]);
1001         }
1002         tegra_dsi_writel(dsi, dsi->dsi_control_val, DSI_CONTROL);
1003
1004         val = DSI_PAD_CONTROL_PAD_PDIO(0) |
1005                         DSI_PAD_CONTROL_PAD_PDIO_CLK(0) |
1006                         DSI_PAD_CONTROL_PAD_PULLDN_ENAB(TEGRA_DSI_DISABLE);
1007         tegra_dsi_writel(dsi, val, DSI_PAD_CONTROL);
1008
1009         val = DSI_POWER_CONTROL_LEG_DSI_ENABLE(TEGRA_DSI_ENABLE);
1010         tegra_dsi_writel(dsi, val, DSI_POWER_CONTROL);
1011
1012         while (tegra_dsi_readl(dsi, DSI_POWER_CONTROL) != val) {
1013                 tegra_dsi_writel(dsi, val, DSI_POWER_CONTROL);
1014         }
1015
1016         dsi->status.init = DSI_MODULE_INIT;
1017         dsi->status.lphs = DSI_LPHS_NOT_INIT;
1018         dsi->status.vtype = DSI_VIDEO_TYPE_NOT_INIT;
1019         dsi->status.driven = DSI_DRIVEN_MODE_NOT_INIT;
1020         dsi->status.clk_out = DSI_PHYCLK_OUT_DIS;
1021         dsi->status.clk_mode = DSI_PHYCLK_NOT_INIT;
1022         dsi->status.clk_burst = DSI_CLK_BURST_NOT_INIT;
1023         dsi->status.dc_stream = DSI_DC_STREAM_DISABLE;
1024 fail:
1025         return err;
1026 }
1027
1028 static int tegra_dsi_set_to_lp_mode(struct tegra_dc *dc,
1029                                                 struct tegra_dc_dsi_data *dsi)
1030 {
1031         int     err;
1032
1033         if (dsi->status.init != DSI_MODULE_INIT) {
1034                 err = -EPERM;
1035                 goto fail;
1036         }
1037
1038         if (dsi->status.lphs == DSI_LPHS_IN_LP_MODE)
1039                 goto success;
1040
1041         if (dsi->status.dc_stream == DSI_DC_STREAM_ENABLE)
1042                 tegra_dsi_stop_dc_stream_at_frame_end(dc, dsi);
1043
1044         /* disable/enable hs clock according to enable_hs_clock_on_lp_cmd_mode */
1045         if ((dsi->status.clk_out == DSI_PHYCLK_OUT_EN) &&
1046                 (!dsi->info.enable_hs_clock_on_lp_cmd_mode))
1047                 tegra_dsi_hs_clk_out_disable(dc, dsi);
1048
1049         if (dsi->current_dsi_clk_khz != dsi->target_lp_clk_khz){
1050                 tegra_dsi_set_dsi_clk(dc, dsi, dsi->target_lp_clk_khz);
1051                 tegra_dsi_set_timeout(dsi);
1052         }
1053
1054         tegra_dsi_set_control_reg_lp(dsi);
1055
1056         if ((dsi->status.clk_out == DSI_PHYCLK_OUT_DIS) &&
1057                 (dsi->info.enable_hs_clock_on_lp_cmd_mode))
1058                 tegra_dsi_hs_clk_out_enable_in_lp(dsi);
1059
1060 success:
1061         dsi->status.lphs = DSI_LPHS_IN_LP_MODE;
1062         err = 0;
1063 fail:
1064         return err;
1065 }
1066
1067 static int tegra_dsi_set_to_hs_mode(struct tegra_dc *dc,
1068                                                 struct tegra_dc_dsi_data *dsi)
1069 {
1070         int err;
1071
1072         if (dsi->status.init != DSI_MODULE_INIT) {
1073                 err = -EPERM;
1074                 goto fail;
1075         }
1076
1077         if (dsi->status.dc_stream == DSI_DC_STREAM_ENABLE)
1078                 tegra_dsi_stop_dc_stream_at_frame_end(dc, dsi);
1079
1080         if ((dsi->status.clk_out == DSI_PHYCLK_OUT_EN) &&
1081                 (!dsi->info.enable_hs_clock_on_lp_cmd_mode))
1082                 tegra_dsi_hs_clk_out_disable(dc, dsi);
1083
1084         if (dsi->current_dsi_clk_khz != dsi->target_hs_clk_khz) {
1085                 tegra_dsi_set_dsi_clk(dc, dsi, dsi->target_hs_clk_khz);
1086                 tegra_dsi_set_timeout(dsi);
1087         }
1088
1089         tegra_dsi_set_phy_timing(dsi);
1090
1091         if (dsi->driven_mode == TEGRA_DSI_DRIVEN_BY_DC){
1092                 tegra_dsi_set_pkt_seq(dc, dsi);
1093                 tegra_dsi_set_pkt_length(dc, dsi);
1094                 tegra_dsi_set_sol_delay(dc, dsi);
1095                 tegra_dsi_set_dc_clk(dc, dsi);
1096         }
1097
1098         tegra_dsi_set_control_reg_hs(dsi);
1099
1100         if (dsi->status.clk_out == DSI_PHYCLK_OUT_DIS)
1101                 tegra_dsi_hs_clk_out_enable(dsi);
1102
1103         dsi->status.lphs = DSI_LPHS_IN_HS_MODE;
1104         err = 0;
1105 fail:
1106         return err;
1107 }
1108
1109 static bool tegra_dsi_is_controller_idle(struct tegra_dc_dsi_data *dsi)
1110 {
1111         u32 timeout = 0;
1112         bool retVal;
1113
1114         retVal = false;
1115         while (timeout <= DSI_MAX_COMMAND_DELAY_USEC) {
1116                 if (!tegra_dsi_readl(dsi, DSI_TRIGGER)) {
1117                         retVal = true;
1118                         break;
1119                 }
1120                 udelay(DSI_COMMAND_DELAY_STEPS_USEC);
1121                 timeout += DSI_COMMAND_DELAY_STEPS_USEC;
1122         }
1123
1124         return retVal;
1125 }
1126
1127 static bool tegra_dsi_host_trigger(struct tegra_dc_dsi_data *dsi)
1128 {
1129         bool status;
1130
1131         status = false;
1132         if (tegra_dsi_readl(dsi, DSI_TRIGGER))
1133                 goto fail;
1134
1135         tegra_dsi_writel(dsi, DSI_TRIGGER_HOST_TRIGGER(TEGRA_DSI_ENABLE),
1136                                                                 DSI_TRIGGER);
1137
1138 #if DSI_USE_SYNC_POINTS
1139         /* TODO: Implement sync point */
1140 #else
1141         status = tegra_dsi_is_controller_idle(dsi);
1142 #endif
1143
1144 fail:
1145         return status;
1146 }
1147
1148 static int _tegra_dsi_write_data(struct tegra_dc_dsi_data *dsi,
1149                                         u8* pdata, u8 data_id, u16 data_len)
1150 {
1151         u8 virtual_channel;
1152         u8 *pval;
1153         u32 val;
1154         int err;
1155
1156         err = 0;
1157
1158         virtual_channel = dsi->info.virtual_channel << DSI_VIR_CHANNEL_BIT_POSITION;
1159
1160         /* always use hw for ecc */
1161         val = (virtual_channel | data_id) << 0 |
1162                         data_len << 8;
1163         tegra_dsi_writel(dsi, val, DSI_WR_DATA);
1164
1165         /* if pdata != NULL, pkt type is long pkt */
1166         if (pdata != NULL) {
1167                 while (data_len) {
1168                         if (data_len >= 4) {
1169                                 val = ((u32*) pdata)[0];
1170                                 data_len -= 4;
1171                                 pdata += 4;
1172                         } else {
1173                                 val = 0;
1174                                 pval = (u8*) &val;
1175                                 do
1176                                         *pval++ = *pdata++;
1177                                 while(--data_len);
1178                         }
1179                         tegra_dsi_writel(dsi, val, DSI_WR_DATA);
1180                 }
1181         }
1182
1183         if (!tegra_dsi_host_trigger(dsi))
1184                 err = -EIO;
1185
1186         return err;
1187 }
1188
1189 static int tegra_dsi_write_data(struct tegra_dc *dc,
1190                                         struct tegra_dc_dsi_data *dsi,
1191                                         u8* pdata, u8 data_id, u16 data_len)
1192 {
1193         bool switch_back_to_hs_mode;
1194         bool switch_back_to_dc_mode;
1195         int err;
1196
1197         err = 0;
1198         switch_back_to_hs_mode = false;
1199         switch_back_to_dc_mode = false;
1200
1201         if ((dsi->status.init != DSI_MODULE_INIT) ||
1202                 (dsi->status.lphs == DSI_LPHS_NOT_INIT)) {
1203                 err = -EPERM;
1204                 goto fail;
1205         }
1206
1207         if (!tegra_dsi_is_controller_idle(dsi)) {
1208                 err = -EBUSY;
1209                 goto fail;
1210         }
1211
1212         err = 0;
1213
1214         if (dsi->status.lphs == DSI_LPHS_IN_HS_MODE) {
1215                 if (dsi->info.hs_cmd_mode_supported) {
1216                         if (dsi->status.driven == DSI_DRIVEN_MODE_DC) {
1217                                 dsi->driven_mode = TEGRA_DSI_DRIVEN_BY_HOST;
1218                                 tegra_dsi_set_to_hs_mode(dc, dsi);
1219                                 switch_back_to_dc_mode = true;
1220                         }
1221                 } else {
1222                         tegra_dsi_set_to_lp_mode(dc, dsi);
1223                         switch_back_to_hs_mode = true;
1224                 }
1225         }
1226
1227         err = _tegra_dsi_write_data(dsi, pdata, data_id, data_len);
1228
1229
1230         if (switch_back_to_dc_mode)
1231                 dsi->driven_mode = TEGRA_DSI_DRIVEN_BY_DC;
1232         if (switch_back_to_dc_mode || switch_back_to_hs_mode)
1233                 tegra_dsi_set_to_hs_mode(dc, dsi);
1234
1235 fail:
1236         return err;
1237 }
1238
1239 static int tegra_dsi_init_panel(struct tegra_dc *dc,
1240                                                 struct tegra_dc_dsi_data *dsi)
1241 {
1242         u32     i;
1243         int err;
1244
1245         err = 0;
1246         for (i = 0; i < dsi->info.n_init_cmd; i++) {
1247                 struct tegra_dsi_cmd *cur_cmd;
1248                 cur_cmd = &dsi->info.dsi_init_cmd[i];
1249
1250                 if (cur_cmd->cmd_type == TEGRA_DSI_DELAY_MS)
1251                         mdelay(cur_cmd->sp_len_dly.delay_ms);
1252                 else {
1253                         err = tegra_dsi_write_data(dc, dsi,
1254                                                 cur_cmd->pdata,
1255                                                 cur_cmd->data_id,
1256                                                 cur_cmd->sp_len_dly.data_len);
1257                         if (err < 0)
1258                                 break;
1259                 }
1260         }
1261         return err;
1262 }
1263
1264 static int tegra_dsi_bta(struct tegra_dc_dsi_data *dsi)
1265 {
1266         u32 val;
1267         u32 poll_time;
1268         int err;
1269
1270         poll_time = 0;
1271         err = 0;
1272
1273         val = tegra_dsi_readl(dsi, DSI_HOST_DSI_CONTROL);
1274         val |= DSI_HOST_DSI_CONTROL_IMM_BTA(TEGRA_DSI_ENABLE);
1275         tegra_dsi_writel(dsi, val, DSI_HOST_DSI_CONTROL);
1276
1277         while (poll_time <  DSI_STATUS_POLLING_DURATION_USEC) {
1278                 val = tegra_dsi_readl(dsi, DSI_HOST_DSI_CONTROL);
1279                 val &= DSI_HOST_DSI_CONTROL_IMM_BTA(TEGRA_DSI_ENABLE);
1280                 if (!val)
1281                         break;
1282                 udelay(DSI_STATUS_POLLING_DELAY_USEC);
1283                 poll_time += DSI_STATUS_POLLING_DELAY_USEC;
1284         }
1285         if (poll_time > DSI_STATUS_POLLING_DURATION_USEC)
1286                 err = -EBUSY;
1287
1288         return err;
1289 }
1290
1291 static void tegra_dsi_read_fifo(struct tegra_dc *dc,
1292                         struct tegra_dc_dsi_data *dsi,
1293                         u32 rd_fifo_cnt,
1294                         u8 *read_fifo)
1295 {
1296         u32 val;
1297         u32 i;
1298
1299         /* Read data from FIFO */
1300         for (i = 0; i < rd_fifo_cnt; i++) {
1301                 val = tegra_dsi_readl(dsi, DSI_RD_DATA);
1302                 printk(KERN_INFO "Read data[%d]: 0x%x\n", i, val);
1303                 memcpy(read_fifo, &val, 4);
1304                 read_fifo += 4;
1305         }
1306
1307         /* Make sure all the data is read from the FIFO */
1308         val = tegra_dsi_readl(dsi, DSI_STATUS);
1309         val &= DSI_STATUS_RD_FIFO_COUNT(0x1f);
1310         if (val)
1311                 dev_err(&dc->ndev->dev, "DSI FIFO_RD_CNT not zero"
1312                 " even after reading FIFO_RD_CNT words from read fifo\n");
1313 }
1314
1315 static int tegra_dsi_parse_read_response(struct tegra_dc *dc,
1316                                 u32 rd_fifo_cnt, u8 *read_fifo)
1317 {
1318         int err;
1319         u32 payload_size;
1320
1321         payload_size = 0;
1322         err = 0;
1323
1324         printk(KERN_INFO "escape sequence[0x%x]\n", read_fifo[0]);
1325         switch (read_fifo[4] & 0xff) {
1326         case GEN_LONG_RD_RES:
1327                 /* Fall through */
1328         case DCS_LONG_RD_RES:
1329                 payload_size = (read_fifo[5] |
1330                                 (read_fifo[6] << 8)) & 0xFFFF;
1331                 printk(KERN_INFO "Long read response Packet\n"
1332                                 "payload_size[0x%x]\n", payload_size);
1333                 break;
1334         case GEN_1_BYTE_SHORT_RD_RES:
1335                 /* Fall through */
1336         case DCS_1_BYTE_SHORT_RD_RES:
1337                 payload_size = 1;
1338                 printk(KERN_INFO "Short read response Packet\n"
1339                         "payload_size[0x%x]\n", payload_size);
1340                 break;
1341         case GEN_2_BYTE_SHORT_RD_RES:
1342                 /* Fall through */
1343         case DCS_2_BYTE_SHORT_RD_RES:
1344                 payload_size = 2;
1345                 printk(KERN_INFO "Short read response Packet\n"
1346                         "payload_size[0x%x]\n", payload_size);
1347                 break;
1348         case ACK_ERR_RES:
1349                 payload_size = 2;
1350                 printk(KERN_INFO "Acknowledge error report response\n"
1351                         "Packet payload_size[0x%x]\n", payload_size);
1352                 break;
1353         default:
1354                 /*reading from RD_FIFO_COUNT*/
1355                 printk(KERN_INFO "Invalid read response payload_size\n");
1356                 err = -EINVAL;
1357                 break;
1358         }
1359         return err;
1360 }
1361
1362 static int tegra_dsi_read_data(struct tegra_dc *dc,
1363                                 struct tegra_dc_dsi_data *dsi,
1364                                 u32 max_ret_payload_size,
1365                                 u32 panel_reg_addr, u8 *read_data)
1366 {
1367         u32 val;
1368         int err;
1369         u32 poll_time;
1370         u32 rd_fifo_cnt;
1371         bool switch_back_to_hs_mode;
1372         bool restart_dc_stream;
1373         bool switch_back_to_dc_mode;
1374
1375         err = 0;
1376         switch_back_to_hs_mode = false;
1377         restart_dc_stream = false;
1378         switch_back_to_dc_mode = false;
1379
1380         if ((dsi->status.init != DSI_MODULE_INIT) ||
1381                 (dsi->status.lphs == DSI_LPHS_NOT_INIT) ||
1382                 (dsi->status.driven == DSI_DRIVEN_MODE_NOT_INIT)) {
1383                 err = -EPERM;
1384                 goto fail;
1385         }
1386
1387         val = tegra_dsi_readl(dsi, DSI_STATUS);
1388         val &= DSI_STATUS_RD_FIFO_COUNT(0x1f);
1389         if (val) {
1390                 err = -EBUSY;
1391                 dev_err(&dc->ndev->dev, "DSI fifo count not zero\n");
1392                 goto fail;
1393         }
1394
1395         if (!tegra_dsi_is_controller_idle(dsi)) {
1396                 err = -EBUSY;
1397                 dev_err(&dc->ndev->dev, "DSI trigger bit is already set\n");
1398                 goto fail;
1399         }
1400
1401         if (dsi->status.lphs == DSI_LPHS_IN_HS_MODE) {
1402                 if (dsi->status.driven == DSI_DRIVEN_MODE_DC) {
1403                         if (dsi->status.dc_stream == DSI_DC_STREAM_ENABLE)
1404                                 restart_dc_stream = true;
1405                         dsi->driven_mode = TEGRA_DSI_DRIVEN_BY_HOST;
1406                         switch_back_to_dc_mode = true;
1407                         if (dsi->info.hs_cmd_mode_supported) {
1408                                 err = tegra_dsi_set_to_hs_mode(dc, dsi);
1409                                 if (err < 0) {
1410                                         dev_err(&dc->ndev->dev,
1411                                         "DSI failed to go to HS mode host driven\n");
1412                                         goto fail;
1413                                 }
1414                         }
1415                 }
1416                 if (!dsi->info.hs_cmd_mode_supported) {
1417                         err = tegra_dsi_set_to_lp_mode(dc, dsi);
1418                         if (err < 0) {
1419                                 dev_err(&dc->ndev->dev,
1420                                 "DSI failed to go to LP mode\n");
1421                                 goto fail;
1422                         }
1423                         switch_back_to_hs_mode = true;
1424                 }
1425         }
1426
1427         /* Set max return payload size in words */
1428         err = _tegra_dsi_write_data(dsi, NULL,
1429                 dsi_command_max_return_pkt_size,
1430                 max_ret_payload_size);
1431         if (err < 0) {
1432                 dev_err(&dc->ndev->dev,
1433                                 "DSI write failed\n");
1434                 goto fail;
1435         }
1436
1437         /* DCS to read given panel register */
1438         err = _tegra_dsi_write_data(dsi, NULL,
1439                 dsi_command_dcs_read_with_no_params,
1440                 panel_reg_addr);
1441         if (err < 0) {
1442                 dev_err(&dc->ndev->dev,
1443                                 "DSI write failed\n");
1444                 goto fail;
1445         }
1446
1447         err = tegra_dsi_bta(dsi);
1448         if (err < 0) {
1449                 dev_err(&dc->ndev->dev,
1450                         "DSI IMM BTA timeout\n");
1451                 goto fail;
1452         }
1453
1454         poll_time = 0;
1455         while (poll_time <  DSI_DELAY_FOR_READ_FIFO) {
1456                 mdelay(1);
1457                 val = tegra_dsi_readl(dsi, DSI_STATUS);
1458                 rd_fifo_cnt = val & DSI_STATUS_RD_FIFO_COUNT(0x1f);
1459                 if (rd_fifo_cnt << 2 > DSI_READ_FIFO_DEPTH)
1460                         dev_err(&dc->ndev->dev,
1461                         "DSI RD_FIFO_CNT is greater than RD_FIFO_DEPTH\n");
1462                         break;
1463                 poll_time++;
1464         }
1465
1466         if (rd_fifo_cnt == 0) {
1467                 dev_info(&dc->ndev->dev,
1468                         "DSI RD_FIFO_CNT is zero\n");
1469                 err = -EINVAL;
1470                 goto fail;
1471         }
1472
1473         if (val & DSI_STATUS_LB_UNDERFLOW(0x1) ||
1474                 val & DSI_STATUS_LB_OVERFLOW(0x1)) {
1475                 dev_err(&dc->ndev->dev,
1476                         "DSI overflow/underflow error\n");
1477                 err = -EINVAL;
1478                 goto fail;
1479         }
1480
1481         tegra_dsi_read_fifo(dc, dsi, rd_fifo_cnt, read_data);
1482
1483         err = tegra_dsi_parse_read_response(dc, rd_fifo_cnt, read_data);
1484 fail:
1485         if (switch_back_to_dc_mode)
1486                 dsi->driven_mode = TEGRA_DSI_DRIVEN_BY_DC;
1487         if (switch_back_to_dc_mode || switch_back_to_hs_mode)
1488                 tegra_dsi_set_to_hs_mode(dc, dsi);
1489         if (restart_dc_stream)
1490                 tegra_dsi_start_dc_stream(dc, dsi);
1491
1492         return err;
1493 }
1494
1495 static void tegra_dc_dsi_enable(struct tegra_dc *dc)
1496 {
1497         struct tegra_dc_dsi_data *dsi = tegra_dc_get_outdata(dc);
1498         int err;
1499
1500         tegra_dc_io_start(dc);
1501         mutex_lock(&dsi->lock);
1502
1503         err = tegra_dsi_init_hw(dc, dsi);
1504         if (err < 0) {
1505                 dev_err(&dc->ndev->dev, "dsi: not able to init dsi hardware\n");
1506                 return;
1507         }
1508
1509         err = tegra_dsi_set_to_lp_mode(dc, dsi);
1510         if (err < 0) {
1511                 dev_err(&dc->ndev->dev, "dsi: not able to set to lp mode\n");
1512                 return;
1513         }
1514
1515         err = tegra_dsi_init_panel(dc, dsi);
1516         if (err < 0) {
1517                 dev_err(&dc->ndev->dev, "dsi: error while sending dsi cmd\n");
1518                 return;
1519         }
1520
1521         err = tegra_dsi_set_to_hs_mode(dc, dsi);
1522         if (err < 0) {
1523                         dev_err(&dc->ndev->dev,
1524                                         "dsi: not able to set to hs mode\n");
1525                 return;
1526         }
1527
1528         if (dsi->status.driven == DSI_DRIVEN_MODE_DC) {
1529                 tegra_dsi_start_dc_stream(dc, dsi);
1530         }
1531
1532         mutex_unlock(&dsi->lock);
1533         tegra_dc_io_end(dc);
1534 }
1535
1536 static void _tegra_dc_dsi_init(struct tegra_dc *dc)
1537 {
1538         struct tegra_dc_dsi_data *dsi = tegra_dc_get_outdata(dc);
1539
1540         tegra_dsi_init_sw(dc, dsi);
1541         /* TODO: Configure the CSI pad configuration */
1542 }
1543
1544 static int tegra_dc_dsi_cp_init_cmd(struct tegra_dsi_cmd* src,
1545                                         struct tegra_dsi_cmd* dst, u16 n_cmd)
1546 {
1547         u16 i;
1548         u16 len;
1549
1550         memcpy(dst, src, sizeof(*dst) * n_cmd);
1551
1552         for (i = 0; i < n_cmd; i++)
1553                 if (src[i].pdata) {
1554                         len = sizeof(*src[i].pdata) * src[i].sp_len_dly.data_len;
1555                         dst[i].pdata = kzalloc(len, GFP_KERNEL);
1556                         if (!dst[i].pdata)
1557                                 goto free_cmd_pdata;
1558                         memcpy(dst[i].pdata, src[i].pdata, len);
1559                 }
1560
1561         return 0;
1562
1563 free_cmd_pdata:
1564         for (--i; i >=0; i--)
1565                 if (dst[i].pdata)
1566                         kfree(dst[i].pdata);
1567         return -ENOMEM;
1568 }
1569
1570 static int tegra_dc_dsi_cp_info(struct tegra_dc_dsi_data* dsi,
1571                                                 struct tegra_dsi_out* p_dsi)
1572 {
1573         struct tegra_dsi_cmd* pcmd;
1574         int err;
1575
1576         pcmd = kzalloc(sizeof(*pcmd) * p_dsi->n_init_cmd, GFP_KERNEL);
1577         if (!pcmd)
1578                 return -ENOMEM;
1579
1580         if (p_dsi->n_data_lanes > MAX_DSI_DATA_LANES) {
1581                 err = -EINVAL;
1582                 goto err_free_pcmd;
1583         }
1584
1585         memcpy(&dsi->info, p_dsi, sizeof(dsi->info));
1586
1587         err = tegra_dc_dsi_cp_init_cmd(p_dsi->dsi_init_cmd,
1588                                                 pcmd, p_dsi->n_init_cmd);
1589         if (err < 0)
1590                 goto err_free_pcmd;
1591
1592         dsi->info.dsi_init_cmd = pcmd;
1593
1594         if (!dsi->info.panel_reset_timeout_msec)
1595                 dsi->info.panel_reset_timeout_msec = DEFAULT_PANEL_RESET_TIMEOUT;
1596
1597         if (!dsi->info.panel_buffer_size_byte)
1598                 dsi->info.panel_buffer_size_byte = DEFAULT_PANEL_BUFFER_BYTE;
1599
1600         if (!dsi->info.max_panel_freq_khz)
1601                 dsi->info.max_panel_freq_khz = DEFAULT_MAX_DSI_PHY_CLK_KHZ;
1602
1603         if (!dsi->info.lp_cmd_mode_freq_khz)
1604                 dsi->info.lp_cmd_mode_freq_khz = DEFAULT_LP_CMD_MODE_CLK_KHZ;
1605
1606         /* host mode is for testing only*/
1607         dsi->driven_mode = TEGRA_DSI_DRIVEN_BY_DC;
1608
1609         return 0;
1610
1611 err_free_pcmd:
1612         kfree(pcmd);
1613         return err;
1614 }
1615
1616 static int tegra_dc_dsi_init(struct tegra_dc *dc)
1617 {
1618         struct tegra_dc_dsi_data *dsi;
1619         struct resource *res;
1620         struct resource *base_res;
1621         void __iomem *base;
1622         struct clk *dc_clk = NULL;
1623         struct clk *dsi_clk = NULL;
1624         struct tegra_dsi_out *dsi_pdata;
1625         int err;
1626
1627         err = 0;
1628
1629         dsi = kzalloc(sizeof(*dsi), GFP_KERNEL);
1630         if (!dsi)
1631                 return -ENOMEM;
1632
1633         res = nvhost_get_resource_byname(dc->ndev, IORESOURCE_MEM,
1634                                         "dsi_regs");
1635         if (!res) {
1636                 dev_err(&dc->ndev->dev, "dsi: no mem resource\n");
1637                 err = -ENOENT;
1638                 goto err_free_dsi;
1639         }
1640
1641         base_res = request_mem_region(res->start, resource_size(res),
1642                                 dc->ndev->name);
1643         if (!base_res) {
1644                 dev_err(&dc->ndev->dev, "dsi: request_mem_region failed\n");
1645                 err = -EBUSY;
1646                 goto err_free_dsi;
1647         }
1648
1649         base = ioremap(res->start, resource_size(res));
1650         if (!base) {
1651                 dev_err(&dc->ndev->dev, "dsi: registers can't be mapped\n");
1652                 err = -EBUSY;
1653                 goto err_release_regs;
1654         }
1655
1656         dsi_pdata = dc->pdata->default_out->dsi;
1657         if (!dsi_pdata) {
1658                 dev_err(&dc->ndev->dev, "dsi: dsi data not available\n");
1659                 goto err_release_regs;
1660         }
1661
1662         if (dsi_pdata->dsi_instance)
1663                 dsi_clk = clk_get(&dc->ndev->dev, "dsib");
1664         else
1665                 dsi_clk = clk_get(&dc->ndev->dev, "dsia");
1666
1667         if (IS_ERR_OR_NULL(dsi_clk)) {
1668                 dev_err(&dc->ndev->dev, "dsi: can't get clock\n");
1669                 err = -EBUSY;
1670                 goto err_release_regs;
1671         }
1672
1673         dc_clk = clk_get_sys(dev_name(&dc->ndev->dev), NULL);
1674         if (IS_ERR_OR_NULL(dc_clk)) {
1675                 dev_err(&dc->ndev->dev, "dsi: dc clock %s unavailable\n",
1676                         dev_name(&dc->ndev->dev));
1677                 err = -EBUSY;
1678                 goto err_clk_put;
1679         }
1680
1681         err = tegra_dc_dsi_cp_info(dsi, dsi_pdata);
1682         if (err < 0)
1683                 goto err_dsi_data;
1684
1685         mutex_init(&dsi->lock);
1686         dsi->dc = dc;
1687         dsi->base = base;
1688         dsi->base_res = base_res;
1689         dsi->dc_clk = dc_clk;
1690         dsi->dsi_clk = dsi_clk;
1691
1692         tegra_dc_set_outdata(dc, dsi);
1693         _tegra_dc_dsi_init(dc);
1694
1695         return 0;
1696
1697 err_dsi_data:
1698 err_clk_put:
1699         clk_put(dsi_clk);
1700 err_release_regs:
1701         release_resource(base_res);
1702 err_free_dsi:
1703         kfree(dsi);
1704
1705         return err;
1706 }
1707
1708 static void tegra_dc_dsi_destroy(struct tegra_dc *dc)
1709 {
1710         struct tegra_dc_dsi_data *dsi = tegra_dc_get_outdata(dc);
1711         u16 i;
1712         u32 val;
1713
1714         mutex_lock(&dsi->lock);
1715
1716         /* free up the pdata*/
1717         for(i = 0; i < dsi->info.n_init_cmd; i++){
1718                 if(dsi->info.dsi_init_cmd[i].pdata)
1719                         kfree(dsi->info.dsi_init_cmd[i].pdata);
1720         }
1721         kfree(dsi->info.dsi_init_cmd);
1722
1723         /* Disable dc stream*/
1724         if(dsi->status.dc_stream == DSI_DC_STREAM_ENABLE)
1725                 tegra_dsi_stop_dc_stream(dc, dsi);
1726
1727         /* Disable dsi phy clock*/
1728         if(dsi->status.clk_out == DSI_PHYCLK_OUT_EN)
1729                 tegra_dsi_hs_clk_out_disable(dc, dsi);
1730
1731         val = DSI_POWER_CONTROL_LEG_DSI_ENABLE(TEGRA_DSI_DISABLE);
1732         tegra_dsi_writel(dsi, val, DSI_POWER_CONTROL);
1733
1734         iounmap(dsi->base);
1735         release_resource(dsi->base_res);
1736
1737         clk_put(dsi->dc_clk);
1738         clk_put(dsi->dsi_clk);
1739
1740         mutex_unlock(&dsi->lock);
1741
1742         mutex_destroy(&dsi->lock);
1743         kfree(dsi);
1744 }
1745
1746 static void tegra_dc_dsi_disable(struct tegra_dc *dc)
1747 {
1748         struct tegra_dc_dsi_data *dsi = tegra_dc_get_outdata(dc);
1749
1750         mutex_lock(&dsi->lock);
1751
1752         if (dsi->status.dc_stream == DSI_DC_STREAM_ENABLE)
1753                 tegra_dsi_stop_dc_stream(dc, dsi);
1754
1755         if (dsi->status.clk_out == DSI_PHYCLK_OUT_EN)
1756                 tegra_dsi_hs_clk_out_disable(dc, dsi);
1757
1758         mutex_unlock(&dsi->lock);
1759
1760         dev_err(&dc->ndev->dev, "dsi: disable\n");
1761 }
1762
1763 struct tegra_dc_out_ops tegra_dc_dsi_ops = {
1764         .init = tegra_dc_dsi_init,
1765         .destroy = tegra_dc_dsi_destroy,
1766         .enable = tegra_dc_dsi_enable,
1767         .disable = tegra_dc_dsi_disable,
1768 };