video: tegra: use public APIs exposed by host1x driver
[linux-2.6.git] / drivers / video / tegra / dc / dsi.c
1 /*
2  * drivers/video/tegra/dc/dsi.c
3  *
4  * Copyright (c) 2011-2012, NVIDIA Corporation.
5  *
6  * This software is licensed under the terms of the GNU General Public
7  * License version 2, as published by the Free Software Foundation, and
8  * may be copied, distributed, and modified under those terms.
9  *
10  * This program is distributed in the hope that it will be useful,
11  * but WITHOUT ANY WARRANTY; without even the implied warranty of
12  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
13  * GNU General Public License for more details.
14  *
15  */
16
17 #include <linux/kernel.h>
18 #include <linux/clk.h>
19 #include <linux/delay.h>
20 #include <linux/err.h>
21 #include <linux/fb.h>
22 #include <linux/gpio.h>
23 #include <linux/interrupt.h>
24 #include <linux/slab.h>
25 #include <linux/spinlock.h>
26 #include <linux/workqueue.h>
27 #include <linux/debugfs.h>
28 #include <linux/seq_file.h>
29 #include <linux/nvhost.h>
30
31 #include <mach/clk.h>
32 #include <mach/dc.h>
33 #include <mach/fb.h>
34 #include <mach/csi.h>
35 #include <mach/iomap.h>
36 #include <linux/nvhost.h>
37
38 #include "dc_reg.h"
39 #include "dc_priv.h"
40 #include "dsi_regs.h"
41 #include "dsi.h"
42
43 #define APB_MISC_GP_MIPI_PAD_CTRL_0     (TEGRA_APB_MISC_BASE + 0x820)
44 #define DSIB_MODE_ENABLE                0x2
45
46 #define DSI_USE_SYNC_POINTS             1
47 #define S_TO_MS(x)                      (1000 * (x))
48
49 #define DSI_MODULE_NOT_INIT             0x0
50 #define DSI_MODULE_INIT                 0x1
51
52 #define DSI_LPHS_NOT_INIT               0x0
53 #define DSI_LPHS_IN_LP_MODE             0x1
54 #define DSI_LPHS_IN_HS_MODE             0x2
55
56 #define DSI_VIDEO_TYPE_NOT_INIT         0x0
57 #define DSI_VIDEO_TYPE_VIDEO_MODE       0x1
58 #define DSI_VIDEO_TYPE_CMD_MODE         0x2
59
60 #define DSI_DRIVEN_MODE_NOT_INIT        0x0
61 #define DSI_DRIVEN_MODE_DC              0x1
62 #define DSI_DRIVEN_MODE_HOST            0x2
63
64 #define DSI_PHYCLK_OUT_DIS              0x0
65 #define DSI_PHYCLK_OUT_EN               0x1
66
67 #define DSI_PHYCLK_NOT_INIT             0x0
68 #define DSI_PHYCLK_CONTINUOUS           0x1
69 #define DSI_PHYCLK_TX_ONLY              0x2
70
71 #define DSI_CLK_BURST_NOT_INIT          0x0
72 #define DSI_CLK_BURST_NONE_BURST        0x1
73 #define DSI_CLK_BURST_BURST_MODE        0x2
74
75 #define DSI_DC_STREAM_DISABLE           0x0
76 #define DSI_DC_STREAM_ENABLE            0x1
77
78 #define DSI_LP_OP_NOT_INIT              0x0
79 #define DSI_LP_OP_WRITE                 0x1
80 #define DSI_LP_OP_READ                  0x2
81
82 static bool enable_read_debug;
83 module_param(enable_read_debug, bool, 0644);
84 MODULE_PARM_DESC(enable_read_debug,
85                 "Enable to print read fifo and return packet type");
86
87 struct dsi_status {
88         unsigned init:2;
89
90         unsigned lphs:2;
91
92         unsigned vtype:2;
93         unsigned driven:2;
94
95         unsigned clk_out:2;
96         unsigned clk_mode:2;
97         unsigned clk_burst:2;
98
99         unsigned lp_op:2;
100
101         unsigned dc_stream:1;
102 };
103
104 /* source of video data */
105 enum {
106         TEGRA_DSI_DRIVEN_BY_DC,
107         TEGRA_DSI_DRIVEN_BY_HOST,
108 };
109
110 struct tegra_dc_dsi_data {
111         struct tegra_dc *dc;
112         void __iomem *base;
113         struct resource *base_res;
114
115         struct clk *dc_clk;
116         struct clk *dsi_clk;
117         struct clk *dsi_fixed_clk;
118         bool clk_ref;
119
120         struct mutex lock;
121
122         /* data from board info */
123         struct tegra_dsi_out info;
124
125         struct dsi_status status;
126
127         struct dsi_phy_timing_inclk phy_timing;
128
129         u8 driven_mode;
130         u8 controller_index;
131
132         u8 pixel_scaler_mul;
133         u8 pixel_scaler_div;
134
135         u32 default_shift_clk_div;
136         u32 default_pixel_clk_khz;
137         u32 default_hs_clk_khz;
138
139         u32 shift_clk_div;
140         u32 target_hs_clk_khz;
141         u32 target_lp_clk_khz;
142
143         u32 syncpt_id;
144         u32 syncpt_val;
145
146         u16 current_bit_clk_ns;
147         u32 current_dsi_clk_khz;
148
149         u32 dsi_control_val;
150
151         bool ulpm;
152         bool enabled;
153 };
154
155 const u32 dsi_pkt_seq_reg[NUMOF_PKT_SEQ] = {
156         DSI_PKT_SEQ_0_LO,
157         DSI_PKT_SEQ_0_HI,
158         DSI_PKT_SEQ_1_LO,
159         DSI_PKT_SEQ_1_HI,
160         DSI_PKT_SEQ_2_LO,
161         DSI_PKT_SEQ_2_HI,
162         DSI_PKT_SEQ_3_LO,
163         DSI_PKT_SEQ_3_HI,
164         DSI_PKT_SEQ_4_LO,
165         DSI_PKT_SEQ_4_HI,
166         DSI_PKT_SEQ_5_LO,
167         DSI_PKT_SEQ_5_HI,
168 };
169
170 const u32 dsi_pkt_seq_video_non_burst_syne[NUMOF_PKT_SEQ] = {
171         PKT_ID0(CMD_VS) | PKT_LEN0(0) | PKT_ID1(CMD_EOT) | PKT_LEN1(0) | PKT_LP,
172         0,
173         PKT_ID0(CMD_VE) | PKT_LEN0(0) | PKT_ID1(CMD_EOT) | PKT_LEN1(0) | PKT_LP,
174         0,
175         PKT_ID0(CMD_HS) | PKT_LEN0(0) | PKT_ID1(CMD_EOT) | PKT_LEN1(0) | PKT_LP,
176         0,
177         PKT_ID0(CMD_HS) | PKT_LEN0(0) | PKT_ID1(CMD_BLNK) | PKT_LEN1(1) |
178         PKT_ID2(CMD_HE) | PKT_LEN2(0),
179         PKT_ID3(CMD_BLNK) | PKT_LEN3(2) | PKT_ID4(CMD_RGB) | PKT_LEN4(3) |
180         PKT_ID5(CMD_BLNK) | PKT_LEN5(4),
181         PKT_ID0(CMD_HS) | PKT_LEN0(0) | PKT_ID1(CMD_EOT) | PKT_LEN1(0) | PKT_LP,
182         0,
183         PKT_ID0(CMD_HS) | PKT_LEN0(0) | PKT_ID1(CMD_BLNK) | PKT_LEN1(1) |
184         PKT_ID2(CMD_HE) | PKT_LEN2(0),
185         PKT_ID3(CMD_BLNK) | PKT_LEN3(2) | PKT_ID4(CMD_RGB) | PKT_LEN4(3) |
186         PKT_ID5(CMD_BLNK) | PKT_LEN5(4),
187 };
188
189 const u32 dsi_pkt_seq_video_non_burst[NUMOF_PKT_SEQ] = {
190         PKT_ID0(CMD_VS) | PKT_LEN0(0) | PKT_ID1(CMD_EOT) | PKT_LEN1(0) | PKT_LP,
191         0,
192         PKT_ID0(CMD_HS) | PKT_LEN0(0) | PKT_ID1(CMD_EOT) | PKT_LEN1(0) | PKT_LP,
193         0,
194         PKT_ID0(CMD_HS) | PKT_LEN0(0) | PKT_ID1(CMD_EOT) | PKT_LEN1(0) | PKT_LP,
195         0,
196         PKT_ID0(CMD_HS) | PKT_LEN0(0) | PKT_ID1(CMD_BLNK) | PKT_LEN1(2) |
197         PKT_ID2(CMD_RGB) | PKT_LEN2(3),
198         PKT_ID3(CMD_BLNK) | PKT_LEN3(4),
199         PKT_ID0(CMD_HS) | PKT_LEN0(0) | PKT_ID1(CMD_EOT) | PKT_LEN1(0) | PKT_LP,
200         0,
201         PKT_ID0(CMD_HS) | PKT_LEN0(0) | PKT_ID1(CMD_BLNK) | PKT_LEN1(2) |
202         PKT_ID2(CMD_RGB) | PKT_LEN2(3),
203         PKT_ID3(CMD_BLNK) | PKT_LEN3(4),
204 };
205
206 static const u32 dsi_pkt_seq_video_burst[NUMOF_PKT_SEQ] = {
207         PKT_ID0(CMD_VS) | PKT_LEN0(0) | PKT_ID1(CMD_EOT) | PKT_LEN1(7) | PKT_LP,
208         0,
209         PKT_ID0(CMD_HS) | PKT_LEN0(0) | PKT_ID1(CMD_EOT) | PKT_LEN1(7) | PKT_LP,
210         0,
211         PKT_ID0(CMD_HS) | PKT_LEN0(0) | PKT_ID1(CMD_EOT) | PKT_LEN1(7) | PKT_LP,
212         0,
213         PKT_ID0(CMD_HS) | PKT_LEN0(0) | PKT_ID1(CMD_BLNK) | PKT_LEN1(2)|
214         PKT_ID2(CMD_RGB) | PKT_LEN2(3) | PKT_LP,
215         PKT_ID0(CMD_EOT) | PKT_LEN0(7),
216         PKT_ID0(CMD_HS) | PKT_LEN0(0) | PKT_ID1(CMD_EOT) | PKT_LEN1(7) | PKT_LP,
217         0,
218         PKT_ID0(CMD_HS) | PKT_LEN0(0) | PKT_ID1(CMD_BLNK) | PKT_LEN1(2)|
219         PKT_ID2(CMD_RGB) | PKT_LEN2(3) | PKT_LP,
220         PKT_ID0(CMD_EOT) | PKT_LEN0(7),
221 };
222
223 static const u32 dsi_pkt_seq_video_burst_no_eot[NUMOF_PKT_SEQ] = {
224         PKT_ID0(CMD_VS) | PKT_LEN0(0) | PKT_ID1(CMD_EOT) | PKT_LEN1(0) | PKT_LP,
225         0,
226         PKT_ID0(CMD_HS) | PKT_LEN0(0) | PKT_ID1(CMD_EOT) | PKT_LEN1(0) | PKT_LP,
227         0,
228         PKT_ID0(CMD_HS) | PKT_LEN0(0) | PKT_ID1(CMD_EOT) | PKT_LEN1(0) | PKT_LP,
229         0,
230         PKT_ID0(CMD_HS) | PKT_LEN0(0) | PKT_ID1(CMD_BLNK) | PKT_LEN1(2)|
231         PKT_ID2(CMD_RGB) | PKT_LEN2(3) | PKT_LP,
232         PKT_ID0(CMD_EOT) | PKT_LEN0(0),
233         PKT_ID0(CMD_HS) | PKT_LEN0(0) | PKT_ID1(CMD_EOT) | PKT_LEN1(0) | PKT_LP,
234         0,
235         PKT_ID0(CMD_HS) | PKT_LEN0(0) | PKT_ID1(CMD_BLNK) | PKT_LEN1(2)|
236         PKT_ID2(CMD_RGB) | PKT_LEN2(3) | PKT_LP,
237         PKT_ID0(CMD_EOT) | PKT_LEN0(0),
238 };
239
240 /* TODO: verify with hw about this format */
241 const u32 dsi_pkt_seq_cmd_mode[NUMOF_PKT_SEQ] = {
242         0,
243         0,
244         0,
245         0,
246         0,
247         0,
248         PKT_ID0(CMD_LONGW) | PKT_LEN0(3) | PKT_ID1(CMD_EOT) | PKT_LEN1(7),
249         0,
250         0,
251         0,
252         PKT_ID0(CMD_LONGW) | PKT_LEN0(3) | PKT_ID1(CMD_EOT) | PKT_LEN1(7),
253         0,
254 };
255
256 const u32 init_reg[] = {
257         DSI_INT_ENABLE,
258         DSI_INT_STATUS,
259         DSI_INT_MASK,
260         DSI_INIT_SEQ_DATA_0,
261         DSI_INIT_SEQ_DATA_1,
262         DSI_INIT_SEQ_DATA_2,
263         DSI_INIT_SEQ_DATA_3,
264         DSI_INIT_SEQ_DATA_4,
265         DSI_INIT_SEQ_DATA_5,
266         DSI_INIT_SEQ_DATA_6,
267         DSI_INIT_SEQ_DATA_7,
268         DSI_DCS_CMDS,
269         DSI_PKT_SEQ_0_LO,
270         DSI_PKT_SEQ_1_LO,
271         DSI_PKT_SEQ_2_LO,
272         DSI_PKT_SEQ_3_LO,
273         DSI_PKT_SEQ_4_LO,
274         DSI_PKT_SEQ_5_LO,
275         DSI_PKT_SEQ_0_HI,
276         DSI_PKT_SEQ_1_HI,
277         DSI_PKT_SEQ_2_HI,
278         DSI_PKT_SEQ_3_HI,
279         DSI_PKT_SEQ_4_HI,
280         DSI_PKT_SEQ_5_HI,
281         DSI_CONTROL,
282         DSI_HOST_DSI_CONTROL,
283         DSI_PAD_CONTROL,
284         DSI_PAD_CONTROL_CD,
285         DSI_SOL_DELAY,
286         DSI_MAX_THRESHOLD,
287         DSI_TRIGGER,
288         DSI_TX_CRC,
289         DSI_INIT_SEQ_CONTROL,
290         DSI_PKT_LEN_0_1,
291         DSI_PKT_LEN_2_3,
292         DSI_PKT_LEN_4_5,
293         DSI_PKT_LEN_6_7,
294 };
295
296 inline unsigned long tegra_dsi_readl(struct tegra_dc_dsi_data *dsi, u32 reg)
297 {
298         unsigned long ret;
299
300         BUG_ON(!nvhost_module_powered_ext(nvhost_get_parent(dsi->dc->ndev)));
301         ret = readl(dsi->base + reg * 4);
302         trace_printk("readl %p=%#08lx\n", dsi->base + reg * 4, ret);
303         return ret;
304 }
305 EXPORT_SYMBOL(tegra_dsi_readl);
306
307 inline void tegra_dsi_writel(struct tegra_dc_dsi_data *dsi, u32 val, u32 reg)
308 {
309         BUG_ON(!nvhost_module_powered_ext(nvhost_get_parent(dsi->dc->ndev)));
310         trace_printk("writel %p=%#08x\n", dsi->base + reg * 4, val);
311         writel(val, dsi->base + reg * 4);
312 }
313 EXPORT_SYMBOL(tegra_dsi_writel);
314
315 #ifdef CONFIG_DEBUG_FS
316 static int dbg_dsi_show(struct seq_file *s, void *unused)
317 {
318         struct tegra_dc_dsi_data *dsi = s->private;
319
320 #define DUMP_REG(a) do {                                                \
321                 seq_printf(s, "%-32s\t%03x\t%08lx\n",                   \
322                        #a, a, tegra_dsi_readl(dsi, a));         \
323         } while (0)
324
325         tegra_dc_io_start(dsi->dc);
326         clk_enable(dsi->dsi_clk);
327
328         DUMP_REG(DSI_INCR_SYNCPT_CNTRL);
329         DUMP_REG(DSI_INCR_SYNCPT_ERROR);
330         DUMP_REG(DSI_CTXSW);
331         DUMP_REG(DSI_POWER_CONTROL);
332         DUMP_REG(DSI_INT_ENABLE);
333         DUMP_REG(DSI_CONTROL);
334         DUMP_REG(DSI_SOL_DELAY);
335         DUMP_REG(DSI_MAX_THRESHOLD);
336         DUMP_REG(DSI_TRIGGER);
337         DUMP_REG(DSI_TX_CRC);
338         DUMP_REG(DSI_STATUS);
339         DUMP_REG(DSI_INIT_SEQ_CONTROL);
340         DUMP_REG(DSI_INIT_SEQ_DATA_0);
341         DUMP_REG(DSI_INIT_SEQ_DATA_1);
342         DUMP_REG(DSI_INIT_SEQ_DATA_2);
343         DUMP_REG(DSI_INIT_SEQ_DATA_3);
344         DUMP_REG(DSI_INIT_SEQ_DATA_4);
345         DUMP_REG(DSI_INIT_SEQ_DATA_5);
346         DUMP_REG(DSI_INIT_SEQ_DATA_6);
347         DUMP_REG(DSI_INIT_SEQ_DATA_7);
348         DUMP_REG(DSI_PKT_SEQ_0_LO);
349         DUMP_REG(DSI_PKT_SEQ_0_HI);
350         DUMP_REG(DSI_PKT_SEQ_1_LO);
351         DUMP_REG(DSI_PKT_SEQ_1_HI);
352         DUMP_REG(DSI_PKT_SEQ_2_LO);
353         DUMP_REG(DSI_PKT_SEQ_2_HI);
354         DUMP_REG(DSI_PKT_SEQ_3_LO);
355         DUMP_REG(DSI_PKT_SEQ_3_HI);
356         DUMP_REG(DSI_PKT_SEQ_4_LO);
357         DUMP_REG(DSI_PKT_SEQ_4_HI);
358         DUMP_REG(DSI_PKT_SEQ_5_LO);
359         DUMP_REG(DSI_PKT_SEQ_5_HI);
360         DUMP_REG(DSI_DCS_CMDS);
361         DUMP_REG(DSI_PKT_LEN_0_1);
362         DUMP_REG(DSI_PKT_LEN_2_3);
363         DUMP_REG(DSI_PKT_LEN_4_5);
364         DUMP_REG(DSI_PKT_LEN_6_7);
365         DUMP_REG(DSI_PHY_TIMING_0);
366         DUMP_REG(DSI_PHY_TIMING_1);
367         DUMP_REG(DSI_PHY_TIMING_2);
368         DUMP_REG(DSI_BTA_TIMING);
369         DUMP_REG(DSI_TIMEOUT_0);
370         DUMP_REG(DSI_TIMEOUT_1);
371         DUMP_REG(DSI_TO_TALLY);
372         DUMP_REG(DSI_PAD_CONTROL);
373         DUMP_REG(DSI_PAD_CONTROL_CD);
374         DUMP_REG(DSI_PAD_CD_STATUS);
375         DUMP_REG(DSI_VID_MODE_CONTROL);
376 #undef DUMP_REG
377
378         clk_disable(dsi->dsi_clk);
379         tegra_dc_io_end(dsi->dc);
380
381         return 0;
382 }
383
384 static int dbg_dsi_open(struct inode *inode, struct file *file)
385 {
386         return single_open(file, dbg_dsi_show, inode->i_private);
387 }
388
389 static const struct file_operations dbg_fops = {
390         .open           = dbg_dsi_open,
391         .read           = seq_read,
392         .llseek         = seq_lseek,
393         .release        = single_release,
394 };
395
396 static struct dentry *dsidir;
397
398 static void tegra_dc_dsi_debug_create(struct tegra_dc_dsi_data *dsi)
399 {
400         struct dentry *retval;
401
402         dsidir = debugfs_create_dir("tegra_dsi", NULL);
403         if (!dsidir)
404                 return;
405         retval = debugfs_create_file("regs", S_IRUGO, dsidir, dsi,
406                 &dbg_fops);
407         if (!retval)
408                 goto free_out;
409         return;
410 free_out:
411         debugfs_remove_recursive(dsidir);
412         dsidir = NULL;
413         return;
414 }
415 #else
416 static inline void tegra_dc_dsi_debug_create(struct tegra_dc_dsi_data *dsi)
417 { }
418 #endif
419
420 static inline void tegra_dsi_clk_enable(struct tegra_dc_dsi_data *dsi)
421 {
422         if (!tegra_is_clk_enabled(dsi->dsi_clk)) {
423                 clk_enable(dsi->dsi_clk);
424                 clk_enable(dsi->dsi_fixed_clk);
425         }
426 }
427
428 static inline void tegra_dsi_clk_disable(struct tegra_dc_dsi_data *dsi)
429 {
430         if (tegra_is_clk_enabled(dsi->dsi_clk)) {
431                 clk_disable(dsi->dsi_clk);
432                 clk_disable(dsi->dsi_fixed_clk);
433         }
434 }
435
436 static int tegra_dsi_syncpt(struct tegra_dc_dsi_data *dsi)
437 {
438         u32 val;
439         int ret;
440
441         ret = 0;
442
443         dsi->syncpt_val = nvhost_syncpt_read_ext(dsi->dc->ndev, dsi->syncpt_id);
444
445         val = DSI_INCR_SYNCPT_COND(OP_DONE) |
446                 DSI_INCR_SYNCPT_INDX(dsi->syncpt_id);
447         tegra_dsi_writel(dsi, val, DSI_INCR_SYNCPT);
448
449         /* TODO: Use interrupt rather than polling */
450         ret = nvhost_syncpt_wait_timeout_ext(dsi->dc->ndev, dsi->syncpt_id,
451                 dsi->syncpt_val + 1, MAX_SCHEDULE_TIMEOUT, NULL);
452         if (ret < 0) {
453                 dev_err(&dsi->dc->ndev->dev, "DSI sync point failure\n");
454                 goto fail;
455         }
456
457         (dsi->syncpt_val)++;
458         return 0;
459 fail:
460         return ret;
461 }
462
463 static u32 tegra_dsi_get_hs_clk_rate(struct tegra_dc_dsi_data *dsi)
464 {
465         u32 dsi_clock_rate_khz;
466
467         switch (dsi->info.video_burst_mode) {
468         case TEGRA_DSI_VIDEO_BURST_MODE_LOW_SPEED:
469         case TEGRA_DSI_VIDEO_BURST_MODE_MEDIUM_SPEED:
470         case TEGRA_DSI_VIDEO_BURST_MODE_FAST_SPEED:
471         case TEGRA_DSI_VIDEO_BURST_MODE_FASTEST_SPEED:
472                 /* Calculate DSI HS clock rate for DSI burst mode */
473                 dsi_clock_rate_khz = dsi->default_pixel_clk_khz *
474                                                         dsi->shift_clk_div;
475                 break;
476         case TEGRA_DSI_VIDEO_NONE_BURST_MODE:
477         case TEGRA_DSI_VIDEO_NONE_BURST_MODE_WITH_SYNC_END:
478         case TEGRA_DSI_VIDEO_BURST_MODE_LOWEST_SPEED:
479         default:
480                 /* Clock rate is default DSI clock rate for non-burst mode */
481                 dsi_clock_rate_khz = dsi->default_hs_clk_khz;
482                 break;
483         }
484
485         return dsi_clock_rate_khz;
486 }
487
488 static u32 tegra_dsi_get_lp_clk_rate(struct tegra_dc_dsi_data *dsi, u8 lp_op)
489 {
490         u32 dsi_clock_rate_khz;
491
492         if (dsi->info.enable_hs_clock_on_lp_cmd_mode)
493                 if (dsi->info.hs_clk_in_lp_cmd_mode_freq_khz)
494                         dsi_clock_rate_khz =
495                                 dsi->info.hs_clk_in_lp_cmd_mode_freq_khz;
496                 else
497                         dsi_clock_rate_khz = tegra_dsi_get_hs_clk_rate(dsi);
498         else
499                 if (lp_op == DSI_LP_OP_READ)
500                         dsi_clock_rate_khz =
501                                 dsi->info.lp_read_cmd_mode_freq_khz;
502                 else
503                         dsi_clock_rate_khz =
504                                 dsi->info.lp_cmd_mode_freq_khz;
505
506         return dsi_clock_rate_khz;
507 }
508
509 static u32 tegra_dsi_get_shift_clk_div(struct tegra_dc_dsi_data *dsi)
510 {
511         u32 shift_clk_div;
512         u32 max_shift_clk_div;
513         u32 burst_width;
514         u32 burst_width_max;
515
516         /* Get the real value of default shift_clk_div. default_shift_clk_div
517          * holds the real value of shift_clk_div.
518          */
519         shift_clk_div = dsi->default_shift_clk_div;
520
521         /* Calculate shift_clk_div which can matche the video_burst_mode. */
522         if (dsi->info.video_burst_mode >=
523                         TEGRA_DSI_VIDEO_BURST_MODE_LOWEST_SPEED) {
524                 /* The max_shift_clk_div is multiplied by 10 to save the
525                  * fraction
526                  */
527                 if (dsi->info.max_panel_freq_khz >= dsi->default_hs_clk_khz)
528                         max_shift_clk_div = dsi->info.max_panel_freq_khz
529                                 * shift_clk_div * 10 / dsi->default_hs_clk_khz;
530                 else
531                         max_shift_clk_div = shift_clk_div * 10;
532
533                 burst_width = dsi->info.video_burst_mode
534                                 - TEGRA_DSI_VIDEO_BURST_MODE_LOWEST_SPEED;
535                 burst_width_max = TEGRA_DSI_VIDEO_BURST_MODE_FASTEST_SPEED
536                                 - TEGRA_DSI_VIDEO_BURST_MODE_LOWEST_SPEED;
537
538                 shift_clk_div = (max_shift_clk_div - shift_clk_div * 10) *
539                         burst_width / (burst_width_max * 10) + shift_clk_div;
540         }
541
542         return shift_clk_div;
543 }
544
545 static void tegra_dsi_init_sw(struct tegra_dc *dc,
546                         struct tegra_dc_dsi_data *dsi)
547 {
548         u32 h_width_pixels;
549         u32 v_width_lines;
550         u32 pixel_clk_hz;
551         u32 byte_clk_hz;
552         u32 plld_clk_mhz;
553
554         switch (dsi->info.pixel_format) {
555         case TEGRA_DSI_PIXEL_FORMAT_16BIT_P:
556                 /* 2 bytes per pixel */
557                 dsi->pixel_scaler_mul = 2;
558                 dsi->pixel_scaler_div = 1;
559                 break;
560         case TEGRA_DSI_PIXEL_FORMAT_18BIT_P:
561                 /* 2.25 bytes per pixel */
562                 dsi->pixel_scaler_mul = 9;
563                 dsi->pixel_scaler_div = 4;
564                 break;
565         case TEGRA_DSI_PIXEL_FORMAT_18BIT_NP:
566         case TEGRA_DSI_PIXEL_FORMAT_24BIT_P:
567                 /* 3 bytes per pixel */
568                 dsi->pixel_scaler_mul = 3;
569                 dsi->pixel_scaler_div = 1;
570                 break;
571         default:
572                 break;
573         }
574
575         dsi->controller_index = dc->ndev->id;
576         dsi->ulpm = false;
577         dsi->enabled = false;
578         dsi->clk_ref = false;
579
580         dsi->dsi_control_val =
581                         DSI_CONTROL_VIRTUAL_CHANNEL(dsi->info.virtual_channel) |
582                         DSI_CONTROL_NUM_DATA_LANES(dsi->info.n_data_lanes - 1) |
583                         DSI_CONTROL_VID_SOURCE(dsi->controller_index) |
584                         DSI_CONTROL_DATA_FORMAT(dsi->info.pixel_format);
585
586         /* Below we are going to calculate dsi and dc clock rate.
587          * Calcuate the horizontal and vertical width.
588          */
589         h_width_pixels = dc->mode.h_back_porch + dc->mode.h_front_porch +
590                         dc->mode.h_sync_width + dc->mode.h_active;
591         v_width_lines = dc->mode.v_back_porch + dc->mode.v_front_porch +
592                         dc->mode.v_sync_width + dc->mode.v_active;
593
594         /* Calculate minimum required pixel rate. */
595         pixel_clk_hz = h_width_pixels * v_width_lines * dsi->info.refresh_rate;
596         if (dc->out->flags & TEGRA_DC_OUT_ONE_SHOT_MODE) {
597                 if (dsi->info.rated_refresh_rate >= dsi->info.refresh_rate)
598                         dev_info(&dc->ndev->dev, "DSI: measured refresh rate "
599                                 "should be larger than rated refresh rate.\n");
600                 dc->mode.rated_pclk = h_width_pixels * v_width_lines *
601                                                 dsi->info.rated_refresh_rate;
602         }
603
604         /* Calculate minimum byte rate on DSI interface. */
605         byte_clk_hz = (pixel_clk_hz * dsi->pixel_scaler_mul) /
606                         (dsi->pixel_scaler_div * dsi->info.n_data_lanes);
607
608         /* Round up to multiple of mega hz. */
609         plld_clk_mhz = DIV_ROUND_UP((byte_clk_hz * NUMOF_BIT_PER_BYTE),
610                                                                 1000000);
611
612         /* Calculate default real shift_clk_div. */
613         dsi->default_shift_clk_div = (NUMOF_BIT_PER_BYTE / 2) *
614                 dsi->pixel_scaler_mul / (dsi->pixel_scaler_div *
615                 dsi->info.n_data_lanes);
616         /* Calculate default DSI hs clock. DSI interface is double data rate.
617          * Data is transferred on both rising and falling edge of clk, div by 2
618          * to get the actual clock rate.
619          */
620         dsi->default_hs_clk_khz = plld_clk_mhz * 1000 / 2;
621         dsi->default_pixel_clk_khz = plld_clk_mhz * 1000 / 2
622                                                 / dsi->default_shift_clk_div;
623
624         /* Get the actual shift_clk_div and clock rates. */
625         dsi->shift_clk_div = tegra_dsi_get_shift_clk_div(dsi);
626         dsi->target_lp_clk_khz =
627                         tegra_dsi_get_lp_clk_rate(dsi, DSI_LP_OP_WRITE);
628         dsi->target_hs_clk_khz = tegra_dsi_get_hs_clk_rate(dsi);
629
630         dev_info(&dc->ndev->dev, "DSI: HS clock rate is %d\n",
631                                                         dsi->target_hs_clk_khz);
632
633         dsi->controller_index = dc->ndev->id;
634
635 #if DSI_USE_SYNC_POINTS
636         dsi->syncpt_id = NVSYNCPT_DSI;
637 #endif
638
639         /*
640          * Force video clock to be continuous mode if
641          * enable_hs_clock_on_lp_cmd_mode is set
642          */
643         if (dsi->info.enable_hs_clock_on_lp_cmd_mode) {
644                 if (dsi->info.video_clock_mode !=
645                                         TEGRA_DSI_VIDEO_CLOCK_CONTINUOUS)
646                         dev_warn(&dc->ndev->dev,
647                                 "Force clock continuous mode\n");
648
649                 dsi->info.video_clock_mode = TEGRA_DSI_VIDEO_CLOCK_CONTINUOUS;
650         }
651
652 }
653
654 #define SELECT_T_PHY(platform_t_phy_ns, default_phy, clk_ns, hw_inc) ( \
655 (platform_t_phy_ns) ? ( \
656 ((DSI_CONVERT_T_PHY_NS_TO_T_PHY(platform_t_phy_ns, clk_ns, hw_inc)) < 0 ? 0 : \
657 (DSI_CONVERT_T_PHY_NS_TO_T_PHY(platform_t_phy_ns, clk_ns, hw_inc)))) : \
658 ((default_phy) < 0 ? 0 : (default_phy)))
659
660 static void tegra_dsi_get_clk_phy_timing(struct tegra_dc_dsi_data *dsi,
661                 struct dsi_phy_timing_inclk *phy_timing_clk, u32 clk_ns)
662 {
663         phy_timing_clk->t_tlpx = SELECT_T_PHY(
664                 dsi->info.phy_timing.t_tlpx_ns,
665                 T_TLPX_DEFAULT(clk_ns), clk_ns, T_TLPX_HW_INC);
666
667         phy_timing_clk->t_clktrail = SELECT_T_PHY(
668                 dsi->info.phy_timing.t_clktrail_ns,
669                 T_CLKTRAIL_DEFAULT(clk_ns), clk_ns, T_CLKTRAIL_HW_INC);
670
671         phy_timing_clk->t_clkpost = SELECT_T_PHY(
672                 dsi->info.phy_timing.t_clkpost_ns,
673                 T_CLKPOST_DEFAULT(clk_ns), clk_ns, T_CLKPOST_HW_INC);
674
675         phy_timing_clk->t_clkzero = SELECT_T_PHY(
676                 dsi->info.phy_timing.t_clkzero_ns,
677                 T_CLKZERO_DEFAULT(clk_ns), clk_ns, T_CLKZERO_HW_INC);
678
679         phy_timing_clk->t_clkprepare = SELECT_T_PHY(
680                 dsi->info.phy_timing.t_clkprepare_ns,
681                 T_CLKPREPARE_DEFAULT(clk_ns), clk_ns, T_CLKPREPARE_HW_INC);
682
683         phy_timing_clk->t_clkpre = SELECT_T_PHY(
684                 dsi->info.phy_timing.t_clkpre_ns,
685                 T_CLKPRE_DEFAULT, clk_ns, T_CLKPRE_HW_INC);
686 }
687
688 static void tegra_dsi_get_hs_phy_timing(struct tegra_dc_dsi_data *dsi,
689                 struct dsi_phy_timing_inclk *phy_timing_clk, u32 clk_ns)
690 {
691         phy_timing_clk->t_tlpx = SELECT_T_PHY(
692                 dsi->info.phy_timing.t_tlpx_ns,
693                 T_TLPX_DEFAULT(clk_ns), clk_ns, T_TLPX_HW_INC);
694
695         phy_timing_clk->t_hsdexit = SELECT_T_PHY(
696                 dsi->info.phy_timing.t_hsdexit_ns,
697                 T_HSEXIT_DEFAULT(clk_ns), clk_ns, T_HSEXIT_HW_INC);
698
699         phy_timing_clk->t_hstrail = SELECT_T_PHY(
700                 dsi->info.phy_timing.t_hstrail_ns,
701                 T_HSTRAIL_DEFAULT(clk_ns), clk_ns, T_HSTRAIL_HW_INC);
702
703         phy_timing_clk->t_datzero = SELECT_T_PHY(
704                 dsi->info.phy_timing.t_datzero_ns,
705                 T_DATZERO_DEFAULT(clk_ns), clk_ns, T_DATZERO_HW_INC);
706
707         phy_timing_clk->t_hsprepare = SELECT_T_PHY(
708                 dsi->info.phy_timing.t_hsprepare_ns,
709                 T_HSPREPARE_DEFAULT(clk_ns), clk_ns, T_HSPREPARE_HW_INC);
710 }
711
712 static void tegra_dsi_get_escape_phy_timing(struct tegra_dc_dsi_data *dsi,
713                 struct dsi_phy_timing_inclk *phy_timing_clk, u32 clk_ns)
714 {
715         phy_timing_clk->t_tlpx = SELECT_T_PHY(
716                 dsi->info.phy_timing.t_tlpx_ns,
717                 T_TLPX_DEFAULT(clk_ns), clk_ns, T_TLPX_HW_INC);
718 }
719
720 static void tegra_dsi_get_bta_phy_timing(struct tegra_dc_dsi_data *dsi,
721                 struct dsi_phy_timing_inclk *phy_timing_clk, u32 clk_ns)
722 {
723         phy_timing_clk->t_tlpx = SELECT_T_PHY(
724                 dsi->info.phy_timing.t_tlpx_ns,
725                 T_TLPX_DEFAULT(clk_ns), clk_ns, T_TLPX_HW_INC);
726
727         phy_timing_clk->t_taget = SELECT_T_PHY(
728                 dsi->info.phy_timing.t_taget_ns,
729                 T_TAGET_DEFAULT(clk_ns), clk_ns, T_TAGET_HW_INC);
730
731         phy_timing_clk->t_tasure = SELECT_T_PHY(
732                 dsi->info.phy_timing.t_tasure_ns,
733                 T_TASURE_DEFAULT(clk_ns), clk_ns, T_TASURE_HW_INC);
734
735         phy_timing_clk->t_tago = SELECT_T_PHY(
736                 dsi->info.phy_timing.t_tago_ns,
737                 T_TAGO_DEFAULT(clk_ns), clk_ns, T_TAGO_HW_INC);
738 }
739
740 static void tegra_dsi_get_ulps_phy_timing(struct tegra_dc_dsi_data *dsi,
741                 struct dsi_phy_timing_inclk *phy_timing_clk, u32 clk_ns)
742 {
743         phy_timing_clk->t_tlpx = SELECT_T_PHY(
744                 dsi->info.phy_timing.t_tlpx_ns,
745                 T_TLPX_DEFAULT(clk_ns), clk_ns, T_TLPX_HW_INC);
746
747         phy_timing_clk->t_wakeup = SELECT_T_PHY(
748                 dsi->info.phy_timing.t_wakeup_ns,
749                 T_WAKEUP_DEFAULT, clk_ns, T_WAKEUP_HW_INC);
750 }
751
752 #undef SELECT_T_PHY
753
754 static void tegra_dsi_get_phy_timing(struct tegra_dc_dsi_data *dsi,
755                                 struct dsi_phy_timing_inclk *phy_timing_clk,
756                                 u32 clk_ns, u8 lphs)
757 {
758         if (lphs == DSI_LPHS_IN_HS_MODE) {
759                 tegra_dsi_get_clk_phy_timing(dsi, phy_timing_clk, clk_ns);
760                 tegra_dsi_get_hs_phy_timing(dsi, phy_timing_clk, clk_ns);
761         } else {
762                 /* default is LP mode */
763                 tegra_dsi_get_escape_phy_timing(dsi, phy_timing_clk, clk_ns);
764                 tegra_dsi_get_bta_phy_timing(dsi, phy_timing_clk, clk_ns);
765                 tegra_dsi_get_ulps_phy_timing(dsi, phy_timing_clk, clk_ns);
766                 if (dsi->info.enable_hs_clock_on_lp_cmd_mode)
767                         tegra_dsi_get_clk_phy_timing
768                                 (dsi, phy_timing_clk, clk_ns);
769         }
770 }
771
772 static int tegra_dsi_mipi_phy_timing_range(struct tegra_dc_dsi_data *dsi,
773                                 struct dsi_phy_timing_inclk *phy_timing,
774                                 u32 clk_ns, u8 lphs)
775 {
776 #define CHECK_RANGE(val, min, max) ( \
777                 ((min) == NOT_DEFINED ? 0 : (val) < (min)) || \
778                 ((max) == NOT_DEFINED ? 0 : (val) > (max)) ? -EINVAL : 0)
779
780         int err = 0;
781
782         err = CHECK_RANGE(
783         DSI_CONVERT_T_PHY_TO_T_PHY_NS(
784                         phy_timing->t_tlpx, clk_ns, T_TLPX_HW_INC),
785                         MIPI_T_TLPX_NS_MIN, MIPI_T_TLPX_NS_MAX);
786         if (err < 0) {
787                 dev_warn(&dsi->dc->ndev->dev,
788                         "dsi: Tlpx mipi range violated\n");
789                 goto fail;
790         }
791
792         if (lphs == DSI_LPHS_IN_HS_MODE) {
793                 err = CHECK_RANGE(
794                 DSI_CONVERT_T_PHY_TO_T_PHY_NS(
795                         phy_timing->t_hsdexit, clk_ns, T_HSEXIT_HW_INC),
796                         MIPI_T_HSEXIT_NS_MIN, MIPI_T_HSEXIT_NS_MAX);
797                 if (err < 0) {
798                         dev_warn(&dsi->dc->ndev->dev,
799                                 "dsi: HsExit mipi range violated\n");
800                         goto fail;
801                 }
802
803                 err = CHECK_RANGE(
804                 DSI_CONVERT_T_PHY_TO_T_PHY_NS(
805                         phy_timing->t_hstrail, clk_ns, T_HSTRAIL_HW_INC),
806                         MIPI_T_HSTRAIL_NS_MIN(clk_ns), MIPI_T_HSTRAIL_NS_MAX);
807                 if (err < 0) {
808                         dev_warn(&dsi->dc->ndev->dev,
809                                 "dsi: HsTrail mipi range violated\n");
810                         goto fail;
811                 }
812
813                 err = CHECK_RANGE(
814                 DSI_CONVERT_T_PHY_TO_T_PHY_NS(
815                         phy_timing->t_datzero, clk_ns, T_DATZERO_HW_INC),
816                         MIPI_T_HSZERO_NS_MIN, MIPI_T_HSZERO_NS_MAX);
817                 if (err < 0) {
818                         dev_warn(&dsi->dc->ndev->dev,
819                                 "dsi: HsZero mipi range violated\n");
820                         goto fail;
821                 }
822
823                 err = CHECK_RANGE(
824                 DSI_CONVERT_T_PHY_TO_T_PHY_NS(
825                         phy_timing->t_hsprepare, clk_ns, T_HSPREPARE_HW_INC),
826                         MIPI_T_HSPREPARE_NS_MIN(clk_ns),
827                         MIPI_T_HSPREPARE_NS_MAX(clk_ns));
828                 if (err < 0) {
829                         dev_warn(&dsi->dc->ndev->dev,
830                                 "dsi: HsPrepare mipi range violated\n");
831                         goto fail;
832                 }
833
834                 err = CHECK_RANGE(
835                 DSI_CONVERT_T_PHY_TO_T_PHY_NS(
836                 phy_timing->t_hsprepare, clk_ns, T_HSPREPARE_HW_INC) +
837                 DSI_CONVERT_T_PHY_TO_T_PHY_NS(
838                         phy_timing->t_datzero, clk_ns, T_DATZERO_HW_INC),
839                         MIPI_T_HSPREPARE_ADD_HSZERO_NS_MIN(clk_ns),
840                         MIPI_T_HSPREPARE_ADD_HSZERO_NS_MAX);
841                 if (err < 0) {
842                         dev_warn(&dsi->dc->ndev->dev,
843                         "dsi: HsPrepare + HsZero mipi range violated\n");
844                         goto fail;
845                 }
846         } else {
847                 /* default is LP mode */
848                 err = CHECK_RANGE(
849                 DSI_CONVERT_T_PHY_TO_T_PHY_NS(
850                         phy_timing->t_wakeup, clk_ns, T_WAKEUP_HW_INC),
851                         MIPI_T_WAKEUP_NS_MIN, MIPI_T_WAKEUP_NS_MAX);
852                 if (err < 0) {
853                         dev_warn(&dsi->dc->ndev->dev,
854                                 "dsi: WakeUp mipi range violated\n");
855                         goto fail;
856                 }
857
858                 err = CHECK_RANGE(
859                 DSI_CONVERT_T_PHY_TO_T_PHY_NS(
860                         phy_timing->t_tasure, clk_ns, T_TASURE_HW_INC),
861                         MIPI_T_TASURE_NS_MIN(DSI_CONVERT_T_PHY_TO_T_PHY_NS(
862                         phy_timing->t_tlpx, clk_ns, T_TLPX_HW_INC)),
863                         MIPI_T_TASURE_NS_MAX(DSI_CONVERT_T_PHY_TO_T_PHY_NS(
864                         phy_timing->t_tlpx, clk_ns, T_TLPX_HW_INC)));
865                 if (err < 0) {
866                         dev_warn(&dsi->dc->ndev->dev,
867                                 "dsi: TaSure mipi range violated\n");
868                         goto fail;
869                 }
870         }
871
872         if (lphs == DSI_LPHS_IN_HS_MODE ||
873                 dsi->info.enable_hs_clock_on_lp_cmd_mode) {
874                 err = CHECK_RANGE(
875                 DSI_CONVERT_T_PHY_TO_T_PHY_NS(
876                         phy_timing->t_clktrail, clk_ns, T_CLKTRAIL_HW_INC),
877                         MIPI_T_CLKTRAIL_NS_MIN, MIPI_T_CLKTRAIL_NS_MAX);
878                 if (err < 0) {
879                         dev_warn(&dsi->dc->ndev->dev,
880                                 "dsi: ClkTrail mipi range violated\n");
881                         goto fail;
882                 }
883
884                 err = CHECK_RANGE(
885                 DSI_CONVERT_T_PHY_TO_T_PHY_NS(
886                         phy_timing->t_clkpost, clk_ns, T_CLKPOST_HW_INC),
887                         MIPI_T_CLKPOST_NS_MIN(clk_ns), MIPI_T_CLKPOST_NS_MAX);
888                 if (err < 0) {
889                         dev_warn(&dsi->dc->ndev->dev,
890                                 "dsi: ClkPost mipi range violated\n");
891                         goto fail;
892                 }
893
894                 err = CHECK_RANGE(
895                 DSI_CONVERT_T_PHY_TO_T_PHY_NS(
896                         phy_timing->t_clkzero, clk_ns, T_CLKZERO_HW_INC),
897                         MIPI_T_CLKZERO_NS_MIN, MIPI_T_CLKZERO_NS_MAX);
898                 if (err < 0) {
899                         dev_warn(&dsi->dc->ndev->dev,
900                                 "dsi: ClkZero mipi range violated\n");
901                         goto fail;
902                 }
903
904                 err = CHECK_RANGE(
905                 DSI_CONVERT_T_PHY_TO_T_PHY_NS(
906                         phy_timing->t_clkprepare, clk_ns, T_CLKPREPARE_HW_INC),
907                         MIPI_T_CLKPREPARE_NS_MIN, MIPI_T_CLKPREPARE_NS_MAX);
908                 if (err < 0) {
909                         dev_warn(&dsi->dc->ndev->dev,
910                                 "dsi: ClkPrepare mipi range violated\n");
911                         goto fail;
912                 }
913
914                 err = CHECK_RANGE(
915                 DSI_CONVERT_T_PHY_TO_T_PHY_NS(
916                         phy_timing->t_clkpre, clk_ns, T_CLKPRE_HW_INC),
917                         MIPI_T_CLKPRE_NS_MIN, MIPI_T_CLKPRE_NS_MAX);
918                 if (err < 0) {
919                         dev_warn(&dsi->dc->ndev->dev,
920                                 "dsi: ClkPre mipi range violated\n");
921                         goto fail;
922                 }
923
924                 err = CHECK_RANGE(
925                 DSI_CONVERT_T_PHY_TO_T_PHY_NS(
926                 phy_timing->t_clkprepare, clk_ns, T_CLKPREPARE_HW_INC) +
927                 DSI_CONVERT_T_PHY_TO_T_PHY_NS(
928                         phy_timing->t_clkzero, clk_ns, T_CLKZERO_HW_INC),
929                         MIPI_T_CLKPREPARE_ADD_CLKZERO_NS_MIN,
930                         MIPI_T_CLKPREPARE_ADD_CLKZERO_NS_MAX);
931                 if (err < 0) {
932                         dev_warn(&dsi->dc->ndev->dev,
933                         "dsi: ClkPrepare + ClkZero mipi range violated\n");
934                         goto fail;
935                 }
936         }
937 fail:
938 #undef CHECK_RANGE
939         return err;
940 }
941
942 static int tegra_dsi_hs_phy_len(struct tegra_dc_dsi_data *dsi,
943                                 struct dsi_phy_timing_inclk *phy_timing,
944                                 u32 clk_ns, u8 lphs)
945 {
946         u32 hs_t_phy_ns;
947         u32 clk_t_phy_ns;
948         u32 t_phy_ns;
949         u32 h_blank_ns;
950         struct tegra_dc_mode *modes;
951         u32 t_pix_ns;
952         int err = 0;
953
954         if (!(lphs == DSI_LPHS_IN_HS_MODE))
955                 goto fail;
956
957         modes = dsi->dc->out->modes;
958         t_pix_ns = clk_ns * BITS_PER_BYTE *
959                 dsi->pixel_scaler_mul / dsi->pixel_scaler_div;
960
961         hs_t_phy_ns =
962                 DSI_CONVERT_T_PHY_TO_T_PHY_NS(
963                 phy_timing->t_tlpx, clk_ns, T_TLPX_HW_INC) +
964                 DSI_CONVERT_T_PHY_TO_T_PHY_NS(
965                 phy_timing->t_hsprepare, clk_ns, T_HSPREPARE_HW_INC) +
966                 DSI_CONVERT_T_PHY_TO_T_PHY_NS(
967                 phy_timing->t_datzero, clk_ns, T_DATZERO_HW_INC) +
968                 DSI_CONVERT_T_PHY_TO_T_PHY_NS(
969                 phy_timing->t_hstrail, clk_ns, T_HSTRAIL_HW_INC) +
970                 DSI_CONVERT_T_PHY_TO_T_PHY_NS(
971                 phy_timing->t_hsdexit, clk_ns, T_HSEXIT_HW_INC);
972
973         clk_t_phy_ns =
974                 DSI_CONVERT_T_PHY_TO_T_PHY_NS(
975                 phy_timing->t_clkpost, clk_ns, T_CLKPOST_HW_INC) +
976                 DSI_CONVERT_T_PHY_TO_T_PHY_NS(
977                 phy_timing->t_clktrail, clk_ns, T_CLKTRAIL_HW_INC) +
978                 DSI_CONVERT_T_PHY_TO_T_PHY_NS(
979                 phy_timing->t_hsdexit, clk_ns, T_HSEXIT_HW_INC) +
980                 DSI_CONVERT_T_PHY_TO_T_PHY_NS(
981                 phy_timing->t_tlpx, clk_ns, T_TLPX_HW_INC) +
982                 DSI_CONVERT_T_PHY_TO_T_PHY_NS(
983                 phy_timing->t_clkprepare, clk_ns, T_CLKPREPARE_HW_INC) +
984                 DSI_CONVERT_T_PHY_TO_T_PHY_NS(
985                 phy_timing->t_clkzero, clk_ns, T_CLKZERO_HW_INC) +
986                 DSI_CONVERT_T_PHY_TO_T_PHY_NS(
987                 phy_timing->t_clkpre, clk_ns, T_CLKPRE_HW_INC);
988
989         h_blank_ns = t_pix_ns * (modes->h_sync_width + modes->h_back_porch +
990                                                 modes->h_front_porch);
991
992         /* Extra tlpx and byte cycle required by dsi HW */
993         t_phy_ns = dsi->info.n_data_lanes * (hs_t_phy_ns + clk_t_phy_ns +
994                 DSI_CONVERT_T_PHY_TO_T_PHY_NS(
995                 phy_timing->t_tlpx, clk_ns, T_TLPX_HW_INC) +
996                 clk_ns * BITS_PER_BYTE);
997
998         if (h_blank_ns < t_phy_ns) {
999                 err = -EINVAL;
1000                 dev_err(&dsi->dc->ndev->dev,
1001                         "dsi: Hblank is smaller than HS trans phy timing\n");
1002                 goto fail;
1003         }
1004
1005         return 0;
1006 fail:
1007         return err;
1008 }
1009
1010 static int tegra_dsi_constraint_phy_timing(struct tegra_dc_dsi_data *dsi,
1011                                 struct dsi_phy_timing_inclk *phy_timing,
1012                                 u32 clk_ns, u8 lphs)
1013 {
1014         int err = 0;
1015
1016         err = tegra_dsi_mipi_phy_timing_range(dsi, phy_timing, clk_ns, lphs);
1017         if (err < 0) {
1018                 dev_warn(&dsi->dc->ndev->dev, "dsi: mipi range violated\n");
1019                 goto fail;
1020         }
1021
1022         err = tegra_dsi_hs_phy_len(dsi, phy_timing, clk_ns, lphs);
1023         if (err < 0) {
1024                 dev_err(&dsi->dc->ndev->dev, "dsi: Hblank too short\n");
1025                 goto fail;
1026         }
1027
1028         /* TODO: add more contraints */
1029 fail:
1030         return err;
1031 }
1032
1033 static void tegra_dsi_set_phy_timing(struct tegra_dc_dsi_data *dsi, u8 lphs)
1034 {
1035         u32 val;
1036         struct dsi_phy_timing_inclk phy_timing = dsi->phy_timing;
1037
1038         tegra_dsi_get_phy_timing
1039                 (dsi, &phy_timing, dsi->current_bit_clk_ns, lphs);
1040
1041         tegra_dsi_constraint_phy_timing(dsi, &phy_timing,
1042                                         dsi->current_bit_clk_ns, lphs);
1043
1044         val = DSI_PHY_TIMING_0_THSDEXIT(phy_timing.t_hsdexit) |
1045                         DSI_PHY_TIMING_0_THSTRAIL(phy_timing.t_hstrail) |
1046                         DSI_PHY_TIMING_0_TDATZERO(phy_timing.t_datzero) |
1047                         DSI_PHY_TIMING_0_THSPREPR(phy_timing.t_hsprepare);
1048         tegra_dsi_writel(dsi, val, DSI_PHY_TIMING_0);
1049
1050         val = DSI_PHY_TIMING_1_TCLKTRAIL(phy_timing.t_clktrail) |
1051                         DSI_PHY_TIMING_1_TCLKPOST(phy_timing.t_clkpost) |
1052                         DSI_PHY_TIMING_1_TCLKZERO(phy_timing.t_clkzero) |
1053                         DSI_PHY_TIMING_1_TTLPX(phy_timing.t_tlpx);
1054         tegra_dsi_writel(dsi, val, DSI_PHY_TIMING_1);
1055
1056         val = DSI_PHY_TIMING_2_TCLKPREPARE(phy_timing.t_clkprepare) |
1057                 DSI_PHY_TIMING_2_TCLKPRE(phy_timing.t_clkpre) |
1058                         DSI_PHY_TIMING_2_TWAKEUP(phy_timing.t_wakeup);
1059         tegra_dsi_writel(dsi, val, DSI_PHY_TIMING_2);
1060
1061         val = DSI_BTA_TIMING_TTAGET(phy_timing.t_taget) |
1062                         DSI_BTA_TIMING_TTASURE(phy_timing.t_tasure) |
1063                         DSI_BTA_TIMING_TTAGO(phy_timing.t_tago);
1064         tegra_dsi_writel(dsi, val, DSI_BTA_TIMING);
1065
1066         dsi->phy_timing = phy_timing;
1067 }
1068
1069 static u32 tegra_dsi_sol_delay_burst(struct tegra_dc *dc,
1070                                 struct tegra_dc_dsi_data *dsi)
1071 {
1072         u32 dsi_to_pixel_clk_ratio;
1073         u32 temp;
1074         u32 temp1;
1075         u32 mipi_clk_adj_kHz;
1076         u32 sol_delay;
1077         struct tegra_dc_mode *dc_modes = &dc->mode;
1078
1079         /* Get Fdsi/Fpixel ration (note: Fdsi is in bit format) */
1080         dsi_to_pixel_clk_ratio = (dsi->current_dsi_clk_khz * 2 +
1081                 dsi->default_pixel_clk_khz - 1) / dsi->default_pixel_clk_khz;
1082
1083         /* Convert Fdsi to byte format */
1084         dsi_to_pixel_clk_ratio *= 1000/8;
1085
1086         /* Multiplying by 1000 so that we don't loose the fraction part */
1087         temp = dc_modes->h_active * 1000;
1088         temp1 = dc_modes->h_active + dc_modes->h_back_porch +
1089                         dc_modes->h_sync_width;
1090
1091         sol_delay = temp1 * dsi_to_pixel_clk_ratio -
1092                         temp * dsi->pixel_scaler_mul /
1093                         (dsi->pixel_scaler_div * dsi->info.n_data_lanes);
1094
1095         /* Do rounding on sol delay */
1096         sol_delay = (sol_delay + 1000 - 1)/1000;
1097
1098         /* TODO:
1099          * 1. find out the correct sol fifo depth to use
1100          * 2. verify with hw about the clamping function
1101          */
1102         if (sol_delay > (480 * 4)) {
1103                 sol_delay = (480 * 4);
1104                 mipi_clk_adj_kHz = sol_delay +
1105                         (dc_modes->h_active * dsi->pixel_scaler_mul) /
1106                         (dsi->info.n_data_lanes * dsi->pixel_scaler_div);
1107
1108                 mipi_clk_adj_kHz *= (dsi->default_pixel_clk_khz / temp1);
1109
1110                 mipi_clk_adj_kHz *= 4;
1111         }
1112
1113         dsi->target_hs_clk_khz = mipi_clk_adj_kHz;
1114
1115         return sol_delay;
1116 }
1117
1118 static void tegra_dsi_set_sol_delay(struct tegra_dc *dc,
1119                                 struct tegra_dc_dsi_data *dsi)
1120 {
1121         u32 sol_delay;
1122
1123         if (dsi->info.video_burst_mode == TEGRA_DSI_VIDEO_NONE_BURST_MODE ||
1124                 dsi->info.video_burst_mode ==
1125                                 TEGRA_DSI_VIDEO_NONE_BURST_MODE_WITH_SYNC_END) {
1126 #define VIDEO_FIFO_LATENCY_PIXEL_CLK 8
1127                 sol_delay = VIDEO_FIFO_LATENCY_PIXEL_CLK *
1128                         dsi->pixel_scaler_mul / dsi->pixel_scaler_div;
1129 #undef VIDEO_FIFO_LATENCY_PIXEL_CLK
1130                 dsi->status.clk_burst = DSI_CLK_BURST_NONE_BURST;
1131         } else {
1132                 sol_delay = tegra_dsi_sol_delay_burst(dc, dsi);
1133                 dsi->status.clk_burst = DSI_CLK_BURST_BURST_MODE;
1134         }
1135
1136         tegra_dsi_writel(dsi, DSI_SOL_DELAY_SOL_DELAY(sol_delay),
1137                                                                 DSI_SOL_DELAY);
1138 }
1139
1140 static void tegra_dsi_set_timeout(struct tegra_dc_dsi_data *dsi)
1141 {
1142         u32 val;
1143         u32 bytes_per_frame;
1144         u32 timeout = 0;
1145
1146         /* TODO: verify the following equation */
1147         bytes_per_frame = dsi->current_dsi_clk_khz * 1000 * 2 /
1148                                                 (dsi->info.refresh_rate * 8);
1149         timeout = bytes_per_frame / DSI_CYCLE_COUNTER_VALUE;
1150         timeout = (timeout + DSI_HTX_TO_MARGIN) & 0xffff;
1151
1152         val = DSI_TIMEOUT_0_LRXH_TO(DSI_LRXH_TO_VALUE) |
1153                         DSI_TIMEOUT_0_HTX_TO(timeout);
1154         tegra_dsi_writel(dsi, val, DSI_TIMEOUT_0);
1155
1156         if (dsi->info.panel_reset_timeout_msec)
1157                 timeout = (dsi->info.panel_reset_timeout_msec * 1000*1000)
1158                                         / dsi->current_bit_clk_ns;
1159         else
1160                 timeout = DSI_PR_TO_VALUE;
1161
1162         val = DSI_TIMEOUT_1_PR_TO(timeout) |
1163                 DSI_TIMEOUT_1_TA_TO(DSI_TA_TO_VALUE);
1164         tegra_dsi_writel(dsi, val, DSI_TIMEOUT_1);
1165
1166         val = DSI_TO_TALLY_P_RESET_STATUS(IN_RESET) |
1167                 DSI_TO_TALLY_TA_TALLY(DSI_TA_TALLY_VALUE)|
1168                 DSI_TO_TALLY_LRXH_TALLY(DSI_LRXH_TALLY_VALUE)|
1169                 DSI_TO_TALLY_HTX_TALLY(DSI_HTX_TALLY_VALUE);
1170         tegra_dsi_writel(dsi, val, DSI_TO_TALLY);
1171 }
1172
1173 static void tegra_dsi_setup_video_mode_pkt_length(struct tegra_dc *dc,
1174                                                 struct tegra_dc_dsi_data *dsi)
1175 {
1176         u32 val;
1177         u32 hact_pkt_len;
1178         u32 hsa_pkt_len;
1179         u32 hbp_pkt_len;
1180         u32 hfp_pkt_len;
1181
1182         hact_pkt_len = dc->mode.h_active * dsi->pixel_scaler_mul /
1183                                                         dsi->pixel_scaler_div;
1184         hsa_pkt_len = dc->mode.h_sync_width * dsi->pixel_scaler_mul /
1185                                                         dsi->pixel_scaler_div;
1186         hbp_pkt_len = dc->mode.h_back_porch * dsi->pixel_scaler_mul /
1187                                                         dsi->pixel_scaler_div;
1188         hfp_pkt_len = dc->mode.h_front_porch * dsi->pixel_scaler_mul /
1189                                                         dsi->pixel_scaler_div;
1190
1191         if (dsi->info.video_burst_mode !=
1192                                 TEGRA_DSI_VIDEO_NONE_BURST_MODE_WITH_SYNC_END)
1193                 hbp_pkt_len += hsa_pkt_len;
1194
1195         hsa_pkt_len -= DSI_HSYNC_BLNK_PKT_OVERHEAD;
1196         hbp_pkt_len -= DSI_HBACK_PORCH_PKT_OVERHEAD;
1197         hfp_pkt_len -= DSI_HFRONT_PORCH_PKT_OVERHEAD;
1198
1199         val = DSI_PKT_LEN_0_1_LENGTH_0(0) |
1200                         DSI_PKT_LEN_0_1_LENGTH_1(hsa_pkt_len);
1201         tegra_dsi_writel(dsi, val, DSI_PKT_LEN_0_1);
1202
1203         val = DSI_PKT_LEN_2_3_LENGTH_2(hbp_pkt_len) |
1204                         DSI_PKT_LEN_2_3_LENGTH_3(hact_pkt_len);
1205         tegra_dsi_writel(dsi, val, DSI_PKT_LEN_2_3);
1206
1207         val = DSI_PKT_LEN_4_5_LENGTH_4(hfp_pkt_len) |
1208                         DSI_PKT_LEN_4_5_LENGTH_5(0);
1209         tegra_dsi_writel(dsi, val, DSI_PKT_LEN_4_5);
1210
1211         val = DSI_PKT_LEN_6_7_LENGTH_6(0) | DSI_PKT_LEN_6_7_LENGTH_7(0);
1212         tegra_dsi_writel(dsi, val, DSI_PKT_LEN_6_7);
1213 }
1214
1215 static void tegra_dsi_setup_cmd_mode_pkt_length(struct tegra_dc *dc,
1216                                                 struct tegra_dc_dsi_data *dsi)
1217 {
1218         unsigned long   val;
1219         unsigned long   act_bytes;
1220
1221         act_bytes = dc->mode.h_active * dsi->pixel_scaler_mul /
1222                         dsi->pixel_scaler_div + 1;
1223
1224         val = DSI_PKT_LEN_0_1_LENGTH_0(0) | DSI_PKT_LEN_0_1_LENGTH_1(0);
1225         tegra_dsi_writel(dsi, val, DSI_PKT_LEN_0_1);
1226
1227         val = DSI_PKT_LEN_2_3_LENGTH_2(0) | DSI_PKT_LEN_2_3_LENGTH_3(act_bytes);
1228         tegra_dsi_writel(dsi, val, DSI_PKT_LEN_2_3);
1229
1230         val = DSI_PKT_LEN_4_5_LENGTH_4(0) | DSI_PKT_LEN_4_5_LENGTH_5(act_bytes);
1231         tegra_dsi_writel(dsi, val, DSI_PKT_LEN_4_5);
1232
1233         val = DSI_PKT_LEN_6_7_LENGTH_6(0) | DSI_PKT_LEN_6_7_LENGTH_7(0x0f0f);
1234         tegra_dsi_writel(dsi, val, DSI_PKT_LEN_6_7);
1235 }
1236
1237 static void tegra_dsi_set_pkt_length(struct tegra_dc *dc,
1238                                 struct tegra_dc_dsi_data *dsi)
1239 {
1240         if (dsi->driven_mode == TEGRA_DSI_DRIVEN_BY_HOST)
1241                 return;
1242
1243         if (dsi->info.video_data_type == TEGRA_DSI_VIDEO_TYPE_VIDEO_MODE)
1244                 tegra_dsi_setup_video_mode_pkt_length(dc, dsi);
1245         else
1246                 tegra_dsi_setup_cmd_mode_pkt_length(dc, dsi);
1247 }
1248
1249 static void tegra_dsi_set_pkt_seq(struct tegra_dc *dc,
1250                                 struct tegra_dc_dsi_data *dsi)
1251 {
1252         const u32 *pkt_seq;
1253         u32 rgb_info;
1254         u32 pkt_seq_3_5_rgb_lo;
1255         u32 pkt_seq_3_5_rgb_hi;
1256         u32     val;
1257         u32 reg;
1258         u8  i;
1259
1260         if (dsi->driven_mode == TEGRA_DSI_DRIVEN_BY_HOST)
1261                 return;
1262
1263         switch (dsi->info.pixel_format) {
1264         case TEGRA_DSI_PIXEL_FORMAT_16BIT_P:
1265                 rgb_info = CMD_RGB_16BPP;
1266                 break;
1267         case TEGRA_DSI_PIXEL_FORMAT_18BIT_P:
1268                 rgb_info = CMD_RGB_18BPP;
1269                 break;
1270         case TEGRA_DSI_PIXEL_FORMAT_18BIT_NP:
1271                 rgb_info = CMD_RGB_18BPPNP;
1272                 break;
1273         case TEGRA_DSI_PIXEL_FORMAT_24BIT_P:
1274         default:
1275                 rgb_info = CMD_RGB_24BPP;
1276                 break;
1277         }
1278
1279         pkt_seq_3_5_rgb_lo = 0;
1280         pkt_seq_3_5_rgb_hi = 0;
1281         if (dsi->info.video_data_type == TEGRA_DSI_VIDEO_TYPE_COMMAND_MODE)
1282                 pkt_seq = dsi_pkt_seq_cmd_mode;
1283         else {
1284                 switch (dsi->info.video_burst_mode) {
1285                 case TEGRA_DSI_VIDEO_BURST_MODE_LOWEST_SPEED:
1286                 case TEGRA_DSI_VIDEO_BURST_MODE_LOW_SPEED:
1287                 case TEGRA_DSI_VIDEO_BURST_MODE_MEDIUM_SPEED:
1288                 case TEGRA_DSI_VIDEO_BURST_MODE_FAST_SPEED:
1289                 case TEGRA_DSI_VIDEO_BURST_MODE_FASTEST_SPEED:
1290                         pkt_seq_3_5_rgb_lo =
1291                                         DSI_PKT_SEQ_3_LO_PKT_32_ID(rgb_info);
1292                         if (!dsi->info.no_pkt_seq_eot)
1293                                 pkt_seq = dsi_pkt_seq_video_burst;
1294                         else
1295                                 pkt_seq = dsi_pkt_seq_video_burst_no_eot;
1296                         break;
1297                 case TEGRA_DSI_VIDEO_NONE_BURST_MODE_WITH_SYNC_END:
1298                         pkt_seq_3_5_rgb_hi =
1299                                         DSI_PKT_SEQ_3_HI_PKT_34_ID(rgb_info);
1300                         pkt_seq = dsi_pkt_seq_video_non_burst_syne;
1301                         break;
1302                 case TEGRA_DSI_VIDEO_NONE_BURST_MODE:
1303                 default:
1304                         pkt_seq_3_5_rgb_lo =
1305                                         DSI_PKT_SEQ_3_LO_PKT_32_ID(rgb_info);
1306                         pkt_seq = dsi_pkt_seq_video_non_burst;
1307                         break;
1308                 }
1309         }
1310
1311         for (i = 0; i < NUMOF_PKT_SEQ; i++) {
1312                 val = pkt_seq[i];
1313                 reg = dsi_pkt_seq_reg[i];
1314                 if ((reg == DSI_PKT_SEQ_3_LO) || (reg == DSI_PKT_SEQ_5_LO))
1315                         val |= pkt_seq_3_5_rgb_lo;
1316                 if ((reg == DSI_PKT_SEQ_3_HI) || (reg == DSI_PKT_SEQ_5_HI))
1317                         val |= pkt_seq_3_5_rgb_hi;
1318                 tegra_dsi_writel(dsi, val, reg);
1319         }
1320 }
1321
1322 static void tegra_dsi_reset_underflow_overflow
1323                                 (struct tegra_dc_dsi_data *dsi)
1324 {
1325         u32 val;
1326
1327         val = tegra_dsi_readl(dsi, DSI_STATUS);
1328         val &= (DSI_STATUS_LB_OVERFLOW(0x1) | DSI_STATUS_LB_UNDERFLOW(0x1));
1329         if (val) {
1330                 if (val & DSI_STATUS_LB_OVERFLOW(0x1))
1331                         dev_warn(&dsi->dc->ndev->dev,
1332                                 "dsi: video fifo overflow. Resetting flag\n");
1333                 if (val & DSI_STATUS_LB_UNDERFLOW(0x1))
1334                         dev_warn(&dsi->dc->ndev->dev,
1335                                 "dsi: video fifo underflow. Resetting flag\n");
1336                 val = tegra_dsi_readl(dsi, DSI_HOST_DSI_CONTROL);
1337                 val |= DSI_HOST_CONTROL_FIFO_STAT_RESET(0x1);
1338                 tegra_dsi_writel(dsi, val, DSI_HOST_DSI_CONTROL);
1339                 udelay(5);
1340         }
1341 }
1342
1343 static void tegra_dsi_stop_dc_stream(struct tegra_dc *dc,
1344                                         struct tegra_dc_dsi_data *dsi)
1345 {
1346         tegra_dc_writel(dc, DISP_CTRL_MODE_STOP, DC_CMD_DISPLAY_COMMAND);
1347         tegra_dc_writel(dc, 0, DC_DISP_DISP_WIN_OPTIONS);
1348         tegra_dc_writel(dc, GENERAL_UPDATE, DC_CMD_STATE_CONTROL);
1349         tegra_dc_writel(dc, GENERAL_ACT_REQ , DC_CMD_STATE_CONTROL);
1350
1351         dsi->status.dc_stream = DSI_DC_STREAM_DISABLE;
1352 }
1353
1354 static void tegra_dsi_stop_dc_stream_at_frame_end(struct tegra_dc *dc,
1355                                                 struct tegra_dc_dsi_data *dsi)
1356 {
1357         int val;
1358         long timeout;
1359         u32 frame_period = DIV_ROUND_UP(S_TO_MS(1), dsi->info.refresh_rate);
1360
1361         /* stop dc */
1362         tegra_dsi_stop_dc_stream(dc, dsi);
1363
1364         /* enable frame end interrupt */
1365         val = tegra_dc_readl(dc, DC_CMD_INT_MASK);
1366         val |= FRAME_END_INT;
1367         tegra_dc_writel(dc, val, DC_CMD_INT_MASK);
1368
1369         /* wait for frame_end completion.
1370          * timeout is 2 frame duration to accomodate for
1371          * internal delay.
1372          */
1373         timeout = wait_for_completion_interruptible_timeout(
1374                         &dc->frame_end_complete,
1375                         msecs_to_jiffies(2 * frame_period));
1376
1377         /* disable frame end interrupt */
1378         val = tegra_dc_readl(dc, DC_CMD_INT_MASK);
1379         val &= ~FRAME_END_INT;
1380         tegra_dc_writel(dc, val, DC_CMD_INT_MASK);
1381
1382         if (timeout == 0)
1383                 dev_warn(&dc->ndev->dev,
1384                         "DC doesn't stop at end of frame.\n");
1385
1386         tegra_dsi_reset_underflow_overflow(dsi);
1387 }
1388
1389 static void tegra_dsi_start_dc_stream(struct tegra_dc *dc,
1390                                         struct tegra_dc_dsi_data *dsi)
1391 {
1392         u32 val;
1393
1394         tegra_dc_writel(dc, DSI_ENABLE, DC_DISP_DISP_WIN_OPTIONS);
1395
1396         /* TODO: clean up */
1397         tegra_dc_writel(dc, PW0_ENABLE | PW1_ENABLE | PW2_ENABLE | PW3_ENABLE |
1398                         PW4_ENABLE | PM0_ENABLE | PM1_ENABLE,
1399                         DC_CMD_DISPLAY_POWER_CONTROL);
1400
1401         /* Configure one-shot mode or continuous mode */
1402         if (dc->out->flags & TEGRA_DC_OUT_ONE_SHOT_MODE) {
1403                 /* disable LSPI/LCD_DE output */
1404                 val = PIN_OUTPUT_LSPI_OUTPUT_DIS;
1405                 tegra_dc_writel(dc, val, DC_COM_PIN_OUTPUT_ENABLE3);
1406
1407                 /* enable MSF & set MSF polarity */
1408                 val = MSF_ENABLE | MSF_LSPI;
1409                 if (!dsi->info.te_polarity_low)
1410                         val |= MSF_POLARITY_HIGH;
1411                 else
1412                         val |= MSF_POLARITY_LOW;
1413                 tegra_dc_writel(dc, val, DC_CMD_DISPLAY_COMMAND_OPTION0);
1414
1415                 /* set non-continuous mode */
1416                 tegra_dc_writel(dc, DISP_CTRL_MODE_NC_DISPLAY,
1417                                                 DC_CMD_DISPLAY_COMMAND);
1418                 tegra_dc_writel(dc, GENERAL_UPDATE, DC_CMD_STATE_CONTROL);
1419                 tegra_dc_writel(dc, GENERAL_ACT_REQ | NC_HOST_TRIG,
1420                                                 DC_CMD_STATE_CONTROL);
1421         } else {
1422                 /* set continuous mode */
1423                 tegra_dc_writel(dc, DISP_CTRL_MODE_C_DISPLAY,
1424                                                 DC_CMD_DISPLAY_COMMAND);
1425                 tegra_dc_writel(dc, GENERAL_UPDATE, DC_CMD_STATE_CONTROL);
1426                 tegra_dc_writel(dc, GENERAL_ACT_REQ, DC_CMD_STATE_CONTROL);
1427         }
1428
1429         dsi->status.dc_stream = DSI_DC_STREAM_ENABLE;
1430 }
1431
1432 static void tegra_dsi_set_dc_clk(struct tegra_dc *dc,
1433                                 struct tegra_dc_dsi_data *dsi)
1434 {
1435         u32 shift_clk_div_register;
1436         u32 val;
1437
1438         /* Get the corresponding register value of shift_clk_div. */
1439         shift_clk_div_register = dsi->shift_clk_div * 2 - 2;
1440
1441 #ifndef CONFIG_TEGRA_SILICON_PLATFORM
1442         shift_clk_div_register = 1;
1443 #endif
1444
1445         /* TODO: find out if PCD3 option is required */
1446         val = PIXEL_CLK_DIVIDER_PCD1 |
1447                 SHIFT_CLK_DIVIDER(shift_clk_div_register);
1448         tegra_dc_writel(dc, val, DC_DISP_DISP_CLOCK_CONTROL);
1449 }
1450
1451 static void tegra_dsi_set_dsi_clk(struct tegra_dc *dc,
1452                         struct tegra_dc_dsi_data *dsi, u32 clk)
1453 {
1454         u32 rm;
1455
1456         /* Round up to MHz */
1457         rm = clk % 1000;
1458         if (rm != 0)
1459                 clk -= rm;
1460
1461         /* Set up pixel clock */
1462         dc->shift_clk_div = dsi->shift_clk_div;
1463         dc->mode.pclk = (clk * 1000) / dsi->shift_clk_div;
1464         /* TODO: Define one shot work delay in board file. */
1465         /* Since for one-shot mode, refresh rate is usually set larger than
1466          * expected refresh rate, it needs at least 3 frame period. Less
1467          * delay one shot work is, more powering saving we have. */
1468         dc->one_shot_delay_ms = 4 *
1469                         DIV_ROUND_UP(S_TO_MS(1), dsi->info.refresh_rate);
1470
1471         /* Enable DSI clock */
1472         tegra_dc_setup_clk(dc, dsi->dsi_clk);
1473         tegra_dsi_clk_enable(dsi);
1474         tegra_periph_reset_deassert(dsi->dsi_clk);
1475
1476         dsi->current_dsi_clk_khz = clk_get_rate(dsi->dsi_clk) / 1000;
1477         dsi->current_bit_clk_ns =  1000*1000 / (dsi->current_dsi_clk_khz * 2);
1478 }
1479
1480 static void tegra_dsi_hs_clk_out_enable(struct tegra_dc_dsi_data *dsi)
1481 {
1482         u32 val;
1483
1484         val = tegra_dsi_readl(dsi, DSI_CONTROL);
1485         val &= ~DSI_CONTROL_HS_CLK_CTRL(1);
1486
1487         if (dsi->info.video_clock_mode == TEGRA_DSI_VIDEO_CLOCK_CONTINUOUS) {
1488                 val |= DSI_CONTROL_HS_CLK_CTRL(CONTINUOUS);
1489                 dsi->status.clk_mode = DSI_PHYCLK_CONTINUOUS;
1490         } else {
1491                 val |= DSI_CONTROL_HS_CLK_CTRL(TX_ONLY);
1492                 dsi->status.clk_mode = DSI_PHYCLK_TX_ONLY;
1493         }
1494         tegra_dsi_writel(dsi, val, DSI_CONTROL);
1495
1496         val = tegra_dsi_readl(dsi, DSI_HOST_DSI_CONTROL);
1497         val &= ~DSI_HOST_DSI_CONTROL_HIGH_SPEED_TRANS(1);
1498         val |= DSI_HOST_DSI_CONTROL_HIGH_SPEED_TRANS(TEGRA_DSI_HIGH);
1499         tegra_dsi_writel(dsi, val, DSI_HOST_DSI_CONTROL);
1500
1501         dsi->status.clk_out = DSI_PHYCLK_OUT_EN;
1502 }
1503
1504 static void tegra_dsi_hs_clk_out_enable_in_lp(struct tegra_dc_dsi_data *dsi)
1505 {
1506         u32 val;
1507         tegra_dsi_hs_clk_out_enable(dsi);
1508
1509         val = tegra_dsi_readl(dsi, DSI_HOST_DSI_CONTROL);
1510         val &= ~DSI_HOST_DSI_CONTROL_HIGH_SPEED_TRANS(1);
1511         val |= DSI_HOST_DSI_CONTROL_HIGH_SPEED_TRANS(TEGRA_DSI_LOW);
1512         tegra_dsi_writel(dsi, val, DSI_HOST_DSI_CONTROL);
1513 }
1514
1515 static void tegra_dsi_hs_clk_out_disable(struct tegra_dc *dc,
1516                                                 struct tegra_dc_dsi_data *dsi)
1517 {
1518         u32 val;
1519
1520         if (dsi->status.dc_stream == DSI_DC_STREAM_ENABLE)
1521                 tegra_dsi_stop_dc_stream_at_frame_end(dc, dsi);
1522
1523         tegra_dsi_writel(dsi, TEGRA_DSI_DISABLE, DSI_POWER_CONTROL);
1524         /* stabilization delay */
1525         udelay(300);
1526
1527         val = tegra_dsi_readl(dsi, DSI_HOST_DSI_CONTROL);
1528         val &= ~DSI_HOST_DSI_CONTROL_HIGH_SPEED_TRANS(1);
1529         val |= DSI_HOST_DSI_CONTROL_HIGH_SPEED_TRANS(TEGRA_DSI_LOW);
1530         tegra_dsi_writel(dsi, val, DSI_HOST_DSI_CONTROL);
1531
1532         tegra_dsi_writel(dsi, TEGRA_DSI_ENABLE, DSI_POWER_CONTROL);
1533         /* stabilization delay */
1534         udelay(300);
1535
1536         dsi->status.clk_mode = DSI_PHYCLK_NOT_INIT;
1537         dsi->status.clk_out = DSI_PHYCLK_OUT_DIS;
1538 }
1539
1540 static void tegra_dsi_set_control_reg_lp(struct tegra_dc_dsi_data *dsi)
1541 {
1542         u32 dsi_control;
1543         u32 host_dsi_control;
1544         u32 max_threshold;
1545
1546         dsi_control = dsi->dsi_control_val | DSI_CTRL_HOST_DRIVEN;
1547         host_dsi_control = HOST_DSI_CTRL_COMMON |
1548                         HOST_DSI_CTRL_HOST_DRIVEN |
1549                         DSI_HOST_DSI_CONTROL_HIGH_SPEED_TRANS(TEGRA_DSI_LOW);
1550         max_threshold = DSI_MAX_THRESHOLD_MAX_THRESHOLD(DSI_HOST_FIFO_DEPTH);
1551
1552         tegra_dsi_writel(dsi, max_threshold, DSI_MAX_THRESHOLD);
1553         tegra_dsi_writel(dsi, dsi_control, DSI_CONTROL);
1554         tegra_dsi_writel(dsi, host_dsi_control, DSI_HOST_DSI_CONTROL);
1555
1556         dsi->status.driven = DSI_DRIVEN_MODE_HOST;
1557         dsi->status.clk_burst = DSI_CLK_BURST_NOT_INIT;
1558         dsi->status.vtype = DSI_VIDEO_TYPE_NOT_INIT;
1559 }
1560
1561 static void tegra_dsi_set_control_reg_hs(struct tegra_dc_dsi_data *dsi)
1562 {
1563         u32 dsi_control;
1564         u32 host_dsi_control;
1565         u32 max_threshold;
1566         u32 dcs_cmd;
1567
1568         dsi_control = dsi->dsi_control_val;
1569         host_dsi_control = HOST_DSI_CTRL_COMMON;
1570         max_threshold = 0;
1571         dcs_cmd = 0;
1572
1573         if (dsi->driven_mode == TEGRA_DSI_DRIVEN_BY_HOST) {
1574                 dsi_control |= DSI_CTRL_HOST_DRIVEN;
1575                 host_dsi_control |= HOST_DSI_CTRL_HOST_DRIVEN;
1576                 max_threshold =
1577                         DSI_MAX_THRESHOLD_MAX_THRESHOLD(DSI_HOST_FIFO_DEPTH);
1578                 dsi->status.driven = DSI_DRIVEN_MODE_HOST;
1579         } else {
1580                 dsi_control |= DSI_CTRL_DC_DRIVEN;
1581                 host_dsi_control |= HOST_DSI_CTRL_DC_DRIVEN;
1582                 max_threshold =
1583                         DSI_MAX_THRESHOLD_MAX_THRESHOLD(DSI_VIDEO_FIFO_DEPTH);
1584                 dsi->status.driven = DSI_DRIVEN_MODE_DC;
1585         }
1586
1587         if (dsi->info.video_data_type == TEGRA_DSI_VIDEO_TYPE_COMMAND_MODE) {
1588                 dsi_control |= DSI_CTRL_CMD_MODE;
1589                 dcs_cmd = DSI_DCS_CMDS_LT5_DCS_CMD(DSI_WRITE_MEMORY_START)|
1590                         DSI_DCS_CMDS_LT3_DCS_CMD(DSI_WRITE_MEMORY_CONTINUE);
1591                 dsi->status.vtype = DSI_VIDEO_TYPE_CMD_MODE;
1592
1593         } else {
1594                 dsi_control |= DSI_CTRL_VIDEO_MODE;
1595                 dsi->status.vtype = DSI_VIDEO_TYPE_VIDEO_MODE;
1596         }
1597
1598         tegra_dsi_writel(dsi, max_threshold, DSI_MAX_THRESHOLD);
1599         tegra_dsi_writel(dsi, dcs_cmd, DSI_DCS_CMDS);
1600         tegra_dsi_writel(dsi, dsi_control, DSI_CONTROL);
1601         tegra_dsi_writel(dsi, host_dsi_control, DSI_HOST_DSI_CONTROL);
1602 }
1603
1604 static void tegra_dsi_pad_calibration(struct tegra_dc_dsi_data *dsi)
1605 {
1606         u32 val;
1607
1608         val =   DSI_PAD_CONTROL_PAD_LPUPADJ(0x1) |
1609                 DSI_PAD_CONTROL_PAD_LPDNADJ(0x1) |
1610                 DSI_PAD_CONTROL_PAD_PREEMP_EN(0x1) |
1611                 DSI_PAD_CONTROL_PAD_SLEWDNADJ(0x6) |
1612                 DSI_PAD_CONTROL_PAD_SLEWUPADJ(0x6);
1613         if (!dsi->ulpm) {
1614                 val |=  DSI_PAD_CONTROL_PAD_PDIO(0) |
1615                         DSI_PAD_CONTROL_PAD_PDIO_CLK(0) |
1616                         DSI_PAD_CONTROL_PAD_PULLDN_ENAB(TEGRA_DSI_DISABLE);
1617         } else {
1618                 val |=  DSI_PAD_CONTROL_PAD_PDIO(0x3) |
1619                         DSI_PAD_CONTROL_PAD_PDIO_CLK(0x1) |
1620                         DSI_PAD_CONTROL_PAD_PULLDN_ENAB(TEGRA_DSI_ENABLE);
1621         }
1622         tegra_dsi_writel(dsi, val, DSI_PAD_CONTROL);
1623
1624         val = MIPI_CAL_TERMOSA(0x4);
1625         tegra_vi_csi_writel(val, CSI_CILA_MIPI_CAL_CONFIG_0);
1626
1627         val = MIPI_CAL_TERMOSB(0x4);
1628         tegra_vi_csi_writel(val, CSI_CILB_MIPI_CAL_CONFIG_0);
1629
1630         val = MIPI_CAL_HSPUOSD(0x3) | MIPI_CAL_HSPDOSD(0x4);
1631         tegra_vi_csi_writel(val, CSI_DSI_MIPI_CAL_CONFIG);
1632
1633         val = PAD_DRIV_DN_REF(0x5) | PAD_DRIV_UP_REF(0x7);
1634         tegra_vi_csi_writel(val, CSI_MIPIBIAS_PAD_CONFIG);
1635
1636         val = PAD_CIL_PDVREG(0x0);
1637         tegra_vi_csi_writel(val, CSI_CIL_PAD_CONFIG);
1638 }
1639
1640 static void tegra_dsi_panelB_enable(void)
1641 {
1642         unsigned int val;
1643
1644         val = readl(IO_ADDRESS(APB_MISC_GP_MIPI_PAD_CTRL_0));
1645         val |= DSIB_MODE_ENABLE;
1646         writel(val, (IO_ADDRESS(APB_MISC_GP_MIPI_PAD_CTRL_0)));
1647 }
1648
1649 static int tegra_dsi_init_hw(struct tegra_dc *dc,
1650                                                 struct tegra_dc_dsi_data *dsi)
1651 {
1652         u32 i;
1653
1654         tegra_dsi_writel(dsi,
1655                 DSI_POWER_CONTROL_LEG_DSI_ENABLE(TEGRA_DSI_DISABLE),
1656                 DSI_POWER_CONTROL);
1657         /* stabilization delay */
1658         udelay(300);
1659
1660         tegra_dsi_set_dsi_clk(dc, dsi, dsi->target_lp_clk_khz);
1661         if (dsi->info.dsi_instance) {
1662                 tegra_dsi_panelB_enable();
1663         }
1664
1665         /* TODO: only need to change the timing for bta */
1666         tegra_dsi_set_phy_timing(dsi, DSI_LPHS_IN_LP_MODE);
1667
1668         if (dsi->status.dc_stream == DSI_DC_STREAM_ENABLE)
1669                 tegra_dsi_stop_dc_stream_at_frame_end(dc, dsi);
1670
1671         /* Initializing DSI registers */
1672         for (i = 0; i < ARRAY_SIZE(init_reg); i++)
1673                 tegra_dsi_writel(dsi, 0, init_reg[i]);
1674
1675         tegra_dsi_writel(dsi, dsi->dsi_control_val, DSI_CONTROL);
1676
1677         tegra_dsi_pad_calibration(dsi);
1678
1679         tegra_dsi_writel(dsi,
1680                 DSI_POWER_CONTROL_LEG_DSI_ENABLE(TEGRA_DSI_ENABLE),
1681                 DSI_POWER_CONTROL);
1682         /* stabilization delay */
1683         udelay(300);
1684
1685         dsi->status.init = DSI_MODULE_INIT;
1686         dsi->status.lphs = DSI_LPHS_NOT_INIT;
1687         dsi->status.vtype = DSI_VIDEO_TYPE_NOT_INIT;
1688         dsi->status.driven = DSI_DRIVEN_MODE_NOT_INIT;
1689         dsi->status.clk_out = DSI_PHYCLK_OUT_DIS;
1690         dsi->status.clk_mode = DSI_PHYCLK_NOT_INIT;
1691         dsi->status.clk_burst = DSI_CLK_BURST_NOT_INIT;
1692         dsi->status.dc_stream = DSI_DC_STREAM_DISABLE;
1693         dsi->status.lp_op = DSI_LP_OP_NOT_INIT;
1694
1695         return 0;
1696 }
1697
1698 static int tegra_dsi_set_to_lp_mode(struct tegra_dc *dc,
1699                         struct tegra_dc_dsi_data *dsi, u8 lp_op)
1700 {
1701         int err;
1702
1703         if (dsi->status.init != DSI_MODULE_INIT) {
1704                 err = -EPERM;
1705                 goto fail;
1706         }
1707
1708         if (dsi->status.lphs == DSI_LPHS_IN_LP_MODE &&
1709                         dsi->status.lp_op == lp_op)
1710                 goto success;
1711
1712         if (dsi->status.dc_stream == DSI_DC_STREAM_ENABLE)
1713                 tegra_dsi_stop_dc_stream_at_frame_end(dc, dsi);
1714
1715         /* disable/enable hs clk according to enable_hs_clock_on_lp_cmd_mode */
1716         if ((dsi->status.clk_out == DSI_PHYCLK_OUT_EN) &&
1717                 (!dsi->info.enable_hs_clock_on_lp_cmd_mode))
1718                 tegra_dsi_hs_clk_out_disable(dc, dsi);
1719
1720         dsi->target_lp_clk_khz = tegra_dsi_get_lp_clk_rate(dsi, lp_op);
1721         if (dsi->current_dsi_clk_khz != dsi->target_lp_clk_khz) {
1722                 tegra_dsi_set_dsi_clk(dc, dsi, dsi->target_lp_clk_khz);
1723                 tegra_dsi_set_timeout(dsi);
1724         }
1725
1726         tegra_dsi_set_phy_timing(dsi, DSI_LPHS_IN_LP_MODE);
1727
1728         tegra_dsi_set_control_reg_lp(dsi);
1729
1730         if ((dsi->status.clk_out == DSI_PHYCLK_OUT_DIS) &&
1731                 (dsi->info.enable_hs_clock_on_lp_cmd_mode))
1732                 tegra_dsi_hs_clk_out_enable_in_lp(dsi);
1733
1734         dsi->status.lphs = DSI_LPHS_IN_LP_MODE;
1735         dsi->status.lp_op = lp_op;
1736 success:
1737         err = 0;
1738 fail:
1739         return err;
1740 }
1741
1742 static int tegra_dsi_set_to_hs_mode(struct tegra_dc *dc,
1743                                         struct tegra_dc_dsi_data *dsi)
1744 {
1745         int err;
1746
1747         if (dsi->status.init != DSI_MODULE_INIT) {
1748                 err = -EPERM;
1749                 goto fail;
1750         }
1751
1752         if (dsi->status.lphs == DSI_LPHS_IN_HS_MODE)
1753                 goto success;
1754
1755         if (dsi->status.dc_stream == DSI_DC_STREAM_ENABLE)
1756                 tegra_dsi_stop_dc_stream_at_frame_end(dc, dsi);
1757
1758         if ((dsi->status.clk_out == DSI_PHYCLK_OUT_EN) &&
1759                 (!dsi->info.enable_hs_clock_on_lp_cmd_mode))
1760                 tegra_dsi_hs_clk_out_disable(dc, dsi);
1761
1762         if (dsi->current_dsi_clk_khz != dsi->target_hs_clk_khz) {
1763                 tegra_dsi_set_dsi_clk(dc, dsi, dsi->target_hs_clk_khz);
1764                 tegra_dsi_set_timeout(dsi);
1765         }
1766
1767         tegra_dsi_set_phy_timing(dsi, DSI_LPHS_IN_HS_MODE);
1768
1769         if (dsi->driven_mode == TEGRA_DSI_DRIVEN_BY_DC) {
1770                 tegra_dsi_set_pkt_seq(dc, dsi);
1771                 tegra_dsi_set_pkt_length(dc, dsi);
1772                 tegra_dsi_set_sol_delay(dc, dsi);
1773                 tegra_dsi_set_dc_clk(dc, dsi);
1774         }
1775
1776         tegra_dsi_set_control_reg_hs(dsi);
1777
1778         if (dsi->status.clk_out == DSI_PHYCLK_OUT_DIS ||
1779                 dsi->info.enable_hs_clock_on_lp_cmd_mode)
1780                 tegra_dsi_hs_clk_out_enable(dsi);
1781
1782         dsi->status.lphs = DSI_LPHS_IN_HS_MODE;
1783 success:
1784         dsi->status.lp_op = DSI_LP_OP_NOT_INIT;
1785         err = 0;
1786 fail:
1787         return err;
1788 }
1789
1790 static bool tegra_dsi_write_busy(struct tegra_dc_dsi_data *dsi)
1791 {
1792         u32 timeout = 0;
1793         bool retVal = true;
1794
1795         while (timeout <= DSI_MAX_COMMAND_DELAY_USEC) {
1796                 if (!(DSI_TRIGGER_HOST_TRIGGER(0x1) &
1797                         tegra_dsi_readl(dsi, DSI_TRIGGER))) {
1798                         retVal = false;
1799                         break;
1800                 }
1801                 udelay(DSI_COMMAND_DELAY_STEPS_USEC);
1802                 timeout += DSI_COMMAND_DELAY_STEPS_USEC;
1803         }
1804
1805         return retVal;
1806 }
1807
1808 static bool tegra_dsi_read_busy(struct tegra_dc_dsi_data *dsi)
1809 {
1810         u32 timeout = 0;
1811         bool retVal = true;
1812
1813         while (timeout <  DSI_STATUS_POLLING_DURATION_USEC) {
1814                 if (!(DSI_HOST_DSI_CONTROL_IMM_BTA(0x1) &
1815                         tegra_dsi_readl(dsi, DSI_HOST_DSI_CONTROL))) {
1816                         retVal = false;
1817                         break;
1818                 }
1819                 udelay(DSI_STATUS_POLLING_DELAY_USEC);
1820                 timeout += DSI_STATUS_POLLING_DELAY_USEC;
1821         }
1822
1823         return retVal;
1824 }
1825
1826 static bool tegra_dsi_host_busy(struct tegra_dc_dsi_data *dsi)
1827 {
1828         int err = 0;
1829
1830         if (tegra_dsi_write_busy(dsi)) {
1831                 err = -EBUSY;
1832                 dev_err(&dsi->dc->ndev->dev,
1833                         "DSI trigger bit already set\n");
1834                 goto fail;
1835         }
1836
1837         if (tegra_dsi_read_busy(dsi)) {
1838                 err = -EBUSY;
1839                 dev_err(&dsi->dc->ndev->dev,
1840                         "DSI immediate bta bit already set\n");
1841                 goto fail;
1842         }
1843 fail:
1844         return (err < 0 ? true : false);
1845 }
1846
1847 static void tegra_dsi_soft_reset(struct tegra_dc_dsi_data *dsi)
1848 {
1849         u32 trigger;
1850         u32 status;
1851
1852         tegra_dsi_writel(dsi,
1853                 DSI_POWER_CONTROL_LEG_DSI_ENABLE(TEGRA_DSI_DISABLE),
1854                 DSI_POWER_CONTROL);
1855         /* stabilization delay */
1856         udelay(300);
1857
1858         tegra_dsi_writel(dsi,
1859                 DSI_POWER_CONTROL_LEG_DSI_ENABLE(TEGRA_DSI_ENABLE),
1860                 DSI_POWER_CONTROL);
1861         /* stabilization delay */
1862         udelay(300);
1863
1864         /* dsi HW does not clear host trigger bit automatically
1865          * on dsi interface disable if host fifo is empty
1866          */
1867         trigger = tegra_dsi_readl(dsi, DSI_TRIGGER);
1868         status = tegra_dsi_readl(dsi, DSI_STATUS);
1869         if (trigger & DSI_TRIGGER_HOST_TRIGGER(0x1) &&
1870                 status & DSI_STATUS_IDLE(0x1)) {
1871                 trigger &= ~(DSI_TRIGGER_HOST_TRIGGER(0x1));
1872                 tegra_dsi_writel(dsi, trigger, DSI_TRIGGER);
1873         }
1874 }
1875
1876 static void tegra_dsi_reset_read_count(struct tegra_dc_dsi_data *dsi)
1877 {
1878         u32 val;
1879
1880         val = tegra_dsi_readl(dsi, DSI_STATUS);
1881         val &= DSI_STATUS_RD_FIFO_COUNT(0x1f);
1882         if (val) {
1883                 dev_warn(&dsi->dc->ndev->dev,
1884                         "DSI read count not zero, resetting\n");
1885                 tegra_dsi_soft_reset(dsi);
1886         }
1887 }
1888
1889 static struct dsi_status *tegra_dsi_save_state_switch_to_host_cmd_mode(
1890                                                 struct tegra_dc_dsi_data *dsi,
1891                                                 struct tegra_dc *dc,
1892                                                 u8 lp_op)
1893 {
1894         struct dsi_status *init_status;
1895         int err;
1896
1897         init_status = kzalloc(sizeof(*init_status), GFP_KERNEL);
1898         if (!init_status)
1899                 return ERR_PTR(-ENOMEM);
1900
1901         *init_status = dsi->status;
1902
1903         if (dsi->status.lphs == DSI_LPHS_IN_HS_MODE) {
1904                 if (dsi->status.driven == DSI_DRIVEN_MODE_DC) {
1905                         if (dsi->status.dc_stream == DSI_DC_STREAM_ENABLE)
1906                                 tegra_dsi_stop_dc_stream_at_frame_end(dc, dsi);
1907                         dsi->driven_mode = TEGRA_DSI_DRIVEN_BY_HOST;
1908                         if (dsi->info.hs_cmd_mode_supported) {
1909                                 err = tegra_dsi_set_to_hs_mode(dc, dsi);
1910                                 if (err < 0) {
1911                                         dev_err(&dc->ndev->dev,
1912                                         "Switch to HS host mode failed\n");
1913                                         goto fail;
1914                                 }
1915                         }
1916                 }
1917                 if (!dsi->info.hs_cmd_mode_supported) {
1918                         err =
1919                         tegra_dsi_set_to_lp_mode(dc, dsi, lp_op);
1920                         if (err < 0) {
1921                                 dev_err(&dc->ndev->dev,
1922                                 "DSI failed to go to LP mode\n");
1923                                 goto fail;
1924                         }
1925                 }
1926         } else if (dsi->status.lphs == DSI_LPHS_IN_LP_MODE) {
1927                 if (dsi->status.lp_op != lp_op) {
1928                         err = tegra_dsi_set_to_lp_mode(dc, dsi, lp_op);
1929                         if (err < 0) {
1930                                 dev_err(&dc->ndev->dev,
1931                                 "DSI failed to go to LP mode\n");
1932                                 goto fail;
1933                         }
1934                 }
1935         }
1936
1937         return init_status;
1938 fail:
1939         kfree(init_status);
1940         return ERR_PTR(err);
1941 }
1942
1943 static struct dsi_status *tegra_dsi_prepare_host_transmission(
1944                                 struct tegra_dc *dc,
1945                                 struct tegra_dc_dsi_data *dsi,
1946                                 u8 lp_op)
1947 {
1948         int err = 0;
1949         struct dsi_status *init_status;
1950
1951         if (dsi->status.init != DSI_MODULE_INIT ||
1952                 dsi->ulpm) {
1953                 err = -EPERM;
1954                 goto fail;
1955         }
1956
1957         if (tegra_dsi_host_busy(dsi)) {
1958                 tegra_dsi_soft_reset(dsi);
1959
1960                 /* WAR to stop host write in middle */
1961                 tegra_dsi_writel(dsi, TEGRA_DSI_DISABLE, DSI_TRIGGER);
1962
1963                 if (tegra_dsi_host_busy(dsi)) {
1964                         err = -EBUSY;
1965                         dev_err(&dc->ndev->dev, "DSI host busy\n");
1966                         goto fail;
1967                 }
1968         }
1969
1970         if (lp_op == DSI_LP_OP_READ)
1971                 tegra_dsi_reset_read_count(dsi);
1972
1973         if (dsi->status.lphs == DSI_LPHS_NOT_INIT) {
1974                 err = tegra_dsi_set_to_lp_mode(dc, dsi, lp_op);
1975                 if (err < 0) {
1976                         dev_err(&dc->ndev->dev, "Failed to config LP write\n");
1977                         goto fail;
1978                 }
1979         }
1980
1981         init_status = tegra_dsi_save_state_switch_to_host_cmd_mode
1982                                         (dsi, dc, lp_op);
1983         if (IS_ERR_OR_NULL(init_status)) {
1984                 err = PTR_ERR(init_status);
1985                 dev_err(&dc->ndev->dev, "DSI state saving failed\n");
1986                 goto fail;
1987         }
1988
1989         return init_status;
1990 fail:
1991         return ERR_PTR(err);
1992 }
1993
1994 static int tegra_dsi_restore_state(struct tegra_dc *dc,
1995                                 struct tegra_dc_dsi_data *dsi,
1996                                 struct dsi_status *init_status)
1997 {
1998         bool switch_back_to_dc_mode = false;
1999         bool switch_back_to_hs_mode = false;
2000         bool restart_dc_stream;
2001         int err = 0;
2002
2003         switch_back_to_dc_mode = (dsi->status.driven ==
2004                                 DSI_DRIVEN_MODE_HOST &&
2005                                 init_status->driven ==
2006                                 DSI_DRIVEN_MODE_DC);
2007         switch_back_to_hs_mode = (dsi->status.lphs ==
2008                                 DSI_LPHS_IN_LP_MODE &&
2009                                 init_status->lphs ==
2010                                 DSI_LPHS_IN_HS_MODE);
2011         restart_dc_stream = (dsi->status.dc_stream ==
2012                                 DSI_DC_STREAM_DISABLE &&
2013                                 init_status->dc_stream ==
2014                                 DSI_DC_STREAM_ENABLE);
2015
2016         if (dsi->status.lphs == DSI_LPHS_IN_LP_MODE &&
2017                 init_status->lphs == DSI_LPHS_IN_LP_MODE) {
2018                 if (dsi->status.lp_op != init_status->lp_op) {
2019                         err =
2020                         tegra_dsi_set_to_lp_mode(dc, dsi, init_status->lp_op);
2021                         if (err < 0) {
2022                                 dev_err(&dc->ndev->dev,
2023                                         "Failed to config LP mode\n");
2024                                 goto fail;
2025                         }
2026                 }
2027                 goto success;
2028         }
2029
2030         if (switch_back_to_dc_mode)
2031                 dsi->driven_mode = TEGRA_DSI_DRIVEN_BY_DC;
2032         if (switch_back_to_dc_mode || switch_back_to_hs_mode) {
2033                 err = tegra_dsi_set_to_hs_mode(dc, dsi);
2034                 if (err < 0) {
2035                         dev_err(&dc->ndev->dev, "Failed to config HS mode\n");
2036                         goto fail;
2037                 }
2038         }
2039         if (restart_dc_stream)
2040                 tegra_dsi_start_dc_stream(dc, dsi);
2041
2042 success:
2043 fail:
2044         kfree(init_status);
2045         return err;
2046 }
2047
2048 static int tegra_dsi_host_trigger(struct tegra_dc_dsi_data *dsi)
2049 {
2050         int status = 0;
2051
2052         if (tegra_dsi_readl(dsi, DSI_TRIGGER)) {
2053                 status = -EBUSY;
2054                 goto fail;
2055         }
2056
2057         tegra_dsi_writel(dsi,
2058                 DSI_TRIGGER_HOST_TRIGGER(TEGRA_DSI_ENABLE), DSI_TRIGGER);
2059
2060 #if DSI_USE_SYNC_POINTS
2061         status = tegra_dsi_syncpt(dsi);
2062         if (status < 0) {
2063                 dev_err(&dsi->dc->ndev->dev,
2064                         "DSI syncpt for host trigger failed\n");
2065                 goto fail;
2066         }
2067 #else
2068         if (tegra_dsi_write_busy(dsi)) {
2069                 status = -EBUSY;
2070                 dev_err(&dsi->dc->ndev->dev,
2071                         "Timeout waiting on write completion\n");
2072         }
2073 #endif
2074
2075 fail:
2076         return status;
2077 }
2078
2079 static int _tegra_dsi_write_data(struct tegra_dc_dsi_data *dsi,
2080                                         u8 *pdata, u8 data_id, u16 data_len)
2081 {
2082         u8 virtual_channel;
2083         u8 *pval;
2084         u32 val;
2085         int err;
2086
2087         err = 0;
2088
2089         virtual_channel = dsi->info.virtual_channel <<
2090                                                 DSI_VIR_CHANNEL_BIT_POSITION;
2091
2092         /* always use hw for ecc */
2093         val = (virtual_channel | data_id) << 0 |
2094                         data_len << 8;
2095         tegra_dsi_writel(dsi, val, DSI_WR_DATA);
2096
2097         /* if pdata != NULL, pkt type is long pkt */
2098         if (pdata != NULL) {
2099                 while (data_len) {
2100                         if (data_len >= 4) {
2101                                 val = ((u32 *) pdata)[0];
2102                                 data_len -= 4;
2103                                 pdata += 4;
2104                         } else {
2105                                 val = 0;
2106                                 pval = (u8 *) &val;
2107                                 do
2108                                         *pval++ = *pdata++;
2109                                 while (--data_len);
2110                         }
2111                         tegra_dsi_writel(dsi, val, DSI_WR_DATA);
2112                 }
2113         }
2114
2115         err = tegra_dsi_host_trigger(dsi);
2116         if (err < 0)
2117                 dev_err(&dsi->dc->ndev->dev, "DSI host trigger failed\n");
2118
2119         return err;
2120 }
2121
2122 int tegra_dsi_write_data(struct tegra_dc *dc,
2123                         struct tegra_dc_dsi_data *dsi,
2124                         u8 *pdata, u8 data_id, u16 data_len)
2125 {
2126         int err = 0;
2127         struct dsi_status *init_status;
2128
2129         tegra_dc_io_start(dc);
2130
2131         init_status = tegra_dsi_prepare_host_transmission(
2132                                 dc, dsi, DSI_LP_OP_WRITE);
2133         if (IS_ERR_OR_NULL(init_status)) {
2134                 err = PTR_ERR(init_status);
2135                 dev_err(&dc->ndev->dev, "DSI host config failed\n");
2136                 goto fail;
2137         }
2138
2139         err = _tegra_dsi_write_data(dsi, pdata, data_id, data_len);
2140 fail:
2141         err = tegra_dsi_restore_state(dc, dsi, init_status);
2142         if (err < 0)
2143                 dev_err(&dc->ndev->dev, "Failed to restore prev state\n");
2144         tegra_dc_io_end(dc);
2145         return err;
2146 }
2147 EXPORT_SYMBOL(tegra_dsi_write_data);
2148
2149 static int tegra_dsi_send_panel_cmd(struct tegra_dc *dc,
2150                                         struct tegra_dc_dsi_data *dsi,
2151                                         struct tegra_dsi_cmd *cmd,
2152                                         u32 n_cmd)
2153 {
2154         u32 i;
2155         int err;
2156
2157         err = 0;
2158         for (i = 0; i < n_cmd; i++) {
2159                 struct tegra_dsi_cmd *cur_cmd;
2160                 cur_cmd = &cmd[i];
2161
2162                 if (cur_cmd->cmd_type == TEGRA_DSI_DELAY_MS)
2163                         mdelay(cur_cmd->sp_len_dly.delay_ms);
2164                 else {
2165                         err = tegra_dsi_write_data(dc, dsi,
2166                                                 cur_cmd->pdata,
2167                                                 cur_cmd->data_id,
2168                                                 cur_cmd->sp_len_dly.data_len);
2169                         if (err < 0)
2170                                 break;
2171                 }
2172         }
2173         return err;
2174 }
2175
2176 static u8 get_8bit_ecc(u32 header)
2177 {
2178         char ecc_parity[24] = {
2179                 0x07, 0x0b, 0x0d, 0x0e, 0x13, 0x15, 0x16, 0x19,
2180                 0x1a, 0x1c, 0x23, 0x25, 0x26, 0x29, 0x2a, 0x2c,
2181                 0x31, 0x32, 0x34, 0x38, 0x1f, 0x2f, 0x37, 0x3b
2182         };
2183         u8 ecc_byte;
2184         int i;
2185
2186         ecc_byte = 0;
2187         for (i = 0; i < 24; i++)
2188                 ecc_byte ^= ((header >> i) & 1) ? ecc_parity[i] : 0x00;
2189
2190         return ecc_byte;
2191 }
2192
2193 /* This function is written to send DCS short write (1 parameter) only.
2194  * This means the cmd will contain only 1 byte of index and 1 byte of value.
2195  * The data type ID is fixed at 0x15 and the ECC is calculated based on the
2196  * data in pdata.
2197  * The command will be sent by hardware every frame.
2198  * pdata should contain both the index + value for each cmd.
2199  * data_len will be the total number of bytes in pdata.
2200  */
2201 int tegra_dsi_send_panel_short_cmd(struct tegra_dc *dc, u8 *pdata, u8 data_len)
2202 {
2203         u8 ecc8bits = 0, data_len_orig = 0;
2204         u32 val = 0, pkthdr = 0;
2205         int err = 0, count = 0;
2206         struct tegra_dc_dsi_data *dsi = tegra_dc_get_outdata(dc);
2207
2208         if (dc->out->flags & TEGRA_DC_OUT_ONE_SHOT_LP_MODE)
2209                 tegra_dc_host_resume(dc);
2210
2211         data_len_orig = data_len;
2212         if (pdata != NULL) {
2213                 while (data_len) {
2214                         if (data_len >= 2) {
2215                                 pkthdr = (CMD_SHORTW |
2216                                         (((u16 *)pdata)[0]) << 8 | 0x00 << 24);
2217                                 ecc8bits = get_8bit_ecc(pkthdr);
2218                                 val = (pkthdr | (ecc8bits << 24));
2219                                 data_len -= 2;
2220                                 pdata += 2;
2221                                 count++;
2222                         }
2223                         switch (count) {
2224                         case 1:
2225                                 tegra_dsi_writel(dsi, val, DSI_INIT_SEQ_DATA_0);
2226                                 break;
2227                         case 2:
2228                                 tegra_dsi_writel(dsi, val, DSI_INIT_SEQ_DATA_1);
2229                                 break;
2230                         case 3:
2231                                 tegra_dsi_writel(dsi, val, DSI_INIT_SEQ_DATA_2);
2232                                 break;
2233                         case 4:
2234                                 tegra_dsi_writel(dsi, val, DSI_INIT_SEQ_DATA_3);
2235                                 break;
2236                         case 5:
2237                                 tegra_dsi_writel(dsi, val, DSI_INIT_SEQ_DATA_4);
2238                                 break;
2239                         case 6:
2240                                 tegra_dsi_writel(dsi, val, DSI_INIT_SEQ_DATA_5);
2241                                 break;
2242                         case 7:
2243                                 tegra_dsi_writel(dsi, val, DSI_INIT_SEQ_DATA_6);
2244                                 break;
2245                         case 8:
2246                                 tegra_dsi_writel(dsi, val, DSI_INIT_SEQ_DATA_7);
2247                                 break;
2248                         default:
2249                                 err = 1;
2250                                 break;
2251                         }
2252                 }
2253         }
2254
2255         val = DSI_INIT_SEQ_CONTROL_DSI_FRAME_INIT_BYTE_COUNT(data_len_orig * 2)
2256                 | DSI_INIT_SEQ_CONTROL_DSI_SEND_INIT_SEQUENCE(1);
2257         tegra_dsi_writel(dsi, val, DSI_INIT_SEQ_CONTROL);
2258
2259         return err;
2260 }
2261 EXPORT_SYMBOL(tegra_dsi_send_panel_short_cmd);
2262
2263 static int tegra_dsi_bta(struct tegra_dc_dsi_data *dsi)
2264 {
2265         u32 val;
2266         u32 poll_time;
2267         int err;
2268
2269         poll_time = 0;
2270         err = 0;
2271
2272         val = tegra_dsi_readl(dsi, DSI_HOST_DSI_CONTROL);
2273         val |= DSI_HOST_DSI_CONTROL_IMM_BTA(TEGRA_DSI_ENABLE);
2274         tegra_dsi_writel(dsi, val, DSI_HOST_DSI_CONTROL);
2275
2276 #if DSI_USE_SYNC_POINTS
2277         dsi->syncpt_val = nvhost_syncpt_read_ext(dsi->dc->ndev,
2278                         dsi->syncpt_id);
2279
2280         val = DSI_INCR_SYNCPT_COND(OP_DONE) |
2281                 DSI_INCR_SYNCPT_INDX(dsi->syncpt_id);
2282         tegra_dsi_writel(dsi, val, DSI_INCR_SYNCPT);
2283
2284         /* TODO: Use interrupt rather than polling */
2285         err = nvhost_syncpt_wait_timeout_ext(dsi->dc->ndev, dsi->syncpt_id,
2286                 dsi->syncpt_val + 1, MAX_SCHEDULE_TIMEOUT, NULL);
2287         if (err < 0)
2288                 dev_err(&dsi->dc->ndev->dev,
2289                         "DSI sync point failure\n");
2290         else
2291                 (dsi->syncpt_val)++;
2292 #else
2293         if (tegra_dsi_read_busy(dsi)) {
2294                 err = -EBUSY;
2295                 dev_err(&dsi->dc->ndev->dev,
2296                         "Timeout wating on read completion\n");
2297         }
2298 #endif
2299
2300         return err;
2301 }
2302
2303 static int tegra_dsi_parse_read_response(struct tegra_dc *dc,
2304                                         u32 rd_fifo_cnt, u8 *read_fifo)
2305 {
2306         int err;
2307         u32 payload_size;
2308
2309         payload_size = 0;
2310         err = 0;
2311
2312         switch (read_fifo[0]) {
2313         case DSI_ESCAPE_CMD:
2314                 dev_info(&dc->ndev->dev, "escape cmd[0x%x]\n", read_fifo[0]);
2315                 break;
2316         case DSI_ACK_NO_ERR:
2317                 dev_info(&dc->ndev->dev,
2318                         "Panel ack, no err[0x%x]\n", read_fifo[0]);
2319                 return err;
2320         default:
2321                 dev_info(&dc->ndev->dev, "Invalid read response\n");
2322                 break;
2323         }
2324
2325         switch (read_fifo[4] & 0xff) {
2326         case GEN_LONG_RD_RES:
2327                 /* Fall through */
2328         case DCS_LONG_RD_RES:
2329                 payload_size = (read_fifo[5] |
2330                                 (read_fifo[6] << 8)) & 0xFFFF;
2331                 dev_info(&dc->ndev->dev, "Long read response Packet\n"
2332                                 "payload_size[0x%x]\n", payload_size);
2333                 break;
2334         case GEN_1_BYTE_SHORT_RD_RES:
2335                 /* Fall through */
2336         case DCS_1_BYTE_SHORT_RD_RES:
2337                 payload_size = 1;
2338                 dev_info(&dc->ndev->dev, "Short read response Packet\n"
2339                         "payload_size[0x%x]\n", payload_size);
2340                 break;
2341         case GEN_2_BYTE_SHORT_RD_RES:
2342                 /* Fall through */
2343         case DCS_2_BYTE_SHORT_RD_RES:
2344                 payload_size = 2;
2345                 dev_info(&dc->ndev->dev, "Short read response Packet\n"
2346                         "payload_size[0x%x]\n", payload_size);
2347                 break;
2348         case ACK_ERR_RES:
2349                 payload_size = 2;
2350                 dev_info(&dc->ndev->dev, "Acknowledge error report response\n"
2351                         "Packet payload_size[0x%x]\n", payload_size);
2352                 break;
2353         default:
2354                 dev_info(&dc->ndev->dev, "Invalid response packet\n");
2355                 err = -EINVAL;
2356                 break;
2357         }
2358         return err;
2359 }
2360
2361 static int tegra_dsi_read_fifo(struct tegra_dc *dc,
2362                         struct tegra_dc_dsi_data *dsi,
2363                         u8 *read_fifo)
2364 {
2365         u32 val;
2366         u32 i;
2367         u32 poll_time = 0;
2368         u32 rd_fifo_cnt;
2369         int err = 0;
2370         u8 *read_fifo_cp = read_fifo;
2371
2372         while (poll_time <  DSI_DELAY_FOR_READ_FIFO) {
2373                 mdelay(1);
2374                 val = tegra_dsi_readl(dsi, DSI_STATUS);
2375                 rd_fifo_cnt = val & DSI_STATUS_RD_FIFO_COUNT(0x1f);
2376                 if (rd_fifo_cnt << 2 > DSI_READ_FIFO_DEPTH)
2377                         dev_err(&dc->ndev->dev,
2378                         "DSI RD_FIFO_CNT is greater than RD_FIFO_DEPTH\n");
2379                         break;
2380                 poll_time++;
2381         }
2382
2383         if (rd_fifo_cnt == 0) {
2384                 dev_info(&dc->ndev->dev,
2385                         "DSI RD_FIFO_CNT is zero\n");
2386                 err = -EINVAL;
2387                 goto fail;
2388         }
2389
2390         if (val & (DSI_STATUS_LB_UNDERFLOW(0x1) |
2391                 DSI_STATUS_LB_OVERFLOW(0x1))) {
2392                 dev_warn(&dc->ndev->dev,
2393                         "DSI overflow/underflow error\n");
2394         }
2395
2396         /* Read data from FIFO */
2397         for (i = 0; i < rd_fifo_cnt; i++) {
2398                 val = tegra_dsi_readl(dsi, DSI_RD_DATA);
2399                 if (enable_read_debug)
2400                         dev_info(&dc->ndev->dev,
2401                         "Read data[%d]: 0x%x\n", i, val);
2402                 memcpy(read_fifo, &val, 4);
2403                 read_fifo += 4;
2404         }
2405
2406         /* Make sure all the data is read from the FIFO */
2407         val = tegra_dsi_readl(dsi, DSI_STATUS);
2408         val &= DSI_STATUS_RD_FIFO_COUNT(0x1f);
2409         if (val)
2410                 dev_err(&dc->ndev->dev, "DSI FIFO_RD_CNT not zero"
2411                 " even after reading FIFO_RD_CNT words from read fifo\n");
2412
2413         if (enable_read_debug) {
2414                 err =
2415                 tegra_dsi_parse_read_response(dc, rd_fifo_cnt, read_fifo_cp);
2416                 if (err < 0)
2417                         dev_warn(&dc->ndev->dev, "Unexpected read data\n");
2418         }
2419 fail:
2420         return err;
2421 }
2422
2423 int tegra_dsi_read_data(struct tegra_dc *dc,
2424                                 struct tegra_dc_dsi_data *dsi,
2425                                 u32 max_ret_payload_size,
2426                                 u32 panel_reg_addr, u8 *read_data)
2427 {
2428         int err = 0;
2429         struct dsi_status *init_status;
2430
2431         tegra_dc_io_start(dc);
2432
2433         init_status = tegra_dsi_prepare_host_transmission(
2434                                 dc, dsi, DSI_LP_OP_WRITE);
2435         if (IS_ERR_OR_NULL(init_status)) {
2436                 err = PTR_ERR(init_status);
2437                 dev_err(&dc->ndev->dev, "DSI host config failed\n");
2438                 goto fail;
2439         }
2440
2441         /* Set max return payload size in words */
2442         err = _tegra_dsi_write_data(dsi, NULL,
2443                 dsi_command_max_return_pkt_size,
2444                 max_ret_payload_size);
2445         if (err < 0) {
2446                 dev_err(&dc->ndev->dev,
2447                                 "DSI write failed\n");
2448                 goto fail;
2449         }
2450
2451         /* DCS to read given panel register */
2452         err = _tegra_dsi_write_data(dsi, NULL,
2453                 dsi_command_dcs_read_with_no_params,
2454                 panel_reg_addr);
2455         if (err < 0) {
2456                 dev_err(&dc->ndev->dev,
2457                                 "DSI write failed\n");
2458                 goto fail;
2459         }
2460
2461         tegra_dsi_reset_read_count(dsi);
2462
2463         if (dsi->status.lp_op == DSI_LP_OP_WRITE) {
2464                 err = tegra_dsi_set_to_lp_mode(dc, dsi, DSI_LP_OP_READ);
2465                 if (err < 0) {
2466                         dev_err(&dc->ndev->dev,
2467                         "DSI failed to go to LP read mode\n");
2468                         goto fail;
2469                 }
2470         }
2471
2472         err = tegra_dsi_bta(dsi);
2473         if (err < 0) {
2474                 dev_err(&dc->ndev->dev,
2475                         "DSI IMM BTA timeout\n");
2476                 goto fail;
2477         }
2478
2479         err = tegra_dsi_read_fifo(dc, dsi, read_data);
2480         if (err < 0) {
2481                 dev_err(&dc->ndev->dev, "DSI read fifo failure\n");
2482                 goto fail;
2483         }
2484 fail:
2485         err = tegra_dsi_restore_state(dc, dsi, init_status);
2486         if (err < 0)
2487                 dev_err(&dc->ndev->dev, "Failed to restore prev state\n");
2488         tegra_dc_io_end(dc);
2489         return err;
2490 }
2491 EXPORT_SYMBOL(tegra_dsi_read_data);
2492
2493 int tegra_dsi_panel_sanity_check(struct tegra_dc *dc,
2494                                 struct tegra_dc_dsi_data *dsi)
2495 {
2496         int err = 0;
2497         u8 read_fifo[DSI_READ_FIFO_DEPTH];
2498         struct dsi_status *init_status;
2499         static struct tegra_dsi_cmd dsi_nop_cmd =
2500                         DSI_CMD_SHORT(0x05, 0x0, 0x0);
2501
2502         tegra_dc_io_start(dc);
2503
2504         init_status = tegra_dsi_prepare_host_transmission(
2505                                         dc, dsi, DSI_LP_OP_WRITE);
2506         if (IS_ERR_OR_NULL(init_status)) {
2507                 err = PTR_ERR(init_status);
2508                 dev_err(&dc->ndev->dev, "DSI host config failed\n");
2509                 goto fail;
2510         }
2511
2512         err = _tegra_dsi_write_data(dsi, NULL, dsi_nop_cmd.data_id, 0x0);
2513         if (err < 0) {
2514                 dev_err(&dc->ndev->dev, "DSI nop write failed\n");
2515                 goto fail;
2516         }
2517
2518         tegra_dsi_reset_read_count(dsi);
2519
2520         if (dsi->status.lp_op == DSI_LP_OP_WRITE) {
2521                 err = tegra_dsi_set_to_lp_mode(dc, dsi, DSI_LP_OP_READ);
2522                 if (err < 0) {
2523                         dev_err(&dc->ndev->dev,
2524                         "DSI failed to go to LP read mode\n");
2525                         goto fail;
2526                 }
2527         }
2528
2529         err = tegra_dsi_bta(dsi);
2530         if (err < 0) {
2531                 dev_err(&dc->ndev->dev, "DSI BTA failed\n");
2532                 goto fail;
2533         }
2534
2535         err = tegra_dsi_read_fifo(dc, dsi, read_fifo);
2536         if (err < 0) {
2537                 dev_err(&dc->ndev->dev, "DSI read fifo failure\n");
2538                 goto fail;
2539         }
2540
2541         if (read_fifo[0] != DSI_ACK_NO_ERR) {
2542                 dev_warn(&dc->ndev->dev,
2543                         "Ack no error trigger message not received\n");
2544                 err = -EAGAIN;
2545         }
2546 fail:
2547         err = tegra_dsi_restore_state(dc, dsi, init_status);
2548         if (err < 0)
2549                 dev_err(&dc->ndev->dev, "Failed to restore prev state\n");
2550         tegra_dc_io_end(dc);
2551         return err;
2552 }
2553 EXPORT_SYMBOL(tegra_dsi_panel_sanity_check);
2554
2555 static int tegra_dsi_enter_ulpm(struct tegra_dc_dsi_data *dsi)
2556 {
2557         u32 val;
2558         int ret;
2559
2560         ret = 0;
2561
2562         val = tegra_dsi_readl(dsi, DSI_HOST_DSI_CONTROL);
2563         val &= ~DSI_HOST_DSI_CONTROL_ULTRA_LOW_POWER(3);
2564         val |= DSI_HOST_DSI_CONTROL_ULTRA_LOW_POWER(ENTER_ULPM);
2565         tegra_dsi_writel(dsi, val, DSI_HOST_DSI_CONTROL);
2566
2567 #if DSI_USE_SYNC_POINTS
2568         ret = tegra_dsi_syncpt(dsi);
2569         if (ret < 0) {
2570                 dev_err(&dsi->dc->ndev->dev,
2571                         "DSI syncpt for ulpm enter failed\n");
2572                 goto fail;
2573         }
2574 #else
2575         /* TODO: Find exact delay required */
2576         mdelay(10);
2577 #endif
2578         dsi->ulpm = true;
2579 fail:
2580         return ret;
2581 }
2582
2583 static int tegra_dsi_exit_ulpm(struct tegra_dc_dsi_data *dsi)
2584 {
2585         u32 val;
2586         int ret;
2587
2588         ret = 0;
2589
2590         val = tegra_dsi_readl(dsi, DSI_HOST_DSI_CONTROL);
2591         val &= ~DSI_HOST_DSI_CONTROL_ULTRA_LOW_POWER(3);
2592         val |= DSI_HOST_DSI_CONTROL_ULTRA_LOW_POWER(EXIT_ULPM);
2593         tegra_dsi_writel(dsi, val, DSI_HOST_DSI_CONTROL);
2594
2595 #if DSI_USE_SYNC_POINTS
2596         ret = tegra_dsi_syncpt(dsi);
2597         if (ret < 0) {
2598                 dev_err(&dsi->dc->ndev->dev,
2599                         "DSI syncpt for ulpm exit failed\n");
2600                 goto fail;
2601         }
2602 #else
2603         /* TODO: Find exact delay required */
2604         mdelay(10);
2605 #endif
2606         dsi->ulpm = false;
2607
2608         val = tegra_dsi_readl(dsi, DSI_HOST_DSI_CONTROL);
2609         val &= ~DSI_HOST_DSI_CONTROL_ULTRA_LOW_POWER(0x3);
2610         val |= DSI_HOST_DSI_CONTROL_ULTRA_LOW_POWER(NORMAL);
2611         tegra_dsi_writel(dsi, val, DSI_HOST_DSI_CONTROL);
2612 fail:
2613         return ret;
2614
2615 }
2616
2617 static void tegra_dc_dsi_enable(struct tegra_dc *dc)
2618 {
2619         struct tegra_dc_dsi_data *dsi = tegra_dc_get_outdata(dc);
2620         int err;
2621         u32 val;
2622
2623         tegra_dc_io_start(dc);
2624         mutex_lock(&dsi->lock);
2625
2626         if (dc->out->flags & TEGRA_DC_OUT_ONE_SHOT_LP_MODE)
2627                 tegra_dc_host_resume(dc);
2628         /* Stop DC stream before configuring DSI registers
2629          * to avoid visible glitches on panel during transition
2630          * from bootloader to kernel driver
2631          */
2632         tegra_dsi_stop_dc_stream(dc, dsi);
2633
2634         if (dsi->enabled) {
2635                 if (dsi->ulpm) {
2636                         if (tegra_dsi_exit_ulpm(dsi) < 0) {
2637                                 dev_err(&dc->ndev->dev,
2638                                         "DSI failed to exit ulpm\n");
2639                                 goto fail;
2640                         }
2641                 }
2642
2643                 if (dsi->info.panel_reset) {
2644                         err = tegra_dsi_send_panel_cmd(dc, dsi,
2645                                                         dsi->info.dsi_init_cmd,
2646                                                         dsi->info.n_init_cmd);
2647                         if (err < 0) {
2648                                 dev_err(&dc->ndev->dev,
2649                                 "dsi: error sending dsi init cmd\n");
2650                                 goto fail;
2651                         }
2652                 } else if (dsi->info.dsi_late_resume_cmd) {
2653                         err = tegra_dsi_send_panel_cmd(dc, dsi,
2654                                                 dsi->info.dsi_late_resume_cmd,
2655                                                 dsi->info.n_late_resume_cmd);
2656                         if (err < 0) {
2657                                 dev_err(&dc->ndev->dev,
2658                                 "dsi: error sending late resume cmd\n");
2659                                 goto fail;
2660                         }
2661                 }
2662         } else {
2663                 err = tegra_dsi_init_hw(dc, dsi);
2664                 if (err < 0) {
2665                         dev_err(&dc->ndev->dev,
2666                                 "dsi: not able to init dsi hardware\n");
2667                         goto fail;
2668                 }
2669
2670                 if (dsi->ulpm) {
2671                         if (tegra_dsi_enter_ulpm(dsi) < 0) {
2672                                 dev_err(&dc->ndev->dev,
2673                                         "DSI failed to enter ulpm\n");
2674                                 goto fail;
2675                         }
2676
2677                         val = tegra_dsi_readl(dsi, DSI_PAD_CONTROL);
2678
2679                         /* erase bits we're about to set */
2680                         val &= ~(DSI_PAD_CONTROL_PAD_PDIO(0x3) |
2681                                 DSI_PAD_CONTROL_PAD_PDIO_CLK(0x1) |
2682                                 DSI_PAD_CONTROL_PAD_PULLDN_ENAB(0x1));
2683
2684                         val |= (DSI_PAD_CONTROL_PAD_PDIO(0) |
2685                                 DSI_PAD_CONTROL_PAD_PDIO_CLK(0) |
2686                                 DSI_PAD_CONTROL_PAD_PULLDN_ENAB
2687                                                 (TEGRA_DSI_DISABLE));
2688
2689                         tegra_dsi_writel(dsi, val, DSI_PAD_CONTROL);
2690                         if (tegra_dsi_exit_ulpm(dsi) < 0) {
2691                                 dev_err(&dc->ndev->dev,
2692                                         "DSI failed to exit ulpm\n");
2693                                 goto fail;
2694                         }
2695                 }
2696
2697                 err = tegra_dsi_set_to_lp_mode(dc, dsi, DSI_LP_OP_WRITE);
2698                 if (err < 0) {
2699                         dev_err(&dc->ndev->dev,
2700                                 "dsi: not able to set to lp mode\n");
2701                         goto fail;
2702                 }
2703
2704                 err = tegra_dsi_send_panel_cmd(dc, dsi, dsi->info.dsi_init_cmd,
2705                                                 dsi->info.n_init_cmd);
2706                 if (err < 0) {
2707                         dev_err(&dc->ndev->dev,
2708                                 "dsi: error while sending dsi init cmd\n");
2709                         goto fail;
2710                 }
2711
2712                 err = tegra_dsi_set_to_hs_mode(dc, dsi);
2713                 if (err < 0) {
2714                         dev_err(&dc->ndev->dev,
2715                                 "dsi: not able to set to hs mode\n");
2716                         goto fail;
2717                 }
2718
2719                 dsi->enabled = true;
2720         }
2721
2722         if (dsi->status.driven == DSI_DRIVEN_MODE_DC)
2723                 tegra_dsi_start_dc_stream(dc, dsi);
2724 fail:
2725         mutex_unlock(&dsi->lock);
2726         tegra_dc_io_end(dc);
2727 }
2728
2729 static void _tegra_dc_dsi_init(struct tegra_dc *dc)
2730 {
2731         struct tegra_dc_dsi_data *dsi = tegra_dc_get_outdata(dc);
2732
2733         tegra_dc_dsi_debug_create(dsi);
2734         tegra_dsi_init_sw(dc, dsi);
2735         /* TODO: Configure the CSI pad configuration */
2736 }
2737
2738 static int tegra_dc_dsi_cp_p_cmd(struct tegra_dsi_cmd *src,
2739                                         struct tegra_dsi_cmd *dst, u16 n_cmd)
2740 {
2741         u16 i;
2742         u16 len;
2743
2744         memcpy(dst, src, sizeof(*dst) * n_cmd);
2745
2746         for (i = 0; i < n_cmd; i++)
2747                 if (src[i].pdata) {
2748                         len = sizeof(*src[i].pdata) *
2749                                         src[i].sp_len_dly.data_len;
2750                         dst[i].pdata = kzalloc(len, GFP_KERNEL);
2751                         if (!dst[i].pdata)
2752                                 goto free_cmd_pdata;
2753                         memcpy(dst[i].pdata, src[i].pdata, len);
2754                 }
2755
2756         return 0;
2757
2758 free_cmd_pdata:
2759         for (--i; i >= 0; i--)
2760                 if (dst[i].pdata)
2761                         kfree(dst[i].pdata);
2762         return -ENOMEM;
2763 }
2764
2765 static int tegra_dc_dsi_cp_info(struct tegra_dc_dsi_data *dsi,
2766                                         struct tegra_dsi_out *p_dsi)
2767 {
2768         struct tegra_dsi_cmd *p_init_cmd;
2769         struct tegra_dsi_cmd *p_early_suspend_cmd = NULL;
2770         struct tegra_dsi_cmd *p_late_resume_cmd = NULL;
2771         struct tegra_dsi_cmd *p_suspend_cmd;
2772         int err;
2773
2774         if (p_dsi->n_data_lanes > MAX_DSI_DATA_LANES)
2775                 return -EINVAL;
2776
2777         p_init_cmd = kzalloc(sizeof(*p_init_cmd) *
2778                                 p_dsi->n_init_cmd, GFP_KERNEL);
2779         if (!p_init_cmd)
2780                 return -ENOMEM;
2781
2782         if (p_dsi->dsi_early_suspend_cmd) {
2783                 p_early_suspend_cmd = kzalloc(sizeof(*p_early_suspend_cmd) *
2784                                         p_dsi->n_early_suspend_cmd,
2785                                         GFP_KERNEL);
2786                 if (!p_early_suspend_cmd) {
2787                         err = -ENOMEM;
2788                         goto err_free_init_cmd;
2789                 }
2790         }
2791
2792         if (p_dsi->dsi_late_resume_cmd) {
2793                 p_late_resume_cmd = kzalloc(sizeof(*p_late_resume_cmd) *
2794                                         p_dsi->n_late_resume_cmd,
2795                                         GFP_KERNEL);
2796                 if (!p_late_resume_cmd) {
2797                         err = -ENOMEM;
2798                         goto err_free_p_early_suspend_cmd;
2799                 }
2800         }
2801
2802         p_suspend_cmd = kzalloc(sizeof(*p_suspend_cmd) * p_dsi->n_suspend_cmd,
2803                                 GFP_KERNEL);
2804         if (!p_suspend_cmd) {
2805                 err = -ENOMEM;
2806                 goto err_free_p_late_resume_cmd;
2807         }
2808
2809         memcpy(&dsi->info, p_dsi, sizeof(dsi->info));
2810
2811         /* Copy panel init cmd */
2812         err = tegra_dc_dsi_cp_p_cmd(p_dsi->dsi_init_cmd,
2813                                                 p_init_cmd, p_dsi->n_init_cmd);
2814         if (err < 0)
2815                 goto err_free;
2816         dsi->info.dsi_init_cmd = p_init_cmd;
2817
2818         /* Copy panel early suspend cmd */
2819         if (p_dsi->dsi_early_suspend_cmd) {
2820                 err = tegra_dc_dsi_cp_p_cmd(p_dsi->dsi_early_suspend_cmd,
2821                                         p_early_suspend_cmd,
2822                                         p_dsi->n_early_suspend_cmd);
2823                 if (err < 0)
2824                         goto err_free;
2825                 dsi->info.dsi_early_suspend_cmd = p_early_suspend_cmd;
2826         }
2827
2828         /* Copy panel late resume cmd */
2829         if (p_dsi->dsi_late_resume_cmd) {
2830                 err = tegra_dc_dsi_cp_p_cmd(p_dsi->dsi_late_resume_cmd,
2831                                                 p_late_resume_cmd,
2832                                                 p_dsi->n_late_resume_cmd);
2833                 if (err < 0)
2834                         goto err_free;
2835                 dsi->info.dsi_late_resume_cmd = p_late_resume_cmd;
2836         }
2837
2838         /* Copy panel suspend cmd */
2839         err = tegra_dc_dsi_cp_p_cmd(p_dsi->dsi_suspend_cmd, p_suspend_cmd,
2840                                         p_dsi->n_suspend_cmd);
2841         if (err < 0)
2842                 goto err_free;
2843         dsi->info.dsi_suspend_cmd = p_suspend_cmd;
2844
2845         if (!dsi->info.panel_reset_timeout_msec)
2846                 dsi->info.panel_reset_timeout_msec =
2847                                                 DEFAULT_PANEL_RESET_TIMEOUT;
2848
2849         if (!dsi->info.panel_buffer_size_byte)
2850                 dsi->info.panel_buffer_size_byte = DEFAULT_PANEL_BUFFER_BYTE;
2851
2852         if (!dsi->info.max_panel_freq_khz) {
2853                 dsi->info.max_panel_freq_khz = DEFAULT_MAX_DSI_PHY_CLK_KHZ;
2854
2855                 if (dsi->info.video_burst_mode >
2856                                 TEGRA_DSI_VIDEO_NONE_BURST_MODE_WITH_SYNC_END){
2857                         dev_err(&dsi->dc->ndev->dev, "DSI: max_panel_freq_khz"
2858                                         "is not set for DSI burst mode.\n");
2859                         dsi->info.video_burst_mode =
2860                                 TEGRA_DSI_VIDEO_BURST_MODE_LOWEST_SPEED;
2861                 }
2862         }
2863
2864         if (!dsi->info.lp_cmd_mode_freq_khz)
2865                 dsi->info.lp_cmd_mode_freq_khz = DEFAULT_LP_CMD_MODE_CLK_KHZ;
2866
2867         if (!dsi->info.chip_id || !dsi->info.chip_rev)
2868                 dev_warn(&dsi->dc->ndev->dev,
2869                         "DSI: Failed to get chip info\n");
2870
2871         if (!dsi->info.lp_read_cmd_mode_freq_khz)
2872                 dsi->info.lp_read_cmd_mode_freq_khz =
2873                         dsi->info.lp_cmd_mode_freq_khz;
2874
2875         /* host mode is for testing only */
2876         dsi->driven_mode = TEGRA_DSI_DRIVEN_BY_DC;
2877         return 0;
2878
2879 err_free:
2880         kfree(p_suspend_cmd);
2881 err_free_p_late_resume_cmd:
2882         kfree(p_late_resume_cmd);
2883 err_free_p_early_suspend_cmd:
2884         kfree(p_early_suspend_cmd);
2885 err_free_init_cmd:
2886         kfree(p_init_cmd);
2887         return err;
2888 }
2889
2890 static int tegra_dc_dsi_init(struct tegra_dc *dc)
2891 {
2892         struct tegra_dc_dsi_data *dsi;
2893         struct resource *res;
2894         struct resource *base_res;
2895         void __iomem *base;
2896         struct clk *dc_clk = NULL;
2897         struct clk *dsi_clk = NULL;
2898         struct clk *dsi_fixed_clk = NULL;
2899         struct tegra_dsi_out *dsi_pdata;
2900         int err;
2901
2902         err = 0;
2903
2904         dsi = kzalloc(sizeof(*dsi), GFP_KERNEL);
2905         if (!dsi)
2906                 return -ENOMEM;
2907
2908         res = nvhost_get_resource_byname(dc->ndev, IORESOURCE_MEM,
2909                                         "dsi_regs");
2910         if (!res) {
2911                 dev_err(&dc->ndev->dev, "dsi: no mem resource\n");
2912                 err = -ENOENT;
2913                 goto err_free_dsi;
2914         }
2915
2916         base_res = request_mem_region(res->start, resource_size(res),
2917                                 dc->ndev->name);
2918         if (!base_res) {
2919                 dev_err(&dc->ndev->dev, "dsi: request_mem_region failed\n");
2920                 err = -EBUSY;
2921                 goto err_free_dsi;
2922         }
2923
2924         base = ioremap(res->start, resource_size(res));
2925         if (!base) {
2926                 dev_err(&dc->ndev->dev, "dsi: registers can't be mapped\n");
2927                 err = -EBUSY;
2928                 goto err_release_regs;
2929         }
2930
2931         dsi_pdata = dc->pdata->default_out->dsi;
2932         if (!dsi_pdata) {
2933                 dev_err(&dc->ndev->dev, "dsi: dsi data not available\n");
2934                 goto err_release_regs;
2935         }
2936
2937         if (dsi_pdata->dsi_instance)
2938                 dsi_clk = clk_get(&dc->ndev->dev, "dsib");
2939         else
2940                 dsi_clk = clk_get(&dc->ndev->dev, "dsia");
2941         dsi_fixed_clk = clk_get(&dc->ndev->dev, "dsi-fixed");
2942
2943         if (IS_ERR_OR_NULL(dsi_clk) || IS_ERR_OR_NULL(dsi_fixed_clk)) {
2944                 dev_err(&dc->ndev->dev, "dsi: can't get clock\n");
2945                 err = -EBUSY;
2946                 goto err_release_regs;
2947         }
2948
2949         dc_clk = clk_get_sys(dev_name(&dc->ndev->dev), NULL);
2950         if (IS_ERR_OR_NULL(dc_clk)) {
2951                 dev_err(&dc->ndev->dev, "dsi: dc clock %s unavailable\n",
2952                         dev_name(&dc->ndev->dev));
2953                 err = -EBUSY;
2954                 goto err_clk_put;
2955         }
2956
2957         mutex_init(&dsi->lock);
2958         dsi->dc = dc;
2959         dsi->base = base;
2960         dsi->base_res = base_res;
2961         dsi->dc_clk = dc_clk;
2962         dsi->dsi_clk = dsi_clk;
2963         dsi->dsi_fixed_clk = dsi_fixed_clk;
2964
2965         err = tegra_dc_dsi_cp_info(dsi, dsi_pdata);
2966         if (err < 0)
2967                 goto err_dsi_data;
2968
2969         tegra_dc_set_outdata(dc, dsi);
2970         _tegra_dc_dsi_init(dc);
2971
2972         return 0;
2973
2974 err_dsi_data:
2975 err_clk_put:
2976         clk_put(dsi_clk);
2977         clk_put(dsi_fixed_clk);
2978 err_release_regs:
2979         release_resource(base_res);
2980 err_free_dsi:
2981         kfree(dsi);
2982
2983         return err;
2984 }
2985
2986 static void tegra_dc_dsi_destroy(struct tegra_dc *dc)
2987 {
2988         struct tegra_dc_dsi_data *dsi = tegra_dc_get_outdata(dc);
2989         u16 i;
2990         u32 val;
2991
2992         mutex_lock(&dsi->lock);
2993
2994         /* free up the pdata */
2995         for (i = 0; i < dsi->info.n_init_cmd; i++) {
2996                 if (dsi->info.dsi_init_cmd[i].pdata)
2997                         kfree(dsi->info.dsi_init_cmd[i].pdata);
2998         }
2999         kfree(dsi->info.dsi_init_cmd);
3000
3001         /* Disable dc stream */
3002         if (dsi->status.dc_stream == DSI_DC_STREAM_ENABLE)
3003                 tegra_dsi_stop_dc_stream_at_frame_end(dc, dsi);
3004
3005         /* Disable dsi phy clock */
3006         if (dsi->status.clk_out == DSI_PHYCLK_OUT_EN)
3007                 tegra_dsi_hs_clk_out_disable(dc, dsi);
3008
3009         val = DSI_POWER_CONTROL_LEG_DSI_ENABLE(TEGRA_DSI_DISABLE);
3010         tegra_dsi_writel(dsi, val, DSI_POWER_CONTROL);
3011
3012         iounmap(dsi->base);
3013         release_resource(dsi->base_res);
3014
3015         clk_put(dsi->dc_clk);
3016         clk_put(dsi->dsi_clk);
3017
3018         mutex_unlock(&dsi->lock);
3019
3020         mutex_destroy(&dsi->lock);
3021         kfree(dsi);
3022 }
3023
3024 static int tegra_dsi_deep_sleep(struct tegra_dc *dc,
3025                                 struct tegra_dc_dsi_data *dsi)
3026 {
3027         int err = 0;
3028         int val;
3029         struct clk *parent_clk = NULL;
3030         struct clk *base_clk = NULL;
3031
3032         if (!dsi->enabled) {
3033                 err = -EPERM;
3034                 goto fail;
3035         }
3036
3037         err = tegra_dsi_set_to_lp_mode(dc, dsi, DSI_LP_OP_WRITE);
3038         if (err < 0) {
3039                 dev_err(&dc->ndev->dev,
3040                 "DSI failed to go to LP mode\n");
3041                 goto fail;
3042         }
3043
3044         /* Suspend panel */
3045         err = tegra_dsi_send_panel_cmd(dc, dsi,
3046                         dsi->info.dsi_suspend_cmd,
3047                         dsi->info.n_suspend_cmd);
3048         if (err < 0) {
3049                 dev_err(&dc->ndev->dev,
3050                         "dsi: Error sending suspend cmd\n");
3051                 goto fail;
3052         }
3053
3054         if (!dsi->ulpm) {
3055                 err = tegra_dsi_enter_ulpm(dsi);
3056                 if (err < 0) {
3057                         dev_err(&dc->ndev->dev,
3058                                 "DSI failed to enter ulpm\n");
3059                         goto fail;
3060                 }
3061         }
3062
3063         /*
3064          * Suspend pad
3065          * It is ok to overwrite previous value of DSI_PAD_CONTROL reg
3066          * because it will be restored properly in resume sequence
3067          */
3068         val = DSI_PAD_CONTROL_PAD_PDIO(0x3) |
3069                 DSI_PAD_CONTROL_PAD_PDIO_CLK(0x1) |
3070                 DSI_PAD_CONTROL_PAD_PULLDN_ENAB(TEGRA_DSI_ENABLE);
3071         tegra_dsi_writel(dsi, val, DSI_PAD_CONTROL);
3072
3073         /* Suspend core-logic */
3074         val = DSI_POWER_CONTROL_LEG_DSI_ENABLE(TEGRA_DSI_DISABLE);
3075         tegra_dsi_writel(dsi, val, DSI_POWER_CONTROL);
3076
3077         /* Disable dsi fast and slow clock */
3078         parent_clk = clk_get_parent(dsi->dsi_clk);
3079         base_clk = clk_get_parent(parent_clk);
3080         if (dsi->info.dsi_instance)
3081                 tegra_clk_cfg_ex(base_clk,
3082                                 TEGRA_CLK_PLLD_CSI_OUT_ENB,
3083                                 0);
3084         else
3085                 tegra_clk_cfg_ex(base_clk,
3086                                 TEGRA_CLK_PLLD_DSI_OUT_ENB,
3087                                 0);
3088
3089         /* Disable dsi source clock */
3090         tegra_dsi_clk_disable(dsi);
3091
3092         dsi->enabled = false;
3093
3094         return 0;
3095 fail:
3096         return err;
3097 }
3098
3099
3100 int tegra_dsi_host_suspend(struct tegra_dc *dc)
3101 {
3102         struct tegra_dc_dsi_data *dsi = tegra_dc_get_outdata(dc);
3103
3104         tegra_dsi_stop_dc_stream(dc, dsi);
3105
3106         tegra_dsi_clk_disable(dsi);
3107 }
3108
3109 void tegra_dsi_host_resume(struct tegra_dc *dc)
3110 {
3111         struct tegra_dc_dsi_data *dsi = tegra_dc_get_outdata(dc);
3112
3113         tegra_dsi_clk_enable(dsi);
3114
3115         tegra_dsi_start_dc_stream(dc, dsi);
3116 }
3117
3118 static void tegra_dc_dsi_disable(struct tegra_dc *dc)
3119 {
3120         int err;
3121         struct tegra_dc_dsi_data *dsi = tegra_dc_get_outdata(dc);
3122
3123         tegra_dc_io_start(dc);
3124         mutex_lock(&dsi->lock);
3125
3126         if (dsi->status.dc_stream == DSI_DC_STREAM_ENABLE)
3127                 tegra_dsi_stop_dc_stream_at_frame_end(dc, dsi);
3128
3129         if (dsi->info.power_saving_suspend) {
3130                 if (tegra_dsi_deep_sleep(dc, dsi) < 0) {
3131                         dev_err(&dc->ndev->dev,
3132                                 "DSI failed to enter deep sleep\n");
3133                         goto fail;
3134                 }
3135         } else {
3136                 if (dsi->info.dsi_early_suspend_cmd) {
3137                         err = tegra_dsi_send_panel_cmd(dc, dsi,
3138                                 dsi->info.dsi_early_suspend_cmd,
3139                                 dsi->info.n_early_suspend_cmd);
3140                         if (err < 0) {
3141                                 dev_err(&dc->ndev->dev,
3142                                 "dsi: Error sending early suspend cmd\n");
3143                                 goto fail;
3144                         }
3145                 }
3146
3147                 if (!dsi->ulpm) {
3148                         if (tegra_dsi_enter_ulpm(dsi) < 0) {
3149                                 dev_err(&dc->ndev->dev,
3150                                         "DSI failed to enter ulpm\n");
3151                                 goto fail;
3152                         }
3153                 }
3154         }
3155
3156 fail:
3157         mutex_unlock(&dsi->lock);
3158         tegra_dc_io_end(dc);
3159 }
3160
3161 #ifdef CONFIG_PM
3162 static void tegra_dc_dsi_suspend(struct tegra_dc *dc)
3163 {
3164         struct tegra_dc_dsi_data *dsi;
3165
3166         dsi = tegra_dc_get_outdata(dc);
3167
3168         if (!dsi->enabled)
3169                 return;
3170
3171         tegra_dc_io_start(dc);
3172         mutex_lock(&dsi->lock);
3173
3174         if (!dsi->info.power_saving_suspend) {
3175                 if (dsi->ulpm) {
3176                         if (tegra_dsi_exit_ulpm(dsi) < 0) {
3177                                 dev_err(&dc->ndev->dev,
3178                                         "DSI failed to exit ulpm");
3179                                 goto fail;
3180                         }
3181                 }
3182
3183                 if (tegra_dsi_deep_sleep(dc, dsi) < 0) {
3184                         dev_err(&dc->ndev->dev,
3185                                 "DSI failed to enter deep sleep\n");
3186                         goto fail;
3187                 }
3188         }
3189 fail:
3190         mutex_unlock(&dsi->lock);
3191         tegra_dc_io_end(dc);
3192 }
3193
3194 static void tegra_dc_dsi_resume(struct tegra_dc *dc)
3195 {
3196         /* Not required since tegra_dc_dsi_enable
3197          * will reconfigure the controller from scratch
3198          */
3199 }
3200 #endif
3201
3202 struct tegra_dc_out_ops tegra_dc_dsi_ops = {
3203         .init = tegra_dc_dsi_init,
3204         .destroy = tegra_dc_dsi_destroy,
3205         .enable = tegra_dc_dsi_enable,
3206         .disable = tegra_dc_dsi_disable,
3207 #ifdef CONFIG_PM
3208         .suspend = tegra_dc_dsi_suspend,
3209         .resume = tegra_dc_dsi_resume,
3210 #endif
3211 };