Merge commit 'main-jb-2012.08.03-B4' into t114-0806
[linux-2.6.git] / drivers / video / tegra / dc / dsi.c
1 /*
2  * drivers/video/tegra/dc/dsi.c
3  *
4  * Copyright (c) 2011-2012, NVIDIA CORPORATION, All rights reserved.
5  *
6  * This software is licensed under the terms of the GNU General Public
7  * License version 2, as published by the Free Software Foundation, and
8  * may be copied, distributed, and modified under those terms.
9  *
10  * This program is distributed in the hope that it will be useful,
11  * but WITHOUT ANY WARRANTY; without even the implied warranty of
12  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
13  * GNU General Public License for more details.
14  *
15  */
16
17 #include <linux/kernel.h>
18 #include <linux/clk.h>
19 #include <linux/delay.h>
20 #include <linux/err.h>
21 #include <linux/fb.h>
22 #include <linux/gpio.h>
23 #include <linux/interrupt.h>
24 #include <linux/slab.h>
25 #include <linux/spinlock.h>
26 #include <linux/workqueue.h>
27 #include <linux/moduleparam.h>
28 #include <linux/export.h>
29 #include <linux/debugfs.h>
30 #include <linux/seq_file.h>
31 #include <linux/nvhost.h>
32
33 #include <mach/clk.h>
34 #include <mach/dc.h>
35 #include <mach/fb.h>
36 #include <mach/csi.h>
37 #include <mach/iomap.h>
38 #include <linux/nvhost.h>
39
40 #include "dc_reg.h"
41 #include "dc_priv.h"
42 #include "dev.h"
43 #include "dsi_regs.h"
44 #include "dsi.h"
45
46 #define APB_MISC_GP_MIPI_PAD_CTRL_0     (TEGRA_APB_MISC_BASE + 0x820)
47 #define DSIB_MODE_ENABLE                0x2
48
49 #define DSI_USE_SYNC_POINTS             1
50 #define S_TO_MS(x)                      (1000 * (x))
51
52 #define DSI_MODULE_NOT_INIT             0x0
53 #define DSI_MODULE_INIT                 0x1
54
55 #define DSI_LPHS_NOT_INIT               0x0
56 #define DSI_LPHS_IN_LP_MODE             0x1
57 #define DSI_LPHS_IN_HS_MODE             0x2
58
59 #define DSI_VIDEO_TYPE_NOT_INIT         0x0
60 #define DSI_VIDEO_TYPE_VIDEO_MODE       0x1
61 #define DSI_VIDEO_TYPE_CMD_MODE         0x2
62
63 #define DSI_DRIVEN_MODE_NOT_INIT        0x0
64 #define DSI_DRIVEN_MODE_DC              0x1
65 #define DSI_DRIVEN_MODE_HOST            0x2
66
67 #define DSI_PHYCLK_OUT_DIS              0x0
68 #define DSI_PHYCLK_OUT_EN               0x1
69
70 #define DSI_PHYCLK_NOT_INIT             0x0
71 #define DSI_PHYCLK_CONTINUOUS           0x1
72 #define DSI_PHYCLK_TX_ONLY              0x2
73
74 #define DSI_CLK_BURST_NOT_INIT          0x0
75 #define DSI_CLK_BURST_NONE_BURST        0x1
76 #define DSI_CLK_BURST_BURST_MODE        0x2
77
78 #define DSI_DC_STREAM_DISABLE           0x0
79 #define DSI_DC_STREAM_ENABLE            0x1
80
81 #define DSI_LP_OP_NOT_INIT              0x0
82 #define DSI_LP_OP_WRITE                 0x1
83 #define DSI_LP_OP_READ                  0x2
84
85 static bool enable_read_debug;
86 module_param(enable_read_debug, bool, 0644);
87 MODULE_PARM_DESC(enable_read_debug,
88                 "Enable to print read fifo and return packet type");
89
90 /* source of video data */
91 enum {
92         TEGRA_DSI_DRIVEN_BY_DC,
93         TEGRA_DSI_DRIVEN_BY_HOST,
94 };
95
96 static struct tegra_dc_dsi_data *tegra_dsi_instance[MAX_DSI_INSTANCE];
97
98 const u32 dsi_pkt_seq_reg[NUMOF_PKT_SEQ] = {
99         DSI_PKT_SEQ_0_LO,
100         DSI_PKT_SEQ_0_HI,
101         DSI_PKT_SEQ_1_LO,
102         DSI_PKT_SEQ_1_HI,
103         DSI_PKT_SEQ_2_LO,
104         DSI_PKT_SEQ_2_HI,
105         DSI_PKT_SEQ_3_LO,
106         DSI_PKT_SEQ_3_HI,
107         DSI_PKT_SEQ_4_LO,
108         DSI_PKT_SEQ_4_HI,
109         DSI_PKT_SEQ_5_LO,
110         DSI_PKT_SEQ_5_HI,
111 };
112
113 const u32 dsi_pkt_seq_video_non_burst_syne[NUMOF_PKT_SEQ] = {
114         PKT_ID0(CMD_VS) | PKT_LEN0(0) | PKT_ID1(CMD_EOT) | PKT_LEN1(0) | PKT_LP,
115         0,
116         PKT_ID0(CMD_VE) | PKT_LEN0(0) | PKT_ID1(CMD_EOT) | PKT_LEN1(0) | PKT_LP,
117         0,
118         PKT_ID0(CMD_HS) | PKT_LEN0(0) | PKT_ID1(CMD_EOT) | PKT_LEN1(0) | PKT_LP,
119         0,
120         PKT_ID0(CMD_HS) | PKT_LEN0(0) | PKT_ID1(CMD_BLNK) | PKT_LEN1(1) |
121         PKT_ID2(CMD_HE) | PKT_LEN2(0),
122         PKT_ID3(CMD_BLNK) | PKT_LEN3(2) | PKT_ID4(CMD_RGB) | PKT_LEN4(3) |
123         PKT_ID5(CMD_BLNK) | PKT_LEN5(4),
124         PKT_ID0(CMD_HS) | PKT_LEN0(0) | PKT_ID1(CMD_EOT) | PKT_LEN1(0) | PKT_LP,
125         0,
126         PKT_ID0(CMD_HS) | PKT_LEN0(0) | PKT_ID1(CMD_BLNK) | PKT_LEN1(1) |
127         PKT_ID2(CMD_HE) | PKT_LEN2(0),
128         PKT_ID3(CMD_BLNK) | PKT_LEN3(2) | PKT_ID4(CMD_RGB) | PKT_LEN4(3) |
129         PKT_ID5(CMD_BLNK) | PKT_LEN5(4),
130 };
131
132 const u32 dsi_pkt_seq_video_non_burst[NUMOF_PKT_SEQ] = {
133         PKT_ID0(CMD_VS) | PKT_LEN0(0) | PKT_ID1(CMD_EOT) | PKT_LEN1(0) | PKT_LP,
134         0,
135         PKT_ID0(CMD_HS) | PKT_LEN0(0) | PKT_ID1(CMD_EOT) | PKT_LEN1(0) | PKT_LP,
136         0,
137         PKT_ID0(CMD_HS) | PKT_LEN0(0) | PKT_ID1(CMD_EOT) | PKT_LEN1(0) | PKT_LP,
138         0,
139         PKT_ID0(CMD_HS) | PKT_LEN0(0) | PKT_ID1(CMD_BLNK) | PKT_LEN1(2) |
140         PKT_ID2(CMD_RGB) | PKT_LEN2(3),
141         PKT_ID3(CMD_BLNK) | PKT_LEN3(4),
142         PKT_ID0(CMD_HS) | PKT_LEN0(0) | PKT_ID1(CMD_EOT) | PKT_LEN1(0) | PKT_LP,
143         0,
144         PKT_ID0(CMD_HS) | PKT_LEN0(0) | PKT_ID1(CMD_BLNK) | PKT_LEN1(2) |
145         PKT_ID2(CMD_RGB) | PKT_LEN2(3),
146         PKT_ID3(CMD_BLNK) | PKT_LEN3(4),
147 };
148
149 const u32 dsi_pkt_seq_video_non_burst_no_eot_no_lp_no_hbp[NUMOF_PKT_SEQ] = {
150         PKT_ID0(CMD_VS) | PKT_LEN0(0),
151         0,
152         PKT_ID0(CMD_HS) | PKT_LEN0(0),
153         0,
154         PKT_ID0(CMD_HS) | PKT_LEN0(0),
155         0,
156         PKT_ID0(CMD_HS) | PKT_LEN0(0) | PKT_ID1(CMD_RGB) | PKT_LEN1(3) |
157         PKT_ID2(CMD_BLNK) | PKT_LEN2(4),
158         0,
159         PKT_ID0(CMD_HS) | PKT_LEN0(0),
160         0,
161         PKT_ID0(CMD_HS) | PKT_LEN0(0) | PKT_ID1(CMD_RGB) | PKT_LEN1(3) |
162         PKT_ID2(CMD_BLNK) | PKT_LEN2(4),
163         0,
164 };
165
166 static const u32 dsi_pkt_seq_video_burst[NUMOF_PKT_SEQ] = {
167         PKT_ID0(CMD_VS) | PKT_LEN0(0) | PKT_ID1(CMD_EOT) | PKT_LEN1(7) | PKT_LP,
168         0,
169         PKT_ID0(CMD_HS) | PKT_LEN0(0) | PKT_ID1(CMD_EOT) | PKT_LEN1(7) | PKT_LP,
170         0,
171         PKT_ID0(CMD_HS) | PKT_LEN0(0) | PKT_ID1(CMD_EOT) | PKT_LEN1(7) | PKT_LP,
172         0,
173         PKT_ID0(CMD_HS) | PKT_LEN0(0) | PKT_ID1(CMD_BLNK) | PKT_LEN1(2)|
174         PKT_ID2(CMD_RGB) | PKT_LEN2(3) | PKT_LP,
175         PKT_ID0(CMD_EOT) | PKT_LEN0(7),
176         PKT_ID0(CMD_HS) | PKT_LEN0(0) | PKT_ID1(CMD_EOT) | PKT_LEN1(7) | PKT_LP,
177         0,
178         PKT_ID0(CMD_HS) | PKT_LEN0(0) | PKT_ID1(CMD_BLNK) | PKT_LEN1(2)|
179         PKT_ID2(CMD_RGB) | PKT_LEN2(3) | PKT_LP,
180         PKT_ID0(CMD_EOT) | PKT_LEN0(7),
181 };
182
183 static const u32 dsi_pkt_seq_video_burst_no_eot[NUMOF_PKT_SEQ] = {
184         PKT_ID0(CMD_VS) | PKT_LEN0(0) | PKT_ID1(CMD_EOT) | PKT_LEN1(0) | PKT_LP,
185         0,
186         PKT_ID0(CMD_HS) | PKT_LEN0(0) | PKT_ID1(CMD_EOT) | PKT_LEN1(0) | PKT_LP,
187         0,
188         PKT_ID0(CMD_HS) | PKT_LEN0(0) | PKT_ID1(CMD_EOT) | PKT_LEN1(0) | PKT_LP,
189         0,
190         PKT_ID0(CMD_HS) | PKT_LEN0(0) | PKT_ID1(CMD_BLNK) | PKT_LEN1(2)|
191         PKT_ID2(CMD_RGB) | PKT_LEN2(3) | PKT_LP,
192         PKT_ID0(CMD_EOT) | PKT_LEN0(0),
193         PKT_ID0(CMD_HS) | PKT_LEN0(0) | PKT_ID1(CMD_EOT) | PKT_LEN1(0) | PKT_LP,
194         0,
195         PKT_ID0(CMD_HS) | PKT_LEN0(0) | PKT_ID1(CMD_BLNK) | PKT_LEN1(2)|
196         PKT_ID2(CMD_RGB) | PKT_LEN2(3) | PKT_LP,
197         PKT_ID0(CMD_EOT) | PKT_LEN0(0),
198 };
199
200 /* TODO: verify with hw about this format */
201 const u32 dsi_pkt_seq_cmd_mode[NUMOF_PKT_SEQ] = {
202         0,
203         0,
204         0,
205         0,
206         0,
207         0,
208         PKT_ID0(CMD_LONGW) | PKT_LEN0(3) | PKT_ID1(CMD_EOT) | PKT_LEN1(7),
209         0,
210         0,
211         0,
212         PKT_ID0(CMD_LONGW) | PKT_LEN0(3) | PKT_ID1(CMD_EOT) | PKT_LEN1(7),
213         0,
214 };
215
216 const u32 init_reg[] = {
217         DSI_INT_ENABLE,
218         DSI_INT_STATUS,
219         DSI_INT_MASK,
220         DSI_INIT_SEQ_DATA_0,
221         DSI_INIT_SEQ_DATA_1,
222         DSI_INIT_SEQ_DATA_2,
223         DSI_INIT_SEQ_DATA_3,
224         DSI_INIT_SEQ_DATA_4,
225         DSI_INIT_SEQ_DATA_5,
226         DSI_INIT_SEQ_DATA_6,
227         DSI_INIT_SEQ_DATA_7,
228         DSI_DCS_CMDS,
229         DSI_PKT_SEQ_0_LO,
230         DSI_PKT_SEQ_1_LO,
231         DSI_PKT_SEQ_2_LO,
232         DSI_PKT_SEQ_3_LO,
233         DSI_PKT_SEQ_4_LO,
234         DSI_PKT_SEQ_5_LO,
235         DSI_PKT_SEQ_0_HI,
236         DSI_PKT_SEQ_1_HI,
237         DSI_PKT_SEQ_2_HI,
238         DSI_PKT_SEQ_3_HI,
239         DSI_PKT_SEQ_4_HI,
240         DSI_PKT_SEQ_5_HI,
241         DSI_CONTROL,
242         DSI_HOST_DSI_CONTROL,
243         DSI_PAD_CONTROL,
244         DSI_PAD_CONTROL_CD,
245         DSI_SOL_DELAY,
246         DSI_MAX_THRESHOLD,
247         DSI_TRIGGER,
248         DSI_TX_CRC,
249         DSI_INIT_SEQ_CONTROL,
250         DSI_PKT_LEN_0_1,
251         DSI_PKT_LEN_2_3,
252         DSI_PKT_LEN_4_5,
253         DSI_PKT_LEN_6_7,
254 };
255
256 const u32 init_reg_vs1_ext[] = {
257         DSI_PAD_CONTROL_0_VS1,
258         DSI_PAD_CONTROL_CD_VS1,
259         DSI_PAD_CD_STATUS_VS1,
260         DSI_PAD_CONTROL_1_VS1,
261         DSI_PAD_CONTROL_2_VS1,
262         DSI_PAD_CONTROL_3_VS1,
263         DSI_PAD_CONTROL_4_VS1,
264         DSI_GANGED_MODE_CONTROL,
265         DSI_GANGED_MODE_START,
266         DSI_GANGED_MODE_SIZE,
267 };
268
269 static int tegra_dsi_host_suspend(struct tegra_dc *dc);
270 static int tegra_dsi_host_resume(struct tegra_dc *dc);
271
272 inline unsigned long tegra_dsi_readl(struct tegra_dc_dsi_data *dsi, u32 reg)
273 {
274         unsigned long ret;
275
276         BUG_ON(!nvhost_module_powered_ext(nvhost_get_parent(dsi->dc->ndev)));
277         ret = readl(dsi->base + reg * 4);
278         trace_printk("readl %p=%#08lx\n", dsi->base + reg * 4, ret);
279         return ret;
280 }
281 EXPORT_SYMBOL(tegra_dsi_readl);
282
283 inline void tegra_dsi_writel(struct tegra_dc_dsi_data *dsi, u32 val, u32 reg)
284 {
285         BUG_ON(!nvhost_module_powered_ext(nvhost_get_parent(dsi->dc->ndev)));
286         trace_printk("writel %p=%#08x\n", dsi->base + reg * 4, val);
287         writel(val, dsi->base + reg * 4);
288 }
289 EXPORT_SYMBOL(tegra_dsi_writel);
290
291 #ifdef CONFIG_DEBUG_FS
292 static int dbg_dsi_show(struct seq_file *s, void *unused)
293 {
294         struct tegra_dc_dsi_data *dsi = s->private;
295
296 #define DUMP_REG(a) do {                                                \
297                 seq_printf(s, "%-32s\t%03x\t%08lx\n",                   \
298                        #a, a, tegra_dsi_readl(dsi, a));         \
299         } while (0)
300
301         tegra_dc_io_start(dsi->dc);
302         clk_enable(dsi->dsi_clk);
303
304         DUMP_REG(DSI_INCR_SYNCPT_CNTRL);
305         DUMP_REG(DSI_INCR_SYNCPT_ERROR);
306         DUMP_REG(DSI_CTXSW);
307         DUMP_REG(DSI_POWER_CONTROL);
308         DUMP_REG(DSI_INT_ENABLE);
309         DUMP_REG(DSI_HOST_DSI_CONTROL);
310         DUMP_REG(DSI_CONTROL);
311         DUMP_REG(DSI_SOL_DELAY);
312         DUMP_REG(DSI_MAX_THRESHOLD);
313         DUMP_REG(DSI_TRIGGER);
314         DUMP_REG(DSI_TX_CRC);
315         DUMP_REG(DSI_STATUS);
316         DUMP_REG(DSI_INIT_SEQ_CONTROL);
317         DUMP_REG(DSI_INIT_SEQ_DATA_0);
318         DUMP_REG(DSI_INIT_SEQ_DATA_1);
319         DUMP_REG(DSI_INIT_SEQ_DATA_2);
320         DUMP_REG(DSI_INIT_SEQ_DATA_3);
321         DUMP_REG(DSI_INIT_SEQ_DATA_4);
322         DUMP_REG(DSI_INIT_SEQ_DATA_5);
323         DUMP_REG(DSI_INIT_SEQ_DATA_6);
324         DUMP_REG(DSI_INIT_SEQ_DATA_7);
325         DUMP_REG(DSI_PKT_SEQ_0_LO);
326         DUMP_REG(DSI_PKT_SEQ_0_HI);
327         DUMP_REG(DSI_PKT_SEQ_1_LO);
328         DUMP_REG(DSI_PKT_SEQ_1_HI);
329         DUMP_REG(DSI_PKT_SEQ_2_LO);
330         DUMP_REG(DSI_PKT_SEQ_2_HI);
331         DUMP_REG(DSI_PKT_SEQ_3_LO);
332         DUMP_REG(DSI_PKT_SEQ_3_HI);
333         DUMP_REG(DSI_PKT_SEQ_4_LO);
334         DUMP_REG(DSI_PKT_SEQ_4_HI);
335         DUMP_REG(DSI_PKT_SEQ_5_LO);
336         DUMP_REG(DSI_PKT_SEQ_5_HI);
337         DUMP_REG(DSI_DCS_CMDS);
338         DUMP_REG(DSI_PKT_LEN_0_1);
339         DUMP_REG(DSI_PKT_LEN_2_3);
340         DUMP_REG(DSI_PKT_LEN_4_5);
341         DUMP_REG(DSI_PKT_LEN_6_7);
342         DUMP_REG(DSI_PHY_TIMING_0);
343         DUMP_REG(DSI_PHY_TIMING_1);
344         DUMP_REG(DSI_PHY_TIMING_2);
345         DUMP_REG(DSI_BTA_TIMING);
346         DUMP_REG(DSI_TIMEOUT_0);
347         DUMP_REG(DSI_TIMEOUT_1);
348         DUMP_REG(DSI_TO_TALLY);
349         DUMP_REG(DSI_PAD_CONTROL);
350         DUMP_REG(DSI_PAD_CONTROL_CD);
351         DUMP_REG(DSI_PAD_CD_STATUS);
352         DUMP_REG(DSI_VID_MODE_CONTROL);
353 #undef DUMP_REG
354
355         clk_disable(dsi->dsi_clk);
356         tegra_dc_io_end(dsi->dc);
357
358         return 0;
359 }
360
361 static int dbg_dsi_open(struct inode *inode, struct file *file)
362 {
363         return single_open(file, dbg_dsi_show, inode->i_private);
364 }
365
366 static const struct file_operations dbg_fops = {
367         .open           = dbg_dsi_open,
368         .read           = seq_read,
369         .llseek         = seq_lseek,
370         .release        = single_release,
371 };
372
373 static struct dentry *dsidir;
374
375 static void tegra_dc_dsi_debug_create(struct tegra_dc_dsi_data *dsi)
376 {
377         struct dentry *retval;
378
379         dsidir = debugfs_create_dir("tegra_dsi", NULL);
380         if (!dsidir)
381                 return;
382         retval = debugfs_create_file("regs", S_IRUGO, dsidir, dsi,
383                 &dbg_fops);
384         if (!retval)
385                 goto free_out;
386         return;
387 free_out:
388         debugfs_remove_recursive(dsidir);
389         dsidir = NULL;
390         return;
391 }
392 #else
393 static inline void tegra_dc_dsi_debug_create(struct tegra_dc_dsi_data *dsi)
394 { }
395 #endif
396
397 static inline void tegra_dsi_clk_enable(struct tegra_dc_dsi_data *dsi)
398 {
399         if (!tegra_is_clk_enabled(dsi->dsi_clk)) {
400                 clk_enable(dsi->dsi_clk);
401                 clk_enable(dsi->dsi_fixed_clk);
402         }
403 }
404
405 static inline void tegra_dsi_clk_disable(struct tegra_dc_dsi_data *dsi)
406 {
407         if (tegra_is_clk_enabled(dsi->dsi_clk)) {
408                 clk_disable(dsi->dsi_clk);
409                 clk_disable(dsi->dsi_fixed_clk);
410         }
411 }
412
413 static int tegra_dsi_syncpt(struct tegra_dc_dsi_data *dsi)
414 {
415         u32 val;
416         int ret;
417
418         ret = 0;
419
420         dsi->syncpt_val = nvhost_syncpt_read_ext(dsi->dc->ndev, dsi->syncpt_id);
421
422         val = DSI_INCR_SYNCPT_COND(OP_DONE) |
423                 DSI_INCR_SYNCPT_INDX(dsi->syncpt_id);
424         tegra_dsi_writel(dsi, val, DSI_INCR_SYNCPT);
425
426         /* TODO: Use interrupt rather than polling */
427         ret = nvhost_syncpt_wait_timeout_ext(dsi->dc->ndev, dsi->syncpt_id,
428                 dsi->syncpt_val + 1, MAX_SCHEDULE_TIMEOUT, NULL);
429         if (ret < 0) {
430                 dev_err(&dsi->dc->ndev->dev, "DSI sync point failure\n");
431                 goto fail;
432         }
433
434         (dsi->syncpt_val)++;
435         return 0;
436 fail:
437         return ret;
438 }
439
440 static u32 tegra_dsi_get_hs_clk_rate(struct tegra_dc_dsi_data *dsi)
441 {
442         u32 dsi_clock_rate_khz;
443
444         switch (dsi->info.video_burst_mode) {
445         case TEGRA_DSI_VIDEO_BURST_MODE_LOW_SPEED:
446         case TEGRA_DSI_VIDEO_BURST_MODE_MEDIUM_SPEED:
447         case TEGRA_DSI_VIDEO_BURST_MODE_FAST_SPEED:
448         case TEGRA_DSI_VIDEO_BURST_MODE_FASTEST_SPEED:
449                 /* Calculate DSI HS clock rate for DSI burst mode */
450                 dsi_clock_rate_khz = dsi->default_pixel_clk_khz *
451                                                         dsi->shift_clk_div;
452                 break;
453         case TEGRA_DSI_VIDEO_NONE_BURST_MODE:
454         case TEGRA_DSI_VIDEO_NONE_BURST_MODE_WITH_SYNC_END:
455         case TEGRA_DSI_VIDEO_BURST_MODE_LOWEST_SPEED:
456         default:
457                 /* Clock rate is default DSI clock rate for non-burst mode */
458                 dsi_clock_rate_khz = dsi->default_hs_clk_khz;
459                 break;
460         }
461
462         return dsi_clock_rate_khz;
463 }
464
465 static u32 tegra_dsi_get_lp_clk_rate(struct tegra_dc_dsi_data *dsi, u8 lp_op)
466 {
467         u32 dsi_clock_rate_khz;
468
469         if (dsi->info.enable_hs_clock_on_lp_cmd_mode)
470                 if (dsi->info.hs_clk_in_lp_cmd_mode_freq_khz)
471                         dsi_clock_rate_khz =
472                                 dsi->info.hs_clk_in_lp_cmd_mode_freq_khz;
473                 else
474                         dsi_clock_rate_khz = tegra_dsi_get_hs_clk_rate(dsi);
475         else
476                 if (lp_op == DSI_LP_OP_READ)
477                         dsi_clock_rate_khz =
478                                 dsi->info.lp_read_cmd_mode_freq_khz;
479                 else
480                         dsi_clock_rate_khz =
481                                 dsi->info.lp_cmd_mode_freq_khz;
482
483         return dsi_clock_rate_khz;
484 }
485
486 static u32 tegra_dsi_get_shift_clk_div(struct tegra_dc_dsi_data *dsi)
487 {
488         u32 shift_clk_div;
489         u32 max_shift_clk_div;
490         u32 burst_width;
491         u32 burst_width_max;
492
493         /* Get the real value of default shift_clk_div. default_shift_clk_div
494          * holds the real value of shift_clk_div.
495          */
496         shift_clk_div = dsi->default_shift_clk_div;
497
498         /* Calculate shift_clk_div which can matche the video_burst_mode. */
499         if (dsi->info.video_burst_mode >=
500                         TEGRA_DSI_VIDEO_BURST_MODE_LOWEST_SPEED) {
501                 /* The max_shift_clk_div is multiplied by 10 to save the
502                  * fraction
503                  */
504                 if (dsi->info.max_panel_freq_khz >= dsi->default_hs_clk_khz)
505                         max_shift_clk_div = dsi->info.max_panel_freq_khz
506                                 * shift_clk_div * 10 / dsi->default_hs_clk_khz;
507                 else
508                         max_shift_clk_div = shift_clk_div * 10;
509
510                 burst_width = dsi->info.video_burst_mode
511                                 - TEGRA_DSI_VIDEO_BURST_MODE_LOWEST_SPEED;
512                 burst_width_max = TEGRA_DSI_VIDEO_BURST_MODE_FASTEST_SPEED
513                                 - TEGRA_DSI_VIDEO_BURST_MODE_LOWEST_SPEED;
514
515                 shift_clk_div = (max_shift_clk_div - shift_clk_div * 10) *
516                         burst_width / (burst_width_max * 10) + shift_clk_div;
517         }
518
519         return shift_clk_div;
520 }
521
522 static void tegra_dsi_pix_correction(struct tegra_dc *dc,
523                                         struct tegra_dc_dsi_data *dsi)
524 {
525         u32 h_width_pixels;
526         u32 h_act_corr = 0;
527         u32 hfp_corr = 0;
528         u32 temp = 0;
529
530         h_width_pixels = dc->mode.h_back_porch + dc->mode.h_front_porch +
531                         dc->mode.h_sync_width + dc->mode.h_active;
532
533         if (dsi->info.ganged_type == TEGRA_DSI_GANGED_SYMMETRIC_EVEN_ODD) {
534                 temp = dc->mode.h_active % dsi->info.n_data_lanes;
535                 if (temp) {
536                         h_act_corr = dsi->info.n_data_lanes - temp;
537                         h_width_pixels += h_act_corr;
538                 }
539         }
540
541         temp = h_width_pixels % dsi->info.n_data_lanes;
542         if (temp) {
543                 hfp_corr = dsi->info.n_data_lanes - temp;
544                 h_width_pixels += hfp_corr;
545         }
546
547         while (1) {
548                 temp = (h_width_pixels * dsi->pixel_scaler_mul /
549                         dsi->pixel_scaler_div) % dsi->info.n_data_lanes;
550                 if (temp) {
551                         hfp_corr += dsi->info.n_data_lanes;
552                         h_width_pixels += dsi->info.n_data_lanes;
553                 }
554                 else
555                         break;
556         }
557
558         dc->mode.h_front_porch += hfp_corr;
559         dc->mode.h_active += h_act_corr;
560 }
561
562 static void tegra_dsi_init_sw(struct tegra_dc *dc,
563                         struct tegra_dc_dsi_data *dsi)
564 {
565         u32 h_width_pixels;
566         u32 v_width_lines;
567         u32 pixel_clk_hz;
568         u32 byte_clk_hz;
569         u32 plld_clk_mhz;
570         u8 n_data_lanes;
571
572         switch (dsi->info.pixel_format) {
573         case TEGRA_DSI_PIXEL_FORMAT_16BIT_P:
574                 /* 2 bytes per pixel */
575                 dsi->pixel_scaler_mul = 2;
576                 dsi->pixel_scaler_div = 1;
577                 break;
578         case TEGRA_DSI_PIXEL_FORMAT_18BIT_P:
579                 /* 2.25 bytes per pixel */
580                 dsi->pixel_scaler_mul = 9;
581                 dsi->pixel_scaler_div = 4;
582                 break;
583         case TEGRA_DSI_PIXEL_FORMAT_18BIT_NP:
584         case TEGRA_DSI_PIXEL_FORMAT_24BIT_P:
585                 /* 3 bytes per pixel */
586                 dsi->pixel_scaler_mul = 3;
587                 dsi->pixel_scaler_div = 1;
588                 break;
589         default:
590                 break;
591         }
592
593         dsi->ulpm = false;
594         dsi->enabled = false;
595         dsi->clk_ref = false;
596
597         if (dsi->info.ganged_type == TEGRA_DSI_GANGED_SYMMETRIC_LEFT_RIGHT ||
598                 dsi->info.ganged_type == TEGRA_DSI_GANGED_SYMMETRIC_EVEN_ODD)
599                 n_data_lanes = dsi->info.n_data_lanes / 2;
600
601         dsi->dsi_control_val =
602                         DSI_CONTROL_VIRTUAL_CHANNEL(dsi->info.virtual_channel) |
603                         DSI_CONTROL_NUM_DATA_LANES(dsi->info.n_data_lanes - 1) |
604                         DSI_CONTROL_VID_SOURCE(dc->ndev->id) |
605                         DSI_CONTROL_DATA_FORMAT(dsi->info.pixel_format);
606
607         if (dsi->info.ganged_type)
608                 tegra_dsi_pix_correction(dc, dsi);
609
610         /* Below we are going to calculate dsi and dc clock rate.
611          * Calcuate the horizontal and vertical width.
612          */
613         h_width_pixels = dc->mode.h_back_porch + dc->mode.h_front_porch +
614                         dc->mode.h_sync_width + dc->mode.h_active;
615
616         v_width_lines = dc->mode.v_back_porch + dc->mode.v_front_porch +
617                         dc->mode.v_sync_width + dc->mode.v_active;
618
619         /* Calculate minimum required pixel rate. */
620         pixel_clk_hz = h_width_pixels * v_width_lines * dsi->info.refresh_rate;
621         if (dc->out->flags & TEGRA_DC_OUT_ONE_SHOT_MODE) {
622                 if (dsi->info.rated_refresh_rate >= dsi->info.refresh_rate)
623                         dev_info(&dc->ndev->dev, "DSI: measured refresh rate "
624                                 "should be larger than rated refresh rate.\n");
625                 dc->mode.rated_pclk = h_width_pixels * v_width_lines *
626                                                 dsi->info.rated_refresh_rate;
627         }
628
629         /* Calculate minimum byte rate on DSI interface. */
630         byte_clk_hz = (pixel_clk_hz * dsi->pixel_scaler_mul) /
631                         (dsi->pixel_scaler_div * dsi->info.n_data_lanes);
632
633         /* Round up to multiple of mega hz. */
634         plld_clk_mhz = DIV_ROUND_UP((byte_clk_hz * NUMOF_BIT_PER_BYTE),
635                                                                 1000000);
636
637         /* Calculate default real shift_clk_div. */
638         dsi->default_shift_clk_div = (NUMOF_BIT_PER_BYTE / 2) *
639                 dsi->pixel_scaler_mul / (dsi->pixel_scaler_div *
640                 dsi->info.n_data_lanes);
641         /* Calculate default DSI hs clock. DSI interface is double data rate.
642          * Data is transferred on both rising and falling edge of clk, div by 2
643          * to get the actual clock rate.
644          */
645         dsi->default_hs_clk_khz = plld_clk_mhz * 1000 / 2;
646         dsi->default_pixel_clk_khz = plld_clk_mhz * 1000 / 2
647                                                 / dsi->default_shift_clk_div;
648
649         /* Get the actual shift_clk_div and clock rates. */
650         dsi->shift_clk_div = tegra_dsi_get_shift_clk_div(dsi);
651         dsi->target_lp_clk_khz =
652                         tegra_dsi_get_lp_clk_rate(dsi, DSI_LP_OP_WRITE);
653         dsi->target_hs_clk_khz = tegra_dsi_get_hs_clk_rate(dsi);
654
655         dev_info(&dc->ndev->dev, "DSI: HS clock rate is %d\n",
656                                                         dsi->target_hs_clk_khz);
657
658 #if DSI_USE_SYNC_POINTS
659         dsi->syncpt_id = NVSYNCPT_DSI;
660 #endif
661
662         /*
663          * Force video clock to be continuous mode if
664          * enable_hs_clock_on_lp_cmd_mode is set
665          */
666         if (dsi->info.enable_hs_clock_on_lp_cmd_mode) {
667                 if (dsi->info.video_clock_mode !=
668                                         TEGRA_DSI_VIDEO_CLOCK_CONTINUOUS)
669                         dev_warn(&dc->ndev->dev,
670                                 "Force clock continuous mode\n");
671
672                 dsi->info.video_clock_mode = TEGRA_DSI_VIDEO_CLOCK_CONTINUOUS;
673         }
674
675 }
676
677 #define SELECT_T_PHY(platform_t_phy_ns, default_phy, clk_ns, hw_inc) ( \
678 (platform_t_phy_ns) ? ( \
679 ((DSI_CONVERT_T_PHY_NS_TO_T_PHY(platform_t_phy_ns, clk_ns, hw_inc)) < 0 ? 0 : \
680 (DSI_CONVERT_T_PHY_NS_TO_T_PHY(platform_t_phy_ns, clk_ns, hw_inc)))) : \
681 ((default_phy) < 0 ? 0 : (default_phy)))
682
683 static void tegra_dsi_get_clk_phy_timing(struct tegra_dc_dsi_data *dsi,
684                 struct dsi_phy_timing_inclk *phy_timing_clk, u32 clk_ns)
685 {
686         phy_timing_clk->t_tlpx = SELECT_T_PHY(
687                 dsi->info.phy_timing.t_tlpx_ns,
688                 T_TLPX_DEFAULT(clk_ns), clk_ns, T_TLPX_HW_INC);
689
690         phy_timing_clk->t_clktrail = SELECT_T_PHY(
691                 dsi->info.phy_timing.t_clktrail_ns,
692                 T_CLKTRAIL_DEFAULT(clk_ns), clk_ns, T_CLKTRAIL_HW_INC);
693
694         phy_timing_clk->t_clkpost = SELECT_T_PHY(
695                 dsi->info.phy_timing.t_clkpost_ns,
696                 T_CLKPOST_DEFAULT(clk_ns), clk_ns, T_CLKPOST_HW_INC);
697
698         phy_timing_clk->t_clkzero = SELECT_T_PHY(
699                 dsi->info.phy_timing.t_clkzero_ns,
700                 T_CLKZERO_DEFAULT(clk_ns), clk_ns, T_CLKZERO_HW_INC);
701
702         phy_timing_clk->t_clkprepare = SELECT_T_PHY(
703                 dsi->info.phy_timing.t_clkprepare_ns,
704                 T_CLKPREPARE_DEFAULT(clk_ns), clk_ns, T_CLKPREPARE_HW_INC);
705
706         phy_timing_clk->t_clkpre = SELECT_T_PHY(
707                 dsi->info.phy_timing.t_clkpre_ns,
708                 T_CLKPRE_DEFAULT, clk_ns, T_CLKPRE_HW_INC);
709 }
710
711 static void tegra_dsi_get_hs_phy_timing(struct tegra_dc_dsi_data *dsi,
712                 struct dsi_phy_timing_inclk *phy_timing_clk, u32 clk_ns)
713 {
714         phy_timing_clk->t_tlpx = SELECT_T_PHY(
715                 dsi->info.phy_timing.t_tlpx_ns,
716                 T_TLPX_DEFAULT(clk_ns), clk_ns, T_TLPX_HW_INC);
717
718         phy_timing_clk->t_hsdexit = SELECT_T_PHY(
719                 dsi->info.phy_timing.t_hsdexit_ns,
720                 T_HSEXIT_DEFAULT(clk_ns), clk_ns, T_HSEXIT_HW_INC);
721
722         phy_timing_clk->t_hstrail = SELECT_T_PHY(
723                 dsi->info.phy_timing.t_hstrail_ns,
724                 T_HSTRAIL_DEFAULT(clk_ns), clk_ns, T_HSTRAIL_HW_INC);
725
726         phy_timing_clk->t_datzero = SELECT_T_PHY(
727                 dsi->info.phy_timing.t_datzero_ns,
728                 T_DATZERO_DEFAULT(clk_ns), clk_ns, T_DATZERO_HW_INC);
729
730         phy_timing_clk->t_hsprepare = SELECT_T_PHY(
731                 dsi->info.phy_timing.t_hsprepare_ns,
732                 T_HSPREPARE_DEFAULT(clk_ns), clk_ns, T_HSPREPARE_HW_INC);
733 }
734
735 static void tegra_dsi_get_escape_phy_timing(struct tegra_dc_dsi_data *dsi,
736                 struct dsi_phy_timing_inclk *phy_timing_clk, u32 clk_ns)
737 {
738         phy_timing_clk->t_tlpx = SELECT_T_PHY(
739                 dsi->info.phy_timing.t_tlpx_ns,
740                 T_TLPX_DEFAULT(clk_ns), clk_ns, T_TLPX_HW_INC);
741 }
742
743 static void tegra_dsi_get_bta_phy_timing(struct tegra_dc_dsi_data *dsi,
744                 struct dsi_phy_timing_inclk *phy_timing_clk, u32 clk_ns)
745 {
746         phy_timing_clk->t_tlpx = SELECT_T_PHY(
747                 dsi->info.phy_timing.t_tlpx_ns,
748                 T_TLPX_DEFAULT(clk_ns), clk_ns, T_TLPX_HW_INC);
749
750         phy_timing_clk->t_taget = SELECT_T_PHY(
751                 dsi->info.phy_timing.t_taget_ns,
752                 T_TAGET_DEFAULT(clk_ns), clk_ns, T_TAGET_HW_INC);
753
754         phy_timing_clk->t_tasure = SELECT_T_PHY(
755                 dsi->info.phy_timing.t_tasure_ns,
756                 T_TASURE_DEFAULT(clk_ns), clk_ns, T_TASURE_HW_INC);
757
758         phy_timing_clk->t_tago = SELECT_T_PHY(
759                 dsi->info.phy_timing.t_tago_ns,
760                 T_TAGO_DEFAULT(clk_ns), clk_ns, T_TAGO_HW_INC);
761 }
762
763 static void tegra_dsi_get_ulps_phy_timing(struct tegra_dc_dsi_data *dsi,
764                 struct dsi_phy_timing_inclk *phy_timing_clk, u32 clk_ns)
765 {
766         phy_timing_clk->t_tlpx = SELECT_T_PHY(
767                 dsi->info.phy_timing.t_tlpx_ns,
768                 T_TLPX_DEFAULT(clk_ns), clk_ns, T_TLPX_HW_INC);
769
770         phy_timing_clk->t_wakeup = SELECT_T_PHY(
771                 dsi->info.phy_timing.t_wakeup_ns,
772                 T_WAKEUP_DEFAULT, clk_ns, T_WAKEUP_HW_INC);
773 }
774
775 #undef SELECT_T_PHY
776
777 static void tegra_dsi_get_phy_timing(struct tegra_dc_dsi_data *dsi,
778                                 struct dsi_phy_timing_inclk *phy_timing_clk,
779                                 u32 clk_ns, u8 lphs)
780 {
781         if (!(dsi->info.ganged_type)) {
782 #ifndef CONFIG_TEGRA_SILICON_PLATFORM
783                 clk_ns = (1000 * 1000) / (dsi->info.fpga_freq_khz ?
784                         dsi->info.fpga_freq_khz : DEFAULT_FPGA_FREQ_KHZ);
785 #endif
786         }
787
788         phy_timing_clk->t_hsdexit = dsi->info.phy_timing.t_hsdexit_ns ?
789                         (dsi->info.phy_timing.t_hsdexit_ns / clk_ns) :
790                         (T_HSEXIT_DEFAULT(clk_ns));
791
792         if (lphs == DSI_LPHS_IN_HS_MODE) {
793                 tegra_dsi_get_clk_phy_timing(dsi, phy_timing_clk, clk_ns);
794                 tegra_dsi_get_hs_phy_timing(dsi, phy_timing_clk, clk_ns);
795         } else {
796                 /* default is LP mode */
797                 tegra_dsi_get_escape_phy_timing(dsi, phy_timing_clk, clk_ns);
798                 tegra_dsi_get_bta_phy_timing(dsi, phy_timing_clk, clk_ns);
799                 tegra_dsi_get_ulps_phy_timing(dsi, phy_timing_clk, clk_ns);
800                 if (dsi->info.enable_hs_clock_on_lp_cmd_mode)
801                         tegra_dsi_get_clk_phy_timing(dsi, phy_timing_clk, clk_ns);
802         }
803 }
804
805 static int tegra_dsi_mipi_phy_timing_range(struct tegra_dc_dsi_data *dsi,
806                                 struct dsi_phy_timing_inclk *phy_timing,
807                                 u32 clk_ns, u8 lphs)
808 {
809         int err = 0;
810
811 #define CHECK_RANGE(val, min, max) ( \
812                 ((min) == NOT_DEFINED ? 0 : (val) < (min)) || \
813                 ((max) == NOT_DEFINED ? 0 : (val) > (max)) ? -EINVAL : 0)
814
815 #ifndef CONFIG_TEGRA_SILICON_PLATFORM
816         clk_ns = dsi->info.fpga_freq_khz ?
817                 ((1000 * 1000) / dsi->info.fpga_freq_khz) :
818                 DEFAULT_FPGA_FREQ_KHZ;
819 #endif
820
821         err = CHECK_RANGE(
822         DSI_CONVERT_T_PHY_TO_T_PHY_NS(
823                         phy_timing->t_tlpx, clk_ns, T_TLPX_HW_INC),
824                         MIPI_T_TLPX_NS_MIN, MIPI_T_TLPX_NS_MAX);
825         if (err < 0) {
826                 dev_warn(&dsi->dc->ndev->dev,
827                         "dsi: Tlpx mipi range violated\n");
828                 goto fail;
829         }
830
831         if (lphs == DSI_LPHS_IN_HS_MODE) {
832                 err = CHECK_RANGE(
833                 DSI_CONVERT_T_PHY_TO_T_PHY_NS(
834                         phy_timing->t_hsdexit, clk_ns, T_HSEXIT_HW_INC),
835                         MIPI_T_HSEXIT_NS_MIN, MIPI_T_HSEXIT_NS_MAX);
836                 if (err < 0) {
837                         dev_warn(&dsi->dc->ndev->dev,
838                                 "dsi: HsExit mipi range violated\n");
839                         goto fail;
840                 }
841
842                 err = CHECK_RANGE(
843                 DSI_CONVERT_T_PHY_TO_T_PHY_NS(
844                         phy_timing->t_hstrail, clk_ns, T_HSTRAIL_HW_INC),
845                         MIPI_T_HSTRAIL_NS_MIN(clk_ns), MIPI_T_HSTRAIL_NS_MAX);
846                 if (err < 0) {
847                         dev_warn(&dsi->dc->ndev->dev,
848                                 "dsi: HsTrail mipi range violated\n");
849                         goto fail;
850                 }
851
852                 err = CHECK_RANGE(
853                 DSI_CONVERT_T_PHY_TO_T_PHY_NS(
854                         phy_timing->t_datzero, clk_ns, T_DATZERO_HW_INC),
855                         MIPI_T_HSZERO_NS_MIN, MIPI_T_HSZERO_NS_MAX);
856                 if (err < 0) {
857                         dev_warn(&dsi->dc->ndev->dev,
858                                 "dsi: HsZero mipi range violated\n");
859                         goto fail;
860                 }
861
862                 err = CHECK_RANGE(
863                 DSI_CONVERT_T_PHY_TO_T_PHY_NS(
864                         phy_timing->t_hsprepare, clk_ns, T_HSPREPARE_HW_INC),
865                         MIPI_T_HSPREPARE_NS_MIN(clk_ns),
866                         MIPI_T_HSPREPARE_NS_MAX(clk_ns));
867                 if (err < 0) {
868                         dev_warn(&dsi->dc->ndev->dev,
869                                 "dsi: HsPrepare mipi range violated\n");
870                         goto fail;
871                 }
872
873                 err = CHECK_RANGE(
874                 DSI_CONVERT_T_PHY_TO_T_PHY_NS(
875                 phy_timing->t_hsprepare, clk_ns, T_HSPREPARE_HW_INC) +
876                 DSI_CONVERT_T_PHY_TO_T_PHY_NS(
877                         phy_timing->t_datzero, clk_ns, T_DATZERO_HW_INC),
878                         MIPI_T_HSPREPARE_ADD_HSZERO_NS_MIN(clk_ns),
879                         MIPI_T_HSPREPARE_ADD_HSZERO_NS_MAX);
880                 if (err < 0) {
881                         dev_warn(&dsi->dc->ndev->dev,
882                         "dsi: HsPrepare + HsZero mipi range violated\n");
883                         goto fail;
884                 }
885         } else {
886                 /* default is LP mode */
887                 err = CHECK_RANGE(
888                 DSI_CONVERT_T_PHY_TO_T_PHY_NS(
889                         phy_timing->t_wakeup, clk_ns, T_WAKEUP_HW_INC),
890                         MIPI_T_WAKEUP_NS_MIN, MIPI_T_WAKEUP_NS_MAX);
891                 if (err < 0) {
892                         dev_warn(&dsi->dc->ndev->dev,
893                                 "dsi: WakeUp mipi range violated\n");
894                         goto fail;
895                 }
896
897                 err = CHECK_RANGE(
898                 DSI_CONVERT_T_PHY_TO_T_PHY_NS(
899                         phy_timing->t_tasure, clk_ns, T_TASURE_HW_INC),
900                         MIPI_T_TASURE_NS_MIN(DSI_CONVERT_T_PHY_TO_T_PHY_NS(
901                         phy_timing->t_tlpx, clk_ns, T_TLPX_HW_INC)),
902                         MIPI_T_TASURE_NS_MAX(DSI_CONVERT_T_PHY_TO_T_PHY_NS(
903                         phy_timing->t_tlpx, clk_ns, T_TLPX_HW_INC)));
904                 if (err < 0) {
905                         dev_warn(&dsi->dc->ndev->dev,
906                                 "dsi: TaSure mipi range violated\n");
907                         goto fail;
908                 }
909         }
910
911         if (lphs == DSI_LPHS_IN_HS_MODE ||
912                 dsi->info.enable_hs_clock_on_lp_cmd_mode) {
913                 err = CHECK_RANGE(
914                 DSI_CONVERT_T_PHY_TO_T_PHY_NS(
915                         phy_timing->t_clktrail, clk_ns, T_CLKTRAIL_HW_INC),
916                         MIPI_T_CLKTRAIL_NS_MIN, MIPI_T_CLKTRAIL_NS_MAX);
917                 if (err < 0) {
918                         dev_warn(&dsi->dc->ndev->dev,
919                                 "dsi: ClkTrail mipi range violated\n");
920                         goto fail;
921                 }
922
923                 err = CHECK_RANGE(
924                 DSI_CONVERT_T_PHY_TO_T_PHY_NS(
925                         phy_timing->t_clkpost, clk_ns, T_CLKPOST_HW_INC),
926                         MIPI_T_CLKPOST_NS_MIN(clk_ns), MIPI_T_CLKPOST_NS_MAX);
927                 if (err < 0) {
928                         dev_warn(&dsi->dc->ndev->dev,
929                                 "dsi: ClkPost mipi range violated\n");
930                         goto fail;
931                 }
932
933                 err = CHECK_RANGE(
934                 DSI_CONVERT_T_PHY_TO_T_PHY_NS(
935                         phy_timing->t_clkzero, clk_ns, T_CLKZERO_HW_INC),
936                         MIPI_T_CLKZERO_NS_MIN, MIPI_T_CLKZERO_NS_MAX);
937                 if (err < 0) {
938                         dev_warn(&dsi->dc->ndev->dev,
939                                 "dsi: ClkZero mipi range violated\n");
940                         goto fail;
941                 }
942
943                 err = CHECK_RANGE(
944                 DSI_CONVERT_T_PHY_TO_T_PHY_NS(
945                         phy_timing->t_clkprepare, clk_ns, T_CLKPREPARE_HW_INC),
946                         MIPI_T_CLKPREPARE_NS_MIN, MIPI_T_CLKPREPARE_NS_MAX);
947                 if (err < 0) {
948                         dev_warn(&dsi->dc->ndev->dev,
949                                 "dsi: ClkPrepare mipi range violated\n");
950                         goto fail;
951                 }
952
953                 err = CHECK_RANGE(
954                 DSI_CONVERT_T_PHY_TO_T_PHY_NS(
955                         phy_timing->t_clkpre, clk_ns, T_CLKPRE_HW_INC),
956                         MIPI_T_CLKPRE_NS_MIN, MIPI_T_CLKPRE_NS_MAX);
957                 if (err < 0) {
958                         dev_warn(&dsi->dc->ndev->dev,
959                                 "dsi: ClkPre mipi range violated\n");
960                         goto fail;
961                 }
962
963                 err = CHECK_RANGE(
964                 DSI_CONVERT_T_PHY_TO_T_PHY_NS(
965                 phy_timing->t_clkprepare, clk_ns, T_CLKPREPARE_HW_INC) +
966                 DSI_CONVERT_T_PHY_TO_T_PHY_NS(
967                         phy_timing->t_clkzero, clk_ns, T_CLKZERO_HW_INC),
968                         MIPI_T_CLKPREPARE_ADD_CLKZERO_NS_MIN,
969                         MIPI_T_CLKPREPARE_ADD_CLKZERO_NS_MAX);
970                 if (err < 0) {
971                         dev_warn(&dsi->dc->ndev->dev,
972                         "dsi: ClkPrepare + ClkZero mipi range violated\n");
973                         goto fail;
974                 }
975         }
976 fail:
977 #undef CHECK_RANGE
978         return err;
979 }
980
981 static int tegra_dsi_hs_phy_len(struct tegra_dc_dsi_data *dsi,
982                                 struct dsi_phy_timing_inclk *phy_timing,
983                                 u32 clk_ns, u8 lphs)
984 {
985         u32 hs_t_phy_ns;
986         u32 clk_t_phy_ns;
987         u32 t_phy_ns;
988         u32 h_blank_ns;
989         struct tegra_dc_mode *modes;
990         u32 t_pix_ns;
991         int err = 0;
992
993         if (!(lphs == DSI_LPHS_IN_HS_MODE))
994                 goto fail;
995
996         modes = dsi->dc->out->modes;
997         t_pix_ns = clk_ns * BITS_PER_BYTE *
998                 dsi->pixel_scaler_mul / dsi->pixel_scaler_div;
999
1000         hs_t_phy_ns =
1001                 DSI_CONVERT_T_PHY_TO_T_PHY_NS(
1002                 phy_timing->t_tlpx, clk_ns, T_TLPX_HW_INC) +
1003                 DSI_CONVERT_T_PHY_TO_T_PHY_NS(
1004                 phy_timing->t_hsprepare, clk_ns, T_HSPREPARE_HW_INC) +
1005                 DSI_CONVERT_T_PHY_TO_T_PHY_NS(
1006                 phy_timing->t_datzero, clk_ns, T_DATZERO_HW_INC) +
1007                 DSI_CONVERT_T_PHY_TO_T_PHY_NS(
1008                 phy_timing->t_hstrail, clk_ns, T_HSTRAIL_HW_INC) +
1009                 DSI_CONVERT_T_PHY_TO_T_PHY_NS(
1010                 phy_timing->t_hsdexit, clk_ns, T_HSEXIT_HW_INC);
1011
1012         clk_t_phy_ns =
1013                 DSI_CONVERT_T_PHY_TO_T_PHY_NS(
1014                 phy_timing->t_clkpost, clk_ns, T_CLKPOST_HW_INC) +
1015                 DSI_CONVERT_T_PHY_TO_T_PHY_NS(
1016                 phy_timing->t_clktrail, clk_ns, T_CLKTRAIL_HW_INC) +
1017                 DSI_CONVERT_T_PHY_TO_T_PHY_NS(
1018                 phy_timing->t_hsdexit, clk_ns, T_HSEXIT_HW_INC) +
1019                 DSI_CONVERT_T_PHY_TO_T_PHY_NS(
1020                 phy_timing->t_tlpx, clk_ns, T_TLPX_HW_INC) +
1021                 DSI_CONVERT_T_PHY_TO_T_PHY_NS(
1022                 phy_timing->t_clkprepare, clk_ns, T_CLKPREPARE_HW_INC) +
1023                 DSI_CONVERT_T_PHY_TO_T_PHY_NS(
1024                 phy_timing->t_clkzero, clk_ns, T_CLKZERO_HW_INC) +
1025                 DSI_CONVERT_T_PHY_TO_T_PHY_NS(
1026                 phy_timing->t_clkpre, clk_ns, T_CLKPRE_HW_INC);
1027
1028         h_blank_ns = t_pix_ns * (modes->h_sync_width + modes->h_back_porch +
1029                                                 modes->h_front_porch);
1030
1031         /* Extra tlpx and byte cycle required by dsi HW */
1032         t_phy_ns = dsi->info.n_data_lanes * (hs_t_phy_ns + clk_t_phy_ns +
1033                 DSI_CONVERT_T_PHY_TO_T_PHY_NS(
1034                 phy_timing->t_tlpx, clk_ns, T_TLPX_HW_INC) +
1035                 clk_ns * BITS_PER_BYTE);
1036
1037         if (h_blank_ns < t_phy_ns) {
1038                 err = -EINVAL;
1039                 dev_err(&dsi->dc->ndev->dev,
1040                         "dsi: Hblank is smaller than HS trans phy timing\n");
1041                 goto fail;
1042         }
1043
1044         return 0;
1045 fail:
1046         return err;
1047 }
1048
1049 static int tegra_dsi_constraint_phy_timing(struct tegra_dc_dsi_data *dsi,
1050                                 struct dsi_phy_timing_inclk *phy_timing,
1051                                 u32 clk_ns, u8 lphs)
1052 {
1053         int err = 0;
1054
1055         err = tegra_dsi_mipi_phy_timing_range(dsi, phy_timing, clk_ns, lphs);
1056         if (err < 0) {
1057                 dev_warn(&dsi->dc->ndev->dev, "dsi: mipi range violated\n");
1058                 goto fail;
1059         }
1060
1061         err = tegra_dsi_hs_phy_len(dsi, phy_timing, clk_ns, lphs);
1062         if (err < 0) {
1063                 dev_err(&dsi->dc->ndev->dev, "dsi: Hblank too short\n");
1064                 goto fail;
1065         }
1066
1067         /* TODO: add more contraints */
1068 fail:
1069         return err;
1070 }
1071
1072 static void tegra_dsi_set_phy_timing(struct tegra_dc_dsi_data *dsi, u8 lphs)
1073 {
1074         u32 val;
1075         struct dsi_phy_timing_inclk phy_timing = dsi->phy_timing;
1076
1077         tegra_dsi_get_phy_timing
1078                 (dsi, &phy_timing, dsi->current_bit_clk_ns, lphs);
1079
1080         tegra_dsi_constraint_phy_timing(dsi, &phy_timing,
1081                                         dsi->current_bit_clk_ns, lphs);
1082
1083         if (dsi->info.ganged_type) {
1084 #ifndef CONFIG_TEGRA_SILICON_PLATFORM
1085                 phy_timing.t_hsdexit += T_HSEXIT_HW_INC;
1086                 phy_timing.t_hstrail += T_HSTRAIL_HW_INC + 3;
1087                 phy_timing.t_datzero += T_DATZERO_HW_INC;
1088                 phy_timing.t_hsprepare += T_HSPREPARE_HW_INC;
1089
1090                 phy_timing.t_clktrail += T_CLKTRAIL_HW_INC;
1091                 phy_timing.t_clkpost += T_CLKPOST_HW_INC;
1092                 phy_timing.t_clkzero += T_CLKZERO_HW_INC;
1093                 phy_timing.t_tlpx += T_TLPX_HW_INC;
1094
1095                 phy_timing.t_clkprepare += T_CLKPREPARE_HW_INC;
1096                 phy_timing.t_clkpre += T_CLKPRE_HW_INC;
1097                 phy_timing.t_wakeup += T_WAKEUP_HW_INC;
1098
1099                 phy_timing.t_taget += T_TAGET_HW_INC;
1100                 phy_timing.t_tasure += T_TASURE_HW_INC;
1101                 phy_timing.t_tago += T_TAGO_HW_INC;
1102 #endif
1103         }
1104
1105         val = DSI_PHY_TIMING_0_THSDEXIT(phy_timing.t_hsdexit) |
1106                         DSI_PHY_TIMING_0_THSTRAIL(phy_timing.t_hstrail) |
1107                         DSI_PHY_TIMING_0_TDATZERO(phy_timing.t_datzero) |
1108                         DSI_PHY_TIMING_0_THSPREPR(phy_timing.t_hsprepare);
1109         tegra_dsi_writel(dsi, val, DSI_PHY_TIMING_0);
1110
1111         val = DSI_PHY_TIMING_1_TCLKTRAIL(phy_timing.t_clktrail) |
1112                         DSI_PHY_TIMING_1_TCLKPOST(phy_timing.t_clkpost) |
1113                         DSI_PHY_TIMING_1_TCLKZERO(phy_timing.t_clkzero) |
1114                         DSI_PHY_TIMING_1_TTLPX(phy_timing.t_tlpx);
1115         tegra_dsi_writel(dsi, val, DSI_PHY_TIMING_1);
1116
1117         val = DSI_PHY_TIMING_2_TCLKPREPARE(phy_timing.t_clkprepare) |
1118                 DSI_PHY_TIMING_2_TCLKPRE(phy_timing.t_clkpre) |
1119                         DSI_PHY_TIMING_2_TWAKEUP(phy_timing.t_wakeup);
1120         tegra_dsi_writel(dsi, val, DSI_PHY_TIMING_2);
1121
1122         val = DSI_BTA_TIMING_TTAGET(phy_timing.t_taget) |
1123                         DSI_BTA_TIMING_TTASURE(phy_timing.t_tasure) |
1124                         DSI_BTA_TIMING_TTAGO(phy_timing.t_tago);
1125         tegra_dsi_writel(dsi, val, DSI_BTA_TIMING);
1126
1127         dsi->phy_timing = phy_timing;
1128 }
1129
1130 static u32 tegra_dsi_sol_delay_burst(struct tegra_dc *dc,
1131                                 struct tegra_dc_dsi_data *dsi)
1132 {
1133         u32 dsi_to_pixel_clk_ratio;
1134         u32 temp;
1135         u32 temp1;
1136         u32 mipi_clk_adj_kHz = 0;
1137         u32 sol_delay;
1138         struct tegra_dc_mode *dc_modes = &dc->mode;
1139
1140         /* Get Fdsi/Fpixel ration (note: Fdsi is in bit format) */
1141         dsi_to_pixel_clk_ratio = (dsi->current_dsi_clk_khz * 2 +
1142                 dsi->default_pixel_clk_khz - 1) / dsi->default_pixel_clk_khz;
1143
1144         /* Convert Fdsi to byte format */
1145         dsi_to_pixel_clk_ratio *= 1000/8;
1146
1147         /* Multiplying by 1000 so that we don't loose the fraction part */
1148         temp = dc_modes->h_active * 1000;
1149         temp1 = dc_modes->h_active + dc_modes->h_back_porch +
1150                         dc_modes->h_sync_width;
1151
1152         sol_delay = temp1 * dsi_to_pixel_clk_ratio -
1153                         temp * dsi->pixel_scaler_mul /
1154                         (dsi->pixel_scaler_div * dsi->info.n_data_lanes);
1155
1156         /* Do rounding on sol delay */
1157         sol_delay = (sol_delay + 1000 - 1)/1000;
1158
1159         /* TODO:
1160          * 1. find out the correct sol fifo depth to use
1161          * 2. verify with hw about the clamping function
1162          */
1163         if (sol_delay > (480 * 4)) {
1164                 sol_delay = (480 * 4);
1165                 mipi_clk_adj_kHz = sol_delay +
1166                         (dc_modes->h_active * dsi->pixel_scaler_mul) /
1167                         (dsi->info.n_data_lanes * dsi->pixel_scaler_div);
1168
1169                 mipi_clk_adj_kHz *= (dsi->default_pixel_clk_khz / temp1);
1170
1171                 mipi_clk_adj_kHz *= 4;
1172         }
1173
1174         dsi->target_hs_clk_khz = mipi_clk_adj_kHz;
1175
1176         return sol_delay;
1177 }
1178
1179 static void tegra_dsi_set_sol_delay(struct tegra_dc *dc,
1180                                 struct tegra_dc_dsi_data *dsi)
1181 {
1182         u32 sol_delay;
1183         u32 internal_delay;
1184         u32 h_width_byte_clk;
1185         u32 h_width_pixels;
1186         u32 h_width_ganged_byte_clk;
1187         u8 n_data_lanes_this_cont = 0;
1188         u8 n_data_lanes_ganged = 0;
1189
1190         if (!(dsi->info.ganged_type)) {
1191                 if (dsi->info.video_burst_mode ==
1192                         TEGRA_DSI_VIDEO_NONE_BURST_MODE ||
1193                         dsi->info.video_burst_mode ==
1194                         TEGRA_DSI_VIDEO_NONE_BURST_MODE_WITH_SYNC_END) {
1195 #define VIDEO_FIFO_LATENCY_PIXEL_CLK 8
1196                         sol_delay = VIDEO_FIFO_LATENCY_PIXEL_CLK *
1197                                 dsi->pixel_scaler_mul / dsi->pixel_scaler_div;
1198 #undef VIDEO_FIFO_LATENCY_PIXEL_CLK
1199                         dsi->status.clk_burst = DSI_CLK_BURST_NONE_BURST;
1200                 } else {
1201                         sol_delay = tegra_dsi_sol_delay_burst(dc, dsi);
1202                         dsi->status.clk_burst = DSI_CLK_BURST_BURST_MODE;
1203                 }
1204         } else {
1205 #define SOL_TO_VALID_PIX_CLK_DELAY 4
1206 #define VALID_TO_FIFO_PIX_CLK_DELAY 4
1207 #define FIFO_WR_PIX_CLK_DELAY 2
1208 #define FIFO_RD_BYTE_CLK_DELAY 6
1209 #define TOT_INTERNAL_PIX_DELAY (SOL_TO_VALID_PIX_CLK_DELAY + \
1210                                 VALID_TO_FIFO_PIX_CLK_DELAY + \
1211                                 FIFO_WR_PIX_CLK_DELAY)
1212
1213                 internal_delay = DIV_ROUND_UP(
1214                                 TOT_INTERNAL_PIX_DELAY * dsi->pixel_scaler_mul,
1215                                 dsi->pixel_scaler_div * dsi->info.n_data_lanes)
1216                                 + FIFO_RD_BYTE_CLK_DELAY;
1217
1218                 h_width_pixels = dc->mode.h_sync_width +
1219                                         dc->mode.h_back_porch +
1220                                         dc->mode.h_active +
1221                                         dc->mode.h_front_porch;
1222
1223                 h_width_byte_clk = DIV_ROUND_UP(h_width_pixels *
1224                                         dsi->pixel_scaler_mul,
1225                                         dsi->pixel_scaler_div *
1226                                         dsi->info.n_data_lanes);
1227
1228                 if (dsi->info.ganged_type ==
1229                         TEGRA_DSI_GANGED_SYMMETRIC_LEFT_RIGHT ||
1230                         dsi->info.ganged_type ==
1231                         TEGRA_DSI_GANGED_SYMMETRIC_EVEN_ODD) {
1232                         n_data_lanes_this_cont = dsi->info.n_data_lanes / 2;
1233                         n_data_lanes_ganged = dsi->info.n_data_lanes;
1234                 }
1235
1236                 h_width_ganged_byte_clk = DIV_ROUND_UP(
1237                                         n_data_lanes_this_cont *
1238                                         h_width_byte_clk,
1239                                         n_data_lanes_ganged);
1240
1241                 sol_delay = h_width_byte_clk - h_width_ganged_byte_clk +
1242                                                         internal_delay;
1243                 sol_delay = (dsi->info.video_data_type ==
1244                                 TEGRA_DSI_VIDEO_TYPE_COMMAND_MODE) ?
1245                                 sol_delay + 20: sol_delay;
1246
1247 #undef SOL_TO_VALID_PIX_CLK_DELAY
1248 #undef VALID_TO_FIFO_PIX_CLK_DELAY
1249 #undef FIFO_WR_PIX_CLK_DELAY
1250 #undef FIFO_RD_BYTE_CLK_DELAY
1251 #undef TOT_INTERNAL_PIX_DELAY
1252         }
1253
1254         tegra_dsi_writel(dsi, DSI_SOL_DELAY_SOL_DELAY(sol_delay),
1255                                                 DSI_SOL_DELAY);
1256 }
1257
1258 static void tegra_dsi_set_timeout(struct tegra_dc_dsi_data *dsi)
1259 {
1260         u32 val;
1261         u32 bytes_per_frame;
1262         u32 timeout = 0;
1263
1264         /* TODO: verify the following equation */
1265         bytes_per_frame = dsi->current_dsi_clk_khz * 1000 * 2 /
1266                                                 (dsi->info.refresh_rate * 8);
1267         timeout = bytes_per_frame / DSI_CYCLE_COUNTER_VALUE;
1268         timeout = (timeout + DSI_HTX_TO_MARGIN) & 0xffff;
1269
1270         val = DSI_TIMEOUT_0_LRXH_TO(DSI_LRXH_TO_VALUE) |
1271                         DSI_TIMEOUT_0_HTX_TO(timeout);
1272         tegra_dsi_writel(dsi, val, DSI_TIMEOUT_0);
1273
1274         if (dsi->info.panel_reset_timeout_msec)
1275                 timeout = (dsi->info.panel_reset_timeout_msec * 1000*1000)
1276                                         / dsi->current_bit_clk_ns;
1277         else
1278                 timeout = DSI_PR_TO_VALUE;
1279
1280         val = DSI_TIMEOUT_1_PR_TO(timeout) |
1281                 DSI_TIMEOUT_1_TA_TO(DSI_TA_TO_VALUE);
1282         tegra_dsi_writel(dsi, val, DSI_TIMEOUT_1);
1283
1284         val = DSI_TO_TALLY_P_RESET_STATUS(IN_RESET) |
1285                 DSI_TO_TALLY_TA_TALLY(DSI_TA_TALLY_VALUE)|
1286                 DSI_TO_TALLY_LRXH_TALLY(DSI_LRXH_TALLY_VALUE)|
1287                 DSI_TO_TALLY_HTX_TALLY(DSI_HTX_TALLY_VALUE);
1288         tegra_dsi_writel(dsi, val, DSI_TO_TALLY);
1289 }
1290
1291 static void tegra_dsi_setup_ganged_mode_pkt_length(struct tegra_dc *dc,
1292                                                 struct tegra_dc_dsi_data *dsi)
1293 {
1294         u32 hact_pkt_len_pix_orig = dc->mode.h_active;
1295         u32 hact_pkt_len_pix = 0;
1296         u32 hact_pkt_len_bytes = 0;
1297         u32 hfp_pkt_len_bytes = 0;
1298         u32 pix_per_line_orig = 0;
1299         u32 pix_per_line = 0;
1300         u32 val = 0;
1301
1302 /* hsync + hact + hfp = (4) + (4+2) + (4+2) */
1303 #define HEADER_OVERHEAD 16
1304
1305         pix_per_line_orig = dc->mode.h_sync_width + dc->mode.h_back_porch +
1306                         dc->mode.h_active + dc->mode.h_front_porch;
1307
1308         if (dsi->info.ganged_type == TEGRA_DSI_GANGED_SYMMETRIC_LEFT_RIGHT ||
1309                 dsi->info.ganged_type == TEGRA_DSI_GANGED_SYMMETRIC_EVEN_ODD) {
1310                 hact_pkt_len_pix = DIV_ROUND_UP(hact_pkt_len_pix_orig, 2);
1311                 pix_per_line = DIV_ROUND_UP(pix_per_line_orig, 2);
1312                 if (dsi->controller_index) {
1313                         hact_pkt_len_pix =
1314                                 hact_pkt_len_pix_orig - hact_pkt_len_pix;
1315                         pix_per_line = pix_per_line_orig - pix_per_line;
1316                 }
1317                 hact_pkt_len_bytes = hact_pkt_len_pix *
1318                         dsi->pixel_scaler_mul / dsi->pixel_scaler_div;
1319                 hfp_pkt_len_bytes = pix_per_line *
1320                         dsi->pixel_scaler_mul / dsi->pixel_scaler_div -
1321                         hact_pkt_len_bytes - HEADER_OVERHEAD;
1322         }
1323
1324         val = DSI_PKT_LEN_0_1_LENGTH_0(0) |
1325                 DSI_PKT_LEN_0_1_LENGTH_1(0);
1326         tegra_dsi_writel(dsi, val, DSI_PKT_LEN_0_1);
1327
1328         val = DSI_PKT_LEN_2_3_LENGTH_2(0x0) |
1329                 DSI_PKT_LEN_2_3_LENGTH_3(hact_pkt_len_bytes);
1330         tegra_dsi_writel(dsi, val, DSI_PKT_LEN_2_3);
1331
1332         val = DSI_PKT_LEN_4_5_LENGTH_4(hfp_pkt_len_bytes) |
1333                 DSI_PKT_LEN_4_5_LENGTH_5(0);
1334         tegra_dsi_writel(dsi, val, DSI_PKT_LEN_4_5);
1335
1336         val = DSI_PKT_LEN_6_7_LENGTH_6(0) |
1337                 DSI_PKT_LEN_6_7_LENGTH_7(0);
1338         tegra_dsi_writel(dsi, val, DSI_PKT_LEN_6_7);
1339
1340 #undef HEADER_OVERHEAD
1341 }
1342
1343 static void tegra_dsi_setup_video_mode_pkt_length(struct tegra_dc *dc,
1344                                                 struct tegra_dc_dsi_data *dsi)
1345 {
1346         u32 val;
1347         u32 hact_pkt_len;
1348         u32 hsa_pkt_len;
1349         u32 hbp_pkt_len;
1350         u32 hfp_pkt_len;
1351
1352         hact_pkt_len = dc->mode.h_active * dsi->pixel_scaler_mul /
1353                                                         dsi->pixel_scaler_div;
1354         hsa_pkt_len = dc->mode.h_sync_width * dsi->pixel_scaler_mul /
1355                                                         dsi->pixel_scaler_div;
1356         hbp_pkt_len = dc->mode.h_back_porch * dsi->pixel_scaler_mul /
1357                                                         dsi->pixel_scaler_div;
1358         hfp_pkt_len = dc->mode.h_front_porch * dsi->pixel_scaler_mul /
1359                                                         dsi->pixel_scaler_div;
1360
1361         if (dsi->info.video_burst_mode !=
1362                                 TEGRA_DSI_VIDEO_NONE_BURST_MODE_WITH_SYNC_END)
1363                 hbp_pkt_len += hsa_pkt_len;
1364
1365         hsa_pkt_len -= DSI_HSYNC_BLNK_PKT_OVERHEAD;
1366         hbp_pkt_len -= DSI_HBACK_PORCH_PKT_OVERHEAD;
1367         hfp_pkt_len -= DSI_HFRONT_PORCH_PKT_OVERHEAD;
1368
1369         val = DSI_PKT_LEN_0_1_LENGTH_0(0) |
1370                         DSI_PKT_LEN_0_1_LENGTH_1(hsa_pkt_len);
1371         tegra_dsi_writel(dsi, val, DSI_PKT_LEN_0_1);
1372
1373         val = DSI_PKT_LEN_2_3_LENGTH_2(hbp_pkt_len) |
1374                         DSI_PKT_LEN_2_3_LENGTH_3(hact_pkt_len);
1375         tegra_dsi_writel(dsi, val, DSI_PKT_LEN_2_3);
1376
1377         val = DSI_PKT_LEN_4_5_LENGTH_4(hfp_pkt_len) |
1378                         DSI_PKT_LEN_4_5_LENGTH_5(0);
1379         tegra_dsi_writel(dsi, val, DSI_PKT_LEN_4_5);
1380
1381         val = DSI_PKT_LEN_6_7_LENGTH_6(0) | DSI_PKT_LEN_6_7_LENGTH_7(0);
1382         tegra_dsi_writel(dsi, val, DSI_PKT_LEN_6_7);
1383 }
1384
1385 static void tegra_dsi_setup_cmd_mode_pkt_length(struct tegra_dc *dc,
1386                                                 struct tegra_dc_dsi_data *dsi)
1387 {
1388         unsigned long   val;
1389         unsigned long   act_bytes;
1390
1391         act_bytes = dc->mode.h_active * dsi->pixel_scaler_mul /
1392                         dsi->pixel_scaler_div + 1;
1393
1394         val = DSI_PKT_LEN_0_1_LENGTH_0(0) | DSI_PKT_LEN_0_1_LENGTH_1(0);
1395         tegra_dsi_writel(dsi, val, DSI_PKT_LEN_0_1);
1396
1397         val = DSI_PKT_LEN_2_3_LENGTH_2(0) | DSI_PKT_LEN_2_3_LENGTH_3(act_bytes);
1398         tegra_dsi_writel(dsi, val, DSI_PKT_LEN_2_3);
1399
1400         val = DSI_PKT_LEN_4_5_LENGTH_4(0) | DSI_PKT_LEN_4_5_LENGTH_5(act_bytes);
1401         tegra_dsi_writel(dsi, val, DSI_PKT_LEN_4_5);
1402
1403         val = DSI_PKT_LEN_6_7_LENGTH_6(0) | DSI_PKT_LEN_6_7_LENGTH_7(0x0f0f);
1404         tegra_dsi_writel(dsi, val, DSI_PKT_LEN_6_7);
1405 }
1406
1407 static void tegra_dsi_set_pkt_length(struct tegra_dc *dc,
1408                                 struct tegra_dc_dsi_data *dsi)
1409 {
1410         if (dsi->driven_mode == TEGRA_DSI_DRIVEN_BY_HOST)
1411                 return;
1412
1413         if (dsi->info.video_data_type == TEGRA_DSI_VIDEO_TYPE_VIDEO_MODE) {
1414                 if (dsi->info.ganged_type)
1415                         tegra_dsi_setup_ganged_mode_pkt_length(dc, dsi);
1416                 else
1417                         tegra_dsi_setup_video_mode_pkt_length(dc, dsi);
1418         } else {
1419                 tegra_dsi_setup_cmd_mode_pkt_length(dc, dsi);
1420         }
1421 }
1422
1423 static void tegra_dsi_set_pkt_seq(struct tegra_dc *dc,
1424                                 struct tegra_dc_dsi_data *dsi)
1425 {
1426         const u32 *pkt_seq;
1427         u32 rgb_info;
1428         u32 pkt_seq_3_5_rgb_lo;
1429         u32 pkt_seq_3_5_rgb_hi;
1430         u32     val;
1431         u32 reg;
1432         u8  i;
1433
1434         if (dsi->driven_mode == TEGRA_DSI_DRIVEN_BY_HOST)
1435                 return;
1436
1437         switch (dsi->info.pixel_format) {
1438         case TEGRA_DSI_PIXEL_FORMAT_16BIT_P:
1439                 rgb_info = CMD_RGB_16BPP;
1440                 break;
1441         case TEGRA_DSI_PIXEL_FORMAT_18BIT_P:
1442                 rgb_info = CMD_RGB_18BPP;
1443                 break;
1444         case TEGRA_DSI_PIXEL_FORMAT_18BIT_NP:
1445                 rgb_info = CMD_RGB_18BPPNP;
1446                 break;
1447         case TEGRA_DSI_PIXEL_FORMAT_24BIT_P:
1448         default:
1449                 rgb_info = CMD_RGB_24BPP;
1450                 break;
1451         }
1452
1453         pkt_seq_3_5_rgb_lo = 0;
1454         pkt_seq_3_5_rgb_hi = 0;
1455         if (dsi->info.video_data_type == TEGRA_DSI_VIDEO_TYPE_COMMAND_MODE)
1456                 pkt_seq = dsi_pkt_seq_cmd_mode;
1457         else {
1458                 switch (dsi->info.video_burst_mode) {
1459                 case TEGRA_DSI_VIDEO_BURST_MODE_LOWEST_SPEED:
1460                 case TEGRA_DSI_VIDEO_BURST_MODE_LOW_SPEED:
1461                 case TEGRA_DSI_VIDEO_BURST_MODE_MEDIUM_SPEED:
1462                 case TEGRA_DSI_VIDEO_BURST_MODE_FAST_SPEED:
1463                 case TEGRA_DSI_VIDEO_BURST_MODE_FASTEST_SPEED:
1464                         pkt_seq_3_5_rgb_lo =
1465                                         DSI_PKT_SEQ_3_LO_PKT_32_ID(rgb_info);
1466                         if (!dsi->info.no_pkt_seq_eot)
1467                                 pkt_seq = dsi_pkt_seq_video_burst;
1468                         else
1469                                 pkt_seq = dsi_pkt_seq_video_burst_no_eot;
1470                         break;
1471                 case TEGRA_DSI_VIDEO_NONE_BURST_MODE_WITH_SYNC_END:
1472                         pkt_seq_3_5_rgb_hi =
1473                                         DSI_PKT_SEQ_3_HI_PKT_34_ID(rgb_info);
1474                         pkt_seq = dsi_pkt_seq_video_non_burst_syne;
1475                         break;
1476                 case TEGRA_DSI_VIDEO_NONE_BURST_MODE:
1477                 default:
1478                         if (dsi->info.ganged_type) {
1479                                 pkt_seq_3_5_rgb_lo =
1480                                         DSI_PKT_SEQ_3_LO_PKT_31_ID(rgb_info);
1481                                 pkt_seq =
1482                                 dsi_pkt_seq_video_non_burst_no_eot_no_lp_no_hbp;
1483                         } else {
1484                                 pkt_seq_3_5_rgb_lo =
1485                                         DSI_PKT_SEQ_3_LO_PKT_32_ID(rgb_info);
1486                                 pkt_seq = dsi_pkt_seq_video_non_burst;
1487                         }
1488                         break;
1489                 }
1490         }
1491
1492         for (i = 0; i < NUMOF_PKT_SEQ; i++) {
1493                 val = pkt_seq[i];
1494                 reg = dsi_pkt_seq_reg[i];
1495                 if ((reg == DSI_PKT_SEQ_3_LO) || (reg == DSI_PKT_SEQ_5_LO))
1496                         val |= pkt_seq_3_5_rgb_lo;
1497                 if ((reg == DSI_PKT_SEQ_3_HI) || (reg == DSI_PKT_SEQ_5_HI))
1498                         val |= pkt_seq_3_5_rgb_hi;
1499                 tegra_dsi_writel(dsi, val, reg);
1500         }
1501 }
1502
1503 static void tegra_dsi_reset_underflow_overflow
1504                                 (struct tegra_dc_dsi_data *dsi)
1505 {
1506         u32 val;
1507
1508         val = tegra_dsi_readl(dsi, DSI_STATUS);
1509         val &= (DSI_STATUS_LB_OVERFLOW(0x1) | DSI_STATUS_LB_UNDERFLOW(0x1));
1510         if (val) {
1511                 if (val & DSI_STATUS_LB_OVERFLOW(0x1))
1512                         dev_warn(&dsi->dc->ndev->dev,
1513                                 "dsi: video fifo overflow. Resetting flag\n");
1514                 if (val & DSI_STATUS_LB_UNDERFLOW(0x1))
1515                         dev_warn(&dsi->dc->ndev->dev,
1516                                 "dsi: video fifo underflow. Resetting flag\n");
1517                 val = tegra_dsi_readl(dsi, DSI_HOST_DSI_CONTROL);
1518                 val |= DSI_HOST_CONTROL_FIFO_STAT_RESET(0x1);
1519                 tegra_dsi_writel(dsi, val, DSI_HOST_DSI_CONTROL);
1520                 udelay(5);
1521         }
1522 }
1523
1524 static void tegra_dsi_soft_reset(struct tegra_dc_dsi_data *dsi)
1525 {
1526         u32 trigger;
1527
1528         tegra_dsi_writel(dsi,
1529                 DSI_POWER_CONTROL_LEG_DSI_ENABLE(TEGRA_DSI_DISABLE),
1530                 DSI_POWER_CONTROL);
1531         /* stabilization delay */
1532         udelay(300);
1533
1534         tegra_dsi_writel(dsi,
1535                 DSI_POWER_CONTROL_LEG_DSI_ENABLE(TEGRA_DSI_ENABLE),
1536                 DSI_POWER_CONTROL);
1537         /* stabilization delay */
1538         udelay(300);
1539
1540         /* dsi HW does not clear host trigger bit automatically
1541          * on dsi interface disable if host fifo is empty or in mid
1542          * of host transmission
1543          */
1544         trigger = tegra_dsi_readl(dsi, DSI_TRIGGER);
1545         if (trigger)
1546                 tegra_dsi_writel(dsi, 0x0, DSI_TRIGGER);
1547 }
1548
1549 static void tegra_dsi_stop_dc_stream(struct tegra_dc *dc,
1550                                         struct tegra_dc_dsi_data *dsi)
1551 {
1552         tegra_dc_writel(dc, DISP_CTRL_MODE_STOP, DC_CMD_DISPLAY_COMMAND);
1553         tegra_dc_writel(dc, 0, DC_DISP_DISP_WIN_OPTIONS);
1554         tegra_dc_writel(dc, GENERAL_UPDATE, DC_CMD_STATE_CONTROL);
1555         tegra_dc_writel(dc, GENERAL_ACT_REQ , DC_CMD_STATE_CONTROL);
1556
1557         dsi->status.dc_stream = DSI_DC_STREAM_DISABLE;
1558 }
1559
1560 static void tegra_dsi_stop_dc_stream_at_frame_end(struct tegra_dc *dc,
1561                                                 struct tegra_dc_dsi_data *dsi)
1562 {
1563         int val;
1564         long timeout;
1565         u32 frame_period = DIV_ROUND_UP(S_TO_MS(1), dsi->info.refresh_rate);
1566
1567         INIT_COMPLETION(dc->frame_end_complete);
1568
1569         /* unmask frame end interrupt */
1570         val = tegra_dc_readl(dc, DC_CMD_INT_MASK);
1571         tegra_dc_writel(dc, val | FRAME_END_INT, DC_CMD_INT_MASK);
1572
1573         tegra_dsi_stop_dc_stream(dc, dsi);
1574
1575         /* wait for frame_end completion.
1576          * timeout is 2 frame duration to accomodate for
1577          * internal delay.
1578          */
1579         timeout = wait_for_completion_interruptible_timeout(
1580                         &dc->frame_end_complete,
1581                         msecs_to_jiffies(2 * frame_period));
1582
1583         /* give 2 line time to dsi HW to catch up
1584          * with pixels sent by dc
1585          */
1586         udelay(50);
1587
1588         tegra_dsi_soft_reset(dsi);
1589
1590         /* reinstate interrupt mask */
1591         tegra_dc_writel(dc, val, DC_CMD_INT_MASK);
1592
1593         if (timeout == 0)
1594                 dev_warn(&dc->ndev->dev,
1595                         "DC doesn't stop at end of frame.\n");
1596
1597         tegra_dsi_reset_underflow_overflow(dsi);
1598 }
1599
1600 static void tegra_dsi_start_dc_stream(struct tegra_dc *dc,
1601                                         struct tegra_dc_dsi_data *dsi)
1602 {
1603         u32 val;
1604
1605         tegra_dc_writel(dc, DSI_ENABLE, DC_DISP_DISP_WIN_OPTIONS);
1606
1607         /* TODO: clean up */
1608         tegra_dc_writel(dc, PW0_ENABLE | PW1_ENABLE | PW2_ENABLE | PW3_ENABLE |
1609                         PW4_ENABLE | PM0_ENABLE | PM1_ENABLE,
1610                         DC_CMD_DISPLAY_POWER_CONTROL);
1611
1612         /* Configure one-shot mode or continuous mode */
1613         if (dc->out->flags & TEGRA_DC_OUT_ONE_SHOT_MODE) {
1614                 /* disable LSPI/LCD_DE output */
1615                 val = PIN_OUTPUT_LSPI_OUTPUT_DIS;
1616                 tegra_dc_writel(dc, val, DC_COM_PIN_OUTPUT_ENABLE3);
1617
1618                 /* enable MSF & set MSF polarity */
1619                 val = MSF_ENABLE | MSF_LSPI;
1620                 if (!dsi->info.te_polarity_low)
1621                         val |= MSF_POLARITY_HIGH;
1622                 else
1623                         val |= MSF_POLARITY_LOW;
1624                 tegra_dc_writel(dc, val, DC_CMD_DISPLAY_COMMAND_OPTION0);
1625
1626                 /* set non-continuous mode */
1627                 tegra_dc_writel(dc, DISP_CTRL_MODE_NC_DISPLAY,
1628                                                 DC_CMD_DISPLAY_COMMAND);
1629                 tegra_dc_writel(dc, GENERAL_UPDATE, DC_CMD_STATE_CONTROL);
1630                 tegra_dc_writel(dc, GENERAL_ACT_REQ | NC_HOST_TRIG,
1631                                                 DC_CMD_STATE_CONTROL);
1632         } else {
1633                 /* set continuous mode */
1634                 tegra_dc_writel(dc, DISP_CTRL_MODE_C_DISPLAY,
1635                                                 DC_CMD_DISPLAY_COMMAND);
1636                 tegra_dc_writel(dc, GENERAL_UPDATE, DC_CMD_STATE_CONTROL);
1637                 tegra_dc_writel(dc, GENERAL_ACT_REQ, DC_CMD_STATE_CONTROL);
1638         }
1639
1640         dsi->status.dc_stream = DSI_DC_STREAM_ENABLE;
1641 }
1642
1643 static void tegra_dsi_set_dc_clk(struct tegra_dc *dc,
1644                                 struct tegra_dc_dsi_data *dsi)
1645 {
1646         u32 shift_clk_div_register;
1647         u32 val;
1648
1649         /* Get the corresponding register value of shift_clk_div. */
1650         shift_clk_div_register = dsi->shift_clk_div * 2 - 2;
1651
1652 #ifndef CONFIG_TEGRA_SILICON_PLATFORM
1653         shift_clk_div_register = 1;
1654         if (dsi->info.ganged_type)
1655                 shift_clk_div_register = 0;
1656 #endif
1657
1658         /* TODO: find out if PCD3 option is required */
1659         val = PIXEL_CLK_DIVIDER_PCD1 |
1660                 SHIFT_CLK_DIVIDER(shift_clk_div_register);
1661         tegra_dc_writel(dc, val, DC_DISP_DISP_CLOCK_CONTROL);
1662 }
1663
1664 static void tegra_dsi_set_dsi_clk(struct tegra_dc *dc,
1665                         struct tegra_dc_dsi_data *dsi, u32 clk)
1666 {
1667         u32 rm;
1668
1669         /* Round up to MHz */
1670         rm = clk % 1000;
1671         if (rm != 0)
1672                 clk -= rm;
1673
1674         /* Set up pixel clock */
1675         dc->shift_clk_div = dsi->shift_clk_div;
1676         dc->mode.pclk = (clk * 1000) / dsi->shift_clk_div;
1677         /* TODO: Define one shot work delay in board file. */
1678         /* Since for one-shot mode, refresh rate is usually set larger than
1679          * expected refresh rate, it needs at least 3 frame period. Less
1680          * delay one shot work is, more powering saving we have. */
1681         dc->one_shot_delay_ms = 4 *
1682                         DIV_ROUND_UP(S_TO_MS(1), dsi->info.refresh_rate);
1683
1684         /* Enable DSI clock */
1685         tegra_dc_setup_clk(dc, dsi->dsi_clk);
1686         tegra_dsi_clk_enable(dsi);
1687         tegra_periph_reset_deassert(dsi->dsi_clk);
1688
1689         dsi->current_dsi_clk_khz = clk_get_rate(dsi->dsi_clk) / 1000;
1690         dsi->current_bit_clk_ns =  1000*1000 / (dsi->current_dsi_clk_khz * 2);
1691 }
1692
1693 static void tegra_dsi_hs_clk_out_enable(struct tegra_dc_dsi_data *dsi)
1694 {
1695         u32 val;
1696
1697         val = tegra_dsi_readl(dsi, DSI_CONTROL);
1698         val &= ~DSI_CONTROL_HS_CLK_CTRL(1);
1699
1700         if (dsi->info.video_clock_mode == TEGRA_DSI_VIDEO_CLOCK_CONTINUOUS) {
1701                 val |= DSI_CONTROL_HS_CLK_CTRL(CONTINUOUS);
1702                 dsi->status.clk_mode = DSI_PHYCLK_CONTINUOUS;
1703         } else {
1704                 val |= DSI_CONTROL_HS_CLK_CTRL(TX_ONLY);
1705                 dsi->status.clk_mode = DSI_PHYCLK_TX_ONLY;
1706         }
1707         tegra_dsi_writel(dsi, val, DSI_CONTROL);
1708
1709         val = tegra_dsi_readl(dsi, DSI_HOST_DSI_CONTROL);
1710         val &= ~DSI_HOST_DSI_CONTROL_HIGH_SPEED_TRANS(1);
1711         val |= DSI_HOST_DSI_CONTROL_HIGH_SPEED_TRANS(TEGRA_DSI_HIGH);
1712         tegra_dsi_writel(dsi, val, DSI_HOST_DSI_CONTROL);
1713
1714         dsi->status.clk_out = DSI_PHYCLK_OUT_EN;
1715 }
1716
1717 static void tegra_dsi_hs_clk_out_enable_in_lp(struct tegra_dc_dsi_data *dsi)
1718 {
1719         u32 val;
1720         tegra_dsi_hs_clk_out_enable(dsi);
1721
1722         val = tegra_dsi_readl(dsi, DSI_HOST_DSI_CONTROL);
1723         val &= ~DSI_HOST_DSI_CONTROL_HIGH_SPEED_TRANS(1);
1724         val |= DSI_HOST_DSI_CONTROL_HIGH_SPEED_TRANS(TEGRA_DSI_LOW);
1725         tegra_dsi_writel(dsi, val, DSI_HOST_DSI_CONTROL);
1726 }
1727
1728 static void tegra_dsi_hs_clk_out_disable(struct tegra_dc *dc,
1729                                                 struct tegra_dc_dsi_data *dsi)
1730 {
1731         u32 val;
1732
1733         if (dsi->status.dc_stream == DSI_DC_STREAM_ENABLE)
1734                 tegra_dsi_stop_dc_stream_at_frame_end(dc, dsi);
1735
1736         tegra_dsi_writel(dsi, TEGRA_DSI_DISABLE, DSI_POWER_CONTROL);
1737         /* stabilization delay */
1738         udelay(300);
1739
1740         val = tegra_dsi_readl(dsi, DSI_HOST_DSI_CONTROL);
1741         val &= ~DSI_HOST_DSI_CONTROL_HIGH_SPEED_TRANS(1);
1742         val |= DSI_HOST_DSI_CONTROL_HIGH_SPEED_TRANS(TEGRA_DSI_LOW);
1743         tegra_dsi_writel(dsi, val, DSI_HOST_DSI_CONTROL);
1744
1745         tegra_dsi_writel(dsi, TEGRA_DSI_ENABLE, DSI_POWER_CONTROL);
1746         /* stabilization delay */
1747         udelay(300);
1748
1749         dsi->status.clk_mode = DSI_PHYCLK_NOT_INIT;
1750         dsi->status.clk_out = DSI_PHYCLK_OUT_DIS;
1751 }
1752
1753 static void tegra_dsi_set_control_reg_lp(struct tegra_dc_dsi_data *dsi)
1754 {
1755         u32 dsi_control;
1756         u32 host_dsi_control;
1757         u32 max_threshold;
1758
1759         dsi_control = dsi->dsi_control_val | DSI_CTRL_HOST_DRIVEN;
1760         host_dsi_control = HOST_DSI_CTRL_COMMON |
1761                         HOST_DSI_CTRL_HOST_DRIVEN |
1762                         DSI_HOST_DSI_CONTROL_HIGH_SPEED_TRANS(TEGRA_DSI_LOW);
1763         max_threshold = DSI_MAX_THRESHOLD_MAX_THRESHOLD(DSI_HOST_FIFO_DEPTH);
1764
1765         tegra_dsi_writel(dsi, max_threshold, DSI_MAX_THRESHOLD);
1766         tegra_dsi_writel(dsi, dsi_control, DSI_CONTROL);
1767         tegra_dsi_writel(dsi, host_dsi_control, DSI_HOST_DSI_CONTROL);
1768
1769         dsi->status.driven = DSI_DRIVEN_MODE_HOST;
1770         dsi->status.clk_burst = DSI_CLK_BURST_NOT_INIT;
1771         dsi->status.vtype = DSI_VIDEO_TYPE_NOT_INIT;
1772 }
1773
1774 static void tegra_dsi_set_control_reg_hs(struct tegra_dc_dsi_data *dsi,
1775                                                 u8 driven_mode)
1776 {
1777         u32 dsi_control;
1778         u32 host_dsi_control;
1779         u32 max_threshold;
1780         u32 dcs_cmd;
1781
1782         dsi_control = dsi->dsi_control_val;
1783         host_dsi_control = HOST_DSI_CTRL_COMMON;
1784         max_threshold = 0;
1785         dcs_cmd = 0;
1786
1787         if (driven_mode == TEGRA_DSI_DRIVEN_BY_HOST) {
1788                 dsi_control |= DSI_CTRL_HOST_DRIVEN;
1789                 host_dsi_control |= HOST_DSI_CTRL_HOST_DRIVEN;
1790                 max_threshold =
1791                         DSI_MAX_THRESHOLD_MAX_THRESHOLD(DSI_HOST_FIFO_DEPTH);
1792                 dsi->status.driven = DSI_DRIVEN_MODE_HOST;
1793         } else {
1794                 dsi_control |= DSI_CTRL_DC_DRIVEN;
1795                 host_dsi_control |= HOST_DSI_CTRL_DC_DRIVEN;
1796                 max_threshold =
1797                         DSI_MAX_THRESHOLD_MAX_THRESHOLD(DSI_VIDEO_FIFO_DEPTH);
1798                 dsi->status.driven = DSI_DRIVEN_MODE_DC;
1799
1800                 if (dsi->info.video_data_type ==
1801                         TEGRA_DSI_VIDEO_TYPE_COMMAND_MODE) {
1802                         dsi_control |= DSI_CTRL_CMD_MODE;
1803                         dcs_cmd = DSI_DCS_CMDS_LT5_DCS_CMD(
1804                                 DSI_WRITE_MEMORY_START)|
1805                                 DSI_DCS_CMDS_LT3_DCS_CMD(
1806                                 DSI_WRITE_MEMORY_CONTINUE);
1807                         dsi->status.vtype = DSI_VIDEO_TYPE_CMD_MODE;
1808                 } else {
1809                         dsi_control |= DSI_CTRL_VIDEO_MODE;
1810                         dsi->status.vtype = DSI_VIDEO_TYPE_VIDEO_MODE;
1811                 }
1812         }
1813
1814         tegra_dsi_writel(dsi, max_threshold, DSI_MAX_THRESHOLD);
1815         tegra_dsi_writel(dsi, dcs_cmd, DSI_DCS_CMDS);
1816         tegra_dsi_writel(dsi, dsi_control, DSI_CONTROL);
1817         tegra_dsi_writel(dsi, host_dsi_control, DSI_HOST_DSI_CONTROL);
1818 }
1819
1820 static void tegra_dsi_pad_disable(struct tegra_dc_dsi_data *dsi)
1821 {
1822         u32 val;
1823
1824         if (dsi->info.controller_vs == DSI_VS_1) {
1825                 val = tegra_dsi_readl(dsi, DSI_PAD_CONTROL_0_VS1);
1826                 val &= ~(DSI_PAD_CONTROL_0_VS1_PAD_PDIO(0xf) |
1827                         DSI_PAD_CONTROL_0_VS1_PAD_PDIO_CLK(0x1) |
1828                         DSI_PAD_CONTROL_0_VS1_PAD_PULLDN_ENAB(0xf) |
1829                         DSI_PAD_CONTROL_0_VS1_PAD_PULLDN_CLK_ENAB(0x1));
1830                 val |= DSI_PAD_CONTROL_0_VS1_PAD_PDIO(0xf) |
1831                         DSI_PAD_CONTROL_0_VS1_PAD_PDIO_CLK
1832                                                 (TEGRA_DSI_PAD_DISABLE) |
1833                         DSI_PAD_CONTROL_0_VS1_PAD_PULLDN_ENAB(0xf) |
1834                         DSI_PAD_CONTROL_0_VS1_PAD_PULLDN_CLK_ENAB
1835                                                 (TEGRA_DSI_PAD_DISABLE);
1836                 tegra_dsi_writel(dsi, val, DSI_PAD_CONTROL_0_VS1);
1837         } else {
1838                 val = tegra_dsi_readl(dsi, DSI_PAD_CONTROL);
1839                 val &= ~(DSI_PAD_CONTROL_PAD_PDIO(0x3) |
1840                         DSI_PAD_CONTROL_PAD_PDIO_CLK(0x1) |
1841                         DSI_PAD_CONTROL_PAD_PULLDN_ENAB(0x1));
1842                 val |= DSI_PAD_CONTROL_PAD_PDIO(0x3) |
1843                         DSI_PAD_CONTROL_PAD_PDIO_CLK(TEGRA_DSI_PAD_DISABLE) |
1844                         DSI_PAD_CONTROL_PAD_PULLDN_ENAB(TEGRA_DSI_PAD_DISABLE);
1845                 tegra_dsi_writel(dsi, val, DSI_PAD_CONTROL);
1846         }
1847 }
1848
1849 static void tegra_dsi_pad_enable(struct tegra_dc_dsi_data *dsi)
1850 {
1851         u32 val;
1852
1853         if (dsi->info.controller_vs == DSI_VS_1) {
1854                 val = tegra_dsi_readl(dsi, DSI_PAD_CONTROL_0_VS1);
1855                 val &= ~(DSI_PAD_CONTROL_0_VS1_PAD_PDIO(0xf) |
1856                         DSI_PAD_CONTROL_0_VS1_PAD_PDIO_CLK(0x1) |
1857                         DSI_PAD_CONTROL_0_VS1_PAD_PULLDN_ENAB(0xf) |
1858                         DSI_PAD_CONTROL_0_VS1_PAD_PULLDN_CLK_ENAB(0x1));
1859                 val |= DSI_PAD_CONTROL_0_VS1_PAD_PDIO(TEGRA_DSI_PAD_ENABLE) |
1860                         DSI_PAD_CONTROL_0_VS1_PAD_PDIO_CLK(
1861                                                 TEGRA_DSI_PAD_ENABLE) |
1862                         DSI_PAD_CONTROL_0_VS1_PAD_PULLDN_ENAB(
1863                                                 TEGRA_DSI_PAD_ENABLE) |
1864                         DSI_PAD_CONTROL_0_VS1_PAD_PULLDN_CLK_ENAB(
1865                                                 TEGRA_DSI_PAD_ENABLE);
1866                 tegra_dsi_writel(dsi, val, DSI_PAD_CONTROL_0_VS1);
1867         } else {
1868                 val = tegra_dsi_readl(dsi, DSI_PAD_CONTROL);
1869                 val &= ~(DSI_PAD_CONTROL_PAD_PDIO(0x3) |
1870                         DSI_PAD_CONTROL_PAD_PDIO_CLK(0x1) |
1871                         DSI_PAD_CONTROL_PAD_PULLDN_ENAB(0x1));
1872                 val |= DSI_PAD_CONTROL_PAD_PDIO(TEGRA_DSI_PAD_ENABLE) |
1873                         DSI_PAD_CONTROL_PAD_PDIO_CLK(TEGRA_DSI_PAD_ENABLE) |
1874                         DSI_PAD_CONTROL_PAD_PULLDN_ENAB(TEGRA_DSI_PAD_ENABLE);
1875                 tegra_dsi_writel(dsi, val, DSI_PAD_CONTROL);
1876         }
1877 }
1878
1879 static void tegra_dsi_pad_calibration(struct tegra_dc_dsi_data *dsi)
1880 {
1881         u32 val;
1882
1883         if (!dsi->ulpm)
1884                 tegra_dsi_pad_enable(dsi);
1885         else
1886                 tegra_dsi_pad_disable(dsi);
1887
1888         if (dsi->info.controller_vs == DSI_VS_1) {
1889                 /* TODO: characterization parameters */
1890         } else {
1891                 val = tegra_dsi_readl(dsi, DSI_PAD_CONTROL);
1892                 val &= ~(DSI_PAD_CONTROL_PAD_LPUPADJ(0x3) |
1893                         DSI_PAD_CONTROL_PAD_LPDNADJ(0x3) |
1894                         DSI_PAD_CONTROL_PAD_PREEMP_EN(0x1) |
1895                         DSI_PAD_CONTROL_PAD_SLEWDNADJ(0x7) |
1896                         DSI_PAD_CONTROL_PAD_SLEWUPADJ(0x7));
1897
1898                 val |= DSI_PAD_CONTROL_PAD_LPUPADJ(0x1) |
1899                         DSI_PAD_CONTROL_PAD_LPDNADJ(0x1) |
1900                         DSI_PAD_CONTROL_PAD_PREEMP_EN(0x1) |
1901                         DSI_PAD_CONTROL_PAD_SLEWDNADJ(0x6) |
1902                         DSI_PAD_CONTROL_PAD_SLEWUPADJ(0x6);
1903
1904                 tegra_dsi_writel(dsi, val, DSI_PAD_CONTROL);
1905
1906                 val = MIPI_CAL_TERMOSA(0x4);
1907                 tegra_vi_csi_writel(val, CSI_CILA_MIPI_CAL_CONFIG_0);
1908
1909                 val = MIPI_CAL_TERMOSB(0x4);
1910                 tegra_vi_csi_writel(val, CSI_CILB_MIPI_CAL_CONFIG_0);
1911
1912                 val = MIPI_CAL_HSPUOSD(0x3) | MIPI_CAL_HSPDOSD(0x4);
1913                 tegra_vi_csi_writel(val, CSI_DSI_MIPI_CAL_CONFIG);
1914
1915                 val = PAD_DRIV_DN_REF(0x5) | PAD_DRIV_UP_REF(0x7);
1916                 tegra_vi_csi_writel(val, CSI_MIPIBIAS_PAD_CONFIG);
1917         }
1918
1919         val = PAD_CIL_PDVREG(0x0);
1920         tegra_vi_csi_writel(val, CSI_CIL_PAD_CONFIG);
1921 }
1922
1923 static void tegra_dsi_panelB_enable(void)
1924 {
1925         unsigned int val;
1926
1927         val = readl(IO_ADDRESS(APB_MISC_GP_MIPI_PAD_CTRL_0));
1928         val |= DSIB_MODE_ENABLE;
1929         writel(val, (IO_ADDRESS(APB_MISC_GP_MIPI_PAD_CTRL_0)));
1930 }
1931
1932 static int tegra_dsi_init_hw(struct tegra_dc *dc,
1933                                 struct tegra_dc_dsi_data *dsi)
1934 {
1935         u32 i;
1936
1937         tegra_dsi_writel(dsi,
1938                 DSI_POWER_CONTROL_LEG_DSI_ENABLE(TEGRA_DSI_DISABLE),
1939                 DSI_POWER_CONTROL);
1940         /* stabilization delay */
1941         udelay(300);
1942
1943         tegra_dsi_set_dsi_clk(dc, dsi, dsi->target_lp_clk_khz);
1944         if (dsi->info.dsi_instance) {
1945                 tegra_dsi_panelB_enable();
1946                 /* TODO:Set the misc register */
1947         }
1948
1949         /* TODO: only need to change the timing for bta */
1950         tegra_dsi_set_phy_timing(dsi, DSI_LPHS_IN_LP_MODE);
1951
1952         if (dsi->status.dc_stream == DSI_DC_STREAM_ENABLE)
1953                 tegra_dsi_stop_dc_stream_at_frame_end(dc, dsi);
1954
1955         /* Initialize DSI registers */
1956         for (i = 0; i < ARRAY_SIZE(init_reg); i++)
1957                 tegra_dsi_writel(dsi, 0, init_reg[i]);
1958         if (dsi->info.controller_vs == DSI_VS_1) {
1959                 for (i = 0; i < ARRAY_SIZE(init_reg_vs1_ext); i++)
1960                         tegra_dsi_writel(dsi, 0, init_reg_vs1_ext[i]);
1961         }
1962
1963         tegra_dsi_writel(dsi, dsi->dsi_control_val, DSI_CONTROL);
1964
1965         tegra_dsi_pad_calibration(dsi);
1966
1967         tegra_dsi_writel(dsi,
1968                 DSI_POWER_CONTROL_LEG_DSI_ENABLE(TEGRA_DSI_ENABLE),
1969                 DSI_POWER_CONTROL);
1970         /* stabilization delay */
1971         udelay(300);
1972
1973         dsi->status.init = DSI_MODULE_INIT;
1974         dsi->status.lphs = DSI_LPHS_NOT_INIT;
1975         dsi->status.vtype = DSI_VIDEO_TYPE_NOT_INIT;
1976         dsi->status.driven = DSI_DRIVEN_MODE_NOT_INIT;
1977         dsi->status.clk_out = DSI_PHYCLK_OUT_DIS;
1978         dsi->status.clk_mode = DSI_PHYCLK_NOT_INIT;
1979         dsi->status.clk_burst = DSI_CLK_BURST_NOT_INIT;
1980         dsi->status.dc_stream = DSI_DC_STREAM_DISABLE;
1981         dsi->status.lp_op = DSI_LP_OP_NOT_INIT;
1982
1983         return 0;
1984 }
1985
1986 static int tegra_dsi_set_to_lp_mode(struct tegra_dc *dc,
1987                         struct tegra_dc_dsi_data *dsi, u8 lp_op)
1988 {
1989         int err;
1990
1991         if (dsi->status.init != DSI_MODULE_INIT) {
1992                 err = -EPERM;
1993                 goto fail;
1994         }
1995
1996         if (dsi->status.lphs == DSI_LPHS_IN_LP_MODE &&
1997                         dsi->status.lp_op == lp_op)
1998                 goto success;
1999
2000         if (dsi->status.dc_stream == DSI_DC_STREAM_ENABLE)
2001                 tegra_dsi_stop_dc_stream_at_frame_end(dc, dsi);
2002
2003         /* disable/enable hs clk according to enable_hs_clock_on_lp_cmd_mode */
2004         if ((dsi->status.clk_out == DSI_PHYCLK_OUT_EN) &&
2005                 (!dsi->info.enable_hs_clock_on_lp_cmd_mode))
2006                 tegra_dsi_hs_clk_out_disable(dc, dsi);
2007
2008         dsi->target_lp_clk_khz = tegra_dsi_get_lp_clk_rate(dsi, lp_op);
2009         if (dsi->current_dsi_clk_khz != dsi->target_lp_clk_khz) {
2010                 tegra_dsi_set_dsi_clk(dc, dsi, dsi->target_lp_clk_khz);
2011                 tegra_dsi_set_timeout(dsi);
2012         }
2013
2014         tegra_dsi_set_phy_timing(dsi, DSI_LPHS_IN_LP_MODE);
2015
2016         tegra_dsi_set_control_reg_lp(dsi);
2017
2018         if ((dsi->status.clk_out == DSI_PHYCLK_OUT_DIS) &&
2019                 (dsi->info.enable_hs_clock_on_lp_cmd_mode))
2020                 tegra_dsi_hs_clk_out_enable_in_lp(dsi);
2021
2022         dsi->status.lphs = DSI_LPHS_IN_LP_MODE;
2023         dsi->status.lp_op = lp_op;
2024         dsi->driven_mode = TEGRA_DSI_DRIVEN_BY_HOST;
2025 success:
2026         err = 0;
2027 fail:
2028         return err;
2029 }
2030
2031 static void tegra_dsi_ganged(struct tegra_dc *dc,
2032                                 struct tegra_dc_dsi_data *dsi)
2033 {
2034         u32 start = 0;
2035         u32 low_width = 0;
2036         u32 high_width = 0;
2037         u32 h_active = dc->out->modes->h_active;
2038         u32 val = 0;
2039
2040         if (dsi->info.controller_vs < DSI_VS_1) {
2041                 dev_err(&dc->ndev->dev, "dsi: ganged mode not"
2042                 "supported with current controller version\n");
2043                 return;
2044         }
2045
2046         if (dsi->info.ganged_type ==
2047                         TEGRA_DSI_GANGED_SYMMETRIC_LEFT_RIGHT) {
2048                 low_width = DIV_ROUND_UP(h_active, 2);
2049                 high_width = h_active - low_width;
2050                 if (dsi->controller_index)
2051                         start = h_active / 2;
2052                 else
2053                         start = 0;
2054         } else if (dsi->info.ganged_type ==
2055                         TEGRA_DSI_GANGED_SYMMETRIC_EVEN_ODD) {
2056                 low_width = 0x1;
2057                 high_width = 0x1;
2058                 if (dsi->controller_index)
2059                         start = 1;
2060                 else
2061                         start = 0;
2062         }
2063
2064         tegra_dsi_writel(dsi, DSI_GANGED_MODE_START_POINTER(start),
2065                                                 DSI_GANGED_MODE_START);
2066
2067         val = DSI_GANGED_MODE_SIZE_VALID_LOW_WIDTH(low_width) |
2068                 DSI_GANGED_MODE_SIZE_VALID_HIGH_WIDTH(high_width);
2069         tegra_dsi_writel(dsi, val, DSI_GANGED_MODE_SIZE);
2070
2071         tegra_dsi_writel(dsi, DSI_GANGED_MODE_CONTROL_EN(TEGRA_DSI_ENABLE),
2072                                                 DSI_GANGED_MODE_CONTROL);
2073 }
2074
2075 static int tegra_dsi_set_to_hs_mode(struct tegra_dc *dc,
2076                                         struct tegra_dc_dsi_data *dsi,
2077                                         u8 driven_mode)
2078 {
2079         int err;
2080
2081         if (dsi->status.init != DSI_MODULE_INIT) {
2082                 err = -EPERM;
2083                 goto fail;
2084         }
2085
2086         if (dsi->status.lphs == DSI_LPHS_IN_HS_MODE &&
2087                 dsi->driven_mode == driven_mode)
2088                 goto success;
2089
2090         dsi->driven_mode = driven_mode;
2091
2092         if (dsi->status.dc_stream == DSI_DC_STREAM_ENABLE)
2093                 tegra_dsi_stop_dc_stream_at_frame_end(dc, dsi);
2094
2095         if ((dsi->status.clk_out == DSI_PHYCLK_OUT_EN) &&
2096                 (!dsi->info.enable_hs_clock_on_lp_cmd_mode))
2097                 tegra_dsi_hs_clk_out_disable(dc, dsi);
2098
2099         if (dsi->current_dsi_clk_khz != dsi->target_hs_clk_khz) {
2100                 tegra_dsi_set_dsi_clk(dc, dsi, dsi->target_hs_clk_khz);
2101                 tegra_dsi_set_timeout(dsi);
2102         }
2103
2104         tegra_dsi_set_phy_timing(dsi, DSI_LPHS_IN_HS_MODE);
2105
2106         if (driven_mode == TEGRA_DSI_DRIVEN_BY_DC) {
2107                 tegra_dsi_set_pkt_seq(dc, dsi);
2108                 tegra_dsi_set_pkt_length(dc, dsi);
2109                 tegra_dsi_set_sol_delay(dc, dsi);
2110                 tegra_dsi_set_dc_clk(dc, dsi);
2111         }
2112
2113         tegra_dsi_set_control_reg_hs(dsi, driven_mode);
2114
2115         if (dsi->info.ganged_type)
2116                 tegra_dsi_ganged(dc, dsi);
2117
2118         if (dsi->status.clk_out == DSI_PHYCLK_OUT_DIS ||
2119                 dsi->info.enable_hs_clock_on_lp_cmd_mode)
2120                 tegra_dsi_hs_clk_out_enable(dsi);
2121
2122         dsi->status.lphs = DSI_LPHS_IN_HS_MODE;
2123 success:
2124         dsi->status.lp_op = DSI_LP_OP_NOT_INIT;
2125         err = 0;
2126 fail:
2127         return err;
2128 }
2129
2130 static bool tegra_dsi_write_busy(struct tegra_dc_dsi_data *dsi)
2131 {
2132         u32 timeout = 0;
2133         bool retVal = true;
2134
2135         while (timeout <= DSI_MAX_COMMAND_DELAY_USEC) {
2136                 if (!(DSI_TRIGGER_HOST_TRIGGER(0x1) &
2137                         tegra_dsi_readl(dsi, DSI_TRIGGER))) {
2138                         retVal = false;
2139                         break;
2140                 }
2141                 udelay(DSI_COMMAND_DELAY_STEPS_USEC);
2142                 timeout += DSI_COMMAND_DELAY_STEPS_USEC;
2143         }
2144
2145         return retVal;
2146 }
2147
2148 static bool tegra_dsi_read_busy(struct tegra_dc_dsi_data *dsi)
2149 {
2150         u32 timeout = 0;
2151         bool retVal = true;
2152
2153         while (timeout <  DSI_STATUS_POLLING_DURATION_USEC) {
2154                 if (!(DSI_HOST_DSI_CONTROL_IMM_BTA(0x1) &
2155                         tegra_dsi_readl(dsi, DSI_HOST_DSI_CONTROL))) {
2156                         retVal = false;
2157                         break;
2158                 }
2159                 udelay(DSI_STATUS_POLLING_DELAY_USEC);
2160                 timeout += DSI_STATUS_POLLING_DELAY_USEC;
2161         }
2162
2163         return retVal;
2164 }
2165
2166 static bool tegra_dsi_host_busy(struct tegra_dc_dsi_data *dsi)
2167 {
2168         int err = 0;
2169
2170         if (tegra_dsi_write_busy(dsi)) {
2171                 err = -EBUSY;
2172                 dev_err(&dsi->dc->ndev->dev,
2173                         "DSI trigger bit already set\n");
2174                 goto fail;
2175         }
2176
2177         if (tegra_dsi_read_busy(dsi)) {
2178                 err = -EBUSY;
2179                 dev_err(&dsi->dc->ndev->dev,
2180                         "DSI immediate bta bit already set\n");
2181                 goto fail;
2182         }
2183 fail:
2184         return (err < 0 ? true : false);
2185 }
2186
2187 static void tegra_dsi_reset_read_count(struct tegra_dc_dsi_data *dsi)
2188 {
2189         u32 val;
2190
2191         val = tegra_dsi_readl(dsi, DSI_STATUS);
2192         val &= DSI_STATUS_RD_FIFO_COUNT(0x1f);
2193         if (val) {
2194                 dev_warn(&dsi->dc->ndev->dev,
2195                         "DSI read count not zero, resetting\n");
2196                 tegra_dsi_soft_reset(dsi);
2197         }
2198 }
2199
2200 static struct dsi_status *tegra_dsi_save_state_switch_to_host_cmd_mode(
2201                                                 struct tegra_dc_dsi_data *dsi,
2202                                                 struct tegra_dc *dc,
2203                                                 u8 lp_op)
2204 {
2205         struct dsi_status *init_status = NULL;
2206         int err;
2207
2208         if (dsi->status.init != DSI_MODULE_INIT ||
2209                 dsi->status.lphs == DSI_LPHS_NOT_INIT) {
2210                 err = -EPERM;
2211                 goto fail;
2212         }
2213
2214         init_status = kzalloc(sizeof(*init_status), GFP_KERNEL);
2215         if (!init_status)
2216                 return ERR_PTR(-ENOMEM);
2217
2218         *init_status = dsi->status;
2219
2220         if (dsi->info.hs_cmd_mode_supported) {
2221                 err = tegra_dsi_set_to_hs_mode(dc, dsi,
2222                                 TEGRA_DSI_DRIVEN_BY_HOST);
2223                 if (err < 0) {
2224                         dev_err(&dc->ndev->dev,
2225                         "Switch to HS host mode failed\n");
2226                         goto fail;
2227                 }
2228
2229                 goto success;
2230         }
2231
2232         if (dsi->status.lp_op != lp_op) {
2233                 err = tegra_dsi_set_to_lp_mode(dc, dsi, lp_op);
2234                 if (err < 0) {
2235                         dev_err(&dc->ndev->dev,
2236                         "DSI failed to go to LP mode\n");
2237                         goto fail;
2238                 }
2239         }
2240 success:
2241         return init_status;
2242 fail:
2243         kfree(init_status);
2244         return ERR_PTR(err);
2245 }
2246
2247 static struct dsi_status *tegra_dsi_prepare_host_transmission(
2248                                 struct tegra_dc *dc,
2249                                 struct tegra_dc_dsi_data *dsi,
2250                                 u8 lp_op)
2251 {
2252         int err = 0;
2253         struct dsi_status *init_status;
2254         bool restart_dc_stream = false;
2255
2256         if (dsi->status.init != DSI_MODULE_INIT ||
2257                 dsi->ulpm) {
2258                 err = -EPERM;
2259                 goto fail;
2260         }
2261
2262         if (dsi->status.dc_stream == DSI_DC_STREAM_ENABLE) {
2263                 restart_dc_stream = true;
2264                 tegra_dsi_stop_dc_stream_at_frame_end(dc, dsi);
2265         }
2266
2267         if (tegra_dsi_host_busy(dsi)) {
2268                 tegra_dsi_soft_reset(dsi);
2269                 if (tegra_dsi_host_busy(dsi)) {
2270                         err = -EBUSY;
2271                         dev_err(&dc->ndev->dev, "DSI host busy\n");
2272                         goto fail;
2273                 }
2274         }
2275
2276         if (lp_op == DSI_LP_OP_READ)
2277                 tegra_dsi_reset_read_count(dsi);
2278
2279         if (dsi->status.lphs == DSI_LPHS_NOT_INIT) {
2280                 err = tegra_dsi_set_to_lp_mode(dc, dsi, lp_op);
2281                 if (err < 0) {
2282                         dev_err(&dc->ndev->dev, "Failed to config LP write\n");
2283                         goto fail;
2284                 }
2285         }
2286
2287         init_status = tegra_dsi_save_state_switch_to_host_cmd_mode
2288                                         (dsi, dc, lp_op);
2289         if (IS_ERR_OR_NULL(init_status)) {
2290                 err = PTR_ERR(init_status);
2291                 dev_err(&dc->ndev->dev, "DSI state saving failed\n");
2292                 goto fail;
2293         }
2294
2295         if (restart_dc_stream)
2296                 init_status->dc_stream = DSI_DC_STREAM_ENABLE;
2297
2298         return init_status;
2299 fail:
2300         return ERR_PTR(err);
2301 }
2302
2303 static int tegra_dsi_restore_state(struct tegra_dc *dc,
2304                                 struct tegra_dc_dsi_data *dsi,
2305                                 struct dsi_status *init_status)
2306 {
2307         int err = 0;
2308
2309         if (init_status->lphs == DSI_LPHS_IN_LP_MODE) {
2310                 err = tegra_dsi_set_to_lp_mode(dc, dsi, init_status->lp_op);
2311                 if (err < 0) {
2312                         dev_err(&dc->ndev->dev,
2313                                 "Failed to config LP mode\n");
2314                         goto fail;
2315                 }
2316                 goto success;
2317         }
2318
2319         if (init_status->lphs == DSI_LPHS_IN_HS_MODE) {
2320                 u8 driven = (init_status->driven == DSI_DRIVEN_MODE_DC) ?
2321                         TEGRA_DSI_DRIVEN_BY_DC : TEGRA_DSI_DRIVEN_BY_HOST;
2322                 err = tegra_dsi_set_to_hs_mode(dc, dsi, driven);
2323                 if (err < 0) {
2324                         dev_err(&dc->ndev->dev, "Failed to config HS mode\n");
2325                         goto fail;
2326                 }
2327         }
2328
2329         if (init_status->dc_stream == DSI_DC_STREAM_ENABLE)
2330                 tegra_dsi_start_dc_stream(dc, dsi);
2331 success:
2332 fail:
2333         kfree(init_status);
2334         return err;
2335 }
2336
2337 static int tegra_dsi_host_trigger(struct tegra_dc_dsi_data *dsi)
2338 {
2339         int status = 0;
2340
2341         if (tegra_dsi_readl(dsi, DSI_TRIGGER)) {
2342                 status = -EBUSY;
2343                 goto fail;
2344         }
2345
2346         tegra_dsi_writel(dsi,
2347                 DSI_TRIGGER_HOST_TRIGGER(TEGRA_DSI_ENABLE), DSI_TRIGGER);
2348
2349 #if DSI_USE_SYNC_POINTS
2350         status = tegra_dsi_syncpt(dsi);
2351         if (status < 0) {
2352                 dev_err(&dsi->dc->ndev->dev,
2353                         "DSI syncpt for host trigger failed\n");
2354                 goto fail;
2355         }
2356 #else
2357         if (tegra_dsi_write_busy(dsi)) {
2358                 status = -EBUSY;
2359                 dev_err(&dsi->dc->ndev->dev,
2360                         "Timeout waiting on write completion\n");
2361         }
2362 #endif
2363
2364 fail:
2365         return status;
2366 }
2367
2368 static int _tegra_dsi_write_data(struct tegra_dc_dsi_data *dsi,
2369                                         u8 *pdata, u8 data_id, u16 data_len)
2370 {
2371         u8 virtual_channel;
2372         u32 val;
2373         int err;
2374
2375         err = 0;
2376
2377         virtual_channel = dsi->info.virtual_channel <<
2378                                                 DSI_VIR_CHANNEL_BIT_POSITION;
2379
2380         /* always use hw for ecc */
2381         val = (virtual_channel | data_id) << 0 |
2382                         data_len << 8;
2383         tegra_dsi_writel(dsi, val, DSI_WR_DATA);
2384
2385         /* if pdata != NULL, pkt type is long pkt */
2386         if (pdata != NULL) {
2387                 while (data_len) {
2388                         if (data_len >= 4) {
2389                                 val = ((u32 *) pdata)[0];
2390                                 data_len -= 4;
2391                                 pdata += 4;
2392                         } else {
2393                                 val = 0;
2394                                 memcpy(&val, pdata, data_len);
2395                                 pdata += data_len;
2396                                 data_len = 0;
2397                         }
2398                         tegra_dsi_writel(dsi, val, DSI_WR_DATA);
2399                 }
2400         }
2401
2402         err = tegra_dsi_host_trigger(dsi);
2403         if (err < 0)
2404                 dev_err(&dsi->dc->ndev->dev, "DSI host trigger failed\n");
2405
2406         return err;
2407 }
2408
2409 static void tegra_dc_dsi_hold_host(struct tegra_dc *dc)
2410 {
2411         struct tegra_dc_dsi_data *dsi = tegra_dc_get_outdata(dc);
2412
2413         if (dc->out->flags & TEGRA_DC_OUT_ONE_SHOT_LP_MODE) {
2414                 /*
2415                  * The reference count should never be more than 1.
2416                  */
2417                 BUG_ON(tegra_is_clk_enabled(dc->clk) > 1);
2418
2419                 if (dsi->host_suspended)
2420                         tegra_dsi_host_resume(dc);
2421
2422                 /*
2423                  * Take an extra refrence to count for the clk_disable in
2424                  * tegra_dc_release_host.
2425                  */
2426                 clk_enable(dc->clk);
2427         }
2428 }
2429
2430 static void tegra_dc_dsi_release_host(struct tegra_dc *dc)
2431 {
2432         if (dc->out->flags & TEGRA_DC_OUT_ONE_SHOT_LP_MODE)
2433                 clk_disable(dc->clk);
2434 }
2435
2436 static void tegra_dc_dsi_idle(struct tegra_dc *dc)
2437 {
2438         if (dc->out->flags & TEGRA_DC_OUT_ONE_SHOT_LP_MODE)
2439                 tegra_dsi_host_suspend(dc);
2440 }
2441
2442 int tegra_dsi_write_data(struct tegra_dc *dc,
2443                         struct tegra_dc_dsi_data *dsi,
2444                         u8 *pdata, u8 data_id, u16 data_len)
2445 {
2446         int err = 0;
2447         struct dsi_status *init_status;
2448
2449         tegra_dc_io_start(dc);
2450
2451         init_status = tegra_dsi_prepare_host_transmission(
2452                                 dc, dsi, DSI_LP_OP_WRITE);
2453         if (IS_ERR_OR_NULL(init_status)) {
2454                 err = PTR_ERR(init_status);
2455                 dev_err(&dc->ndev->dev, "DSI host config failed\n");
2456                 goto fail;
2457         }
2458
2459         err = _tegra_dsi_write_data(dsi, pdata, data_id, data_len);
2460 fail:
2461         err = tegra_dsi_restore_state(dc, dsi, init_status);
2462         if (err < 0)
2463                 dev_err(&dc->ndev->dev, "Failed to restore prev state\n");
2464         tegra_dc_io_end(dc);
2465
2466         return err;
2467 }
2468 EXPORT_SYMBOL(tegra_dsi_write_data);
2469
2470 static int tegra_dsi_send_panel_cmd(struct tegra_dc *dc,
2471                                         struct tegra_dc_dsi_data *dsi,
2472                                         struct tegra_dsi_cmd *cmd,
2473                                         u32 n_cmd)
2474 {
2475         u32 i;
2476         int err;
2477
2478         err = 0;
2479         for (i = 0; i < n_cmd; i++) {
2480                 struct tegra_dsi_cmd *cur_cmd;
2481                 cur_cmd = &cmd[i];
2482
2483                 if (cur_cmd->cmd_type == TEGRA_DSI_DELAY_MS)
2484                         mdelay(cur_cmd->sp_len_dly.delay_ms);
2485                 else {
2486                         err = tegra_dsi_write_data(dc, dsi,
2487                                                 cur_cmd->pdata,
2488                                                 cur_cmd->data_id,
2489                                                 cur_cmd->sp_len_dly.data_len);
2490                         if (err < 0)
2491                                 break;
2492                 }
2493         }
2494         return err;
2495 }
2496
2497 static u8 tegra_dsi_ecc(u32 header)
2498 {
2499         char ecc_parity[24] = {
2500                 0x07, 0x0b, 0x0d, 0x0e, 0x13, 0x15, 0x16, 0x19,
2501                 0x1a, 0x1c, 0x23, 0x25, 0x26, 0x29, 0x2a, 0x2c,
2502                 0x31, 0x32, 0x34, 0x38, 0x1f, 0x2f, 0x37, 0x3b
2503         };
2504         u8 ecc_byte;
2505         int i;
2506
2507         ecc_byte = 0;
2508         for (i = 0; i < 24; i++)
2509                 ecc_byte ^= ((header >> i) & 1) ? ecc_parity[i] : 0x00;
2510
2511         return ecc_byte;
2512 }
2513
2514 static u16 tegra_dsi_cs(char *pdata, u16 data_len)
2515 {
2516         u16 byte_cnt;
2517         u8 bit_cnt;
2518         char curr_byte;
2519         u16 crc = 0xFFFF;
2520         u16 poly = 0x8408;
2521
2522         if (data_len > 0) {
2523                 for (byte_cnt = 0; byte_cnt < data_len; byte_cnt++) {
2524                         curr_byte = pdata[byte_cnt];
2525                         for (bit_cnt = 0; bit_cnt < 8; bit_cnt++) {
2526                                 if (((crc & 0x0001 ) ^
2527                                         (curr_byte & 0x0001)) > 0)
2528                                         crc = ((crc >> 1) & 0x7FFF) ^ poly;
2529                                 else
2530                                         crc = (crc >> 1) & 0x7FFF;
2531
2532                                 curr_byte = (curr_byte >> 1 ) & 0x7F;
2533                         }
2534                 }
2535         }
2536         return crc;
2537 }
2538
2539 static int tegra_dsi_dcs_pkt_seq_ctrl_init(struct tegra_dc_dsi_data *dsi,
2540                                                 struct tegra_dsi_cmd *cmd)
2541 {
2542         u8 virtual_channel;
2543         u32 val;
2544         u16 data_len = cmd->sp_len_dly.data_len;
2545         u8 seq_ctrl_reg = 0;
2546
2547         virtual_channel = dsi->info.virtual_channel <<
2548                                 DSI_VIR_CHANNEL_BIT_POSITION;
2549
2550         val = (virtual_channel | cmd->data_id) << 0 |
2551                 data_len << 8;
2552
2553         val |= tegra_dsi_ecc(val) << 24;
2554
2555         tegra_dsi_writel(dsi, val, DSI_INIT_SEQ_DATA_0 + seq_ctrl_reg++);
2556
2557         /* if pdata != NULL, pkt type is long pkt */
2558         if (cmd->pdata != NULL) {
2559                 u8 *pdata;
2560                 u8 *pdata_mem;
2561                 /*  allocate memory for pdata + 2 bytes checksum */
2562                 pdata_mem = kzalloc(sizeof(u8) * data_len + 2, GFP_KERNEL);
2563                 if (!pdata_mem) {
2564                         dev_err(&dsi->dc->ndev->dev, "dsi: memory err\n");
2565                         tegra_dsi_soft_reset(dsi);
2566                         return -ENOMEM;
2567                 }
2568
2569                 memcpy(pdata_mem, cmd->pdata, data_len);
2570                 pdata = pdata_mem;
2571                 *((u16 *)(pdata + data_len)) = tegra_dsi_cs(pdata, data_len);
2572
2573                 /* data_len = length of pdata + 2 byte checksum */
2574                 data_len += 2;
2575
2576                 while (data_len) {
2577                         if (data_len >= 4) {
2578                                 val = ((u32 *) pdata)[0];
2579                                 data_len -= 4;
2580                                 pdata += 4;
2581                         } else {
2582                                 val = 0;
2583                                 memcpy(&val, pdata, data_len);
2584                                 pdata += data_len;
2585                                 data_len = 0;
2586                         }
2587                         tegra_dsi_writel(dsi, val, DSI_INIT_SEQ_DATA_0 +
2588                                                         seq_ctrl_reg++);
2589                 }
2590                 kfree(pdata_mem);
2591         }
2592
2593         return 0;
2594 }
2595
2596 int tegra_dsi_start_host_cmd_v_blank_dcs(struct tegra_dc_dsi_data * dsi,
2597                                                 struct tegra_dsi_cmd *cmd)
2598 {
2599 #define PKT_HEADER_LEN_BYTE     4
2600 #define CHECKSUM_LEN_BYTE       2
2601
2602         int err = 0;
2603         u32 val;
2604         u16 tot_pkt_len = PKT_HEADER_LEN_BYTE;
2605         struct tegra_dc *dc = dsi->dc;
2606
2607         if (cmd->cmd_type != TEGRA_DSI_PACKET_CMD)
2608                 return -EINVAL;
2609
2610         mutex_lock(&dsi->lock);
2611         tegra_dc_dsi_hold_host(dc);
2612
2613         tegra_dc_io_start(dc);
2614
2615
2616         err = tegra_dsi_dcs_pkt_seq_ctrl_init(dsi, cmd);
2617         if (err < 0) {
2618                 dev_err(&dsi->dc->ndev->dev,
2619                         "dsi: dcs pkt seq ctrl init failed\n");
2620                 goto fail;
2621         }
2622
2623         if (cmd->pdata) {
2624                 u16 data_len = cmd->sp_len_dly.data_len;
2625                 tot_pkt_len += data_len + CHECKSUM_LEN_BYTE;
2626         }
2627
2628         val = DSI_INIT_SEQ_CONTROL_DSI_FRAME_INIT_BYTE_COUNT(tot_pkt_len) |
2629                 DSI_INIT_SEQ_CONTROL_DSI_SEND_INIT_SEQUENCE(
2630                                                 TEGRA_DSI_ENABLE);
2631         tegra_dsi_writel(dsi, val, DSI_INIT_SEQ_CONTROL);
2632
2633 fail:
2634         tegra_dc_io_end(dc);
2635         tegra_dc_dsi_release_host(dc);
2636         mutex_unlock(&dsi->lock);
2637         return err;
2638
2639 #undef PKT_HEADER_LEN_BYTE
2640 #undef CHECKSUM_LEN_BYTE
2641 }
2642 EXPORT_SYMBOL(tegra_dsi_start_host_cmd_v_blank_dcs);
2643
2644 void tegra_dsi_stop_host_cmd_v_blank_dcs(struct tegra_dc_dsi_data * dsi)
2645 {
2646         struct tegra_dc *dc = dsi->dc;
2647         u32 cnt;
2648
2649         mutex_lock(&dsi->lock);
2650         tegra_dc_dsi_hold_host(dc);
2651
2652         tegra_dc_io_start(dc);
2653
2654         tegra_dsi_writel(dsi, TEGRA_DSI_DISABLE, DSI_INIT_SEQ_CONTROL);
2655
2656         /* clear seq data registers */
2657         for (cnt = 0; cnt < 8; cnt++)
2658                 tegra_dsi_writel(dsi, 0, DSI_INIT_SEQ_DATA_0 + cnt);
2659
2660         tegra_dc_io_end(dc);
2661
2662         tegra_dc_dsi_release_host(dc);
2663         mutex_unlock(&dsi->lock);
2664 }
2665 EXPORT_SYMBOL(tegra_dsi_stop_host_cmd_v_blank_dcs);
2666
2667 static int tegra_dsi_bta(struct tegra_dc_dsi_data *dsi)
2668 {
2669         u32 val;
2670         u32 poll_time;
2671         int err;
2672
2673         poll_time = 0;
2674         err = 0;
2675
2676         val = tegra_dsi_readl(dsi, DSI_HOST_DSI_CONTROL);
2677         val |= DSI_HOST_DSI_CONTROL_IMM_BTA(TEGRA_DSI_ENABLE);
2678         tegra_dsi_writel(dsi, val, DSI_HOST_DSI_CONTROL);
2679
2680 #if DSI_USE_SYNC_POINTS
2681         dsi->syncpt_val = nvhost_syncpt_read_ext(dsi->dc->ndev,
2682                         dsi->syncpt_id);
2683
2684         val = DSI_INCR_SYNCPT_COND(OP_DONE) |
2685                 DSI_INCR_SYNCPT_INDX(dsi->syncpt_id);
2686         tegra_dsi_writel(dsi, val, DSI_INCR_SYNCPT);
2687
2688         /* TODO: Use interrupt rather than polling */
2689         err = nvhost_syncpt_wait_timeout_ext(dsi->dc->ndev, dsi->syncpt_id,
2690                 dsi->syncpt_val + 1, MAX_SCHEDULE_TIMEOUT, NULL);
2691         if (err < 0)
2692                 dev_err(&dsi->dc->ndev->dev,
2693                         "DSI sync point failure\n");
2694         else
2695                 (dsi->syncpt_val)++;
2696 #else
2697         if (tegra_dsi_read_busy(dsi)) {
2698                 err = -EBUSY;
2699                 dev_err(&dsi->dc->ndev->dev,
2700                         "Timeout wating on read completion\n");
2701         }
2702 #endif
2703
2704         return err;
2705 }
2706
2707 static int tegra_dsi_parse_read_response(struct tegra_dc *dc,
2708                                         u32 rd_fifo_cnt, u8 *read_fifo)
2709 {
2710         int err;
2711         u32 payload_size;
2712
2713         payload_size = 0;
2714         err = 0;
2715
2716         switch (read_fifo[0]) {
2717         case DSI_ESCAPE_CMD:
2718                 dev_info(&dc->ndev->dev, "escape cmd[0x%x]\n", read_fifo[0]);
2719                 break;
2720         case DSI_ACK_NO_ERR:
2721                 dev_info(&dc->ndev->dev,
2722                         "Panel ack, no err[0x%x]\n", read_fifo[0]);
2723                 return err;
2724         default:
2725                 dev_info(&dc->ndev->dev, "Invalid read response\n");
2726                 break;
2727         }
2728
2729         switch (read_fifo[4] & 0xff) {
2730         case GEN_LONG_RD_RES:
2731                 /* Fall through */
2732         case DCS_LONG_RD_RES:
2733                 payload_size = (read_fifo[5] |
2734                                 (read_fifo[6] << 8)) & 0xFFFF;
2735                 dev_info(&dc->ndev->dev, "Long read response Packet\n"
2736                                 "payload_size[0x%x]\n", payload_size);
2737                 break;
2738         case GEN_1_BYTE_SHORT_RD_RES:
2739                 /* Fall through */
2740         case DCS_1_BYTE_SHORT_RD_RES:
2741                 payload_size = 1;
2742                 dev_info(&dc->ndev->dev, "Short read response Packet\n"
2743                         "payload_size[0x%x]\n", payload_size);
2744                 break;
2745         case GEN_2_BYTE_SHORT_RD_RES:
2746                 /* Fall through */
2747         case DCS_2_BYTE_SHORT_RD_RES:
2748                 payload_size = 2;
2749                 dev_info(&dc->ndev->dev, "Short read response Packet\n"
2750                         "payload_size[0x%x]\n", payload_size);
2751                 break;
2752         case ACK_ERR_RES:
2753                 payload_size = 2;
2754                 dev_info(&dc->ndev->dev, "Acknowledge error report response\n"
2755                         "Packet payload_size[0x%x]\n", payload_size);
2756                 break;
2757         default:
2758                 dev_info(&dc->ndev->dev, "Invalid response packet\n");
2759                 err = -EINVAL;
2760                 break;
2761         }
2762         return err;
2763 }
2764
2765 static int tegra_dsi_read_fifo(struct tegra_dc *dc,
2766                         struct tegra_dc_dsi_data *dsi,
2767                         u8 *read_fifo)
2768 {
2769         u32 val;
2770         u32 i;
2771         u32 poll_time = 0;
2772         u32 rd_fifo_cnt;
2773         int err = 0;
2774         u8 *read_fifo_cp = read_fifo;
2775
2776         while (poll_time <  DSI_DELAY_FOR_READ_FIFO) {
2777                 mdelay(1);
2778                 val = tegra_dsi_readl(dsi, DSI_STATUS);
2779                 rd_fifo_cnt = val & DSI_STATUS_RD_FIFO_COUNT(0x1f);
2780                 if (rd_fifo_cnt << 2 > DSI_READ_FIFO_DEPTH)
2781                         dev_err(&dc->ndev->dev,
2782                         "DSI RD_FIFO_CNT is greater than RD_FIFO_DEPTH\n");
2783                         break;
2784                 poll_time++;
2785         }
2786
2787         if (rd_fifo_cnt == 0) {
2788                 dev_info(&dc->ndev->dev,
2789                         "DSI RD_FIFO_CNT is zero\n");
2790                 err = -EINVAL;
2791                 goto fail;
2792         }
2793
2794         if (val & (DSI_STATUS_LB_UNDERFLOW(0x1) |
2795                 DSI_STATUS_LB_OVERFLOW(0x1))) {
2796                 dev_warn(&dc->ndev->dev,
2797                         "DSI overflow/underflow error\n");
2798         }
2799
2800         /* Read data from FIFO */
2801         for (i = 0; i < rd_fifo_cnt; i++) {
2802                 val = tegra_dsi_readl(dsi, DSI_RD_DATA);
2803                 if (enable_read_debug)
2804                         dev_info(&dc->ndev->dev,
2805                         "Read data[%d]: 0x%x\n", i, val);
2806                 memcpy(read_fifo, &val, 4);
2807                 read_fifo += 4;
2808         }
2809
2810         /* Make sure all the data is read from the FIFO */
2811         val = tegra_dsi_readl(dsi, DSI_STATUS);
2812         val &= DSI_STATUS_RD_FIFO_COUNT(0x1f);
2813         if (val)
2814                 dev_err(&dc->ndev->dev, "DSI FIFO_RD_CNT not zero"
2815                 " even after reading FIFO_RD_CNT words from read fifo\n");
2816
2817         if (enable_read_debug) {
2818                 err =
2819                 tegra_dsi_parse_read_response(dc, rd_fifo_cnt, read_fifo_cp);
2820                 if (err < 0)
2821                         dev_warn(&dc->ndev->dev, "Unexpected read data\n");
2822         }
2823 fail:
2824         return err;
2825 }
2826
2827 int tegra_dsi_read_data(struct tegra_dc *dc,
2828                                 struct tegra_dc_dsi_data *dsi,
2829                                 u32 max_ret_payload_size,
2830                                 u32 panel_reg_addr, u8 *read_data)
2831 {
2832         int err = 0;
2833         struct dsi_status *init_status;
2834
2835         mutex_lock(&dsi->lock);
2836         tegra_dc_io_start(dc);
2837
2838         init_status = tegra_dsi_prepare_host_transmission(
2839                                 dc, dsi, DSI_LP_OP_WRITE);
2840         if (IS_ERR_OR_NULL(init_status)) {
2841                 err = PTR_ERR(init_status);
2842                 dev_err(&dc->ndev->dev, "DSI host config failed\n");
2843                 goto fail;
2844         }
2845
2846         /* Set max return payload size in words */
2847         err = _tegra_dsi_write_data(dsi, NULL,
2848                 dsi_command_max_return_pkt_size,
2849                 max_ret_payload_size);
2850         if (err < 0) {
2851                 dev_err(&dc->ndev->dev,
2852                                 "DSI write failed\n");
2853                 goto fail;
2854         }
2855
2856         /* DCS to read given panel register */
2857         err = _tegra_dsi_write_data(dsi, NULL,
2858                 dsi_command_dcs_read_with_no_params,
2859                 panel_reg_addr);
2860         if (err < 0) {
2861                 dev_err(&dc->ndev->dev,
2862                                 "DSI write failed\n");
2863                 goto fail;
2864         }
2865
2866         tegra_dsi_reset_read_count(dsi);
2867
2868         if (dsi->status.lp_op == DSI_LP_OP_WRITE) {
2869                 err = tegra_dsi_set_to_lp_mode(dc, dsi, DSI_LP_OP_READ);
2870                 if (err < 0) {
2871                         dev_err(&dc->ndev->dev,
2872                         "DSI failed to go to LP read mode\n");
2873                         goto fail;
2874                 }
2875         }
2876
2877         err = tegra_dsi_bta(dsi);
2878         if (err < 0) {
2879                 dev_err(&dc->ndev->dev,
2880                         "DSI IMM BTA timeout\n");
2881                 goto fail;
2882         }
2883
2884         err = tegra_dsi_read_fifo(dc, dsi, read_data);
2885         if (err < 0) {
2886                 dev_err(&dc->ndev->dev, "DSI read fifo failure\n");
2887                 goto fail;
2888         }
2889 fail:
2890         err = tegra_dsi_restore_state(dc, dsi, init_status);
2891         if (err < 0)
2892                 dev_err(&dc->ndev->dev, "Failed to restore prev state\n");
2893         tegra_dc_io_end(dc);
2894         mutex_unlock(&dsi->lock);
2895         return err;
2896 }
2897 EXPORT_SYMBOL(tegra_dsi_read_data);
2898
2899 int tegra_dsi_panel_sanity_check(struct tegra_dc *dc,
2900                                 struct tegra_dc_dsi_data *dsi)
2901 {
2902         int err = 0;
2903         u8 read_fifo[DSI_READ_FIFO_DEPTH];
2904         struct dsi_status *init_status;
2905         static struct tegra_dsi_cmd dsi_nop_cmd =
2906                         DSI_CMD_SHORT(0x05, 0x0, 0x0);
2907
2908         tegra_dc_io_start(dc);
2909
2910         init_status = tegra_dsi_prepare_host_transmission(
2911                                         dc, dsi, DSI_LP_OP_WRITE);
2912         if (IS_ERR_OR_NULL(init_status)) {
2913                 err = PTR_ERR(init_status);
2914                 dev_err(&dc->ndev->dev, "DSI host config failed\n");
2915                 goto fail;
2916         }
2917
2918         err = _tegra_dsi_write_data(dsi, NULL, dsi_nop_cmd.data_id, 0x0);
2919         if (err < 0) {
2920                 dev_err(&dc->ndev->dev, "DSI nop write failed\n");
2921                 goto fail;
2922         }
2923
2924         tegra_dsi_reset_read_count(dsi);
2925
2926         if (dsi->status.lp_op == DSI_LP_OP_WRITE) {
2927                 err = tegra_dsi_set_to_lp_mode(dc, dsi, DSI_LP_OP_READ);
2928                 if (err < 0) {
2929                         dev_err(&dc->ndev->dev,
2930                         "DSI failed to go to LP read mode\n");
2931                         goto fail;
2932                 }
2933         }
2934
2935         err = tegra_dsi_bta(dsi);
2936         if (err < 0) {
2937                 dev_err(&dc->ndev->dev, "DSI BTA failed\n");
2938                 goto fail;
2939         }
2940
2941         err = tegra_dsi_read_fifo(dc, dsi, read_fifo);
2942         if (err < 0) {
2943                 dev_err(&dc->ndev->dev, "DSI read fifo failure\n");
2944                 goto fail;
2945         }
2946
2947         if (read_fifo[0] != DSI_ACK_NO_ERR) {
2948                 dev_warn(&dc->ndev->dev,
2949                         "Ack no error trigger message not received\n");
2950                 err = -EAGAIN;
2951         }
2952 fail:
2953         err = tegra_dsi_restore_state(dc, dsi, init_status);
2954         if (err < 0)
2955                 dev_err(&dc->ndev->dev, "Failed to restore prev state\n");
2956         tegra_dc_io_end(dc);
2957         return err;
2958 }
2959 EXPORT_SYMBOL(tegra_dsi_panel_sanity_check);
2960
2961 static int tegra_dsi_enter_ulpm(struct tegra_dc_dsi_data *dsi)
2962 {
2963         u32 val;
2964         int ret;
2965
2966         ret = 0;
2967
2968         val = tegra_dsi_readl(dsi, DSI_HOST_DSI_CONTROL);
2969         val &= ~DSI_HOST_DSI_CONTROL_ULTRA_LOW_POWER(3);
2970         val |= DSI_HOST_DSI_CONTROL_ULTRA_LOW_POWER(ENTER_ULPM);
2971         tegra_dsi_writel(dsi, val, DSI_HOST_DSI_CONTROL);
2972
2973 #if DSI_USE_SYNC_POINTS
2974         ret = tegra_dsi_syncpt(dsi);
2975         if (ret < 0) {
2976                 dev_err(&dsi->dc->ndev->dev,
2977                         "DSI syncpt for ulpm enter failed\n");
2978                 goto fail;
2979         }
2980 #else
2981         /* TODO: Find exact delay required */
2982         mdelay(10);
2983 #endif
2984         dsi->ulpm = true;
2985 fail:
2986         return ret;
2987 }
2988
2989 static int tegra_dsi_exit_ulpm(struct tegra_dc_dsi_data *dsi)
2990 {
2991         u32 val;
2992         int ret;
2993
2994         ret = 0;
2995
2996         val = tegra_dsi_readl(dsi, DSI_HOST_DSI_CONTROL);
2997         val &= ~DSI_HOST_DSI_CONTROL_ULTRA_LOW_POWER(3);
2998         val |= DSI_HOST_DSI_CONTROL_ULTRA_LOW_POWER(EXIT_ULPM);
2999         tegra_dsi_writel(dsi, val, DSI_HOST_DSI_CONTROL);
3000
3001 #if DSI_USE_SYNC_POINTS
3002         ret = tegra_dsi_syncpt(dsi);
3003         if (ret < 0) {
3004                 dev_err(&dsi->dc->ndev->dev,
3005                         "DSI syncpt for ulpm exit failed\n");
3006                 goto fail;
3007         }
3008 #else
3009         /* TODO: Find exact delay required */
3010         mdelay(10);
3011 #endif
3012         dsi->ulpm = false;
3013
3014         val = tegra_dsi_readl(dsi, DSI_HOST_DSI_CONTROL);
3015         val &= ~DSI_HOST_DSI_CONTROL_ULTRA_LOW_POWER(0x3);
3016         val |= DSI_HOST_DSI_CONTROL_ULTRA_LOW_POWER(NORMAL);
3017         tegra_dsi_writel(dsi, val, DSI_HOST_DSI_CONTROL);
3018 fail:
3019         return ret;
3020
3021 }
3022
3023 static void tegra_dsi_send_dc_frames(struct tegra_dc *dc,
3024                                      struct tegra_dc_dsi_data *dsi,
3025                                      int no_of_frames)
3026 {
3027         int err;
3028         u32 frame_period = DIV_ROUND_UP(S_TO_MS(1), dsi->info.refresh_rate);
3029         u8 lp_op = dsi->status.lp_op;
3030         bool switch_to_lp = (dsi->status.lphs == DSI_LPHS_IN_LP_MODE);
3031
3032         if (dsi->status.lphs != DSI_LPHS_IN_HS_MODE) {
3033                 err = tegra_dsi_set_to_hs_mode(dc, dsi,
3034                                 TEGRA_DSI_DRIVEN_BY_DC);
3035                 if (err < 0) {
3036                         dev_err(&dc->ndev->dev,
3037                                 "Switch to HS host mode failed\n");
3038                         return;
3039                 }
3040         }
3041
3042         /*
3043          * Some panels need DC frames be sent under certain
3044          * conditions. We are working on the right fix for this
3045          * requirement, while using this current fix.
3046          */
3047         tegra_dsi_start_dc_stream(dc, dsi);
3048
3049         /*
3050          * Send frames in Continuous or One-shot mode.
3051          */
3052         if (dc->out->flags & TEGRA_DC_OUT_ONE_SHOT_MODE) {
3053                 while (no_of_frames--) {
3054                         tegra_dc_writel(dc, GENERAL_ACT_REQ | NC_HOST_TRIG,
3055                                         DC_CMD_STATE_CONTROL);
3056                         mdelay(frame_period);
3057                 }
3058         } else
3059                 mdelay(no_of_frames * frame_period);
3060
3061         tegra_dsi_stop_dc_stream_at_frame_end(dc, dsi);
3062
3063         if (switch_to_lp) {
3064                 err = tegra_dsi_set_to_lp_mode(dc, dsi, lp_op);
3065                 if (err < 0)
3066                         dev_err(&dc->ndev->dev,
3067                                 "DSI failed to go to LP mode\n");
3068         }
3069 }
3070
3071 static void _tegra_dc_dsi_enable(struct tegra_dc *dc)
3072 {
3073         struct tegra_dc_dsi_data *dsi = tegra_dc_get_outdata(dc);
3074         int err = 0;
3075
3076         mutex_lock(&dsi->lock);
3077         tegra_dc_dsi_hold_host(dc);
3078
3079         tegra_dc_io_start(dc);
3080         /* Stop DC stream before configuring DSI registers
3081          * to avoid visible glitches on panel during transition
3082          * from bootloader to kernel driver
3083          */
3084         tegra_dsi_stop_dc_stream(dc, dsi);
3085
3086         if (dsi->enabled) {
3087                 if (dsi->ulpm) {
3088                         if (tegra_dsi_exit_ulpm(dsi) < 0) {
3089                                 dev_err(&dc->ndev->dev,
3090                                         "DSI failed to exit ulpm\n");
3091                                 goto fail;
3092                         }
3093                 }
3094
3095                 if (dsi->info.panel_reset) {
3096                         /*
3097                          * Certain panels need dc frames be sent before
3098                          * waking panel.
3099                          */
3100                         if (dsi->info.panel_send_dc_frames)
3101                                 tegra_dsi_send_dc_frames(dc, dsi, 2);
3102
3103                         err = tegra_dsi_send_panel_cmd(dc, dsi,
3104                                                         dsi->info.dsi_init_cmd,
3105                                                         dsi->info.n_init_cmd);
3106                         if (err < 0) {
3107                                 dev_err(&dc->ndev->dev,
3108                                 "dsi: error sending dsi init cmd\n");
3109                                 goto fail;
3110                         }
3111                 } else if (dsi->info.dsi_late_resume_cmd) {
3112                         err = tegra_dsi_send_panel_cmd(dc, dsi,
3113                                                 dsi->info.dsi_late_resume_cmd,
3114                                                 dsi->info.n_late_resume_cmd);
3115                         if (err < 0) {
3116                                 dev_err(&dc->ndev->dev,
3117                                 "dsi: error sending late resume cmd\n");
3118                                 goto fail;
3119                         }
3120                 }
3121         } else {
3122                 err = tegra_dsi_init_hw(dc, dsi);
3123                 if (err < 0) {
3124                         dev_err(&dc->ndev->dev,
3125                                 "dsi: not able to init dsi hardware\n");
3126                         goto fail;
3127                 }
3128
3129                 if (dsi->ulpm) {
3130                         if (tegra_dsi_enter_ulpm(dsi) < 0) {
3131                                 dev_err(&dc->ndev->dev,
3132                                         "DSI failed to enter ulpm\n");
3133                                 goto fail;
3134                         }
3135
3136                         tegra_dsi_pad_enable(dsi);
3137
3138                         if (tegra_dsi_exit_ulpm(dsi) < 0) {
3139                                 dev_err(&dc->ndev->dev,
3140                                         "DSI failed to exit ulpm\n");
3141                                 goto fail;
3142                         }
3143                 }
3144
3145                 /*
3146                  * Certain panels need dc frames be sent before
3147                  * waking panel.
3148                  */
3149                 if (dsi->info.panel_send_dc_frames)
3150                         tegra_dsi_send_dc_frames(dc, dsi, 2);
3151
3152                 err = tegra_dsi_set_to_lp_mode(dc, dsi, DSI_LP_OP_WRITE);
3153                 if (err < 0) {
3154                         dev_err(&dc->ndev->dev,
3155                                 "dsi: not able to set to lp mode\n");
3156                         goto fail;
3157                 }
3158
3159                 err = tegra_dsi_send_panel_cmd(dc, dsi, dsi->info.dsi_init_cmd,
3160                                                 dsi->info.n_init_cmd);
3161                 if (err < 0) {
3162                         dev_err(&dc->ndev->dev,
3163                                 "dsi: error while sending dsi init cmd\n");
3164                         goto fail;
3165                 }
3166
3167                 err = tegra_dsi_set_to_hs_mode(dc, dsi,
3168                                 TEGRA_DSI_DRIVEN_BY_DC);
3169                 if (err < 0) {
3170                         dev_err(&dc->ndev->dev,
3171                                 "dsi: not able to set to hs mode\n");
3172                         goto fail;
3173                 }
3174
3175                 dsi->enabled = true;
3176         }
3177
3178         if (dsi->out_ops && dsi->out_ops->enable)
3179                 dsi->out_ops->enable(dsi);
3180
3181         if (dsi->status.driven == DSI_DRIVEN_MODE_DC)
3182                 tegra_dsi_start_dc_stream(dc, dsi);
3183
3184 fail:
3185         tegra_dc_io_end(dc);
3186         tegra_dc_dsi_release_host(dc);
3187         mutex_unlock(&dsi->lock);
3188 }
3189
3190 static void __tegra_dc_dsi_init(struct tegra_dc *dc)
3191 {
3192         struct tegra_dc_dsi_data *dsi = tegra_dc_get_outdata(dc);
3193
3194         tegra_dc_dsi_debug_create(dsi);
3195
3196         if (dsi->info.dsi2lvds_bridge_enable)
3197                 dsi->out_ops = &tegra_dsi2lvds_ops;
3198         else
3199                 dsi->out_ops = NULL;
3200
3201         if (dsi->out_ops && dsi->out_ops->init)
3202                 dsi->out_ops->init(dsi);
3203
3204         tegra_dsi_init_sw(dc, dsi);
3205         /* TODO: Configure the CSI pad configuration */
3206 }
3207
3208 static int tegra_dc_dsi_cp_p_cmd(struct tegra_dsi_cmd *src,
3209                                         struct tegra_dsi_cmd *dst, u16 n_cmd)
3210 {
3211         u16 i;
3212         u16 len;
3213
3214         memcpy(dst, src, sizeof(*dst) * n_cmd);
3215
3216         for (i = 0; i < n_cmd; i++)
3217                 if (src[i].pdata) {
3218                         len = sizeof(*src[i].pdata) *
3219                                         src[i].sp_len_dly.data_len;
3220                         dst[i].pdata = kzalloc(len, GFP_KERNEL);
3221                         if (!dst[i].pdata)
3222                                 goto free_cmd_pdata;
3223                         memcpy(dst[i].pdata, src[i].pdata, len);
3224                 }
3225
3226         return 0;
3227
3228 free_cmd_pdata:
3229         for (--i; i >= 0; i--)
3230                 if (dst[i].pdata)
3231                         kfree(dst[i].pdata);
3232         return -ENOMEM;
3233 }
3234
3235 static int tegra_dc_dsi_cp_info(struct tegra_dc_dsi_data *dsi,
3236                                         struct tegra_dsi_out *p_dsi)
3237 {
3238         struct tegra_dsi_cmd *p_init_cmd;
3239         struct tegra_dsi_cmd *p_early_suspend_cmd = NULL;
3240         struct tegra_dsi_cmd *p_late_resume_cmd = NULL;
3241         struct tegra_dsi_cmd *p_suspend_cmd;
3242         int err;
3243
3244         if (p_dsi->n_data_lanes > MAX_DSI_DATA_LANES)
3245                 return -EINVAL;
3246
3247         p_init_cmd = kzalloc(sizeof(*p_init_cmd) *
3248                                 p_dsi->n_init_cmd, GFP_KERNEL);
3249         if (!p_init_cmd)
3250                 return -ENOMEM;
3251
3252         if (p_dsi->dsi_early_suspend_cmd) {
3253                 p_early_suspend_cmd = kzalloc(sizeof(*p_early_suspend_cmd) *
3254                                         p_dsi->n_early_suspend_cmd,
3255                                         GFP_KERNEL);
3256                 if (!p_early_suspend_cmd) {
3257                         err = -ENOMEM;
3258                         goto err_free_init_cmd;
3259                 }
3260         }
3261
3262         if (p_dsi->dsi_late_resume_cmd) {
3263                 p_late_resume_cmd = kzalloc(sizeof(*p_late_resume_cmd) *
3264                                         p_dsi->n_late_resume_cmd,
3265                                         GFP_KERNEL);
3266                 if (!p_late_resume_cmd) {
3267                         err = -ENOMEM;
3268                         goto err_free_p_early_suspend_cmd;
3269                 }
3270         }
3271
3272         p_suspend_cmd = kzalloc(sizeof(*p_suspend_cmd) * p_dsi->n_suspend_cmd,
3273                                 GFP_KERNEL);
3274         if (!p_suspend_cmd) {
3275                 err = -ENOMEM;
3276                 goto err_free_p_late_resume_cmd;
3277         }
3278
3279         memcpy(&dsi->info, p_dsi, sizeof(dsi->info));
3280
3281         /* Copy panel init cmd */
3282         err = tegra_dc_dsi_cp_p_cmd(p_dsi->dsi_init_cmd,
3283                                                 p_init_cmd, p_dsi->n_init_cmd);
3284         if (err < 0)
3285                 goto err_free;
3286         dsi->info.dsi_init_cmd = p_init_cmd;
3287
3288         /* Copy panel early suspend cmd */
3289         if (p_dsi->dsi_early_suspend_cmd) {
3290                 err = tegra_dc_dsi_cp_p_cmd(p_dsi->dsi_early_suspend_cmd,
3291                                         p_early_suspend_cmd,
3292                                         p_dsi->n_early_suspend_cmd);
3293                 if (err < 0)
3294                         goto err_free;
3295                 dsi->info.dsi_early_suspend_cmd = p_early_suspend_cmd;
3296         }
3297
3298         /* Copy panel late resume cmd */
3299         if (p_dsi->dsi_late_resume_cmd) {
3300                 err = tegra_dc_dsi_cp_p_cmd(p_dsi->dsi_late_resume_cmd,
3301                                                 p_late_resume_cmd,
3302                                                 p_dsi->n_late_resume_cmd);
3303                 if (err < 0)
3304                         goto err_free;
3305                 dsi->info.dsi_late_resume_cmd = p_late_resume_cmd;
3306         }
3307
3308         /* Copy panel suspend cmd */
3309         err = tegra_dc_dsi_cp_p_cmd(p_dsi->dsi_suspend_cmd, p_suspend_cmd,
3310                                         p_dsi->n_suspend_cmd);
3311         if (err < 0)
3312                 goto err_free;
3313         dsi->info.dsi_suspend_cmd = p_suspend_cmd;
3314
3315         if (!dsi->info.panel_reset_timeout_msec)
3316                 dsi->info.panel_reset_timeout_msec =
3317                                                 DEFAULT_PANEL_RESET_TIMEOUT;
3318
3319         if (!dsi->info.panel_buffer_size_byte)
3320                 dsi->info.panel_buffer_size_byte = DEFAULT_PANEL_BUFFER_BYTE;
3321
3322         if (!dsi->info.max_panel_freq_khz) {
3323                 dsi->info.max_panel_freq_khz = DEFAULT_MAX_DSI_PHY_CLK_KHZ;
3324
3325                 if (dsi->info.video_burst_mode >
3326                                 TEGRA_DSI_VIDEO_NONE_BURST_MODE_WITH_SYNC_END){
3327                         dev_err(&dsi->dc->ndev->dev, "DSI: max_panel_freq_khz"
3328                                         "is not set for DSI burst mode.\n");
3329                         dsi->info.video_burst_mode =
3330                                 TEGRA_DSI_VIDEO_BURST_MODE_LOWEST_SPEED;
3331                 }
3332         }
3333
3334         if (!dsi->info.lp_cmd_mode_freq_khz)
3335                 dsi->info.lp_cmd_mode_freq_khz = DEFAULT_LP_CMD_MODE_CLK_KHZ;
3336
3337         if (!dsi->info.chip_id || !dsi->info.chip_rev)
3338                 dev_warn(&dsi->dc->ndev->dev,
3339                         "DSI: Failed to get chip info\n");
3340
3341         if (!dsi->info.lp_read_cmd_mode_freq_khz)
3342                 dsi->info.lp_read_cmd_mode_freq_khz =
3343                         dsi->info.lp_cmd_mode_freq_khz;
3344
3345         /* host mode is for testing only */
3346         dsi->driven_mode = TEGRA_DSI_DRIVEN_BY_DC;
3347         return 0;
3348
3349 err_free:
3350         kfree(p_suspend_cmd);
3351 err_free_p_late_resume_cmd:
3352         kfree(p_late_resume_cmd);
3353 err_free_p_early_suspend_cmd:
3354         kfree(p_early_suspend_cmd);
3355 err_free_init_cmd:
3356         kfree(p_init_cmd);
3357         return err;
3358 }
3359
3360 /* returns next null enumeration from  tegra_dsi_instance */
3361 static inline int tegra_dsi_get_enumeration(void)
3362 {
3363         int i = 0;
3364         for (; i < MAX_DSI_INSTANCE; i++) {
3365                 if (!tegra_dsi_instance[i])
3366                         return i;
3367         }
3368         return -EINVAL;
3369 }
3370
3371 static int _tegra_dc_dsi_init(struct tegra_dc *dc)
3372 {
3373         struct tegra_dc_dsi_data *dsi;
3374         struct resource *res;
3375         struct resource *base_res;
3376         void __iomem *base;
3377         struct clk *dc_clk = NULL;
3378         struct clk *dsi_clk = NULL;
3379         struct clk *dsi_fixed_clk = NULL;
3380         struct tegra_dsi_out *dsi_pdata;
3381         int err = 0;
3382         int dsi_enum = -1;
3383
3384         dsi_enum = tegra_dsi_get_enumeration();
3385         if (dsi_enum < 0) {
3386                 err = -EINVAL;
3387                 dev_err(&dc->ndev->dev, "dsi: invalid enum retured\n");
3388                 return err;
3389         }
3390
3391         dsi = kzalloc(sizeof(*dsi), GFP_KERNEL);
3392         if (!dsi) {
3393                 dev_err(&dc->ndev->dev, "dsi: memory allocation failed\n");
3394                 return -ENOMEM;
3395         }
3396         tegra_dsi_instance[dsi_enum] = dsi;
3397
3398         if (dc->out->dsi->ganged_type) {
3399                 if (dsi_enum)
3400                         res = nvhost_get_resource_byname(dc->ndev,
3401                                                 IORESOURCE_MEM,
3402                                                 "ganged_dsib_regs");
3403                 else
3404                         res = nvhost_get_resource_byname(dc->ndev,
3405                                                 IORESOURCE_MEM,
3406                                                 "ganged_dsia_regs");
3407         } else {
3408                 res = nvhost_get_resource_byname(dc->ndev,
3409                                         IORESOURCE_MEM,
3410                                         "dsi_regs");
3411         }
3412
3413         if (!res) {
3414                 dev_err(&dc->ndev->dev, "dsi: no mem resource\n");
3415                 err = -ENOENT;
3416                 goto err_free_dsi;
3417         }
3418
3419         base_res = request_mem_region(res->start, resource_size(res),
3420                                 dc->ndev->name);
3421         if (!base_res) {
3422                 dev_err(&dc->ndev->dev, "dsi: request_mem_region failed\n");
3423                 err = -EBUSY;
3424                 goto err_free_dsi;
3425         }
3426
3427         base = ioremap(res->start, resource_size(res));
3428         if (!base) {
3429                 dev_err(&dc->ndev->dev, "dsi: registers can't be mapped\n");
3430                 err = -EBUSY;
3431                 goto err_release_regs;
3432         }
3433
3434         dsi_pdata = dc->pdata->default_out->dsi;
3435         if (!dsi_pdata) {
3436                 dev_err(&dc->ndev->dev, "dsi: dsi data not available\n");
3437                 goto err_release_regs;
3438         }
3439
3440         if (dsi_enum)
3441                 dsi_clk = clk_get(&dc->ndev->dev, "dsib");
3442         else
3443                 dsi_clk = clk_get(&dc->ndev->dev, "dsia");
3444
3445         dsi_fixed_clk = clk_get(&dc->ndev->dev, "dsi-fixed");
3446
3447         if (IS_ERR_OR_NULL(dsi_clk) || IS_ERR_OR_NULL(dsi_fixed_clk)) {
3448                 dev_err(&dc->ndev->dev, "dsi: can't get clock\n");
3449                 err = -EBUSY;
3450                 goto err_release_regs;
3451         }
3452
3453         dc_clk = clk_get_sys(dev_name(&dc->ndev->dev), NULL);
3454         if (IS_ERR_OR_NULL(dc_clk)) {
3455                 dev_err(&dc->ndev->dev, "dsi: dc clock %s unavailable\n",
3456                         dev_name(&dc->ndev->dev));
3457                 err = -EBUSY;
3458                 goto err_clk_put;
3459         }
3460
3461         mutex_init(&dsi->lock);
3462         dsi->controller_index = dsi_enum;
3463         dsi->dc = dc;
3464         dsi->base = base;
3465         dsi->base_res = base_res;
3466         dsi->dc_clk = dc_clk;
3467         dsi->dsi_clk = dsi_clk;
3468         dsi->dsi_fixed_clk = dsi_fixed_clk;
3469
3470         err = tegra_dc_dsi_cp_info(dsi, dsi_pdata);
3471         if (err < 0)
3472                 goto err_dsi_data;
3473
3474         tegra_dc_set_outdata(dc, dsi);
3475         __tegra_dc_dsi_init(dc);
3476
3477         return 0;
3478
3479 err_dsi_data:
3480 err_clk_put:
3481         clk_put(dsi_clk);
3482         clk_put(dsi_fixed_clk);
3483 err_release_regs:
3484         release_resource(base_res);
3485 err_free_dsi:
3486         kfree(dsi);
3487
3488         return err;
3489 }
3490
3491 static void _tegra_dc_dsi_destroy(struct tegra_dc *dc)
3492 {
3493         struct tegra_dc_dsi_data *dsi = tegra_dc_get_outdata(dc);
3494         u16 i;
3495         u32 val;
3496
3497         mutex_lock(&dsi->lock);
3498
3499         if (dsi->out_ops && dsi->out_ops->destroy)
3500                 dsi->out_ops->destroy(dsi);
3501
3502         /* free up the pdata */
3503         for (i = 0; i < dsi->info.n_init_cmd; i++) {
3504                 if (dsi->info.dsi_init_cmd[i].pdata)
3505                         kfree(dsi->info.dsi_init_cmd[i].pdata);
3506         }
3507         kfree(dsi->info.dsi_init_cmd);
3508
3509         /* Disable dc stream */
3510         if (dsi->status.dc_stream == DSI_DC_STREAM_ENABLE)
3511                 tegra_dsi_stop_dc_stream_at_frame_end(dc, dsi);
3512
3513         /* Disable dsi phy clock */
3514         if (dsi->status.clk_out == DSI_PHYCLK_OUT_EN)
3515                 tegra_dsi_hs_clk_out_disable(dc, dsi);
3516
3517         val = DSI_POWER_CONTROL_LEG_DSI_ENABLE(TEGRA_DSI_DISABLE);
3518         tegra_dsi_writel(dsi, val, DSI_POWER_CONTROL);
3519
3520         iounmap(dsi->base);
3521         release_resource(dsi->base_res);
3522
3523         clk_put(dsi->dc_clk);
3524         clk_put(dsi->dsi_clk);
3525
3526         mutex_unlock(&dsi->lock);
3527
3528         mutex_destroy(&dsi->lock);
3529         kfree(dsi);
3530 }
3531
3532 static void tegra_dsi_config_phy_clk(struct tegra_dc_dsi_data *dsi,
3533                                                         u32 settings)
3534 {
3535         struct clk *parent_clk = NULL;
3536         struct clk *base_clk = NULL;
3537
3538         /* Disable dsi fast and slow clock */
3539         parent_clk = clk_get_parent(dsi->dsi_clk);
3540         base_clk = clk_get_parent(parent_clk);
3541         if (dsi->info.dsi_instance)
3542                 tegra_clk_cfg_ex(base_clk,
3543                                 TEGRA_CLK_PLLD_CSI_OUT_ENB,
3544                                 settings);
3545         else
3546                 tegra_clk_cfg_ex(base_clk,
3547                                 TEGRA_CLK_PLLD_DSI_OUT_ENB,
3548                                 settings);
3549 }
3550
3551 static int tegra_dsi_deep_sleep(struct tegra_dc *dc,
3552                                 struct tegra_dc_dsi_data *dsi, u32 suspend_aggr)
3553 {
3554         int val = 0;
3555         int err = 0;
3556
3557         if (!dsi->enabled) {
3558                 err = -EPERM;
3559                 goto fail;
3560         }
3561
3562         switch (suspend_aggr) {
3563         case DSI_SUSPEND_FULL:
3564                 /* Suspend DSI panel */
3565                 err = tegra_dsi_set_to_lp_mode(dc, dsi, DSI_LP_OP_WRITE);
3566                 if (err < 0) {
3567                         dev_err(&dc->ndev->dev,
3568                         "DSI failed to go to LP mode\n");
3569                         goto fail;
3570                 }
3571
3572                 err = tegra_dsi_send_panel_cmd(dc, dsi,
3573                                 dsi->info.dsi_suspend_cmd,
3574                                 dsi->info.n_suspend_cmd);
3575                 /*
3576                  * Certain panels need dc frames be sent after
3577                  * putting panel to sleep.
3578                  */
3579                 if (dsi->info.panel_send_dc_frames)
3580                         tegra_dsi_send_dc_frames(dc, dsi, 2);
3581
3582                 if (err < 0) {
3583                         dev_err(&dc->ndev->dev,
3584                                 "dsi: Error sending suspend cmd\n");
3585                         goto fail;
3586                 }
3587         case DSI_HOST_SUSPEND_LV2:
3588                 /* Set DSI to ULPM and suspend pads. DSI will be set to the
3589                  * lowest power state in this level. */
3590                 if (!dsi->ulpm) {
3591                         err = tegra_dsi_enter_ulpm(dsi);
3592                         if (err < 0) {
3593                                 dev_err(&dc->ndev->dev,
3594                                         "DSI failed to enter ulpm\n");
3595                                 goto fail;
3596                         }
3597                 }
3598
3599                 val = DSI_PAD_CONTROL_PAD_PDIO(0x3) |
3600                         DSI_PAD_CONTROL_PAD_PDIO_CLK(0x1) |
3601                         DSI_PAD_CONTROL_PAD_PULLDN_ENAB(TEGRA_DSI_ENABLE);
3602                 tegra_dsi_writel(dsi, val, DSI_PAD_CONTROL);
3603
3604                 /* Suspend core-logic */
3605                 val = DSI_POWER_CONTROL_LEG_DSI_ENABLE(TEGRA_DSI_DISABLE);
3606                 tegra_dsi_writel(dsi, val, DSI_POWER_CONTROL);
3607         case DSI_HOST_SUSPEND_LV1:
3608                 /* Disable dsi fast and slow clock */
3609                 tegra_dsi_config_phy_clk(dsi, TEGRA_DSI_DISABLE);
3610         case DSI_HOST_SUSPEND_LV0:
3611                 /* Disable dsi source clock */
3612                 tegra_dsi_clk_disable(dsi);
3613                 break;
3614         case DSI_NO_SUSPEND:
3615                 break;
3616         default:
3617                 dev_err(&dc->ndev->dev, "DSI suspend aggressiveness"
3618                                                 "is not supported.\n");
3619         }
3620
3621         dsi->enabled = false;
3622
3623         return 0;
3624 fail:
3625         return err;
3626 }
3627
3628 static int tegra_dsi_host_suspend(struct tegra_dc *dc)
3629 {
3630         int err = 0;
3631         struct tegra_dc_dsi_data *dsi = tegra_dc_get_outdata(dc);
3632
3633         if (dsi->host_suspended)
3634                 return 0;
3635
3636         dsi->host_suspended = true;
3637
3638         tegra_dsi_stop_dc_stream(dc, dsi);
3639
3640         err = tegra_dsi_deep_sleep(dc, dsi, dsi->info.suspend_aggr);
3641         if (err < 0)
3642                 dev_err(&dc->ndev->dev,
3643                         "DSI failed to enter deep sleep\n");
3644
3645         tegra_dc_clk_disable(dc);
3646
3647         return err;
3648 }
3649
3650 static int tegra_dsi_host_resume(struct tegra_dc *dc)
3651 {
3652         int val = 0;
3653         int err = 0;
3654         struct tegra_dc_dsi_data *dsi = tegra_dc_get_outdata(dc);
3655
3656         if (!dsi->host_suspended)
3657                 return 0;
3658
3659         tegra_dc_clk_enable(dc);
3660         switch (dsi->info.suspend_aggr) {
3661         case DSI_HOST_SUSPEND_LV0:
3662                 tegra_dsi_clk_enable(dsi);
3663                 break;
3664         case DSI_HOST_SUSPEND_LV1:
3665                 tegra_dsi_config_phy_clk(dsi, TEGRA_DSI_ENABLE);
3666                 tegra_dsi_clk_enable(dsi);
3667                 break;
3668         case DSI_HOST_SUSPEND_LV2:
3669                 tegra_dsi_config_phy_clk(dsi, TEGRA_DSI_ENABLE);
3670                 tegra_dsi_clk_enable(dsi);
3671
3672                 tegra_dsi_writel(dsi,
3673                         DSI_POWER_CONTROL_LEG_DSI_ENABLE(TEGRA_DSI_ENABLE),
3674                         DSI_POWER_CONTROL);
3675
3676                 if (dsi->ulpm) {
3677                         err = tegra_dsi_enter_ulpm(dsi);
3678                         if (err < 0) {
3679                                 dev_err(&dc->ndev->dev,
3680                                         "DSI failed to enter ulpm\n");
3681                                 goto fail;
3682                         }
3683
3684                         val = tegra_dsi_readl(dsi, DSI_PAD_CONTROL);
3685                         val &= ~(DSI_PAD_CONTROL_PAD_PDIO(0x3) |
3686                                 DSI_PAD_CONTROL_PAD_PDIO_CLK(0x1) |
3687                                 DSI_PAD_CONTROL_PAD_PULLDN_ENAB(0x1));
3688                         tegra_dsi_writel(dsi, val, DSI_PAD_CONTROL);
3689
3690                         if (tegra_dsi_exit_ulpm(dsi) < 0) {
3691                                 dev_err(&dc->ndev->dev,
3692                                         "DSI failed to exit ulpm\n");
3693                                 goto fail;
3694                         }
3695                 }
3696                 break;
3697         case DSI_NO_SUSPEND:
3698                 break;
3699         default:
3700                 dev_err(&dc->ndev->dev, "DSI suspend aggressivenes"
3701                                                 "is not supported.\n");
3702         }
3703
3704         tegra_dsi_start_dc_stream(dc, dsi);
3705         dsi->enabled = true;
3706         dsi->host_suspended = false;
3707 fail:
3708         return err;
3709 }
3710
3711 static void tegra_dc_dsi_disable(struct tegra_dc *dc)
3712 {
3713         int err;
3714         struct tegra_dc_dsi_data *dsi = tegra_dc_get_outdata(dc);
3715
3716         tegra_dc_io_start(dc);
3717         mutex_lock(&dsi->lock);
3718
3719         if (dsi->status.dc_stream == DSI_DC_STREAM_ENABLE)
3720                 tegra_dsi_stop_dc_stream_at_frame_end(dc, dsi);
3721
3722         if (dsi->out_ops && dsi->out_ops->disable)
3723                 dsi->out_ops->disable(dsi);
3724
3725         if (dsi->info.power_saving_suspend) {
3726                 if (tegra_dsi_deep_sleep(dc, dsi, DSI_SUSPEND_FULL) < 0) {
3727                         dev_err(&dc->ndev->dev,
3728                                 "DSI failed to enter deep sleep\n");
3729                         goto fail;
3730                 }
3731         } else {
3732                 if (dsi->info.dsi_early_suspend_cmd) {
3733                         err = tegra_dsi_send_panel_cmd(dc, dsi,
3734                                 dsi->info.dsi_early_suspend_cmd,
3735                                 dsi->info.n_early_suspend_cmd);
3736                         if (err < 0) {
3737                                 dev_err(&dc->ndev->dev,
3738                                 "dsi: Error sending early suspend cmd\n");
3739                                 goto fail;
3740                         }
3741                 }
3742
3743                 if (!dsi->ulpm) {
3744                         if (tegra_dsi_enter_ulpm(dsi) < 0) {
3745                                 dev_err(&dc->ndev->dev,
3746                                         "DSI failed to enter ulpm\n");
3747                                 goto fail;
3748                         }
3749                 }
3750         }
3751 fail:
3752         mutex_unlock(&dsi->lock);
3753         tegra_dc_io_end(dc);
3754 }
3755
3756 #ifdef CONFIG_PM
3757 static void _tegra_dc_dsi_suspend(struct tegra_dc *dc)
3758 {
3759         struct tegra_dc_dsi_data *dsi;
3760
3761         dsi = tegra_dc_get_outdata(dc);
3762
3763         if (!dsi->enabled)
3764                 return;
3765
3766         tegra_dc_io_start(dc);
3767         mutex_lock(&dsi->lock);
3768
3769         if (dsi->out_ops && dsi->out_ops->suspend)
3770                 dsi->out_ops->suspend(dsi);
3771
3772         if (!dsi->info.power_saving_suspend) {
3773                 if (dsi->ulpm) {
3774                         if (tegra_dsi_exit_ulpm(dsi) < 0) {
3775                                 dev_err(&dc->ndev->dev,
3776                                         "DSI failed to exit ulpm");
3777                                 goto fail;
3778                         }
3779                 }
3780
3781                 if (tegra_dsi_deep_sleep(dc, dsi, DSI_SUSPEND_FULL) < 0) {
3782                         dev_err(&dc->ndev->dev,
3783                                 "DSI failed to enter deep sleep\n");
3784                         goto fail;
3785                 }
3786         }
3787 fail:
3788         mutex_unlock(&dsi->lock);
3789         tegra_dc_io_end(dc);
3790 }
3791
3792 static void _tegra_dc_dsi_resume(struct tegra_dc *dc)
3793 {
3794         struct tegra_dc_dsi_data *dsi;
3795
3796         dsi = tegra_dc_get_outdata(dc);
3797
3798         /* No dsi config required since tegra_dc_dsi_enable
3799          * will reconfigure the controller from scratch
3800          */
3801
3802          if (dsi->out_ops && dsi->out_ops->resume)
3803                 dsi->out_ops->resume(dsi);
3804 }
3805
3806 static void tegra_dc_dsi_suspend(struct tegra_dc *dc)
3807 {
3808         _tegra_dc_dsi_suspend(dc);
3809
3810         if (dc->out->dsi->ganged_type) {
3811                 tegra_dc_set_outdata(dc, tegra_dsi_instance[DSI_INSTANCE_1]);
3812                 _tegra_dc_dsi_suspend(dc);
3813                 tegra_dc_set_outdata(dc, tegra_dsi_instance[DSI_INSTANCE_0]);
3814         }
3815 }
3816
3817 static void tegra_dc_dsi_resume(struct tegra_dc *dc)
3818 {
3819         _tegra_dc_dsi_resume(dc);
3820
3821         if (dc->out->dsi->ganged_type) {
3822                 tegra_dc_set_outdata(dc, tegra_dsi_instance[DSI_INSTANCE_1]);
3823                 _tegra_dc_dsi_resume(dc);
3824                 tegra_dc_set_outdata(dc, tegra_dsi_instance[DSI_INSTANCE_0]);
3825         }
3826 }
3827 #endif
3828
3829 static int tegra_dc_dsi_init(struct tegra_dc *dc)
3830 {
3831         int err = 0;
3832
3833         err = _tegra_dc_dsi_init(dc);
3834         if (err < 0) {
3835                 dev_err(&dc->ndev->dev,
3836                         "dsi: Instance A init failed\n");
3837                 goto fail;
3838         }
3839
3840         if (dc->out->dsi->ganged_type) {
3841                 err = _tegra_dc_dsi_init(dc);
3842                 if (err < 0) {
3843                         dev_err(&dc->ndev->dev,
3844                                 "dsi: Instance B init failed\n");
3845                         goto fail;
3846                 }
3847                 tegra_dc_set_outdata(dc, tegra_dsi_instance[DSI_INSTANCE_0]);
3848         }
3849 fail:
3850         return err;
3851 }
3852
3853 static void tegra_dc_dsi_destroy(struct tegra_dc *dc)
3854 {
3855         _tegra_dc_dsi_destroy(dc);
3856
3857         if (dc->out->dsi->ganged_type) {
3858                 tegra_dc_set_outdata(dc, tegra_dsi_instance[DSI_INSTANCE_1]);
3859                 _tegra_dc_dsi_destroy(dc);
3860                 tegra_dc_set_outdata(dc, tegra_dsi_instance[DSI_INSTANCE_0]);
3861         }
3862 }
3863
3864 static void tegra_dc_dsi_enable(struct tegra_dc *dc)
3865 {
3866         _tegra_dc_dsi_enable(dc);
3867
3868         if (dc->out->dsi->ganged_type) {
3869                 tegra_dc_set_outdata(dc, tegra_dsi_instance[DSI_INSTANCE_1]);
3870                 _tegra_dc_dsi_enable(dc);
3871                 tegra_dc_set_outdata(dc, tegra_dsi_instance[DSI_INSTANCE_0]);
3872         }
3873 }
3874
3875 struct tegra_dc_out_ops tegra_dc_dsi_ops = {
3876         .init = tegra_dc_dsi_init,
3877         .destroy = tegra_dc_dsi_destroy,
3878         .enable = tegra_dc_dsi_enable,
3879         .disable = tegra_dc_dsi_disable,
3880         .hold = tegra_dc_dsi_hold_host,
3881         .release = tegra_dc_dsi_release_host,
3882         .idle = tegra_dc_dsi_idle,
3883 #ifdef CONFIG_PM
3884         .suspend = tegra_dc_dsi_suspend,
3885         .resume = tegra_dc_dsi_resume,
3886 #endif
3887 };