2 * drivers/video/tegra/dc/dsi.c
4 * Copyright (c) 2011, NVIDIA Corporation.
6 * This software is licensed under the terms of the GNU General Public
7 * License version 2, as published by the Free Software Foundation, and
8 * may be copied, distributed, and modified under those terms.
10 * This program is distributed in the hope that it will be useful,
11 * but WITHOUT ANY WARRANTY; without even the implied warranty of
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 * GNU General Public License for more details.
17 #include <linux/clk.h>
18 #include <linux/delay.h>
19 #include <linux/err.h>
21 #include <linux/gpio.h>
22 #include <linux/interrupt.h>
23 #include <linux/kernel.h>
24 #include <linux/slab.h>
25 #include <linux/spinlock.h>
26 #include <linux/workqueue.h>
31 #include <mach/nvhost.h>
32 #include <../gpio-names.h>
39 #define DSI_USE_SYNC_POINTS 1
41 #define DSI_STOP_DC_DURATION_MSEC 1000
43 #define DSI_MODULE_NOT_INIT 0x0
44 #define DSI_MODULE_INIT 0x1
46 #define DSI_LPHS_NOT_INIT 0x0
47 #define DSI_LPHS_IN_LP_MODE 0x1
48 #define DSI_LPHS_IN_HS_MODE 0x2
50 #define DSI_VIDEO_TYPE_NOT_INIT 0x0
51 #define DSI_VIDEO_TYPE_VIDEO_MODE 0x1
52 #define DSI_VIDEO_TYPE_CMD_MODE 0x2
54 #define DSI_DRIVEN_MODE_NOT_INIT 0x0
55 #define DSI_DRIVEN_MODE_DC 0x1
56 #define DSI_DRIVEN_MODE_HOST 0x2
58 #define DSI_PHYCLK_OUT_DIS 0x0
59 #define DSI_PHYCLK_OUT_EN 0x1
61 #define DSI_PHYCLK_NOT_INIT 0x0
62 #define DSI_PHYCLK_CONTINUOUS 0x1
63 #define DSI_PHYCLK_TX_ONLY 0x2
65 #define DSI_CLK_BURST_NOT_INIT 0x0
66 #define DSI_CLK_BURST_NONE_BURST 0x1
67 #define DSI_CLK_BURST_BURST_MODE 0x2
69 #define DSI_DC_STREAM_DISABLE 0x0
70 #define DSI_DC_STREAM_ENABLE 0x1
87 /* source of video data */
89 TEGRA_DSI_DRIVEN_BY_DC,
90 TEGRA_DSI_DRIVEN_BY_HOST,
93 struct tegra_dc_dsi_data {
96 struct resource *base_res;
104 /* data from board info */
105 struct tegra_dsi_out info;
107 struct dsi_status status;
115 u32 default_shift_clk_div;
116 u32 default_pixel_clk_khz;
117 u32 default_hs_clk_khz;
120 u32 target_hs_clk_khz;
121 u32 target_lp_clk_khz;
126 u16 current_bit_clk_ns;
127 u32 current_dsi_clk_khz;
135 const u32 dsi_pkt_seq_reg[NUMOF_PKT_SEQ] = {
150 const u32 dsi_pkt_seq_video_non_burst_syne[NUMOF_PKT_SEQ] = {
151 PKT_ID0(CMD_VS) | PKT_LEN0(0) | PKT_ID1(CMD_EOT) | PKT_LEN1(0) | PKT_LP,
153 PKT_ID0(CMD_VE) | PKT_LEN0(0) | PKT_ID1(CMD_EOT) | PKT_LEN1(0) | PKT_LP,
155 PKT_ID0(CMD_HS) | PKT_LEN0(0) | PKT_ID1(CMD_EOT) | PKT_LEN1(0) | PKT_LP,
157 PKT_ID0(CMD_HS) | PKT_LEN0(0) | PKT_ID1(CMD_BLNK) | PKT_LEN1(1) |
158 PKT_ID2(CMD_HE) | PKT_LEN2(0),
159 PKT_ID3(CMD_BLNK) | PKT_LEN3(2) | PKT_ID4(CMD_RGB) | PKT_LEN4(3) |
160 PKT_ID5(CMD_BLNK) | PKT_LEN5(4),
161 PKT_ID0(CMD_HS) | PKT_LEN0(0) | PKT_ID1(CMD_EOT) | PKT_LEN1(0) | PKT_LP,
163 PKT_ID0(CMD_HS) | PKT_LEN0(0) | PKT_ID1(CMD_BLNK) | PKT_LEN1(1) |
164 PKT_ID2(CMD_HE) | PKT_LEN2(0),
165 PKT_ID3(CMD_BLNK) | PKT_LEN3(2) | PKT_ID4(CMD_RGB) | PKT_LEN4(3) |
166 PKT_ID5(CMD_BLNK) | PKT_LEN5(4),
169 const u32 dsi_pkt_seq_video_non_burst[NUMOF_PKT_SEQ] = {
170 PKT_ID0(CMD_VS) | PKT_LEN0(0) | PKT_ID1(CMD_EOT) | PKT_LEN1(0) | PKT_LP,
172 PKT_ID0(CMD_HS) | PKT_LEN0(0) | PKT_ID1(CMD_EOT) | PKT_LEN1(0) | PKT_LP,
174 PKT_ID0(CMD_HS) | PKT_LEN0(0) | PKT_ID1(CMD_EOT) | PKT_LEN1(0) | PKT_LP,
176 PKT_ID0(CMD_HS) | PKT_LEN0(0) | PKT_ID1(CMD_BLNK) | PKT_LEN1(2) |
177 PKT_ID2(CMD_RGB) | PKT_LEN2(3),
178 PKT_ID3(CMD_BLNK) | PKT_LEN3(4),
179 PKT_ID0(CMD_HS) | PKT_LEN0(0) | PKT_ID1(CMD_EOT) | PKT_LEN1(0) | PKT_LP,
181 PKT_ID0(CMD_HS) | PKT_LEN0(0) | PKT_ID1(CMD_BLNK) | PKT_LEN1(2) |
182 PKT_ID2(CMD_RGB) | PKT_LEN2(3),
183 PKT_ID3(CMD_BLNK) | PKT_LEN3(4),
186 static const u32 dsi_pkt_seq_video_burst[NUMOF_PKT_SEQ] = {
187 PKT_ID0(CMD_VS) | PKT_LEN0(0) | PKT_ID1(CMD_EOT) | PKT_LEN1(7) | PKT_LP,
189 PKT_ID0(CMD_HS) | PKT_LEN0(0) | PKT_ID1(CMD_EOT) | PKT_LEN1(7) | PKT_LP,
191 PKT_ID0(CMD_HS) | PKT_LEN0(0) | PKT_ID1(CMD_EOT) | PKT_LEN1(7) | PKT_LP,
193 PKT_ID0(CMD_HS) | PKT_LEN0(0) | PKT_ID1(CMD_BLNK) | PKT_LEN1(2)|
194 PKT_ID2(CMD_RGB) | PKT_LEN2(3) | PKT_LP,
195 PKT_ID0(CMD_EOT) | PKT_LEN0(7),
196 PKT_ID0(CMD_HS) | PKT_LEN0(0) | PKT_ID1(CMD_EOT) | PKT_LEN1(7) | PKT_LP,
198 PKT_ID0(CMD_HS) | PKT_LEN0(0) | PKT_ID1(CMD_BLNK) | PKT_LEN1(2)|
199 PKT_ID2(CMD_RGB) | PKT_LEN2(3) | PKT_LP,
200 PKT_ID0(CMD_EOT) | PKT_LEN0(7),
203 static const u32 dsi_pkt_seq_video_burst_no_eot[NUMOF_PKT_SEQ] = {
204 PKT_ID0(CMD_VS) | PKT_LEN0(0) | PKT_ID1(CMD_EOT) | PKT_LEN1(0) | PKT_LP,
206 PKT_ID0(CMD_HS) | PKT_LEN0(0) | PKT_ID1(CMD_EOT) | PKT_LEN1(0) | PKT_LP,
208 PKT_ID0(CMD_HS) | PKT_LEN0(0) | PKT_ID1(CMD_EOT) | PKT_LEN1(0) | PKT_LP,
210 PKT_ID0(CMD_HS) | PKT_LEN0(0) | PKT_ID1(CMD_BLNK) | PKT_LEN1(2)|
211 PKT_ID2(CMD_RGB) | PKT_LEN2(3) | PKT_LP,
212 PKT_ID0(CMD_EOT) | PKT_LEN0(0),
213 PKT_ID0(CMD_HS) | PKT_LEN0(0) | PKT_ID1(CMD_EOT) | PKT_LEN1(0) | PKT_LP,
215 PKT_ID0(CMD_HS) | PKT_LEN0(0) | PKT_ID1(CMD_BLNK) | PKT_LEN1(2)|
216 PKT_ID2(CMD_RGB) | PKT_LEN2(3) | PKT_LP,
217 PKT_ID0(CMD_EOT) | PKT_LEN0(0),
220 /* TODO: verify with hw about this format */
221 const u32 dsi_pkt_seq_cmd_mode[NUMOF_PKT_SEQ] = {
228 PKT_ID0(CMD_LONGW) | PKT_LEN0(3) | PKT_ID1(CMD_EOT) | PKT_LEN1(7),
232 PKT_ID0(CMD_LONGW) | PKT_LEN0(3) | PKT_ID1(CMD_EOT) | PKT_LEN1(7),
236 const u32 init_reg[] = {
258 DSI_HOST_DSI_CONTROL,
265 DSI_INIT_SEQ_CONTROL,
272 inline unsigned long tegra_dsi_readl(struct tegra_dc_dsi_data *dsi, u32 reg)
274 return readl(dsi->base + reg * 4);
276 EXPORT_SYMBOL(tegra_dsi_readl);
278 inline void tegra_dsi_writel(struct tegra_dc_dsi_data *dsi, u32 val, u32 reg)
280 writel(val, dsi->base + reg * 4);
282 EXPORT_SYMBOL(tegra_dsi_writel);
284 static int tegra_dsi_syncpt(struct tegra_dc_dsi_data *dsi)
291 dsi->syncpt_val = nvhost_syncpt_read(
292 &dsi->dc->ndev->host->syncpt, dsi->syncpt_id);
294 val = DSI_INCR_SYNCPT_COND(OP_DONE) |
295 DSI_INCR_SYNCPT_INDX(dsi->syncpt_id);
296 tegra_dsi_writel(dsi, val, DSI_INCR_SYNCPT);
298 /* TODO: Use interrupt rather than polling */
299 ret = nvhost_syncpt_wait(&dsi->dc->ndev->host->syncpt,
300 dsi->syncpt_id, dsi->syncpt_val + 1);
302 printk(KERN_ERR "DSI sync point failure\n");
312 static u32 tegra_dsi_get_hs_clk_rate(struct tegra_dc_dsi_data *dsi)
314 u32 dsi_clock_rate_khz;
316 switch (dsi->info.video_burst_mode) {
317 case TEGRA_DSI_VIDEO_BURST_MODE_LOW_SPEED:
318 case TEGRA_DSI_VIDEO_BURST_MODE_MEDIUM_SPEED:
319 case TEGRA_DSI_VIDEO_BURST_MODE_FAST_SPEED:
320 case TEGRA_DSI_VIDEO_BURST_MODE_FASTEST_SPEED:
321 /* Calculate DSI HS clock rate for DSI burst mode */
322 dsi_clock_rate_khz = dsi->default_pixel_clk_khz *
325 case TEGRA_DSI_VIDEO_NONE_BURST_MODE:
326 case TEGRA_DSI_VIDEO_NONE_BURST_MODE_WITH_SYNC_END:
327 case TEGRA_DSI_VIDEO_BURST_MODE_LOWEST_SPEED:
329 /* Clock rate is default DSI clock rate for non-burst mode */
330 dsi_clock_rate_khz = dsi->default_hs_clk_khz;
334 return dsi_clock_rate_khz;
337 static u32 tegra_dsi_get_lp_clk_rate(struct tegra_dc_dsi_data *dsi)
339 u32 dsi_clock_rate_khz;
341 if (dsi->info.enable_hs_clock_on_lp_cmd_mode)
342 if (dsi->info.hs_clk_in_lp_cmd_mode_freq_khz)
344 dsi->info.hs_clk_in_lp_cmd_mode_freq_khz;
346 dsi_clock_rate_khz = tegra_dsi_get_hs_clk_rate(dsi);
348 dsi_clock_rate_khz = dsi->info.lp_cmd_mode_freq_khz;
350 return dsi_clock_rate_khz;
353 static u32 tegra_dsi_get_shift_clk_div(struct tegra_dc_dsi_data *dsi)
356 u32 max_shift_clk_div;
360 /* Get the real value of default shift_clk_div. default_shift_clk_div
361 * holds the real value of shift_clk_div. */
362 shift_clk_div = dsi->default_shift_clk_div;
364 /* Calculate shift_clk_div which can matche the video_burst_mode.*/
365 if (dsi->info.video_burst_mode >=
366 TEGRA_DSI_VIDEO_BURST_MODE_LOWEST_SPEED) {
367 /* The max_shift_clk_div is multiplied by 10 to save the
369 if (dsi->info.max_panel_freq_khz >= dsi->default_hs_clk_khz)
370 max_shift_clk_div = dsi->info.max_panel_freq_khz
371 * shift_clk_div * 10 / dsi->default_hs_clk_khz;
373 max_shift_clk_div = shift_clk_div * 10;
375 burst_width = dsi->info.video_burst_mode
376 - TEGRA_DSI_VIDEO_BURST_MODE_LOWEST_SPEED;
377 burst_width_max = TEGRA_DSI_VIDEO_BURST_MODE_FASTEST_SPEED
378 - TEGRA_DSI_VIDEO_BURST_MODE_LOWEST_SPEED;
380 shift_clk_div = (max_shift_clk_div - shift_clk_div * 10) *
381 burst_width / (burst_width_max * 10) + shift_clk_div;
384 return shift_clk_div;
387 static void tegra_dsi_init_sw(struct tegra_dc *dc,
388 struct tegra_dc_dsi_data *dsi)
396 switch (dsi->info.pixel_format) {
397 case TEGRA_DSI_PIXEL_FORMAT_16BIT_P:
398 /* 2 bytes per pixel */
399 dsi->pixel_scaler_mul = 2;
400 dsi->pixel_scaler_div = 1;
402 case TEGRA_DSI_PIXEL_FORMAT_18BIT_P:
403 /* 2.25 bytes per pixel */
404 dsi->pixel_scaler_mul = 9;
405 dsi->pixel_scaler_div = 4;
407 case TEGRA_DSI_PIXEL_FORMAT_18BIT_NP:
408 case TEGRA_DSI_PIXEL_FORMAT_24BIT_P:
409 /* 3 bytes per pixel */
410 dsi->pixel_scaler_mul = 3;
411 dsi->pixel_scaler_div = 1;
417 dsi->controller_index = dc->ndev->id;
419 dsi->enabled = false;
420 dsi->clk_ref = false;
422 dsi->dsi_control_val =
423 DSI_CONTROL_VIRTUAL_CHANNEL(dsi->info.virtual_channel) |
424 DSI_CONTROL_NUM_DATA_LANES(dsi->info.n_data_lanes - 1) |
425 DSI_CONTROL_VID_SOURCE(dsi->controller_index) |
426 DSI_CONTROL_DATA_FORMAT(dsi->info.pixel_format);
428 /* Below we are going to calculate dsi and dc clock rate.
429 * Calcuate the horizontal and vertical width. */
430 h_width_pixels = dc->mode.h_back_porch + dc->mode.h_front_porch +
431 dc->mode.h_sync_width + dc->mode.h_active;
432 v_width_lines = dc->mode.v_back_porch + dc->mode.v_front_porch +
433 dc->mode.v_sync_width + dc->mode.v_active;
435 /* Calculate minimum required pixel rate. */
436 pixel_clk_hz = h_width_pixels * v_width_lines * dsi->info.refresh_rate;
438 dc->pixel_clk = pixel_clk_hz;
440 /* Calculate minimum byte rate on DSI interface. */
441 byte_clk_hz = (pixel_clk_hz * dsi->pixel_scaler_mul) /
442 (dsi->pixel_scaler_div * dsi->info.n_data_lanes);
444 /* Round up to multiple of mega hz. */
445 plld_clk_mhz = DIV_ROUND_UP((byte_clk_hz * NUMOF_BIT_PER_BYTE),
448 /* Calculate default real shift_clk_div. */
449 dsi->default_shift_clk_div = (NUMOF_BIT_PER_BYTE / 2) *
450 dsi->pixel_scaler_mul / (dsi->pixel_scaler_div *
451 dsi->info.n_data_lanes);
452 /* Calculate default DSI hs clock. DSI interface is double data rate.
453 * Data is transferred on both rising and falling edge of clk, div by 2
454 * to get the actual clock rate.
456 dsi->default_hs_clk_khz = plld_clk_mhz * 1000 / 2;
457 dsi->default_pixel_clk_khz = plld_clk_mhz * 1000 / 2
458 / dsi->default_shift_clk_div;
460 /* Get the actual shift_clk_div and clock rates. */
461 dsi->shift_clk_div = tegra_dsi_get_shift_clk_div(dsi);
462 dsi->target_lp_clk_khz = tegra_dsi_get_lp_clk_rate(dsi);
463 dsi->target_hs_clk_khz = tegra_dsi_get_hs_clk_rate(dsi);
465 dev_info(&dc->ndev->dev, "DSI: HS clock rate is %d\n",
466 dsi->target_hs_clk_khz);
468 dsi->controller_index = dc->ndev->id;
470 #if DSI_USE_SYNC_POINTS
471 dsi->syncpt_id = NVSYNCPT_DSI;
475 * Force video clock to be continuous mode if
476 * enable_hs_clock_on_lp_cmd_mode is set
478 if (dsi->info.enable_hs_clock_on_lp_cmd_mode) {
479 if (dsi->info.video_clock_mode !=
480 TEGRA_DSI_VIDEO_CLOCK_CONTINUOUS)
481 printk("Force to clock continuous mode\n");
483 dsi->info.video_clock_mode = TEGRA_DSI_VIDEO_CLOCK_CONTINUOUS;
488 static void tegra_dsi_get_phy_timing(struct tegra_dc_dsi_data *dsi,
489 struct dsi_phy_timing_inclk *phy_timing_clk,
493 phy_timing_clk->t_hsdexit = dsi->info.phy_timing.t_hsdexit_ns ?
494 (dsi->info.phy_timing.t_hsdexit_ns / clk_ns) :
495 (T_HSEXIT_DEFAULT(clk_ns));
497 phy_timing_clk->t_hstrail = dsi->info.phy_timing.t_hstrail_ns ?
498 (dsi->info.phy_timing.t_hstrail_ns / clk_ns) :
499 (T_HSTRAIL_DEFAULT(clk_ns));
501 phy_timing_clk->t_datzero = dsi->info.phy_timing.t_datzero_ns ?
502 (dsi->info.phy_timing.t_datzero_ns / clk_ns) :
503 (T_DATZERO_DEFAULT(clk_ns));
505 phy_timing_clk->t_hsprepr = dsi->info.phy_timing.t_hsprepr_ns ?
506 (dsi->info.phy_timing.t_hsprepr_ns / clk_ns) :
507 (T_HSPREPR_DEFAULT(clk_ns));
509 phy_timing_clk->t_clktrail = dsi->info.phy_timing.t_clktrail_ns ?
510 (dsi->info.phy_timing.t_clktrail_ns / clk_ns) :
511 (T_CLKTRAIL_DEFAULT(clk_ns));
513 phy_timing_clk->t_clkpost = dsi->info.phy_timing.t_clkpost_ns ?
514 (dsi->info.phy_timing.t_clkpost_ns / clk_ns) :
515 (T_CLKPOST_DEFAULT(clk_ns));
517 phy_timing_clk->t_clkzero = dsi->info.phy_timing.t_clkzero_ns ?
518 (dsi->info.phy_timing.t_clkzero_ns / clk_ns) :
519 (T_CLKZERO_DEFAULT(clk_ns));
521 phy_timing_clk->t_tlpx = dsi->info.phy_timing.t_tlpx_ns ?
522 (dsi->info.phy_timing.t_tlpx_ns / clk_ns) :
523 (T_TLPX_DEFAULT(clk_ns));
525 phy_timing_clk->t_clkpre = T_CLKPRE_DEFAULT(clk_ns);
526 phy_timing_clk->t_clkprepare = T_CLKPREPARE_DEFAULT(clk_ns);
527 phy_timing_clk->t_wakeup = T_WAKEUP_DEFAULT(clk_ns);
529 phy_timing_clk->t_taget = 5 * phy_timing_clk->t_tlpx;
530 phy_timing_clk->t_tasure = 2 * phy_timing_clk->t_tlpx;
531 phy_timing_clk->t_tago = 4 * phy_timing_clk->t_tlpx;
534 static void tegra_dsi_set_phy_timing(struct tegra_dc_dsi_data *dsi)
537 struct dsi_phy_timing_inclk phy_timing;
539 tegra_dsi_get_phy_timing(dsi, &phy_timing, dsi->current_bit_clk_ns);
541 val = DSI_PHY_TIMING_0_THSDEXIT(phy_timing.t_hsdexit) |
542 DSI_PHY_TIMING_0_THSTRAIL(phy_timing.t_hstrail) |
543 DSI_PHY_TIMING_0_TDATZERO(phy_timing.t_datzero) |
544 DSI_PHY_TIMING_0_THSPREPR(phy_timing.t_hsprepr);
545 tegra_dsi_writel(dsi, val, DSI_PHY_TIMING_0);
547 val = DSI_PHY_TIMING_1_TCLKTRAIL(phy_timing.t_clktrail) |
548 DSI_PHY_TIMING_1_TCLKPOST(phy_timing.t_clkpost) |
549 DSI_PHY_TIMING_1_TCLKZERO(phy_timing.t_clkzero) |
550 DSI_PHY_TIMING_1_TTLPX(phy_timing.t_tlpx);
551 tegra_dsi_writel(dsi, val, DSI_PHY_TIMING_1);
553 val = DSI_PHY_TIMING_2_TCLKPREPARE(phy_timing.t_clkprepare) |
554 DSI_PHY_TIMING_2_TCLKPRE(phy_timing.t_clkpre) |
555 DSI_PHY_TIMING_2_TWAKEUP(phy_timing.t_wakeup);
556 tegra_dsi_writel(dsi, val, DSI_PHY_TIMING_2);
558 val = DSI_BTA_TIMING_TTAGET(phy_timing.t_taget) |
559 DSI_BTA_TIMING_TTASURE(phy_timing.t_tasure) |
560 DSI_BTA_TIMING_TTAGO(phy_timing.t_tago);
561 tegra_dsi_writel(dsi, val, DSI_BTA_TIMING);
564 static u32 tegra_dsi_sol_delay_burst(struct tegra_dc *dc,
565 struct tegra_dc_dsi_data *dsi)
567 u32 dsi_to_pixel_clk_ratio;
570 u32 mipi_clk_adj_kHz;
572 struct tegra_dc_mode *dc_modes = &dc->mode;
574 /* Get Fdsi/Fpixel ration (note: Fdsi si in bit format) */
575 dsi_to_pixel_clk_ratio = (dsi->current_dsi_clk_khz * 2 +
576 dsi->default_pixel_clk_khz - 1) / dsi->default_pixel_clk_khz;
578 /* Convert Fdsi to byte format */
579 dsi_to_pixel_clk_ratio *= 1000/8;
581 /* Multiplying by 1000 so that we don't loose the fraction part */
582 temp = dc_modes->h_active * 1000;
583 temp1 = dc_modes->h_active + dc_modes->h_back_porch +
584 dc_modes->h_sync_width;
586 sol_delay = temp1 * dsi_to_pixel_clk_ratio -
587 temp * dsi->pixel_scaler_mul /
588 (dsi->pixel_scaler_div * dsi->info.n_data_lanes);
590 /* Do rounding on sol delay */
591 sol_delay = (sol_delay + 1000 - 1)/1000;
594 * 1. find out the correct sol fifo depth to use
595 * 2. verify with hw about the clamping function
597 if (sol_delay > (480 * 4)) {
598 sol_delay = (480 * 4);
599 mipi_clk_adj_kHz = sol_delay +
600 (dc_modes->h_active * dsi->pixel_scaler_mul) /
601 (dsi->info.n_data_lanes * dsi->pixel_scaler_div);
603 mipi_clk_adj_kHz *= (dsi->default_pixel_clk_khz / temp1);
605 mipi_clk_adj_kHz *= 4;
608 dsi->target_hs_clk_khz = mipi_clk_adj_kHz;
613 static void tegra_dsi_set_sol_delay(struct tegra_dc *dc,
614 struct tegra_dc_dsi_data *dsi)
618 if (dsi->info.video_burst_mode == TEGRA_DSI_VIDEO_NONE_BURST_MODE ||
619 dsi->info.video_burst_mode ==
620 TEGRA_DSI_VIDEO_NONE_BURST_MODE_WITH_SYNC_END) {
621 sol_delay = NUMOF_BIT_PER_BYTE * dsi->pixel_scaler_mul /
622 (dsi->pixel_scaler_div * dsi->info.n_data_lanes);
623 dsi->status.clk_burst = DSI_CLK_BURST_NONE_BURST;
625 sol_delay = tegra_dsi_sol_delay_burst(dc, dsi);
626 dsi->status.clk_burst = DSI_CLK_BURST_BURST_MODE;
629 tegra_dsi_writel(dsi, DSI_SOL_DELAY_SOL_DELAY(sol_delay),
633 static void tegra_dsi_set_timeout(struct tegra_dc_dsi_data *dsi)
639 /* TODO: verify the following eq */
640 bytes_per_frame = dsi->current_dsi_clk_khz * 1000 * 2 /
641 (dsi->info.refresh_rate * 8);
642 timeout = bytes_per_frame / DSI_CYCLE_COUNTER_VALUE;
643 timeout = (timeout + DSI_HTX_TO_MARGIN) & 0xffff;
645 val = DSI_TIMEOUT_0_LRXH_TO(DSI_LRXH_TO_VALUE) |
646 DSI_TIMEOUT_0_HTX_TO(timeout);
647 tegra_dsi_writel(dsi, val, DSI_TIMEOUT_0);
649 if (dsi->info.panel_reset_timeout_msec)
650 timeout = (dsi->info.panel_reset_timeout_msec * 1000*1000)
651 / dsi->current_bit_clk_ns;
653 timeout = DSI_PR_TO_VALUE;
655 val = DSI_TIMEOUT_1_PR_TO(timeout) |
656 DSI_TIMEOUT_1_TA_TO(DSI_TA_TO_VALUE);
657 tegra_dsi_writel(dsi, val, DSI_TIMEOUT_1);
659 val = DSI_TO_TALLY_P_RESET_STATUS(IN_RESET) |
660 DSI_TO_TALLY_TA_TALLY(DSI_TA_TALLY_VALUE)|
661 DSI_TO_TALLY_LRXH_TALLY(DSI_LRXH_TALLY_VALUE)|
662 DSI_TO_TALLY_HTX_TALLY(DSI_HTX_TALLY_VALUE);
663 tegra_dsi_writel(dsi, val, DSI_TO_TALLY);
666 static void tegra_dsi_setup_video_mode_pkt_length(struct tegra_dc *dc,
667 struct tegra_dc_dsi_data *dsi)
675 hact_pkt_len = dc->mode.h_active * dsi->pixel_scaler_mul /
676 dsi->pixel_scaler_div;
677 hsa_pkt_len = dc->mode.h_sync_width * dsi->pixel_scaler_mul /
678 dsi->pixel_scaler_div;
679 hbp_pkt_len = dc->mode.h_back_porch * dsi->pixel_scaler_mul /
680 dsi->pixel_scaler_div;
681 hfp_pkt_len = dc->mode.h_front_porch * dsi->pixel_scaler_mul /
682 dsi->pixel_scaler_div;
684 if (dsi->info.video_burst_mode !=
685 TEGRA_DSI_VIDEO_NONE_BURST_MODE_WITH_SYNC_END)
686 hbp_pkt_len += hsa_pkt_len;
688 hsa_pkt_len -= DSI_HSYNC_BLNK_PKT_OVERHEAD;
689 hbp_pkt_len -= DSI_HBACK_PORCH_PKT_OVERHEAD;
690 hfp_pkt_len -= DSI_HFRONT_PORCH_PKT_OVERHEAD;
692 val = DSI_PKT_LEN_0_1_LENGTH_0(0) |
693 DSI_PKT_LEN_0_1_LENGTH_1(hsa_pkt_len);
694 tegra_dsi_writel(dsi, val, DSI_PKT_LEN_0_1);
696 val = DSI_PKT_LEN_2_3_LENGTH_2(hbp_pkt_len) |
697 DSI_PKT_LEN_2_3_LENGTH_3(hact_pkt_len);
698 tegra_dsi_writel(dsi, val, DSI_PKT_LEN_2_3);
700 val = DSI_PKT_LEN_4_5_LENGTH_4(hfp_pkt_len) |
701 DSI_PKT_LEN_4_5_LENGTH_5(0);
702 tegra_dsi_writel(dsi, val, DSI_PKT_LEN_4_5);
704 val = DSI_PKT_LEN_6_7_LENGTH_6(0) | DSI_PKT_LEN_6_7_LENGTH_7(0);
705 tegra_dsi_writel(dsi, val, DSI_PKT_LEN_6_7);
708 static void tegra_dsi_setup_cmd_mode_pkt_length(struct tegra_dc *dc,
709 struct tegra_dc_dsi_data *dsi)
712 unsigned long act_bytes;
714 act_bytes = dc->mode.h_active * dsi->pixel_scaler_mul /
715 dsi->pixel_scaler_div + 1;
717 val = DSI_PKT_LEN_0_1_LENGTH_0(0) | DSI_PKT_LEN_0_1_LENGTH_1(0);
718 tegra_dsi_writel(dsi, val, DSI_PKT_LEN_0_1);
720 val = DSI_PKT_LEN_2_3_LENGTH_2(0) | DSI_PKT_LEN_2_3_LENGTH_3(act_bytes);
721 tegra_dsi_writel(dsi, val, DSI_PKT_LEN_2_3);
723 val = DSI_PKT_LEN_4_5_LENGTH_4(0) | DSI_PKT_LEN_4_5_LENGTH_5(act_bytes);
724 tegra_dsi_writel(dsi, val, DSI_PKT_LEN_4_5);
726 val = DSI_PKT_LEN_6_7_LENGTH_6(0) | DSI_PKT_LEN_6_7_LENGTH_7(0x0f0f);
727 tegra_dsi_writel(dsi, val, DSI_PKT_LEN_6_7);
730 static void tegra_dsi_set_pkt_length(struct tegra_dc *dc,
731 struct tegra_dc_dsi_data *dsi)
733 if (dsi->driven_mode == TEGRA_DSI_DRIVEN_BY_HOST)
736 if (dsi->info.video_data_type == TEGRA_DSI_VIDEO_TYPE_VIDEO_MODE)
737 tegra_dsi_setup_video_mode_pkt_length(dc, dsi);
739 tegra_dsi_setup_cmd_mode_pkt_length(dc, dsi);
742 static void tegra_dsi_set_pkt_seq(struct tegra_dc *dc,
743 struct tegra_dc_dsi_data *dsi)
747 u32 pkt_seq_3_5_rgb_lo;
748 u32 pkt_seq_3_5_rgb_hi;
753 if (dsi->driven_mode == TEGRA_DSI_DRIVEN_BY_HOST)
756 switch (dsi->info.pixel_format) {
757 case TEGRA_DSI_PIXEL_FORMAT_16BIT_P:
758 rgb_info = CMD_RGB_16BPP;
760 case TEGRA_DSI_PIXEL_FORMAT_18BIT_P:
761 rgb_info = CMD_RGB_18BPP;
763 case TEGRA_DSI_PIXEL_FORMAT_18BIT_NP:
764 rgb_info = CMD_RGB_18BPPNP;
766 case TEGRA_DSI_PIXEL_FORMAT_24BIT_P:
768 rgb_info = CMD_RGB_24BPP;
772 pkt_seq_3_5_rgb_lo = 0;
773 pkt_seq_3_5_rgb_hi = 0;
774 if (dsi->info.video_data_type == TEGRA_DSI_VIDEO_TYPE_COMMAND_MODE)
775 pkt_seq = dsi_pkt_seq_cmd_mode;
777 switch (dsi->info.video_burst_mode) {
778 case TEGRA_DSI_VIDEO_BURST_MODE_LOWEST_SPEED:
779 case TEGRA_DSI_VIDEO_BURST_MODE_LOW_SPEED:
780 case TEGRA_DSI_VIDEO_BURST_MODE_MEDIUM_SPEED:
781 case TEGRA_DSI_VIDEO_BURST_MODE_FAST_SPEED:
782 case TEGRA_DSI_VIDEO_BURST_MODE_FASTEST_SPEED:
784 DSI_PKT_SEQ_3_LO_PKT_32_ID(rgb_info);
785 if (!dsi->info.no_pkt_seq_eot)
786 pkt_seq = dsi_pkt_seq_video_burst;
788 pkt_seq = dsi_pkt_seq_video_burst_no_eot;
790 case TEGRA_DSI_VIDEO_NONE_BURST_MODE_WITH_SYNC_END:
792 DSI_PKT_SEQ_3_HI_PKT_34_ID(rgb_info);
793 pkt_seq = dsi_pkt_seq_video_non_burst_syne;
795 case TEGRA_DSI_VIDEO_NONE_BURST_MODE:
798 DSI_PKT_SEQ_3_LO_PKT_32_ID(rgb_info);
799 pkt_seq = dsi_pkt_seq_video_non_burst;
804 for (i = 0; i < NUMOF_PKT_SEQ; i++) {
806 reg = dsi_pkt_seq_reg[i];
807 if ((reg == DSI_PKT_SEQ_3_LO) || (reg == DSI_PKT_SEQ_5_LO))
808 val |= pkt_seq_3_5_rgb_lo;
809 if ((reg == DSI_PKT_SEQ_3_HI) || (reg == DSI_PKT_SEQ_5_HI))
810 val |= pkt_seq_3_5_rgb_hi;
811 tegra_dsi_writel(dsi, val, reg);
815 static void tegra_dsi_stop_dc_stream(struct tegra_dc *dc,
816 struct tegra_dc_dsi_data *dsi)
818 tegra_dc_writel(dc, 0, DC_DISP_DISP_WIN_OPTIONS);
819 tegra_dc_writel(dc, GENERAL_ACT_REQ << 8, DC_CMD_STATE_CONTROL);
820 tegra_dc_writel(dc, GENERAL_ACT_REQ, DC_CMD_STATE_CONTROL);
822 dsi->status.dc_stream = DSI_DC_STREAM_DISABLE;
825 void tegra_dsi_stop_dc_stream_at_frame_end(struct tegra_dc *dc,
826 struct tegra_dc_dsi_data *dsi)
832 tegra_dsi_stop_dc_stream(dc, dsi);
834 /* enable vblank interrupt */
835 val = tegra_dc_readl(dc, DC_CMD_INT_ENABLE);
837 tegra_dc_writel(dc, val, DC_CMD_INT_ENABLE);
839 val = tegra_dc_readl(dc, DC_CMD_INT_MASK);
841 tegra_dc_writel(dc, val, DC_CMD_INT_MASK);
843 /* wait for vblank completion */
844 timeout = wait_for_completion_interruptible_timeout(
845 &dc->vblank_complete, DSI_STOP_DC_DURATION_MSEC);
847 /* disable vblank interrupt */
848 val = tegra_dc_readl(dc, DC_CMD_INT_ENABLE);
850 tegra_dc_writel(dc, val, DC_CMD_INT_ENABLE);
853 printk("Warning: dc dosen't stop at the end of the frame.\n");
856 static void tegra_dsi_start_dc_stream(struct tegra_dc *dc,
857 struct tegra_dc_dsi_data *dsi)
861 tegra_dc_writel(dc, DSI_ENABLE, DC_DISP_DISP_WIN_OPTIONS);
864 tegra_dc_writel(dc, PW0_ENABLE | PW1_ENABLE | PW2_ENABLE | PW3_ENABLE |
865 PW4_ENABLE | PM0_ENABLE | PM1_ENABLE,
866 DC_CMD_DISPLAY_POWER_CONTROL);
868 /* Configure one-shot mode or continuous mode */
869 if (dc->out->flags & TEGRA_DC_OUT_ONE_SHOT_MODE) {
870 /* disable LSPI/LCD_DE output */
871 val = PIN_OUTPUT_LSPI_OUTPUT_DIS;
872 tegra_dc_writel(dc, val, DC_COM_PIN_OUTPUT_ENABLE3);
874 /* enable MSF & set MSF polarity */
875 val = MSF_ENABLE | MSF_LSPI;
876 if (!dsi->info.te_polarity_low)
877 val |= MSF_POLARITY_HIGH;
879 val |= MSF_POLARITY_LOW;
880 tegra_dc_writel(dc, val, DC_CMD_DISPLAY_COMMAND_OPTION0);
882 /* set non-continuous mode */
883 tegra_dc_writel(dc, DISP_CTRL_MODE_NC_DISPLAY,
884 DC_CMD_DISPLAY_COMMAND);
885 tegra_dc_writel(dc, GENERAL_UPDATE, DC_CMD_STATE_CONTROL);
886 tegra_dc_writel(dc, GENERAL_ACT_REQ | NC_HOST_TRIG,
887 DC_CMD_STATE_CONTROL);
889 /* set continuous mode */
890 tegra_dc_writel(dc, DISP_CTRL_MODE_C_DISPLAY,
891 DC_CMD_DISPLAY_COMMAND);
892 tegra_dc_writel(dc, GENERAL_UPDATE, DC_CMD_STATE_CONTROL);
893 tegra_dc_writel(dc, GENERAL_ACT_REQ, DC_CMD_STATE_CONTROL);
896 dsi->status.dc_stream = DSI_DC_STREAM_ENABLE;
899 static void tegra_dsi_set_dc_clk(struct tegra_dc *dc,
900 struct tegra_dc_dsi_data *dsi)
902 u32 shift_clk_div_register;
905 /* Get the corresponding register value of shift_clk_div. */
906 shift_clk_div_register = dsi->shift_clk_div * 2 - 2;
908 #ifndef CONFIG_TEGRA_SILICON_PLATFORM
909 shift_clk_div_register = 1;
912 /* TODO: find out if PCD3 option is required */
913 val = PIXEL_CLK_DIVIDER_PCD1 |
914 SHIFT_CLK_DIVIDER(shift_clk_div_register);
915 tegra_dc_writel(dc, val, DC_DISP_DISP_CLOCK_CONTROL);
918 static void tegra_dsi_set_dsi_clk(struct tegra_dc *dc,
919 struct tegra_dc_dsi_data *dsi, u32 clk)
928 * Value for PLLD routine is required to be twice as
929 * the desired clock rate
932 dc->mode.pclk = clk*1000;
933 tegra_dc_setup_clk(dc, dsi->dsi_clk);
934 if (dsi->clk_ref == true)
935 clk_disable(dsi->dsi_clk);
938 clk_enable(dsi->dsi_clk);
939 tegra_periph_reset_deassert(dsi->dsi_clk);
941 dsi->current_dsi_clk_khz = clk_get_rate(dsi->dsi_clk) / 1000;
943 dsi->current_bit_clk_ns = 1000*1000 / (dsi->current_dsi_clk_khz * 2);
946 static void tegra_dsi_hs_clk_out_enable(struct tegra_dc_dsi_data *dsi)
950 val = tegra_dsi_readl(dsi, DSI_CONTROL);
951 val &= ~DSI_CONTROL_HS_CLK_CTRL(1);
953 if (dsi->info.video_clock_mode == TEGRA_DSI_VIDEO_CLOCK_CONTINUOUS) {
954 val |= DSI_CONTROL_HS_CLK_CTRL(CONTINUOUS);
955 dsi->status.clk_mode = DSI_PHYCLK_CONTINUOUS;
957 val |= DSI_CONTROL_HS_CLK_CTRL(TX_ONLY);
958 dsi->status.clk_mode = DSI_PHYCLK_TX_ONLY;
960 tegra_dsi_writel(dsi, val, DSI_CONTROL);
962 val = tegra_dsi_readl(dsi, DSI_HOST_DSI_CONTROL);
963 val &= ~DSI_HOST_DSI_CONTROL_HIGH_SPEED_TRANS(1);
964 val |= DSI_HOST_DSI_CONTROL_HIGH_SPEED_TRANS(TEGRA_DSI_HIGH);
965 tegra_dsi_writel(dsi, val, DSI_HOST_DSI_CONTROL);
967 dsi->status.clk_out = DSI_PHYCLK_OUT_EN;
970 static void tegra_dsi_hs_clk_out_enable_in_lp(struct tegra_dc_dsi_data *dsi)
973 tegra_dsi_hs_clk_out_enable(dsi);
975 val = tegra_dsi_readl(dsi, DSI_HOST_DSI_CONTROL);
976 val &= ~DSI_HOST_DSI_CONTROL_HIGH_SPEED_TRANS(1);
977 val |= DSI_HOST_DSI_CONTROL_HIGH_SPEED_TRANS(TEGRA_DSI_LOW);
978 tegra_dsi_writel(dsi, val, DSI_HOST_DSI_CONTROL);
981 static void tegra_dsi_hs_clk_out_disable(struct tegra_dc *dc,
982 struct tegra_dc_dsi_data *dsi)
986 if (dsi->status.dc_stream == DSI_DC_STREAM_ENABLE)
987 tegra_dsi_stop_dc_stream(dc, dsi);
989 val = tegra_dsi_readl(dsi, DSI_CONTROL);
990 val &= ~DSI_CONTROL_HS_CLK_CTRL(1);
991 val |= DSI_CONTROL_HS_CLK_CTRL(TX_ONLY);
992 tegra_dsi_writel(dsi, val, DSI_CONTROL);
994 /* TODO: issue a cmd */
996 val = tegra_dsi_readl(dsi, DSI_HOST_DSI_CONTROL);
997 val &= ~DSI_HOST_DSI_CONTROL_HIGH_SPEED_TRANS(1);
998 val |= DSI_HOST_DSI_CONTROL_HIGH_SPEED_TRANS(TEGRA_DSI_LOW);
999 tegra_dsi_writel(dsi, val, DSI_HOST_DSI_CONTROL);
1001 dsi->status.clk_mode = DSI_PHYCLK_NOT_INIT;
1002 dsi->status.clk_out = DSI_PHYCLK_OUT_DIS;
1005 static void tegra_dsi_set_control_reg_lp(struct tegra_dc_dsi_data *dsi)
1008 u32 host_dsi_control;
1011 dsi_control = dsi->dsi_control_val | DSI_CTRL_HOST_DRIVEN;
1012 host_dsi_control = HOST_DSI_CTRL_COMMON |
1013 HOST_DSI_CTRL_HOST_DRIVEN |
1014 DSI_HOST_DSI_CONTROL_HIGH_SPEED_TRANS(TEGRA_DSI_LOW);
1015 max_threshold = DSI_MAX_THRESHOLD_MAX_THRESHOLD(DSI_HOST_FIFO_DEPTH);
1017 tegra_dsi_writel(dsi, max_threshold, DSI_MAX_THRESHOLD);
1018 tegra_dsi_writel(dsi, dsi_control, DSI_CONTROL);
1019 tegra_dsi_writel(dsi, host_dsi_control, DSI_HOST_DSI_CONTROL);
1021 dsi->status.driven = DSI_DRIVEN_MODE_HOST;
1022 dsi->status.clk_burst = DSI_CLK_BURST_NOT_INIT;
1023 dsi->status.vtype = DSI_VIDEO_TYPE_NOT_INIT;
1026 static void tegra_dsi_set_control_reg_hs(struct tegra_dc_dsi_data *dsi)
1029 u32 host_dsi_control;
1033 dsi_control = dsi->dsi_control_val;
1034 host_dsi_control = HOST_DSI_CTRL_COMMON;
1038 if (dsi->driven_mode == TEGRA_DSI_DRIVEN_BY_HOST) {
1039 dsi_control |= DSI_CTRL_HOST_DRIVEN;
1040 host_dsi_control |= HOST_DSI_CTRL_HOST_DRIVEN;
1042 DSI_MAX_THRESHOLD_MAX_THRESHOLD(DSI_HOST_FIFO_DEPTH);
1043 dsi->status.driven = DSI_DRIVEN_MODE_HOST;
1045 dsi_control |= DSI_CTRL_DC_DRIVEN;
1046 host_dsi_control |= HOST_DSI_CTRL_DC_DRIVEN;
1048 DSI_MAX_THRESHOLD_MAX_THRESHOLD(DSI_VIDEO_FIFO_DEPTH);
1049 dsi->status.driven = DSI_DRIVEN_MODE_DC;
1052 if (dsi->info.video_data_type == TEGRA_DSI_VIDEO_TYPE_COMMAND_MODE) {
1053 dsi_control |= DSI_CTRL_CMD_MODE;
1054 host_dsi_control |= HOST_DSI_CTRL_CMD_MODE;
1055 dcs_cmd = DSI_DCS_CMDS_LT5_DCS_CMD(DSI_WRITE_MEMORY_START)|
1056 DSI_DCS_CMDS_LT3_DCS_CMD(DSI_WRITE_MEMORY_CONTINUE);
1057 dsi->status.vtype = DSI_VIDEO_TYPE_CMD_MODE;
1060 dsi_control |= DSI_CTRL_VIDEO_MODE;
1061 host_dsi_control |= HOST_DSI_CTRL_VIDEO_MODE;
1062 dsi->status.vtype = DSI_VIDEO_TYPE_VIDEO_MODE;
1065 tegra_dsi_writel(dsi, max_threshold, DSI_MAX_THRESHOLD);
1066 tegra_dsi_writel(dsi, dcs_cmd, DSI_DCS_CMDS);
1067 tegra_dsi_writel(dsi, dsi_control, DSI_CONTROL);
1068 tegra_dsi_writel(dsi, host_dsi_control, DSI_HOST_DSI_CONTROL);
1071 static int tegra_dsi_init_hw(struct tegra_dc *dc,
1072 struct tegra_dc_dsi_data *dsi)
1077 tegra_dsi_set_dsi_clk(dc, dsi, dsi->target_lp_clk_khz);
1078 if (dsi->info.dsi_instance) {
1079 /* TODO:Set the misc register*/
1082 /* TODO: only need to change the timing for bta */
1083 tegra_dsi_set_phy_timing(dsi);
1085 if (dsi->status.dc_stream == DSI_DC_STREAM_ENABLE)
1086 tegra_dsi_stop_dc_stream(dc, dsi);
1088 /* Initializing DSI registers */
1089 for (i = 0; i < ARRAY_SIZE(init_reg); i++)
1090 tegra_dsi_writel(dsi, 0, init_reg[i]);
1092 tegra_dsi_writel(dsi, dsi->dsi_control_val, DSI_CONTROL);
1093 /* Initialize DSI_PAD_CONTROL register. */
1094 val = DSI_PAD_CONTROL_PAD_LPUPADJ(0x1) |
1095 DSI_PAD_CONTROL_PAD_LPDNADJ(0x1) |
1096 DSI_PAD_CONTROL_PAD_PREEMP_EN(0x1) |
1097 DSI_PAD_CONTROL_PAD_SLEWDNADJ(0x6) |
1098 DSI_PAD_CONTROL_PAD_SLEWUPADJ(0x6);
1101 val |= DSI_PAD_CONTROL_PAD_PDIO(0) |
1102 DSI_PAD_CONTROL_PAD_PDIO_CLK(0) |
1103 DSI_PAD_CONTROL_PAD_PULLDN_ENAB(TEGRA_DSI_DISABLE);
1105 val |= DSI_PAD_CONTROL_PAD_PDIO(0x3) |
1106 DSI_PAD_CONTROL_PAD_PDIO_CLK(0x1) |
1107 DSI_PAD_CONTROL_PAD_PULLDN_ENAB(TEGRA_DSI_ENABLE);
1109 tegra_dsi_writel(dsi, val, DSI_PAD_CONTROL);
1111 val = DSI_POWER_CONTROL_LEG_DSI_ENABLE(TEGRA_DSI_ENABLE);
1112 tegra_dsi_writel(dsi, val, DSI_POWER_CONTROL);
1114 while (tegra_dsi_readl(dsi, DSI_POWER_CONTROL) != val)
1115 tegra_dsi_writel(dsi, val, DSI_POWER_CONTROL);
1117 dsi->status.init = DSI_MODULE_INIT;
1118 dsi->status.lphs = DSI_LPHS_NOT_INIT;
1119 dsi->status.vtype = DSI_VIDEO_TYPE_NOT_INIT;
1120 dsi->status.driven = DSI_DRIVEN_MODE_NOT_INIT;
1121 dsi->status.clk_out = DSI_PHYCLK_OUT_DIS;
1122 dsi->status.clk_mode = DSI_PHYCLK_NOT_INIT;
1123 dsi->status.clk_burst = DSI_CLK_BURST_NOT_INIT;
1124 dsi->status.dc_stream = DSI_DC_STREAM_DISABLE;
1129 static int tegra_dsi_set_to_lp_mode(struct tegra_dc *dc,
1130 struct tegra_dc_dsi_data *dsi)
1134 if (dsi->status.init != DSI_MODULE_INIT) {
1139 if (dsi->status.lphs == DSI_LPHS_IN_LP_MODE)
1142 if (dsi->status.dc_stream == DSI_DC_STREAM_ENABLE)
1143 tegra_dsi_stop_dc_stream_at_frame_end(dc, dsi);
1145 /* disable/enable hs clk according to enable_hs_clock_on_lp_cmd_mode */
1146 if ((dsi->status.clk_out == DSI_PHYCLK_OUT_EN) &&
1147 (!dsi->info.enable_hs_clock_on_lp_cmd_mode))
1148 tegra_dsi_hs_clk_out_disable(dc, dsi);
1150 if (dsi->current_dsi_clk_khz != dsi->target_lp_clk_khz) {
1151 tegra_dsi_set_dsi_clk(dc, dsi, dsi->target_lp_clk_khz);
1152 tegra_dsi_set_timeout(dsi);
1155 tegra_dsi_set_control_reg_lp(dsi);
1157 if ((dsi->status.clk_out == DSI_PHYCLK_OUT_DIS) &&
1158 (dsi->info.enable_hs_clock_on_lp_cmd_mode))
1159 tegra_dsi_hs_clk_out_enable_in_lp(dsi);
1162 dsi->status.lphs = DSI_LPHS_IN_LP_MODE;
1168 static int tegra_dsi_set_to_hs_mode(struct tegra_dc *dc,
1169 struct tegra_dc_dsi_data *dsi)
1173 if (dsi->status.init != DSI_MODULE_INIT) {
1178 if (dsi->status.dc_stream == DSI_DC_STREAM_ENABLE)
1179 tegra_dsi_stop_dc_stream_at_frame_end(dc, dsi);
1181 if ((dsi->status.clk_out == DSI_PHYCLK_OUT_EN) &&
1182 (!dsi->info.enable_hs_clock_on_lp_cmd_mode))
1183 tegra_dsi_hs_clk_out_disable(dc, dsi);
1185 if (dsi->current_dsi_clk_khz != dsi->target_hs_clk_khz) {
1186 tegra_dsi_set_dsi_clk(dc, dsi, dsi->target_hs_clk_khz);
1187 tegra_dsi_set_timeout(dsi);
1190 tegra_dsi_set_phy_timing(dsi);
1192 if (dsi->driven_mode == TEGRA_DSI_DRIVEN_BY_DC) {
1193 tegra_dsi_set_pkt_seq(dc, dsi);
1194 tegra_dsi_set_pkt_length(dc, dsi);
1195 tegra_dsi_set_sol_delay(dc, dsi);
1196 tegra_dsi_set_dc_clk(dc, dsi);
1199 tegra_dsi_set_control_reg_hs(dsi);
1201 if (dsi->status.clk_out == DSI_PHYCLK_OUT_DIS)
1202 tegra_dsi_hs_clk_out_enable(dsi);
1204 dsi->status.lphs = DSI_LPHS_IN_HS_MODE;
1210 static bool tegra_dsi_is_controller_idle(struct tegra_dc_dsi_data *dsi)
1216 while (timeout <= DSI_MAX_COMMAND_DELAY_USEC) {
1217 if (!tegra_dsi_readl(dsi, DSI_TRIGGER)) {
1221 udelay(DSI_COMMAND_DELAY_STEPS_USEC);
1222 timeout += DSI_COMMAND_DELAY_STEPS_USEC;
1228 static int tegra_dsi_host_trigger(struct tegra_dc_dsi_data *dsi)
1232 if (tegra_dsi_readl(dsi, DSI_TRIGGER)) {
1237 tegra_dsi_writel(dsi,
1238 DSI_TRIGGER_HOST_TRIGGER(TEGRA_DSI_ENABLE), DSI_TRIGGER);
1240 #if DSI_USE_SYNC_POINTS
1241 status = tegra_dsi_syncpt(dsi);
1243 printk(KERN_ERR "DSI syncpt for host trigger failed\n");
1247 if (!tegra_dsi_is_controller_idle(dsi))
1255 static int _tegra_dsi_write_data(struct tegra_dc_dsi_data *dsi,
1256 u8 *pdata, u8 data_id, u16 data_len)
1265 virtual_channel = dsi->info.virtual_channel <<
1266 DSI_VIR_CHANNEL_BIT_POSITION;
1268 /* always use hw for ecc */
1269 val = (virtual_channel | data_id) << 0 |
1271 tegra_dsi_writel(dsi, val, DSI_WR_DATA);
1273 /* if pdata != NULL, pkt type is long pkt */
1274 if (pdata != NULL) {
1276 if (data_len >= 4) {
1277 val = ((u32 *) pdata)[0];
1287 tegra_dsi_writel(dsi, val, DSI_WR_DATA);
1291 err = tegra_dsi_host_trigger(dsi);
1293 printk(KERN_ERR "DSI host trigger failed\n");
1298 int tegra_dsi_write_data(struct tegra_dc *dc,
1299 struct tegra_dc_dsi_data *dsi,
1300 u8 *pdata, u8 data_id, u16 data_len)
1302 bool switch_back_to_hs_mode;
1303 bool switch_back_to_dc_mode;
1307 switch_back_to_hs_mode = false;
1308 switch_back_to_dc_mode = false;
1310 if ((dsi->status.init != DSI_MODULE_INIT) ||
1311 (dsi->status.lphs == DSI_LPHS_NOT_INIT)) {
1316 if (!tegra_dsi_is_controller_idle(dsi)) {
1323 if (dsi->status.lphs == DSI_LPHS_IN_HS_MODE) {
1324 if (dsi->info.hs_cmd_mode_supported) {
1325 if (dsi->status.driven == DSI_DRIVEN_MODE_DC) {
1326 dsi->driven_mode = TEGRA_DSI_DRIVEN_BY_HOST;
1327 tegra_dsi_set_to_hs_mode(dc, dsi);
1328 switch_back_to_dc_mode = true;
1331 tegra_dsi_set_to_lp_mode(dc, dsi);
1332 switch_back_to_hs_mode = true;
1336 err = _tegra_dsi_write_data(dsi, pdata, data_id, data_len);
1339 if (switch_back_to_dc_mode)
1340 dsi->driven_mode = TEGRA_DSI_DRIVEN_BY_DC;
1341 if (switch_back_to_dc_mode || switch_back_to_hs_mode)
1342 tegra_dsi_set_to_hs_mode(dc, dsi);
1347 EXPORT_SYMBOL(tegra_dsi_write_data);
1349 static int tegra_dsi_send_panel_cmd(struct tegra_dc *dc,
1350 struct tegra_dc_dsi_data *dsi,
1351 struct tegra_dsi_cmd *cmd,
1358 for (i = 0; i < n_cmd; i++) {
1359 struct tegra_dsi_cmd *cur_cmd;
1362 if (cur_cmd->cmd_type == TEGRA_DSI_DELAY_MS)
1363 mdelay(cur_cmd->sp_len_dly.delay_ms);
1365 err = tegra_dsi_write_data(dc, dsi,
1368 cur_cmd->sp_len_dly.data_len);
1376 static int tegra_dsi_bta(struct tegra_dc_dsi_data *dsi)
1385 val = tegra_dsi_readl(dsi, DSI_HOST_DSI_CONTROL);
1386 val |= DSI_HOST_DSI_CONTROL_IMM_BTA(TEGRA_DSI_ENABLE);
1387 tegra_dsi_writel(dsi, val, DSI_HOST_DSI_CONTROL);
1389 #if DSI_USE_SYNC_POINTS
1390 /* FIXME: Workaround for nvhost_syncpt_read */
1391 dsi->syncpt_val = nvhost_syncpt_update_min(
1392 &dsi->dc->ndev->host->syncpt, dsi->syncpt_id);
1394 val = DSI_INCR_SYNCPT_COND(OP_DONE) |
1395 DSI_INCR_SYNCPT_INDX(dsi->syncpt_id);
1396 tegra_dsi_writel(dsi, val, DSI_INCR_SYNCPT);
1398 /* TODO: Use interrupt rather than polling */
1399 err = nvhost_syncpt_wait(&dsi->dc->ndev->host->syncpt,
1400 dsi->syncpt_id, dsi->syncpt_val + 1);
1402 printk(KERN_ERR "DSI sync point failure\n");
1404 (dsi->syncpt_val)++;
1406 while (poll_time < DSI_STATUS_POLLING_DURATION_USEC) {
1407 val = tegra_dsi_readl(dsi, DSI_HOST_DSI_CONTROL);
1408 val &= DSI_HOST_DSI_CONTROL_IMM_BTA(TEGRA_DSI_ENABLE);
1411 udelay(DSI_STATUS_POLLING_DELAY_USEC);
1412 poll_time += DSI_STATUS_POLLING_DELAY_USEC;
1414 if (poll_time > DSI_STATUS_POLLING_DURATION_USEC)
1421 static void tegra_dsi_read_fifo(struct tegra_dc *dc,
1422 struct tegra_dc_dsi_data *dsi,
1429 /* Read data from FIFO */
1430 for (i = 0; i < rd_fifo_cnt; i++) {
1431 val = tegra_dsi_readl(dsi, DSI_RD_DATA);
1432 printk(KERN_INFO "Read data[%d]: 0x%x\n", i, val);
1433 memcpy(read_fifo, &val, 4);
1437 /* Make sure all the data is read from the FIFO */
1438 val = tegra_dsi_readl(dsi, DSI_STATUS);
1439 val &= DSI_STATUS_RD_FIFO_COUNT(0x1f);
1441 dev_err(&dc->ndev->dev, "DSI FIFO_RD_CNT not zero"
1442 " even after reading FIFO_RD_CNT words from read fifo\n");
1445 static int tegra_dsi_parse_read_response(struct tegra_dc *dc,
1446 u32 rd_fifo_cnt, u8 *read_fifo)
1454 printk(KERN_INFO "escape sequence[0x%x]\n", read_fifo[0]);
1455 switch (read_fifo[4] & 0xff) {
1456 case GEN_LONG_RD_RES:
1458 case DCS_LONG_RD_RES:
1459 payload_size = (read_fifo[5] |
1460 (read_fifo[6] << 8)) & 0xFFFF;
1461 printk(KERN_INFO "Long read response Packet\n"
1462 "payload_size[0x%x]\n", payload_size);
1464 case GEN_1_BYTE_SHORT_RD_RES:
1466 case DCS_1_BYTE_SHORT_RD_RES:
1468 printk(KERN_INFO "Short read response Packet\n"
1469 "payload_size[0x%x]\n", payload_size);
1471 case GEN_2_BYTE_SHORT_RD_RES:
1473 case DCS_2_BYTE_SHORT_RD_RES:
1475 printk(KERN_INFO "Short read response Packet\n"
1476 "payload_size[0x%x]\n", payload_size);
1480 printk(KERN_INFO "Acknowledge error report response\n"
1481 "Packet payload_size[0x%x]\n", payload_size);
1484 /*reading from RD_FIFO_COUNT*/
1485 printk(KERN_INFO "Invalid read response payload_size\n");
1492 int tegra_dsi_read_data(struct tegra_dc *dc,
1493 struct tegra_dc_dsi_data *dsi,
1494 u32 max_ret_payload_size,
1495 u32 panel_reg_addr, u8 *read_data)
1501 bool switch_back_to_hs_mode;
1502 bool restart_dc_stream;
1503 bool switch_back_to_dc_mode;
1506 switch_back_to_hs_mode = false;
1507 restart_dc_stream = false;
1508 switch_back_to_dc_mode = false;
1510 if ((dsi->status.init != DSI_MODULE_INIT) ||
1511 (dsi->status.lphs == DSI_LPHS_NOT_INIT) ||
1512 (dsi->status.driven == DSI_DRIVEN_MODE_NOT_INIT)) {
1517 val = tegra_dsi_readl(dsi, DSI_STATUS);
1518 val &= DSI_STATUS_RD_FIFO_COUNT(0x1f);
1521 dev_err(&dc->ndev->dev, "DSI fifo count not zero\n");
1525 if (!tegra_dsi_is_controller_idle(dsi)) {
1527 dev_err(&dc->ndev->dev, "DSI trigger bit is already set\n");
1531 if (dsi->status.lphs == DSI_LPHS_IN_HS_MODE) {
1532 if (dsi->status.driven == DSI_DRIVEN_MODE_DC) {
1533 if (dsi->status.dc_stream == DSI_DC_STREAM_ENABLE)
1534 restart_dc_stream = true;
1535 dsi->driven_mode = TEGRA_DSI_DRIVEN_BY_HOST;
1536 switch_back_to_dc_mode = true;
1537 if (dsi->info.hs_cmd_mode_supported) {
1538 err = tegra_dsi_set_to_hs_mode(dc, dsi);
1540 dev_err(&dc->ndev->dev,
1541 "DSI failed to go to HS mode host driven\n");
1546 if (!dsi->info.hs_cmd_mode_supported) {
1547 err = tegra_dsi_set_to_lp_mode(dc, dsi);
1549 dev_err(&dc->ndev->dev,
1550 "DSI failed to go to LP mode\n");
1553 switch_back_to_hs_mode = true;
1557 /* Set max return payload size in words */
1558 err = _tegra_dsi_write_data(dsi, NULL,
1559 dsi_command_max_return_pkt_size,
1560 max_ret_payload_size);
1562 dev_err(&dc->ndev->dev,
1563 "DSI write failed\n");
1567 /* DCS to read given panel register */
1568 err = _tegra_dsi_write_data(dsi, NULL,
1569 dsi_command_dcs_read_with_no_params,
1572 dev_err(&dc->ndev->dev,
1573 "DSI write failed\n");
1577 err = tegra_dsi_bta(dsi);
1579 dev_err(&dc->ndev->dev,
1580 "DSI IMM BTA timeout\n");
1585 while (poll_time < DSI_DELAY_FOR_READ_FIFO) {
1587 val = tegra_dsi_readl(dsi, DSI_STATUS);
1588 rd_fifo_cnt = val & DSI_STATUS_RD_FIFO_COUNT(0x1f);
1589 if (rd_fifo_cnt << 2 > DSI_READ_FIFO_DEPTH)
1590 dev_err(&dc->ndev->dev,
1591 "DSI RD_FIFO_CNT is greater than RD_FIFO_DEPTH\n");
1596 if (rd_fifo_cnt == 0) {
1597 dev_info(&dc->ndev->dev,
1598 "DSI RD_FIFO_CNT is zero\n");
1603 if (val & DSI_STATUS_LB_UNDERFLOW(0x1) ||
1604 val & DSI_STATUS_LB_OVERFLOW(0x1)) {
1605 dev_err(&dc->ndev->dev,
1606 "DSI overflow/underflow error\n");
1611 tegra_dsi_read_fifo(dc, dsi, rd_fifo_cnt, read_data);
1613 err = tegra_dsi_parse_read_response(dc, rd_fifo_cnt, read_data);
1615 if (switch_back_to_dc_mode)
1616 dsi->driven_mode = TEGRA_DSI_DRIVEN_BY_DC;
1617 if (switch_back_to_dc_mode || switch_back_to_hs_mode)
1618 tegra_dsi_set_to_hs_mode(dc, dsi);
1619 if (restart_dc_stream)
1620 tegra_dsi_start_dc_stream(dc, dsi);
1624 EXPORT_SYMBOL(tegra_dsi_read_data);
1626 static int tegra_dsi_enter_ulpm(struct tegra_dc_dsi_data *dsi)
1633 val = tegra_dsi_readl(dsi, DSI_HOST_DSI_CONTROL);
1634 val &= ~DSI_HOST_DSI_CONTROL_ULTRA_LOW_POWER(3);
1635 val |= DSI_HOST_DSI_CONTROL_ULTRA_LOW_POWER(ENTER_ULPM);
1636 tegra_dsi_writel(dsi, val, DSI_HOST_DSI_CONTROL);
1638 #if DSI_USE_SYNC_POINTS
1639 ret = tegra_dsi_syncpt(dsi);
1641 printk(KERN_ERR "DSI syncpt for ulpm enter failed\n");
1645 /* TODO: Find exact delay required */
1653 static int tegra_dsi_exit_ulpm(struct tegra_dc_dsi_data *dsi)
1660 val = tegra_dsi_readl(dsi, DSI_HOST_DSI_CONTROL);
1661 val &= ~DSI_HOST_DSI_CONTROL_ULTRA_LOW_POWER(3);
1662 val |= DSI_HOST_DSI_CONTROL_ULTRA_LOW_POWER(EXIT_ULPM);
1663 tegra_dsi_writel(dsi, val, DSI_HOST_DSI_CONTROL);
1665 #if DSI_USE_SYNC_POINTS
1666 ret = tegra_dsi_syncpt(dsi);
1668 printk(KERN_ERR "DSI syncpt for ulpm exit failed\n");
1672 /* TODO: Find exact delay required */
1677 val = tegra_dsi_readl(dsi, DSI_HOST_DSI_CONTROL);
1678 val &= ~DSI_HOST_DSI_CONTROL_ULTRA_LOW_POWER(0x3);
1679 val |= DSI_HOST_DSI_CONTROL_ULTRA_LOW_POWER(NORMAL);
1680 tegra_dsi_writel(dsi, val, DSI_HOST_DSI_CONTROL);
1686 static void tegra_dc_dsi_enable(struct tegra_dc *dc)
1688 struct tegra_dc_dsi_data *dsi = tegra_dc_get_outdata(dc);
1692 tegra_dc_io_start(dc);
1693 mutex_lock(&dsi->lock);
1695 /* Stop DC stream before configuring DSI registers
1696 * to avoid visible glitches on panel during transition
1697 * from bootloader to kernel driver
1699 tegra_dsi_stop_dc_stream_at_frame_end(dc, dsi);
1703 if (tegra_dsi_exit_ulpm(dsi) < 0) {
1704 printk(KERN_ERR "DSI failed to exit ulpm\n");
1709 if (dsi->info.panel_reset) {
1710 err = tegra_dsi_send_panel_cmd(dc, dsi,
1711 dsi->info.dsi_init_cmd,
1712 dsi->info.n_init_cmd);
1714 dev_err(&dc->ndev->dev,
1715 "dsi: error sending dsi init cmd\n");
1718 } else if (dsi->info.dsi_late_resume_cmd) {
1719 err = tegra_dsi_send_panel_cmd(dc, dsi,
1720 dsi->info.dsi_late_resume_cmd,
1721 dsi->info.n_late_resume_cmd);
1723 dev_err(&dc->ndev->dev,
1724 "dsi: error sending late resume cmd\n");
1729 err = tegra_dsi_init_hw(dc, dsi);
1731 dev_err(&dc->ndev->dev,
1732 "dsi: not able to init dsi hardware\n");
1737 if (tegra_dsi_enter_ulpm(dsi) < 0) {
1738 printk(KERN_ERR "DSI failed to enter ulpm\n");
1741 val = DSI_PAD_CONTROL_PAD_PDIO(0) |
1742 DSI_PAD_CONTROL_PAD_PDIO_CLK(0) |
1743 DSI_PAD_CONTROL_PAD_PULLDN_ENAB(TEGRA_DSI_DISABLE);
1744 tegra_dsi_writel(dsi, val, DSI_PAD_CONTROL);
1745 if (tegra_dsi_exit_ulpm(dsi) < 0) {
1746 printk(KERN_ERR "DSI failed to exit ulpm\n");
1751 err = tegra_dsi_set_to_lp_mode(dc, dsi);
1753 dev_err(&dc->ndev->dev,
1754 "dsi: not able to set to lp mode\n");
1758 err = tegra_dsi_send_panel_cmd(dc, dsi, dsi->info.dsi_init_cmd,
1759 dsi->info.n_init_cmd);
1761 dev_err(&dc->ndev->dev,
1762 "dsi: error while sending dsi init cmd\n");
1766 err = tegra_dsi_set_to_hs_mode(dc, dsi);
1768 dev_err(&dc->ndev->dev,
1769 "dsi: not able to set to hs mode\n");
1773 dsi->enabled = true;
1776 if (dsi->status.driven == DSI_DRIVEN_MODE_DC)
1777 tegra_dsi_start_dc_stream(dc, dsi);
1779 mutex_unlock(&dsi->lock);
1780 tegra_dc_io_end(dc);
1783 static void _tegra_dc_dsi_init(struct tegra_dc *dc)
1785 struct tegra_dc_dsi_data *dsi = tegra_dc_get_outdata(dc);
1787 tegra_dsi_init_sw(dc, dsi);
1788 /* TODO: Configure the CSI pad configuration */
1791 static int tegra_dc_dsi_cp_p_cmd(struct tegra_dsi_cmd *src,
1792 struct tegra_dsi_cmd *dst, u16 n_cmd)
1797 memcpy(dst, src, sizeof(*dst) * n_cmd);
1799 for (i = 0; i < n_cmd; i++)
1801 len = sizeof(*src[i].pdata) *
1802 src[i].sp_len_dly.data_len;
1803 dst[i].pdata = kzalloc(len, GFP_KERNEL);
1805 goto free_cmd_pdata;
1806 memcpy(dst[i].pdata, src[i].pdata, len);
1812 for (--i; i >= 0; i--)
1814 kfree(dst[i].pdata);
1818 static int tegra_dc_dsi_cp_info(struct tegra_dc_dsi_data *dsi,
1819 struct tegra_dsi_out *p_dsi)
1821 struct tegra_dsi_cmd *p_init_cmd;
1822 struct tegra_dsi_cmd *p_early_suspend_cmd;
1823 struct tegra_dsi_cmd *p_late_resume_cmd;
1824 struct tegra_dsi_cmd *p_suspend_cmd;
1827 if (p_dsi->n_data_lanes > MAX_DSI_DATA_LANES)
1830 p_init_cmd = kzalloc(sizeof(*p_init_cmd) *
1831 p_dsi->n_init_cmd, GFP_KERNEL);
1835 if (p_dsi->dsi_early_suspend_cmd) {
1836 p_early_suspend_cmd = kzalloc(sizeof(*p_early_suspend_cmd) *
1837 p_dsi->n_early_suspend_cmd,
1839 if (!p_early_suspend_cmd) {
1841 goto err_free_init_cmd;
1845 if (p_dsi->dsi_late_resume_cmd) {
1846 p_late_resume_cmd = kzalloc(sizeof(*p_late_resume_cmd) *
1847 p_dsi->n_late_resume_cmd,
1849 if (!p_late_resume_cmd) {
1851 goto err_free_p_early_suspend_cmd;
1855 p_suspend_cmd = kzalloc(sizeof(*p_suspend_cmd) * p_dsi->n_suspend_cmd,
1857 if (!p_suspend_cmd) {
1859 goto err_free_p_late_resume_cmd;
1862 memcpy(&dsi->info, p_dsi, sizeof(dsi->info));
1864 /* Copy panel init cmd */
1865 err = tegra_dc_dsi_cp_p_cmd(p_dsi->dsi_init_cmd,
1866 p_init_cmd, p_dsi->n_init_cmd);
1869 dsi->info.dsi_init_cmd = p_init_cmd;
1871 /* Copy panel early suspend cmd */
1872 if (p_dsi->dsi_early_suspend_cmd) {
1873 err = tegra_dc_dsi_cp_p_cmd(p_dsi->dsi_early_suspend_cmd,
1874 p_early_suspend_cmd,
1875 p_dsi->n_early_suspend_cmd);
1878 dsi->info.dsi_early_suspend_cmd = p_early_suspend_cmd;
1881 /* Copy panel late resume cmd */
1882 if (p_dsi->dsi_late_resume_cmd) {
1883 err = tegra_dc_dsi_cp_p_cmd(p_dsi->dsi_late_resume_cmd,
1885 p_dsi->n_late_resume_cmd);
1888 dsi->info.dsi_late_resume_cmd = p_late_resume_cmd;
1891 /* Copy panel suspend cmd */
1892 err = tegra_dc_dsi_cp_p_cmd(p_dsi->dsi_suspend_cmd, p_suspend_cmd,
1893 p_dsi->n_suspend_cmd);
1896 dsi->info.dsi_suspend_cmd = p_suspend_cmd;
1898 if (!dsi->info.panel_reset_timeout_msec)
1899 dsi->info.panel_reset_timeout_msec =
1900 DEFAULT_PANEL_RESET_TIMEOUT;
1902 if (!dsi->info.panel_buffer_size_byte)
1903 dsi->info.panel_buffer_size_byte = DEFAULT_PANEL_BUFFER_BYTE;
1905 if (!dsi->info.max_panel_freq_khz) {
1906 dsi->info.max_panel_freq_khz = DEFAULT_MAX_DSI_PHY_CLK_KHZ;
1908 if (dsi->info.video_burst_mode >
1909 TEGRA_DSI_VIDEO_NONE_BURST_MODE_WITH_SYNC_END){
1910 dev_err(&dsi->dc->ndev->dev, "DSI: max_panel_freq_khz"
1911 "is not set for DSI burst mode.\n");
1912 dsi->info.video_burst_mode =
1913 TEGRA_DSI_VIDEO_BURST_MODE_LOWEST_SPEED;
1917 if (!dsi->info.lp_cmd_mode_freq_khz)
1918 dsi->info.lp_cmd_mode_freq_khz = DEFAULT_LP_CMD_MODE_CLK_KHZ;
1920 if (!dsi->info.chip_id || !dsi->info.chip_rev)
1921 printk(KERN_WARNING "DSI: Failed to get chip info\n");
1923 /* host mode is for testing only*/
1924 dsi->driven_mode = TEGRA_DSI_DRIVEN_BY_DC;
1928 kfree(p_suspend_cmd);
1929 err_free_p_late_resume_cmd:
1930 kfree(p_late_resume_cmd);
1931 err_free_p_early_suspend_cmd:
1932 kfree(p_early_suspend_cmd);
1938 static int tegra_dc_dsi_init(struct tegra_dc *dc)
1940 struct tegra_dc_dsi_data *dsi;
1941 struct resource *res;
1942 struct resource *base_res;
1944 struct clk *dc_clk = NULL;
1945 struct clk *dsi_clk = NULL;
1946 struct tegra_dsi_out *dsi_pdata;
1951 dsi = kzalloc(sizeof(*dsi), GFP_KERNEL);
1955 res = nvhost_get_resource_byname(dc->ndev, IORESOURCE_MEM,
1958 dev_err(&dc->ndev->dev, "dsi: no mem resource\n");
1963 base_res = request_mem_region(res->start, resource_size(res),
1966 dev_err(&dc->ndev->dev, "dsi: request_mem_region failed\n");
1971 base = ioremap(res->start, resource_size(res));
1973 dev_err(&dc->ndev->dev, "dsi: registers can't be mapped\n");
1975 goto err_release_regs;
1978 dsi_pdata = dc->pdata->default_out->dsi;
1980 dev_err(&dc->ndev->dev, "dsi: dsi data not available\n");
1981 goto err_release_regs;
1984 if (dsi_pdata->dsi_instance)
1985 dsi_clk = clk_get(&dc->ndev->dev, "dsib");
1987 dsi_clk = clk_get(&dc->ndev->dev, "dsia");
1989 if (IS_ERR_OR_NULL(dsi_clk)) {
1990 dev_err(&dc->ndev->dev, "dsi: can't get clock\n");
1992 goto err_release_regs;
1995 dc_clk = clk_get_sys(dev_name(&dc->ndev->dev), NULL);
1996 if (IS_ERR_OR_NULL(dc_clk)) {
1997 dev_err(&dc->ndev->dev, "dsi: dc clock %s unavailable\n",
1998 dev_name(&dc->ndev->dev));
2003 mutex_init(&dsi->lock);
2006 dsi->base_res = base_res;
2007 dsi->dc_clk = dc_clk;
2008 dsi->dsi_clk = dsi_clk;
2010 err = tegra_dc_dsi_cp_info(dsi, dsi_pdata);
2014 tegra_dc_set_outdata(dc, dsi);
2015 _tegra_dc_dsi_init(dc);
2023 release_resource(base_res);
2030 static void tegra_dc_dsi_destroy(struct tegra_dc *dc)
2032 struct tegra_dc_dsi_data *dsi = tegra_dc_get_outdata(dc);
2036 mutex_lock(&dsi->lock);
2038 /* free up the pdata*/
2039 for (i = 0; i < dsi->info.n_init_cmd; i++) {
2040 if (dsi->info.dsi_init_cmd[i].pdata)
2041 kfree(dsi->info.dsi_init_cmd[i].pdata);
2043 kfree(dsi->info.dsi_init_cmd);
2045 /* Disable dc stream*/
2046 if (dsi->status.dc_stream == DSI_DC_STREAM_ENABLE)
2047 tegra_dsi_stop_dc_stream(dc, dsi);
2049 /* Disable dsi phy clock*/
2050 if (dsi->status.clk_out == DSI_PHYCLK_OUT_EN)
2051 tegra_dsi_hs_clk_out_disable(dc, dsi);
2053 val = DSI_POWER_CONTROL_LEG_DSI_ENABLE(TEGRA_DSI_DISABLE);
2054 tegra_dsi_writel(dsi, val, DSI_POWER_CONTROL);
2057 release_resource(dsi->base_res);
2059 clk_put(dsi->dc_clk);
2060 clk_put(dsi->dsi_clk);
2062 mutex_unlock(&dsi->lock);
2064 mutex_destroy(&dsi->lock);
2068 static void tegra_dc_dsi_disable(struct tegra_dc *dc)
2072 struct clk *base_clk;
2073 struct tegra_dc_dsi_data *dsi = tegra_dc_get_outdata(dc);
2075 tegra_dc_io_start(dc);
2076 mutex_lock(&dsi->lock);
2078 if (dsi->status.dc_stream == DSI_DC_STREAM_ENABLE)
2079 tegra_dsi_stop_dc_stream_at_frame_end(dc, dsi);
2081 if (dsi->info.power_saving_suspend) {
2085 err = tegra_dsi_set_to_lp_mode(dc, dsi);
2087 dev_err(&dc->ndev->dev,
2088 "DSI failed to go to LP mode\n");
2092 err = tegra_dsi_send_panel_cmd(dc, dsi,
2093 dsi->info.dsi_suspend_cmd,
2094 dsi->info.n_suspend_cmd);
2096 dev_err(&dc->ndev->dev,
2097 "dsi: Error sending suspend cmd\n");
2102 if (tegra_dsi_enter_ulpm(dsi) < 0)
2103 printk(KERN_ERR "DSI failed to enter ulpm\n");
2107 val = tegra_dsi_readl(dsi, DSI_PAD_CONTROL);
2108 val = DSI_PAD_CONTROL_PAD_PDIO(0x3) |
2109 DSI_PAD_CONTROL_PAD_PDIO_CLK(0x1) |
2110 DSI_PAD_CONTROL_PAD_PULLDN_ENAB(TEGRA_DSI_ENABLE);
2111 tegra_dsi_writel(dsi, val, DSI_PAD_CONTROL);
2113 /* Suspend core-logic */
2114 val = DSI_POWER_CONTROL_LEG_DSI_ENABLE(TEGRA_DSI_DISABLE);
2115 tegra_dsi_writel(dsi, val, DSI_POWER_CONTROL);
2117 /* Disable phy clock */
2118 base_clk = clk_get_parent(dsi->dsi_clk);
2119 if (dsi->info.dsi_instance)
2120 tegra_clk_cfg_ex(base_clk,
2121 TEGRA_CLK_PLLD_CSI_OUT_ENB,
2124 tegra_clk_cfg_ex(base_clk,
2125 TEGRA_CLK_PLLD_DSI_OUT_ENB,
2128 /* Disable DSI source clock */
2129 clk_disable(dsi->dsi_clk);
2130 dsi->clk_ref = false;
2131 dsi->enabled = false;
2133 if (dsi->info.dsi_early_suspend_cmd) {
2134 err = tegra_dsi_send_panel_cmd(dc, dsi,
2135 dsi->info.dsi_early_suspend_cmd,
2136 dsi->info.n_early_suspend_cmd);
2138 dev_err(&dc->ndev->dev,
2139 "dsi: Error sending early suspend cmd\n");
2145 if (tegra_dsi_enter_ulpm(dsi) < 0)
2146 printk(KERN_ERR "DSI failed to enter ulpm\n");
2151 mutex_unlock(&dsi->lock);
2152 tegra_dc_io_end(dc);
2156 static void tegra_dc_dsi_suspend(struct tegra_dc *dc)
2158 struct tegra_dc_dsi_data *dsi;
2162 dsi = tegra_dc_get_outdata(dc);
2164 tegra_dc_io_start(dc);
2165 mutex_lock(&dsi->lock);
2170 if (!dsi->info.power_saving_suspend) {
2172 if (tegra_dsi_exit_ulpm(dsi) < 0) {
2173 printk(KERN_ERR "DSI failed to exit ulpm");
2179 err = tegra_dsi_send_panel_cmd(dc, dsi,
2180 dsi->info.dsi_suspend_cmd,
2181 dsi->info.n_suspend_cmd);
2183 dev_err(&dc->ndev->dev,
2184 "dsi: Error sending suspend cmd\n");
2188 if (tegra_dsi_enter_ulpm(dsi) < 0) {
2189 printk(KERN_ERR "DSI failed to enter ulpm\n");
2195 val = tegra_dsi_readl(dsi, DSI_PAD_CONTROL);
2196 val = DSI_PAD_CONTROL_PAD_PDIO(0x3) |
2197 DSI_PAD_CONTROL_PAD_PDIO_CLK(0x1) |
2198 DSI_PAD_CONTROL_PAD_PULLDN_ENAB(TEGRA_DSI_ENABLE);
2199 tegra_dsi_writel(dsi, val, DSI_PAD_CONTROL);
2201 /* Suspend core-logic */
2202 val = DSI_POWER_CONTROL_LEG_DSI_ENABLE(TEGRA_DSI_DISABLE);
2203 tegra_dsi_writel(dsi, val, DSI_POWER_CONTROL);
2205 dsi->enabled = false;
2207 clk_disable(dsi->dsi_clk);
2208 dsi->clk_ref = false;
2211 mutex_unlock(&dsi->lock);
2212 tegra_dc_io_end(dc);
2215 static void tegra_dc_dsi_resume(struct tegra_dc *dc)
2217 /* Not required since tegra_dc_dsi_enable
2218 * will reconfigure the controller from scratch
2223 struct tegra_dc_out_ops tegra_dc_dsi_ops = {
2224 .init = tegra_dc_dsi_init,
2225 .destroy = tegra_dc_dsi_destroy,
2226 .enable = tegra_dc_dsi_enable,
2227 .disable = tegra_dc_dsi_disable,
2229 .suspend = tegra_dc_dsi_suspend,
2230 .resume = tegra_dc_dsi_resume,